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authorYaochenger <[email protected]>2025-05-29 11:30:04 +0800
committerRbb666 <[email protected]>2025-05-30 09:32:08 +0800
commit5889db68191a563bc0d8d2439a0e38e6bf9b4ecc (patch)
treebab000e41e1cc1f08fb24c2aa53d531bace5e548
parent898b9f1ff8c40d47b59f61fde31c877224b44ab5 (diff)
[libcpu/common] 修正对RV32E的支持,RV32E不支持s2寄存器,修改为s1寄存器
-rw-r--r--libcpu/risc-v/common/interrupt_gcc.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/libcpu/risc-v/common/interrupt_gcc.S b/libcpu/risc-v/common/interrupt_gcc.S
index fc916dd821..6eb0ef371f 100644
--- a/libcpu/risc-v/common/interrupt_gcc.S
+++ b/libcpu/risc-v/common/interrupt_gcc.S
@@ -337,8 +337,8 @@ trap_entry:
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
- lw s2, 0(s0)
- beqz s2, spurious_interrupt
+ lw s1, 0(s0)
+ beqz s1, spurious_interrupt
sw zero, 0(s0)
la s0, rt_interrupt_from_thread