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authorYonggang Luo <[email protected]>2025-10-11 09:28:52 +0800
committerGitHub <[email protected]>2025-10-11 09:28:52 +0800
commit5ae232b6d0752ab823b5d0a52ef0aa269fdb3aed (patch)
tree5ca94ab6a3b945cc9b6694ce8daf6fd5caa1710e
parentba795c6d6543aca68cc2fb34ff9cf6a5e07190ad (diff)
bsp/w60x: fixes cppcheck: (#10781)
[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError] [cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]
-rw-r--r--bsp/w60x/drivers/drv_rtc.c4
-rw-r--r--libcpu/arm/s3c24x0/rtc.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/bsp/w60x/drivers/drv_rtc.c b/bsp/w60x/drivers/drv_rtc.c
index 13fc00ea99..392bb950f3 100644
--- a/bsp/w60x/drivers/drv_rtc.c
+++ b/bsp/w60x/drivers/drv_rtc.c
@@ -55,7 +55,7 @@ static int wm_set_timestamp(time_t timestamp)
gmtime_r(&timestamp, &tblock);
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* disable */
- ctrl2 &= ~(1 << 16);
+ ctrl2 &= ~(BIT(16));
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl1 |= tblock.tm_sec;
@@ -70,7 +70,7 @@ static int wm_set_timestamp(time_t timestamp)
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2);/* enable */
- ctrl2 |= (1 << 16);
+ ctrl2 |= BIT(16);
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
return RT_EOK;
diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c
index 60703f9d94..2dda7b0334 100644
--- a/libcpu/arm/s3c24x0/rtc.c
+++ b/libcpu/arm/s3c24x0/rtc.c
@@ -31,7 +31,7 @@ void rt_hw_rtc_get(struct tm *ti)
rt_uint8_t sec, min, hour, mday, wday, mon, year;
/* enable access to RTC registers */
- RTCCON |= RTC_ENABLE;
+ RTC_ENABLE;
/* read RTC registers */
do