diff options
| author | Kevin Peng <[email protected]> | 2019-10-28 14:35:50 +0800 |
|---|---|---|
| committer | Karl Zhang <[email protected]> | 2020-01-03 15:51:24 +0800 |
| commit | 5f4b780558366ed7fd72e08bdfada6243252d2fc (patch) | |
| tree | 3ed01a856e36e928feeb561e5f01c348b2dffc99 | |
| parent | 8d0ca47526d23e8191139b304b6050c5eacf7401 (diff) | |
LPC55S69: Integration with TF-M
This patch enables TF-M running on secure side and RT-Thread running on
NS side by:
1. Updates the VTOR address
2. Remove a HW initialization which is already done in TF-M
3. Add a new project and linker script to build RTT in NS
Note:
There are no secure service calls to TF-M in this patch
Change-Id: I4023a082cfb5c8df8a4f0ecc7ffee850daaadeb4
Signed-off-by: Kevin Peng <[email protected]>
Signed-off-by: Karl Zhang <[email protected]>
4 files changed, 3089 insertions, 0 deletions
diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c index 4a7fb3f885..22e663b1f4 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +11,7 @@ * 2010-05-02 Aozima update CMSIS to 130 * 2017-08-02 XiaoYang porting to LPC54608 bsp * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + * 2020-01-01 Karl Add RT_USING_TFM support */ #include <rthw.h> @@ -56,11 +58,20 @@ void rt_hw_board_init() /* Set the Vector Table base location at 0x10000000 */ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); #else /* VECT_TAB_FLASH */ + +#ifdef RT_USING_TFM + /* Set the Vector Table base location at 0x00020000 when RTT with TF-M*/ + SCB->VTOR = (0x00020000 & NVIC_VTOR_MASK); +#else /* Set the Vector Table base location at 0x00000000 */ SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif +#endif +#ifndef RT_USING_TFM + /* This init has finished in secure side of TF-M */ BOARD_BootClockPLL150M(); +#endif //BOARD_BootClockFROHF96M(); /* init systick 1 systick = 1/(100M / 100) 100��systick = 1s*/ diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf new file mode 100644 index 0000000000..bb14890505 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf @@ -0,0 +1,110 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +/* + * Original code taken from RTT project at: + * https://github.com/RT-Thread/rt-thread + * File: bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf + * Git SHA of the original version: 64945ba882d651a14933eb4e7b3d93d10d6daae1 + */ + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x1000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x00071E00 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20000000 + #define m_data_size 0x00031800 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20000000 + #define m_data_size 0x00033000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx new file mode 100644 index 0000000000..7f28d506da --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx @@ -0,0 +1,1811 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + 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Software</Header> + + <Targets> + <Target> + <TargetName>rtthread-lpc55s6x</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pArmCC>6120000::V6.12::.\ARMCLANG</pArmCC> + <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed> + <uAC6>1</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>LPC55S69JBD100:cm33_core0</Device> + <Vendor>NXP</Vendor> + <PackID>NXP.LPC55S69_DFP.12.0.0</PackID> + <PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL> + <Cpu>IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:LPC55S69JBD100$fsl_device_registers.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\</OutputDirectory> + <OutputName>rtthread-lpc55s6x</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + 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+ <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x44000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x4000000</StartAddress> + <Size>0x8000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>3</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls>--target=arm-arm-none-eabi</MiscControls> + <Define>CPU_LPC55S69JBD100_cm33_core0, RT_USING_ARM_LIBC, RT_USING_TFM</Define> + <Undefine></Undefine> + <IncludePath>.;..\..\..\include;applications;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + 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