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authorbernard.xiong <[email protected]>2009-09-28 00:00:23 +0000
committerbernard.xiong <[email protected]>2009-09-28 00:00:23 +0000
commit6a26038b1669eb29cda1c5213eb76205dd90d20e (patch)
treef1a80130d4e441d581e5767b1675944b05d4ab56
parent60e88011e8f0411c54e94f857ac6a53ce4d20d65 (diff)
modify for STM32 FW library 3.1.0.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@52 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat
-rw-r--r--libcpu/arm/stm32/context_iar.S85
-rw-r--r--libcpu/arm/stm32/fault_iar.S34
-rw-r--r--libcpu/arm/stm32/fault_rvds.S26
-rw-r--r--libcpu/arm/stm32/serial.c1173
-rw-r--r--libcpu/arm/stm32/serial.h2
-rw-r--r--libcpu/arm/stm32/start_iar.c176
-rw-r--r--libcpu/arm/stm32/start_iar.s435
-rw-r--r--libcpu/arm/stm32/start_rvds.s223
8 files changed, 1224 insertions, 930 deletions
diff --git a/libcpu/arm/stm32/context_iar.S b/libcpu/arm/stm32/context_iar.S
index d20cdf9dd4..f62d3c36dd 100644
--- a/libcpu/arm/stm32/context_iar.S
+++ b/libcpu/arm/stm32/context_iar.S
@@ -10,6 +10,7 @@
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
+; * 2009-09-27 Bernard add protect when contex switch occurs
; */
;/**
@@ -53,18 +54,28 @@ rt_hw_interrupt_enable:
; * r0 --> from
; * r1 --> to
; */
+ EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
rt_hw_context_switch:
- LDR r2, =rt_interrupt_from_thread
- STR r0, [r2]
-
- LDR r2, =rt_interrupt_to_thread
- STR r1, [r2]
+ ; set rt_thread_switch_interrput_flag to 1
+ LDR r2, =rt_thread_switch_interrput_flag
+ LDR r3, [r2]
+ CMP r3, #1
+ BEQ _reswitch
+ MOV r3, #1
+ STR r3, [r2]
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
+ LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
+ STR r0, [r2]
+
+_reswitch
+ LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
+ STR r1, [r2]
+
+ LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
- CPSIE I ; enable interrupts at processor level
BX LR
; r0 --> swith from thread stack
@@ -72,6 +83,16 @@ rt_hw_context_switch:
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT rt_hw_pend_sv
rt_hw_pend_sv:
+
+ ; disable interrupt to protect context switch
+ MRS r2, PRIMASK
+ CPSID I
+
+ ; clear rt_thread_switch_interrput_flag to 0
+ LDR r0, =rt_thread_switch_interrput_flag
+ MOV r1, #0x00
+ STR r1, [r0]
+
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
@@ -89,6 +110,9 @@ swtich_to_thread
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
MSR psp, r1 ; update stack pointer
+ ; restore interrupt
+ MSR PRIMASK, r2
+
ORR lr, lr, #0x04
BX lr
@@ -119,52 +143,9 @@ rt_hw_context_switch_to:
; never reach here!
-;/*
-; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)
-; * {
-; * if (rt_thread_switch_interrput_flag == 1)
-; * {
-; * rt_interrupt_to_thread = to;
-; * }
-; * else
-; * {
-; * rt_thread_switch_interrput_flag = 1;
-; * rt_interrupt_from_thread = from;
-; * rt_interrupt_to_thread = to;
-; * }
-; * }
-; */
- EXPORT rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- LDR r2, =rt_thread_switch_interrput_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
- STR r3, [r2]
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-_reswitch:
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
- BX lr
-
+; compatible with old version
EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch:
- LDR r0, =rt_thread_switch_interrput_flag
- LDR r1, [r0]
- CBZ r1, _no_switch
-
- ; clear rt_thread_switch_interrput_flag to 0
- MOV r1, #0x00
- STR r1, [r0]
-
- ; trigger context switch
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
-
-_no_switch:
BX lr
- END \ No newline at end of file
+ END
diff --git a/libcpu/arm/stm32/fault_iar.S b/libcpu/arm/stm32/fault_iar.S
new file mode 100644
index 0000000000..21f9302558
--- /dev/null
+++ b/libcpu/arm/stm32/fault_iar.S
@@ -0,0 +1,34 @@
+;/*
+; * File : context.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-01-17 Bernard first version
+; */
+
+ SECTION .text:CODE(2)
+ THUMB
+ REQUIRE8
+ PRESERVE8
+
+ IMPORT rt_hw_hard_fault_exception
+
+ EXPORT rt_hw_hard_fault
+rt_hw_hard_fault:
+
+ ; get current context
+ MRS r0, psp ; get fault thread stack pointer
+ PUSH {lr}
+ BL rt_hw_hard_fault_exception
+ POP {lr}
+
+ ORR lr, lr, #0x04
+ BX lr
+
+ END
diff --git a/libcpu/arm/stm32/fault_rvds.S b/libcpu/arm/stm32/fault_rvds.S
index 90419337ad..799f8d40f1 100644
--- a/libcpu/arm/stm32/fault_rvds.S
+++ b/libcpu/arm/stm32/fault_rvds.S
@@ -12,22 +12,24 @@
; * 2009-01-17 Bernard first version
; */
- AREA |.text|, CODE, READONLY, ALIGN=2
- THUMB
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2
+ THUMB
+ REQUIRE8
+ PRESERVE8
- IMPORT rt_hw_hard_fault_exception
+ IMPORT rt_hw_hard_fault_exception
-rt_hw_hard_fault PROC
- EXPORT rt_hw_hard_fault
+rt_hw_hard_fault PROC
+ EXPORT rt_hw_hard_fault
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- BL rt_hw_hard_fault_exception
+ ; get current context
+ MRS r0, psp ; get fault thread stack pointer
+ PUSH {lr}
+ BL rt_hw_hard_fault_exception
+ POP {lr}
- ORR lr, lr, #0x04
- BX lr
+ ORR lr, lr, #0x04
+ BX lr
ENDP
END
diff --git a/libcpu/arm/stm32/serial.c b/libcpu/arm/stm32/serial.c
index 3140a8446a..66cd85fe98 100644
--- a/libcpu/arm/stm32/serial.c
+++ b/libcpu/arm/stm32/serial.c
@@ -1,586 +1,587 @@
-/*
- * File : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-02-05 Bernard first version
- */
-
-#include "serial.h"
-
-static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
- rt_uint32_t address, rt_uint32_t size);
-
-/**
- * @addtogroup STM32
- */
-/*@{*/
-
-/**
- * This function read a character from serial without interrupt enable mode
- *
- * @return the read char
- */
-int rt_serial_getc(struct stm32_serial_device* uart)
-{
- rt_base_t level;
- int ch = -1;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- if (uart->int_rx->read_index != uart->int_rx->save_index)
- {
- ch = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- return ch;
-}
-
-/* save a char to serial buffer */
-void rt_serial_savechar(struct stm32_serial_device* uart, char ch)
-{
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
- uart->int_rx->save_index ++;
- if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (uart->int_rx->save_index == uart->int_rx->read_index)
- {
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-}
-
-/**
- * This function will write a character to serial without interrupt enable mode
- *
- * @param c the char to write
- */
-void rt_serial_putc(rt_device_t device, const char c)
-{
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
-
- /*
- * to be polite with serial console add a line feed
- * to the carriage return character
- */
- if (c=='\n' && (device->flag & RT_DEVICE_FLAG_STREAM))
- rt_serial_putc(device, '\r');
-
- while (!(uart->uart_device->SR & USART_FLAG_TXE));
- uart->uart_device->DR = (c & 0x1FF);
-}
-
-/* RT-Thread Device Interface */
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->private;
-
- if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
- {
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_memset(uart->int_rx->rx_buffer, 0,
- sizeof(uart->int_rx->rx_buffer));
- uart->int_rx->read_index = 0;
- uart->int_rx->save_index = 0;
- }
-
- if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- RT_ASSERT(uart->dma_rx->dma_channel != RT_NULL);
- uart->dma_rx->read_index = uart->dma_rx->read_descriptor = 0;
- uart->dma_rx->is_full = RT_FALSE;
- }
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- rt_memset(uart->int_tx->tx_buffer, 0,
- sizeof(uart->int_tx->tx_buffer));
- uart->int_tx->write_index = uart->int_tx->save_index = 0;
- }
-
- if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- RT_ASSERT(uart->dma_rx->dma_channel != RT_NULL);
- uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
- }
-
- /* Enable USART */
- USART_Cmd(uart->uart_device, ENABLE);
-
- dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- struct stm32_serial_device* uart;
-
- RT_ASSERT(dev != RT_NULL);
-
- uart = (struct stm32_serial_device*)dev->private;
-
- if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* enable Rx DMA */
- rt_serial_enable_dma(uart->dma_rx->dma_channel,
- (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
- UART_DMA_RX_BUFFER_SIZE);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- struct stm32_serial_device* uart;
-
- RT_ASSERT(dev != RT_NULL);
-
- uart = (struct stm32_serial_device*)dev->private;
-
- if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* disable DMA */
- DMA_Cmd(uart->dma_rx->dma_channel, DISABLE);
- }
- return RT_EOK;
-}
-
-static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct stm32_serial_device* uart;
-
- ptr = buffer;
- err_code = RT_EOK;
- uart = (struct stm32_serial_device*)dev->private;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_int32_t ch;
-
- /* interrupt mode Rx */
- while (size)
- {
- /* get a character */
- ch = rt_serial_getc(uart);
- if (ch < 0)
- {
- /* set error code */
- err_code = -RT_EEMPTY;
- }
- else
- {
- *ptr++ = ch;
- size --;
- }
- }
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* check queue empty */
- if ((uart->dma_rx->read_descriptor == uart->dma_rx->save_descriptor))
- {
- /* set error code */
- err_code = -RT_EEMPTY;
- }
- else
- {
- /* read data */
- while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
- {
- /* read buffer */
- *ptr ++ = uart->dma_rx->
- rx_buffer[uart->dma_rx->read_descriptor][uart->dma_rx->read_index];
-
- /* move to next position */
- uart->dma_rx->read_index ++;
-
- /* wrap read index */
- if (uart->dma_rx->read_index >= UART_DMA_RX_BUFFER_SIZE)
- {
- /* wrap read index */
- uart->dma_rx->read_index = 0;
-
- /* move to next read descriptor */
- uart->dma_rx->read_descriptor ++;
- /* wrap read descriptor */
- if (uart->dma_rx->read_descriptor >= UART_DMA_RX_DESCRIPTOR)
- uart->dma_rx->read_descriptor = 0;
-
- if (uart->dma_rx->is_full == RT_TRUE)
- {
- rt_uint32_t level;
-
- level = rt_hw_interrupt_disable();
- uart->dma_rx->save_descriptor ++;
- if (uart->dma_rx->save_descriptor >= UART_DMA_RX_DESCRIPTOR)
- uart->dma_rx->save_descriptor = 0;
- rt_hw_interrupt_enable(level);
-
- /* re-enable DMA to receive */
- rt_serial_enable_dma(uart->dma_rx->dma_channel,
- (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
- UART_DMA_RX_BUFFER_SIZE);
- }
-
- /* check queue empty */
- if ((uart->dma_rx->read_descriptor == uart->dma_rx->save_descriptor))
- {
- /* set error code */
- err_code = -RT_EEMPTY;
- break;
- }
- }
- }
- }
- }
- else
- {
- /* polling mode */
- while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
- {
- while (uart->uart_device->SR & USART_FLAG_RXNE)
- {
- *ptr = uart->uart_device->DR & 0xff;
- ptr ++;
- }
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
- rt_uint32_t address, rt_uint32_t size)
-{
- RT_ASSERT(dma_channel != RT_NULL);
-
- /* disable DMA */
- DMA_Cmd(dma_channel, DISABLE);
-
- /* set buffer address */
- dma_channel->CMAR = address;
- /* set size */
- dma_channel->CNDTR = size;
-
- /* enable DMA */
- DMA_Cmd(dma_channel, ENABLE);
-}
-
-static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct stm32_serial_device* uart;
-
- err_code = RT_EOK;
- ptr = (rt_uint8_t*)buffer;
- uart = (struct stm32_serial_device*)dev->private;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* interrupt mode Tx */
- while (uart->int_tx->save_index != uart->int_tx->write_index)
- {
- /* save on tx buffer */
- uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
- -- size;
-
- /* move to next position */
- uart->int_tx->save_index ++;
-
- /* wrap save index */
- if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
- uart->int_tx->save_index = 0;
- }
-
- /* set error code */
- if (size > 0)
- err_code = -RT_EFULL;
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- /* DMA mode Tx */
-
- /* allocate a data node */
- struct stm32_serial_data_node* data_node =
- (struct stm32_serial_data_node*) rt_malloc (sizeof(struct stm32_serial_data_node));
- if (data_node == RT_NULL)
- {
- /* set error code */
- err_code = -RT_ENOMEM;
- }
- else
- {
- rt_uint32_t level;
-
- /* fill data node */
- data_node->data_ptr = ptr;
- data_node->data_size = size;
-
- /* insert to data link */
- data_node->next = RT_NULL;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- data_node->prev = uart->dma_tx->list_tail;
- if (uart->dma_tx->list_tail != RT_NULL)
- uart->dma_tx->list_tail->next = data_node;
- uart->dma_tx->list_tail = data_node;
-
- if (uart->dma_tx->list_head == RT_NULL)
- {
- /* start DMA to transmit data */
- uart->dma_tx->list_head = data_node;
-
- /* Enable DMA Channel */
- rt_serial_enable_dma(uart->dma_tx->dma_channel,
- (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
- uart->dma_tx->list_head->data_size);
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
- }
- else
- {
- /* polling mode */
- while (size)
- {
- rt_serial_putc(dev, *ptr);
- ++ptr; --size;
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- struct stm32_serial_device* uart;
-
- RT_ASSERT(dev != RT_NULL);
-
- uart = (struct stm32_serial_device*)dev->private;
- switch (cmd)
- {
- case RT_DEVICE_CTRL_SUSPEND:
- /* suspend device */
- dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
- USART_Cmd(uart->uart_device, DISABLE);
- break;
-
- case RT_DEVICE_CTRL_RESUME:
- /* resume device */
- dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
- USART_Cmd(uart->uart_device, ENABLE);
- break;
- }
-
- return RT_EOK;
-}
-
-/*
- * serial register for STM32
- * support STM32F103VB and STM32F103ZE
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
-{
- RT_ASSERT(device != RT_NULL);
-
- device->type = RT_Device_Class_Char;
- device->rx_indicate = RT_NULL;
- device->tx_complete = RT_NULL;
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
- device->private = serial;
-
- /* register a character device */
- return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
-
- if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
- {
- /* interrupt mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
- /* save on rx buffer */
- while (uart->uart_device->SR & USART_FLAG_RXNE)
- {
- rt_serial_savechar(uart, uart->uart_device->DR & 0xff);
- }
-
- /* clear interrupt */
- USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
-
- /* invoke callback */
- if (device->rx_indicate != RT_NULL)
- {
- rt_size_t rx_length;
-
- /* get rx length */
- rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
- UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
- uart->int_rx->save_index - uart->int_rx->read_index;
-
- device->rx_indicate(device, rx_length);
- }
- }
-
- if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
- {
- /* interrupt mode transmission */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_TX);
-
- /* transmission completed */
- uart->int_tx->write_index ++;
- if (uart->int_tx->write_index >= UART_TX_BUFFER_SIZE)
- uart->int_tx->write_index = 0;
-
- /* clear interrupt */
- USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
-
- /* start next transmission */
- if (uart->int_tx->write_index <
- uart->int_tx->save_index)
- {
- uart->uart_device->DR = uart->int_tx
- ->tx_buffer[uart->int_tx->write_index];
- }
- }
-}
-
-/*
- * ISR for DMA mode Rx
- */
-void rt_hw_serial_dma_rx_isr(rt_device_t device)
-{
- rt_uint32_t next_descriptor;
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
-
- /* DMA mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_RX);
-
- /* invoke callback */
- if (device->rx_indicate != RT_NULL)
- device->rx_indicate(device, UART_DMA_RX_BUFFER_SIZE);
-
- next_descriptor = uart->dma_rx->save_descriptor;
-
- /* move to next descriptor */
- next_descriptor ++;
- if (next_descriptor >= UART_DMA_RX_DESCRIPTOR)
- next_descriptor = 0;
-
- if (next_descriptor != uart->dma_rx->read_descriptor)
- {
- uart->dma_rx->save_descriptor = next_descriptor;
- /* enable next DMA */
- rt_serial_enable_dma(uart->dma_rx->dma_channel,
- (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
- UART_DMA_RX_BUFFER_SIZE);
- }
- else
- {
- /* no descriptor yet, disable DMA */
- DMA_Cmd(uart->dma_rx->dma_channel, DISABLE);
- uart->dma_rx->is_full = RT_TRUE;
- }
-}
-
-/*
- * ISR for DMA mode Tx
- */
-void rt_hw_serial_dma_tx_isr(rt_device_t device)
-{
- rt_uint32_t level;
- struct stm32_serial_data_node* data_node;
- struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
-
- /* DMA mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
-
- /* get the first data node */
- data_node = uart->dma_tx->list_head;
- RT_ASSERT(data_node != RT_NULL);
-
- /* invoke call to notify tx complete */
- if (device->tx_complete != RT_NULL)
- device->tx_complete(device, data_node->data_ptr);
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- /* remove list tail */
- uart->dma_tx->list_tail = data_node->prev;
- if (uart->dma_tx->list_tail == RT_NULL)
- uart->dma_tx->list_head = RT_NULL;
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- /* free data node memory */
- rt_free(data_node);
-
- if (uart->dma_tx->list_tail != RT_NULL)
- {
- /* transmit next data node */
- rt_serial_enable_dma(uart->dma_tx->dma_channel,
- (rt_uint32_t)uart->dma_tx->list_tail->data_ptr,
- uart->dma_tx->list_tail->data_size);
- }
- else
- {
- /* no data to be transmitted, disable DMA */
- DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
- }
-}
-
-/*@}*/
+/*
+ * File : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-02-05 Bernard first version
+ */
+
+#include "serial.h"
+#include <stm32f10x_dma.h>
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+ rt_uint32_t address, rt_uint32_t size);
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+/**
+ * This function read a character from serial without interrupt enable mode
+ *
+ * @return the read char
+ */
+int rt_serial_getc(struct stm32_serial_device* uart)
+{
+ rt_base_t level;
+ int ch = -1;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ if (uart->int_rx->read_index != uart->int_rx->save_index)
+ {
+ ch = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+
+ return ch;
+}
+
+/* save a char to serial buffer */
+void rt_serial_savechar(struct stm32_serial_device* uart, char ch)
+{
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+ uart->int_rx->save_index ++;
+ if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->save_index = 0;
+
+ /* if the next position is read index, discard this 'read char' */
+ if (uart->int_rx->save_index == uart->int_rx->read_index)
+ {
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+}
+
+/**
+ * This function will write a character to serial without interrupt enable mode
+ *
+ * @param c the char to write
+ */
+void rt_serial_putc(rt_device_t device, const char c)
+{
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
+
+ /*
+ * to be polite with serial console add a line feed
+ * to the carriage return character
+ */
+ if (c=='\n' && (device->flag & RT_DEVICE_FLAG_STREAM))
+ rt_serial_putc(device, '\r');
+
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = (c & 0x1FF);
+}
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->private;
+
+ if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+ {
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_memset(uart->int_rx->rx_buffer, 0,
+ sizeof(uart->int_rx->rx_buffer));
+ uart->int_rx->read_index = 0;
+ uart->int_rx->save_index = 0;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+ {
+ RT_ASSERT(uart->dma_rx->dma_channel != RT_NULL);
+ uart->dma_rx->read_index = uart->dma_rx->read_descriptor = 0;
+ uart->dma_rx->is_full = RT_FALSE;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ rt_memset(uart->int_tx->tx_buffer, 0,
+ sizeof(uart->int_tx->tx_buffer));
+ uart->int_tx->write_index = uart->int_tx->save_index = 0;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ RT_ASSERT(uart->dma_rx->dma_channel != RT_NULL);
+ uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+ }
+
+ /* Enable USART */
+ USART_Cmd(uart->uart_device, ENABLE);
+
+ dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ struct stm32_serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ uart = (struct stm32_serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+ {
+ /* enable Rx DMA */
+ rt_serial_enable_dma(uart->dma_rx->dma_channel,
+ (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
+ UART_DMA_RX_BUFFER_SIZE);
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+ struct stm32_serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ uart = (struct stm32_serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+ {
+ /* disable DMA */
+ DMA_Cmd(uart->dma_rx->dma_channel, DISABLE);
+ }
+ return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
+
+ ptr = buffer;
+ err_code = RT_EOK;
+ uart = (struct stm32_serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_int32_t ch;
+
+ /* interrupt mode Rx */
+ while (size)
+ {
+ /* get a character */
+ ch = rt_serial_getc(uart);
+ if (ch < 0)
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+ }
+ else
+ {
+ *ptr++ = ch;
+ size --;
+ }
+ }
+ }
+ else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+ {
+ /* check queue empty */
+ if ((uart->dma_rx->read_descriptor == uart->dma_rx->save_descriptor))
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+ }
+ else
+ {
+ /* read data */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ /* read buffer */
+ *ptr ++ = uart->dma_rx->
+ rx_buffer[uart->dma_rx->read_descriptor][uart->dma_rx->read_index];
+
+ /* move to next position */
+ uart->dma_rx->read_index ++;
+
+ /* wrap read index */
+ if (uart->dma_rx->read_index >= UART_DMA_RX_BUFFER_SIZE)
+ {
+ /* wrap read index */
+ uart->dma_rx->read_index = 0;
+
+ /* move to next read descriptor */
+ uart->dma_rx->read_descriptor ++;
+ /* wrap read descriptor */
+ if (uart->dma_rx->read_descriptor >= UART_DMA_RX_DESCRIPTOR)
+ uart->dma_rx->read_descriptor = 0;
+
+ if (uart->dma_rx->is_full == RT_TRUE)
+ {
+ rt_uint32_t level;
+
+ level = rt_hw_interrupt_disable();
+ uart->dma_rx->save_descriptor ++;
+ if (uart->dma_rx->save_descriptor >= UART_DMA_RX_DESCRIPTOR)
+ uart->dma_rx->save_descriptor = 0;
+ rt_hw_interrupt_enable(level);
+
+ /* re-enable DMA to receive */
+ rt_serial_enable_dma(uart->dma_rx->dma_channel,
+ (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
+ UART_DMA_RX_BUFFER_SIZE);
+ }
+
+ /* check queue empty */
+ if ((uart->dma_rx->read_descriptor == uart->dma_rx->save_descriptor))
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+ break;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ *ptr = uart->uart_device->DR & 0xff;
+ ptr ++;
+ }
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+ rt_uint32_t address, rt_uint32_t size)
+{
+ RT_ASSERT(dma_channel != RT_NULL);
+
+ /* disable DMA */
+ DMA_Cmd(dma_channel, DISABLE);
+
+ /* set buffer address */
+ dma_channel->CMAR = address;
+ /* set size */
+ dma_channel->CNDTR = size;
+
+ /* enable DMA */
+ DMA_Cmd(dma_channel, ENABLE);
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
+
+ err_code = RT_EOK;
+ ptr = (rt_uint8_t*)buffer;
+ uart = (struct stm32_serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /* interrupt mode Tx */
+ while (uart->int_tx->save_index != uart->int_tx->write_index)
+ {
+ /* save on tx buffer */
+ uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+ -- size;
+
+ /* move to next position */
+ uart->int_tx->save_index ++;
+
+ /* wrap save index */
+ if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+ uart->int_tx->save_index = 0;
+ }
+
+ /* set error code */
+ if (size > 0)
+ err_code = -RT_EFULL;
+ }
+ else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ /* DMA mode Tx */
+
+ /* allocate a data node */
+ struct stm32_serial_data_node* data_node =
+ (struct stm32_serial_data_node*) rt_malloc (sizeof(struct stm32_serial_data_node));
+ if (data_node == RT_NULL)
+ {
+ /* set error code */
+ err_code = -RT_ENOMEM;
+ }
+ else
+ {
+ rt_uint32_t level;
+
+ /* fill data node */
+ data_node->data_ptr = ptr;
+ data_node->data_size = size;
+
+ /* insert to data link */
+ data_node->next = RT_NULL;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ data_node->prev = uart->dma_tx->list_tail;
+ if (uart->dma_tx->list_tail != RT_NULL)
+ uart->dma_tx->list_tail->next = data_node;
+ uart->dma_tx->list_tail = data_node;
+
+ if (uart->dma_tx->list_head == RT_NULL)
+ {
+ /* start DMA to transmit data */
+ uart->dma_tx->list_head = data_node;
+
+ /* Enable DMA Channel */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+ uart->dma_tx->list_head->data_size);
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while (size)
+ {
+ rt_serial_putc(dev, *ptr);
+ ++ptr; --size;
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ struct stm32_serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ uart = (struct stm32_serial_device*)dev->private;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_SUSPEND:
+ /* suspend device */
+ dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, DISABLE);
+ break;
+
+ case RT_DEVICE_CTRL_RESUME:
+ /* resume device */
+ dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, ENABLE);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/*
+ * serial register for STM32
+ * support STM32F103VB and STM32F103ZE
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
+{
+ RT_ASSERT(device != RT_NULL);
+
+ device->type = RT_Device_Class_Char;
+ device->rx_indicate = RT_NULL;
+ device->tx_complete = RT_NULL;
+ device->init = rt_serial_init;
+ device->open = rt_serial_open;
+ device->close = rt_serial_close;
+ device->read = rt_serial_read;
+ device->write = rt_serial_write;
+ device->control = rt_serial_control;
+ device->private = serial;
+
+ /* register a character device */
+ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
+
+ if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+ {
+ /* interrupt mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+ /* save on rx buffer */
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ rt_serial_savechar(uart, uart->uart_device->DR & 0xff);
+ }
+
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ {
+ rt_size_t rx_length;
+
+ /* get rx length */
+ rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+ UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+ uart->int_rx->save_index - uart->int_rx->read_index;
+
+ device->rx_indicate(device, rx_length);
+ }
+ }
+
+ if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+ {
+ /* interrupt mode transmission */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_TX);
+
+ /* transmission completed */
+ uart->int_tx->write_index ++;
+ if (uart->int_tx->write_index >= UART_TX_BUFFER_SIZE)
+ uart->int_tx->write_index = 0;
+
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+ /* start next transmission */
+ if (uart->int_tx->write_index <
+ uart->int_tx->save_index)
+ {
+ uart->uart_device->DR = uart->int_tx
+ ->tx_buffer[uart->int_tx->write_index];
+ }
+ }
+}
+
+/*
+ * ISR for DMA mode Rx
+ */
+void rt_hw_serial_dma_rx_isr(rt_device_t device)
+{
+ rt_uint32_t next_descriptor;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
+
+ /* DMA mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_RX);
+
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ device->rx_indicate(device, UART_DMA_RX_BUFFER_SIZE);
+
+ next_descriptor = uart->dma_rx->save_descriptor;
+
+ /* move to next descriptor */
+ next_descriptor ++;
+ if (next_descriptor >= UART_DMA_RX_DESCRIPTOR)
+ next_descriptor = 0;
+
+ if (next_descriptor != uart->dma_rx->read_descriptor)
+ {
+ uart->dma_rx->save_descriptor = next_descriptor;
+ /* enable next DMA */
+ rt_serial_enable_dma(uart->dma_rx->dma_channel,
+ (rt_uint32_t)&(uart->dma_rx->rx_buffer[uart->dma_rx->save_descriptor][0]),
+ UART_DMA_RX_BUFFER_SIZE);
+ }
+ else
+ {
+ /* no descriptor yet, disable DMA */
+ DMA_Cmd(uart->dma_rx->dma_channel, DISABLE);
+ uart->dma_rx->is_full = RT_TRUE;
+ }
+}
+
+/*
+ * ISR for DMA mode Tx
+ */
+void rt_hw_serial_dma_tx_isr(rt_device_t device)
+{
+ rt_uint32_t level;
+ struct stm32_serial_data_node* data_node;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->private;
+
+ /* DMA mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+
+ /* get the first data node */
+ data_node = uart->dma_tx->list_head;
+ RT_ASSERT(data_node != RT_NULL);
+
+ /* invoke call to notify tx complete */
+ if (device->tx_complete != RT_NULL)
+ device->tx_complete(device, data_node->data_ptr);
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ /* remove list tail */
+ uart->dma_tx->list_tail = data_node->prev;
+ if (uart->dma_tx->list_tail == RT_NULL)
+ uart->dma_tx->list_head = RT_NULL;
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+
+ /* free data node memory */
+ rt_free(data_node);
+
+ if (uart->dma_tx->list_tail != RT_NULL)
+ {
+ /* transmit next data node */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_tail->data_ptr,
+ uart->dma_tx->list_tail->data_size);
+ }
+ else
+ {
+ /* no data to be transmitted, disable DMA */
+ DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+ }
+}
+
+/*@}*/
diff --git a/libcpu/arm/stm32/serial.h b/libcpu/arm/stm32/serial.h
index a36cad79a2..5bf3b8155e 100644
--- a/libcpu/arm/stm32/serial.h
+++ b/libcpu/arm/stm32/serial.h
@@ -5,7 +5,7 @@
#include <rtthread.h>
/* STM32F10x library definitions */
-#include <stm32f10x_lib.h>
+#include <stm32f10x.h>
#define UART_DMA_RX_DESCRIPTOR 2
#define UART_DMA_RX_BUFFER_SIZE 16
diff --git a/libcpu/arm/stm32/start_iar.c b/libcpu/arm/stm32/start_iar.c
deleted file mode 100644
index 3cc01ed9e8..0000000000
--- a/libcpu/arm/stm32/start_iar.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_vector.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : STM32F10x vector table for EWARM5.x toolchain.
-* This module performs:
-* - Set the initial SP
-* - Set the initial PC == __iar_program_start,
-* - Set the vector table entries with the exceptions ISR address,
-* - Configure external SRAM mounted on STM3210E-EVAL board
-* to be used as data memory (optional, to be enabled by user)
-* After Reset the Cortex-M3 processor is in Thread mode,
-* priority is Privileged, and the Stack is set to Main.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
-#include "stm32f10x_it.h"
-
-/* Private typedef -----------------------------------------------------------*/
-typedef void( *intfunc )( void );
-typedef union { intfunc __fun; void * __ptr; } intvec_elem;
-
-/* Private define ------------------------------------------------------------*/
-/* Uncomment the following line if you need to use external SRAM mounted on
- STM3210E-EVAL board as data memory */
-/* #define DATA_IN_ExtSRAM */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-#pragma language=extended
-#pragma segment="CSTACK"
-
-void __iar_program_start( void );
-
-#pragma location = ".intvec"
-/* STM32F10x Vector Table entries */
-const intvec_elem __vector_table[] =
-{
- { .__ptr = __sfe( "CSTACK" ) },
- __iar_program_start,
- NMIException,
- HardFaultException,
- MemManageException,
- BusFaultException,
- UsageFaultException,
- 0, 0, 0, 0, /* Reserved */
- SVCHandler,
- DebugMonitor,
- 0, /* Reserved */
- rt_hw_pend_sv,
- SysTickHandler,
- WWDG_IRQHandler,
- PVD_IRQHandler,
- TAMPER_IRQHandler,
- RTC_IRQHandler,
- FLASH_IRQHandler,
- RCC_IRQHandler,
- EXTI0_IRQHandler,
- EXTI1_IRQHandler,
- EXTI2_IRQHandler,
- EXTI3_IRQHandler,
- EXTI4_IRQHandler,
- DMA1_Channel1_IRQHandler,
- DMA1_Channel2_IRQHandler,
- DMA1_Channel3_IRQHandler,
- DMA1_Channel4_IRQHandler,
- DMA1_Channel5_IRQHandler,
- DMA1_Channel6_IRQHandler,
- DMA1_Channel7_IRQHandler,
- ADC1_2_IRQHandler,
- USB_HP_CAN_TX_IRQHandler,
- USB_LP_CAN_RX0_IRQHandler,
- CAN_RX1_IRQHandler,
- CAN_SCE_IRQHandler,
- EXTI9_5_IRQHandler,
- TIM1_BRK_IRQHandler,
- TIM1_UP_IRQHandler,
- TIM1_TRG_COM_IRQHandler,
- TIM1_CC_IRQHandler,
- TIM2_IRQHandler,
- TIM3_IRQHandler,
- TIM4_IRQHandler,
- I2C1_EV_IRQHandler,
- I2C1_ER_IRQHandler,
- I2C2_EV_IRQHandler,
- I2C2_ER_IRQHandler,
- SPI1_IRQHandler,
- SPI2_IRQHandler,
- USART1_IRQHandler,
- USART2_IRQHandler,
- USART3_IRQHandler,
- EXTI15_10_IRQHandler,
- RTCAlarm_IRQHandler,
- USBWakeUp_IRQHandler,
- TIM8_BRK_IRQHandler,
- TIM8_UP_IRQHandler,
- TIM8_TRG_COM_IRQHandler,
- TIM8_CC_IRQHandler,
- ADC3_IRQHandler,
- FSMC_IRQHandler,
- SDIO_IRQHandler,
- TIM5_IRQHandler,
- SPI3_IRQHandler,
- UART4_IRQHandler,
- UART5_IRQHandler,
- TIM6_IRQHandler,
- TIM7_IRQHandler,
- DMA2_Channel1_IRQHandler,
- DMA2_Channel2_IRQHandler,
- DMA2_Channel3_IRQHandler,
- DMA2_Channel4_5_IRQHandler,
-};
-
-#ifdef DATA_IN_ExtSRAM
-#pragma language=extended
-
-__interwork int __low_level_init(void);
-
-#pragma location="ICODE"
-__interwork int __low_level_init(void)
-{
-
-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses*/
-
- /* Enable FSMC clock */
- *(vu32 *)0x40021014 = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- *(vu32 *)0x40021018 = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- *(vu32 *)0x40011400 = 0x44BB44BB;
- *(vu32 *)0x40011404 = 0xBBBBBBBB;
-
- *(vu32 *)0x40011800 = 0xB44444BB;
- *(vu32 *)0x40011804 = 0xBBBBBBBB;
-
- *(vu32 *)0x40011C00 = 0x44BBBBBB;
- *(vu32 *)0x40011C04 = 0xBBBB4444;
-
- *(vu32 *)0x40012000 = 0x44BBBBBB;
- *(vu32 *)0x40012004 = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- *(vu32 *)0xA0000010 = 0x00001011;
- *(vu32 *)0xA0000014 = 0x00000200;
-
-
- return (1);
-}
-#endif /*DATA_IN_ExtSRAM*/
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
-
-
diff --git a/libcpu/arm/stm32/start_iar.s b/libcpu/arm/stm32/start_iar.s
new file mode 100644
index 0000000000..bd0d76d086
--- /dev/null
+++ b/libcpu/arm/stm32/start_iar.s
@@ -0,0 +1,435 @@
+;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd.s
+;* Author : MCD Application Team
+;* Version : V3.0.0
+;* Date : 04/06/2009
+;* Description : STM32F10x High Density Devices vector table for EWARM5.x
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR address,
+;* - Configure external SRAM mounted on STM3210E-EVAL board
+;* to be used as data memory (optional, to be enabled by user)
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; ICODE is the same segment as cstartup. By placing __low_level_init
+ ;; in the same segment, we make sure it can be reached with BL. */
+
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .icode:CODE:NOROOT(2)
+
+ IMPORT rt_hw_hard_fault
+ IMPORT rt_hw_pend_sv
+ IMPORT rt_hw_timer_handler
+
+ PUBLIC __low_level_init
+
+ PUBWEAK SystemInit_ExtMemCtl
+ SECTION .text:CODE:REORDER(2)
+ THUMB
+SystemInit_ExtMemCtl
+ BX LR
+
+__low_level_init:
+
+ ;; Initialize hardware.
+ LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
+ MOV R11, LR
+ BLX R0
+ LDR R1, =sfe(CSTACK) ; restore original stack pointer
+ MSR MSP, R1
+ MOV R0,#1
+ ;; Return with BX to be independent of mode of caller
+ BX R11
+
+ ;; Forward declaration of sections.
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__intial_sp EQU 0x20000400
+__vector_table
+ DCD __intial_sp
+ DCD __iar_program_start
+
+ DCD NMI_Handler ; NMI Handler
+ DCD rt_hw_hard_fault ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD rt_hw_pend_sv ; PendSV Handler
+ DCD rt_hw_timer_handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+ PUBWEAK FSMC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler
+ B FSMC_IRQHandler
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+ PUBWEAK DMA2_Channel4_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+ B DMA2_Channel4_5_IRQHandler
+
+
+ END
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/libcpu/arm/stm32/start_rvds.s b/libcpu/arm/stm32/start_rvds.s
index b212037fca..f3ebbc2537 100644
--- a/libcpu/arm/stm32/start_rvds.s
+++ b/libcpu/arm/stm32/start_rvds.s
@@ -1,29 +1,18 @@
-;******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
-;* File Name : startup_stm32f10x_hd.s
-;* Author : MCD Application Team
-;* Version : V3.1.0
-;* Date : 06/19/2009
-;* Description : STM32F10x High Density Devices vector table for RVMDK
-;* toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure external SRAM mounted on STM3210E-EVAL board
-;* to be used as data memory (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
+; /*
+; * File : start_rvds.s
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-09-23 Bernard first implementation
+; */
+
;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
@@ -35,8 +24,8 @@ Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
-__initial_sp EQU 0x20000400 ; stack used for SystemInit_ExtMemCtl
- ; always internal RAM used
+__initial_sp
+; not use external SRAM as data memory
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
@@ -62,84 +51,94 @@ __heap_limit
EXPORT __Vectors_End
EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD rt_hw_hard_fault ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD rt_hw_pend_sv ; PendSV Handler
- DCD rt_hw_timer_handler ; SysTick Handler
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD rt_hw_hard_fault ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD rt_hw_pend_sv ; PendSV Handler in RT-Thread
+ DCD rt_hw_timer_handler ; SysTick Handler in RT-Thread
; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
- DCD TIM1_BRK_IRQHandler ; TIM1 Break
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TIM8_BRK_IRQHandler ; TIM8 Break
- DCD TIM8_UP_IRQHandler ; TIM8 Update
- DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 and Channel5
+ ; for STM32F10x Connectivity line devices
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@@ -238,7 +237,7 @@ Default_Handler PROC
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
@@ -256,6 +255,15 @@ Default_Handler PROC
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
+ ; for STM32F10x Connectivity line devices
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
@@ -299,7 +307,7 @@ USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
+OTG_FS_WKUP_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
@@ -317,6 +325,15 @@ DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
+; for STM32F10x Connectivity line devices
+DMA2_Channel5_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
B .
ENDP
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 16:42:22 +0000