diff options
| author | nxp-ran <[email protected]> | 2026-08-21 17:45:38 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-08-21 17:45:38 +0800 |
| commit | 6ea682795bdbac59d3700b21e159ccaa3f7632cb (patch) | |
| tree | 2c660d04ccc7a439857a899155a3d137c71e354d | |
| parent | ba79f69477686196da1aa1aca3792e8f6c4e3085 (diff) | |
[BSP][NXP] Add new features of I2C DMA, CAN, SPI, DWT and SDIO for RT1180 (#11715)
* updated template files, conifg files and script files to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.
* updated different link files of GCC, IAR and KEIL, for supporting multicore kick-off and different loading methods
* Updated .ini files to support debugging in keil. And updeated .mac files to support deugging in iar.
* Updated template files, conifg files and script files of CM7 to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.
* Updated different link files of GCC, IAR and KEIL of CM7 project, for supporting multicore kick-off and different loading methods.
* Modify LittleFS to use the last 1 MB of flash and update CM7 support for LittleFS on QSPI flash.
* Updated different link files of loading to hyperram.
* Updated .ini files of CM7 to support debugging in keil. And updeated .mac files of CM7 to support deugging in iar.
* Remove Keil projects and keep templates only.
* Remove RAMFUNC due to IAR compilation issues, and use linker configuration to place all flash operation code in RAM.
* Add related code to support kick-offing CM7 and rpmsg-lite.
* Add codes to support cherryUSB for CM33 and CM7.
* Add mnt.c to support littleFS for CM7.
* Add codes to support etherCAT for CM7.
* Add codes to support USART12 for RT1180.
* Modify the drv_uart_v2.c to fix some bug to make it can work in CM33, but still cannot work in CM7. Will continue to update in next version.
* Updated README with both Chinese and English versions.
* Move the EtherCAT code into the packages\nxp-imxrt-sdk-latest.
* Remove EtherCAT-related sources, keep only SConscript.
* updated ci.attachconfig.yml for cm33 and cm7 projects.
* Fixed BSP_ROOT path error in rtconfig.py.
* Added drv_netc.c and updated SConscript for netc.
* Updated cherryusb_port.c to avoid worning.
* Updated sconscript to locate multicore directory in packages for header inclusion.
* Updated cm33/board/board.c to avoid worning when enable cm33_kickoff_cm7.
* Deleted peripheral.ethercat, because the related protocol stack has not been uploaded. And added CONFIG_BSP_USING_GPIO=y for Peripheral.netc.:
* Removed the SConscript of multicore and ethercat to packages.
* Added CONFIG_BSP_USING_GPIO=y to Peripheral.hyperflash_dma.
* Added CONFIG_BSP_USING_GPIO=y for Peripheral.hyperflash.
* Reformat code according to coding standards.
* Reformat code according to coding standards.
* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM33.
* Updated flexspi_port.h to support using flexspi api only.
* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM33.
* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM7.
* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM7.
* Added driver of DWT.
* Added driver of flexCAN for RT1180.
* Added driver of i2c dma for RT1180.
* Added driver of lpspi and dma for RT1180.
* Added driver of sdio for RT1180.
* Added driver of RTC for RT1180.
* Updated driver of drv_uart.c and fixed some bugs in drv_uart_v2.c.
* Updated README of imxrt1180-nxp-evk.
* Reformat codes according to tools/ci/clang_format_check.py
* fix: use unsigned shift to avoid UB in drv_can.c
* Removed unnecessary build artifacts and test files.
* bsp/nxp/imxrt: fix CI build errors for non-RT1180 BSPs
* bsp/nxp/imxrt: clang-format drv_lpadc.c to fix CI format check
* Fixed standalone driver compilation errors and code formatting issues.
* Fixed CI attach failures by updating the default linker script for CM7-only ITCM builds with large .text sections.
* [bsp][imxrt] fix BBNSM GPR epoch truncation by storing epoch in two 32-bit GPRs
* [bsp][imxrt] define DBG_TAG/DBG_LVL before rtdbg.h in cm7 mnt.c
* [bsp][imxrt1180] fix(sdcard): add timeout to sd0 wait loop in mnt.c
46 files changed, 3579 insertions, 769 deletions
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md index 17decced9c..4b53e3b04e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README.md @@ -34,14 +34,14 @@ This BSP currently provides peripheral support: | Rpmsg-lite | Supported | | | GPIO | supported | | | UART | Supported | | -| SPI | Not yet supported | | +| SPI | supported | | | I2C | supported | | | ADC | supported | | | Timer | supported | | -| SDIO | Not yet supported | | -| RTC | Not yet supported | | +| SDIO | supported | | +| RTC | supported | | | PWM | Not yet supported | | -| CAN | Not yet supported | | +| CAN | supported | | ## Usage Instructions diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md index 8f178e4e10..9b266190e4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md @@ -36,14 +36,14 @@ CM33对CM7的kick off将在后续版本中支持。 | Rpmsg-lite | 支持 | | | GPIO | 支持 | | | UART | 支持 | | -| SPI | 暂不支持 | | +| SPI | 支持 | | | I2C | 支持 | | | ADC | 支持 | | | Timer | 支持 | | -| SDIO | 暂不支持 | | -| RTC | 暂不支持 | | +| SDIO | 支持 | | +| RTC | 支持 | | | PWM | 暂不支持 | | -| CAN | 暂不支持 | | +| CAN | 支持 | | ## 使用说明 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml index d8b14a2d8f..8f1e47fe19 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml @@ -23,6 +23,37 @@ Peripheral.lpadc1: - CONFIG_RT_USING_ADC=y - CONFIG_BSP_USING_LPADC=y - CONFIG_BSP_USING_LPADC1=y +Peripheral.lpuart_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_LPUART=y + - CONFIG_BSP_USING_DMA=y +Peripheral.i2c_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_DMA=y +Peripheral.spi_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_DMA=y +Peripheral.can_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_CAN=y +Peripheral.rtc_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_RTC=y +Peripheral.dwt_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_DWT=y +Peripheral.sdio_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_SDCARD_FATFS=y Peripheral.usb_device: <<: *scons kconfig: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config index ba1a0be158..daef32c4e9 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -244,7 +244,7 @@ CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V2=y # CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y -# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_ADC is not set @@ -1445,15 +1445,18 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y # # On-chip Peripheral Drivers # -# CONFIG_BSP_USING_DMA is not set +# CONFIG_BSP_USING_DWT is not set +CONFIG_BSP_USING_DMA=y CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_SDIO is not set CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y -# CONFIG_BSP_LPUART1_RX_USING_DMA is not set -# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +CONFIG_BSP_LPUART1_RX_USING_DMA=y +CONFIG_BSP_LPUART1_RX_DMA_CHANNEL=0 +CONFIG_BSP_LPUART1_TX_USING_DMA=y +CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1 # CONFIG_BSP_USING_LPUART2 is not set # CONFIG_BSP_USING_LPUART3 is not set # CONFIG_BSP_USING_LPUART4 is not set @@ -1465,6 +1468,8 @@ CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_USING_LPUART10 is not set # CONFIG_BSP_USING_LPUART11 is not set # CONFIG_BSP_USING_LPUART12 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_FLEXSPI is not set # end of On-chip Peripheral Drivers @@ -1476,6 +1481,7 @@ CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_USE_MULTICORE is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_FS is not set +# CONFIG_BSP_USING_QSPI_FLASH is not set # end of Onboard Peripheral Drivers # diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c index 854f9aa21f..d05e4c71e2 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c @@ -31,9 +31,9 @@ #include <dfs_fs.h> #include <fal.h> -#define FS_PARTITION_NAME "filesystem" -#define FS_TYPE_NAME "lfs" -#define FS_MOUNT_POINT "/" +#define FS_PARTITION_NAME "filesystem" +#define FS_TYPE_NAME "lfs" +#define FS_MOUNT_POINT "/" static int _qspi_flash_fs_mount(void) { @@ -97,4 +97,48 @@ INIT_APP_EXPORT(_qspi_flash_fs_mount); */ INIT_COMPONENT_EXPORT(fal_init); -#endif /* BSP_USING_QSPI_FLASH_FS */
\ No newline at end of file +#endif /* BSP_USING_QSPI_FLASH_FS */ + +/* ==================================================================== + * SD card FAT filesystem (controlled by BSP_USING_SDCARD_FATFS) + * + * Dependencies: + * - drv_sdio.c / sdio_port.c (USDHC1 driver + board init) + * - RT-Thread MMCSD / elmfat component + * + * The driver registers the block device as "sd0" asynchronously, so + * this function polls until the device appears before mounting. + * ==================================================================== */ +#ifdef BSP_USING_SDCARD_FATFS +#include <dfs_fs.h> +#include <dfs_file.h> +#define DBG_TAG "app.sdcard" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +static int _sdcard_fs_mount(void) +{ + rt_tick_t start = rt_tick_get(); + while (rt_device_find("sd0") == RT_NULL) + { + if ((rt_tick_get() - start) > (5 * RT_TICK_PER_SECOND)) + { + LOG_E("wait for 'sd0' timeout"); + return -RT_ETIMEOUT; + } + rt_thread_mdelay(10); + } + + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + LOG_E("sd0 mount to '/' failed! (ret=%d)", ret); + return ret; + } + + LOG_I("sd0 mounted at '/'"); + return RT_EOK; +} +INIT_ENV_EXPORT(_sdcard_fs_mount); + +#endif /* BSP_USING_SDCARD_FATFS */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig index 7e2a35c94e..a8e23399de 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -21,6 +21,14 @@ config SOC_MIMXRT1189CVM8C_CM33 menu "On-chip Peripheral Drivers" + config BSP_USING_DWT + bool "Enable DWT (cycle counter, us delay)" + default n + help + Enable the ARM DWT cycle counter for high-resolution timing and + busy-wait microsecond delays. Provides dwt_init(), dwt_get_cycles(), + dwt_cycles_to_us(), and dwt_delay_us(). + config BSP_USING_DMA bool "Enable DMA" default n @@ -431,6 +439,228 @@ menu "On-chip Peripheral Drivers" default 23 endif + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 (LPSPI1)" + default n + + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + depends on BSP_USING_SPI1 + select BSP_USING_DMA + default n + + config BSP_SPI1_RX_DMA_CHANNEL + depends on BSP_SPI1_USING_DMA + int "Set SPI1 RX DMA channel (0-31)" + default 0 + + config BSP_SPI1_TX_DMA_CHANNEL + depends on BSP_SPI1_USING_DMA + int "Set SPI1 TX DMA channel (0-31)" + default 1 + + config BSP_USING_SPI2 + bool "Enable SPI2 (LPSPI2)" + default n + + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + depends on BSP_USING_SPI2 + select BSP_USING_DMA + default n + + config BSP_SPI2_RX_DMA_CHANNEL + depends on BSP_SPI2_USING_DMA + int "Set SPI2 RX DMA channel (0-31)" + default 2 + + config BSP_SPI2_TX_DMA_CHANNEL + depends on BSP_SPI2_USING_DMA + int "Set SPI2 TX DMA channel (0-31)" + default 3 + + config BSP_USING_SPI3 + bool "Enable SPI3 (LPSPI3)" + default n + + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + depends on BSP_USING_SPI3 + select BSP_USING_DMA + default n + + config BSP_SPI3_RX_DMA_CHANNEL + depends on BSP_SPI3_USING_DMA + int "Set SPI3 RX DMA channel (0-31)" + default 4 + + config BSP_SPI3_TX_DMA_CHANNEL + depends on BSP_SPI3_USING_DMA + int "Set SPI3 TX DMA channel (0-31)" + default 5 + + config BSP_USING_SPI4 + bool "Enable SPI4 (LPSPI4)" + default n + + config BSP_SPI4_USING_DMA + bool "Enable SPI4 DMA" + depends on BSP_USING_SPI4 + select BSP_USING_DMA + default n + + config BSP_SPI4_RX_DMA_CHANNEL + depends on BSP_SPI4_USING_DMA + int "Set SPI4 RX DMA channel (0-31)" + default 6 + + config BSP_SPI4_TX_DMA_CHANNEL + depends on BSP_SPI4_USING_DMA + int "Set SPI4 TX DMA channel (0-31)" + default 7 + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1 (LPI2C1)" + default n + + if BSP_USING_I2C1 + choice + prompt "Select I2C1 baudrate" + default HW_I2C1_BADURATE_100kHZ + + config HW_I2C1_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C1_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C1_RX_DMA_CHANNEL + depends on BSP_I2C1_USING_DMA + int "Set I2C1 RX DMA channel (0-31)" + default 8 + + config BSP_I2C1_TX_DMA_CHANNEL + depends on BSP_I2C1_USING_DMA + int "Set I2C1 TX DMA channel (0-31)" + default 9 + endif + + config BSP_USING_I2C2 + bool "Enable I2C2 (LPI2C2)" + default n + + if BSP_USING_I2C2 + choice + prompt "Select I2C2 baudrate" + default HW_I2C2_BADURATE_100kHZ + + config HW_I2C2_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C2_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C2_RX_DMA_CHANNEL + depends on BSP_I2C2_USING_DMA + int "Set I2C2 RX DMA channel (0-31)" + default 10 + + config BSP_I2C2_TX_DMA_CHANNEL + depends on BSP_I2C2_USING_DMA + int "Set I2C2 TX DMA channel (0-31)" + default 11 + endif + + config BSP_USING_I2C3 + bool "Enable I2C3 (LPI2C3)" + default n + + if BSP_USING_I2C3 + choice + prompt "Select I2C3 baudrate" + default HW_I2C3_BADURATE_100kHZ + + config HW_I2C3_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C3_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C3_RX_DMA_CHANNEL + depends on BSP_I2C3_USING_DMA + int "Set I2C3 RX DMA channel (0-31)" + default 12 + + config BSP_I2C3_TX_DMA_CHANNEL + depends on BSP_I2C3_USING_DMA + int "Set I2C3 TX DMA channel (0-31)" + default 13 + endif + + config BSP_USING_I2C6 + bool "Enable I2C6 (LPI2C6)" + default n + + if BSP_USING_I2C6 + choice + prompt "Select I2C6 baudrate" + default HW_I2C6_BADURATE_100kHZ + + config HW_I2C6_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C6_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C6_USING_DMA + bool "Enable I2C6 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C6_RX_DMA_CHANNEL + depends on BSP_I2C6_USING_DMA + int "Set I2C6 RX DMA channel (0-31)" + default 14 + + config BSP_I2C6_TX_DMA_CHANNEL + depends on BSP_I2C6_USING_DMA + int "Set I2C6 TX DMA channel (0-31)" + default 15 + endif + endif + menuconfig BSP_USING_CAN bool "Enable CAN" select RT_USING_CAN @@ -438,7 +668,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_CAN config BSP_USING_CAN3 bool "Enable FLEXCAN3" - default n + default y endif menuconfig BSP_USING_FLEXSPI @@ -562,6 +792,12 @@ endmenu default n endif + config BSP_USING_QSPI_FLASH + bool "Enable QSPI Flash" + select BSP_USING_FLEXSPI + select BSP_USING_FLEXSPI1 + default n + endmenu menu "Board extended module Drivers" @@ -570,7 +806,7 @@ endmenu choice prompt "Linker Script Selection" - default BSP_LINKER_SCRIPT_RAM + default BSP_LINKER_SCRIPT_FLEXSPI_NOR help Select the linker script that matches your target memory configuration. diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c index 6fa3317b23..6da27f847a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c @@ -36,30 +36,18 @@ void BOARD_InitBootPins(void) BOARD_InitPins(); } -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} -- pin_list: - - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, - slew_rate: Slow} - - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, - slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. - * Description : Configures pin routing and optionally pin electrical features. + * Function Name : BOARD_InitLPUART1Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPUART1 (GPIO_AON_08/09). * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) +#ifdef BSP_USING_LPUART1 +void BOARD_InitLPUART1Pins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); -#ifdef BSP_USING_LPUART1 IOMUXC_SetPinMux( IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -80,9 +68,21 @@ void BOARD_InitPins(void) Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled */ -#endif +} +#endif /* BSP_USING_LPUART1 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPUART10Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPUART10 (GPIO_AD_32/33). + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_LPUART10 +void BOARD_InitLPUART10Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( IOMUXC_GPIO_AD_32_LPUART10_TX, /* GPIO_AD_32 is configured as LPUART10_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -103,9 +103,21 @@ void BOARD_InitPins(void) Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled */ -#endif +} +#endif /* BSP_USING_LPUART10 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPUART12Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPUART12 (GPIO_AON_19/20). + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_LPUART12 +void BOARD_InitLPUART12Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 is configured as LPUART12_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -126,9 +138,21 @@ void BOARD_InitPins(void) Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled */ -#endif +} +#endif /* BSP_USING_LPUART12 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPI2C2Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPI2C2 (GPIO_AON_15/16). + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_I2C2 +void BOARD_InitLPI2C2Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ @@ -147,27 +171,181 @@ void BOARD_InitPins(void) Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ -#endif +} +#endif /* BSP_USING_I2C2 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPI2C3Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPI2C3 (GPIO_AD_18/19). + * SCL -> GPIO_AD_18 (LPI2C3_SCL) + * SDA -> GPIO_AD_19 (LPI2C3_SDA) + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_I2C3 +void BOARD_InitLPI2C3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ + IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 is configured as LPI2C3_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_18 */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ + IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 is configured as LPI2C3_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_19 */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 PAD functional properties : */ 0x1DU); /* Slew Rate Field: Slow Slew Rate Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 PAD functional properties : */ 0x1DU); /* Slew Rate Field: Slow Slew Rate Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ +} +#endif /* BSP_USING_I2C3 */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPSPI3Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for LPSPI3 (GPIO_SD_B1_00..03). + * SCK -> GPIO_SD_B1_01 (LPSPI3_SCK) + * SOUT -> GPIO_SD_B1_02 (LPSPI3_SDO) + * SIN -> GPIO_SD_B1_03 (LPSPI3_SDI) + * PCS0 -> GPIO_SD_B1_00 (LPSPI3_PCS0, hardware CS, optional) + * + * END ****************************************************************************************************************/ +#ifdef BSP_USING_SPI3 +void BOARD_InitLPSPI3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + /* LPSPI3_SCK: GPIO_SD_B1_01, high driver */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK, 0x08U); + /* LPSPI3_SDO (SOUT/MOSI): GPIO_SD_B1_02, high driver + pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO, 0x04U); + /* LPSPI3_SDI (SIN/MISO): GPIO_SD_B1_03, high driver + pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI, 0x04U); + /* LPSPI3_PCS0 (hardware CS): GPIO_SD_B1_00, high driver */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0, 0x08U); +} +#endif /* BSP_USING_SPI3 */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCAN3Pins, assigned for the Cortex-M33 core. + * Description : Configures pin routing for CAN3. + * TX -> GPIO_AON_18 (CAN3_TX) + * RX -> GPIO_AON_03 (CAN3_RX) + * + * END ****************************************************************************************************************/ +#ifdef BSP_USING_CAN3 +void BOARD_InitCAN3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_18_CAN3_TX, /* GPIO_AON_18 is configured as CAN3_TX */ + 1U); /* Software Input On Field: Force input path */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_03_CAN3_RX, /* GPIO_AON_03 is configured as CAN3_RX */ + 1U); /* Software Input On Field: Force input path */ +} +#endif /* BSP_USING_CAN3 */ + +#ifdef BSP_USING_SDIO +void BOARD_InitSDIO1Pins(void) +{ + rgpio_pin_config_t pinCfg; + + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + /* SD_PWREN_B: GPIO_AD_14 -> RGPIO4_IO14, output low = card power on */ + pinCfg.pinDirection = kRGPIO_DigitalOutput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO4, 14U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_14_GPIO4_IO14, 0U); + + /* SD1_CD_B: GPIO_AD_15 -> RGPIO4_IO15, input (card detect) */ + pinCfg.pinDirection = kRGPIO_DigitalInput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO4, 15U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_15_GPIO4_IO15, 0U); + + /* VSELECT: GPIO_AD_34 -> GPIO5_IO02, output (voltage select) */ + pinCfg.pinDirection = kRGPIO_DigitalOutput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO5, 2U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_GPIO5_IO02, 0U); + + /* CMD: high driver, pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, 0x04U); + + /* CLK: high driver, no pull */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, 0x0CU); + + /* DATA0 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, 0x04U); + + /* DATA1 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, 0x04U); + + /* DATA2 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, 0x04U); + + /* DATA3 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, 0x04U); +} +#endif /* BSP_USING_SDIO */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : Calls peripheral-specific pin initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ +#ifdef BSP_USING_LPUART1 + BOARD_InitLPUART1Pins(); +#endif +#ifdef BSP_USING_LPUART10 + BOARD_InitLPUART10Pins(); +#endif +#ifdef BSP_USING_LPUART12 + BOARD_InitLPUART12Pins(); +#endif +#ifdef BSP_USING_I2C2 + BOARD_InitLPI2C2Pins(); +#endif +#ifdef BSP_USING_I2C3 + BOARD_InitLPI2C3Pins(); +#endif +#ifdef BSP_USING_SPI3 + BOARD_InitLPSPI3Pins(); +#endif +#ifdef BSP_USING_SDIO + BOARD_InitSDIO1Pins(); +#endif +#ifdef BSP_USING_CAN3 + BOARD_InitCAN3Pins(); #endif } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h index c2838ad1d2..3e81948d02 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h @@ -41,6 +41,34 @@ void BOARD_InitPins(void); /* Function assigned for the Corte void BOARD_InitLeds(void); +#ifdef BSP_USING_LPUART1 +void BOARD_InitLPUART1Pins(void); +#endif + +#ifdef BSP_USING_LPUART10 +void BOARD_InitLPUART10Pins(void); +#endif + +#ifdef BSP_USING_LPUART12 +void BOARD_InitLPUART12Pins(void); +#endif + +#ifdef BSP_USING_I2C2 +void BOARD_InitLPI2C2Pins(void); +#endif + +#ifdef BSP_USING_I2C3 +void BOARD_InitLPI2C3Pins(void); +#endif + +#ifdef BSP_USING_SPI3 +void BOARD_InitLPSPI3Pins(void); +#endif + +#ifdef BSP_USING_SDIO +void BOARD_InitSDIO1Pins(void); +#endif + #if defined(__cplusplus) } #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript index bc237a49c4..b5ab58e802 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript @@ -23,6 +23,9 @@ else: MCUX_Config/peripherals.c """) +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += ['ports/drv_flexspi_nor_flash.c'] + if GetDepend(['BSP_USING_QSPI_FLASH_FS']): src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c'] diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index 6ba6cab748..70b7b41b6b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -1500,24 +1500,21 @@ void rt_hw_board_init() extern void BOARD_InitPeripherals(void); BOARD_CommonSetting(); BOARD_ConfigMPU(); - BOARD_InitPins(); + BOARD_InitBootPins(); BOARD_BootClockRUN(); // BOARD_InitPeripherals(); NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - /*init uart device*/ - rt_hw_uart_init(); +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif - #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h index 82e65d68f3..64f627b4bc 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h @@ -30,7 +30,7 @@ #define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102 #endif #ifndef BOARD_DEBUG_UART_BASEADDR -#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#define BOARD_DEBUG_UART_BASEADDR (uint32_t)LPUART1 #endif #ifndef BOARD_DEBUG_UART_INSTANCE #define BOARD_DEBUG_UART_INSTANCE 1U @@ -88,7 +88,7 @@ #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO1_0_IRQHandler #define BOARD_USER_BUTTON_NAME "SW8" -#define BOARD_WAKEUP_BUTTON_NAME "SW4" +#define BOARD_WAKEUP_BUTTON_NAME "SW4" /*! @brief The board flash size */ #define BOARD_FLASH_SIZE (0x1000000U) @@ -167,17 +167,17 @@ void PHY_Reset(void); #if defined(__ARMCC_VERSION) extern int Image$$ARM_LIB_HEAP$$ZI$$Base; extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) -#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit) +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Limit) #elif defined(__ICCARM__) -#pragma section="HEAP" -#define HEAP_BEGIN (__section_begin("HEAP")) -#define HEAP_END (__section_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) #elif defined(__GNUC__) extern int __HeapBase; extern int __HeapLimit; -#define HEAP_BEGIN ((void *)&__HeapBase) -#define HEAP_END ((void *)&__HeapLimit) +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) #endif void rt_hw_board_init(void); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c index 60f31b39fd..eb43ad8da7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/drv_flexspi_nor_flash.c @@ -20,8 +20,8 @@ /* * Logging configuration */ -#define LOG_TAG "drv.flash" -#define LOG_LVL LOG_LVL_INFO +#define LOG_TAG "drv.flash" +#define LOG_LVL LOG_LVL_INFO #include <rtdbg.h> /* @@ -29,10 +29,10 @@ * FLASH_BUSY_STATUS_OFFSET = 0 : WIP bit is SR[0] * FLASH_QUAD_ENABLE = 0x40 : write to SR to enable Quad mode */ -#define FLASH_QUAD_ENABLE_VAL 0x40U +#define FLASH_QUAD_ENABLE_VAL 0x40U /* WIP polling upper limit to prevent infinite loop on Flash failure */ -#define WIP_TIMEOUT_COUNT 2000000UL +#define WIP_TIMEOUT_COUNT 2000000UL /* * Internal write buffer (must reside in SRAM) @@ -45,9 +45,9 @@ static uint8_t SDK_ALIGN(s_write_buf[QSPI_PAGE_SIZE], 4); /* Internal state */ -static imxrt_flexspi_handle_t *s_handle = RT_NULL; -static struct rt_mutex s_mutex; -static int s_inited = 0; +static imxrt_flexspi_handle_t *s_handle = RT_NULL; +static struct rt_mutex s_mutex; +static int s_inited = 0; /* * _range_valid - check whether [offset, offset+size) is within Flash @@ -109,10 +109,10 @@ static status_t _nor_write_enable(rt_uint32_t base_addr) flexspi_transfer_t xfer; xfer.deviceAddress = base_addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Command; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; return FLEXSPI_TransferBlocking(s_handle->base, &xfer); } @@ -125,19 +125,19 @@ static status_t _nor_write_enable(rt_uint32_t base_addr) */ static status_t _nor_wait_busy(void) { - rt_uint32_t read_val = 0; - rt_uint32_t timeout = 0; - status_t status; - rt_bool_t is_busy; + rt_uint32_t read_val = 0; + rt_uint32_t timeout = 0; + status_t status; + rt_bool_t is_busy; flexspi_transfer_t xfer; xfer.deviceAddress = 0; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Read; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; - xfer.data = &read_val; - xfer.dataSize = 1; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + xfer.data = &read_val; + xfer.dataSize = 1; do { @@ -161,8 +161,7 @@ static status_t _nor_wait_busy(void) { return kStatus_Timeout; } - } - while (is_busy); + } while (is_busy); return kStatus_Success; } @@ -174,17 +173,17 @@ static status_t _nor_wait_busy(void) */ static status_t _nor_erase_sector(rt_uint32_t addr) { - rt_base_t level; - status_t status; + rt_base_t level; + status_t status; flexspi_transfer_t xfer; level = rt_hw_interrupt_disable(); xfer.deviceAddress = addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Command; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Command; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -220,8 +219,8 @@ static status_t _nor_erase_sector(rt_uint32_t addr) */ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) { - rt_base_t level; - status_t status; + rt_base_t level; + status_t status; flexspi_transfer_t xfer; level = rt_hw_interrupt_disable(); @@ -241,12 +240,12 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) } xfer.deviceAddress = addr; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Write; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; - xfer.data = (rt_uint32_t *)src; - xfer.dataSize = QSPI_PAGE_SIZE; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Write; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + xfer.data = (rt_uint32_t *)src; + xfer.dataSize = QSPI_PAGE_SIZE; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -279,9 +278,9 @@ static status_t _nor_page_program(rt_uint32_t addr, const rt_uint32_t *src) */ int rt_qspi_flash_init(void) { - rt_uint8_t vendor_id = 0; - rt_uint32_t temp = 0; - status_t status; + rt_uint8_t vendor_id = 0; + rt_uint32_t temp = 0; + status_t status; flexspi_transfer_t xfer; if (s_inited) @@ -299,12 +298,12 @@ int rt_qspi_flash_init(void) /* Read Vendor ID to verify Flash connectivity (SDK: flexspi_nor_get_vendor_id) */ xfer.deviceAddress = 0; - xfer.port = FLASH_PORT; - xfer.cmdType = kFLEXSPI_Read; - xfer.SeqNumber = 1; - xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; - xfer.data = &temp; - xfer.dataSize = 1; + xfer.port = FLASH_PORT; + xfer.cmdType = kFLEXSPI_Read; + xfer.SeqNumber = 1; + xfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; + xfer.data = &temp; + xfer.dataSize = 1; status = FLEXSPI_TransferBlocking(s_handle->base, &xfer); if (status != kStatus_Success) @@ -410,7 +409,7 @@ void *rt_qspi_flash_mmap(rt_uint32_t offset, rt_size_t size) int rt_qspi_flash_write(rt_uint32_t offset, const rt_uint8_t *buf, rt_size_t size) { rt_size_t written = 0; - status_t status; + status_t status; if (!s_inited) { @@ -477,7 +476,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) { rt_uint32_t addr; rt_uint32_t addr_end; - status_t status; + status_t status; if (!s_inited) { @@ -496,7 +495,7 @@ int rt_qspi_flash_erase(rt_uint32_t offset, rt_size_t size) return -RT_EINVAL; } - addr = offset; + addr = offset; addr_end = offset + (rt_uint32_t)size; rt_mutex_take(&s_mutex, RT_WAITING_FOREVER); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c index ae1c3c4133..6cfdb9dc6f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/fal_flash_port.c @@ -17,8 +17,8 @@ /* * Logging configuration */ -#define LOG_TAG "fal.flash" -#define LOG_LVL LOG_LVL_INFO +#define LOG_TAG "fal.flash" +#define LOG_LVL LOG_LVL_INFO #include <rtdbg.h> /* FAL ops bridge */ @@ -44,13 +44,12 @@ static int _fal_erase(long offset, size_t size) return rt_qspi_flash_erase((rt_uint32_t)offset, size); } -const struct fal_flash_dev imxrt1180_nor_flash = -{ - .name = "norflash0", - .addr = QSPI_FLASH_BASE, - .len = QSPI_FLASH_SIZE, - .blk_size = QSPI_SECTOR_SIZE, - .ops = { _fal_init, _fal_read, _fal_write, _fal_erase }, +const struct fal_flash_dev imxrt1180_nor_flash = { + .name = "norflash0", + .addr = QSPI_FLASH_BASE, + .len = QSPI_FLASH_SIZE, + .blk_size = QSPI_SECTOR_SIZE, + .ops = { _fal_init, _fal_read, _fal_write, _fal_erase }, .write_gran = QSPI_PAGE_SIZE, }; diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/flexspi_port.h index dc7cb6c69e..6bd926af70 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/flexspi_port.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/ports/flexspi_port.h @@ -13,32 +13,39 @@ #define FLEXSPI_PORT_H__ /* parameters for flexpsi peripheral */ -#define FLEXSPI1_CONTROL_BASE FLEXSPI1 -#define FLEXSPI2_CONTROL_BASE FLEXSPI2 -#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/ -#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */ -#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ -#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ -#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ -#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ -#define ARD_SEQ_CMD 0xBB /* cmd for read */ -#define AWR_SEQ_CMD 0xAA /* cmd for write */ -#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad -#define FLASH_PORT kFLEXSPI_PortA1 -#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M -#define CLOCK_DIV 2U -#define CUSTOM_LUT_LENGTH 60U +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI2_CONTROL_BASE FLEXSPI2 +#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/ +#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */ +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ +#define ARD_SEQ_CMD 0xBB /* cmd for read */ +#define AWR_SEQ_CMD 0xAA /* cmd for write */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M +#define CLOCK_DIV 2U +#define CUSTOM_LUT_LENGTH 60U #define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U) #define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) -#define COMBINATION_MODE 0U -#define FREE_RUNNING_MODE 0U +#define COMBINATION_MODE 0U +#define FREE_RUNNING_MODE 0U -#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE -#define FLASH_PAGE_SIZE 256 -#define SECTOR_SIZE 0x1000 /* 4K */ -#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1 -#define FLASH_PORT kFLEXSPI_PortA1 +#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE +#define FLASH_PAGE_SIZE 256 +#define SECTOR_SIZE 0x1000 /* 4K */ +#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1 +#define FLASH_PORT kFLEXSPI_PortA1 + +/* DMA related. */ +#define FLEXSPI_DMA (DMA4) +#define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx +#define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx +#define FLEXSPI_TX_DMA_CHANNEL 0U +#define FLEXSPI_RX_DMA_CHANNEL 2U #define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 #define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h index 9e88a2b2dd..bbea69d06c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -151,6 +151,7 @@ #define RT_USING_SERIAL #define RT_USING_SERIAL_V2 #define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* end of Device Drivers */ @@ -420,9 +421,14 @@ /* On-chip Peripheral Drivers */ +#define BSP_USING_DMA #define BSP_USING_GPIO #define BSP_USING_LPUART #define BSP_USING_LPUART1 +#define BSP_LPUART1_RX_USING_DMA +#define BSP_LPUART1_RX_DMA_CHANNEL 0 +#define BSP_LPUART1_TX_USING_DMA +#define BSP_LPUART1_TX_DMA_CHANNEL 1 /* end of On-chip Peripheral Drivers */ /* Onboard Peripheral Drivers */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h index 9b73d5947c..c116c0037e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h @@ -62,22 +62,22 @@ typedef enum _FlashReadSampleClkSource { kFlexSPIReadSampleClk_LoopbackInternally = 0, kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_Reversed = 2, - kFlexSPIReadSampleClk_FlashProvidedDqs = 3, + kFlexSPIReadSampleClk_Reversed = 2, + kFlexSPIReadSampleClk_FlashProvidedDqs = 3, } flexspi_read_sample_clk_t; //!@brief Flash Type Definition enum { - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH }; //!@brief Flash Pad Definitions enum { - kSerialFlash_1Pad = 1, + kSerialFlash_1Pad = 1, kSerialFlash_2Pads = 2, kSerialFlash_4Pads = 4, kSerialFlash_8Pads = 8, @@ -86,10 +86,10 @@ enum //!@brief Definitions for FlexSPI Serial Clock Frequency typedef enum _FlexSpiSerialClockFreq { - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, kFlexSpiSerialClk_100MHz = 5, kFlexSpiSerialClk_120MHz = 6, kFlexSpiSerialClk_133MHz = 7, diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c index 773275023c..b62922b63e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c @@ -61,4 +61,4 @@ const container container_data = }; /* clang-format on */ -#endif
\ No newline at end of file +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml index be051e4a4a..f239d67b2b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -24,6 +24,37 @@ Peripheral.qspi_flash_FS: <<: *scons kconfig: - CONFIG_BSP_USING_QSPI_FLASH_FS=y +Peripheral.lpuart_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_LPUART=y + - CONFIG_BSP_USING_DMA=y +Peripheral.i2c_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_DMA=y +Peripheral.spi_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_DMA=y +Peripheral.can_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_CAN=y +Peripheral.rtc_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_RTC=y +Peripheral.dwt_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_DWT=y +Peripheral.sdio_device: + <<: *scons + kconfig: + - CONFIG_BSP_USING_SDCARD_FATFS=y Peripheral.usb_device: <<: *scons kconfig: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config index adda3dafdd..33552fce3a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -243,10 +243,11 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_ADC is not set @@ -1449,8 +1450,9 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y # # On-chip Peripheral Drivers # -# CONFIG_BSP_USING_DMA is not set -# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_DWT is not set +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_SDIO is not set @@ -1467,8 +1469,12 @@ CONFIG_BSP_USING_LPUART=y # CONFIG_BSP_USING_LPUART10 is not set # CONFIG_BSP_USING_LPUART11 is not set CONFIG_BSP_USING_LPUART12=y -# CONFIG_BSP_LPUART12_RX_USING_DMA is not set -# CONFIG_BSP_LPUART12_TX_USING_DMA is not set +CONFIG_BSP_LPUART12_RX_USING_DMA=y +CONFIG_BSP_LPUART12_RX_DMA_CHANNEL=22 +CONFIG_BSP_LPUART12_TX_USING_DMA=y +CONFIG_BSP_LPUART12_TX_DMA_CHANNEL=23 +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_FLEXSPI is not set # end of On-chip Peripheral Drivers @@ -1481,13 +1487,15 @@ CONFIG_BSP_USING_LPUART12=y # CONFIG_BSP_USING_ETHERCAT is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_FS is not set +# CONFIG_BSP_USING_QSPI_FLASH is not set +# CONFIG_BSP_USING_OSPI_FLASH is not set # end of Onboard Peripheral Drivers # # Board extended module Drivers # -CONFIG_BSP_LINKER_SCRIPT_RAM=y +# CONFIG_BSP_LINKER_SCRIPT_RAM is not set # CONFIG_BSP_LINKER_SCRIPT_HYPERRAM is not set -# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR is not set +CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y # CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c index 5ec32db446..402d422e29 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c @@ -9,6 +9,9 @@ */ #include <rtthread.h> +#define DBG_TAG "mnt" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> /* ==================================================================== * QSPI NOR Flash LittleFS (controlled by BSP_USING_QSPI_FLASH_FS) @@ -98,3 +101,30 @@ INIT_APP_EXPORT(_qspi_flash_fs_mount); INIT_COMPONENT_EXPORT(fal_init); #endif /* BSP_USING_QSPI_FLASH_FS */ + +#ifdef BSP_USING_SDCARD_FATFS +#include <dfs_fs.h> + +static int _sdcard_fs_mount(void) +{ + rt_tick_t start = rt_tick_get(); + while (rt_device_find("sd0") == RT_NULL) + { + if ((rt_tick_get() - start) > (5 * RT_TICK_PER_SECOND)) + { + LOG_E("wait for 'sd0' timeout"); + return -RT_ETIMEOUT; + } + rt_thread_mdelay(10); + } + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + LOG_E("sd0 mount to '/' failed! (ret=%d)", ret); + return ret; + } + LOG_I("sd0 mounted at '/'"); + return RT_EOK; +} +INIT_ENV_EXPORT(_sdcard_fs_mount); +#endif /* BSP_USING_SDCARD_FATFS */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig index 2c4c78b6a1..cdf8842e5a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -21,6 +21,14 @@ config SOC_MIMXRT1189CVM8C_CM7 menu "On-chip Peripheral Drivers" + config BSP_USING_DWT + bool "Enable DWT (cycle counter, us delay)" + default n + help + Enable the ARM DWT cycle counter for high-resolution timing and + busy-wait microsecond delays. Provides dwt_init(), dwt_get_cycles(), + dwt_cycles_to_us(), and dwt_delay_us(). + config BSP_USING_DMA bool "Enable DMA" default n @@ -431,6 +439,228 @@ menu "On-chip Peripheral Drivers" default 23 endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1 (LPI2C1)" + default n + + if BSP_USING_I2C1 + choice + prompt "Select I2C1 baudrate" + default HW_I2C1_BADURATE_100kHZ + + config HW_I2C1_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C1_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C1_RX_DMA_CHANNEL + depends on BSP_I2C1_USING_DMA + int "Set I2C1 RX DMA channel (0-31)" + default 8 + + config BSP_I2C1_TX_DMA_CHANNEL + depends on BSP_I2C1_USING_DMA + int "Set I2C1 TX DMA channel (0-31)" + default 9 + endif + + config BSP_USING_I2C2 + bool "Enable I2C2 (LPI2C2)" + default n + + if BSP_USING_I2C2 + choice + prompt "Select I2C2 baudrate" + default HW_I2C2_BADURATE_100kHZ + + config HW_I2C2_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C2_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C2_RX_DMA_CHANNEL + depends on BSP_I2C2_USING_DMA + int "Set I2C2 RX DMA channel (0-31)" + default 10 + + config BSP_I2C2_TX_DMA_CHANNEL + depends on BSP_I2C2_USING_DMA + int "Set I2C2 TX DMA channel (0-31)" + default 11 + endif + + config BSP_USING_I2C3 + bool "Enable I2C3 (LPI2C3)" + default n + + if BSP_USING_I2C3 + choice + prompt "Select I2C3 baudrate" + default HW_I2C3_BADURATE_100kHZ + + config HW_I2C3_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C3_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C3_RX_DMA_CHANNEL + depends on BSP_I2C3_USING_DMA + int "Set I2C3 RX DMA channel (0-31)" + default 12 + + config BSP_I2C3_TX_DMA_CHANNEL + depends on BSP_I2C3_USING_DMA + int "Set I2C3 TX DMA channel (0-31)" + default 13 + endif + + config BSP_USING_I2C6 + bool "Enable I2C6 (LPI2C6)" + default n + + if BSP_USING_I2C6 + choice + prompt "Select I2C6 baudrate" + default HW_I2C6_BADURATE_100kHZ + + config HW_I2C6_BADURATE_100kHZ + bool "Baudrate 100kHz" + + config HW_I2C6_BADURATE_400kHZ + bool "Baudrate 400kHz" + endchoice + + config BSP_I2C6_USING_DMA + bool "Enable I2C6 DMA" + select BSP_USING_DMA + default n + + config BSP_I2C6_RX_DMA_CHANNEL + depends on BSP_I2C6_USING_DMA + int "Set I2C6 RX DMA channel (0-31)" + default 14 + + config BSP_I2C6_TX_DMA_CHANNEL + depends on BSP_I2C6_USING_DMA + int "Set I2C6 TX DMA channel (0-31)" + default 15 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 (LPSPI1)" + default n + + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + depends on BSP_USING_SPI1 + select BSP_USING_DMA + default n + + config BSP_SPI1_RX_DMA_CHANNEL + depends on BSP_SPI1_USING_DMA + int "SPI1 RX DMA channel" + default 0 + + config BSP_SPI1_TX_DMA_CHANNEL + depends on BSP_SPI1_USING_DMA + int "SPI1 TX DMA channel" + default 1 + + config BSP_USING_SPI2 + bool "Enable SPI2 (LPSPI2)" + default n + + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + depends on BSP_USING_SPI2 + select BSP_USING_DMA + default n + + config BSP_SPI2_RX_DMA_CHANNEL + depends on BSP_SPI2_USING_DMA + int "SPI2 RX DMA channel" + default 2 + + config BSP_SPI2_TX_DMA_CHANNEL + depends on BSP_SPI2_USING_DMA + int "SPI2 TX DMA channel" + default 3 + + config BSP_USING_SPI3 + bool "Enable SPI3 (LPSPI3)" + default n + + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + depends on BSP_USING_SPI3 + select BSP_USING_DMA + default n + + config BSP_SPI3_RX_DMA_CHANNEL + depends on BSP_SPI3_USING_DMA + int "SPI3 RX DMA channel" + default 4 + + config BSP_SPI3_TX_DMA_CHANNEL + depends on BSP_SPI3_USING_DMA + int "SPI3 TX DMA channel" + default 5 + + config BSP_USING_SPI4 + bool "Enable SPI4 (LPSPI4)" + default n + + config BSP_SPI4_USING_DMA + bool "Enable SPI4 DMA" + depends on BSP_USING_SPI4 + select BSP_USING_DMA + default n + + config BSP_SPI4_RX_DMA_CHANNEL + depends on BSP_SPI4_USING_DMA + int "SPI4 RX DMA channel" + default 6 + + config BSP_SPI4_TX_DMA_CHANNEL + depends on BSP_SPI4_USING_DMA + int "SPI4 TX DMA channel" + default 7 + endif + menuconfig BSP_USING_CAN bool "Enable CAN" select RT_USING_CAN @@ -438,7 +668,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_CAN config BSP_USING_CAN3 bool "Enable FLEXCAN3" - default n + default y endif menuconfig BSP_USING_FLEXSPI @@ -521,7 +751,6 @@ menu "Onboard Peripheral Drivers" select RT_USING_LWIP default n - if BSP_USING_ETH config LWIP_SUPPORT_CUSTOM_PBUF int @@ -563,9 +792,16 @@ menu "Onboard Peripheral Drivers" default n endif + config BSP_USING_QSPI_FLASH + bool "Enable QSPI Flash" + select BSP_USING_FLEXSPI + select BSP_USING_FLEXSPI1 + default n + config BSP_USING_OSPI_FLASH bool "Enable HyperFlash Example" - depends on BSP_USING_FLEXSPI1 + select BSP_USING_FLEXSPI + select BSP_USING_FLEXSPI1 default n endmenu @@ -576,7 +812,7 @@ endmenu choice prompt "Linker Script Selection" - default BSP_LINKER_SCRIPT_RAM + default BSP_LINKER_SCRIPT_FLEXSPI_NOR help Select the linker script that matches your target memory configuration. diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c index a996efd45c..427894a6f9 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c @@ -34,26 +34,20 @@ processor_version: 0.15.9 void BOARD_InitBootPins(void) { BOARD_InitPins(); - -#ifdef BSP_USING_ETH - BOARD_InitPhyAccessPins(); - BOARD_InitEpPins(); - BOARD_InitSwtPort0Pins(); -#endif } /* FUNCTION ************************************************************************************************************ * - * Function Name : BOARD_InitPins, assigned for the Cortex-M7 core. - * Description : Configures pin routing and optionally pin electrical features. + * Function Name : BOARD_InitLPUART12Pins, assigned for the Cortex-M7 core. + * Description : Configures pin routing for LPUART12 (GPIO_AON_19/20). * * END ****************************************************************************************************************/ -void BOARD_InitPins(void) +#ifdef BSP_USING_LPUART12 +void BOARD_InitLPUART12Pins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ - CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); -#ifdef BSP_USING_LPUART12 IOMUXC_SetPinMux( IOMUXC_GPIO_AON_19_LPUART12_TX, /* GPIO_AON_19 is configured as LPUART12_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -74,9 +68,21 @@ void BOARD_InitPins(void) Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled */ -#endif +} +#endif /* BSP_USING_LPUART12 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPI2C2Pins, assigned for the Cortex-M7 core. + * Description : Configures pin routing for LPI2C2 (GPIO_AON_15/16). + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_I2C2 +void BOARD_InitLPI2C2Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ @@ -95,30 +101,149 @@ void BOARD_InitPins(void) Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ -#endif +} +#endif /* BSP_USING_I2C2 */ +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPI2C3Pins, assigned for the Cortex-M7 core. + * Description : Configures pin routing for LPI2C3 (GPIO_AD_18/19). + * SCL -> GPIO_AD_18 (LPI2C3_SCL) + * SDA -> GPIO_AD_19 (LPI2C3_SDA) + * + * END ****************************************************************************************************************/ #ifdef BSP_USING_I2C3 +void BOARD_InitLPI2C3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 is configured as LPI2C2_SCL */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_16 */ + IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 is configured as LPI2C3_SCL */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_18 */ IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 is configured as LPI2C2_SDA */ - 1U); /* Software Input On Field: Force input path of pad GPIO_AON_15 */ + IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 is configured as LPI2C3_SDA */ + 1U); /* Software Input On Field: Force input path of pad GPIO_AD_19 */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_16_LPI2C2_SCL, /* GPIO_AON_16 PAD functional properties : */ + IOMUXC_GPIO_AD_18_LPI2C3_SCL, /* GPIO_AD_18 PAD functional properties : */ 0x1DU); /* Slew Rate Field: Slow Slew Rate Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_15_LPI2C2_SDA, /* GPIO_AON_15 PAD functional properties : */ + IOMUXC_GPIO_AD_19_LPI2C3_SDA, /* GPIO_AD_19 PAD functional properties : */ 0x1DU); /* Slew Rate Field: Slow Slew Rate Pull Enable Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain Field: Enabled */ -#endif } +#endif /* BSP_USING_I2C3 */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLPSPI3Pins, assigned for the Cortex-M7 core. + * Description : Configures pin routing for LPSPI3 (GPIO_SD_B1_00..03). + * SCK -> GPIO_SD_B1_01 (LPSPI3_SCK) + * SOUT -> GPIO_SD_B1_02 (LPSPI3_SDO) + * SIN -> GPIO_SD_B1_03 (LPSPI3_SDI) + * PCS0 -> GPIO_SD_B1_00 (LPSPI3_PCS0, hardware CS, optional) + * + * END ****************************************************************************************************************/ +#ifdef BSP_USING_SPI3 +void BOARD_InitLPSPI3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + /* LPSPI3_SCK: GPIO_SD_B1_01, high driver */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_LPSPI3_SCK, 0x08U); + /* LPSPI3_SDO (SOUT/MOSI): GPIO_SD_B1_02, high driver + pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_LPSPI3_SDO, 0x04U); + /* LPSPI3_SDI (SIN/MISO): GPIO_SD_B1_03, high driver + pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_LPSPI3_SDI, 0x04U); + /* LPSPI3_PCS0 (hardware CS): GPIO_SD_B1_00, high driver */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_LPSPI3_PCS0, 0x08U); +} +#endif /* BSP_USING_SPI3 */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCAN3Pins, assigned for the Cortex-M7 core. + * Description : Configures pin routing for CAN3. + * TX -> GPIO_AON_18 (CAN3_TX) + * RX -> GPIO_AON_03 (CAN3_RX) + * + * END ****************************************************************************************************************/ +#ifdef BSP_USING_CAN3 +void BOARD_InitCAN3Pins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_18_CAN3_TX, /* GPIO_AON_18 is configured as CAN3_TX */ + 1U); /* Software Input On Field: Force input path */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_03_CAN3_RX, /* GPIO_AON_03 is configured as CAN3_RX */ + 1U); /* Software Input On Field: Force input path */ +} +#endif /* BSP_USING_CAN3 */ + +#ifdef BSP_USING_SDIO +void BOARD_InitSDIO1Pins(void) +{ + rgpio_pin_config_t pinCfg; + CLOCK_EnableClock(kCLOCK_Iomuxc1); + CLOCK_EnableClock(kCLOCK_Iomuxc2); + + /* SD_PWREN_B: GPIO_AD_14 -> RGPIO4_IO14, output low = card power on */ + pinCfg.pinDirection = kRGPIO_DigitalOutput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO4, 14U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_14_GPIO4_IO14, 0U); + + /* SD1_CD_B: GPIO_AD_15 -> RGPIO4_IO15, input (card detect) */ + pinCfg.pinDirection = kRGPIO_DigitalInput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO4, 15U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_15_GPIO4_IO15, 0U); + + /* VSELECT: GPIO_AD_34 -> GPIO5_IO02, output (voltage select) */ + pinCfg.pinDirection = kRGPIO_DigitalOutput; + pinCfg.outputLogic = 0U; + RGPIO_PinInit(RGPIO5, 2U, &pinCfg); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_GPIO5_IO02, 0U); + + /* CMD: high driver, pull-up */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, 0x04U); + + /* CLK: high driver, no pull */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, 0x0CU); + + /* DATA0 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, 0x04U); + + /* DATA1 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, 0x04U); + + /* DATA2 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, 0x04U); + + /* DATA3 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, 0x04U); +} +#endif /* BSP_USING_SDIO */ #ifdef BSP_USING_ETH /* @@ -569,6 +694,39 @@ void BOARD_InitSwtPort3Pins(void) } #endif +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M7 core. + * Description : Calls peripheral-specific pin initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ +#ifdef BSP_USING_LPUART12 + BOARD_InitLPUART12Pins(); +#endif +#ifdef BSP_USING_I2C2 + BOARD_InitLPI2C2Pins(); +#endif +#ifdef BSP_USING_I2C3 + BOARD_InitLPI2C3Pins(); +#endif +#ifdef BSP_USING_SPI3 + BOARD_InitLPSPI3Pins(); +#endif +#ifdef BSP_USING_SDIO + BOARD_InitSDIO1Pins(); +#endif +#ifdef BSP_USING_CAN3 + BOARD_InitCAN3Pins(); +#endif +#ifdef BSP_USING_ETH + BOARD_InitPhyAccessPins(); + BOARD_InitEpPins(); + BOARD_InitSwtPort0Pins(); +#endif +} + /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h index c09654d770..00144339a4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h @@ -37,7 +37,133 @@ void BOARD_InitBootPins(void); * @brief Configures pin routing and optionally pin electrical features. * */ -void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M7 */ + +#ifdef BSP_USING_LPUART12 +void BOARD_InitLPUART12Pins(void); +#endif + +#ifdef BSP_USING_I2C2 +void BOARD_InitLPI2C2Pins(void); +#endif + +#ifdef BSP_USING_I2C3 +void BOARD_InitLPI2C3Pins(void); +#endif + +#ifdef BSP_USING_SPI3 +void BOARD_InitLPSPI3Pins(void); +#endif + +#ifdef BSP_USING_SDIO +void BOARD_InitSDIO1Pins(void); +#endif + +#ifdef BSP_USING_ETH +/* GPIO_AD_25 (coord M15), ENET0_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_CHANNEL 25U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN 25U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET0_RST_B_GPIO_PIN_MASK (1U << 25U) /*!< GPIO pin mask */ + +/* GPIO_B1_13 (coord B11), ENET1_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_CHANNEL 13U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET1_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ + +/* GPIO_AD_28 (coord L16), ENET2_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_CHANNEL 28U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN 28U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET2_RST_B_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */ + +/* GPIO_B2_01 (coord E10), ENET3_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_PERIPHERAL RGPIO6 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_CHANNEL 15U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO RGPIO6 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN 15U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET3_RST_B_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */ + +/* GPIO_AD_13 (coord N15), ENET4_RST_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_CHANNEL 13U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN 13U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_RST_B_GPIO_PIN_MASK (1U << 13U) /*!< GPIO pin mask */ + +/* GPIO_AD_12 (coord P17), ENET4_INT_B */ +/* Routed pin properties */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_CHANNEL 12U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN 12U /*!< GPIO pin number */ +#define BOARD_INITPHYACCESSPINS_ENET4_INT_B_GPIO_PIN_MASK (1U << 12U) /*!< GPIO pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPhyAccessPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitEpPins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort0Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort1Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort2Pins(void); /* Function assigned for the Cortex-M33 */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSwtPort3Pins(void); /* Function assigned for the Cortex-M33 */ + +#endif + #ifdef BSP_USING_ETH /* GPIO_AD_25 (coord M15), ENET0_RST_B */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript index fc2d191f94..f9fa157f1a 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -21,6 +21,9 @@ else: MCUX_Config/pin_mux.c """) +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += ['ports/drv_flexspi_nor_flash.c'] + if GetDepend(['BSP_USING_QSPI_FLASH_FS']): src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c'] diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c index ffd577ad0a..c7f63b79af 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -1264,8 +1264,9 @@ void rt_hw_board_init() NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - /*init uart device*/ - rt_hw_uart_init(); +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); @@ -1280,8 +1281,6 @@ void rt_hw_board_init() rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n", HEAP_BEGIN, HEAP_END, (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); - - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c index cfd4d5f077..87a56b9a1b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c @@ -127,9 +127,9 @@ status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool en /* Write enable */ flashXfer.deviceAddress = baseAddr; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; if (enableOctal) { flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI; @@ -148,14 +148,14 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal) { /* Wait status ready. */ bool isBusy; - uint32_t readValue=0; + uint32_t readValue = 0; status_t status; flexspi_transfer_t flashXfer; flashXfer.deviceAddress = 0; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; if (enableOctal) { flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI; @@ -165,7 +165,7 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal) flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS; } - flashXfer.data = &readValue; + flashXfer.data = &readValue; flashXfer.dataSize = 1; do @@ -239,12 +239,12 @@ status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base) /* Enable quad mode. */ flashXfer.deviceAddress = 0; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI; - flashXfer.data = &writeValue; - flashXfer.dataSize = 1; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; status = FLEXSPI_TransferBlocking(base, &flashXfer); if (status != kStatus_Success) @@ -252,7 +252,7 @@ status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base) return status; } - status = flexspi_nor_wait_bus_busy(base, true); + status = flexspi_nor_wait_bus_busy(base, true); /* Do software reset. */ FLEXSPI_SoftwareReset(base); @@ -284,11 +284,11 @@ status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) } flashXfer.deviceAddress = address; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; - status = FLEXSPI_TransferBlocking(base, &flashXfer); + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); if (status != kStatus_Success) { @@ -331,17 +331,17 @@ status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, co /* Prepare page program command */ flashXfer.deviceAddress = dstAddr; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)src; - flashXfer.dataSize = FLASH_PAGE_SIZE; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; #ifdef BSP_USING_DMA g_completionFlag = false; - status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); + status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); #else - status = FLEXSPI_TransferBlocking(base, &flashXfer); + status = FLEXSPI_TransferBlocking(base, &flashXfer); #endif if (status != kStatus_Success) { @@ -373,14 +373,14 @@ status_t flexspi_nor_read_data(FLEXSPI_Type *base, uint32_t startAddress, uint32 /* Read page. */ flashXfer.deviceAddress = readAddress; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ; - flashXfer.data = buffer; - flashXfer.dataSize = length; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ; + flashXfer.data = buffer; + flashXfer.dataSize = length; #ifdef BSP_USING_DMA - g_completionFlag = false; + g_completionFlag = false; status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); @@ -406,14 +406,14 @@ status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) { /* Read manufacturer ID based on JEP106V spec, max continuation code table is 9, max manufacturer ID starts from * 9 + 1. */ - uint8_t id[10] = {0x00U}; + uint8_t id[10] = { 0x00U }; flexspi_transfer_t flashXfer; flashXfer.deviceAddress = 0; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID_OPI; - flashXfer.data = (uint32_t *)id; + flashXfer.data = (uint32_t *)id; flashXfer.dataSize = 10U; status_t status = FLEXSPI_TransferBlocking(base, &flashXfer); @@ -444,10 +444,10 @@ status_t flexspi_nor_erase_chip(FLEXSPI_Type *base) } flashXfer.deviceAddress = 0; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE; status = FLEXSPI_TransferBlocking(base, &flashXfer); @@ -486,18 +486,18 @@ status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const u /* Prepare page program command */ flashXfer.deviceAddress = dstAddr; - flashXfer.port = FLASH_PORT; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)src; - flashXfer.dataSize = length; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = length; #ifdef BSP_USING_DMA - g_completionFlag = false; + g_completionFlag = false; - status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); + status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); #else - status = FLEXSPI_TransferBlocking(base, &flashXfer); + status = FLEXSPI_TransferBlocking(base, &flashXfer); #endif if (status != kStatus_Success) { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h index eb1f073c69..3cea12172b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h @@ -18,7 +18,7 @@ #error "Please enable only one of BSP_USING_QSPI_FLASH_FS or BSP_USING_OSPI_FLASH" #endif -#if defined(BSP_USING_QSPI_FLASH_FS) +#if defined(BSP_USING_QSPI_FLASH_FS) || defined(BSP_USING_QSPI_FLASH) /* parameters for flexpsi peripheral */ #define FLEXSPI1_CONTROL_BASE FLEXSPI1 #define FLEXSPI2_CONTROL_BASE FLEXSPI2 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h index cf59d84e60..fe014c4513 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -152,8 +152,9 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* end of Device Drivers */ @@ -423,8 +424,14 @@ /* On-chip Peripheral Drivers */ +#define BSP_USING_DMA +#define BSP_USING_GPIO #define BSP_USING_LPUART #define BSP_USING_LPUART12 +#define BSP_LPUART12_RX_USING_DMA +#define BSP_LPUART12_RX_DMA_CHANNEL 22 +#define BSP_LPUART12_TX_USING_DMA +#define BSP_LPUART12_TX_DMA_CHANNEL 23 /* end of On-chip Peripheral Drivers */ /* Onboard Peripheral Drivers */ @@ -433,7 +440,7 @@ /* Board extended module Drivers */ -#define BSP_LINKER_SCRIPT_RAM +#define BSP_LINKER_SCRIPT_FLEXSPI_NOR /* end of Hardware Drivers Config */ #endif diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript index fd9034f2fb..a34644e64b 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript +++ b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript @@ -22,7 +22,10 @@ if GetDepend('BSP_USING_CLOCK_TIMER'): src += ['drv_timer.c'] if GetDepend('BSP_USING_RTC'): - src += ['drv_rtc.c'] + if GetDepend('SOC_IMXRT1180_SERIES'): + src += ['drv_rtc_bbnsm.c'] + else: + src += ['drv_rtc.c'] if GetDepend('BSP_USING_SPI'): src += ['drv_spi.c'] @@ -33,6 +36,9 @@ if GetDepend('BSP_USING_I2C'): if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] +if GetDepend('BSP_USING_DWT'): + src += ['drv_dwt.c'] + if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c index 519f21bfa1..918baca022 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c @@ -20,7 +20,7 @@ #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif -#define LOG_TAG "drv.adc" +#define LOG_TAG "drv.adc" #include <drv_log.h> #include "drv_adc.h" #include "fsl_adc.h" @@ -52,8 +52,7 @@ static rt_err_t imxrt_hp_adc_convert(struct rt_adc_device *device, rt_uint32_t c return RT_EOK; } -static struct rt_adc_ops imxrt_adc_ops = -{ +static struct rt_adc_ops imxrt_adc_ops = { .enabled = imxrt_hp_adc_enabled, .convert = imxrt_hp_adc_convert, }; diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_can.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_can.c index dc4840a22f..eb5d036ac0 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_can.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_can.c @@ -7,6 +7,7 @@ * Date Author Notes * 2019-06-27 misonyo the first version. * 2022-09-01 xjy198903 add support for imxrt1170 + * 2026-08-13 nxp-ran add support for imxrt1180 (SOC_IMXRT1180_SERIES) */ #include <rtthread.h> @@ -18,18 +19,18 @@ #include "fsl_iomuxc.h" #include "fsl_flexcan.h" -#define LOG_TAG "drv.can" +#define LOG_TAG "drv.can" #include <drv_log.h> #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif -#define RX_MB_COUNT 32 +#define RX_MB_COUNT 32 static flexcan_frame_t frame[RX_MB_COUNT]; /* one frame buffer per RX MB */ static rt_uint32_t filter_mask = 0; -#ifdef SOC_IMXRT1170_SERIES +#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) #define USE_IMPROVED_TIMING_CONFIG (1U) #endif @@ -55,8 +56,7 @@ struct imxrt_can struct rt_can_device can_dev; }; -struct imxrt_can flexcans[] = -{ +struct imxrt_can flexcans[] = { #ifdef BSP_USING_CAN1 { .name = "can1", @@ -83,30 +83,30 @@ struct imxrt_can flexcans[] = uint32_t GetCanSrcFreq(CAN_Type *can_base) { uint32_t freq; -#ifdef SOC_IMXRT1170_SERIES - uint32_t base = (uint32_t) can_base; +#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) + uint32_t base = (uint32_t)can_base; switch (base) - { - case CAN1_BASE: - freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can1) / 100000U) * 100000U; - break; - case CAN2_BASE: - freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can2) / 100000U) * 100000U; - break; - case CAN3_BASE: - freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U; - break; - default: - freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U; - break; - } + { + case CAN1_BASE: + freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can1) / 100000U) * 100000U; + break; + case CAN2_BASE: + freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can2) / 100000U) * 100000U; + break; + case CAN3_BASE: + freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U; + break; + default: + freq = (CLOCK_GetRootClockFreq(kCLOCK_Root_Can3) / 100000U) * 100000U; + break; + } #else freq = (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 6) / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1U); #endif return freq; } -#ifdef SOC_IMXRT1170_SERIES +#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData) #else static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData) @@ -179,13 +179,13 @@ static rt_err_t can_cfg(struct rt_can_device *can_dev, struct can_configure *cfg break; } -#ifdef SOC_IMXRT1170_SERIES +#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) flexcan_timing_config_t timing_config; rt_memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); - if(FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, GetCanSrcFreq(can->base), &timing_config)) + if (FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, GetCanSrcFreq(can->base), &timing_config)) { - /* Update the improved timing configuration*/ + /* Update the improved timing configuration */ rt_memcpy(&(config.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); } else @@ -222,7 +222,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg) rt_uint32_t argval, mask; rt_uint32_t res = RT_EOK; flexcan_rx_mb_config_t mbConfig; - struct rt_can_filter_config *cfg; + struct rt_can_filter_config *cfg; struct rt_can_filter_item *item; rt_uint8_t i, count, index; @@ -234,7 +234,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg) switch (cmd) { case RT_DEVICE_CTRL_SET_INT: - argval = (rt_uint32_t) arg; + argval = (rt_uint32_t)arg; if (argval == RT_DEVICE_FLAG_INT_RX) { mask = kFLEXCAN_RxWarningInterruptEnable; @@ -302,10 +302,9 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg) /* user does not specify hdr index,set hdr_bank from RX MB 1 */ if (item->hdr_bank == -1) { - for (i = 0; i < 32; i++) { - if (!(filter_mask & (1 << i))) + if (!(filter_mask & (1U << i))) { index = i; break; @@ -314,7 +313,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg) } else /* use user specified hdr_bank */ { - if (filter_mask & (1 << item->hdr_bank)) + if (filter_mask & (1U << item->hdr_bank)) { res = -RT_ERROR; LOG_E("%s hdr%d filter already set!\n", can->name, item->hdr_bank); @@ -329,7 +328,7 @@ static rt_err_t can_control(struct rt_can_device *can_dev, int cmd, void *arg) /* RX MB index from 1 to 32,hdr index 0~31 map RX MB index 1~32. */ FLEXCAN_SetRxIndividualMask(can->base, index + 1, mask); FLEXCAN_SetRxMbConfig(can->base, index + 1, &mbConfig, true); - filter_mask |= 1 << index; + filter_mask |= 1U << index; item++; count--; @@ -372,7 +371,7 @@ static rt_ssize_t can_send(struct rt_can_device *can_dev, const void *buf, rt_ui RT_ASSERT(buf != RT_NULL); can = (struct imxrt_can *)can_dev->parent.user_data; - msg = (struct rt_can_msg *) buf; + msg = (struct rt_can_msg *)buf; RT_ASSERT(can != RT_NULL); RT_ASSERT(msg != RT_NULL); @@ -439,7 +438,7 @@ static rt_ssize_t can_recv(struct rt_can_device *can_dev, void *buf, rt_uint32_t RT_ASSERT(can_dev != RT_NULL); can = (struct imxrt_can *)can_dev->parent.user_data; - pmsg = (struct rt_can_msg *) buf; + pmsg = (struct rt_can_msg *)buf; RT_ASSERT(can != RT_NULL); index = boxno - 1; @@ -477,12 +476,11 @@ static rt_ssize_t can_recv(struct rt_can_device *can_dev, void *buf, rt_uint32_t return 0; } -static struct rt_can_ops imxrt_can_ops = -{ - .configure = can_cfg, - .control = can_control, - .sendmsg = can_send, - .recvmsg = can_recv, +static struct rt_can_ops imxrt_can_ops = { + .configure = can_cfg, + .control = can_control, + .sendmsg = can_send, + .recvmsg = can_recv, }; int rt_hw_can_init(void) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.c new file mode 100644 index 0000000000..91bd5c2ecb --- /dev/null +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-01 RTT the first version, generic i.MX RT DWT driver + */ + +#include "drv_dwt.h" + +#ifdef BSP_USING_DWT + +#include <rtthread.h> + +/* CMSIS standard variable updated by SystemCoreClockUpdate() in the SDK's + * system_<device>.c. Declared extern here to stay device-family-agnostic. */ +extern uint32_t SystemCoreClock; + +/* CoreDebug and DWT register base addresses (Cortex-M, ARMv7-M / ARMv8-M) */ +#define DWT_CTRL (*(volatile rt_uint32_t *)0xE0001000UL) /* DWT Control */ +#define DWT_CYCCNT (*(volatile rt_uint32_t *)0xE0001004UL) /* Cycle Count */ +#define CoreDebug_DEMCR (*(volatile rt_uint32_t *)0xE000EDFCUL) /* DEMCR */ + +/* DEMCR: enable DWT and ITM trace */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24) +/* DWT_CTRL: enable cycle counter */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL << 0) +/* DWT_CTRL: NOCYCCNT - set if the cycle counter is not implemented */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << 25) + +/** + * Initialize the DWT cycle counter. + */ +rt_err_t dwt_init(void) +{ + /* Enable DWT trace by setting TRCENA in DEMCR */ + CoreDebug_DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + /* Check that the cycle counter is implemented on this device */ + if (DWT_CTRL & DWT_CTRL_NOCYCCNT_Msk) + { + return -RT_ERROR; + } + + /* Reset then enable the cycle counter */ + DWT_CYCCNT = 0U; + DWT_CTRL |= DWT_CTRL_CYCCNTENA_Msk; + + return RT_EOK; +} + +/** + * Read the current DWT cycle counter value. + */ +rt_uint32_t dwt_get_cycles(void) +{ + return DWT_CYCCNT; +} + +/** + * Convert a cycle count to microseconds using SystemCoreClock. + */ +rt_uint32_t dwt_cycles_to_us(rt_uint32_t cycles) +{ + return (rt_uint32_t)((rt_uint64_t)cycles * 1000000UL / SystemCoreClock); +} + +/** + * Busy-wait for the requested number of microseconds. + */ +void dwt_delay_us(rt_uint32_t us) +{ + rt_uint32_t start = DWT_CYCCNT; + rt_uint32_t ticks = (rt_uint32_t)((rt_uint64_t)us * SystemCoreClock / 1000000UL); + + /* Unsigned subtraction handles counter wrap-around correctly */ + while ((DWT_CYCCNT - start) < ticks) + { + /* busy wait */ + } +} + +#ifdef RT_USING_FINSH +#include <finsh.h> + +/** + * MSH command: dwt_test + * Tests the DWT cycle counter by measuring rt_thread_mdelay(100) and + * a 200 us busy-wait delay, then prints the results over the console. + */ +static void dwt_test(int argc, char **argv) +{ + rt_uint32_t t0, t1, elapsed_us; + + if (dwt_init() != RT_EOK) + { + rt_kprintf("[DWT] init FAILED: cycle counter not implemented on this device\r\n"); + return; + } + rt_kprintf("[DWT] init OK, cycle counter started\r\n"); + + /* test 1: measure a 100 ms OS delay */ + t0 = dwt_get_cycles(); + rt_thread_mdelay(100); + t1 = dwt_get_cycles(); + elapsed_us = dwt_cycles_to_us(t1 - t0); + rt_kprintf("[DWT] rt_thread_mdelay(100) took %u us\r\n", elapsed_us); + + /* test 2: busy-wait 200 us and measure it back */ + t0 = dwt_get_cycles(); + dwt_delay_us(200); + t1 = dwt_get_cycles(); + elapsed_us = dwt_cycles_to_us(t1 - t0); + rt_kprintf("[DWT] dwt_delay_us(200) measured %u us\r\n", elapsed_us); +} +MSH_CMD_EXPORT(dwt_test, test DWT cycle counter and us delay); + +#endif /* RT_USING_FINSH */ + +#endif /* BSP_USING_DWT */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.h new file mode 100644 index 0000000000..a8592dccc8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_dwt.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-01 RTT the first version, generic i.MX RT DWT driver + */ + +#ifndef DRV_DWT_H__ +#define DRV_DWT_H__ + +#include <rtthread.h> +#include <stdint.h> + +#ifdef BSP_USING_DWT + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize the DWT cycle counter. + * Enables the CoreDebug trace and sets CYCCNTENA in DWT_CTRL. + * Must be called before using any other dwt_* functions. + * + * @return RT_EOK on success, -RT_ERROR if DWT is not available. + */ +rt_err_t dwt_init(void); + +/** + * Read the current DWT cycle counter value. + * + * @return 32-bit free-running cycle count. Wraps around after 2^32 cycles. + */ +rt_uint32_t dwt_get_cycles(void); + +/** + * Convert a DWT cycle count difference to microseconds. + * Uses the CMSIS SystemCoreClock variable for the conversion. + * + * @param cycles number of cycles to convert + * @return elapsed time in microseconds + */ +rt_uint32_t dwt_cycles_to_us(rt_uint32_t cycles); + +/** + * Busy-wait delay using the DWT cycle counter. + * dwt_init() must have been called before using this function. + * + * @param us delay duration in microseconds + */ +void dwt_delay_us(rt_uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_USING_DWT */ + +#endif /* DRV_DWT_H__ */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c index c1ab4b66d6..8e1b3b9974 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c @@ -49,25 +49,25 @@ static void flexspi_callback(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, #endif #define FLEXSPI_DEBUG -#define LOG_TAG "drv.flexspi" +#define LOG_TAG "drv.flexspi" #include <drv_log.h> #if defined(SOC_IMXRT1170_SERIES) static flexspi_device_config_t deviceconfig = { - .flexspiRootClk = 12000000, - .flashSize = FLASH_SIZE, - .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, - .CSInterval = 2, - .CSHoldTime = 3, - .CSSetupTime = 3, - .dataValidTime = 0, - .columnspace = 0, - .enableWordAddress = 0, - .AWRSeqIndex = AWR_SEQ_INDEX, - .AWRSeqNumber = AWR_SEQ_NUMBER, - .ARDSeqIndex = ARD_SEQ_INDEX, - .ARDSeqNumber = ARD_SEQ_NUMBER, - .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .flexspiRootClk = 12000000, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = AWR_SEQ_INDEX, + .AWRSeqNumber = AWR_SEQ_NUMBER, + .ARDSeqIndex = ARD_SEQ_INDEX, + .ARDSeqNumber = ARD_SEQ_NUMBER, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 0, }; const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { @@ -78,157 +78,157 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { #elif defined(SOC_IMXRT1180_SERIES) static flexspi_device_config_t deviceconfig = { #ifndef BSP_USING_OSPI_FLASH - .flexspiRootClk = 12000000, + .flexspiRootClk = 12000000, #else - .flexspiRootClk = 200000000, + .flexspiRootClk = 200000000, #endif - .flashSize = FLASH_SIZE, - .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, - .CSInterval = 2, - .CSHoldTime = 3, - .CSSetupTime = 3, - .dataValidTime = 0, - .columnspace = 0, - .enableWordAddress = 0, - .AWRSeqIndex = AWR_SEQ_INDEX, - .AWRSeqNumber = AWR_SEQ_NUMBER, - .ARDSeqIndex = ARD_SEQ_INDEX, - .ARDSeqNumber = ARD_SEQ_NUMBER, - .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = AWR_SEQ_INDEX, + .AWRSeqNumber = AWR_SEQ_NUMBER, + .ARDSeqIndex = ARD_SEQ_INDEX, + .ARDSeqNumber = ARD_SEQ_NUMBER, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 0, }; const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { -#ifndef BSP_USING_OSPI_FLASH +#ifndef BSP_USING_OSPI_FLASH /* Normal read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, - kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), /* Fast read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, - kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), /* Fast read quad mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, - kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), + kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), /* Write Enable */ [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, - kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), /* Erase Sector */ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), /* Page Program - single mode */ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, - kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), /* Page Program - quad mode */ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, - kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, - kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), /* Read ID */ [4 * NOR_CMD_LUT_SEQ_IDX_READID] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, - kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, + kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), /* Write Status Register */ [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, - kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, + kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), /* Read status register */ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, - kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, + kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), /* Erase whole chip */ [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, - kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), #else - /* OPI DDR read */ + /* OPI DDR read */ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 0] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC), - [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x20), [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), /* Read ID */ [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F), [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), /* Write Enable */ [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06), /* Erase Sector */ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21), [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0), /* Erase Chip */ [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4), [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0), /* Program */ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E), - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04), /* Dummy write, do nothing when AHB write command is triggered. */ [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), /* Read status register using Octal DDR read */ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), #endif }; @@ -239,10 +239,9 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* -------------------------------------------------------------------------- * Internal handle * -------------------------------------------------------------------------- */ -static imxrt_flexspi_handle_t s_flexspi_handle = -{ - .base = FLEXSPI1_CONTROL_BASE, - .port = FLASH_PORT, +static imxrt_flexspi_handle_t s_flexspi_handle = { + .base = FLEXSPI1_CONTROL_BASE, + .port = FLASH_PORT, .ahb_base = FLEXSPI1_AHB_DATA_ADDRESS }; @@ -265,22 +264,22 @@ static int rt_hw_imxrt_flexspi_init(void) #ifdef BSP_USING_FLEXSPI1 base = FLEXSPI1_CONTROL_BASE; - s_flexspi_handle.base = FLEXSPI1_CONTROL_BASE; - s_flexspi_handle.port = FLASH_PORT; + s_flexspi_handle.base = FLEXSPI1_CONTROL_BASE; + s_flexspi_handle.port = FLASH_PORT; s_flexspi_handle.ahb_base = FLEXSPI1_AHB_DATA_ADDRESS; //Set root clk 80MHz for QSPI, 200MHz for OSPI flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV); #else base = FLEXSPI2_CONTROL_BASE; - s_flexspi_handle.base = FLEXSPI2_CONTROL_BASE; - s_flexspi_handle.port = FLASH_PORT; + s_flexspi_handle.base = FLEXSPI2_CONTROL_BASE; + s_flexspi_handle.port = FLASH_PORT; s_flexspi_handle.ahb_base = FLEXSPI2_AHB_DATA_ADDRESS; flexspi_clock_init(kCLOCK_Root_Flexspi2, CLOCK_SRC, CLOCK_DIV); #endif #ifdef BSP_USING_DMA edma_config_t userConfig; - edma_handle_t dmaTxHandle; + edma_handle_t dmaTxHandle; edma_handle_t dmaRxHandle; /* EDMA init */ @@ -311,13 +310,13 @@ static int rt_hw_imxrt_flexspi_init(void) config.ahbConfig.enableAHBBufferable = true; config.ahbConfig.enableReadAddressOpt = true; config.ahbConfig.enableAHBCachable = true; - config.ahbConfig.enableClearAHBBufferOpt = true; + config.ahbConfig.enableClearAHBBufferOpt = true; config.rxSampleClock = FLEXSPI_RX_SAMPLE_CLOCK; - if(COMBINATION_MODE) + if (COMBINATION_MODE) { config.enableCombination = true; } - if(FREE_RUNNING_MODE) + if (FREE_RUNNING_MODE) { config.enableSckFreeRunning = true; } @@ -347,7 +346,7 @@ INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init); #ifndef BSP_USING_OSPI_FLASH #define FLEXSPI_DATALEN 4U -static rt_uint32_t send_buf[FLEXSPI_DATALEN] = {0x11223344, 0x55667788, 0x12345678, 0x9900aabb}; +static rt_uint32_t send_buf[FLEXSPI_DATALEN] = { 0x11223344, 0x55667788, 0x12345678, 0x9900aabb }; static uint32_t recv_buf[FLEXSPI_DATALEN]; /* read write 32bit test */ @@ -379,7 +378,7 @@ static void flexspi_test(void) #else -#define EXAMPLE_SECTOR 20 +#define EXAMPLE_SECTOR 20 /******************************************************************************* * Variables ******************************************************************************/ @@ -410,12 +409,12 @@ static void flexspi_test(void) status = flexspi_nor_enable_octal_mode(FLEXSPI1_CONTROL_BASE); if (status != kStatus_Success) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Enable octal mode failure ! -- DMA mode\r\n"); - #else +#else LOG_E("Enable octal mode failure !\r\n"); - #endif - return ; +#endif + return; } #ifdef BSP_USING_DMA LOG_W("Enabled octal mode. -- DMA mode\r\n"); @@ -428,12 +427,12 @@ static void flexspi_test(void) status = flexspi_nor_get_vendor_id(FLEXSPI1_CONTROL_BASE, &vendorID); if (status != kStatus_Success) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Get vendor id failure ! -- DMA mode\r\n"); - #else +#else LOG_E("Get vendor id failure !\r\n"); - #endif - return ; +#endif + return; } #ifdef BSP_USING_DMA LOG_W("Vendor ID: 0x%x -- DMA mode\r\n", vendorID); @@ -448,12 +447,12 @@ static void flexspi_test(void) status = flexspi_nor_flash_erase_sector(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE); if (status != kStatus_Success) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Erase sector failure ! -- DMA mode\r\n"); - #else +#else LOG_E("Erase sector failure !\r\n"); - #endif - return ; +#endif + return; } #if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN @@ -466,20 +465,20 @@ static void flexspi_test(void) if (memcmp(s_nor_program_buffer, s_nor_read_buffer, sizeof(s_nor_program_buffer))) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Erase data - read out data value incorrect ! -- DMA mode\r\n "); - #else +#else LOG_E("Erase data - read out data value incorrect !\r\n "); - #endif - return ; +#endif + return; } else { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_W("Erase data - successfully. -- DMA mode\r\n"); - #else +#else LOG_W("Erase data - successfully. \r\n"); - #endif +#endif } for (i = 0; i < 0xFFU; i++) @@ -491,12 +490,12 @@ static void flexspi_test(void) flexspi_nor_flash_page_program(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE, (void *)s_nor_program_buffer); if (status != kStatus_Success) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Page program failure ! -- DMA mode\r\n"); - #else +#else LOG_E("Page program failure !\r\n"); - #endif - return ; +#endif + return; } #if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN @@ -508,22 +507,21 @@ static void flexspi_test(void) if (memcmp(s_nor_read_buffer, s_nor_program_buffer, sizeof(s_nor_program_buffer)) != 0) { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_E("Program data - read out data value incorrect ! -- DMA mode\r\n "); - #else +#else LOG_E("Program data - read out data value incorrect !\r\n "); - #endif - return ; +#endif + return; } else { - #ifdef BSP_USING_DMA +#ifdef BSP_USING_DMA LOG_W("Program data - successfully. -- DMA mode\r\n"); - #else +#else LOG_W("Program data - successfully. \r\n"); - #endif +#endif } - } #endif MSH_CMD_EXPORT(flexspi_test, flexspi test) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.h index d72df3481a..9d1152cb42 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.h +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.h @@ -20,20 +20,20 @@ extern "C" { /* Put critical transfer code into ITCM (Code TCM) */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) -#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) +#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) #elif defined(__GNUC__) -#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) +#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline)) #elif defined(__ICCARM__) -#define FLEXSPI_RAM_CODE __ramfunc +#define FLEXSPI_RAM_CODE __ramfunc #else #define FLEXSPI_RAM_CODE #endif typedef struct { - FLEXSPI_Type *base; - flexspi_port_t port; - uint32_t ahb_base; + FLEXSPI_Type *base; + flexspi_port_t port; + uint32_t ahb_base; } imxrt_flexspi_handle_t; /* Get initialized FlexSPI handle (FlexSPI1 or FlexSPI2 decided by BSP config) */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c index fbd075b39a..ed14696302 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c @@ -23,7 +23,7 @@ #endif #include "fsl_iomuxc.h" -#define LOG_TAG "drv.gpio" +#define LOG_TAG "drv.gpio" #include <drv_log.h> #ifdef SOC_IMXRT1180_SERIES @@ -36,7 +36,7 @@ #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif -#define __IMXRT_HDR_DEFAULT {-1, 0, RT_NULL, RT_NULL} +#define __IMXRT_HDR_DEFAULT { -1, 0, RT_NULL, RT_NULL } #if defined(SOC_IMXRT1170_SERIES) #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 7) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0) @@ -47,28 +47,28 @@ #endif #if defined(SOC_IMXRT1015_SERIES) -#define MUX_BASE 0x401f8024 -#define CONFIG_BASE 0x401f8198 +#define MUX_BASE 0x401f8024 +#define CONFIG_BASE 0x401f8198 #elif defined(SOC_IMXRT1020_SERIES) -#define MUX_BASE 0x401f8014 -#define CONFIG_BASE 0x401f8188 +#define MUX_BASE 0x401f8014 +#define CONFIG_BASE 0x401f8188 #elif defined(SOC_IMXRT1170_SERIES) -#define MUX_BASE 0x400E8010 -#define CONFIG_BASE 0x400E8254 +#define MUX_BASE 0x400E8010 +#define CONFIG_BASE 0x400E8254 #elif defined(SOC_IMXRT1180_SERIES) #define MUX_BASE (IOMUXC_BASE + 0x10u) #define CONFIG_BASE (IOMUXC_BASE + 0x258u) #else /* 1050 & 1060 & 1064 series*/ -#define MUX_BASE 0x401f8014 -#define CONFIG_BASE 0x401f8204 +#define MUX_BASE 0x401f8014 +#define CONFIG_BASE 0x401f8204 #endif -#define GPIO5_MUX_BASE 0x400A8000 -#define GPIO5_CONFIG_BASE 0x400A8018 -#define GPIO6_MUX_BASE 0x40C08000 -#define GPIO6_CONFIG_BASE 0x40C08040 -#define GPIO13_MUX_BASE 0x40C94000 -#define GPIO13_CONFIG_BASE 0x40C94040 +#define GPIO5_MUX_BASE 0x400A8000 +#define GPIO5_CONFIG_BASE 0x400A8018 +#define GPIO6_MUX_BASE 0x40C08000 +#define GPIO6_CONFIG_BASE 0x40C08040 +#define GPIO13_MUX_BASE 0x40C94000 +#define GPIO13_CONFIG_BASE 0x40C94040 #if defined(SOC_IMXRT1180_SERIES) #define AON_MUX_BASE (IOMUXC_AON_BASE) @@ -80,9 +80,9 @@ struct pin_mask #if defined(SOC_IMXRT1180_SERIES) RGPIO_Type *gpio; #else - GPIO_Type *gpio; + GPIO_Type *gpio; #endif - rt_int32_t valid_mask; + rt_int32_t valid_mask; }; #if defined(SOC_IMXRT1170_SERIES) @@ -130,22 +130,363 @@ const struct pin_mask mask_tab[5] = }; -const rt_int32_t reg_offset[] = -{ +/* clang-format off */ +const rt_int32_t reg_offset[] = { #if defined(SOC_IMXRT1015_SERIES) - 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 64, 65, 66, 67, 68, 69, - -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, -1, -1, -1, -1, - 28, 29, 30, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + 64, + 65, + 66, + 67, + 68, + 69, + -1, + -1, + -1, + -1, + 0, + 1, + 2, + 3, + 4, + 5, + -1, + -1, + -1, + -1, + -1, + -1, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + -1, + -1, + -1, + -1, + 28, + 29, + 30, + 31, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, #elif defined(SOC_IMXRT1020_SERIES) - 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + -1, + -1, + -1, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, #elif defined(SOC_IMXRT1170_SERIES) - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, - 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, - 128,129, 130,131,132,133,134,135,136,137,138,139,140,141,142,143,144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127, + 128, + 129, + 130, + 131, + 132, + 133, + 134, + 135, + 136, + 137, + 138, + 139, + 140, + 141, + 142, + 143, + 144, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, #elif defined(SOC_IMXRT1180_SERIES) /* GPIO1 (AON domain) */ 0, @@ -346,13 +687,138 @@ const rt_int32_t reg_offset[] = -1, -1, #else /* 1050 & 1060 & 1064 series*/ - 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, - 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, - 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1, - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 106, + 107, + 108, + 109, + 110, + 111, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + -1, + -1, + -1, + -1, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, #endif }; +/* clang-format on */ static const IRQn_Type irq_tab[] = { #if defined(SOC_IMXRT1180_SERIES) @@ -857,7 +1323,7 @@ static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *b pin_end = pin_start + 15; isr_status = GPIO_PortGetInterruptFlags(base) & base->IMR; - for (i = pin_start; i <= pin_end ; i++) + for (i = pin_start; i <= pin_end; i++) { if (isr_status & (1 << i)) { @@ -1077,7 +1543,7 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return; } @@ -1223,7 +1689,7 @@ static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return -RT_EINVAL; } @@ -1243,7 +1709,7 @@ static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return; } @@ -1265,7 +1731,7 @@ static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin, if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return -RT_ENOSYS; } @@ -1279,8 +1745,8 @@ static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin, return RT_EOK; } - hdr_tab[pin].pin = pin; - hdr_tab[pin].hdr = hdr; + hdr_tab[pin].pin = pin; + hdr_tab[pin].hdr = hdr; hdr_tab[pin].mode = mode; hdr_tab[pin].args = args; rt_hw_interrupt_enable(level); @@ -1298,7 +1764,7 @@ static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_base_t pin) if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return -RT_ENOSYS; } @@ -1326,7 +1792,7 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt if (PIN_INVALID_CHECK(port, pin_num)) { - LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); + LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin, port + 1, pin_num); return -RT_ENOSYS; } @@ -1477,8 +1943,7 @@ static rt_base_t imxrt_pin_get(const char *name) return pin; } -const static struct rt_pin_ops imxrt_pin_ops = -{ +const static struct rt_pin_ops imxrt_pin_ops = { imxrt_pin_mode, imxrt_pin_write, imxrt_pin_read, diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.h index 0ea8ead068..5cf86ea011 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.h +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.h @@ -14,7 +14,7 @@ #include <rtthread.h> #include <rtdevice.h> -#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ +#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ int rt_hw_pin_init(void); diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_i2c.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_i2c.c index a953e9a6ca..ee730b3e08 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_i2c.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_i2c.c @@ -8,6 +8,7 @@ * 2017-08-08 Yang the first version * 2018-03-24 LaiYiKeTang add hardware iic * 2019-04-22 tyustli add imxrt series support + * 2026-08-13 Ran add RT1180 CM33 DMA support * */ @@ -15,17 +16,40 @@ #ifdef BSP_USING_I2C -#define LOG_TAG "drv.i2c" +#define LOG_TAG "drv.i2c" #include <drv_log.h> -#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) && !defined(BSP_USING_I2C5)&& !defined(BSP_USING_I2C6) -#error "Please define at least one BSP_USING_I2Cx" -#endif - #include <rtdevice.h> #include "fsl_lpi2c.h" +#ifdef SOC_IMXRT1180_SERIES +#include "fsl_lpi2c_edma.h" +#endif #include "drv_i2c.h" +#ifdef SOC_IMXRT1180_SERIES +struct i2c_dma_config +{ + lpi2c_master_edma_handle_t i2c_edma; + + edma_handle_t rx_edma; + dma_request_source_t rx_request; + rt_uint8_t rx_channel; + + edma_handle_t tx_edma; + dma_request_source_t tx_request; + rt_uint8_t tx_channel; + + EDMA_Type *edma_base; + volatile status_t last_status; /* completion status from DMA callback */ + + /* rx_offset: number of leading bytes to skip in the RX bounce buffer. + * DMA3 (AON domain, LPI2C1/2): EDMA reads one spurious 0x00 beat from + * MRDR before real data arrives, so rx_offset = 1. + * DMA4 (WAKEUP domain, LPI2C3/6): no spurious beat, rx_offset = 0. */ + rt_uint8_t rx_offset; +}; +#endif /* SOC_IMXRT1180_SERIES */ + struct imxrt_i2c_bus { struct rt_i2c_bus_device parent; @@ -38,32 +62,37 @@ struct imxrt_i2c_bus #if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) clock_root_t clock_root; #endif +#ifdef SOC_IMXRT1180_SERIES + struct i2c_dma_config *dma; + rt_uint8_t dma_flag; + rt_sem_t xfer_sem; +#endif }; -#if defined (BSP_USING_I2C1) -#define I2C1BUS_NAME "i2c1" +#if defined(BSP_USING_I2C1) +#define I2C1BUS_NAME "i2c1" #endif /*BSP_USING_I2C1*/ -#if defined (BSP_USING_I2C2) -#define I2C2BUS_NAME "i2c2" +#if defined(BSP_USING_I2C2) +#define I2C2BUS_NAME "i2c2" #endif /*BSP_USING_I2C2*/ -#if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/ +#if !defined(MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/ -#if defined (BSP_USING_I2C3) -#define I2C3BUS_NAME "i2c3" +#if defined(BSP_USING_I2C3) +#define I2C3BUS_NAME "i2c3" #endif /*BSP_USING_I2C3*/ -#if defined (BSP_USING_I2C4) -#define I2C4BUS_NAME "i2c4" +#if defined(BSP_USING_I2C4) +#define I2C4BUS_NAME "i2c4" #endif /*BSP_USING_I2C4*/ -#if defined (BSP_USING_I2C5) +#if defined(BSP_USING_I2C5) #define I2C5BUS_NAME "i2c5" #endif /*BSP_USING_I2C5*/ -#if defined (BSP_USING_I2C6) -#define I2C6BUS_NAME "i2c6" +#if defined(BSP_USING_I2C6) +#define I2C6BUS_NAME "i2c6" #endif /*BSP_USING_I2C6*/ #endif /* MIMXRT1015_SERIES */ @@ -77,75 +106,219 @@ struct imxrt_i2c_bus #define LPI2C_CLOCK_SOURCE_DIVIDER (0U) /* Get frequency of lpi2c clock */ -#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) +#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) #endif #ifdef BSP_USING_I2C1 -static struct imxrt_i2c_bus lpi2c1 = -{ +static struct imxrt_i2c_bus lpi2c1 = { .I2C = LPI2C1, .device_name = I2C1BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C1 */ #ifdef BSP_USING_I2C2 -static struct imxrt_i2c_bus lpi2c2 = -{ +static struct imxrt_i2c_bus lpi2c2 = { .I2C = LPI2C2, .device_name = I2C2BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C2 */ -#if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/ +#if !defined(MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/ #ifdef BSP_USING_I2C3 -static struct imxrt_i2c_bus lpi2c3 = -{ +static struct imxrt_i2c_bus lpi2c3 = { .I2C = LPI2C3, .device_name = I2C3BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C3 */ #ifdef BSP_USING_I2C4 -static struct imxrt_i2c_bus lpi2c4 = -{ +static struct imxrt_i2c_bus lpi2c4 = { .I2C = LPI2C4, .device_name = I2C4BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C4 */ #ifdef BSP_USING_I2C5 -static struct imxrt_i2c_bus lpi2c5 = -{ +static struct imxrt_i2c_bus lpi2c5 = { .I2C = LPI2C5, .device_name = I2C5BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C5 */ #ifdef BSP_USING_I2C6 -static struct imxrt_i2c_bus lpi2c6 = -{ +static struct imxrt_i2c_bus lpi2c6 = { .I2C = LPI2C6, .device_name = I2C6BUS_NAME, +#ifdef SOC_IMXRT1180_SERIES + .dma = RT_NULL, + .dma_flag = RT_FALSE, +#endif }; #endif /* RT_USING_HW_I2C6 */ #endif /* MIMXRT1015_SERIES */ -#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) ||defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)) +/* --- RT1180 DMA config instances --- + * i2c_dma_config contains lpi2c_master_edma_handle_t which embeds edma_tcd_t[] + * that the DMA engine accesses directly. Place in non-cacheable memory to prevent + * cache coherency issues. */ +#ifdef SOC_IMXRT1180_SERIES + +#ifdef BSP_I2C1_USING_DMA +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct i2c_dma_config i2c1_dma, 32) = { + .rx_request = kDma3RequestMuxLPI2C1Rx, + .rx_channel = BSP_I2C1_RX_DMA_CHANNEL, + .tx_request = kDma3RequestMuxLPI2C1Tx, + .tx_channel = BSP_I2C1_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA3, + .rx_offset = 1U, /* DMA3: one spurious 0x00 beat before real data */ +}; +#endif + +#ifdef BSP_I2C2_USING_DMA +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct i2c_dma_config i2c2_dma, 32) = { + .rx_request = kDma3RequestMuxLPI2C2Rx, + .rx_channel = BSP_I2C2_RX_DMA_CHANNEL, + .tx_request = kDma3RequestMuxLPI2C2Tx, + .tx_channel = BSP_I2C2_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA3, + .rx_offset = 1U, /* DMA3: one spurious 0x00 beat before real data */ +}; +#endif + +#ifdef BSP_I2C3_USING_DMA +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct i2c_dma_config i2c3_dma, 32) = { + .rx_request = kDma4RequestMuxLPI2C3Rx, + .rx_channel = BSP_I2C3_RX_DMA_CHANNEL, + .tx_request = kDma4RequestMuxLPI2C3Tx, + .tx_channel = BSP_I2C3_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA4, + .rx_offset = 0U, /* DMA4: no spurious beat, real data at bounce[0] */ +}; +#endif + +#ifdef BSP_I2C6_USING_DMA +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct i2c_dma_config i2c6_dma, 32) = { + .rx_request = kDma4RequestMuxLPI2C6Rx, + .rx_channel = BSP_I2C6_RX_DMA_CHANNEL, + .tx_request = kDma4RequestMuxLPI2C6Tx, + .tx_channel = BSP_I2C6_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA4, + .rx_offset = 0U, /* DMA4: no spurious beat, real data at bounce[0] */ +}; +#endif + +static void i2c_get_dma_config(void) +{ +#ifdef BSP_I2C1_USING_DMA + lpi2c1.dma = &i2c1_dma; + lpi2c1.dma_flag = RT_TRUE; +#endif +#ifdef BSP_I2C2_USING_DMA + lpi2c2.dma = &i2c2_dma; + lpi2c2.dma_flag = RT_TRUE; +#endif +#ifdef BSP_I2C3_USING_DMA + lpi2c3.dma = &i2c3_dma; + lpi2c3.dma_flag = RT_TRUE; +#endif +#ifdef BSP_I2C6_USING_DMA + lpi2c6.dma = &i2c6_dma; + lpi2c6.dma_flag = RT_TRUE; +#endif +} + +#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)) + +/* RT1180 EDMA4 RX bounce buffer. + * + * Observed behavior on RT1180 LPI2C + EDMA4: + * The EDMA reads one spurious 0x00 byte from the (not-yet-ready) MRDR before + * the first real data byte arrives. After that, data bytes land consecutively: + * bounce[0] = 0x00 (spurious MRDR read before data is ready) + * bounce[1] = I2C data byte 0 + * bounce[2] = I2C data byte 1 + * ... + * bounce[N] = I2C data byte N-1 + * To capture all N data bytes the DMA must perform N+1 beats minimum. + * Setting xfer.dataSize = 2*N is safe (drives 2N beats, easily covers N+1). + * After DMA completes, de-interleave: result[j] = bounce[j + 1]. + * + * Size: 512 bytes supports up to 255 I2C bytes per transfer ((512/2)-1). + * + * TX bounce buffer: + * DMA3 cannot access DTCM (stack/heap). The caller's TX buffer may be on the + * stack. memcpy it into this SRAM buffer before starting the EDMA TX so the + * DMA engine can always read from DMA-accessible SRAM. + */ +#define I2C_DMA_BOUNCE_SIZE 512U +static rt_uint8_t i2c_dma_bounce[I2C_DMA_BOUNCE_SIZE]; /* RX bounce buffer */ +static rt_uint8_t i2c_dma_tx_bounce[I2C_DMA_BOUNCE_SIZE]; /* TX bounce buffer */ + +static void lpi2c_edma_callback(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, + status_t completionStatus, void *userData) +{ + struct imxrt_i2c_bus *i2c = (struct imxrt_i2c_bus *)userData; + rt_sem_release(i2c->xfer_sem); +} + +static void lpi2c_dma_config(struct imxrt_i2c_bus *bus) +{ + EDMA_Type *edma_base = bus->dma->edma_base; + + EDMA_SetChannelMux(edma_base, bus->dma->rx_channel, bus->dma->rx_request); + EDMA_CreateHandle(&bus->dma->rx_edma, edma_base, bus->dma->rx_channel); + + EDMA_SetChannelMux(edma_base, bus->dma->tx_channel, bus->dma->tx_request); + EDMA_CreateHandle(&bus->dma->tx_edma, edma_base, bus->dma->tx_channel); + + LPI2C_MasterCreateEDMAHandle(bus->I2C, + &bus->dma->i2c_edma, + &bus->dma->rx_edma, + &bus->dma->tx_edma, + lpi2c_edma_callback, + bus); + + LOG_D("%s dma config done", bus->device_name); +} + +#endif /* BSP_USING_I2Cx - bounce buffers and lpi2c_dma_config */ +#endif /* SOC_IMXRT1180_SERIES */ + +#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)) static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); + struct rt_i2c_msg msgs[], + rt_uint32_t num); static rt_ssize_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); + struct rt_i2c_msg msgs[], + rt_uint32_t num); static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args); -static const struct rt_i2c_bus_device_ops imxrt_i2c_ops = -{ +static const struct rt_i2c_bus_device_ops imxrt_i2c_ops = { .master_xfer = imxrt_i2c_mst_xfer, .slave_xfer = imxrt_i2c_slv_xfer, .i2c_bus_control = imxrt_i2c_bus_control, @@ -158,7 +331,7 @@ static rt_err_t imxrt_lpi2c_configure(struct imxrt_i2c_bus *bus, lpi2c_master_co bus->parent.ops = &imxrt_i2c_ops; #ifdef SOC_IMXRT1170_SERIES - clock_root_config_t rootCfg = {0}; + clock_root_config_t rootCfg = { 0 }; rootCfg.mux = LPI2C_CLOCK_SOURCE_SELECT; rootCfg.div = LPI2C_CLOCK_SOURCE_DIVIDER + 1; CLOCK_SetRootClock(bus->clock_root, &rootCfg); @@ -217,6 +390,10 @@ status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status) return result; } +/* LPI2C_MasterWaitForTxFifoAllEmpty is only used in the non-RT1180 legacy + * transfer path. Guard it so the compiler does not warn about an unused + * static function when building for RT1180. */ +#ifndef SOC_IMXRT1180_SERIES /*! * @brief Wait until the tx fifo all empty. * @param base The LPI2C peripheral base address. @@ -251,84 +428,217 @@ static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base) return kStatus_Success; } +#endif /* !SOC_IMXRT1180_SERIES */ #ifdef SOC_IMXRT1180_SERIES static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) + struct rt_i2c_msg msgs[], + rt_uint32_t num) { struct imxrt_i2c_bus *imxrt_i2c; rt_size_t i; status_t status; - rt_bool_t is_read; - lpi2c_direction_t dir; RT_ASSERT(bus != RT_NULL); - imxrt_i2c = (struct imxrt_i2c_bus *) bus; + imxrt_i2c = (struct imxrt_i2c_bus *)bus; imxrt_i2c->msg = msgs; imxrt_i2c->msg_ptr = 0; imxrt_i2c->msg_cnt = num; imxrt_i2c->dptr = 0; - for (i = 0; i < num; i++) +#ifdef BSP_USING_DMA + if (imxrt_i2c->dma_flag == RT_TRUE) { - is_read = (msgs[i].flags & RT_I2C_RD) != 0U; - dir = is_read ? kLPI2C_Read : kLPI2C_Write; - - /* Issue START (first message) or Repeated START (subsequent messages). */ - if ((msgs[i].flags & RT_I2C_NO_START) != RT_I2C_NO_START) + /* DMA path: use the SDK non-blocking EDMA transfer API. + * Each rt_i2c_msg maps to one lpi2c_master_transfer_t. + * + * Restrictions: + * - DMA cannot handle zero-length data (EDMA never fires a completion + * interrupt, and NACK detection is unreliable). Fall back to blocking + * for zero-length probe transfers. + * - The caller's buffer may be in cacheable memory (e.g. stack). + * Clean the D-cache before a TX DMA so the DMA sees current data. + * Invalidate the D-cache after an RX DMA so the CPU sees DMA data. */ + for (i = 0; i < num; i++) { - if (i == 0) + lpi2c_master_transfer_t xfer; + rt_memset(&xfer, 0, sizeof(xfer)); + + xfer.slaveAddress = msgs[i].addr; + xfer.data = msgs[i].buf; + xfer.dataSize = msgs[i].len; + xfer.direction = (msgs[i].flags & RT_I2C_RD) ? kLPI2C_Read : kLPI2C_Write; + + if (msgs[i].flags & RT_I2C_NO_START) + { + xfer.flags = kLPI2C_TransferNoStartFlag; + } + else if (i + 1 < num) { - status = LPI2C_MasterStart(imxrt_i2c->I2C, msgs[i].addr, dir); + xfer.flags = kLPI2C_TransferNoStopFlag; } else { - status = LPI2C_MasterRepeatedStart(imxrt_i2c->I2C, msgs[i].addr, dir); + xfer.flags = kLPI2C_TransferDefaultFlag; } - if (status != kStatus_Success) + + /* Short or zero-length transfers: use blocking. + * Zero-length: EDMA never fires completion, NACK not detected. + * Short (<4 bytes): overhead is negligible; use blocking. */ + if (xfer.dataSize < 4U) { - i = 0; - break; + status = LPI2C_MasterTransferBlocking(imxrt_i2c->I2C, &xfer); + if (status != kStatus_Success) + { + i = 0; + break; + } + continue; + } + + /* RT1180 EDMA4 DMA-accessible buffer workaround: + * + * TX: DMA3 cannot read from DTCM (stack/heap). Copy the caller's TX + * data into the SRAM TX bounce buffer before starting the EDMA. + * + * RX: EDMA4 prepends one spurious 0x00 beat before real data arrives. + * Redirect into a 2x RX bounce buffer; de-interleave after DMA. */ + if (xfer.direction == kLPI2C_Write) + { + if (xfer.dataSize > I2C_DMA_BOUNCE_SIZE) + { + /* TX data too large for bounce; fall back to blocking. */ + status = LPI2C_MasterTransferBlocking(imxrt_i2c->I2C, &xfer); + if (status != kStatus_Success) + { + i = 0; + break; + } + continue; + } + rt_memcpy(i2c_dma_tx_bounce, xfer.data, xfer.dataSize); + xfer.data = i2c_dma_tx_bounce; + } + + if (xfer.direction == kLPI2C_Read) + { + /* DMA3 (LPI2C1/2): one spurious 0x00 beat precedes real data, + * so request orig_len + 1 beats to capture all N real bytes. + * DMA4 (LPI2C3/6): no spurious beat, request orig_len beats. */ + rt_size_t orig_len = xfer.dataSize; + rt_uint8_t rx_off = imxrt_i2c->dma->rx_offset; + rt_size_t bounce_len = orig_len + (rt_size_t)rx_off; + if (bounce_len > I2C_DMA_BOUNCE_SIZE) + { + /* Bounce buffer too small; fall back to blocking. */ + status = LPI2C_MasterTransferBlocking(imxrt_i2c->I2C, &xfer); + if (status != kStatus_Success) + { + i = 0; + break; + } + continue; + } + rt_memset(i2c_dma_bounce, 0, bounce_len); + xfer.data = i2c_dma_bounce; + xfer.dataSize = bounce_len; + (void)orig_len; /* used after DMA completes below */ } - /* Wait for address byte to be sent and check ACK/NACK. */ - status = LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C); + status = LPI2C_MasterTransferEDMA(imxrt_i2c->I2C, + &imxrt_i2c->dma->i2c_edma, + &xfer); if (status != kStatus_Success) { i = 0; break; } - if (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag) + if (rt_sem_take(imxrt_i2c->xfer_sem, rt_tick_from_millisecond(1000)) != RT_EOK) { + LPI2C_MasterTransferAbortEDMA(imxrt_i2c->I2C, &imxrt_i2c->dma->i2c_edma); i = 0; break; } - } + /* Wait for the LPI2C master to finish driving the STOP condition. + * The EDMA callback fires when the last DMA beat completes, but the + * LPI2C peripheral may still be clocking out the STOP condition. + * Poll the StopDetect flag (set when STOP is seen on bus, cleared by writing 1) + * then also wait for BusBusy to clear so SCL/SDA are released. */ + { + uint32_t deadline = 100000U; + /* Wait for stop detect or timeout. */ + while (!(LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterStopDetectFlag) && (deadline > 0U)) + { + deadline--; + } + /* Clear the stop detect flag. */ + LPI2C_MasterClearStatusFlags(imxrt_i2c->I2C, kLPI2C_MasterStopDetectFlag); + /* Also wait for bus to go idle. */ + deadline = 10000U; + while ((LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterBusBusyFlag) && (deadline > 0U)) + { + deadline--; + } + /* Flush RX and TX FIFOs to discard any residual bytes left after DMA. + * Without this, a stale byte in the RX FIFO is returned by the next + * blocking read instead of a fresh byte from the bus. */ + imxrt_i2c->I2C->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } - if (is_read) - { - status = LPI2C_MasterReceive(imxrt_i2c->I2C, msgs[i].buf, msgs[i].len); - } - else - { - status = LPI2C_MasterSend(imxrt_i2c->I2C, msgs[i].buf, msgs[i].len); - if (status == kStatus_Success) + /* Copy bounce into caller buffer for RX. + * DMA3 (LPI2C1/2): real data starts at bounce[1] (skip spurious byte). + * DMA4 (LPI2C3/6): real data starts at bounce[0] (no spurious byte). */ + if ((msgs[i].flags & RT_I2C_RD) && (msgs[i].len >= 4U)) { - status = LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C); + rt_size_t j; + rt_uint8_t rx_off = imxrt_i2c->dma->rx_offset; + for (j = 0; j < msgs[i].len; j++) + { + msgs[i].buf[j] = i2c_dma_bounce[j + (rt_size_t)rx_off]; + } } } - if (status != kStatus_Success) - { - i = 0; - break; - } } - - status = LPI2C_MasterStop(imxrt_i2c->I2C); - if (status != kStatus_Success) + else +#endif /* BSP_USING_DMA */ { - i = 0; + /* Non-DMA (polling) path. + * Use LPI2C_MasterTransferBlocking which handles the complete state machine + * (START, address, ACK/NACK, data, repeated-START, STOP) correctly. */ + for (i = 0; i < num; i++) + { + lpi2c_master_transfer_t xfer; + rt_memset(&xfer, 0, sizeof(xfer)); + + xfer.slaveAddress = msgs[i].addr; + xfer.data = msgs[i].buf; + xfer.dataSize = msgs[i].len; + xfer.direction = (msgs[i].flags & RT_I2C_RD) ? kLPI2C_Read : kLPI2C_Write; + + if (msgs[i].flags & RT_I2C_NO_START) + { + /* Continue an in-progress transaction: no START, no STOP. */ + xfer.flags = kLPI2C_TransferNoStartFlag; + } + else if (i + 1 < num) + { + /* More messages follow: hold the bus (no STOP) so the next + * message issues a repeated START. */ + xfer.flags = kLPI2C_TransferNoStopFlag; + } + else + { + /* Last (or only) message: send a STOP to release the bus. */ + xfer.flags = kLPI2C_TransferDefaultFlag; + } + + status = LPI2C_MasterTransferBlocking(imxrt_i2c->I2C, &xfer); + if (status != kStatus_Success) + { + i = 0; + break; + } + } } imxrt_i2c->msg = RT_NULL; @@ -340,13 +650,13 @@ static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, } #else static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) + struct rt_i2c_msg msgs[], + rt_uint32_t num) { struct imxrt_i2c_bus *imxrt_i2c; rt_size_t i; RT_ASSERT(bus != RT_NULL); - imxrt_i2c = (struct imxrt_i2c_bus *) bus; + imxrt_i2c = (struct imxrt_i2c_bus *)bus; imxrt_i2c->msg = msgs; imxrt_i2c->msg_ptr = 0; @@ -415,7 +725,7 @@ static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, // while((LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterBusBusyFlag)) // { // } - if(LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success) + if (LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success) { i = 0; break; @@ -444,7 +754,6 @@ static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, { i = 0; } - } imxrt_i2c->msg = RT_NULL; @@ -457,8 +766,8 @@ static rt_ssize_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, #endif static rt_ssize_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) + struct rt_i2c_msg msgs[], + rt_uint32_t num) { return 0; } @@ -473,11 +782,17 @@ static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, int rt_hw_i2c_init(void) { - lpi2c_master_config_t masterConfig = {0}; +#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)) + lpi2c_master_config_t masterConfig = { 0 }; +#endif -#if defined(BSP_USING_I2C1) +#ifdef SOC_IMXRT1180_SERIES + i2c_get_dma_config(); +#endif + +#if defined(BSP_USING_I2C1) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C1_BADURATE_400kHZ) +#if defined(HW_I2C1_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C1_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -489,11 +804,18 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c1, &masterConfig); rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c1.xfer_sem = rt_sem_create("i2c1_s", 0, RT_IPC_FLAG_PRIO); + if (lpi2c1.dma_flag == RT_TRUE) + { + lpi2c_dma_config(&lpi2c1); + } +#endif #endif /* BSP_USING_I2C1 */ -#if defined(BSP_USING_I2C2) +#if defined(BSP_USING_I2C2) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C2_BADURATE_400kHZ) +#if defined(HW_I2C2_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C2_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -505,13 +827,20 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c2, &masterConfig); rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c2.xfer_sem = rt_sem_create("i2c2_s", 0, RT_IPC_FLAG_PRIO); + if (lpi2c2.dma_flag == RT_TRUE) + { + lpi2c_dma_config(&lpi2c2); + } +#endif #endif /* BSP_USING_I2C2 */ #if !defined(MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/ -#if defined(BSP_USING_I2C3) +#if defined(BSP_USING_I2C3) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C3_BADURATE_400kHZ) +#if defined(HW_I2C3_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C3_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -523,11 +852,18 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c3, &masterConfig); rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c3.xfer_sem = rt_sem_create("i2c3_s", 0, RT_IPC_FLAG_PRIO); + if (lpi2c3.dma_flag == RT_TRUE) + { + lpi2c_dma_config(&lpi2c3); + } +#endif #endif /* BSP_USING_I2C3 */ -#if defined(BSP_USING_I2C4) +#if defined(BSP_USING_I2C4) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C4_BADURATE_400kHZ) +#if defined(HW_I2C4_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C4_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -539,11 +875,14 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c4, &masterConfig); rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c4.xfer_sem = rt_sem_create("i2c4_s", 0, RT_IPC_FLAG_PRIO); +#endif #endif /* BSP_USING_I2C4 */ -#if defined(BSP_USING_I2C5) +#if defined(BSP_USING_I2C5) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C5_BADURATE_400kHZ) +#if defined(HW_I2C5_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C5_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -555,11 +894,14 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c5, &masterConfig); rt_i2c_bus_device_register(&lpi2c5.parent, lpi2c5.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c5.xfer_sem = rt_sem_create("i2c5_s", 0, RT_IPC_FLAG_PRIO); +#endif #endif /* BSP_USING_I2C5 */ -#if defined(BSP_USING_I2C6) +#if defined(BSP_USING_I2C6) LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C6_BADURATE_400kHZ) +#if defined(HW_I2C6_BADURATE_400kHZ) masterConfig.baudRate_Hz = 400000U; #elif defined(HW_I2C6_BADURATE_100kHZ) masterConfig.baudRate_Hz = 100000U; @@ -571,6 +913,13 @@ int rt_hw_i2c_init(void) #endif imxrt_lpi2c_configure(&lpi2c6, &masterConfig); rt_i2c_bus_device_register(&lpi2c6.parent, lpi2c6.device_name); +#ifdef SOC_IMXRT1180_SERIES + lpi2c6.xfer_sem = rt_sem_create("i2c6_s", 0, RT_IPC_FLAG_PRIO); + if (lpi2c6.dma_flag == RT_TRUE) + { + lpi2c_dma_config(&lpi2c6); + } +#endif #endif /* BSP_USING_I2C6 */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c index 3999b293f4..6f71436b8a 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c @@ -20,7 +20,7 @@ #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif -#define LOG_TAG "drv.lpadc" +#define LOG_TAG "drv.lpadc" #include <drv_log.h> #include "drv_lpadc.h" #include "fsl_lpadc.h" @@ -40,7 +40,7 @@ static struct rt_adc_device lpadc2_device; #include "fsl_edma.h" volatile bool g_Transfer_Done = false; -AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = {0x0,0x0,0x0,0x0,0x0,0x0,0x0}; +AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; /* User callback function for EDMA transfer. */ void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) @@ -57,13 +57,17 @@ static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t cha ADC_Type *base; /* channel check*/ - if(channel < 4) return -RT_EINVAL; + if (channel < 4) + { + return -RT_EINVAL; + } base = (ADC_Type *)(device->parent.user_data); - if( RT_TRUE == enabled ) + if (RT_TRUE == enabled) { LPADC_Enable(base, true); - } else + } + else { LPADC_Enable(base, false); } @@ -74,12 +78,12 @@ static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t cha static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { ADC_Type *base; - uint32_t data_mask=0xffffffff; + uint32_t data_mask = 0xffffffff; #if defined(BSP_LPADC1_USING_DMA) #else - uint8_t i=0; - uint32_t adc_result[7] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0}; /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */ + uint8_t i = 0; + uint32_t adc_result[7] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */ lpadc_conv_result_t mLpadcResultConfigStruct; #endif @@ -87,7 +91,7 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha LPADC_DoSoftwareTrigger(base, 1U); #if defined(BSP_LPADC1_USING_DMA) - extern edma_handle_t DMA4_CH0_Handle; + extern edma_handle_t DMA4_CH0_Handle; data_mask = 0xffff; g_Transfer_Done = false; EDMA_StartTransfer(&DMA4_CH0_Handle); @@ -96,7 +100,7 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha { } #else - for(i=0;i<7;i++) + for (i = 0; i < 7; i++) { #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U)) @@ -108,17 +112,23 @@ static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t cha adc_result[i] = (mLpadcResultConfigStruct.convValue); } #endif - switch(channel) + switch (channel) { - case 4: *value = adc_result[0] & data_mask; + case 4: + *value = adc_result[0] & data_mask; break; - case 5: *value = adc_result[4] & data_mask; + case 5: + *value = adc_result[4] & data_mask; break; - case 6: *value = adc_result[2] & data_mask; + case 6: + *value = adc_result[2] & data_mask; break; - case 7: *value = adc_result[3] & data_mask; + case 7: + *value = adc_result[3] & data_mask; break; - default: *value = 0; return -RT_EINVAL; + default: + *value = 0; + return -RT_EINVAL; } return RT_EOK; @@ -135,8 +145,7 @@ static rt_int16_t imxrt_lp_adc_get_vref(struct rt_adc_device *device) } -static struct rt_adc_ops imxrt_lpadc_ops = -{ +static struct rt_adc_ops imxrt_lpadc_ops = { .enabled = imxrt_lp_adc_enabled, .convert = imxrt_lp_adc_convert, .get_resolution = imxrt_lp_adc_get_resolution, diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.c new file mode 100644 index 0000000000..bdd98c87a2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.c @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-14 nxp-ran First version for MIMXRT1180 CM33 BBNSM RTC. + * 2026-08-16 nxp-ran v2: use real BBNSM 32768 Hz hardware counter + * with GPR-based sync point for time offset. + */ + +/* + * RT-Thread RTC driver for MIMXRT1180 CM33 -- BBNSM-based. + * + * Hardware constraints (RT1180 specific): + * - The RT1180 has BBNSM (Battery-Backed Non-Secure Module) instead of SNVS. + * - The BBNSM RTC is a 47-bit free-running counter at 32.768 kHz (32768 Hz). + * - BBNSM_RTC_LS[31:0] holds lower counter bits; BBNSM_RTC_MS[14:0] upper. + * - Writes to BBNSM_RTC_LS/MS are blocked by ELE firmware even from CM33 + * secure world. We therefore CANNOT set the hardware counter directly. + * - BBNSM GPR[0..7] are 8x 32-bit battery-backed SRAM registers that + * survive warm resets (NVIC reset, watchdog, reset button) as long as + * VDD_BBSM is powered. These registers CAN be read and written freely. + * + * Time-keeping strategy (sync-point / offset method): + * A sync point is stored in BBNSM GPR registers: + * GPR[0] = epoch_lo : lower 32 bits of Unix seconds at last SET_TIME. + * GPR[1] = epoch_hi : upper 32 bits of Unix seconds at last SET_TIME. + * GPR[2] = snap_lo : lower 32 bits of BBNSM RTC ticks at sync. + * GPR[3] = snap_hi : upper bits of BBNSM RTC ticks at sync. + * GPR[4] = magic : 0xBBCC0002 -- marks valid GPR contents. + * + * GET_TIME computes: + * current = epoch_base + (bbnsm_ticks_now - snap_ticks) / 32768 + * + * This gives monotonically increasing time that: + * - Uses the hardware 32768 Hz counter for sub-second accuracy. + * - Survives warm resets (GPR retains values, counter keeps running). + * - Falls back to rt_tick-based delta on boards without a 32K crystal + * (detected when the counter is not advancing -- reads stuck at 0). + * + * Usage: + * Enable BSP_USING_RTC in menuconfig. SOC_IMXRT1180_SERIES selects this + * driver automatically instead of drv_rtc.c. + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include <sys/time.h> + +#ifdef BSP_USING_RTC +#ifdef SOC_IMXRT1180_SERIES + +#define LOG_TAG "drv.rtc" +#include <drv_log.h> + +#include "drv_rtc_bbnsm.h" +#include "fsl_device_registers.h" + +/* Magic value stored in BBNSM GPR[GPR_IDX_MAGIC] to detect valid warm-reset state. */ +#define BBNSM_GPR_MAGIC (0xBBCC0002u) + +/* BBNSM GPR array indices used by this driver. */ +#define GPR_IDX_EPOCH_LO (0u) /* lower 32 bits of Unix epoch seconds at sync */ +#define GPR_IDX_EPOCH_HI (1u) /* upper 32 bits of Unix epoch seconds at sync */ +#define GPR_IDX_SNAP_LO (2u) /* lower 32 bits of RTC ticks at sync */ +#define GPR_IDX_SNAP_HI (3u) /* upper bits of RTC ticks at sync */ +#define GPR_IDX_MAGIC (4u) /* magic sentinel */ + +/* 32768 Hz crystal clock rate of the BBNSM RTC counter. */ +#define BBNSM_RTC_FREQ (32768u) + +/* + * In-RAM copies of the sync point (loaded at init, updated on SET_TIME). + * These avoid GPR reads on every GET_TIME call. + */ +static time_t s_epoch_base = 0; +static uint32_t s_snap_lo = 0; +static uint32_t s_snap_hi = 0; + +/* + * Fallback: rt_tick at init (used only when BBNSM RTC ticks are stuck at 0, + * i.e. no 32K crystal populated). + */ +static rt_tick_t s_tick_base = 0; +static rt_bool_t s_use_rtc_hw = RT_FALSE; + +/******************************************************************************* + * Internal helpers + ******************************************************************************/ + +/* + * Read the 47-bit BBNSM RTC counter using a double-read of the MS register + * to guard against a carry between LS and MS during the read. + */ +static uint64_t bbnsm_read_ticks(void) +{ + uint32_t ms1, ms2, ls; + do + { + ms1 = BBNSM->BBNSM_RTC_MS & BBNSM_BBNSM_RTC_MS_RTC_MASK; + ls = BBNSM->BBNSM_RTC_LS; + ms2 = BBNSM->BBNSM_RTC_MS & BBNSM_BBNSM_RTC_MS_RTC_MASK; + } while (ms1 != ms2); + + return ((uint64_t)ms1 << 32u) | (uint64_t)ls; +} + +/* + * Enable the BBNSM RTC counter (if it is not already running). + * Writing 0x2 to the RTC_EN field enables it; 0x1 disables it. + * We only set the enable bit -- we do NOT write the counter itself. + */ +static void bbnsm_rtc_enable(void) +{ + uint32_t ctrl = BBNSM->BBNSM_CTRL; + /* Field is 2-bit: 0x2 = enable, 0x1 = disable, 0x0 = no change. */ + uint32_t en = (ctrl & BBNSM_BBNSM_CTRL_RTC_EN_MASK) >> + BBNSM_BBNSM_CTRL_RTC_EN_SHIFT; + if (en != 0x2u) + { + BBNSM->BBNSM_CTRL = (ctrl & ~BBNSM_BBNSM_CTRL_RTC_EN_MASK) | + BBNSM_BBNSM_CTRL_RTC_EN(0x2u); + } +} + +/* + * Persist the sync point to BBNSM GPR registers. + * Magic is cleared first so a torn write does not leave stale values. + */ +static void bbnsm_gpr_save(time_t epoch, uint32_t snap_lo, uint32_t snap_hi) +{ + BBNSM->GPR[GPR_IDX_MAGIC] = 0u; /* invalidate while writing */ + BBNSM->GPR[GPR_IDX_EPOCH_LO] = (uint32_t)((uint64_t)epoch & 0xFFFFFFFFu); + BBNSM->GPR[GPR_IDX_EPOCH_HI] = (uint32_t)(((uint64_t)epoch >> 32u) & 0xFFFFFFFFu); + BBNSM->GPR[GPR_IDX_SNAP_LO] = snap_lo; + BBNSM->GPR[GPR_IDX_SNAP_HI] = snap_hi; + BBNSM->GPR[GPR_IDX_MAGIC] = BBNSM_GPR_MAGIC; +} + +/* + * Try to restore the sync point from BBNSM GPR registers. + * Returns RT_TRUE if a valid saved state was found, RT_FALSE on cold boot. + */ +static rt_bool_t bbnsm_gpr_restore(time_t *out_epoch, + uint32_t *out_snap_lo, + uint32_t *out_snap_hi) +{ + if (BBNSM->GPR[GPR_IDX_MAGIC] == BBNSM_GPR_MAGIC) + { + uint64_t epoch = ((uint64_t)BBNSM->GPR[GPR_IDX_EPOCH_HI] << 32u) | + (uint64_t)BBNSM->GPR[GPR_IDX_EPOCH_LO]; + *out_epoch = (time_t)epoch; + *out_snap_lo = BBNSM->GPR[GPR_IDX_SNAP_LO]; + *out_snap_hi = BBNSM->GPR[GPR_IDX_SNAP_HI]; + return RT_TRUE; + } + return RT_FALSE; +} + +/******************************************************************************* + * RT-Thread device ops + ******************************************************************************/ + +static rt_err_t imxrt1180_rtc_init(rt_device_t dev) +{ + (void)dev; + + /* Make sure the BBNSM RTC counter is running. */ + bbnsm_rtc_enable(); + + /* Detect whether the 32K crystal is working: if the counter is + * non-zero (or if it advances) we use the hardware ticks; otherwise + * we fall back to rt_tick_get() delta. */ + uint64_t t0 = bbnsm_read_ticks(); + /* A simple non-zero check is sufficient: if no crystal the counter + * will remain 0 forever. */ + s_use_rtc_hw = (t0 != 0u) ? RT_TRUE : RT_FALSE; + + if (!s_use_rtc_hw) + { + LOG_W("BBNSM RTC counter is 0 -- no 32K crystal? falling back to rt_tick"); + } + + /* Try to restore sync point from GPR (warm reset). */ + time_t epoch = 0; + uint32_t snap_lo = 0; + uint32_t snap_hi = 0; + + if (bbnsm_gpr_restore(&epoch, &snap_lo, &snap_hi)) + { + s_epoch_base = epoch; + s_snap_lo = snap_lo; + s_snap_hi = snap_hi; + s_tick_base = rt_tick_get(); + LOG_I("warm reset: RTC epoch=%u snap_hi=%u snap_lo=%u", + (unsigned)epoch, (unsigned)snap_hi, (unsigned)snap_lo); + } + else + { + /* Cold boot: start from epoch 0; wait for a SET_TIME call. */ + s_epoch_base = 0; + s_snap_lo = (uint32_t)(t0 & 0xFFFFFFFFu); + s_snap_hi = (uint32_t)(t0 >> 32u); + s_tick_base = rt_tick_get(); + LOG_I("cold boot: BBNSM GPR no valid epoch, RTC at epoch 0"); + } + + return RT_EOK; +} + +static rt_err_t imxrt1180_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + (void)dev; + (void)oflag; + return RT_EOK; +} + +static rt_err_t imxrt1180_rtc_close(rt_device_t dev) +{ + (void)dev; + return RT_EOK; +} + +static rt_ssize_t imxrt1180_rtc_read(rt_device_t dev, rt_off_t pos, + void *buf, rt_size_t size) +{ + (void)dev; + (void)pos; + (void)buf; + (void)size; + return -RT_EINVAL; +} + +static rt_ssize_t imxrt1180_rtc_write(rt_device_t dev, rt_off_t pos, + const void *buf, rt_size_t size) +{ + (void)dev; + (void)pos; + (void)buf; + (void)size; + return -RT_EINVAL; +} + +static rt_err_t imxrt1180_rtc_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + { + time_t current; + + if (s_use_rtc_hw) + { + /* Hardware path: compute elapsed seconds from RTC tick delta. */ + uint64_t now_ticks = bbnsm_read_ticks(); + uint64_t snap_ticks = ((uint64_t)s_snap_hi << 32u) | + (uint64_t)s_snap_lo; + uint64_t delta_ticks = (now_ticks >= snap_ticks) ? (now_ticks - snap_ticks) : 0u; + current = s_epoch_base + (time_t)(delta_ticks / BBNSM_RTC_FREQ); + } + else + { + /* Fallback path: use rt_tick delta (no 32K crystal). */ + rt_tick_t elapsed_ticks = rt_tick_get() - s_tick_base; + current = s_epoch_base + + (time_t)(elapsed_ticks / RT_TICK_PER_SECOND); + } + + *(time_t *)args = current; + break; + } + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + time_t new_epoch = *(time_t *)args; + uint64_t now_ticks = bbnsm_read_ticks(); + uint32_t snap_lo = (uint32_t)(now_ticks & 0xFFFFFFFFu); + uint32_t snap_hi = (uint32_t)(now_ticks >> 32u); + + s_epoch_base = new_epoch; + s_snap_lo = snap_lo; + s_snap_hi = snap_hi; + s_tick_base = rt_tick_get(); + + bbnsm_gpr_save(new_epoch, snap_lo, snap_hi); + + if (s_use_rtc_hw == RT_FALSE && now_ticks != 0u) + { + /* Crystal may have started since init -- re-enable hw path. */ + s_use_rtc_hw = RT_TRUE; + LOG_I("RTC hw counter now non-zero, switching to hardware path"); + } + + LOG_D("RTC SET_TIME: epoch=%u", (unsigned)new_epoch); + break; + } + + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + +/******************************************************************************* + * Device registration + ******************************************************************************/ + +static struct rt_device s_rtc_device = { + .type = RT_Device_Class_RTC, + .init = imxrt1180_rtc_init, + .open = imxrt1180_rtc_open, + .close = imxrt1180_rtc_close, + .read = imxrt1180_rtc_read, + .write = imxrt1180_rtc_write, + .control = imxrt1180_rtc_control, +}; + +int rt_hw_rtc_init(void) +{ + rt_err_t ret; + + ret = rt_device_register(&s_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR); + if (ret != RT_EOK) + { + LOG_E("rtc device register failed: %d", ret); + return ret; + } + + ret = rt_device_open(&s_rtc_device, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + LOG_E("rtc device open failed: %d", ret); + return ret; + } + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* SOC_IMXRT1180_SERIES */ +#endif /* BSP_USING_RTC */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.h new file mode 100644 index 0000000000..4ae9d61249 --- /dev/null +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_rtc_bbnsm.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-14 nxp-ran First version for MIMXRT1180 CM33 BBNSM RTC. + * + * This driver is for the MIMXRT1180 (RT1180) CM33 core only. + * The RT1180 does not have SNVS; the battery-backed domain is BBNSM. + * CM33 in TrustZone secure world can access BBNSM registers directly. + * + * Do NOT use drv_rtc.c (SNVS/SNVS_LP) for RT1180 -- use this driver. + */ + +#ifndef DRV_RTC_BBNSM_H__ +#define DRV_RTC_BBNSM_H__ + +#include <rtdevice.h> + +int rt_hw_rtc_init(void); + +#endif /* DRV_RTC_BBNSM_H__ */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_sdio.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_sdio.c index 229b3c3aef..8442a3517f 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_sdio.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_sdio.c @@ -14,9 +14,15 @@ #include <board.h> #include <fsl_usdhc.h> +#if !defined(SOC_IMXRT1180_SERIES) +/* RT1180 uses RGPIO (fsl_rgpio.h); GPIO pin control is done in board sdio_port.c */ #include <fsl_gpio.h> +#endif #include <fsl_iomuxc.h> - +#if defined(SOC_IMXRT1180_SERIES) +/* RT1180 uses XCACHE-based cache maintenance API (CM33 variant). */ +#include <fsl_cache.h> +#endif #include <finsh.h> #define RT_USING_SDIO1 @@ -39,16 +45,16 @@ static int enable_log = 1; #define MMCSD_DGB(fmt, ...) #endif -#define CACHE_LINESIZE (32) +#define CACHE_LINESIZE (32) -#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL) +#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL) -#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ -#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ -#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ -#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (4096U) -#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (USDHC_MAX_BLOCK_COUNT) +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ +#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (4096U) +#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (USDHC_MAX_BLOCK_COUNT) /* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ #define USDHC_READ_WATERMARK_LEVEL (0x80U) @@ -61,8 +67,8 @@ static int enable_log = 1; #define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle //#ifdef SOC_IMXRT1170_SERIES -#define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */ -#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ //#else //#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ //#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ @@ -82,7 +88,7 @@ struct imxrt_mmcsd //USDHC_Type *base; usdhc_host_t usdhc_host; -#ifndef SOC_IMXRT1170_SERIES +#if !defined(SOC_IMXRT1170_SERIES) && !defined(SOC_IMXRT1180_SERIES) clock_div_t usdhc_div; #endif clock_ip_name_t ip_clock; @@ -93,7 +99,6 @@ struct imxrt_mmcsd #ifndef CODE_STORED_ON_SDCARD static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd) { - // CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ } #endif @@ -137,7 +142,7 @@ static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd) static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd) { CLOCK_EnableClock(mmcsd->ip_clock); -#if !defined(SOC_IMXRT1170_SERIES) && !defined(SOC_MIMXRT1062DVL6A) +#if !defined(SOC_IMXRT1170_SERIES) && !defined(SOC_MIMXRT1062DVL6A) && !defined(SOC_IMXRT1180_SERIES) CLOCK_SetDiv(mmcsd->usdhc_div, 5U); #endif } @@ -155,9 +160,9 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) struct rt_mmcsd_data *data; status_t error; usdhc_adma_config_t dmaConfig; - usdhc_transfer_t fsl_content = {0}; - usdhc_command_t fsl_command = {0}; - usdhc_data_t fsl_data = {0}; + usdhc_transfer_t fsl_content = { 0 }; + usdhc_command_t fsl_command = { 0 }; + usdhc_data_t fsl_data = { 0 }; rt_uint32_t *buf = NULL; RT_ASSERT(host != RT_NULL); @@ -243,10 +248,9 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount); if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) - ((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM - ((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM + ((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) || // ITCM + ((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)) // DTCM/System TCM - not DMA-accessible { - buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); RT_ASSERT(buf != RT_NULL); @@ -290,6 +294,15 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) fsl_content.data = NULL; } +#if defined(SOC_IMXRT1180_SERIES) + /* RT1180: clean D-cache before TX so DMA sees updated data in OCRAM. */ + if (data && fsl_data.txData) + { + DCACHE_CleanByRange((uint32_t)fsl_data.txData, + (uint32_t)(fsl_data.blockSize * fsl_data.blockCount)); + } +#endif + error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content); if (error != kStatus_Success) { @@ -298,6 +311,15 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) cmd->err = -RT_ERROR; } +#if defined(SOC_IMXRT1180_SERIES) + /* RT1180: invalidate D-cache after RX so CPU sees data written by USDHC DMA. */ + if (data && fsl_data.rxData) + { + DCACHE_InvalidateByRange((uint32_t)fsl_data.rxData, + (uint32_t)(fsl_data.blockSize * fsl_data.blockCount)); + } +#endif + if (buf) { if (fsl_data.rxData) @@ -331,7 +353,6 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - struct imxrt_mmcsd *mmcsd; unsigned int usdhc_clk; unsigned int bus_width; @@ -347,19 +368,22 @@ static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *i if (usdhc_clk > IMXRT_MAX_FREQ) usdhc_clk = IMXRT_MAX_FREQ; -#ifdef SOC_IMXRT1170_SERIES - clock_root_config_t rootCfg = {0}; +#if defined(SOC_IMXRT1170_SERIES) + clock_root_config_t rootCfg = { 0 }; /* SYS PLL2 528MHz. */ - const clock_sys_pll2_config_t sysPll2Config = { - .ssEnable = false, - }; + const clock_sys_pll2_config_t sysPll2Config = { + .ssEnable = false, + }; - CLOCK_InitSysPll2(&sysPll2Config); - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + CLOCK_InitSysPll2(&sysPll2Config); + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); - rootCfg.mux = 4; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + rootCfg.mux = 4; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + src_clk = CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1); +#elif defined(SOC_IMXRT1180_SERIES) + /* RT1180: USDHC1 clock root configured once in sdio_port.c board init. */ src_clk = CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1); #elif defined(SOC_MIMXRT1062DVL6A) CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); @@ -368,11 +392,11 @@ static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *i /* Configure USDHC clock source and divider */ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); - src_clk = 396000000U / 2U; + src_clk = 396000000U / 2U; #else src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U)); #endif - MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width); + MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width); if (usdhc_clk) { @@ -398,8 +422,7 @@ static void log_toggle(int en) FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple); #endif -static const struct rt_mmcsd_host_ops ops = -{ +static const struct rt_mmcsd_host_ops ops = { _mmc_request, _mmc_set_iocfg, RT_NULL,//_mmc_get_card_status, @@ -411,9 +434,6 @@ rt_int32_t _imxrt_mci_init(void) struct rt_mmcsd_host *host; struct imxrt_mmcsd *mmcsd; -#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE)) - uint32_t hs400Capability = 0U; -#endif host = mmcsd_alloc_host(); if (!host) @@ -430,6 +450,9 @@ rt_int32_t _imxrt_mci_init(void) rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd)); mmcsd->usdhc_host.base = USDHC1; +#if defined(SOC_IMXRT1180_SERIES) + mmcsd->ip_clock = kCLOCK_Usdhc1; +#endif //#ifndef SOC_IMXRT1170_SERIES // mmcsd->usdhc_div = kCLOCK_Usdhc1Div; //#endif @@ -439,13 +462,13 @@ rt_int32_t _imxrt_mci_init(void) host->freq_min = 375000; host->freq_max = 25000000; host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; #if defined(FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) && (FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) - hs400Capability = (uint32_t)FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(mmcsd->usdhc_host.base); + uint32_t hs400Capability = (uint32_t)FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(mmcsd->usdhc_host.base); #endif -#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE)) +#if defined(FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) && (FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) && defined(MMCSD_SUP_HIGHSPEED_HS400) if (hs400Capability != 0U) { host->flags |= (uint32_t)MMCSD_SUP_HIGHSPEED_HS400; diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_spi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_spi.c index b53e45a0b5..02d5c6231c 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_spi.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_spi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-03-27 Liuguang the first version. + * 2026-08-11 Ran add RT1180 CM33 support with DMA */ #include <rtthread.h> @@ -16,13 +17,15 @@ #include "fsl_iomuxc.h" #include "fsl_lpspi.h" #include "fsl_lpspi_edma.h" +#ifndef SOC_IMXRT1180_SERIES #include "fsl_dmamux.h" +#endif -#define LOG_TAG "drv.spi" +#define LOG_TAG "drv.spi" #include <drv_log.h> #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif enum @@ -39,6 +42,7 @@ enum #ifdef BSP_USING_SPI4 SPI4_INDEX, #endif + SPI_INDEX_MAX }; struct imxrt_sw_spi_cs @@ -57,6 +61,10 @@ struct dma_config edma_handle_t tx_edma; dma_request_source_t tx_request; rt_uint8_t tx_channel; + +#ifdef SOC_IMXRT1180_SERIES + EDMA_Type *edma_base; +#endif }; struct imxrt_spi @@ -68,18 +76,25 @@ struct imxrt_spi lpspi_master_handle_t spi_normal; struct dma_config *dma; rt_uint8_t dma_flag; +#if defined(SOC_IMXRT1170_SERIES) rt_uint16_t masterclock; +#elif defined(SOC_IMXRT1180_SERIES) + clock_root_t clock_root; +#endif }; -static struct imxrt_spi lpspis[] = -{ +static struct imxrt_spi lpspis[] = { #ifdef BSP_USING_SPI1 { .bus_name = "spi1", .base = LPSPI1, .dma = RT_NULL, .dma_flag = RT_FALSE, +#if defined(SOC_IMXRT1170_SERIES) .masterclock = 171, +#elif defined(SOC_IMXRT1180_SERIES) + .clock_root = kCLOCK_Root_Lpspi0102, +#endif }, #endif #ifdef BSP_USING_SPI2 @@ -88,7 +103,11 @@ static struct imxrt_spi lpspis[] = .base = LPSPI2, .dma = RT_NULL, .dma_flag = RT_FALSE, +#if defined(SOC_IMXRT1170_SERIES) .masterclock = 172, +#elif defined(SOC_IMXRT1180_SERIES) + .clock_root = kCLOCK_Root_Lpspi0102, +#endif }, #endif #ifdef BSP_USING_SPI3 @@ -97,7 +116,11 @@ static struct imxrt_spi lpspis[] = .base = LPSPI3, .dma = RT_NULL, .dma_flag = RT_FALSE, +#if defined(SOC_IMXRT1170_SERIES) .masterclock = 173, +#elif defined(SOC_IMXRT1180_SERIES) + .clock_root = kCLOCK_Root_Lpspi0304, +#endif }, #endif #ifdef BSP_USING_SPI4 @@ -106,61 +129,103 @@ static struct imxrt_spi lpspis[] = .base = LPSPI4, .dma = RT_NULL, .dma_flag = RT_FALSE, +#if defined(SOC_IMXRT1170_SERIES) .masterclock = 174, +#elif defined(SOC_IMXRT1180_SERIES) + .clock_root = kCLOCK_Root_Lpspi0304, +#endif }, #endif }; -static void spi_get_dma_config(void) -{ +/* DMA config structs must be in non-cacheable memory because lpspi_master_edma_handle_t + * embeds lpspiSoftwareTCD[] which the DMA engine reads directly. If the struct is in + * cached SRAM the DMA sees stale cache lines and corrupts the transfer. + * AT_NONCACHEABLE_SECTION_ALIGN_INIT places zero-or-nonzero-inited globals in the + * NonCacheable linker section (defined in the RT1180 linker script). */ #ifdef BSP_SPI1_USING_DMA - static struct dma_config spi1_dma = - { +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct dma_config spi1_dma, 4) = { +#ifdef SOC_IMXRT1180_SERIES + .rx_request = kDma3RequestMuxLPSPI1Rx, + .rx_channel = BSP_SPI1_RX_DMA_CHANNEL, + .tx_request = kDma3RequestMuxLPSPI1Tx, + .tx_channel = BSP_SPI1_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA3, +#else .rx_request = kDmaRequestMuxLPSPI1Rx, .rx_channel = BSP_SPI1_RX_DMA_CHANNEL, .tx_request = kDmaRequestMuxLPSPI1Tx, .tx_channel = BSP_SPI1_TX_DMA_CHANNEL, - }; - - lpspis[SPI1_INDEX].dma = &spi1_dma; - lpspis[SPI1_INDEX].dma_flag = RT_TRUE; +#endif +}; #endif #ifdef BSP_SPI2_USING_DMA - static struct dma_config spi2_dma = - { +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct dma_config spi2_dma, 4) = { +#ifdef SOC_IMXRT1180_SERIES + .rx_request = kDma3RequestMuxLPSPI2Rx, + .rx_channel = BSP_SPI2_RX_DMA_CHANNEL, + .tx_request = kDma3RequestMuxLPSPI2Tx, + .tx_channel = BSP_SPI2_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA3, +#else .rx_request = kDmaRequestMuxLPSPI2Rx, .rx_channel = BSP_SPI2_RX_DMA_CHANNEL, .tx_request = kDmaRequestMuxLPSPI2Tx, .tx_channel = BSP_SPI2_TX_DMA_CHANNEL, - }; - - lpspis[SPI2_INDEX].dma = &spi2_dma; - lpspis[SPI2_INDEX].dma_flag = RT_TRUE; +#endif +}; #endif #ifdef BSP_SPI3_USING_DMA - static struct dma_config spi3_dma = - { +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct dma_config spi3_dma, 4) = { +#ifdef SOC_IMXRT1180_SERIES + .rx_request = kDma4RequestMuxLPSPI3Rx, + .rx_channel = BSP_SPI3_RX_DMA_CHANNEL, + .tx_request = kDma4RequestMuxLPSPI3Tx, + .tx_channel = BSP_SPI3_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA4, +#else .rx_request = kDmaRequestMuxLPSPI3Rx, .rx_channel = BSP_SPI3_RX_DMA_CHANNEL, .tx_request = kDmaRequestMuxLPSPI3Tx, .tx_channel = BSP_SPI3_TX_DMA_CHANNEL, - }; - - lpspis[SPI3_INDEX].dma = &spi3_dma; - lpspis[SPI3_INDEX].dma_flag = RT_TRUE; +#endif +}; #endif #ifdef BSP_SPI4_USING_DMA - static struct dma_config spi4_dma = - { +static AT_NONCACHEABLE_SECTION_ALIGN_INIT(struct dma_config spi4_dma, 4) = { +#ifdef SOC_IMXRT1180_SERIES + .rx_request = kDma4RequestMuxLPSPI4Rx, + .rx_channel = BSP_SPI4_RX_DMA_CHANNEL, + .tx_request = kDma4RequestMuxLPSPI4Tx, + .tx_channel = BSP_SPI4_TX_DMA_CHANNEL, + .edma_base = (EDMA_Type *)DMA4, +#else .rx_request = kDmaRequestMuxLPSPI4Rx, .rx_channel = BSP_SPI4_RX_DMA_CHANNEL, .tx_request = kDmaRequestMuxLPSPI4Tx, .tx_channel = BSP_SPI4_TX_DMA_CHANNEL, - }; +#endif +}; +#endif +static void spi_get_dma_config(void) +{ +#ifdef BSP_SPI1_USING_DMA + lpspis[SPI1_INDEX].dma = &spi1_dma; + lpspis[SPI1_INDEX].dma_flag = RT_TRUE; +#endif +#ifdef BSP_SPI2_USING_DMA + lpspis[SPI2_INDEX].dma = &spi2_dma; + lpspis[SPI2_INDEX].dma_flag = RT_TRUE; +#endif +#ifdef BSP_SPI3_USING_DMA + lpspis[SPI3_INDEX].dma = &spi3_dma; + lpspis[SPI3_INDEX].dma_flag = RT_TRUE; +#endif +#ifdef BSP_SPI4_USING_DMA lpspis[SPI4_INDEX].dma = &spi4_dma; lpspis[SPI4_INDEX].dma_flag = RT_TRUE; #endif @@ -199,17 +264,22 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, return ret; } -static uint32_t imxrt_get_lpspi_freq(void) +static uint32_t imxrt_get_lpspi_freq(struct imxrt_spi *spi) { uint32_t freq = 0; +#if defined(SOC_IMXRT1180_SERIES) + freq = CLOCK_GetRootClockFreq(spi->clock_root); +#elif defined(SOC_IMXRT1170_SERIES) + freq = CLOCK_GetFreqFromObs(spi->masterclock, 2); +#else /* CLOCK_GetMux(kCLOCK_LpspiMux): 00b: derive clock from PLL3 PFD1 720M 01b: derive clock from PLL3 PFD0 720M 10b: derive clock from PLL2 528M 11b: derive clock from PLL2 PFD2 396M */ - switch(CLOCK_GetMux(kCLOCK_LpspiMux)) + switch (CLOCK_GetMux(kCLOCK_LpspiMux)) { case 0: freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); @@ -229,6 +299,7 @@ static uint32_t imxrt_get_lpspi_freq(void) } freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); +#endif return freq; } @@ -238,10 +309,10 @@ static void lpspi_normal_config(struct imxrt_spi *spi) RT_ASSERT(spi != RT_NULL); LPSPI_MasterTransferCreateHandle(spi->base, - &spi->spi_normal, - normal_xfer_callback, - spi); - LOG_D(LOG_TAG" %s normal config done\n", spi->bus_name); + &spi->spi_normal, + normal_xfer_callback, + spi); + LOG_D(LOG_TAG " %s normal config done\n", spi->bus_name); } static void lpspi_dma_config(struct imxrt_spi *spi) @@ -249,6 +320,15 @@ static void lpspi_dma_config(struct imxrt_spi *spi) #ifdef BSP_USING_DMA RT_ASSERT(spi != RT_NULL); +#ifdef SOC_IMXRT1180_SERIES + EDMA_Type *edma_base = spi->dma->edma_base; + + EDMA_SetChannelMux(edma_base, spi->dma->rx_channel, spi->dma->rx_request); + EDMA_CreateHandle(&spi->dma->rx_edma, edma_base, spi->dma->rx_channel); + + EDMA_SetChannelMux(edma_base, spi->dma->tx_channel, spi->dma->tx_request); + EDMA_CreateHandle(&spi->dma->tx_edma, edma_base, spi->dma->tx_channel); +#else DMAMUX_SetSource(DMAMUX, spi->dma->rx_channel, spi->dma->rx_request); DMAMUX_EnableChannel(DMAMUX, spi->dma->rx_channel); EDMA_CreateHandle(&spi->dma->rx_edma, DMA0, spi->dma->rx_channel); @@ -256,13 +336,14 @@ static void lpspi_dma_config(struct imxrt_spi *spi) DMAMUX_SetSource(DMAMUX, spi->dma->tx_channel, spi->dma->tx_request); DMAMUX_EnableChannel(DMAMUX, spi->dma->tx_channel); EDMA_CreateHandle(&spi->dma->tx_edma, DMA0, spi->dma->tx_channel); +#endif LPSPI_MasterTransferCreateHandleEDMA(spi->base, - &spi->dma->spi_edma, - edma_xfer_callback, - spi, - &spi->dma->rx_edma, - &spi->dma->tx_edma); + &spi->dma->spi_edma, + edma_xfer_callback, + spi, + &spi->dma->rx_edma, + &spi->dma->tx_edma); LOG_D("%s dma config done\n", spi->bus_name); #endif @@ -279,21 +360,21 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config spi = (struct imxrt_spi *)(device->bus->parent.user_data); RT_ASSERT(spi != RT_NULL); - if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) + if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) { return -RT_EINVAL; } LPSPI_MasterGetDefaultConfig(&masterConfig); - if(cfg->max_hz > 40*1000*1000) + if (cfg->max_hz > 40 * 1000 * 1000) { - cfg->max_hz = 40*1000*1000; + cfg->max_hz = 40 * 1000 * 1000; } - masterConfig.baudRate = cfg->max_hz; + masterConfig.baudRate = cfg->max_hz; masterConfig.bitsPerFrame = cfg->data_width; - if(cfg->mode & RT_SPI_MSB) + if (cfg->mode & RT_SPI_MSB) { masterConfig.direction = kLPSPI_MsbFirst; } @@ -302,7 +383,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config masterConfig.direction = kLPSPI_LsbFirst; } - if(cfg->mode & RT_SPI_CPHA) + if (cfg->mode & RT_SPI_CPHA) { masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; } @@ -311,7 +392,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; } - if(cfg->mode & RT_SPI_CPOL) + if (cfg->mode & RT_SPI_CPOL) { masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; } @@ -321,25 +402,32 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config } masterConfig.whichPcs = kLPSPI_Pcs0; -#if defined(SOC_IMXRT1170_SERIES) - freq = CLOCK_GetFreqFromObs(spi->masterclock, 2); - LPSPI_MasterInit(spi->base, &masterConfig, freq); +#if defined(SOC_IMXRT1180_SERIES) || defined(SOC_IMXRT1170_SERIES) + LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq(spi)); +#ifndef BSP_USING_BLOCKING_SPI + if (RT_TRUE == spi->dma_flag) + { + lpspi_dma_config(spi); + } + else + { + lpspi_normal_config(spi); + } +#endif #else - masterConfig.pinCfg = kLPSPI_SdiInSdoOut; - masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; - masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.pinCfg = kLPSPI_SdiInSdoOut; + masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; - LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq()); + LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq(spi)); spi->base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; - #endif - return RT_EOK; } -static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { lpspi_transfer_t transfer; status_t status; @@ -350,18 +438,19 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * struct imxrt_spi *spi = (struct imxrt_spi *)(device->bus->parent.user_data); struct imxrt_sw_spi_cs *cs = device->parent.user_data; - if(message->cs_take) + if (message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } transfer.dataSize = message->length; - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); - transfer.configFlags = - kLPSPI_MasterPcs0 | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; - if(RT_FALSE == spi->dma_flag) + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + + if (RT_FALSE == spi->dma_flag) { + /* Non-DMA path: byte-swap and PCS-continuous are safe for interrupt/polling mode. */ + transfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; #ifdef BSP_USING_BLOCKING_SPI status = LPSPI_MasterTransferBlocking(spi->base, &transfer); rt_sem_release(spi->xfer_sem); @@ -372,29 +461,32 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * else { #ifdef BSP_USING_DMA - status = LPSPI_MasterTransferEDMA(spi->base,&spi->dma->spi_edma,&transfer); + /* DMA path: do NOT use kLPSPI_MasterByteSwap - the EDMA driver packs 8-bit + * frames into 32-bit FIFO words; byte-swap reverses order within each word + * and corrupts data after the first word boundary. Use plain Pcs0 only. */ + transfer.configFlags = kLPSPI_MasterPcs0; + status = LPSPI_MasterTransferEDMA(spi->base, &spi->dma->spi_edma, &transfer); #endif } rt_sem_take(spi->xfer_sem, RT_WAITING_FOREVER); - if(message->cs_release) + if (message->cs_release) { rt_pin_write(cs->pin, PIN_HIGH); } if (status != kStatus_Success) { - LOG_E("%s transfer error : %d", spi->bus_name,status); + LOG_E("%s transfer error : %d", spi->bus_name, status); message->length = 0; } return message->length; } -static struct rt_spi_ops imxrt_spi_ops = -{ +static struct rt_spi_ops imxrt_spi_ops = { .configure = spi_configure, - .xfer = spixfer + .xfer = spixfer }; int rt_hw_spi_bus_init(void) @@ -409,8 +501,14 @@ int rt_hw_spi_bus_init(void) lpspis[i].spi_bus.parent.user_data = &lpspis[i]; ret = rt_spi_bus_register(&lpspis[i].spi_bus, lpspis[i].bus_name, &imxrt_spi_ops); + /* For RT1180/RT1170: handle setup is deferred to spi_configure() after + * LPSPI_MasterInit() enables the peripheral clock gate. Calling it here + * (before any spi_configure) would access an un-clocked peripheral and + * cause a HardFault. + * For other platforms the handle is set up here as before. */ +#if !defined(SOC_IMXRT1180_SERIES) && !defined(SOC_IMXRT1170_SERIES) #ifndef BSP_USING_BLOCKING_SPI - if(RT_TRUE == lpspis[i].dma_flag) + if (RT_TRUE == lpspis[i].dma_flag) { lpspi_dma_config(&lpspis[i]); } @@ -419,6 +517,7 @@ int rt_hw_spi_bus_init(void) lpspi_normal_config(&lpspis[i]); } #endif +#endif char sem_name[RT_NAME_MAX]; rt_sprintf(sem_name, "%s_s", lpspis[i].bus_name); lpspis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); @@ -426,6 +525,6 @@ int rt_hw_spi_bus_init(void) return ret; } -INIT_BOARD_EXPORT(rt_hw_spi_bus_init); +INIT_DEVICE_EXPORT(rt_hw_spi_bus_init); #endif /* BSP_USING_SPI */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c index 24edb9f88e..67308dc3b5 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c @@ -13,7 +13,7 @@ #ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.clock_timer" +#define LOG_TAG "drv.clock_timer" #include <drv_log.h> #include <rtdevice.h> @@ -40,13 +40,13 @@ /* The effective GPT input clock after root/prescaler configuration. * 1170: 24 MHz root / 3 = 8 MHz; 1180: 240 MHz root / 3 = 80 MHz. */ #if defined(SOC_IMXRT1180_SERIES) -#define IMXRT_GPT_MAXFREQ (80000000U) +#define IMXRT_GPT_MAXFREQ (80000000U) #elif defined(SOC_IMXRT1170_SERIES) -#define IMXRT_GPT_MAXFREQ (8000000U) +#define IMXRT_GPT_MAXFREQ (8000000U) #else -#define IMXRT_GPT_MAXFREQ (25000000U) +#define IMXRT_GPT_MAXFREQ (25000000U) #endif -#define IMXRT_GPT_MINFREQ (1U) +#define IMXRT_GPT_MINFREQ (1U) static void NVIC_Configuration(void) { @@ -135,22 +135,22 @@ static void imxrt_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) if (state == 1) { - #if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) - #ifdef BSP_USING_CLOCK_TIMER1 +#if defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES) +#ifdef BSP_USING_CLOCK_TIMER1 /*Clock setting for GPT*/ CLOCK_SetRootClockMux(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); - #endif - #ifdef BSP_USING_CLOCK_TIMER2 +#endif +#ifdef BSP_USING_CLOCK_TIMER2 /*Clock setting for GPT*/ CLOCK_SetRootClockMux(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); - #endif - #else +#endif +#else /*Clock setting for GPT*/ CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); - #endif +#endif /* Initialize GPT module by default config */ GPT_GetDefaultConfig(&gptConfig); @@ -198,8 +198,7 @@ static void imxrt_clock_timer_stop(rt_clock_timer_t *timer) GPT_StopTimer(clock_timer_dev); } -static const struct rt_clock_timer_ops imxrt_clock_timer_ops = -{ +static const struct rt_clock_timer_ops imxrt_clock_timer_ops = { .init = imxrt_clock_timer_init, .start = imxrt_clock_timer_start, .stop = imxrt_clock_timer_stop, @@ -207,8 +206,7 @@ static const struct rt_clock_timer_ops imxrt_clock_timer_ops = .control = imxrt_clock_timer_control, }; -static const struct rt_clock_timer_info imxrt_clock_timer_info = -{ +static const struct rt_clock_timer_info imxrt_clock_timer_info = { IMXRT_GPT_MAXFREQ, /* the maximum count frequency can be set */ IMXRT_GPT_MINFREQ, /* the minimum count frequency can be set */ 0xFFFFFFFF, @@ -229,7 +227,7 @@ int rt_hw_clock_timer_init(void) #ifdef BSP_USING_CLOCK_TIMER1 GPT_timer1.info = &imxrt_clock_timer_info; - GPT_timer1.ops = &imxrt_clock_timer_ops; + GPT_timer1.ops = &imxrt_clock_timer_ops; ret = rt_clock_timer_register(&GPT_timer1, "gpt1", GPT1); if (ret != RT_EOK) diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index eab245e79c..cdb2d6542a 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -8,6 +8,7 @@ * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function * 2026-4-29 Ran add RT1180 support + * 2026-8-12 Ran add RT1180 DMA (edma_base, DMA3/DMA4 mux) */ #include <rtthread.h> #ifdef BSP_USING_LPUART @@ -74,6 +75,11 @@ struct dma_rx_config dma_request_source_t request; rt_uint8_t channel; rt_uint32_t last_index; +#ifdef SOC_IMXRT1180_SERIES + EDMA_Type *edma_base; +#else + DMA_Type *edma_base; +#endif }; struct dma_tx_config @@ -82,6 +88,11 @@ struct dma_tx_config lpuart_edma_handle_t uart_edma; dma_request_source_t request; rt_uint8_t channel; +#ifdef SOC_IMXRT1180_SERIES + EDMA_Type *edma_base; +#else + DMA_Type *edma_base; +#endif }; #endif @@ -248,137 +259,276 @@ static struct imxrt_uart uarts[] = { static void uart_get_dma_config(void) { +#ifdef SOC_IMXRT1180_SERIES + /* RT1180: LPUART1-8, 11-12 are served by DMA3; LPUART9-10 are served by DMA4. + * Request source constants follow the kDma3RequestMux / kDma4RequestMux naming. */ #ifdef BSP_LPUART1_RX_USING_DMA - static struct dma_rx_config uart1_dma_rx = { .request = kDmaRequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart1_dma_rx = { .request = kDma3RequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART1_INDEX].dma_rx = &uart1_dma_rx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART1_TX_USING_DMA - static struct dma_tx_config uart1_dma_tx = { .request = kDmaRequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL }; + static struct dma_tx_config uart1_dma_tx = { .request = kDma3RequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART1_INDEX].dma_tx = &uart1_dma_tx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART2_RX_USING_DMA - static struct dma_rx_config uart2_dma_rx = { .request = kDmaRequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart2_dma_rx = { .request = kDma3RequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART2_INDEX].dma_rx = &uart2_dma_rx; uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART2_TX_USING_DMA - static struct dma_tx_config uart2_dma_tx = { .request = kDmaRequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL }; + static struct dma_tx_config uart2_dma_tx = { .request = kDma3RequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART2_INDEX].dma_tx = &uart2_dma_tx; uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART3_RX_USING_DMA - static struct dma_rx_config uart3_dma_rx = { .request = kDmaRequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart3_dma_rx = { .request = kDma3RequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART3_INDEX].dma_rx = &uart3_dma_rx; uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART3_TX_USING_DMA - static struct dma_tx_config uart3_dma_tx = { .request = kDmaRequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL }; + static struct dma_tx_config uart3_dma_tx = { .request = kDma3RequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART3_INDEX].dma_tx = &uart3_dma_tx; uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART4_RX_USING_DMA - static struct dma_rx_config uart4_dma_rx = { .request = kDmaRequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart4_dma_rx = { .request = kDma3RequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART4_INDEX].dma_rx = &uart4_dma_rx; uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART4_TX_USING_DMA - static struct dma_tx_config uart4_dma_tx = { .request = kDmaRequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL }; + static struct dma_tx_config uart4_dma_tx = { .request = kDma3RequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART4_INDEX].dma_tx = &uart4_dma_tx; uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART5_RX_USING_DMA - static struct dma_rx_config uart5_dma_rx = { .request = kDmaRequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart5_dma_rx = { .request = kDma3RequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART5_INDEX].dma_rx = &uart5_dma_rx; uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART5_TX_USING_DMA - static struct dma_tx_config uart5_dma_tx = { .request = kDmaRequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL }; + static struct dma_tx_config uart5_dma_tx = { .request = kDma3RequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART5_INDEX].dma_tx = &uart5_dma_tx; uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART6_RX_USING_DMA - static struct dma_rx_config uart6_dma_rx = { .request = kDmaRequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart6_dma_rx = { .request = kDma3RequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART6_INDEX].dma_rx = &uart6_dma_rx; uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART6_TX_USING_DMA - static struct dma_tx_config uart6_dma_tx = { .request = kDmaRequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL }; + static struct dma_tx_config uart6_dma_tx = { .request = kDma3RequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART6_INDEX].dma_tx = &uart6_dma_tx; uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART7_RX_USING_DMA - static struct dma_rx_config uart7_dma_rx = { .request = kDmaRequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart7_dma_rx = { .request = kDma3RequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART7_INDEX].dma_rx = &uart7_dma_rx; uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART7_TX_USING_DMA - static struct dma_tx_config uart7_dma_tx = { .request = kDmaRequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL }; + static struct dma_tx_config uart7_dma_tx = { .request = kDma3RequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART7_INDEX].dma_tx = &uart7_dma_tx; uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART8_RX_USING_DMA - static struct dma_rx_config uart8_dma_rx = { .request = kDmaRequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart8_dma_rx = { .request = kDma3RequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART8_INDEX].dma_rx = &uart8_dma_rx; uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART8_TX_USING_DMA - static struct dma_tx_config uart8_dma_tx = { .request = kDmaRequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL }; + static struct dma_tx_config uart8_dma_tx = { .request = kDma3RequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART8_INDEX].dma_tx = &uart8_dma_tx; uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART9_RX_USING_DMA - static struct dma_rx_config uart9_dma_rx = { .request = kDmaRequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart9_dma_rx = { .request = kDma4RequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA4 }; uarts[LPUART9_INDEX].dma_rx = &uart9_dma_rx; uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART9_TX_USING_DMA - static struct dma_tx_config uart9_dma_tx = { .request = kDmaRequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL }; + static struct dma_tx_config uart9_dma_tx = { .request = kDma4RequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA4 }; uarts[LPUART9_INDEX].dma_tx = &uart9_dma_tx; uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART10_RX_USING_DMA - static struct dma_rx_config uart10_dma_rx = { .request = kDmaRequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart10_dma_rx = { .request = kDma4RequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA4 }; uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx; uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART10_TX_USING_DMA - static struct dma_tx_config uart10_dma_tx = { .request = kDmaRequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL }; + static struct dma_tx_config uart10_dma_tx = { .request = kDma4RequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA4 }; uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx; uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART11_RX_USING_DMA - static struct dma_rx_config uart11_dma_rx = { .request = kDmaRequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart11_dma_rx = { .request = kDma3RequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART11_INDEX].dma_rx = &uart11_dma_rx; uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART11_TX_USING_DMA - static struct dma_tx_config uart11_dma_tx = { .request = kDmaRequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL }; + static struct dma_tx_config uart11_dma_tx = { .request = kDma3RequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART11_INDEX].dma_tx = &uart11_dma_tx; uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif #ifdef BSP_LPUART12_RX_USING_DMA - static struct dma_rx_config uart12_dma_rx = { .request = kDmaRequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0 }; + static struct dma_rx_config uart12_dma_rx = { .request = kDma3RequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx; uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART12_TX_USING_DMA - static struct dma_tx_config uart12_dma_tx = { .request = kDmaRequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL }; + static struct dma_tx_config uart12_dma_tx = { .request = kDma3RequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 }; uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx; uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif + +#else /* non-RT1180: single DMA0 with DMAMUX */ + +#ifdef BSP_LPUART1_RX_USING_DMA + static struct dma_rx_config uart1_dma_rx = { .request = kDmaRequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART1_INDEX].dma_rx = &uart1_dma_rx; + uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART1_TX_USING_DMA + static struct dma_tx_config uart1_dma_tx = { .request = kDmaRequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART1_INDEX].dma_tx = &uart1_dma_tx; + uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART2_RX_USING_DMA + static struct dma_rx_config uart2_dma_rx = { .request = kDmaRequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART2_INDEX].dma_rx = &uart2_dma_rx; + uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART2_TX_USING_DMA + static struct dma_tx_config uart2_dma_tx = { .request = kDmaRequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART2_INDEX].dma_tx = &uart2_dma_tx; + uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART3_RX_USING_DMA + static struct dma_rx_config uart3_dma_rx = { .request = kDmaRequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART3_INDEX].dma_rx = &uart3_dma_rx; + uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART3_TX_USING_DMA + static struct dma_tx_config uart3_dma_tx = { .request = kDmaRequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART3_INDEX].dma_tx = &uart3_dma_tx; + uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART4_RX_USING_DMA + static struct dma_rx_config uart4_dma_rx = { .request = kDmaRequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART4_INDEX].dma_rx = &uart4_dma_rx; + uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART4_TX_USING_DMA + static struct dma_tx_config uart4_dma_tx = { .request = kDmaRequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART4_INDEX].dma_tx = &uart4_dma_tx; + uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART5_RX_USING_DMA + static struct dma_rx_config uart5_dma_rx = { .request = kDmaRequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART5_INDEX].dma_rx = &uart5_dma_rx; + uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART5_TX_USING_DMA + static struct dma_tx_config uart5_dma_tx = { .request = kDmaRequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART5_INDEX].dma_tx = &uart5_dma_tx; + uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART6_RX_USING_DMA + static struct dma_rx_config uart6_dma_rx = { .request = kDmaRequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART6_INDEX].dma_rx = &uart6_dma_rx; + uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART6_TX_USING_DMA + static struct dma_tx_config uart6_dma_tx = { .request = kDmaRequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART6_INDEX].dma_tx = &uart6_dma_tx; + uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART7_RX_USING_DMA + static struct dma_rx_config uart7_dma_rx = { .request = kDmaRequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART7_INDEX].dma_rx = &uart7_dma_rx; + uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART7_TX_USING_DMA + static struct dma_tx_config uart7_dma_tx = { .request = kDmaRequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART7_INDEX].dma_tx = &uart7_dma_tx; + uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART8_RX_USING_DMA + static struct dma_rx_config uart8_dma_rx = { .request = kDmaRequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART8_INDEX].dma_rx = &uart8_dma_rx; + uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART8_TX_USING_DMA + static struct dma_tx_config uart8_dma_tx = { .request = kDmaRequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART8_INDEX].dma_tx = &uart8_dma_tx; + uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART9_RX_USING_DMA + static struct dma_rx_config uart9_dma_rx = { .request = kDmaRequestMuxLPUART9Rx, .channel = BSP_LPUART9_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART9_INDEX].dma_rx = &uart9_dma_rx; + uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART9_TX_USING_DMA + static struct dma_tx_config uart9_dma_tx = { .request = kDmaRequestMuxLPUART9Tx, .channel = BSP_LPUART9_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART9_INDEX].dma_tx = &uart9_dma_tx; + uarts[LPUART9_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART10_RX_USING_DMA + static struct dma_rx_config uart10_dma_rx = { .request = kDmaRequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART10_TX_USING_DMA + static struct dma_tx_config uart10_dma_tx = { .request = kDmaRequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART11_RX_USING_DMA + static struct dma_rx_config uart11_dma_rx = { .request = kDmaRequestMuxLPUART11Rx, .channel = BSP_LPUART11_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART11_INDEX].dma_rx = &uart11_dma_rx; + uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART11_TX_USING_DMA + static struct dma_tx_config uart11_dma_tx = { .request = kDmaRequestMuxLPUART11Tx, .channel = BSP_LPUART11_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART11_INDEX].dma_tx = &uart11_dma_tx; + uarts[LPUART11_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#ifdef BSP_LPUART12_RX_USING_DMA + static struct dma_rx_config uart12_dma_rx = { .request = kDmaRequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0, .edma_base = DMA0 }; + uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#endif +#ifdef BSP_LPUART12_TX_USING_DMA + static struct dma_tx_config uart12_dma_tx = { .request = kDmaRequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL, .edma_base = DMA0 }; + uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#endif + +#endif /* SOC_IMXRT1180_SERIES */ } static void uart_isr(struct imxrt_uart *uart); @@ -568,7 +718,16 @@ static void uart_isr(struct imxrt_uart *uart) LPUART_ClearStatusFlags(uart->uart_base, kLPUART_IdleLineFlag); level = rt_hw_interrupt_disable(); - total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(DMA0, uart->dma_rx->channel); +#ifdef SOC_IMXRT1180_SERIES + /* EDMA4 (RT1180): read CITER from tcdBase TCD. */ + total_index = EDMA_TCD_CITER(&uart->dma_rx->edma.tcdBase[uart->dma_rx->edma.channel], + EDMA_TCD_TYPE(uart->dma_rx->edma.base)) & + 0x7FFFU; +#else + /* Classic EDMA: read CITER directly from TCD hardware register. */ + total_index = (rt_size_t)(uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].CITER_ELINKNO & 0x7FFFU); +#endif + total_index = uart->serial.config.bufsz - total_index; if (total_index > uart->dma_rx->last_index) { recv_len = total_index - uart->dma_rx->last_index; @@ -605,10 +764,10 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer { level = rt_hw_interrupt_disable(); - if ((EDMA_GetChannelStatusFlags(DMA0, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U) + if ((EDMA_GetChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U) { /* clear full interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel, kEDMA_DoneFlag); + EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_DoneFlag); recv_len = uart->serial.config.bufsz - uart->dma_rx->last_index; uart->dma_rx->last_index = 0; @@ -616,9 +775,14 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer else { /* clear half interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel, kEDMA_InterruptFlag); + EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_InterruptFlag); - total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(DMA0, uart->dma_rx->channel); +#ifdef SOC_IMXRT1180_SERIES + total_index = EDMA_TCD_CITER(&handle->tcdBase[handle->channel], EDMA_TCD_TYPE(handle->base)) & 0x7FFFU; +#else + total_index = (rt_size_t)(handle->base->TCD[handle->channel].CITER_ELINKNO & 0x7FFFU); +#endif + total_index = uart->serial.config.bufsz - total_index; if (total_index > uart->dma_rx->last_index) { recv_len = total_index - uart->dma_rx->last_index; @@ -649,6 +813,20 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } } +#ifdef SOC_IMXRT1180_SERIES +static void imxrt_edma_mux_setup(EDMA_Type *base, rt_uint8_t channel, dma_request_source_t request) +{ + EDMA_SetChannelMux(base, channel, request); +} +#else +static void imxrt_edma_mux_setup(DMA_Type *base, rt_uint8_t channel, dma_request_source_t request) +{ + (void)base; + DMAMUX_SetSource(DMAMUX, channel, (uint8_t)(uint32_t)request); + DMAMUX_EnableChannel(DMAMUX, channel); +} +#endif + static void imxrt_dma_rx_config(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); @@ -656,15 +834,9 @@ static void imxrt_dma_rx_config(struct imxrt_uart *uart) edma_transfer_config_t xferConfig; struct rt_serial_rx_fifo *rx_fifo; -#ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); -#else - /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); -#endif + imxrt_edma_mux_setup(uart->dma_rx->edma_base, uart->dma_rx->channel, uart->dma_rx->request); - EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); + EDMA_CreateHandle(&uart->dma_rx->edma, uart->dma_rx->edma_base, uart->dma_rx->channel); EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; @@ -679,10 +851,16 @@ static void imxrt_dma_rx_config(struct imxrt_uart *uart) kEDMA_PeripheralToMemory); EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); - EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); - EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); - /* complement to adjust final destination address */ - uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); + EDMA_EnableChannelInterrupts(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(uart->dma_rx->edma_base, uart->dma_rx->channel, false); +#ifdef SOC_IMXRT1180_SERIES + /* EDMA4 (RT1180): set DLAST_SGA for circular DMA wrap-around. */ + EDMA_TCD_DLAST_SGA(&uart->dma_rx->edma.tcdBase[uart->dma_rx->edma.channel], + EDMA_TCD_TYPE(uart->dma_rx->edma.base)) = -(int32_t)(uart->serial.config.bufsz); +#else + /* Classic EDMA (RT1052/RT1064 etc.): write DLAST_SGA directly via TCD register. */ + uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(int32_t)(uart->serial.config.bufsz); +#endif EDMA_StartTransfer(&uart->dma_rx->edma); LPUART_EnableRxDMA(uart->uart_base, true); @@ -697,15 +875,9 @@ static void imxrt_dma_tx_config(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); -#ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); -#else - /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); -#endif + imxrt_edma_mux_setup(uart->dma_tx->edma_base, uart->dma_tx->channel, uart->dma_tx->request); - EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); + EDMA_CreateHandle(&uart->dma_tx->edma, uart->dma_tx->edma_base, uart->dma_tx->channel); LPUART_TransferCreateHandleEDMA(uart->uart_base, &uart->dma_tx->uart_edma, @@ -923,11 +1095,11 @@ static int imxrt_getc(struct rt_serial_device *serial) } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) -rt_size_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +rt_ssize_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) { struct imxrt_uart *uart; lpuart_transfer_t xfer; - rt_size_t xfer_size = 0; + rt_ssize_t xfer_size = 0; RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct imxrt_uart, serial); diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c index 4be908ffc6..ea7bd49ae7 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c @@ -359,18 +359,20 @@ static void uart_isr(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); - if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag) + /* Check and clear overrun first: when overrun is set, the RX data register + * content is unreliable on LPUART. Clear before reading to avoid consuming + * a corrupted byte. */ + if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag) + { + LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag); + } + else if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag) { uint8_t ch = LPUART_ReadByte(uart->uart_base); rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_PUTC, &ch); rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); } - if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag) - { - LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag); - } - if ((LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag) && (LPUART_GetEnabledInterrupts(uart->uart_base) & kLPUART_TxDataRegEmptyInterruptEnable)) { @@ -667,6 +669,11 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: + /* Disable both the LPUART interrupt sources and the NVIC line so that + * no RX/TX interrupts fire after the device is closed. */ + LPUART_DisableInterrupts(uart->uart_base, + kLPUART_RxDataRegFullInterruptEnable | + kLPUART_TxDataRegEmptyInterruptEnable); DisableIRQ(uart->irqn); break; |