Optimize System Resource Allocation for ra6w1

8 files changed, 311 insertions, 16 deletions

diff --git a/bsp/renesas/ra6w1-ek/.config b/bsp/renesas/ra6w1-ek/.config
index dfc0413d54..8f7e06ceab 100644
--- a/bsp/renesas/ra6w1-ek/.config
+++ b/bsp/renesas/ra6w1-ek/.config
@@ -107,7 +107,7 @@ CONFIG_SOC_R7SA6W1CED=y
 # end of rt_strnlen options
 # end of klibc options
 
-CONFIG_RT_NAME_MAX=12
+CONFIG_RT_NAME_MAX=32
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_SMART is not set
@@ -126,10 +126,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
 # CONFIG_RT_USING_HOOKLIST is not set
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_IDLE_THREAD_STACK_SIZE=512
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set
 # CONFIG_RT_USING_CPU_USAGE_TRACER is not set
 
@@ -171,7 +171,7 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_NOHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
-# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP_ISR=y
 CONFIG_RT_USING_HEAP=y
 # end of Memory Management
 
@@ -183,7 +183,7 @@ CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
 CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
-CONFIG_RT_VER_NUM=0x50300
+CONFIG_RT_VER_NUM=0x50301
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # end of RT-Thread Kernel
@@ -229,7 +229,12 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 # CONFIG_RT_USING_DFS is not set
 # end of DFS: device virtual file system
 
-# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_FAL=y
+CONFIG_FAL_USING_DEBUG=y
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+# CONFIG_FAL_USING_SFUD_PORT is not set
+CONFIG_FAL_DEV_NAME_MAX=24
+CONFIG_FAL_DEV_BLK_MAX=6
 
 #
 # Device Drivers
@@ -238,7 +243,9 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 # CONFIG_RT_USING_DEV_BUS is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=15
 CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_USING_SERIAL_V1 is not set
 CONFIG_RT_USING_SERIAL_V2=y
@@ -1473,7 +1480,7 @@ CONFIG_BSP_UART0_TX_BUFSIZE=0
 #
 # On-chip Peripheral Port
 #
-# CONFIG_BSP_USING_OSPI_FLASH is not set
+CONFIG_BSP_USING_OSPI_FLASH=y
 # CONFIG_BSP_USING_QSPI_PSRAM is not set
 # end of On-chip Peripheral Port
 # end of Hardware Drivers Config
diff --git a/bsp/renesas/ra6w1-ek/board/ports/ra6w1_pin_ext.h b/bsp/renesas/ra6w1-ek/board/ports/ra6w1_pin_ext.h
new file mode 100644
index 0000000000..43b37b0157
--- /dev/null
+++ b/bsp/renesas/ra6w1-ek/board/ports/ra6w1_pin_ext.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2026, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2026-09-21     rcitach           INITIAL VERSION
+ */
+
+
+#ifndef __RA6W1_PIN_EXT_H__
+#define __RA6W1_PIN_EXT_H__
+
+#ifdef EXTRA_IO_INCLUDE
+#define RA6W1_PIN_INCLUDE_FILE_(name) <name>
+#define RA6W1_PIN_INCLUDE_FILE(name)  RA6W1_PIN_INCLUDE_FILE_(name)
+#include RA6W1_PIN_INCLUDE_FILE(EXTRA_IO_INCLUDE)
+#undef RA6W1_PIN_INCLUDE_FILE
+#undef RA6W1_PIN_INCLUDE_FILE_
+#endif
+
+#ifndef RA6W1_PIN_CFG_EXTRA
+#define RA6W1_PIN_CFG_EXTRA
+#endif
+
+#ifndef RA6W1_PIN_NAME_EXTRA
+#define RA6W1_PIN_NAME_EXTRA
+#endif
+
+#ifndef RA6W1_PIN_COUNT_EXTRA
+#define RA6W1_PIN_COUNT_EXTRA 0
+#endif
+
+#endif /* __RA6W1_PIN_EXT_H__ */
diff --git a/bsp/renesas/ra6w1-ek/ra/SConscript b/bsp/renesas/ra6w1-ek/ra/SConscript
index 79ab1ceacf..baec95f214 100644
--- a/bsp/renesas/ra6w1-ek/ra/SConscript
+++ b/bsp/renesas/ra6w1-ek/ra/SConscript
@@ -14,7 +14,9 @@ CPPPATH = [cwd + "/arm/CMSIS_6/CMSIS/Core/Include",
         cwd + "/fsp/src/bsp_w/cmsis/Device/RENESAS/Include",
         cwd + "/fsp/src/bsp_w/mcu/all",
         cwd + "/fsp/src/bsp_w/mcu/ra6w1",
-        cwd + "/fsp/src/bsp_w/mcu/ra6w1/config"]
+        cwd + "/fsp/src/bsp_w/mcu/ra6w1/config",
+        cwd + "/fsp/src/bsp_w/mcu/ra6w1/config/include",
+]
 
 src += Glob("./board/rrq61xxx_evb/*.c")
 src += Glob("./fsp/src/bsp_w/cmsis/Device/RENESAS/Source/*.c")
diff --git a/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c b/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c
index 97c34d11d7..9147dc86e8 100644
--- a/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c
+++ b/bsp/renesas/ra6w1-ek/rafw_gen/pin_data.c
@@ -6,6 +6,7 @@
 #include "bsp_api.h"
 #include "hal_data.h"
 #include "r_gpio_w.h"
+#include "ra6w1_pin_ext.h"
 
 ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
 {
@@ -258,6 +259,7 @@ ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
                    GPIO_W_CFG_PORT_DIRECTION_INPUT | GPIO_W_CFG_SLW_FAST,
     },
 #endif
+RA6W1_PIN_CFG_EXTRA
     {
         .pin = BSP_IO_PORT_01_PIN_16,
         .pin_cfg = GPIO_W_CFG_PERIPHERAL_PIN | GPIO_W_CFG_PORT_DIRECTION_INPUT |
@@ -355,6 +357,7 @@ static const char * const g_bsp_pin_cfg_name[] =
     "qspi.io2",
     "qspi.io3",
 #endif
+RA6W1_PIN_NAME_EXTRA
     "swd.swclk",
     "swd.swdio",
 };
@@ -640,7 +643,7 @@ void ra_w_pin_config_init(void)
 #ifdef BSP_USING_QSPI
     index += 6;
 #endif
-
+    index += RA6W1_PIN_COUNT_EXTRA;
     /* SWD pins are fixed and are always the last two entries. */
     index += 2;
     if (index != RA_W_PIN_CFG_COUNT)
diff --git a/bsp/renesas/ra6w1-ek/rtconfig.h b/bsp/renesas/ra6w1-ek/rtconfig.h
index faaddf945a..cd2c5b1844 100644
--- a/bsp/renesas/ra6w1-ek/rtconfig.h
+++ b/bsp/renesas/ra6w1-ek/rtconfig.h
@@ -63,7 +63,7 @@
 
 /* end of rt_strnlen options */
 /* end of klibc options */
-#define RT_NAME_MAX 12
+#define RT_NAME_MAX 32
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
@@ -74,10 +74,10 @@
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
+#define IDLE_THREAD_STACK_SIZE 512
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_TIMER_THREAD_STACK_SIZE 1024
 
 /* kservice options */
 
@@ -100,6 +100,7 @@
 
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP_ISR
 #define RT_USING_HEAP
 /* end of Memory Management */
 #define RT_USING_DEVICE
@@ -107,7 +108,7 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart0"
 #define RT_USING_CONSOLE_OUTPUT_CTL
-#define RT_VER_NUM 0x50300
+#define RT_VER_NUM 0x50301
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
 /* end of RT-Thread Kernel */
 #define RT_USING_HW_ATOMIC
@@ -142,11 +143,19 @@
 /* DFS: device virtual file system */
 
 /* end of DFS: device virtual file system */
+#define RT_USING_FAL
+#define FAL_USING_DEBUG
+#define FAL_PART_HAS_TABLE_CFG
+#define FAL_DEV_NAME_MAX 24
+#define FAL_DEV_BLK_MAX 6
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 15
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V2
 #define RT_SERIAL_BUF_STRATEGY_OVERWRITE
@@ -430,6 +439,7 @@
 
 /* On-chip Peripheral Port */
 
+#define BSP_USING_OSPI_FLASH
 /* end of On-chip Peripheral Port */
 /* end of Hardware Drivers Config */
 
diff --git a/bsp/renesas/ra6w1-ek/rtconfig.py b/bsp/renesas/ra6w1-ek/rtconfig.py
index 3122a25922..2dc6103f96 100644
--- a/bsp/renesas/ra6w1-ek/rtconfig.py
+++ b/bsp/renesas/ra6w1-ek/rtconfig.py
@@ -40,7 +40,7 @@ if PLATFORM == 'gcc':
     DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
     CFLAGS = DEVICE + ' -Dgcc'
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp.ld -L script/'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler,--no-warn-execstack -T script/fsp.ld -L script/'
 
     CPATH = ''
     LPATH = ''
diff --git a/bsp/renesas/ra6w1-ek/script/fsp.ld b/bsp/renesas/ra6w1-ek/script/fsp.ld
index 55e7ceb358..dd22bb3dfd 100644
--- a/bsp/renesas/ra6w1-ek/script/fsp.ld
+++ b/bsp/renesas/ra6w1-ek/script/fsp.ld
@@ -1,4 +1,5 @@
 INCLUDE memory_regions.ld
+INCLUDE rom_code_gcc.symbols
 MEMORY
 {
 	RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
@@ -382,4 +383,3 @@ PROVIDE( _end = __HeapBase);
 PROVIDE( __end__ = __HeapBase);
 
 ASSERT(__HeapBase <= __HeapLimit, "RAM overflow: no space left for RT-Thread heap");
-
diff --git a/bsp/renesas/ra6w1-ek/script/rom_code_gcc.symbols b/bsp/renesas/ra6w1-ek/script/rom_code_gcc.symbols
new file mode 100644
index 0000000000..f4b509cb85
--- /dev/null
+++ b/bsp/renesas/ra6w1-ek/script/rom_code_gcc.symbols
@@ -0,0 +1,238 @@
+/**************************************************
+ * Crypto-related symbols in ROM
+ **************************************************/
+CC_PalVerifyCertValidity         = 0x0f042901 ;
+CCCertFieldsParse                = 0x0f0403c5 ;
+SBRT_SwVersionGet                = 0x0f044675 ;
+CC_BsvOTPWordRead                = 0x0f04184d ;
+ProcessAesCcm                    = 0x0f04353d ;
+UTIL_X509VerifyPubKey            = 0x0f044b0d ;
+SBRT_SHA256                      = 0x0f044605 ;
+UTIL_MemCmp                      = 0x0f0447e1 ;
+SBRT_CryptoImageInit             = 0x0f044349 ;
+CC_BsvOTPWordWrite               = 0x0f04188d ;
+SBRT_OTPWordRead                 = 0x0f044519 ;
+CCCertSecDbgParse                = 0x0f0404ed ;
+__rom_CC_BsvCoreClkGatingEnable  = 0x0f040f7d ;
+RSA_PKA_SetRegsMapTab            = 0x0f043db9 ;
+InitBsvAes                       = 0x0f042ec9 ;
+BsvAes                           = 0x0f040041 ;
+BsvCryptoImageInit               = 0x0f0400a9 ;
+CC_BsvPrivModeSet                = 0x0f0419d9 ;
+CC_BsvSecModeSet                 = 0x0f041cf5 ;
+SBRT_HalWaitInterrupt            = 0x0f044401 ;
+__rom_CC_BsvLcsGetAndInit        = 0x0f0415d9 ;
+SBROM_CryptoFinishDriver         = 0x0f043fd9 ;
+InitContextToSha256              = 0x0f043021 ;
+CC_BsvSHA256                     = 0x0f041c8d ;
+CCSbCalcPublicKeyHASH            = 0x0f0409cd ;
+SBRT_RSA_PSS_Verify              = 0x0f044521 ;
+UTIL_X509VerifySubjectName       = 0x0f044d21 ;
+CCCommonKeyCertVerify            = 0x0f040985 ;
+FreeHash                         = 0x0f042e39 ;
+_RSA_PKA_ExecOperation           = 0x0f044d55 ;
+SBRT_LcsGet                      = 0x0f0444e1 ;
+NVM_SetSwVersion                 = 0x0f043239 ;
+CC_BsvFatalErrorSet              = 0x0f040f95 ;
+SBROM_CryptoInitDriver           = 0x0f044019 ;
+CCSbVerifySignature              = 0x0f040c55 ;
+FinishAesCcm                     = 0x0f042b69 ;
+CC_BsvAesCcm                     = 0x0f040cb9 ;
+UTIL_X509VerifyIssuerName        = 0x0f044aed ;
+CCCommonContentCertVerify        = 0x0f040841 ;
+InitBsvHash                      = 0x0f042f19 ;
+CCSbSetNvCounter                 = 0x0f040bed ;
+CC_BsvOemAssetProvisioningOpen   = 0x0f0418d9 ;
+get_romcrypto_info               = 0x0f044e8d ;
+SBRT_HalClearInterruptBit        = 0x0f0443f1 ;
+CC_BsvSwVersionGet               = 0x0f0424b9 ;
+SBRT_PubKeyHashGet               = 0x0f04451d ;
+ProcessAes                       = 0x0f043269 ;
+UTIL_X509GetSignature            = 0x0f0448b5 ;
+CC_BsvRMAModeEnable              = 0x0f041bbd ;
+UTIL_Asn1ReadItemVerifyTagFW     = 0x0f04476d ;
+SB_HalClearInterruptBit          = 0x0f044679 ;
+FinishHash                       = 0x0f042d0d ;
+UTIL_ReverseWordsBuff            = 0x0f044891 ;
+SBRT_ReverseMemCopy              = 0x0f0445c9 ;
+ProcessBsvHash                   = 0x0f0439ad ;
+NVM_GetSwVersion                 = 0x0f0431c5 ;
+UTIL_ReverseMemCopy              = 0x0f044855 ;
+SBRT_ImageLoadAndVerify          = 0x0f044409 ;
+UTIL_X509VerifyStr               = 0x0f044c89 ;
+SBRT_MemCmp                      = 0x0f0444e5 ;
+SB_HalWaitInterrupt              = 0x0f04468d ;
+CCSbVerifyNvCounter              = 0x0f040c09 ;
+SBROM_CryptoUpdateBlockDriver    = 0x0f0441f1 ;
+FinishBsvAes                     = 0x0f042c11 ;
+FreeAes                          = 0x0f042dd1 ;
+SBRT_CryptoImageUpdate           = 0x0f044399 ;
+SBRT_HalMaskInterrupt            = 0x0f0443f9 ;
+FreeBsvHash                      = 0x0f042e09 ;
+FinishBsvHash                    = 0x0f042c61 ;
+certType2SubjectNames            = 0x0f045080 ;
+RSA_PKA_SetRegsSizesTab          = 0x0f043e11 ;
+CCCertValidateSWComps            = 0x0f04053d ;
+ProcessBsvAes                    = 0x0f0436d9 ;
+CC_BsvHashFinish                 = 0x0f040ff1 ;
+get_romcrypto_date               = 0x0f044e85 ;
+CC_DeviceCompleteDisable         = 0x0f0426a1 ;
+FinishAes                        = 0x0f042b19 ;
+CC_BsvPubKeyHashGet              = 0x0f041a45 ;
+NVM_ReadHASHPubKey               = 0x0f0431ed ;
+CC_BsvICVKeyLock                 = 0x0f04108d ;
+CC_BsvSwVersionSet               = 0x0f0425b9 ;
+InitHash                         = 0x0f04303d ;
+RSA_PSS_Verify                   = 0x0f043f89 ;
+CCCertLoadCertificate            = 0x0f04047d ;
+CC_BsvOTPPrivateKeysErase        = 0x0f041665 ;
+RSA_PKA_InitPka                  = 0x0f043d61 ;
+BsvCryptoImageUpdate             = 0x0f040105 ;
+BsvCryptoImageFinish             = 0x0f040089 ;
+RSA_HW_PKI_PKA_FinishPKA         = 0x0f043d4d ;
+RSA_HW_PKI_PKA_CopyDataFromPkaReg = 0x0f043c39 ;
+CC_SbCertChainVerificationInit   = 0x0f042919 ;
+CC_BsvKeyDerivation              = 0x0f0413b9 ;
+CC_BsvHashInit                   = 0x0f04104d ;
+SBRT_CryptoImageFinish           = 0x0f044329 ;
+CC_BsvInit                       = 0x0f041275 ;
+RSA_HW_PKI_PKA_CopyDataIntoPkaReg = 0x0f043c89 ;
+CCCommonCertVerify               = 0x0f0406b9 ;
+CC_BsvIcvAssetProvisioningOpen   = 0x0f041175 ;
+LoadDigest                       = 0x0f0430a9 ;
+CC_BsvSecureDebugSet             = 0x0f041d61 ;
+LoadInitialDigest                = 0x0f04311d ;
+UTIL_MemSet                      = 0x0f04482d ;
+RSA_CalcExponent                 = 0x0f043ba5 ;
+CCCertGetUnsignedDataOffset      = 0x0f040465 ;
+__rom_CC_HalTerminate            = 0x0f0427a1 ;
+StoreDigest                      = 0x0f044695 ;
+SB_HalMaskInterrupt              = 0x0f044685 ;
+get_romcrypto_time               = 0x0f044e95 ;
+ProcessHashDrvBsv                = 0x0f043af1 ;
+FreeBsvAes                       = 0x0f042ded ;
+CCSbCalcPublicKeyHASHAndCompare  = 0x0f0409e5 ;
+CC_BsvHashUpdate                 = 0x0f041061 ;
+SB_HalInit                       = 0x0f044681 ;
+CC_BsvICVRMAFlagBitLock          = 0x0f0410f1 ;
+InitAes                          = 0x0f042e79 ;
+UTIL_MemCopy                     = 0x0f044815 ;
+BsvHashAdaptor                   = 0x0f040165 ;
+__rom_init_romcrypto_platform    = 0x0f044e9d ;
+NVM_GetLCS                       = 0x0f0431c1 ;
+CC_BsvSocIDCompute               = 0x0f0423c9 ;
+CCSbImageLoadAndVerify           = 0x0f040a35 ;
+UTIL_Asn1ReadItemVerifyTag       = 0x0f044709 ;
+DischargeDigest                  = 0x0f042a79 ;
+RSA_PSS_Decode                   = 0x0f043e45 ;
+ProcessHash                      = 0x0f043a7d ;
+CC_SbCertVerifySingle            = 0x0f042939 ;
+UTIL_ReverseBuff                 = 0x0f044835 ;
+__rom_CC_HalInit                 = 0x0f042775 ;
+__romcrypto_ram_start__          = 0x200a8d00 ;
+__romcrypto_ram_end__            = 0x200a8d08 ;
+
+/**************************************************
+ * MAC-related symbols in ROM
+ **************************************************/
+dpmtm_calc_dur256us              = 0x0f048045 ;
+RomacStartup                     = 0x0f046005 ;
+dpmtm_init_timer                 = 0x0f049a15 ;
+romac_primitive                  = 0x200a9260 ;
+dpmtm_update_topfunc             = 0x0f04a4ad ;
+dpm_get_adj_period               = 0x0f04762d ;
+dpm_preced_cb                    = 0x200a8d10 ;
+dpm_preced_cb                    = 0x200a8d10 ;
+timp_intf                        = 0x200a9280 ;
+tim_calc_bcncnt                  = 0x0f04da1d ;
+timp_reset_buf                   = 0x0f0537ad ;
+tim_rtm_init                     = 0x0f051509 ;
+timp_perf                        = 0x200a9284 ;
+__rommac_ram_end__               = 0x200aa058 ;
+dpmtm_check_mainst               = 0x0f049649 ;
+timprep_get_func_prep            = 0x0f0539d1 ;
+timprep_get_next_prep_us         = 0x0f053b2d ;
+dpmtm_update_next_timer          = 0x0f04a169 ;
+dpmtm_add_tcpka_timer            = 0x0f049101 ;
+timp_u_0                         = 0x200a9288 ;
+dpmtm_update_timer               = 0x0f04a1f9 ;
+dpm_get_wk_rtclk                 = 0x0f047b75 ;
+dpmtm_add_fb1_timer              = 0x0f048f09 ;
+dpmtm_add_timer                  = 0x0f0491f5 ;
+dpmtm_add_udph_timer             = 0x0f049339 ;
+dpmtm_chk_prio                   = 0x0f0496dd ;
+dpmtm_del_all_timer              = 0x0f049765 ;
+dpmtm_add_bufp_timer             = 0x0f048cb1 ;
+dpmtm_dealloc_no                 = 0x0f0496f1 ;
+dpmtm_push_topback               = 0x0f049e51 ;
+dpmtm_check_topfunc              = 0x0f049695 ;
+dpmtm_move_back                  = 0x0f049a79 ;
+dpmtm_fire_timer                 = 0x0f049781 ;
+dpm_wait_us                      = 0x0f048679 ;
+__rommac_ram_start__             = 0x200a8d10 ;
+dpmtm_peek_timer                 = 0x0f049b0d ;
+dpmtm_handle_timer               = 0x0f0499d9 ;
+dpmtm_remove_completed_timer     = 0x0f049efd ;
+dpmtm_is_empty                   = 0x0f049a45 ;
+dpmtm_check_subst                = 0x0f04966d ;
+dpmtm_remove_subst               = 0x0f049ff5 ;
+timp_w_1                         = 0x200a9294 ;
+dpmtm_remove_func                = 0x0f049f9d ;
+dpmtm_prog_timer                 = 0x0f049bd1 ;
+dpmtm_is_full                    = 0x0f049a5d ;
+timp_set_period                  = 0x0f053849 ;
+timp_check                       = 0x0f0534f1 ;
+dpmtm_pop_timer                  = 0x0f049b39 ;
+dpm_wait_clk                     = 0x0f04864d ;
+timp_get_interface               = 0x0f0535f1 ;
+dpmtm_search_no                  = 0x0f04a089 ;
+timp_update                      = 0x0f053881 ;
+dpmtm_calc_dur2clk               = 0x0f049401 ;
+dpm_get_rtcnt                    = 0x0f0477ad ;
+dpmtm_remove_mainst              = 0x0f049fc9 ;
+dpmtm_calc_time_us               = 0x0f04956d ;
+dpmtm_add_timchk_timer           = 0x0f049191 ;
+timp_set_condition               = 0x0f0537ed ;
+dpmtm_move_front                 = 0x0f049ac5 ;
+dpmtm_search_elapsed             = 0x0f04a045 ;
+dpmtm_check_id                   = 0x0f049625 ;
+dpmtm_get_txcnt_timer            = 0x0f049971 ;
+dpmtm_push_preced_topfunc        = 0x0f049d11 ;
+dpmtm_add_tim_timer              = 0x0f049165 ;
+pdpm                             = 0x200a926c ;
+dpm_update_period                = 0x0f04856d ;
+dpmtm_calc_dur2tick              = 0x0f049479 ;
+dpmtm_add_fb0_timer              = 0x0f048e49 ;
+dpmtm_add_tcpack_timer           = 0x0f049039 ;
+timp_reset                       = 0x0f053765 ;
+dpmtm_update_stclk               = 0x0f04a1ad ;
+dpmtm_set_preced_cb              = 0x0f04a121 ;
+init_romsys_primitives           = 0x0f04b135 ;
+dpmtm_add_setps_timer            = 0x0f049005 ;
+timp_w_0                         = 0x200a9290 ;
+timp_get_interface_data          = 0x0f05362d ;
+dpmtm_precedence_timer           = 0x0f049b51 ;
+timp_get_condition               = 0x0f0535c9 ;
+dpmtm_remove_topfunc             = 0x0f04a021 ;
+dpmtm_get_datacnt_timer          = 0x0f0498fd ;
+timp_init                        = 0x0f053671 ;
+timp_get_performance             = 0x0f053665 ;
+timp_u_1                         = 0x200a928c ;
+dpm_reset_apsync                 = 0x0f047efd ;
+dpm_calc_next_twt                = 0x0f047161 ;
+tim_calc_timcnt                  = 0x0f04da3d ;
+dpmtm_add_ka_timer               = 0x0f048fc9 ;
+dpmtm_check_func                 = 0x0f0495fd ;
+dpmtm_push_topfunc               = 0x0f049ea5 ;
+dpm_restart_rtclk                = 0x0f047f61 ;
+dpmtm_add_tcpchk_timer           = 0x0f04909d ;
+dpmtm_calc_dur2tu                = 0x0f0494e5 ;
+dpmtm_alloc_no                   = 0x0f04939d ;
+timp_get_interface_current       = 0x0f0535fd ;
+dpmtm_calc_dur2us                = 0x0f04952d ;
+dpmtm_push_timer                 = 0x0f049d6d ;
+dpmtm_setup_timer                = 0x0f04a12d ;
+dpm_reset                        = 0x0f047ed9 ;
+romac_store_machwkey             = 0x0f04ca79 ;
+romac_rem_machwkey               = 0x0f04ca4d ;
+dpmtxb_init                      = 0x0f04a5c9 ;