diff options
| author | Yilin Sun <[email protected]> | 2025-02-19 14:59:44 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2025-03-10 22:40:53 +0800 |
| commit | 73b90afbd9ae797ffd08972059a45f8ec24c67cb (patch) | |
| tree | bfea013d340a9fec625c475055979fb2fa987a79 | |
| parent | 988c695f4540f11e3a54403451139d4535ccdfa0 (diff) | |
bsp: nxp/mcx/mcxa/frdm-mcxa156: Enable PORT and GPIO clocks.
Enable PORT and GPIO peripheral clocks and release resets for all
ports.
Signed-off-by: Yilin Sun <[email protected]>
| -rw-r--r-- | bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c | 52 |
1 files changed, 48 insertions, 4 deletions
diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c index c9be992461..d4ed54f469 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c @@ -59,12 +59,31 @@ BOARD_InitPins: * END ****************************************************************************************************************/ void BOARD_InitPins(void) { - /* PORT0: Peripheral clock is enabled */ + /* Enable all PORT clocks */ CLOCK_EnableClock(kCLOCK_GatePORT0); - /* LPUART0 peripheral is released from reset */ - RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); - /* PORT0 peripheral is released from reset */ + CLOCK_EnableClock(kCLOCK_GatePORT1); + CLOCK_EnableClock(kCLOCK_GatePORT2); + CLOCK_EnableClock(kCLOCK_GatePORT3); + + /* Enable all GPIO clocks */ + CLOCK_EnableClock(kCLOCK_GateGPIO0); + CLOCK_EnableClock(kCLOCK_GateGPIO1); + CLOCK_EnableClock(kCLOCK_GateGPIO2); + CLOCK_EnableClock(kCLOCK_GateGPIO3); + + /* Release all PORT resets */ RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + + /* Release LPUART0 resets */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, @@ -115,6 +134,31 @@ void BOARD_InitPins(void) kPORT_UnlockRegister}; /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); + + const port_pin_config_t port3_12_pin63_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainEnable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_TXD */ + kPORT_MuxAsGpio, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT3_12 (pin 63) is configured as LED_RED */ + PORT_SetPinConfig(PORT3, 12U, &port3_12_pin63_config); } /*********************************************************************************************************************** * EOF |