Add Soft I2c and SPI,modify Pin Device

18 files changed, 882 insertions, 263 deletions

diff --git a/bsp/cypress/libraries/HAL_Drivers/SConscript b/bsp/cypress/libraries/HAL_Drivers/SConscript
index 1835c3a3bf..3d413974d4 100644
--- a/bsp/cypress/libraries/HAL_Drivers/SConscript
+++ b/bsp/cypress/libraries/HAL_Drivers/SConscript
@@ -26,9 +26,12 @@ if GetDepend(['RT_USING_I2C']):
     if GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C6'):
         src += ['drv_i2c.c']
 
-if GetDepend(['BSP_USING_PWM']):
+if GetDepend(['RT_USING_PWM']):
     src += ['drv_pwm.c']
 
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
 if GetDepend(['RT_USING_ADC']):
     src += ['drv_adc.c']
 
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_gpio.c b/bsp/cypress/libraries/HAL_Drivers/drv_gpio.c
index 04278fa475..ec5ab50d07 100644
--- a/bsp/cypress/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_gpio.c
@@ -66,12 +66,13 @@ rt_inline void pin_irq_handler(int irqno)
     }
 }
 
-void gpio_exint_handler(uint16_t GPIO_Pin)
+void gpio_exint_handler(uint16_t GPIO_Port)
 {
-    pin_irq_handler(GPIO_Pin);
+    pin_irq_handler(GPIO_Port);
 }
 
-static void irq0_callback(void *callback_arg, cyhal_gpio_event_t event)
+/* interrupt callback definition*/
+static void irq_callback(void *callback_arg, cyhal_gpio_event_t event)
 {
     /* To avoid compiler warnings */
     (void) callback_arg;
@@ -80,228 +81,13 @@ static void irq0_callback(void *callback_arg, cyhal_gpio_event_t event)
     /* enter interrupt */
     rt_interrupt_enter();
 
-    gpio_exint_handler(CYHAL_PORT_0);
+    gpio_exint_handler(*(rt_uint16_t *)callback_arg);
 
     /* leave interrupt */
     rt_interrupt_leave();
 }
 
-static void irq1_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_1);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq2_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_2);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq3_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_3);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq4_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_4);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq5_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_5);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq6_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_6);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq7_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_7);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq8_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_8);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq9_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_9);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq10_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_10);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq11_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_11);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq12_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_12);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq13_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_13);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void irq14_callback(void *callback_arg, cyhal_gpio_event_t event)
-{
-    /* To avoid compiler warnings */
-    (void) callback_arg;
-    (void) event;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    gpio_exint_handler(CYHAL_PORT_14);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/* interrupt0 callback definition*/
-cyhal_gpio_callback_data_t irq0_cb_data =
-{
-    .callback     = irq0_callback,
-    .callback_arg = (void *)NULL
-};
+cyhal_gpio_callback_data_t irq_cb_data;
 
 static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
@@ -319,19 +105,19 @@ static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     switch (mode)
     {
     case PIN_MODE_OUTPUT:
-        cyhal_gpio_configure(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG);
+        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true);
         break;
     case PIN_MODE_INPUT:
-        cyhal_gpio_configure(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_NONE);
+        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_NONE, false);
         break;
     case PIN_MODE_INPUT_PULLUP:
-        cyhal_gpio_configure(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_PULL_NONE);
+        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
         break;
     case PIN_MODE_INPUT_PULLDOWN:
-        cyhal_gpio_configure(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_PULL_NONE);
+        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLDOWN, false);
         break;
     case PIN_MODE_OUTPUT_OD:
-        cyhal_gpio_configure(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH);
+        cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
         break;
     }
 }
@@ -349,12 +135,11 @@ static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
         return;
     }
 
-    cyhal_gpio_write_internal(gpio_pin, value);
+    cyhal_gpio_write(gpio_pin, value);
 }
 
 static int ifx_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value = PIN_LOW;
     rt_uint16_t gpio_pin;
 
     if (PORT_GET(pin) < PIN_IFXPORT_MAX)
@@ -366,7 +151,7 @@ static int ifx_pin_read(rt_device_t dev, rt_base_t pin)
         return -RT_ERROR;
     }
 
-    return cyhal_gpio_read_internal(pin);
+    return cyhal_gpio_read(gpio_pin);
 }
 
 static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
@@ -375,7 +160,6 @@ static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     rt_uint16_t gpio_port;
     rt_uint16_t gpio_pin;
     rt_base_t level;
-    rt_uint8_t pin_irq_mode;
 
     if (PORT_GET(pin) < PIN_IFXPORT_MAX)
     {
@@ -415,7 +199,6 @@ static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     rt_uint16_t gpio_port;
     rt_uint16_t gpio_pin;
     rt_base_t level;
-    rt_uint8_t pin_irq_mode;
 
     if (PORT_GET(pin) < PIN_IFXPORT_MAX)
     {
@@ -475,7 +258,10 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
 
         irqmap = &pin_irq_map[gpio_port];
 
-        cyhal_gpio_register_callback(gpio_pin, &irq0_cb_data);
+        irq_cb_data.callback = irq_callback;
+        irq_cb_data.callback_arg = (rt_uint16_t *)&pin_irq_map[gpio_port].port;
+
+        cyhal_gpio_register_callback(gpio_pin, &irq_cb_data);
 
         Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(gpio_pin), CYHAL_GET_PIN(gpio_pin));
 
@@ -493,22 +279,8 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         default:
             break;
         }
-#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
-        Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(gpio_pin), CYHAL_GET_PIN(gpio_pin), (uint32_t)pin_irq_mode);
-        Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(gpio_pin), CYHAL_GET_PIN(gpio_pin), (uint32_t)RT_TRUE);
-#endif
-#if !defined(COMPONENT_CAT1C)
-        IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->pin));
-#endif
-        if (false == NVIC_GetEnableIRQ(irqn))
-        {
-            _cyhal_irq_register(irqn, GPIO_INTERRUPT_PRIORITY, _cyhal_gpio_irq_handler);
-            _cyhal_irq_enable(irqn);
-        }
-        else
-        {
-            _cyhal_irq_set_priority(irqn, GPIO_INTERRUPT_PRIORITY);
-        }
+
+        cyhal_gpio_enable_event(gpio_pin, pin_irq_mode, GPIO_INTERRUPT_PRIORITY, RT_TRUE);
 
         rt_hw_interrupt_enable(level);
     }
@@ -519,7 +291,7 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         Cy_GPIO_Port_Deinit(CYHAL_GET_PORTADDR(gpio_pin));
 
 #if !defined(COMPONENT_CAT1C)
-        IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->pin));
+        IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->port));
 #endif
         _cyhal_irq_disable(irqn);
 
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_gpio.h b/bsp/cypress/libraries/HAL_Drivers/drv_gpio.h
index dcaaa029fc..c8beff6d85 100644
--- a/bsp/cypress/libraries/HAL_Drivers/drv_gpio.h
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_gpio.h
@@ -25,7 +25,7 @@
 
 struct pin_irq_map
 {
-    rt_uint16_t pin;
+    rt_uint16_t port;
     IRQn_Type irqno;
 };
 
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_pwm.c b/bsp/cypress/libraries/HAL_Drivers/drv_pwm.c
index d0049fb2c5..64199d53d2 100644
--- a/bsp/cypress/libraries/HAL_Drivers/drv_pwm.c
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_pwm.c
@@ -181,7 +181,7 @@ __exit:
 
 static int rt_hw_pwm_init(void)
 {
-    int i = 0;
+    int i;
     int result = RT_EOK;
 
     pwm_get_pin_number();
@@ -190,6 +190,7 @@ static int rt_hw_pwm_init(void)
     for (i = 0; i < sizeof(ifx_pwm_obj) / sizeof(ifx_pwm_obj[0]); i++)
     {
         ifx_pwm_obj[i].pwm_obj = rt_malloc(sizeof(cyhal_pwm_t));
+        RT_ASSERT(ifx_pwm_obj[i].pwm_obj != RT_NULL);
 
         /* pwm init */
         if (ifx_hw_pwm_init(&ifx_pwm_obj[i]) != RT_EOK)
@@ -213,7 +214,6 @@ static int rt_hw_pwm_init(void)
     }
 
 __exit:
-    rt_free(ifx_pwm_obj[i].pwm_obj);
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pwm_init);
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.c b/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.c
new file mode 100644
index 0000000000..9bb066c3d5
--- /dev/null
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Rbb666       first version
+ */
+
+#include <board.h>
+#include "drv_soft_i2c.h"
+
+#ifdef RT_USING_I2C
+
+//#define DRV_DEBUG
+#define LOG_TAG              "drv.i2c"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_I2C1)
+    #error "Please define at least one BSP_USING_I2Cx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+static const struct ifx_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_I2C1
+    I2C1_BUS_CONFIG,
+#endif
+};
+
+static struct ifx_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param ifx i2c dirver class.
+ */
+static void ifx_i2c_gpio_init(struct ifx_i2c *i2c)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param ifx config class.
+ * @param The sda pin state.
+ */
+static void ifx_set_sda(void *data, rt_int32_t state)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param ifx config class.
+ * @param The scl pin state.
+ */
+static void ifx_set_scl(void *data, rt_int32_t state)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t ifx_get_sda(void *data)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t ifx_get_scl(void *data)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    return rt_pin_read(cfg->scl);
+}
+
+static const struct rt_i2c_bit_ops ifx_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = ifx_set_sda,
+    .set_scl  = ifx_set_scl,
+    .get_sda  = ifx_get_sda,
+    .get_scl  = ifx_get_scl,
+    .udelay   = rt_hw_us_delay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param ifx config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t ifx_i2c_bus_unlock(const struct ifx_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            rt_hw_us_delay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            rt_hw_us_delay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ifx_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = ifx_bit_ops_default;
+        i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        ifx_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        ifx_i2c_bus_unlock(&soft_i2c_config[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              soft_i2c_config[i].bus_name,
+              soft_i2c_config[i].scl,
+              soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.h b/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.h
new file mode 100644
index 0000000000..a54eec66d4
--- /dev/null
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_soft_i2c.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Rbb666       first version
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+/* ifx config class */
+struct ifx_soft_i2c_config
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *bus_name;
+};
+/* ifx i2c dirver class */
+struct ifx_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C1_SCL_PIN,                         \
+        .sda = BSP_I2C1_SDA_PIN,                         \
+        .bus_name = "i2c1",                              \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_spi.c b/bsp/cypress/libraries/HAL_Drivers/drv_spi.c
new file mode 100644
index 0000000000..9d7b06a9ff
--- /dev/null
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_spi.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-18     Rbb666       first version
+ */
+
+#include <drv_spi.h>
+
+#ifdef RT_USING_SPI
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.spi"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ifx_sw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+#ifdef BSP_USING_SPI3
+    static struct rt_spi_bus spi_bus3;
+#endif
+
+static struct ifx_spi spi_bus_obj[] =
+{
+#ifdef BSP_USING_SPI3
+    {
+        .bus_name = "spi3",
+        .spi_bus = &spi_bus3,
+        .sck_pin = GET_PIN(6, 2),
+        .miso_pin = GET_PIN(6, 1),
+        .mosi_pin = GET_PIN(6, 0),
+    },
+#endif
+};
+
+/* private rt-thread spi ops function */
+static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message);
+
+static struct rt_spi_ops ifx_spi_ops =
+{
+    .configure = spi_configure,
+    .xfer = spixfer,
+};
+
+static void ifx_spi_init(struct ifx_spi *ifx_spi)
+{
+    int result = RT_EOK;
+
+    result = cyhal_spi_init(ifx_spi->spi_obj, ifx_spi->mosi_pin, ifx_spi->miso_pin, ifx_spi->sck_pin,
+                            NC, NULL, ifx_spi->spi_obj->data_bits, ifx_spi->spi_obj->mode, false);
+
+    RT_ASSERT(result != RT_ERROR);
+
+    rt_kprintf("[%s] Freq:[%d]HZ\n", ifx_spi->bus_name, ifx_spi->freq);
+
+    result = cyhal_spi_set_frequency(ifx_spi->spi_obj, ifx_spi->freq);
+
+    RT_ASSERT(result != CYHAL_SPI_RSLT_CLOCK_ERROR);
+}
+
+static rt_err_t spi_configure(struct rt_spi_device *device,
+                              struct rt_spi_configuration *configuration)
+{
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    /* data_width */
+    if (configuration->data_width <= 8)
+    {
+        spi_device->spi_obj->data_bits = 8;
+    }
+    else if (configuration->data_width <= 16)
+    {
+        spi_device->spi_obj->data_bits = 16;
+    }
+    else
+    {
+        return RT_EIO;
+    }
+
+    uint32_t max_hz;
+    max_hz = configuration->max_hz;
+
+    spi_device->freq = max_hz;
+
+    /* MSB or LSB */
+    switch (configuration->mode & RT_SPI_MODE_3)
+    {
+    case RT_SPI_MODE_0:
+        spi_device->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
+        break;
+    case RT_SPI_MODE_1:
+        spi_device->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
+        break;
+    case RT_SPI_MODE_2:
+        spi_device->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
+        break;
+    case RT_SPI_MODE_3:
+        spi_device->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
+        break;
+    }
+
+    ifx_spi_init(spi_device);
+
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
+    struct rt_spi_configuration *config = &device->config;
+    struct ifx_sw_spi_cs *cs = device->parent.user_data;
+
+    /* take CS */
+    if (message->cs_take)
+    {
+        cyhal_gpio_write(cs->pin, PIN_LOW);
+        LOG_D("spi take cs\n");
+    }
+
+    int result = RT_EOK;
+
+    if (message->length > 0)
+    {
+        if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< receive message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, RT_NULL, 0x00, message->recv_buf, message->length, 0x00);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
+        {
+            /**< send message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, RT_NULL, 0x00, 0x00);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< send and receive message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0x00);
+        }
+    }
+
+    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+            cyhal_gpio_write(cs->pin, PIN_LOW);
+        else
+            cyhal_gpio_write(cs->pin, PIN_HIGH);
+    }
+
+    return message->length;
+}
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin)
+{
+    RT_ASSERT(bus_name != RT_NULL);
+    RT_ASSERT(device_name != RT_NULL);
+
+    rt_err_t result;
+    struct rt_spi_device *spi_device;
+
+    /* attach the device to spi bus */
+    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct ifx_sw_spi_cs *cs_pin = (struct ifx_sw_spi_cs *)rt_malloc(sizeof(struct ifx_sw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+
+    cs_pin->pin = cs_gpio_pin;
+
+    if (cs_pin->pin != 0x00)
+    {
+        /* initialize the cs pin & select the slave*/
+        cyhal_gpio_init(cs_pin->pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, 1);
+        cyhal_gpio_write(cs_pin->pin, PIN_HIGH);
+    }
+
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+    RT_ASSERT(spi_device != RT_NULL);
+
+    return result;
+}
+
+int rt_hw_spi_init(void)
+{
+    int result = RT_EOK;
+
+    for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++)
+    {
+        spi_bus_obj[i].spi_obj = rt_malloc(sizeof(cyhal_spi_t));
+
+        RT_ASSERT(spi_bus_obj[i].spi_obj != RT_NULL);
+
+        spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i];
+
+        result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &ifx_spi_ops);
+
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("%s bus init done", spi_bus_obj[i].bus_name);
+
+        LOG_D("MOSI PIN:[%d], MISO PIN[%d],CLK PIN[%d]\n",
+              spi_bus_obj[i].mosi_pin, spi_bus_obj[i].miso_pin,
+              spi_bus_obj[i].sck_pin);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+#endif /* RT_USING_SPI */
diff --git a/bsp/cypress/libraries/HAL_Drivers/drv_spi.h b/bsp/cypress/libraries/HAL_Drivers/drv_spi.h
new file mode 100644
index 0000000000..36ab233f55
--- /dev/null
+++ b/bsp/cypress/libraries/HAL_Drivers/drv_spi.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-18     Rbb666       first version
+ */
+
+#ifndef __DRV_SPI__
+#define __DRV_SPI__
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+#include "drv_gpio.h"
+
+#define SPI_FREQ_HZ			(10000000UL)
+
+/* gd32 spi dirver class */
+struct ifx_spi
+{
+    char *bus_name;
+    struct rt_spi_bus *spi_bus;
+	cyhal_spi_t *spi_obj;
+
+    uint16_t sck_pin;
+    uint16_t miso_pin;
+    uint16_t mosi_pin;
+	uint32_t freq;
+};
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
+
+#endif
diff --git a/bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript b/bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript
index f953d4afa0..52d2bdf043 100644
--- a/bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript
+++ b/bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript
@@ -83,6 +83,11 @@ if GetDepend(['RT_USING_PWM']):
     src += ['mtb-pdl-cat1/drivers/source/cy_tcpwm_pwm.c']
     src += ['mtb-pdl-cat1/drivers/source/cy_tcpwm_counter.c']
 
+if GetDepend(['RT_USING_SPI']):
+    src += ['mtb-hal-cat1/source/cyhal_spi.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_scb_spi.c']
+
+
 if GetDepend(['RT_USING_I2C']):
     src += ['mtb-hal-cat1/source/cyhal_i2c.c']
 
diff --git a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index a4c5afbdd1..365ae6e7b4 100644
--- a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+++ b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -26,16 +26,26 @@
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ********************************************************************************/
+#include <rtthread.h>
 
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
-    {
-        .type = CYHAL_RSC_CLOCK,
-        .block_num = CYBSP_CSD_CLK_DIV_HW,
-        .channel_num = CYBSP_CSD_CLK_DIV_NUM,
-    };
+const cyhal_resource_inst_t CLK_PWM_obj =
+{
+    .type = CYHAL_RSC_CLOCK,
+    .block_num = CLK_PWM_HW,
+    .channel_num = CLK_PWM_NUM,
+};
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+{
+    .type = CYHAL_RSC_CLOCK,
+    .block_num = CYBSP_CSD_CLK_DIV_HW,
+    .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+};
 #endif //defined (CY_USING_HAL)
 
 
diff --git a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index ffc5ecad3a..53b6c0d3c5 100644
--- a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
+++ b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -40,6 +40,10 @@
 extern "C" {
 #endif
 
+#define CLK_PWM_ENABLED 1U
+#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT
+#define CLK_PWM_NUM 0U
+
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
diff --git a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 2ffab3dc6a..1f24e6c1b2 100644
--- a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
+++ b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -51,7 +51,7 @@ void init_cycfg_peripherals(void)
     /* UART2 Device Clock*/
     Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 #endif
-#ifdef BSP_USING_UART3
+#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
     /* UART3 Device Clock*/
     Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 #endif
diff --git a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 4adca0b709..eddda04023 100644
--- a/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+++ b/bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -29,6 +29,74 @@
 
 #include "cycfg_pins.h"
 
+#define CYBSP_SDHC_IO1_PORT GPIO_PRT13
+#define CYBSP_SDHC_IO1_PORT_NUM 13U
+#define CYBSP_SDHC_IO1_PIN 1U
+
+#ifndef ioss_0_port_13_pin_1_HSIOM
+    #define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SDHC_IO1_HSIOM ioss_0_port_13_pin_1_HSIOM
+
+#define CYBSP_SDHC_IO2_PORT GPIO_PRT13
+#define CYBSP_SDHC_IO2_PORT_NUM 13U
+#define CYBSP_SDHC_IO2_PIN 2U
+
+#ifndef ioss_0_port_13_pin_2_HSIOM
+    #define ioss_0_port_13_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SDHC_IO2_HSIOM ioss_0_port_13_pin_2_HSIOM
+
+const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .hsiom = CYBSP_SDHC_IO1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SDHC_IO1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SDHC_IO1_PORT_NUM,
+        .channel_num = CYBSP_SDHC_IO1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .hsiom = CYBSP_SDHC_IO2_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SDHC_IO2_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SDHC_IO2_PORT_NUM,
+        .channel_num = CYBSP_SDHC_IO2_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
 const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 {
     .outVal = 1,
@@ -414,6 +482,31 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
     };
 #endif //defined (CY_USING_HAL)
 
+const cy_stc_gpio_pin_config_t SMART_IO_OUTPUT_PIN_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+    .hsiom = P9_1_TCPWM1_LINE_COMPL20,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t SMART_IO_OUTPUT_PIN_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = 9U,
+        .channel_num = 1U,
+    };
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_pins(void)
 {
diff --git a/bsp/cypress/psoc6-cy8cproto-4343w/board/Kconfig b/bsp/cypress/psoc6-cy8cproto-4343w/board/Kconfig
index 5a0918b2d1..9a646e0a3b 100644
--- a/bsp/cypress/psoc6-cy8cproto-4343w/board/Kconfig
+++ b/bsp/cypress/psoc6-cy8cproto-4343w/board/Kconfig
@@ -14,7 +14,6 @@ menu "Onboard Peripheral Drivers"
         select BSP_USING_UART
         select BSP_USING_UART5
         default y
- 
 endmenu
 
 menu "On-chip Peripheral Drivers"
@@ -94,6 +93,21 @@ menu "On-chip Peripheral Drivers"
             endif
         endif
 
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        select RT_USING_SPI
+        default n
+        if BSP_USING_SPI
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_USING_SPI3_SAMPLE
+                        bool "Enable SPI3 BUS Sample"
+                        default n                
+                endif
+        endif
+
     menuconfig BSP_USING_ADC
         bool "Enable ADC"
         default n
@@ -172,7 +186,43 @@ menu "On-chip Peripheral Drivers"
 endmenu
 
 menu "Board extended module Drivers"
+        menuconfig BSP_USING_RW007
+            bool "Enable RW007"
+            default n
+            select PKG_USING_RW007
+            select BSP_USING_SPI
+            select RW007_NOT_USE_EXAMPLE_DRIVERS
+            
+        if BSP_USING_RW007
+            config IFX_RW007_SPI_BUS_NAME
+                string "RW007 BUS NAME"
+                default "spi3"
 
+            config IFX_RW007_CS_PIN
+                int "(INT)CS pin index"
+                range 1 113
+                default 96
+
+            config IFX_RW007_BOOT0_PIN
+                int "(INT)BOOT0 pin index (same as spi clk pin)"
+                range 1 113
+                default 50
+
+            config IFX_RW007_BOOT1_PIN
+                int "(INT)BOOT1 pin index (same as spi cs pin)"
+                range 1 113
+                default 96
+
+            config IFX_RW007_INT_BUSY_PIN
+                int "(INT)INT/BUSY pin index"
+                range 1 113
+                default 47
+
+            config IFX_RW007_RST_PIN
+                int "(INT)RESET pin index"
+                range 1 113
+                default 53
+        endif
 endmenu
 
 endmenu
diff --git a/bsp/cypress/psoc6-cy8cproto-4343w/board/SConscript b/bsp/cypress/psoc6-cy8cproto-4343w/board/SConscript
index fd43599d32..0c06cfdd5e 100644
--- a/bsp/cypress/psoc6-cy8cproto-4343w/board/SConscript
+++ b/bsp/cypress/psoc6-cy8cproto-4343w/board/SConscript
@@ -13,7 +13,14 @@ src = Split('''
 board.c
 ''')
 
+if GetDepend(['BSP_USING_SPI3_SAMPLE']):
+    src += Glob('ports/spi_sample.c')
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('ports/drv_rw007.c')
+
 path = [cwd]
+path += [cwd + '/port']
 
 startup_path_prefix = SDK_LIB
 
@@ -27,4 +34,4 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']:
 CPPDEFINES = ['IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
 group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
 
-Return('group')
+Return('group')
\ No newline at end of file
diff --git a/bsp/cypress/psoc6-cy8cproto-4343w/board/linker_scripts/link.ld b/bsp/cypress/psoc6-cy8cproto-4343w/board/linker_scripts/link.ld
index 844ae9ff59..8425d46368 100644
--- a/bsp/cypress/psoc6-cy8cproto-4343w/board/linker_scripts/link.ld
+++ b/bsp/cypress/psoc6-cy8cproto-4343w/board/linker_scripts/link.ld
@@ -228,13 +228,54 @@ SECTIONS
         KEEP(*(VSymTab))
         __vsymtab_end = .;
     } > flash
-    rti_fn : 
+    /* section information for utest */
+    UtestTcTab :
+    {
+        . = ALIGN(4);
+         __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+    }
+    /* section information for at server */
+    RtAtCmdTab :
+    {
+        . = ALIGN(4);
+         __rtatcmdtab_start = .;
+        KEEP(*(UtestTcTab))
+        __rtatcmdtab_end = .;
+    }
+    /* section information for modules */
+    RTMSymTab :
+    {
+        . = ALIGN(4);
+         __rtmsymtab_start = .;
+        KEEP(*(UtestTcTab))
+        __rtmsymtab_end = .;
+    }
+    /* section information for initial. */  
+    rti_fn :
     {
         . = ALIGN(4);
         __rt_init_start = .;
         KEEP(*(SORT(.rti_fn*)))
         __rt_init_end = .;
     } > flash
+    rti_fn :
+    {
+        . = ALIGN(4);
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __rt_init_end = .;
+        PROVIDE(__ctors_end__ = .);
+    } > flash
+    init_array :
+    {
+        . = ALIGN(4);
+        __ctors_start__ = .;
+        KEEP(*(SORT(.init_array*)))
+        __ctors_end__ = .;
+    } > flash       
     /* setction information for finsh shell end */
 
     /* To clear multiple BSS sections,
@@ -251,7 +292,6 @@ SECTIONS
 
     __etext =  . ;
 
-
     .ramVectors (NOLOAD) : ALIGN(8)
     {
         __ram_vectors_start__ = .;
diff --git a/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/drv_rw007.c b/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/drv_rw007.c
new file mode 100644
index 0000000000..c4c5211c58
--- /dev/null
+++ b/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/drv_rw007.c
@@ -0,0 +1,67 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static struct rt_spi_device rw007_dev;
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = IFX_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */
diff --git a/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/spi_sample.c b/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/spi_sample.c
new file mode 100644
index 0000000000..69a6fbd63a
--- /dev/null
+++ b/bsp/cypress/psoc6-cy8cproto-4343w/board/ports/spi_sample.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-19     Rbbb666	   first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_SPI3_SAMPLE)
+#include <drv_spi.h>
+
+#define SPI_NAME     "spi30"
+static struct rt_spi_device *spi_dev = RT_NULL;
+
+/* attach spi5 device */
+static int rt_spi_device_init(void)
+{
+    struct rt_spi_configuration cfg;
+
+    rt_hw_spi_device_attach("spi3", "spi30", NULL);
+
+    cfg.data_width = 8;
+    cfg.mode   = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
+    cfg.max_hz = 1 *1000 *1000;
+
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
+
+    if (RT_NULL == spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
+        return RT_ERROR;
+    }
+
+    rt_spi_configure(spi_dev, &cfg);
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_spi_device_init);
+
+/* spi5 loopback mode test case */
+static int spi_sample(int argc, char **argv)
+{
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
+    static struct rt_spi_message msg1;
+
+    if (argc != 9)
+    {
+        rt_kprintf("Please Usage:\n");
+        rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        t_buf[i] = atoi(argv[i+1]);
+    }
+
+    msg1.send_buf   = &t_buf;
+    msg1.recv_buf   = &r_buf;
+    msg1.length     = sizeof(t_buf);
+    msg1.cs_take    = 1;
+    msg1.cs_release = 0;
+    msg1.next       = RT_NULL;
+
+    rt_spi_transfer_message(spi_dev, &msg1);
+
+    rt_kprintf("spi rbuf : ");
+    for (i = 0; i < sizeof(t_buf); i++)
+    {
+        rt_kprintf("%x ", r_buf[i]);
+    }
+
+    rt_kprintf("\nspi loopback mode test over!\n");
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(spi_sample, spi loopback test);
+
+#endif /* BSP_USING_SPI3 */