diff options
| author | Meco Man <[email protected]> | 2022-06-14 06:50:31 -0400 |
|---|---|---|
| committer | guo <[email protected]> | 2022-06-15 17:30:28 +0800 |
| commit | 808259135fe0c24e17c9f990bf28f9d13e1a04d1 (patch) | |
| tree | ceb9b9ecdd4c4d9adfe92f0021b292111d134805 | |
| parent | b010e434ed3839e5064f7fc8337591a18d6b67cd (diff) | |
[cputime] suuport perf_counter
| -rwxr-xr-x | components/drivers/Kconfig | 8 | ||||
| -rw-r--r-- | components/drivers/cputime/cputime_cortexm.c | 15 |
2 files changed, 16 insertions, 7 deletions
diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 18f074ed70..d432faee05 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -79,12 +79,10 @@ config RT_USING_CPUTIME if RT_USING_CPUTIME config RT_USING_CPUTIME_CORTEXM - bool "Use DWT for CPU time" + bool "Support Cortex-M CPU" default y - depends on ARCH_ARM_CORTEX_M3 || ARCH_ARM_CORTEX_M4 || ARCH_ARM_CORTEX_M7 - help - Some Cortex-M3/4/7 MCU has Data Watchpoint and Trace Register, use - the cycle counter in DWT for CPU time. + depends on ARCH_ARM_CORTEX_M0 || ARCH_ARM_CORTEX_M3 || ARCH_ARM_CORTEX_M4 || ARCH_ARM_CORTEX_M7 + select PKG_USING_PERF_COUNTER endif config RT_USING_I2C diff --git a/components/drivers/cputime/cputime_cortexm.c b/components/drivers/cputime/cputime_cortexm.c index 48ccfdb126..d877064893 100644 --- a/components/drivers/cputime/cputime_cortexm.c +++ b/components/drivers/cputime/cputime_cortexm.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2017-12-23 Bernard first version + * 2022-06-14 Meco Man suuport pref_counter */ #include <rthw.h> @@ -13,9 +14,11 @@ #include <rtthread.h> #include <board.h> +#ifdef PKG_USING_PERF_COUNTER +#include <perf_counter.h> +#endif /* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */ - static float cortexm_cputime_getres(void) { float ret = 1000 * 1000 * 1000; @@ -26,7 +29,11 @@ static float cortexm_cputime_getres(void) static uint64_t cortexm_cputime_gettime(void) { +#ifdef PKG_USING_PERF_COUNTER + return get_system_ticks(); +#else return DWT->CYCCNT; +#endif } const static struct rt_clock_cputime_ops _cortexm_ops = @@ -35,8 +42,12 @@ const static struct rt_clock_cputime_ops _cortexm_ops = cortexm_cputime_gettime }; + int cortexm_cputime_init(void) { +#ifdef PKG_USING_PERF_COUNTER + clock_cpu_setops(&_cortexm_ops); +#else /* check support bit */ if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0) { @@ -52,7 +63,7 @@ int cortexm_cputime_init(void) clock_cpu_setops(&_cortexm_ops); } - +#endif /* PKG_USING_PERF_COUNTER */ return 0; } INIT_BOARD_EXPORT(cortexm_cputime_init); |