[bsp][mcxc] initial commit for frdm-mcxc444

143 files changed, 94013 insertions, 265 deletions

diff --git a/bsp/nxp/mcx/mcxc/Libraries/.ignore_format.yml b/bsp/nxp/mcx/mcxc/Libraries/.ignore_format.yml
new file mode 100644
index 0000000000..44315486a7
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/.ignore_format.yml
@@ -0,0 +1,4 @@
+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- MCXC444
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 0000000000..6911417747
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1503 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.4.3
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000000..1e255d5907
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1928 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang_ltm.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V1.5.3
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_compiler.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 0000000000..adbf296f15
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_gcc.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 0000000000..67bda4ef3c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2211 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.4.1
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+
+  _start();
+}
+
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              __StackSeal
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi":::"memory")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe":::"memory")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+    __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+  } else {
+    result = __SXTB16(__ROR(op1, rotate)) ;
+  }
+  return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+  uint32_t result;
+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
+    __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
+  } else {
+    result = __SXTAB16(op1, __ROR(op2, rotate));
+  }
+  return result;
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 0000000000..65b824b009
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,1002 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.3.0
+ * @date     14. April 2021
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2021 IAR Systems
+// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#undef __WEAK                           /* undo the definition from DLib_Defaults.h */
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              STACKSEAL$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __arm_wsr("CONTROL", control);
+  __iar_builtin_ISB();
+}
+
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __arm_wsr("CONTROL_NS", control);
+  __iar_builtin_ISB();
+}
+
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+      __iar_builtin_ISB();
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_version.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 0000000000..8b4765f186
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/core_cm0plus.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/core_cm0plus.h
new file mode 100644
index 0000000000..879a384124
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/core_cm0plus.h
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */
+#endif
+  /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/mpu_armv7.h b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 0000000000..9909f83990
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.2
+ * @date     25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/CMSIS/LICENSE.txt b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/LICENSE.txt
new file mode 100644
index 0000000000..8dada3edaf
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
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diff --git a/bsp/nxp/mcx/mcxc/Libraries/Kconfig b/bsp/nxp/mcx/mcxc/Libraries/Kconfig
new file mode 100644
index 0000000000..054b8e7fc6
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/Kconfig
@@ -0,0 +1,3 @@
+config SOC_MCX
+    bool
+    select ARCH_ARM_CORTEX_M0
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444.h
new file mode 100644
index 0000000000..a8aa9a3d82
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444.h
@@ -0,0 +1,16556 @@
+/*
+** ###################################################################
+**     Processors:          MCXC444VLH
+**                          MCXC444VMP
+**
+**     Compilers:           Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240401
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MCXC444
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-11)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXC444.h
+ * @version 1.0
+ * @date 2024-03-11
+ * @brief CMSIS Peripheral Access Layer for MCXC444
+ *
+ * CMSIS Peripheral Access Layer for MCXC444
+ */
+
+#if !defined(MCXC444_H_)
+#define MCXC444_H_                               /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete */
+  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete */
+  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete */
+  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete */
+  Reserved20_IRQn              = 4,                /**< Reserved interrupt */
+  FTFA_IRQn                    = 5,                /**< Command complete and read collision */
+  PMC_IRQn                     = 6,                /**< Low-voltage detect, low-voltage warning */
+  LLWU_IRQn                    = 7,                /**< Low leakage wakeup */
+  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
+  I2C1_IRQn                    = 9,                /**< I2C1 interrupt */
+  SPI0_IRQn                    = 10,               /**< SPI0 single interrupt vector for all sources */
+  SPI1_IRQn                    = 11,               /**< SPI1 single interrupt vector for all sources */
+  LPUART0_IRQn                 = 12,               /**< LPUART0 status and error */
+  LPUART1_IRQn                 = 13,               /**< LPUART1 status and error */
+  UART2_FLEXIO_IRQn            = 14,               /**< UART2 or FLEXIO */
+  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
+  TPM0_IRQn                    = 17,               /**< TPM0 single interrupt vector for all sources */
+  TPM1_IRQn                    = 18,               /**< TPM1 single interrupt vector for all sources */
+  TPM2_IRQn                    = 19,               /**< TPM2 single interrupt vector for all sources */
+  RTC_IRQn                     = 20,               /**< RTC alarm */
+  RTC_Seconds_IRQn             = 21,               /**< RTC seconds */
+  PIT_IRQn                     = 22,               /**< PIT interrupt */
+  I2S0_IRQn                    = 23,               /**< I2S0 interrupt */
+  USB0_IRQn                    = 24,               /**< USB0 interrupt */
+  DAC0_IRQn                    = 25,               /**< DAC0 interrupt */
+  Reserved42_IRQn              = 26,               /**< Reserved interrupt */
+  Reserved43_IRQn              = 27,               /**< Reserved interrupt */
+  LPTMR0_IRQn                  = 28,               /**< LPTMR0 interrupt */
+  LCD_IRQn                     = 29,               /**< LCD interrupt */
+  PORTA_IRQn                   = 30,               /**< PORTA Pin detect */
+  PORTC_PORTD_IRQn             = 31                /**< Single interrupt vector for PORTC; PORTD Pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if VTOR is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+#include "system_MCXC444.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0LPUART0Rx        = 2|0x100U,    /**< LPUART0 Receive */
+    kDmaRequestMux0LPUART0Tx        = 3|0x100U,    /**< LPUART0 Transmit */
+    kDmaRequestMux0LPUART1Rx        = 4|0x100U,    /**< LPUART1 Receive */
+    kDmaRequestMux0LPUART1Tx        = 5|0x100U,    /**< LPUART1 Transmit */
+    kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 Receive */
+    kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 Transmit */
+    kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
+    kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
+    kDmaRequestMux0FlexIOChannel0   = 10|0x100U,   /**< FlexIO Channel 0 */
+    kDmaRequestMux0FlexIOChannel1   = 11|0x100U,   /**< FlexIO Channel 1 */
+    kDmaRequestMux0FlexIOChannel2   = 12|0x100U,   /**< FlexIO Channel 2 */
+    kDmaRequestMux0FlexIOChannel3   = 13|0x100U,   /**< FlexIO Channel 3 */
+    kDmaRequestMux0I2S0Rx           = 14|0x100U,   /**< I2S0 Receive */
+    kDmaRequestMux0I2S0Tx           = 15|0x100U,   /**< I2S0 Transmit */
+    kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 Receive */
+    kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 Transmit */
+    kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 Receive */
+    kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 Transmit */
+    kDmaRequestMux0Reserved20       = 20|0x100U,   /**< Reserved20 */
+    kDmaRequestMux0Reserved21       = 21|0x100U,   /**< Reserved21 */
+    kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0 */
+    kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1 */
+    kDmaRequestMux0TPM0Channel0     = 24|0x100U,   /**< TPM0 channel 0 */
+    kDmaRequestMux0TPM0Channel1     = 25|0x100U,   /**< TPM0 channel 1 */
+    kDmaRequestMux0TPM0Channel2     = 26|0x100U,   /**< TPM0 channel 2 */
+    kDmaRequestMux0TPM0Channel3     = 27|0x100U,   /**< TPM0 channel 3 */
+    kDmaRequestMux0TPM0Channel4     = 28|0x100U,   /**< TPM0 channel 4 */
+    kDmaRequestMux0TPM0Channel5     = 29|0x100U,   /**< TPM0 channel 5 */
+    kDmaRequestMux0Reserved30       = 30|0x100U,   /**< Reserved30 */
+    kDmaRequestMux0Reserved31       = 31|0x100U,   /**< Reserved31 */
+    kDmaRequestMux0TPM1Channel0     = 32|0x100U,   /**< TPM1 channel 0 */
+    kDmaRequestMux0TPM1Channel1     = 33|0x100U,   /**< TPM1 channel 1 */
+    kDmaRequestMux0TPM2Channel0     = 34|0x100U,   /**< TPM2 channel 0 */
+    kDmaRequestMux0TPM2Channel1     = 35|0x100U,   /**< TPM2 channel 1 */
+    kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
+    kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
+    kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
+    kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0 */
+    kDmaRequestMux0Reserved41       = 41|0x100U,   /**< Reserved41 */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0 */
+    kDmaRequestMux0Reserved43       = 43|0x100U,   /**< Reserved43 */
+    kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0 */
+    kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
+    kDmaRequestMux0Reserved47       = 47|0x100U,   /**< Reserved47 */
+    kDmaRequestMux0Reserved48       = 48|0x100U,   /**< Reserved48 */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< GPIO Port A */
+    kDmaRequestMux0Reserved50       = 50|0x100U,   /**< Reserved50 */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< GPIO Port C */
+    kDmaRequestMux0PortD            = 52|0x100U,   /**< GPIO Port D */
+    kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
+    kDmaRequestMux0TPM0Overflow     = 54|0x100U,   /**< TPM0 overflow */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< TPM1 overflow */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< TPM2 overflow */
+    kDmaRequestMux0Reserved57       = 57|0x100U,   /**< Reserved57 */
+    kDmaRequestMux0Reserved58       = 58|0x100U,   /**< Reserved58 */
+    kDmaRequestMux0Reserved59       = 59|0x100U,   /**< Reserved59 */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+/*! @{ */
+
+#define ADC_SC1_ADCH_MASK                        (0x1FU)
+#define ADC_SC1_ADCH_SHIFT                       (0U)
+/*! ADCH - Input channel select
+ *  0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
+ *  0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
+ *  0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
+ *  0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
+ *  0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
+ *  0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
+ *  0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
+ *  0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
+ *  0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
+ *  0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
+ *  0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
+ *  0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
+ *  0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
+ *  0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
+ *  0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
+ *  0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
+ *  0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
+ *  0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
+ *  0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
+ *  0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
+ *  0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
+ *  0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
+ *  0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
+ *  0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
+ *  0b11000..Reserved.
+ *  0b11001..Reserved.
+ *  0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
+ *  0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
+ *  0b11100..Reserved.
+ *  0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input.
+ *           Voltage reference selected is determined by SC2[REFSEL].
+ *  0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
+ *  0b11111..Module is disabled.
+ */
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+
+#define ADC_SC1_DIFF_MASK                        (0x20U)
+#define ADC_SC1_DIFF_SHIFT                       (5U)
+/*! DIFF - Differential Mode Enable
+ *  0b0..Single-ended conversions and input channels are selected.
+ *  0b1..Differential conversions and input channels are selected.
+ */
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+
+#define ADC_SC1_AIEN_MASK                        (0x40U)
+#define ADC_SC1_AIEN_SHIFT                       (6U)
+/*! AIEN - Interrupt Enable
+ *  0b0..Conversion complete interrupt is disabled.
+ *  0b1..Conversion complete interrupt is enabled.
+ */
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+
+#define ADC_SC1_COCO_MASK                        (0x80U)
+#define ADC_SC1_COCO_SHIFT                       (7U)
+/*! COCO - Conversion Complete Flag
+ *  0b0..Conversion is not completed.
+ *  0b1..Conversion is completed.
+ */
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+/*! @} */
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT                            (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+/*! @{ */
+
+#define ADC_CFG1_ADICLK_MASK                     (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT                    (0U)
+/*! ADICLK - Input Clock Select
+ *  0b00..Bus clock
+ *  0b01..Bus clock divided by 2(BUSCLK/DIV2)
+ *  0b10..Alternate clock (ALTCLK)
+ *  0b11..Asynchronous clock (ADACK)
+ */
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+
+#define ADC_CFG1_MODE_MASK                       (0xCU)
+#define ADC_CFG1_MODE_SHIFT                      (2U)
+/*! MODE - Conversion mode selection
+ *  0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
+ *  0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
+ *  0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
+ *  0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
+ */
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+
+#define ADC_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT                    (4U)
+/*! ADLSMP - Sample Time Configuration
+ *  0b0..Short sample time.
+ *  0b1..Long sample time.
+ */
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+
+#define ADC_CFG1_ADIV_MASK                       (0x60U)
+#define ADC_CFG1_ADIV_SHIFT                      (5U)
+/*! ADIV - Clock Divide Select
+ *  0b00..The divide ratio is 1 and the clock rate is input clock.
+ *  0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
+ *  0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
+ *  0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+
+#define ADC_CFG1_ADLPC_MASK                      (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT                     (7U)
+/*! ADLPC - Low-Power Configuration
+ *  0b0..Normal power configuration.
+ *  0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
+ */
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+/*! @} */
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+/*! @{ */
+
+#define ADC_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT                    (0U)
+/*! ADLSTS - Long Sample Time Select
+ *  0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
+ *  0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ *  0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ *  0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+
+#define ADC_CFG2_ADHSC_MASK                      (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT                     (2U)
+/*! ADHSC - High-Speed Configuration
+ *  0b0..Normal conversion sequence selected.
+ *  0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
+ */
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+
+#define ADC_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT                   (3U)
+/*! ADACKEN - Asynchronous Clock Output Enable
+ *  0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
+ *  0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
+ */
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+
+#define ADC_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT                    (4U)
+/*! MUXSEL - ADC Mux Select
+ *  0b0..ADxxa channels are selected.
+ *  0b1..ADxxb channels are selected.
+ */
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+/*! @} */
+
+/*! @name R - ADC Data Result Register */
+/*! @{ */
+
+#define ADC_R_D_MASK                             (0xFFFFU)
+#define ADC_R_D_SHIFT                            (0U)
+/*! D - Data result */
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+/*! @} */
+
+/* The count of ADC_R */
+#define ADC_R_COUNT                              (2U)
+
+/*! @name CV1 - Compare Value Registers */
+/*! @{ */
+
+#define ADC_CV1_CV_MASK                          (0xFFFFU)
+#define ADC_CV1_CV_SHIFT                         (0U)
+/*! CV - Compare Value. */
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+/*! @} */
+
+/*! @name CV2 - Compare Value Registers */
+/*! @{ */
+
+#define ADC_CV2_CV_MASK                          (0xFFFFU)
+#define ADC_CV2_CV_SHIFT                         (0U)
+/*! CV - Compare Value. */
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+/*! @} */
+
+/*! @name SC2 - Status and Control Register 2 */
+/*! @{ */
+
+#define ADC_SC2_REFSEL_MASK                      (0x3U)
+#define ADC_SC2_REFSEL_SHIFT                     (0U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
+ *  0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or
+ *        internal sources depending on the MCU configuration. See the chip configuration information for details
+ *        specific to this MCU
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+
+#define ADC_SC2_DMAEN_MASK                       (0x4U)
+#define ADC_SC2_DMAEN_SHIFT                      (2U)
+/*! DMAEN - DMA Enable
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any
+ *       of the SC1n[COCO] flags is asserted.
+ */
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+
+#define ADC_SC2_ACREN_MASK                       (0x8U)
+#define ADC_SC2_ACREN_SHIFT                      (3U)
+/*! ACREN - Compare Function Range Enable
+ *  0b0..Range function disabled. Only CV1 is compared.
+ *  0b1..Range function enabled. Both CV1 and CV2 are compared.
+ */
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+
+#define ADC_SC2_ACFGT_MASK                       (0x10U)
+#define ADC_SC2_ACFGT_SHIFT                      (4U)
+/*! ACFGT - Compare Function Greater Than Enable
+ *  0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality
+ *       based on the values placed in CV1 and CV2.
+ *  0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+
+#define ADC_SC2_ACFE_MASK                        (0x20U)
+#define ADC_SC2_ACFE_SHIFT                       (5U)
+/*! ACFE - Compare Function Enable
+ *  0b0..Compare function disabled.
+ *  0b1..Compare function enabled.
+ */
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+
+#define ADC_SC2_ADTRG_MASK                       (0x40U)
+#define ADC_SC2_ADTRG_SHIFT                      (6U)
+/*! ADTRG - Conversion Trigger Select
+ *  0b0..Software trigger selected.
+ *  0b1..Hardware trigger selected.
+ */
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+
+#define ADC_SC2_ADACT_MASK                       (0x80U)
+#define ADC_SC2_ADACT_SHIFT                      (7U)
+/*! ADACT - Conversion Active
+ *  0b0..Conversion not in progress.
+ *  0b1..Conversion in progress.
+ */
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+/*! @} */
+
+/*! @name SC3 - Status and Control Register 3 */
+/*! @{ */
+
+#define ADC_SC3_AVGS_MASK                        (0x3U)
+#define ADC_SC3_AVGS_SHIFT                       (0U)
+/*! AVGS - Hardware Average Select
+ *  0b00..4 samples averaged.
+ *  0b01..8 samples averaged.
+ *  0b10..16 samples averaged.
+ *  0b11..32 samples averaged.
+ */
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+
+#define ADC_SC3_AVGE_MASK                        (0x4U)
+#define ADC_SC3_AVGE_SHIFT                       (2U)
+/*! AVGE - Hardware Average Enable
+ *  0b0..Hardware average function disabled.
+ *  0b1..Hardware average function enabled.
+ */
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+
+#define ADC_SC3_ADCO_MASK                        (0x8U)
+#define ADC_SC3_ADCO_SHIFT                       (3U)
+/*! ADCO - Continuous Conversion Enable
+ *  0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
+ *  0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+
+#define ADC_SC3_CALF_MASK                        (0x40U)
+#define ADC_SC3_CALF_SHIFT                       (6U)
+/*! CALF - Calibration Failed Flag
+ *  0b0..Calibration completed normally.
+ *  0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+
+#define ADC_SC3_CAL_MASK                         (0x80U)
+#define ADC_SC3_CAL_SHIFT                        (7U)
+/*! CAL - Calibration */
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+/*! @} */
+
+/*! @name OFS - ADC Offset Correction Register */
+/*! @{ */
+
+#define ADC_OFS_OFS_MASK                         (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT                        (0U)
+/*! OFS - Offset Error Correction Value */
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+/*! @} */
+
+/*! @name PG - ADC Plus-Side Gain Register */
+/*! @{ */
+
+#define ADC_PG_PG_MASK                           (0xFFFFU)
+#define ADC_PG_PG_SHIFT                          (0U)
+/*! PG - Plus-Side Gain */
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+/*! @} */
+
+/*! @name MG - ADC Minus-Side Gain Register */
+/*! @{ */
+
+#define ADC_MG_MG_MASK                           (0xFFFFU)
+#define ADC_MG_MG_SHIFT                          (0U)
+/*! MG - Minus-Side Gain */
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+/*! @} */
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLPD_CLPD_MASK                       (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT                      (0U)
+/*! CLPD - Calibration Value */
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+/*! @} */
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLPS_CLPS_MASK                       (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT                      (0U)
+/*! CLPS - Calibration Value */
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+/*! @} */
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT                      (0U)
+/*! CLP4 - Calibration Value */
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+/*! @} */
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT                      (0U)
+/*! CLP3 - Calibration Value */
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+/*! @} */
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLP2_CLP2_MASK                       (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT                      (0U)
+/*! CLP2 - Calibration Value */
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+/*! @} */
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLP1_CLP1_MASK                       (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT                      (0U)
+/*! CLP1 - Calibration Value */
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+/*! @} */
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLP0_CLP0_MASK                       (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT                      (0U)
+/*! CLP0 - Calibration Value */
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+/*! @} */
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLMD_CLMD_MASK                       (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT                      (0U)
+/*! CLMD - Calibration Value */
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+/*! @} */
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLMS_CLMS_MASK                       (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT                      (0U)
+/*! CLMS - Calibration Value */
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+/*! @} */
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT                      (0U)
+/*! CLM4 - Calibration Value */
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+/*! @} */
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT                      (0U)
+/*! CLM3 - Calibration Value */
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+/*! @} */
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLM2_CLM2_MASK                       (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT                      (0U)
+/*! CLM2 - Calibration Value */
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+/*! @} */
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLM1_CLM1_MASK                       (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT                      (0U)
+/*! CLM1 - Calibration Value */
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+/*! @} */
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+
+#define ADC_CLM0_CLM0_MASK                       (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT                      (0U)
+/*! CLM0 - Calibration Value */
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+/*! @{ */
+
+#define CMP_CR0_HYSTCTR_MASK                     (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+/*! HYSTCTR - Comparator hard block hysteresis control
+ *  0b00..Level 0
+ *  0b01..Level 1
+ *  0b10..Level 2
+ *  0b11..Level 3
+ */
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+
+#define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+/*! FILTER_CNT - Filter Sample Count
+ *  0b000..Filter is disabled. SE = 0, COUT = COUTA.
+ *  0b001..One sample must agree. The comparator output is simply sampled.
+ *  0b010..2 consecutive samples must agree.
+ *  0b011..3 consecutive samples must agree.
+ *  0b100..4 consecutive samples must agree.
+ *  0b101..5 consecutive samples must agree.
+ *  0b110..6 consecutive samples must agree.
+ *  0b111..7 consecutive samples must agree.
+ */
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+/*! @} */
+
+/*! @name CR1 - CMP Control Register 1 */
+/*! @{ */
+
+#define CMP_CR1_EN_MASK                          (0x1U)
+#define CMP_CR1_EN_SHIFT                         (0U)
+/*! EN - Comparator Module Enable
+ *  0b0..Analog Comparator is disabled.
+ *  0b1..Analog Comparator is enabled.
+ */
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+
+#define CMP_CR1_OPE_MASK                         (0x2U)
+#define CMP_CR1_OPE_SHIFT                        (1U)
+/*! OPE - Comparator Output Pin Enable
+ *  0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
+ *  0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
+ *       associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
+ *       bit has no effect.
+ */
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+
+#define CMP_CR1_COS_MASK                         (0x4U)
+#define CMP_CR1_COS_SHIFT                        (2U)
+/*! COS - Comparator Output Select
+ *  0b0..Set the filtered comparator output (CMPO) to equal COUT.
+ *  0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+
+#define CMP_CR1_INV_MASK                         (0x8U)
+#define CMP_CR1_INV_SHIFT                        (3U)
+/*! INV - Comparator INVERT
+ *  0b0..Does not invert the comparator output.
+ *  0b1..Inverts the comparator output.
+ */
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+
+#define CMP_CR1_PMODE_MASK                       (0x10U)
+#define CMP_CR1_PMODE_SHIFT                      (4U)
+/*! PMODE - Power Mode Select
+ *  0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
+ *  0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
+ */
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+
+#define CMP_CR1_TRIGM_MASK                       (0x20U)
+#define CMP_CR1_TRIGM_SHIFT                      (5U)
+/*! TRIGM - Trigger Mode Enable
+ *  0b0..Trigger mode is disabled.
+ *  0b1..Trigger mode is enabled.
+ */
+#define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+
+#define CMP_CR1_WE_MASK                          (0x40U)
+#define CMP_CR1_WE_SHIFT                         (6U)
+/*! WE - Windowing Enable
+ *  0b0..Windowing mode is not selected.
+ *  0b1..Windowing mode is selected.
+ */
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+
+#define CMP_CR1_SE_MASK                          (0x80U)
+#define CMP_CR1_SE_SHIFT                         (7U)
+/*! SE - Sample Enable
+ *  0b0..Sampling mode is not selected.
+ *  0b1..Sampling mode is selected.
+ */
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+/*! @} */
+
+/*! @name FPR - CMP Filter Period Register */
+/*! @{ */
+
+#define CMP_FPR_FILT_PER_MASK                    (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT                   (0U)
+/*! FILT_PER - Filter Sample Period */
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+/*! @} */
+
+/*! @name SCR - CMP Status and Control Register */
+/*! @{ */
+
+#define CMP_SCR_COUT_MASK                        (0x1U)
+#define CMP_SCR_COUT_SHIFT                       (0U)
+/*! COUT - Analog Comparator Output */
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+
+#define CMP_SCR_CFF_MASK                         (0x2U)
+#define CMP_SCR_CFF_SHIFT                        (1U)
+/*! CFF - Analog Comparator Flag Falling
+ *  0b0..Falling-edge on COUT has not been detected.
+ *  0b1..Falling-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+
+#define CMP_SCR_CFR_MASK                         (0x4U)
+#define CMP_SCR_CFR_SHIFT                        (2U)
+/*! CFR - Analog Comparator Flag Rising
+ *  0b0..Rising-edge on COUT has not been detected.
+ *  0b1..Rising-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+
+#define CMP_SCR_IEF_MASK                         (0x8U)
+#define CMP_SCR_IEF_SHIFT                        (3U)
+/*! IEF - Comparator Interrupt Enable Falling
+ *  0b0..Interrupt is disabled.
+ *  0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+
+#define CMP_SCR_IER_MASK                         (0x10U)
+#define CMP_SCR_IER_SHIFT                        (4U)
+/*! IER - Comparator Interrupt Enable Rising
+ *  0b0..Interrupt is disabled.
+ *  0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+
+#define CMP_SCR_DMAEN_MASK                       (0x40U)
+#define CMP_SCR_DMAEN_SHIFT                      (6U)
+/*! DMAEN - DMA Enable Control
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled.
+ */
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+/*! @} */
+
+/*! @name DACCR - DAC Control Register */
+/*! @{ */
+
+#define CMP_DACCR_VOSEL_MASK                     (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT                    (0U)
+/*! VOSEL - DAC Output Voltage Select */
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+
+#define CMP_DACCR_VRSEL_MASK                     (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT                    (6U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ *  0b0..Vin1 is selected as resistor ladder network supply reference.
+ *  0b1..Vin2 is selected as resistor ladder network supply reference.
+ */
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+
+#define CMP_DACCR_DACEN_MASK                     (0x80U)
+#define CMP_DACCR_DACEN_SHIFT                    (7U)
+/*! DACEN - DAC Enable
+ *  0b0..DAC is disabled.
+ *  0b1..DAC is enabled.
+ */
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+/*! @} */
+
+/*! @name MUXCR - MUX Control Register */
+/*! @{ */
+
+#define CMP_MUXCR_MSEL_MASK                      (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT                     (0U)
+/*! MSEL - Minus Input Mux Control
+ *  0b000..IN0
+ *  0b001..IN1
+ *  0b010..IN2
+ *  0b011..IN3
+ *  0b100..IN4
+ *  0b101..IN5
+ *  0b110..IN6
+ *  0b111..IN7
+ */
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+
+#define CMP_MUXCR_PSEL_MASK                      (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT                     (3U)
+/*! PSEL - Plus Input Mux Control
+ *  0b000..IN0
+ *  0b001..IN1
+ *  0b010..IN2
+ *  0b011..IN3
+ *  0b100..IN4
+ *  0b101..IN5
+ *  0b110..IN6
+ *  0b111..IN7
+ */
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+
+#define CMP_MUXCR_PSTM_MASK                      (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT                     (7U)
+/*! PSTM - Pass Through Mode Enable
+ *  0b0..Pass Through Mode is disabled.
+ *  0b1..Pass Through Mode is enabled.
+ */
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[2];
+       uint8_t RESERVED_0[28];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+/*! @{ */
+
+#define DAC_DATL_DATA0_MASK                      (0xFFU)
+#define DAC_DATL_DATA0_SHIFT                     (0U)
+/*! DATA0 - DATA0 */
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+/*! @} */
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT                           (2U)
+
+/*! @name DATH - DAC Data High Register */
+/*! @{ */
+
+#define DAC_DATH_DATA1_MASK                      (0xFU)
+#define DAC_DATH_DATA1_SHIFT                     (0U)
+/*! DATA1 - DATA1 */
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+/*! @} */
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT                           (2U)
+
+/*! @name SR - DAC Status Register */
+/*! @{ */
+
+#define DAC_SR_DACBFRPBF_MASK                    (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT                   (0U)
+/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
+ *  0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
+ *  0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+
+#define DAC_SR_DACBFRPTF_MASK                    (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT                   (1U)
+/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
+ *  0b0..The DAC buffer read pointer is not zero.
+ *  0b1..The DAC buffer read pointer is zero.
+ */
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+/*! @} */
+
+/*! @name C0 - DAC Control Register */
+/*! @{ */
+
+#define DAC_C0_DACBBIEN_MASK                     (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT                    (0U)
+/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
+ *  0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
+ *  0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+
+#define DAC_C0_DACBTIEN_MASK                     (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT                    (1U)
+/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
+ *  0b0..The DAC buffer read pointer top flag interrupt is disabled.
+ *  0b1..The DAC buffer read pointer top flag interrupt is enabled.
+ */
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+
+#define DAC_C0_LPEN_MASK                         (0x8U)
+#define DAC_C0_LPEN_SHIFT                        (3U)
+/*! LPEN - DAC Low Power Control
+ *  0b0..High-Power mode
+ *  0b1..Low-Power mode
+ */
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+
+#define DAC_C0_DACSWTRG_MASK                     (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT                    (4U)
+/*! DACSWTRG - DAC Software Trigger
+ *  0b0..The DAC soft trigger is not valid.
+ *  0b1..The DAC soft trigger is valid.
+ */
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+
+#define DAC_C0_DACTRGSEL_MASK                    (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT                   (5U)
+/*! DACTRGSEL - DAC Trigger Select
+ *  0b0..The DAC hardware trigger is selected.
+ *  0b1..The DAC software trigger is selected.
+ */
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+
+#define DAC_C0_DACRFS_MASK                       (0x40U)
+#define DAC_C0_DACRFS_SHIFT                      (6U)
+/*! DACRFS - DAC Reference Select
+ *  0b0..The DAC selects DACREF_1 as the reference voltage.
+ *  0b1..The DAC selects DACREF_2 as the reference voltage.
+ */
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+
+#define DAC_C0_DACEN_MASK                        (0x80U)
+#define DAC_C0_DACEN_SHIFT                       (7U)
+/*! DACEN - DAC Enable
+ *  0b0..The DAC system is disabled.
+ *  0b1..The DAC system is enabled.
+ */
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+/*! @} */
+
+/*! @name C1 - DAC Control Register 1 */
+/*! @{ */
+
+#define DAC_C1_DACBFEN_MASK                      (0x1U)
+#define DAC_C1_DACBFEN_SHIFT                     (0U)
+/*! DACBFEN - DAC Buffer Enable
+ *  0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
+ *  0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means
+ *       converted data can be from any word of the buffer.
+ */
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+
+#define DAC_C1_DACBFMD_MASK                      (0x6U)
+#define DAC_C1_DACBFMD_SHIFT                     (1U)
+/*! DACBFMD - DAC Buffer Work Mode Select
+ *  0b00..Normal mode
+ *  0b01..Reserved
+ *  0b10..One-Time Scan mode
+ *  0b11..FIFO mode
+ */
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+
+#define DAC_C1_DMAEN_MASK                        (0x80U)
+#define DAC_C1_DMAEN_SHIFT                       (7U)
+/*! DMAEN - DMA Enable Select
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
+ *       interrupts will not be presented on this module at the same time.
+ */
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+/*! @} */
+
+/*! @name C2 - DAC Control Register 2 */
+/*! @{ */
+
+#define DAC_C2_DACBFUP_MASK                      (0x1U)
+#define DAC_C2_DACBFUP_SHIFT                     (0U)
+/*! DACBFUP - DAC Buffer Upper Limit */
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+
+#define DAC_C2_DACBFRP_MASK                      (0x10U)
+#define DAC_C2_DACBFRP_SHIFT                     (4U)
+/*! DACBFRP - DAC Buffer Read Pointer */
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[256];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+    __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+    union {                                          /* offset: 0x108, array step: 0x10 */
+      struct {                                         /* offset: 0x108, array step: 0x10 */
+             uint8_t RESERVED_0[3];
+             uint8_t DSR;                                /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+      } DMA_DSR_ACCESS8BIT;
+      __IO uint32_t DSR_BCR;                           /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+    };
+    __IO uint32_t DCR;                               /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+  } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name SAR - Source Address Register */
+/*! @{ */
+
+#define DMA_SAR_SAR_MASK                         (0xFFFFFFFFU)
+#define DMA_SAR_SAR_SHIFT                        (0U)
+/*! SAR - SAR */
+#define DMA_SAR_SAR(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
+/*! @} */
+
+/* The count of DMA_SAR */
+#define DMA_SAR_COUNT                            (4U)
+
+/*! @name DAR - Destination Address Register */
+/*! @{ */
+
+#define DMA_DAR_DAR_MASK                         (0xFFFFFFFFU)
+#define DMA_DAR_DAR_SHIFT                        (0U)
+/*! DAR - DAR */
+#define DMA_DAR_DAR(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
+/*! @} */
+
+/* The count of DMA_DAR */
+#define DMA_DAR_COUNT                            (4U)
+
+/* The count of DMA_DSR */
+#define DMA_DSR_COUNT                            (4U)
+
+/*! @name DSR_BCR - DMA Status Register / Byte Count Register */
+/*! @{ */
+
+#define DMA_DSR_BCR_BCR_MASK                     (0xFFFFFFU)
+#define DMA_DSR_BCR_BCR_SHIFT                    (0U)
+/*! BCR - BCR */
+#define DMA_DSR_BCR_BCR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
+
+#define DMA_DSR_BCR_DONE_MASK                    (0x1000000U)
+#define DMA_DSR_BCR_DONE_SHIFT                   (24U)
+/*! DONE - Transactions Done
+ *  0b0..DMA transfer is not yet complete. Writing a 0 has no effect.
+ *  0b1..DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an
+ *       interrupt service routine to clear the DMA interrupt and error bits.
+ */
+#define DMA_DSR_BCR_DONE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
+
+#define DMA_DSR_BCR_BSY_MASK                     (0x2000000U)
+#define DMA_DSR_BCR_BSY_SHIFT                    (25U)
+/*! BSY - Busy
+ *  0b0..DMA channel is inactive. Cleared when the DMA has finished the last transaction.
+ *  0b1..BSY is set the first time the channel is enabled after a transfer is initiated.
+ */
+#define DMA_DSR_BCR_BSY(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
+
+#define DMA_DSR_BCR_REQ_MASK                     (0x4000000U)
+#define DMA_DSR_BCR_REQ_SHIFT                    (26U)
+/*! REQ - Request
+ *  0b0..No request is pending or the channel is currently active. Cleared when the channel is selected.
+ *  0b1..The DMA channel has a transfer remaining and the channel is not selected.
+ */
+#define DMA_DSR_BCR_REQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
+
+#define DMA_DSR_BCR_BED_MASK                     (0x10000000U)
+#define DMA_DSR_BCR_BED_SHIFT                    (28U)
+/*! BED - Bus Error on Destination
+ *  0b0..No bus error occurred.
+ *  0b1..The DMA channel terminated with a bus error during the write portion of a transfer.
+ */
+#define DMA_DSR_BCR_BED(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
+
+#define DMA_DSR_BCR_BES_MASK                     (0x20000000U)
+#define DMA_DSR_BCR_BES_SHIFT                    (29U)
+/*! BES - Bus Error on Source
+ *  0b0..No bus error occurred.
+ *  0b1..The DMA channel terminated with a bus error during the read portion of a transfer.
+ */
+#define DMA_DSR_BCR_BES(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
+
+#define DMA_DSR_BCR_CE_MASK                      (0x40000000U)
+#define DMA_DSR_BCR_CE_SHIFT                     (30U)
+/*! CE - Configuration Error
+ *  0b0..No configuration error exists.
+ *  0b1..A configuration error has occurred.
+ */
+#define DMA_DSR_BCR_CE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
+/*! @} */
+
+/* The count of DMA_DSR_BCR */
+#define DMA_DSR_BCR_COUNT                        (4U)
+
+/*! @name DCR - DMA Control Register */
+/*! @{ */
+
+#define DMA_DCR_LCH2_MASK                        (0x3U)
+#define DMA_DCR_LCH2_SHIFT                       (0U)
+/*! LCH2 - Link Channel 2
+ *  0b00..DMA Channel 0
+ *  0b01..DMA Channel 1
+ *  0b10..DMA Channel 2
+ *  0b11..DMA Channel 3
+ */
+#define DMA_DCR_LCH2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
+
+#define DMA_DCR_LCH1_MASK                        (0xCU)
+#define DMA_DCR_LCH1_SHIFT                       (2U)
+/*! LCH1 - Link Channel 1
+ *  0b00..DMA Channel 0
+ *  0b01..DMA Channel 1
+ *  0b10..DMA Channel 2
+ *  0b11..DMA Channel 3
+ */
+#define DMA_DCR_LCH1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
+
+#define DMA_DCR_LINKCC_MASK                      (0x30U)
+#define DMA_DCR_LINKCC_SHIFT                     (4U)
+/*! LINKCC - Link Channel Control
+ *  0b00..No channel-to-channel linking
+ *  0b01..Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
+ *  0b10..Perform a link to channel LCH1 after each cycle-steal transfer
+ *  0b11..Perform a link to channel LCH1 after the BCR decrements to 0.
+ */
+#define DMA_DCR_LINKCC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
+
+#define DMA_DCR_D_REQ_MASK                       (0x80U)
+#define DMA_DCR_D_REQ_SHIFT                      (7U)
+/*! D_REQ - Disable Request
+ *  0b0..ERQ bit is not affected.
+ *  0b1..ERQ bit is cleared when the BCR is exhausted.
+ */
+#define DMA_DCR_D_REQ(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
+
+#define DMA_DCR_DMOD_MASK                        (0xF00U)
+#define DMA_DCR_DMOD_SHIFT                       (8U)
+/*! DMOD - Destination Address Modulo
+ *  0b0000..Buffer disabled
+ *  0b0001..Circular buffer size is 16 bytes
+ *  0b0010..Circular buffer size is 32 bytes
+ *  0b0011..Circular buffer size is 64 bytes
+ *  0b0100..Circular buffer size is 128 bytes
+ *  0b0101..Circular buffer size is 256 bytes
+ *  0b0110..Circular buffer size is 512 bytes
+ *  0b0111..Circular buffer size is 1 KB
+ *  0b1000..Circular buffer size is 2 KB
+ *  0b1001..Circular buffer size is 4 KB
+ *  0b1010..Circular buffer size is 8 KB
+ *  0b1011..Circular buffer size is 16 KB
+ *  0b1100..Circular buffer size is 32 KB
+ *  0b1101..Circular buffer size is 64 KB
+ *  0b1110..Circular buffer size is 128 KB
+ *  0b1111..Circular buffer size is 256 KB
+ */
+#define DMA_DCR_DMOD(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
+
+#define DMA_DCR_SMOD_MASK                        (0xF000U)
+#define DMA_DCR_SMOD_SHIFT                       (12U)
+/*! SMOD - Source Address Modulo
+ *  0b0000..Buffer disabled
+ *  0b0001..Circular buffer size is 16 bytes.
+ *  0b0010..Circular buffer size is 32 bytes.
+ *  0b0011..Circular buffer size is 64 bytes.
+ *  0b0100..Circular buffer size is 128 bytes.
+ *  0b0101..Circular buffer size is 256 bytes.
+ *  0b0110..Circular buffer size is 512 bytes.
+ *  0b0111..Circular buffer size is 1 KB.
+ *  0b1000..Circular buffer size is 2 KB.
+ *  0b1001..Circular buffer size is 4 KB.
+ *  0b1010..Circular buffer size is 8 KB.
+ *  0b1011..Circular buffer size is 16 KB.
+ *  0b1100..Circular buffer size is 32 KB.
+ *  0b1101..Circular buffer size is 64 KB.
+ *  0b1110..Circular buffer size is 128 KB.
+ *  0b1111..Circular buffer size is 256 KB.
+ */
+#define DMA_DCR_SMOD(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
+
+#define DMA_DCR_START_MASK                       (0x10000U)
+#define DMA_DCR_START_SHIFT                      (16U)
+/*! START - Start Transfer
+ *  0b0..DMA inactive
+ *  0b1..The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after
+ *       one module clock and always reads as logic 0.
+ */
+#define DMA_DCR_START(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
+
+#define DMA_DCR_DSIZE_MASK                       (0x60000U)
+#define DMA_DCR_DSIZE_SHIFT                      (17U)
+/*! DSIZE - Destination Size
+ *  0b00..32-bit
+ *  0b01..8-bit
+ *  0b10..16-bit
+ *  0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
+ */
+#define DMA_DCR_DSIZE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
+
+#define DMA_DCR_DINC_MASK                        (0x80000U)
+#define DMA_DCR_DINC_SHIFT                       (19U)
+/*! DINC - Destination Increment
+ *  0b0..No change to the DAR after a successful transfer.
+ *  0b1..The DAR increments by 1, 2, 4 depending upon the size of the transfer.
+ */
+#define DMA_DCR_DINC(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
+
+#define DMA_DCR_SSIZE_MASK                       (0x300000U)
+#define DMA_DCR_SSIZE_SHIFT                      (20U)
+/*! SSIZE - Source Size
+ *  0b00..32-bit
+ *  0b01..8-bit
+ *  0b10..16-bit
+ *  0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
+ */
+#define DMA_DCR_SSIZE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
+
+#define DMA_DCR_SINC_MASK                        (0x400000U)
+#define DMA_DCR_SINC_SHIFT                       (22U)
+/*! SINC - Source Increment
+ *  0b0..No change to SAR after a successful transfer.
+ *  0b1..The SAR increments by 1, 2, 4 as determined by the transfer size.
+ */
+#define DMA_DCR_SINC(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
+
+#define DMA_DCR_EADREQ_MASK                      (0x800000U)
+#define DMA_DCR_EADREQ_SHIFT                     (23U)
+/*! EADREQ - Enable asynchronous DMA requests
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define DMA_DCR_EADREQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
+
+#define DMA_DCR_AA_MASK                          (0x10000000U)
+#define DMA_DCR_AA_SHIFT                         (28U)
+/*! AA - Auto-align
+ *  0b0..Auto-align disabled
+ *  0b1..If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise,
+ *       destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If
+ *       auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
+ */
+#define DMA_DCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
+
+#define DMA_DCR_CS_MASK                          (0x20000000U)
+#define DMA_DCR_CS_SHIFT                         (29U)
+/*! CS - Cycle Steal
+ *  0b0..DMA continuously makes read/write transfers until the BCR decrements to 0.
+ *  0b1..Forces a single read/write transfer per request.
+ */
+#define DMA_DCR_CS(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
+
+#define DMA_DCR_ERQ_MASK                         (0x40000000U)
+#define DMA_DCR_ERQ_SHIFT                        (30U)
+/*! ERQ - Enable Peripheral Request
+ *  0b0..Peripheral request is ignored.
+ *  0b1..Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
+ */
+#define DMA_DCR_ERQ(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
+
+#define DMA_DCR_EINT_MASK                        (0x80000000U)
+#define DMA_DCR_EINT_SHIFT                       (31U)
+/*! EINT - Enable Interrupt on Completion of Transfer
+ *  0b0..No interrupt is generated.
+ *  0b1..Interrupt signal is enabled.
+ */
+#define DMA_DCR_EINT(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
+/*! @} */
+
+/* The count of DMA_DCR */
+#define DMA_DCR_COUNT                            (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+/*! @{ */
+
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+/*! SOURCE - DMA Channel Source (Slot)
+ *  0b000000..Disable_Signal
+ *  0b000010..LPUART0_Rx_Signal
+ *  0b000011..LPUART0_Tx_Signal
+ *  0b000100..LPUART1_Rx_Signal
+ *  0b000101..LPUART1_Tx_Signal
+ *  0b000110..UART2_Rx_Signal
+ *  0b000111..UART2_Tx_Signal
+ *  0b001010..FlexIO_Channel0_Signal
+ *  0b001011..FlexIO_Channel1_Signal
+ *  0b001100..FlexIO_Channel2_Signal
+ *  0b001101..FlexIO_Channel3_Signal
+ *  0b001110..I2S0_Rx_Signal
+ *  0b001111..I2S0_Tx_Signal
+ *  0b010000..SPI0_Rx_Signal
+ *  0b010001..SPI0_Tx_Signal
+ *  0b010010..SPI1_Rx_Signal
+ *  0b010011..SPI1_Tx_Signal
+ *  0b010110..I2C0_Signal
+ *  0b010111..I2C1_Signal
+ *  0b011000..TPM0_Channel0_Signal
+ *  0b011001..TPM0_Channel1_Signal
+ *  0b011010..TPM0_Channel2_Signal
+ *  0b011011..TPM0_Channel3_Signal
+ *  0b011100..TPM0_Channel4_Signal
+ *  0b011101..TPM0_Channel5_Signal
+ *  0b100000..TPM1_Channel0_Signal
+ *  0b100001..TPM1_Channel1_Signal
+ *  0b100010..TPM2_Channel0_Signal
+ *  0b100011..TPM2_Channel1_Signal
+ *  0b101000..ADC0_Signal
+ *  0b101010..CMP0_Signal
+ *  0b101101..DAC0_Signal
+ *  0b110001..Port_A_Signal
+ *  0b110011..Port_C_Signal
+ *  0b110100..Port_D_Signal
+ *  0b110110..TPM0_Overflow_Signal
+ *  0b110111..TPM1_Overflow_Signal
+ *  0b111000..TPM2_Overflow_Signal
+ *  0b111100..AlwaysOn60_Signal
+ *  0b111101..AlwaysOn61_Signal
+ *  0b111110..AlwaysOn62_Signal
+ *  0b111111..AlwaysOn63_Signal
+ */
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
+/*! TRIG - DMA Channel Trigger Enable
+ *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
+ *       specified source to the DMA channel. (Normal mode)
+ *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
+ */
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
+/*! ENBL - DMA Channel Enable
+ *  0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has
+ *       separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
+ *  0b1..DMA channel is enabled
+ */
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+/*! @} */
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE                             (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+
+#define FGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDOR_PDO_SHIFT                     (0U)
+/*! PDO - Port Data Output
+ *  0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
+ *  0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
+ */
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+
+#define FGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PSOR_PTSO_SHIFT                    (0U)
+/*! PTSO - Port Set Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
+ */
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+
+#define FGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PCOR_PTCO_SHIFT                    (0U)
+/*! PTCO - Port Clear Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
+ */
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+
+#define FGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PTOR_PTTO_SHIFT                    (0U)
+/*! PTTO - Port Toggle Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
+ */
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+
+#define FGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDIR_PDI_SHIFT                     (0U)
+/*! PDI - Port Data Input
+ *  0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
+ *  0b00000000000000000000000000000001..Pin logic level is logic 1.
+ */
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+
+#define FGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDDR_PDD_SHIFT                     (0U)
+/*! PDD - Port Data Direction
+ *  0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
+ *  0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
+ */
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE                              (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA                                   ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE                              (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB                                   ((FGPIO_Type *)FGPIOB_BASE)
+/** Peripheral FGPIOC base address */
+#define FGPIOC_BASE                              (0xF8000080u)
+/** Peripheral FGPIOC base pointer */
+#define FGPIOC                                   ((FGPIO_Type *)FGPIOC_BASE)
+/** Peripheral FGPIOD base address */
+#define FGPIOD_BASE                              (0xF80000C0u)
+/** Peripheral FGPIOD base pointer */
+#define FGPIOD                                   ((FGPIO_Type *)FGPIOD_BASE)
+/** Peripheral FGPIOE base address */
+#define FGPIOE_BASE                              (0xF8000100u)
+/** Peripheral FGPIOE base pointer */
+#define FGPIOE                                   ((FGPIO_Type *)FGPIOE_BASE)
+/** Array initializer of FGPIO peripheral base addresses */
+#define FGPIO_BASE_ADDRS                         { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASE_PTRS                          { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
+  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
+  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
+  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
+  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
+       uint8_t RESERVED_3[76];
+  __IO uint32_t SHIFTCTL[4];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_4[112];
+  __IO uint32_t SHIFTCFG[4];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_5[240];
+  __IO uint32_t SHIFTBUF[4];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[112];
+  __IO uint32_t SHIFTBUFBIS[4];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_7[112];
+  __IO uint32_t SHIFTBUFBYS[4];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_8[112];
+  __IO uint32_t SHIFTBUFBBS[4];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_9[112];
+  __IO uint32_t TIMCTL[4];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_10[112];
+  __IO uint32_t TIMCFG[4];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+       uint8_t RESERVED_11[112];
+  __IO uint32_t TIMCMP[4];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+} FLEXIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+
+#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
+#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ *  0b0000000000000001..Supports state, logic and parallel modes.
+ */
+#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
+
+#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
+#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
+/*! MINOR - Minor Version Number */
+#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
+
+#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
+#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
+/*! MAJOR - Major Version Number */
+#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+
+#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
+#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
+/*! SHIFTER - Shifter Number */
+#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
+
+#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
+#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
+/*! TIMER - Timer Number */
+#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
+
+#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
+#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
+/*! PIN - Pin Number */
+#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
+
+#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
+#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
+/*! TRIGGER - Trigger Number */
+#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
+/*! @} */
+
+/*! @name CTRL - FlexIO Control Register */
+/*! @{ */
+
+#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
+#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
+/*! FLEXEN - FlexIO Enable
+ *  0b0..FlexIO module is disabled.
+ *  0b1..FlexIO module is enabled.
+ */
+#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
+
+#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
+#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
+/*! SWRST - Software Reset
+ *  0b0..Software reset is disabled
+ *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
+ */
+#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
+
+#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
+#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
+/*! FASTACC - Fast Access
+ *  0b0..Configures for normal register accesses to FlexIO
+ *  0b1..Configures for fast register accesses to FlexIO
+ */
+#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
+
+#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
+#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
+/*! DBGE - Debug Enable
+ *  0b0..FlexIO is disabled in debug modes.
+ *  0b1..FlexIO is enabled in debug modes
+ */
+#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
+
+#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
+#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
+/*! DOZEN - Doze Enable
+ *  0b0..FlexIO enabled in Doze modes.
+ *  0b1..FlexIO disabled in Doze modes.
+ */
+#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
+/*! @} */
+
+/*! @name SHIFTSTAT - Shifter Status Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFU)
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
+/*! SSF - Shifter Status Flag
+ *  0b0000..Status flag is clear
+ *  0b0001..Status flag is set
+ */
+#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
+/*! @} */
+
+/*! @name SHIFTERR - Shifter Error Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFU)
+#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
+/*! SEF - Shifter Error Flags
+ *  0b0000..Shifter Error Flag is clear
+ *  0b0001..Shifter Error Flag is set
+ */
+#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
+/*! @} */
+
+/*! @name TIMSTAT - Timer Status Register */
+/*! @{ */
+
+#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFU)
+#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
+/*! TSF - Timer Status Flags
+ *  0b0000..Timer Status Flag is clear
+ *  0b0001..Timer Status Flag is set
+ */
+#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
+/*! @} */
+
+/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
+/*! @{ */
+
+#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFU)
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
+/*! SSIE - Shifter Status Interrupt Enable
+ *  0b0000..Shifter Status Flag interrupt disabled
+ *  0b0001..Shifter Status Flag interrupt enabled
+ */
+#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
+/*! @} */
+
+/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
+/*! @{ */
+
+#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFU)
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
+/*! SEIE - Shifter Error Interrupt Enable
+ *  0b0000..Shifter Error Flag interrupt disabled
+ *  0b0001..Shifter Error Flag interrupt enabled
+ */
+#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
+/*! @} */
+
+/*! @name TIMIEN - Timer Interrupt Enable Register */
+/*! @{ */
+
+#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFU)
+#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
+/*! TEIE - Timer Status Interrupt Enable
+ *  0b0000..Timer Status Flag interrupt is disabled
+ *  0b0001..Timer Status Flag interrupt is enabled
+ */
+#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
+/*! @} */
+
+/*! @name SHIFTSDEN - Shifter Status DMA Enable */
+/*! @{ */
+
+#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFU)
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
+/*! SSDE - Shifter Status DMA Enable
+ *  0b0000..Shifter Status Flag DMA request is disabled
+ *  0b0001..Shifter Status Flag DMA request is enabled
+ */
+#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
+/*! @} */
+
+/*! @name SHIFTCTL - Shifter Control N Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
+/*! SMOD - Shifter Mode
+ *  0b000..Disabled.
+ *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
+ *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
+ *  0b011..Reserved.
+ *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
+ *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
+ *  0b110..Reserved.
+ *  0b111..Reserved.
+ */
+#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
+
+#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
+/*! PINPOL - Shifter Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
+
+#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x700U)
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
+/*! PINSEL - Shifter Pin Select */
+#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
+
+#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
+/*! PINCFG - Shifter Pin Configuration
+ *  0b00..Shifter pin output disabled
+ *  0b01..Shifter pin open drain or bidirectional output enable
+ *  0b10..Shifter pin bidirectional output data
+ *  0b11..Shifter pin output
+ */
+#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
+
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
+/*! TIMPOL - Timer Polarity
+ *  0b0..Shift on posedge of Shift clock
+ *  0b1..Shift on negedge of Shift clock
+ */
+#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
+
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x3000000U)
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
+/*! TIMSEL - Timer Select */
+#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCTL */
+#define FLEXIO_SHIFTCTL_COUNT                    (4U)
+
+/*! @name SHIFTCFG - Shifter Configuration N Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
+/*! SSTART - Shifter Start bit
+ *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
+ *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
+ *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
+ *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
+
+#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
+/*! SSTOP - Shifter Stop bit
+ *  0b00..Stop bit disabled for transmitter/receiver/match store
+ *  0b01..Reserved for transmitter/receiver/match store
+ *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
+ *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
+
+#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
+/*! INSRC - Input Source
+ *  0b0..Pin
+ *  0b1..Shifter N+1 Output
+ */
+#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCFG */
+#define FLEXIO_SHIFTCFG_COUNT                    (4U)
+
+/*! @name SHIFTBUF - Shifter Buffer N Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
+/*! SHIFTBUF - Shift Buffer */
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUF */
+#define FLEXIO_SHIFTBUF_COUNT                    (4U)
+
+/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
+/*! SHIFTBUFBIS - Shift Buffer */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBIS */
+#define FLEXIO_SHIFTBUFBIS_COUNT                 (4U)
+
+/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
+/*! SHIFTBUFBYS - Shift Buffer */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBYS */
+#define FLEXIO_SHIFTBUFBYS_COUNT                 (4U)
+
+/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
+/*! @{ */
+
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
+/*! SHIFTBUFBBS - Shift Buffer */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBBS */
+#define FLEXIO_SHIFTBUFBBS_COUNT                 (4U)
+
+/*! @name TIMCTL - Timer Control N Register */
+/*! @{ */
+
+#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
+#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
+/*! TIMOD - Timer Mode
+ *  0b00..Timer Disabled.
+ *  0b01..Dual 8-bit counters baud/bit mode.
+ *  0b10..Dual 8-bit counters PWM mode.
+ *  0b11..Single 16-bit counter mode.
+ */
+#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
+
+#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
+#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
+/*! PINPOL - Timer Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
+
+#define FLEXIO_TIMCTL_PINSEL_MASK                (0x700U)
+#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
+/*! PINSEL - Timer Pin Select */
+#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
+
+#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
+#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
+/*! PINCFG - Timer Pin Configuration
+ *  0b00..Timer pin output disabled
+ *  0b01..Timer pin open drain or bidirectional output enable
+ *  0b10..Timer pin bidirectional output data
+ *  0b11..Timer pin output
+ */
+#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
+
+#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
+/*! TRGSRC - Trigger Source
+ *  0b0..External trigger selected
+ *  0b1..Internal trigger selected
+ */
+#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
+
+#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger active high
+ *  0b1..Trigger active low
+ */
+#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
+
+#define FLEXIO_TIMCTL_TRGSEL_MASK                (0xF000000U)
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
+/*! TRGSEL - Trigger Select */
+#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCTL */
+#define FLEXIO_TIMCTL_COUNT                      (4U)
+
+/*! @name TIMCFG - Timer Configuration N Register */
+/*! @{ */
+
+#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
+#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
+/*! TSTART - Timer Start Bit
+ *  0b0..Start bit disabled
+ *  0b1..Start bit enabled
+ */
+#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
+
+#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
+#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
+/*! TSTOP - Timer Stop Bit
+ *  0b00..Stop bit disabled
+ *  0b01..Stop bit is enabled on timer compare
+ *  0b10..Stop bit is enabled on timer disable
+ *  0b11..Stop bit is enabled on timer compare and timer disable
+ */
+#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
+
+#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
+#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
+/*! TIMENA - Timer Enable
+ *  0b000..Timer always enabled
+ *  0b001..Timer enabled on Timer N-1 enable
+ *  0b010..Timer enabled on Trigger high
+ *  0b011..Timer enabled on Trigger high and Pin high
+ *  0b100..Timer enabled on Pin rising edge
+ *  0b101..Timer enabled on Pin rising edge and Trigger high
+ *  0b110..Timer enabled on Trigger rising edge
+ *  0b111..Timer enabled on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
+
+#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
+/*! TIMDIS - Timer Disable
+ *  0b000..Timer never disabled
+ *  0b001..Timer disabled on Timer N-1 disable
+ *  0b010..Timer disabled on Timer compare
+ *  0b011..Timer disabled on Timer compare and Trigger Low
+ *  0b100..Timer disabled on Pin rising or falling edge
+ *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
+ *  0b110..Timer disabled on Trigger falling edge
+ *  0b111..Reserved
+ */
+#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
+
+#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
+#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
+/*! TIMRST - Timer Reset
+ *  0b000..Timer never reset
+ *  0b001..Reserved
+ *  0b010..Timer reset on Timer Pin equal to Timer Output
+ *  0b011..Timer reset on Timer Trigger equal to Timer Output
+ *  0b100..Timer reset on Timer Pin rising edge
+ *  0b101..Reserved
+ *  0b110..Timer reset on Trigger rising edge
+ *  0b111..Timer reset on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
+
+#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
+/*! TIMDEC - Timer Decrement
+ *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
+ *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
+ *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
+ */
+#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
+
+#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
+/*! TIMOUT - Timer Output
+ *  0b00..Timer output is logic one when enabled and is not affected by timer reset
+ *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
+ *  0b10..Timer output is logic one when enabled and on timer reset
+ *  0b11..Timer output is logic zero when enabled and on timer reset
+ */
+#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCFG */
+#define FLEXIO_TIMCFG_COUNT                      (4U)
+
+/*! @name TIMCMP - Timer Compare N Register */
+/*! @{ */
+
+#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
+#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
+/*! CMP - Timer Compare Value */
+#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCMP */
+#define FLEXIO_TIMCMP_COUNT                      (4U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO base address */
+#define FLEXIO_BASE                              (0x4005F000u)
+/** Peripheral FLEXIO base pointer */
+#define FLEXIO                                   ((FLEXIO_Type *)FLEXIO_BASE)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS                        { FLEXIO_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS                         { FLEXIO }
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS                              { UART2_FLEXIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+/*! @{ */
+
+#define FTFA_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT                 (0U)
+/*! MGSTAT0 - Memory Controller Command Completion Status Flag */
+#define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+
+#define FTFA_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT                  (4U)
+/*! FPVIOL - Flash Protection Violation Flag
+ *  0b0..No protection violation detected
+ *  0b1..Protection violation detected
+ */
+#define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+
+#define FTFA_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT                  (5U)
+/*! ACCERR - Flash Access Error Flag
+ *  0b0..No access error detected
+ *  0b1..Access error detected
+ */
+#define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+
+#define FTFA_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT                (6U)
+/*! RDCOLERR - Flash Read Collision Error Flag
+ *  0b0..No collision error detected
+ *  0b1..Collision error detected
+ */
+#define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+
+#define FTFA_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT                    (7U)
+/*! CCIF - Command Complete Interrupt Flag
+ *  0b0..Flash command in progress
+ *  0b1..Flash command has completed
+ */
+#define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+/*! @} */
+
+/*! @name FCNFG - Flash Configuration Register */
+/*! @{ */
+
+#define FTFA_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT                 (4U)
+/*! ERSSUSP - Erase Suspend
+ *  0b0..No suspend requested
+ *  0b1..Suspend the current Erase Flash Sector command execution.
+ */
+#define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+
+#define FTFA_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT                 (5U)
+/*! ERSAREQ - Erase All Request
+ *  0b0..No request or request complete
+ *  0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the
+ *       Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to
+ *       the unsecure state.
+ */
+#define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+
+#define FTFA_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT                (6U)
+/*! RDCOLLIE - Read Collision Error Interrupt Enable
+ *  0b0..Read collision error interrupt disabled
+ *  0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read
+ *       collision error is detected (see the description of FSTAT[RDCOLERR]).
+ */
+#define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+
+#define FTFA_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT                    (7U)
+/*! CCIE - Command Complete Interrupt Enable
+ *  0b0..Command complete interrupt disabled
+ *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
+ */
+#define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+/*! @} */
+
+/*! @name FSEC - Flash Security Register */
+/*! @{ */
+
+#define FTFA_FSEC_SEC_MASK                       (0x3U)
+#define FTFA_FSEC_SEC_SHIFT                      (0U)
+/*! SEC - Flash Security
+ *  0b00..MCU security status is secure.
+ *  0b01..MCU security status is secure.
+ *  0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
+ *  0b11..MCU security status is secure.
+ */
+#define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+
+#define FTFA_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT                   (2U)
+/*! FSLACC - Freescale Failure Analysis Access Code
+ *  0b00..Freescale factory access granted
+ *  0b01..Freescale factory access denied
+ *  0b10..Freescale factory access denied
+ *  0b11..Freescale factory access granted
+ */
+#define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+
+#define FTFA_FSEC_MEEN_MASK                      (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT                     (4U)
+/*! MEEN - Mass Erase Enable Bits
+ *  0b00..Mass erase is enabled
+ *  0b01..Mass erase is enabled
+ *  0b10..Mass erase is disabled
+ *  0b11..Mass erase is enabled
+ */
+#define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+
+#define FTFA_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT                    (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ *  0b00..Backdoor key access disabled
+ *  0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
+ *  0b10..Backdoor key access enabled
+ *  0b11..Backdoor key access disabled
+ */
+#define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FOPT - Flash Option Register */
+/*! @{ */
+
+#define FTFA_FOPT_OPT_MASK                       (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT                      (0U)
+/*! OPT - Nonvolatile Option */
+#define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+/*! @} */
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+/*! @{ */
+
+#define FTFA_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+/*! @} */
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+/*! @{ */
+
+#define FTFA_FPROT3_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT                   (0U)
+/*! PROT - Program Flash Region Protect
+ *  0b00000000..Program flash region is protected.
+ *  0b00000001..Program flash region is not protected
+ */
+#define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+/*! @{ */
+
+#define FTFA_FPROT2_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT                   (0U)
+/*! PROT - Program Flash Region Protect
+ *  0b00000000..Program flash region is protected.
+ *  0b00000001..Program flash region is not protected
+ */
+#define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+/*! @{ */
+
+#define FTFA_FPROT1_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT                   (0U)
+/*! PROT - Program Flash Region Protect
+ *  0b00000000..Program flash region is protected.
+ *  0b00000001..Program flash region is not protected
+ */
+#define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+/*! @{ */
+
+#define FTFA_FPROT0_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT                   (0U)
+/*! PROT - Program Flash Region Protect
+ *  0b00000000..Program flash region is protected.
+ *  0b00000001..Program flash region is not protected
+ */
+#define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE                                (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA                                     ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS                          { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+/*! PDO - Port Data Output
+ *  0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
+ *  0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
+ */
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+/*! PTSO - Port Set Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
+ */
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+/*! PTCO - Port Clear Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
+ */
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+/*! PTTO - Port Toggle Output
+ *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
+ */
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+/*! PDI - Port Data Input
+ *  0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
+ *  0b00000000000000000000000000000001..Pin logic level is logic 1.
+ */
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+/*! PDD - Port Data Direction
+ *  0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
+ *  0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
+ */
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+  __IO uint8_t S2;                                 /**< I2C Status register 2, offset: 0xC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+/*! @{ */
+
+#define I2C_A1_AD_MASK                           (0xFEU)
+#define I2C_A1_AD_SHIFT                          (1U)
+/*! AD - Address */
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+/*! @} */
+
+/*! @name F - I2C Frequency Divider register */
+/*! @{ */
+
+#define I2C_F_ICR_MASK                           (0x3FU)
+#define I2C_F_ICR_SHIFT                          (0U)
+/*! ICR - ClockRate */
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+
+#define I2C_F_MULT_MASK                          (0xC0U)
+#define I2C_F_MULT_SHIFT                         (6U)
+/*! MULT - Multiplier Factor
+ *  0b00..mul = 1
+ *  0b01..mul = 2
+ *  0b10..mul = 4
+ *  0b11..Reserved
+ */
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+/*! @} */
+
+/*! @name C1 - I2C Control Register 1 */
+/*! @{ */
+
+#define I2C_C1_DMAEN_MASK                        (0x1U)
+#define I2C_C1_DMAEN_SHIFT                       (0U)
+/*! DMAEN - DMA Enable
+ *  0b0..All DMA signalling disabled.
+ *  0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data
+ *       byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received
+ *       matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF]
+ *       are set. If the direction of transfer is known from master to slave, then it is not required to check
+ *       S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from
+ *       the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be
+ *       used. When FACK = 1, an address or a data byte is transmitted.
+ */
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+
+#define I2C_C1_WUEN_MASK                         (0x2U)
+#define I2C_C1_WUEN_SHIFT                        (1U)
+/*! WUEN - Wakeup Enable
+ *  0b0..Normal operation. No interrupt generated when address matching in low power mode.
+ *  0b1..Enables the wakeup function in low power mode.
+ */
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+
+#define I2C_C1_RSTA_MASK                         (0x4U)
+#define I2C_C1_RSTA_SHIFT                        (2U)
+/*! RSTA - Repeat START */
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+
+#define I2C_C1_TXAK_MASK                         (0x8U)
+#define I2C_C1_TXAK_SHIFT                        (3U)
+/*! TXAK - Transmit Acknowledge Enable
+ *  0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the
+ *       current receiving byte (if FACK is set).
+ *  0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the
+ *       current receiving data byte (if FACK is set).
+ */
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+
+#define I2C_C1_TX_MASK                           (0x10U)
+#define I2C_C1_TX_SHIFT                          (4U)
+/*! TX - Transmit Mode Select
+ *  0b0..Receive
+ *  0b1..Transmit
+ */
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+
+#define I2C_C1_MST_MASK                          (0x20U)
+#define I2C_C1_MST_SHIFT                         (5U)
+/*! MST - Master Mode Select
+ *  0b0..Slave mode
+ *  0b1..Master mode
+ */
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+
+#define I2C_C1_IICIE_MASK                        (0x40U)
+#define I2C_C1_IICIE_SHIFT                       (6U)
+/*! IICIE - I2C Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+
+#define I2C_C1_IICEN_MASK                        (0x80U)
+#define I2C_C1_IICEN_SHIFT                       (7U)
+/*! IICEN - I2C Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+/*! @} */
+
+/*! @name S - I2C Status register */
+/*! @{ */
+
+#define I2C_S_RXAK_MASK                          (0x1U)
+#define I2C_S_RXAK_SHIFT                         (0U)
+/*! RXAK - Receive Acknowledge
+ *  0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
+ *  0b1..No acknowledge signal detected
+ */
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+
+#define I2C_S_IICIF_MASK                         (0x2U)
+#define I2C_S_IICIF_SHIFT                        (1U)
+/*! IICIF - Interrupt Flag
+ *  0b0..No interrupt pending
+ *  0b1..Interrupt pending
+ */
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+
+#define I2C_S_SRW_MASK                           (0x4U)
+#define I2C_S_SRW_SHIFT                          (2U)
+/*! SRW - Slave Read/Write
+ *  0b0..Slave receive, master writing to slave
+ *  0b1..Slave transmit, master reading from slave
+ */
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+
+#define I2C_S_RAM_MASK                           (0x8U)
+#define I2C_S_RAM_SHIFT                          (3U)
+/*! RAM - Range Address Match
+ *  0b0..Not addressed
+ *  0b1..Addressed as a slave
+ */
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+
+#define I2C_S_ARBL_MASK                          (0x10U)
+#define I2C_S_ARBL_SHIFT                         (4U)
+/*! ARBL - Arbitration Lost
+ *  0b0..Standard bus operation.
+ *  0b1..Loss of arbitration.
+ */
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+
+#define I2C_S_BUSY_MASK                          (0x20U)
+#define I2C_S_BUSY_SHIFT                         (5U)
+/*! BUSY - Bus Busy
+ *  0b0..Bus is idle
+ *  0b1..Bus is busy
+ */
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+
+#define I2C_S_IAAS_MASK                          (0x40U)
+#define I2C_S_IAAS_SHIFT                         (6U)
+/*! IAAS - Addressed As A Slave
+ *  0b0..Not addressed
+ *  0b1..Addressed as a slave
+ */
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+
+#define I2C_S_TCF_MASK                           (0x80U)
+#define I2C_S_TCF_SHIFT                          (7U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..Transfer in progress
+ *  0b1..Transfer complete
+ */
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+/*! @} */
+
+/*! @name D - I2C Data I/O register */
+/*! @{ */
+
+#define I2C_D_DATA_MASK                          (0xFFU)
+#define I2C_D_DATA_SHIFT                         (0U)
+/*! DATA - Data */
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+/*! @} */
+
+/*! @name C2 - I2C Control Register 2 */
+/*! @{ */
+
+#define I2C_C2_AD_MASK                           (0x7U)
+#define I2C_C2_AD_SHIFT                          (0U)
+/*! AD - Slave Address */
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+
+#define I2C_C2_RMEN_MASK                         (0x8U)
+#define I2C_C2_RMEN_SHIFT                        (3U)
+/*! RMEN - Range Address Matching Enable
+ *  0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
+ *  0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
+ */
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+
+#define I2C_C2_SBRC_MASK                         (0x10U)
+#define I2C_C2_SBRC_SHIFT                        (4U)
+/*! SBRC - Slave Baud Rate Control
+ *  0b0..The slave baud rate follows the master baud rate and clock stretching may occur
+ *  0b1..Slave baud rate is independent of the master baud rate
+ */
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+
+#define I2C_C2_HDRS_MASK                         (0x20U)
+#define I2C_C2_HDRS_SHIFT                        (5U)
+/*! HDRS - High Drive Select
+ *  0b0..Normal drive mode
+ *  0b1..High drive mode
+ */
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+
+#define I2C_C2_ADEXT_MASK                        (0x40U)
+#define I2C_C2_ADEXT_SHIFT                       (6U)
+/*! ADEXT - Address Extension
+ *  0b0..7-bit address scheme
+ *  0b1..10-bit address scheme
+ */
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+
+#define I2C_C2_GCAEN_MASK                        (0x80U)
+#define I2C_C2_GCAEN_SHIFT                       (7U)
+/*! GCAEN - General Call Address Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+/*! @} */
+
+/*! @name FLT - I2C Programmable Input Glitch Filter Register */
+/*! @{ */
+
+#define I2C_FLT_FLT_MASK                         (0xFU)
+#define I2C_FLT_FLT_SHIFT                        (0U)
+/*! FLT - I2C Programmable Filter Factor
+ *  0b0000..No filter/bypass
+ *  0b0001-0b1111..Filter glitches up to width of n I2C module clock cycles, where n=1-15d
+ */
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+
+#define I2C_FLT_STARTF_MASK                      (0x10U)
+#define I2C_FLT_STARTF_SHIFT                     (4U)
+/*! STARTF - I2C Bus Start Detect Flag
+ *  0b0..No start happens on I2C bus
+ *  0b1..Start detected on I2C bus
+ */
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+
+#define I2C_FLT_SSIE_MASK                        (0x20U)
+#define I2C_FLT_SSIE_SHIFT                       (5U)
+/*! SSIE - I2C Bus Stop or Start Interrupt Enable
+ *  0b0..Stop or start detection interrupt is disabled
+ *  0b1..Stop or start detection interrupt is enabled
+ */
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+
+#define I2C_FLT_STOPF_MASK                       (0x40U)
+#define I2C_FLT_STOPF_SHIFT                      (6U)
+/*! STOPF - I2C Bus Stop Detect Flag
+ *  0b0..No stop happens on I2C bus
+ *  0b1..Stop detected on I2C bus
+ */
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+
+#define I2C_FLT_SHEN_MASK                        (0x80U)
+#define I2C_FLT_SHEN_SHIFT                       (7U)
+/*! SHEN - Stop Hold Enable
+ *  0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ *  0b1..Stop holdoff is enabled.
+ */
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+/*! @} */
+
+/*! @name RA - I2C Range Address register */
+/*! @{ */
+
+#define I2C_RA_RAD_MASK                          (0xFEU)
+#define I2C_RA_RAD_SHIFT                         (1U)
+/*! RAD - Range Slave Address */
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+/*! @} */
+
+/*! @name SMB - I2C SMBus Control and Status register */
+/*! @{ */
+
+#define I2C_SMB_SHTF2IE_MASK                     (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT                    (0U)
+/*! SHTF2IE - SHTF2 Interrupt Enable
+ *  0b0..SHTF2 interrupt is disabled
+ *  0b1..SHTF2 interrupt is enabled
+ */
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+
+#define I2C_SMB_SHTF2_MASK                       (0x2U)
+#define I2C_SMB_SHTF2_SHIFT                      (1U)
+/*! SHTF2 - SCL High Timeout Flag 2
+ *  0b0..No SCL high and SDA low timeout occurs
+ *  0b1..SCL high and SDA low timeout occurs
+ */
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+
+#define I2C_SMB_SHTF1_MASK                       (0x4U)
+#define I2C_SMB_SHTF1_SHIFT                      (2U)
+/*! SHTF1 - SCL High Timeout Flag 1
+ *  0b0..No SCL high and SDA high timeout occurs
+ *  0b1..SCL high and SDA high timeout occurs
+ */
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+
+#define I2C_SMB_SLTF_MASK                        (0x8U)
+#define I2C_SMB_SLTF_SHIFT                       (3U)
+/*! SLTF - SCL Low Timeout Flag
+ *  0b0..No low timeout occurs
+ *  0b1..Low timeout occurs
+ */
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+
+#define I2C_SMB_TCKSEL_MASK                      (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT                     (4U)
+/*! TCKSEL - Timeout Counter Clock Select
+ *  0b0..Timeout counter counts at the frequency of the I2C module clock / 64
+ *  0b1..Timeout counter counts at the frequency of the I2C module clock
+ */
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+
+#define I2C_SMB_SIICAEN_MASK                     (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT                    (5U)
+/*! SIICAEN - Second I2C Address Enable
+ *  0b0..I2C address register 2 matching is disabled
+ *  0b1..I2C address register 2 matching is enabled
+ */
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+
+#define I2C_SMB_ALERTEN_MASK                     (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT                    (6U)
+/*! ALERTEN - SMBus Alert Response Address Enable
+ *  0b0..SMBus alert response address matching is disabled
+ *  0b1..SMBus alert response address matching is enabled
+ */
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+
+#define I2C_SMB_FACK_MASK                        (0x80U)
+#define I2C_SMB_FACK_SHIFT                       (7U)
+/*! FACK - Fast NACK/ACK Enable
+ *  0b0..An ACK or NACK is sent on the following receiving data byte
+ *  0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+/*! @} */
+
+/*! @name A2 - I2C Address Register 2 */
+/*! @{ */
+
+#define I2C_A2_SAD_MASK                          (0xFEU)
+#define I2C_A2_SAD_SHIFT                         (1U)
+/*! SAD - SMBus Address */
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+/*! @} */
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+/*! @{ */
+
+#define I2C_SLTH_SSLT_MASK                       (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT                      (0U)
+/*! SSLT - SSLT[15:8] */
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+/*! @} */
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+/*! @{ */
+
+#define I2C_SLTL_SSLT_MASK                       (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT                      (0U)
+/*! SSLT - SSLT[7:0] */
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+/*! @} */
+
+/*! @name S2 - I2C Status register 2 */
+/*! @{ */
+
+#define I2C_S2_EMPTY_MASK                        (0x1U)
+#define I2C_S2_EMPTY_SHIFT                       (0U)
+/*! EMPTY - Empty flag
+ *  0b0..Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
+ *  0b1..Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.
+ */
+#define I2C_S2_EMPTY(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
+
+#define I2C_S2_ERROR_MASK                        (0x2U)
+#define I2C_S2_ERROR_SHIFT                       (1U)
+/*! ERROR - Error flag
+ *  0b0..The buffer is not full and all write/read operations have no errors.
+ *  0b1..There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).
+ */
+#define I2C_S2_ERROR(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_2[60];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+/*! @{ */
+
+#define I2S_TCSR_FWDE_MASK                       (0x2U)
+#define I2S_TCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+
+#define I2S_TCSR_FWIE_MASK                       (0x200U)
+#define I2S_TCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+
+#define I2S_TCSR_FEIE_MASK                       (0x400U)
+#define I2S_TCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+
+#define I2S_TCSR_SEIE_MASK                       (0x800U)
+#define I2S_TCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+
+#define I2S_TCSR_WSIE_MASK                       (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+
+#define I2S_TCSR_FWF_MASK                        (0x20000U)
+#define I2S_TCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled transmit FIFO is empty.
+ *  0b1..Enabled transmit FIFO is empty.
+ */
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+
+#define I2S_TCSR_FEF_MASK                        (0x40000U)
+#define I2S_TCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Transmit underrun not detected.
+ *  0b1..Transmit underrun detected.
+ */
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+
+#define I2S_TCSR_SEF_MASK                        (0x80000U)
+#define I2S_TCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+
+#define I2S_TCSR_WSF_MASK                        (0x100000U)
+#define I2S_TCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+
+#define I2S_TCSR_SR_MASK                         (0x1000000U)
+#define I2S_TCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+
+#define I2S_TCSR_FR_MASK                         (0x2000000U)
+#define I2S_TCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+
+#define I2S_TCSR_BCE_MASK                        (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Transmit bit clock is disabled.
+ *  0b1..Transmit bit clock is enabled.
+ */
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+
+#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
+ *  0b1..Transmitter is enabled in Debug mode.
+ */
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+
+#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Transmitter disabled in Stop mode.
+ *  0b1..Transmitter enabled in Stop mode.
+ */
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+
+#define I2S_TCSR_TE_MASK                         (0x80000000U)
+#define I2S_TCSR_TE_SHIFT                        (31U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter is disabled.
+ *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
+ */
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+/*! @} */
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+/*! @{ */
+
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+/*! DIV - Bit Clock Divide */
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+
+#define I2S_TCR2_BCD_MASK                        (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+
+#define I2S_TCR2_BCP_MASK                        (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+
+#define I2S_TCR2_BCI_MASK                        (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+
+#define I2S_TCR2_BCS_MASK                        (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with receiver.
+ *  0b10..Synchronous with another SAI transmitter.
+ *  0b11..Synchronous with another SAI receiver.
+ */
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+/*! @{ */
+
+#define I2S_TCR3_WDFL_MASK                       (0x1U)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+/*! WDFL - Word Flag Configuration */
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+
+#define I2S_TCR3_TCE_MASK                        (0x10000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+/*! TCE - Transmit Channel Enable
+ *  0b0..Transmit data channel N is disabled.
+ *  0b1..Transmit data channel N is enabled.
+ */
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+/*! @} */
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+/*! @{ */
+
+#define I2S_TCR4_FSD_MASK                        (0x1U)
+#define I2S_TCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame sync is generated externally in Slave mode.
+ *  0b1..Frame sync is generated internally in Master mode.
+ */
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+
+#define I2S_TCR4_FSP_MASK                        (0x2U)
+#define I2S_TCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+
+#define I2S_TCR4_ONDEM_MASK                      (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+
+#define I2S_TCR4_FSE_MASK                        (0x8U)
+#define I2S_TCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+
+#define I2S_TCR4_MF_MASK                         (0x10U)
+#define I2S_TCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is transmitted first.
+ *  0b1..MSB is transmitted first.
+ */
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+/*! SYWD - Sync Width */
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+
+#define I2S_TCR4_FRSZ_MASK                       (0x10000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+/*! FRSZ - Frame size */
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+
+#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+/*! @{ */
+
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+/*! FBT - First Bit Shifted */
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+/*! W0W - Word 0 Width */
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+/*! WNW - Word N Width */
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+/*! @} */
+
+/*! @name TDR - SAI Transmit Data Register */
+/*! @{ */
+
+#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT                        (0U)
+/*! TDR - Transmit Data Register */
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+/*! @} */
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (1U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+/*! @{ */
+
+#define I2S_TMR_TWM_MASK                         (0x3U)
+#define I2S_TMR_TWM_SHIFT                        (0U)
+/*! TWM - Transmit Word Mask
+ *  0b00..Word N is enabled.
+ *  0b01..Word N is masked. The transmit data pins are tri-stated when masked.
+ */
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+/*! @} */
+
+/*! @name RCSR - SAI Receive Control Register */
+/*! @{ */
+
+#define I2S_RCSR_FWDE_MASK                       (0x2U)
+#define I2S_RCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+
+#define I2S_RCSR_FWIE_MASK                       (0x200U)
+#define I2S_RCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+
+#define I2S_RCSR_FEIE_MASK                       (0x400U)
+#define I2S_RCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+
+#define I2S_RCSR_SEIE_MASK                       (0x800U)
+#define I2S_RCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+
+#define I2S_RCSR_WSIE_MASK                       (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+
+#define I2S_RCSR_FWF_MASK                        (0x20000U)
+#define I2S_RCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled receive FIFO is full.
+ *  0b1..Enabled receive FIFO is full.
+ */
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+
+#define I2S_RCSR_FEF_MASK                        (0x40000U)
+#define I2S_RCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Receive overflow not detected.
+ *  0b1..Receive overflow detected.
+ */
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+
+#define I2S_RCSR_SEF_MASK                        (0x80000U)
+#define I2S_RCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+
+#define I2S_RCSR_WSF_MASK                        (0x100000U)
+#define I2S_RCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+
+#define I2S_RCSR_SR_MASK                         (0x1000000U)
+#define I2S_RCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+
+#define I2S_RCSR_FR_MASK                         (0x2000000U)
+#define I2S_RCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+
+#define I2S_RCSR_BCE_MASK                        (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Receive bit clock is disabled.
+ *  0b1..Receive bit clock is enabled.
+ */
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+
+#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
+ *  0b1..Receiver is enabled in Debug mode.
+ */
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+
+#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Receiver disabled in Stop mode.
+ *  0b1..Receiver enabled in Stop mode.
+ */
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+
+#define I2S_RCSR_RE_MASK                         (0x80000000U)
+#define I2S_RCSR_RE_SHIFT                        (31U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver is disabled.
+ *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
+ */
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+/*! @} */
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+/*! @{ */
+
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+/*! DIV - Bit Clock Divide */
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+
+#define I2S_RCR2_BCD_MASK                        (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+
+#define I2S_RCR2_BCP_MASK                        (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+
+#define I2S_RCR2_BCI_MASK                        (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+
+#define I2S_RCR2_BCS_MASK                        (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with transmitter.
+ *  0b10..Synchronous with another SAI receiver.
+ *  0b11..Synchronous with another SAI transmitter.
+ */
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+/*! @{ */
+
+#define I2S_RCR3_WDFL_MASK                       (0x1U)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+/*! WDFL - Word Flag Configuration */
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+
+#define I2S_RCR3_RCE_MASK                        (0x10000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+/*! RCE - Receive Channel Enable
+ *  0b0..Receive data channel N is disabled.
+ *  0b1..Receive data channel N is enabled.
+ */
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+/*! @} */
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+/*! @{ */
+
+#define I2S_RCR4_FSD_MASK                        (0x1U)
+#define I2S_RCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame Sync is generated externally in Slave mode.
+ *  0b1..Frame Sync is generated internally in Master mode.
+ */
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+
+#define I2S_RCR4_FSP_MASK                        (0x2U)
+#define I2S_RCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+
+#define I2S_RCR4_ONDEM_MASK                      (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+
+#define I2S_RCR4_FSE_MASK                        (0x8U)
+#define I2S_RCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+
+#define I2S_RCR4_MF_MASK                         (0x10U)
+#define I2S_RCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is received first.
+ *  0b1..MSB is received first.
+ */
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+/*! SYWD - Sync Width */
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+
+#define I2S_RCR4_FRSZ_MASK                       (0x10000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+/*! FRSZ - Frame Size */
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved.
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+
+#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+/*! @{ */
+
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+/*! FBT - First Bit Shifted */
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+/*! W0W - Word 0 Width */
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+/*! WNW - Word N Width */
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+/*! @} */
+
+/*! @name RDR - SAI Receive Data Register */
+/*! @{ */
+
+#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT                        (0U)
+/*! RDR - Receive Data Register */
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+/*! @} */
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (1U)
+
+/*! @name RMR - SAI Receive Mask Register */
+/*! @{ */
+
+#define I2S_RMR_RWM_MASK                         (0x3U)
+#define I2S_RMR_RWM_SHIFT                        (0U)
+/*! RWM - Receive Word Mask
+ *  0b00..Word N is enabled.
+ *  0b01..Word N is masked.
+ */
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+/*! @} */
+
+/*! @name MCR - SAI MCLK Control Register */
+/*! @{ */
+
+#define I2S_MCR_MICS_MASK                        (0x3000000U)
+#define I2S_MCR_MICS_SHIFT                       (24U)
+/*! MICS - MCLK Input Clock Select
+ *  0b00..MCLK divider input clock 0 selected.
+ *  0b01..MCLK divider input clock 1 selected.
+ *  0b10..MCLK divider input clock 2 selected.
+ *  0b11..MCLK divider input clock 3 selected.
+ */
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+
+#define I2S_MCR_MOE_MASK                         (0x40000000U)
+#define I2S_MCR_MOE_SHIFT                        (30U)
+/*! MOE - MCLK Output Enable
+ *  0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider.
+ *  0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
+ */
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+
+#define I2S_MCR_DUF_MASK                         (0x80000000U)
+#define I2S_MCR_DUF_SHIFT                        (31U)
+/*! DUF - Divider Update Flag
+ *  0b0..MCLK divider ratio is not being updated currently.
+ *  0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
+ */
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_IRQn }
+#define I2S_TX_IRQS                              { I2S0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GCR;                               /**< LCD General Control Register, offset: 0x0 */
+  __IO uint32_t AR;                                /**< LCD Auxiliary Register, offset: 0x4 */
+  __IO uint32_t FDCR;                              /**< LCD Fault Detect Control Register, offset: 0x8 */
+  __IO uint32_t FDSR;                              /**< LCD Fault Detect Status Register, offset: 0xC */
+  __IO uint32_t PEN[2];                            /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t BPEN[2];                           /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+  union {                                          /* offset: 0x20 */
+    __IO uint8_t WF8B[64];                           /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+    __IO uint32_t WF[16];                            /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+  };
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/*! @name GCR - LCD General Control Register */
+/*! @{ */
+
+#define LCD_GCR_DUTY_MASK                        (0x7U)
+#define LCD_GCR_DUTY_SHIFT                       (0U)
+/*! DUTY - LCD duty select
+ *  0b000..Use 1 BP (1/1 duty cycle).
+ *  0b001..Use 2 BP (1/2 duty cycle).
+ *  0b010..Use 3 BP (1/3 duty cycle).
+ *  0b011..Use 4 BP (1/4 duty cycle). (Default)
+ *  0b100..
+ *  0b101..
+ *  0b110..
+ *  0b111..Use 8 BP (1/8 duty cycle).
+ */
+#define LCD_GCR_DUTY(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_GCR_DUTY_SHIFT)) & LCD_GCR_DUTY_MASK)
+
+#define LCD_GCR_LCLK_MASK                        (0x38U)
+#define LCD_GCR_LCLK_SHIFT                       (3U)
+/*! LCLK - LCD Clock Prescaler */
+#define LCD_GCR_LCLK(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCLK_SHIFT)) & LCD_GCR_LCLK_MASK)
+
+#define LCD_GCR_SOURCE_MASK                      (0x40U)
+#define LCD_GCR_SOURCE_SHIFT                     (6U)
+/*! SOURCE - LCD Clock Source Select
+ *  0b0..Selects the default clock as the LCD clock source.
+ *  0b1..Selects output of the alternate clock source selection (see ALTSOURCE) as the LCD clock source.
+ */
+#define LCD_GCR_SOURCE(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SOURCE_SHIFT)) & LCD_GCR_SOURCE_MASK)
+
+#define LCD_GCR_LCDEN_MASK                       (0x80U)
+#define LCD_GCR_LCDEN_SHIFT                      (7U)
+/*! LCDEN - LCD Driver Enable
+ *  0b0..All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD
+ *       waveform generation clocks are stopped. V LL3 is connected to V DD internally. All LCD pins, LCD_Pn,
+ *       enabled using the LCD Pin Enable register, output a low value.
+ *  0b1..LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD
+ *       pins, LCD_Pn, enabled if PAD_SAFE is clearusing the LCD Pin Enable register, output an LCD driver
+ *       waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. Charge
+ *       pump or resistor bias is enabled.
+ */
+#define LCD_GCR_LCDEN(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDEN_SHIFT)) & LCD_GCR_LCDEN_MASK)
+
+#define LCD_GCR_LCDSTP_MASK                      (0x100U)
+#define LCD_GCR_LCDSTP_SHIFT                     (8U)
+/*! LCDSTP - LCD Stop
+ *  0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.
+ *  0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Stop mode.
+ */
+#define LCD_GCR_LCDSTP(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDSTP_SHIFT)) & LCD_GCR_LCDSTP_MASK)
+
+#define LCD_GCR_LCDDOZE_MASK                     (0x200U)
+#define LCD_GCR_LCDDOZE_SHIFT                    (9U)
+/*! LCDDOZE - LCD Doze enable
+ *  0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Doze mode.
+ *  0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Doze mode.
+ */
+#define LCD_GCR_LCDDOZE(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDDOZE_SHIFT)) & LCD_GCR_LCDDOZE_MASK)
+
+#define LCD_GCR_FFR_MASK                         (0x400U)
+#define LCD_GCR_FFR_SHIFT                        (10U)
+/*! FFR - Fast Frame Rate Select
+ *  0b0..Standard Frame Rate LCD Frame Freq: 23.3 (min) 73.1 (max)
+ *  0b1..Fast Frame Rate (Standard Frame Rate x2) LCD Frame Freq: 46.6 (min) 146.2 (max)
+ */
+#define LCD_GCR_FFR(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FFR_SHIFT)) & LCD_GCR_FFR_MASK)
+
+#define LCD_GCR_ALTSOURCE_MASK                   (0x800U)
+#define LCD_GCR_ALTSOURCE_SHIFT                  (11U)
+/*! ALTSOURCE - Selects the alternate clock source
+ *  0b0..Select Alternate Clock Source 1 (default)
+ *  0b1..Select Alternate Clock Source 2
+ */
+#define LCD_GCR_ALTSOURCE(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTSOURCE_SHIFT)) & LCD_GCR_ALTSOURCE_MASK)
+
+#define LCD_GCR_ALTDIV_MASK                      (0x3000U)
+#define LCD_GCR_ALTDIV_SHIFT                     (12U)
+/*! ALTDIV - LCD AlternateClock Divider
+ *  0b00..Divide factor = 1 (No divide)
+ *  0b01..Divide factor = 8
+ *  0b10..Divide factor = 64
+ *  0b11..Divide factor = 512
+ */
+#define LCD_GCR_ALTDIV(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTDIV_SHIFT)) & LCD_GCR_ALTDIV_MASK)
+
+#define LCD_GCR_FDCIEN_MASK                      (0x4000U)
+#define LCD_GCR_FDCIEN_SHIFT                     (14U)
+/*! FDCIEN - LCD Fault Detection Complete Interrupt Enable
+ *  0b0..No interrupt request is generated by this event.
+ *  0b1..When a fault is detected and FDCF bit is set, this event causes an interrupt request.
+ */
+#define LCD_GCR_FDCIEN(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FDCIEN_SHIFT)) & LCD_GCR_FDCIEN_MASK)
+
+#define LCD_GCR_PADSAFE_MASK                     (0x8000U)
+#define LCD_GCR_PADSAFE_SHIFT                    (15U)
+/*! PADSAFE - Pad Safe State Enable
+ *  0b0..LCD frontplane and backplane functions enabled according to other LCD control bits
+ *  0b1..LCD frontplane and backplane functions disabled
+ */
+#define LCD_GCR_PADSAFE(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_GCR_PADSAFE_SHIFT)) & LCD_GCR_PADSAFE_MASK)
+
+#define LCD_GCR_VSUPPLY_MASK                     (0x20000U)
+#define LCD_GCR_VSUPPLY_SHIFT                    (17U)
+/*! VSUPPLY - Voltage Supply Control
+ *  0b0..Drive VLL3 internally from VDD
+ *  0b1..Drive VLL3 externally from VDD or drive VLL internally from vIREG
+ */
+#define LCD_GCR_VSUPPLY(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VSUPPLY_SHIFT)) & LCD_GCR_VSUPPLY_MASK)
+
+#define LCD_GCR_LADJ_MASK                        (0x300000U)
+#define LCD_GCR_LADJ_SHIFT                       (20U)
+/*! LADJ - Load Adjust */
+#define LCD_GCR_LADJ(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LADJ_SHIFT)) & LCD_GCR_LADJ_MASK)
+
+#define LCD_GCR_CPSEL_MASK                       (0x800000U)
+#define LCD_GCR_CPSEL_SHIFT                      (23U)
+/*! CPSEL - Charge Pump or Resistor Bias Select
+ *  0b0..LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)
+ *  0b1..LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)
+ */
+#define LCD_GCR_CPSEL(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_GCR_CPSEL_SHIFT)) & LCD_GCR_CPSEL_MASK)
+
+#define LCD_GCR_RVTRIM_MASK                      (0xF000000U)
+#define LCD_GCR_RVTRIM_SHIFT                     (24U)
+/*! RVTRIM - Regulated Voltage Trim */
+#define LCD_GCR_RVTRIM(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVTRIM_SHIFT)) & LCD_GCR_RVTRIM_MASK)
+
+#define LCD_GCR_RVEN_MASK                        (0x80000000U)
+#define LCD_GCR_RVEN_SHIFT                       (31U)
+/*! RVEN - Regulated Voltage Enable
+ *  0b0..Regulated voltage disabled.
+ *  0b1..Regulated voltage enabled.
+ */
+#define LCD_GCR_RVEN(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVEN_SHIFT)) & LCD_GCR_RVEN_MASK)
+/*! @} */
+
+/*! @name AR - LCD Auxiliary Register */
+/*! @{ */
+
+#define LCD_AR_BRATE_MASK                        (0x7U)
+#define LCD_AR_BRATE_SHIFT                       (0U)
+/*! BRATE - Blink-rate configuration */
+#define LCD_AR_BRATE(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_AR_BRATE_SHIFT)) & LCD_AR_BRATE_MASK)
+
+#define LCD_AR_BMODE_MASK                        (0x8U)
+#define LCD_AR_BMODE_SHIFT                       (3U)
+/*! BMODE - Blink mode
+ *  0b0..Display blank during the blink period.
+ *  0b1..Display alternate display during blink period (Ignored if duty is 5 or greater).
+ */
+#define LCD_AR_BMODE(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_AR_BMODE_SHIFT)) & LCD_AR_BMODE_MASK)
+
+#define LCD_AR_BLANK_MASK                        (0x20U)
+#define LCD_AR_BLANK_SHIFT                       (5U)
+/*! BLANK - Blank display mode
+ *  0b0..Normal or alternate display mode.
+ *  0b1..Blank display mode.
+ */
+#define LCD_AR_BLANK(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLANK_SHIFT)) & LCD_AR_BLANK_MASK)
+
+#define LCD_AR_ALT_MASK                          (0x40U)
+#define LCD_AR_ALT_SHIFT                         (6U)
+/*! ALT - Alternate display mode
+ *  0b0..Normal display mode.
+ *  0b1..Alternate display mode.
+ */
+#define LCD_AR_ALT(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_AR_ALT_SHIFT)) & LCD_AR_ALT_MASK)
+
+#define LCD_AR_BLINK_MASK                        (0x80U)
+#define LCD_AR_BLINK_SHIFT                       (7U)
+/*! BLINK - Blink command
+ *  0b0..Disables blinking.
+ *  0b1..Starts blinking at blinking frequency specified by LCD blink rate calculation.
+ */
+#define LCD_AR_BLINK(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLINK_SHIFT)) & LCD_AR_BLINK_MASK)
+/*! @} */
+
+/*! @name FDCR - LCD Fault Detect Control Register */
+/*! @{ */
+
+#define LCD_FDCR_FDPINID_MASK                    (0x3FU)
+#define LCD_FDCR_FDPINID_SHIFT                   (0U)
+/*! FDPINID - Fault Detect Pin ID
+ *  0b000000..Fault detection for LCD_P0 pin.
+ *  0b000001..Fault detection for LCD_P1 pin.
+ *  0b111111..Fault detection for LCD_P63 pin.
+ */
+#define LCD_FDCR_FDPINID(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPINID_SHIFT)) & LCD_FDCR_FDPINID_MASK)
+
+#define LCD_FDCR_FDBPEN_MASK                     (0x40U)
+#define LCD_FDCR_FDBPEN_SHIFT                    (6U)
+/*! FDBPEN - Fault Detect Back Plane Enable
+ *  0b0..Type of the selected pin under fault detect test is front plane.
+ *  0b1..Type of the selected pin under fault detect test is back plane.
+ */
+#define LCD_FDCR_FDBPEN(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDBPEN_SHIFT)) & LCD_FDCR_FDBPEN_MASK)
+
+#define LCD_FDCR_FDEN_MASK                       (0x80U)
+#define LCD_FDCR_FDEN_SHIFT                      (7U)
+/*! FDEN - Fault Detect Enable
+ *  0b0..Disable fault detection.
+ *  0b1..Enable fault detection.
+ */
+#define LCD_FDCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDEN_SHIFT)) & LCD_FDCR_FDEN_MASK)
+
+#define LCD_FDCR_FDSWW_MASK                      (0xE00U)
+#define LCD_FDCR_FDSWW_SHIFT                     (9U)
+/*! FDSWW - Fault Detect Sample Window Width
+ *  0b000..Sample window width is 4 sample clock cycles.
+ *  0b001..Sample window width is 8 sample clock cycles.
+ *  0b010..Sample window width is 16 sample clock cycles.
+ *  0b011..Sample window width is 32 sample clock cycles.
+ *  0b100..Sample window width is 64 sample clock cycles.
+ *  0b101..Sample window width is 128 sample clock cycles.
+ *  0b110..Sample window width is 256 sample clock cycles.
+ *  0b111..Sample window width is 512 sample clock cycles.
+ */
+#define LCD_FDCR_FDSWW(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDSWW_SHIFT)) & LCD_FDCR_FDSWW_MASK)
+
+#define LCD_FDCR_FDPRS_MASK                      (0x7000U)
+#define LCD_FDCR_FDPRS_SHIFT                     (12U)
+/*! FDPRS - Fault Detect Clock Prescaler
+ *  0b000..1/1 bus clock.
+ *  0b001..1/2 bus clock.
+ *  0b010..1/4 bus clock.
+ *  0b011..1/8 bus clock.
+ *  0b100..1/16 bus clock.
+ *  0b101..1/32 bus clock.
+ *  0b110..1/64 bus clock.
+ *  0b111..1/128 bus clock.
+ */
+#define LCD_FDCR_FDPRS(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPRS_SHIFT)) & LCD_FDCR_FDPRS_MASK)
+/*! @} */
+
+/*! @name FDSR - LCD Fault Detect Status Register */
+/*! @{ */
+
+#define LCD_FDSR_FDCNT_MASK                      (0xFFU)
+#define LCD_FDSR_FDCNT_SHIFT                     (0U)
+/*! FDCNT - Fault Detect Counter
+ *  0b00000000..No "one" samples.
+ *  0b00000001..1 "one" samples.
+ *  0b00000010..2 "one" samples.
+ *  0b11111110..254 "one" samples.
+ *  0b11111111..255 or more "one" samples. The FDCNT can overflow. Therefore, FDSWW and FDPRS must be reconfigured for proper sampling.
+ */
+#define LCD_FDSR_FDCNT(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCNT_SHIFT)) & LCD_FDSR_FDCNT_MASK)
+
+#define LCD_FDSR_FDCF_MASK                       (0x8000U)
+#define LCD_FDSR_FDCF_SHIFT                      (15U)
+/*! FDCF - Fault Detection Complete Flag
+ *  0b0..Fault detection is not completed.
+ *  0b1..Fault detection is completed.
+ */
+#define LCD_FDSR_FDCF(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCF_SHIFT)) & LCD_FDSR_FDCF_MASK)
+/*! @} */
+
+/*! @name PEN - LCD Pin Enable register */
+/*! @{ */
+
+#define LCD_PEN_PEN_MASK                         (0xFFFFFFFFU)
+#define LCD_PEN_PEN_SHIFT                        (0U)
+/*! PEN - LCD Pin Enable
+ *  0b00000000000000000000000000000000..LCD operation disabled on LCD_Pn.
+ *  0b00000000000000000000000000000001..LCD operation enabled on LCD_Pn.
+ */
+#define LCD_PEN_PEN(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PEN_SHIFT)) & LCD_PEN_PEN_MASK)
+/*! @} */
+
+/* The count of LCD_PEN */
+#define LCD_PEN_COUNT                            (2U)
+
+/*! @name BPEN - LCD Back Plane Enable register */
+/*! @{ */
+
+#define LCD_BPEN_BPEN_MASK                       (0xFFFFFFFFU)
+#define LCD_BPEN_BPEN_SHIFT                      (0U)
+/*! BPEN - Back Plane Enable
+ *  0b00000000000000000000000000000000..Front plane operation enabled on LCD_Pn.
+ *  0b00000000000000000000000000000001..Back plane operation enabled on LCD_Pn.
+ */
+#define LCD_BPEN_BPEN(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_BPEN_SHIFT)) & LCD_BPEN_BPEN_MASK)
+/*! @} */
+
+/* The count of LCD_BPEN */
+#define LCD_BPEN_COUNT                           (2U)
+
+/*! @name WF8B - LCD Waveform Register 0...LCD Waveform Register 63. */
+/*! @{ */
+
+#define LCD_WF8B_BPALCD0_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD0_SHIFT                   (0U)
+/*! BPALCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD0_SHIFT)) & LCD_WF8B_BPALCD0_MASK)
+
+#define LCD_WF8B_BPALCD1_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD1_SHIFT                   (0U)
+/*! BPALCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD1_SHIFT)) & LCD_WF8B_BPALCD1_MASK)
+
+#define LCD_WF8B_BPALCD2_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD2_SHIFT                   (0U)
+/*! BPALCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD2_SHIFT)) & LCD_WF8B_BPALCD2_MASK)
+
+#define LCD_WF8B_BPALCD3_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD3_SHIFT                   (0U)
+/*! BPALCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD3_SHIFT)) & LCD_WF8B_BPALCD3_MASK)
+
+#define LCD_WF8B_BPALCD4_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD4_SHIFT                   (0U)
+/*! BPALCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD4_SHIFT)) & LCD_WF8B_BPALCD4_MASK)
+
+#define LCD_WF8B_BPALCD5_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD5_SHIFT                   (0U)
+/*! BPALCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD5_SHIFT)) & LCD_WF8B_BPALCD5_MASK)
+
+#define LCD_WF8B_BPALCD6_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD6_SHIFT                   (0U)
+/*! BPALCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD6_SHIFT)) & LCD_WF8B_BPALCD6_MASK)
+
+#define LCD_WF8B_BPALCD7_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD7_SHIFT                   (0U)
+/*! BPALCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD7_SHIFT)) & LCD_WF8B_BPALCD7_MASK)
+
+#define LCD_WF8B_BPALCD8_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD8_SHIFT                   (0U)
+/*! BPALCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD8_SHIFT)) & LCD_WF8B_BPALCD8_MASK)
+
+#define LCD_WF8B_BPALCD9_MASK                    (0x1U)
+#define LCD_WF8B_BPALCD9_SHIFT                   (0U)
+/*! BPALCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD9_SHIFT)) & LCD_WF8B_BPALCD9_MASK)
+
+#define LCD_WF8B_BPALCD10_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD10_SHIFT                  (0U)
+/*! BPALCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD10_SHIFT)) & LCD_WF8B_BPALCD10_MASK)
+
+#define LCD_WF8B_BPALCD11_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD11_SHIFT                  (0U)
+/*! BPALCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD11_SHIFT)) & LCD_WF8B_BPALCD11_MASK)
+
+#define LCD_WF8B_BPALCD12_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD12_SHIFT                  (0U)
+/*! BPALCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD12_SHIFT)) & LCD_WF8B_BPALCD12_MASK)
+
+#define LCD_WF8B_BPALCD13_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD13_SHIFT                  (0U)
+/*! BPALCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD13_SHIFT)) & LCD_WF8B_BPALCD13_MASK)
+
+#define LCD_WF8B_BPALCD14_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD14_SHIFT                  (0U)
+/*! BPALCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD14_SHIFT)) & LCD_WF8B_BPALCD14_MASK)
+
+#define LCD_WF8B_BPALCD15_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD15_SHIFT                  (0U)
+/*! BPALCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD15_SHIFT)) & LCD_WF8B_BPALCD15_MASK)
+
+#define LCD_WF8B_BPALCD16_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD16_SHIFT                  (0U)
+/*! BPALCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD16_SHIFT)) & LCD_WF8B_BPALCD16_MASK)
+
+#define LCD_WF8B_BPALCD17_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD17_SHIFT                  (0U)
+/*! BPALCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD17_SHIFT)) & LCD_WF8B_BPALCD17_MASK)
+
+#define LCD_WF8B_BPALCD18_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD18_SHIFT                  (0U)
+/*! BPALCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD18_SHIFT)) & LCD_WF8B_BPALCD18_MASK)
+
+#define LCD_WF8B_BPALCD19_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD19_SHIFT                  (0U)
+/*! BPALCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD19_SHIFT)) & LCD_WF8B_BPALCD19_MASK)
+
+#define LCD_WF8B_BPALCD20_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD20_SHIFT                  (0U)
+/*! BPALCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD20_SHIFT)) & LCD_WF8B_BPALCD20_MASK)
+
+#define LCD_WF8B_BPALCD21_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD21_SHIFT                  (0U)
+/*! BPALCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD21_SHIFT)) & LCD_WF8B_BPALCD21_MASK)
+
+#define LCD_WF8B_BPALCD22_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD22_SHIFT                  (0U)
+/*! BPALCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD22_SHIFT)) & LCD_WF8B_BPALCD22_MASK)
+
+#define LCD_WF8B_BPALCD23_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD23_SHIFT                  (0U)
+/*! BPALCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD23_SHIFT)) & LCD_WF8B_BPALCD23_MASK)
+
+#define LCD_WF8B_BPALCD24_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD24_SHIFT                  (0U)
+/*! BPALCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD24_SHIFT)) & LCD_WF8B_BPALCD24_MASK)
+
+#define LCD_WF8B_BPALCD25_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD25_SHIFT                  (0U)
+/*! BPALCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD25_SHIFT)) & LCD_WF8B_BPALCD25_MASK)
+
+#define LCD_WF8B_BPALCD26_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD26_SHIFT                  (0U)
+/*! BPALCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD26_SHIFT)) & LCD_WF8B_BPALCD26_MASK)
+
+#define LCD_WF8B_BPALCD27_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD27_SHIFT                  (0U)
+/*! BPALCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD27_SHIFT)) & LCD_WF8B_BPALCD27_MASK)
+
+#define LCD_WF8B_BPALCD28_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD28_SHIFT                  (0U)
+/*! BPALCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD28_SHIFT)) & LCD_WF8B_BPALCD28_MASK)
+
+#define LCD_WF8B_BPALCD29_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD29_SHIFT                  (0U)
+/*! BPALCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD29_SHIFT)) & LCD_WF8B_BPALCD29_MASK)
+
+#define LCD_WF8B_BPALCD30_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD30_SHIFT                  (0U)
+/*! BPALCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD30_SHIFT)) & LCD_WF8B_BPALCD30_MASK)
+
+#define LCD_WF8B_BPALCD31_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD31_SHIFT                  (0U)
+/*! BPALCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD31_SHIFT)) & LCD_WF8B_BPALCD31_MASK)
+
+#define LCD_WF8B_BPALCD32_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD32_SHIFT                  (0U)
+/*! BPALCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD32_SHIFT)) & LCD_WF8B_BPALCD32_MASK)
+
+#define LCD_WF8B_BPALCD33_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD33_SHIFT                  (0U)
+/*! BPALCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD33_SHIFT)) & LCD_WF8B_BPALCD33_MASK)
+
+#define LCD_WF8B_BPALCD34_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD34_SHIFT                  (0U)
+/*! BPALCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD34_SHIFT)) & LCD_WF8B_BPALCD34_MASK)
+
+#define LCD_WF8B_BPALCD35_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD35_SHIFT                  (0U)
+/*! BPALCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD35_SHIFT)) & LCD_WF8B_BPALCD35_MASK)
+
+#define LCD_WF8B_BPALCD36_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD36_SHIFT                  (0U)
+/*! BPALCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD36_SHIFT)) & LCD_WF8B_BPALCD36_MASK)
+
+#define LCD_WF8B_BPALCD37_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD37_SHIFT                  (0U)
+/*! BPALCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD37_SHIFT)) & LCD_WF8B_BPALCD37_MASK)
+
+#define LCD_WF8B_BPALCD38_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD38_SHIFT                  (0U)
+/*! BPALCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD38_SHIFT)) & LCD_WF8B_BPALCD38_MASK)
+
+#define LCD_WF8B_BPALCD39_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD39_SHIFT                  (0U)
+/*! BPALCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD39_SHIFT)) & LCD_WF8B_BPALCD39_MASK)
+
+#define LCD_WF8B_BPALCD40_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD40_SHIFT                  (0U)
+/*! BPALCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD40_SHIFT)) & LCD_WF8B_BPALCD40_MASK)
+
+#define LCD_WF8B_BPALCD41_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD41_SHIFT                  (0U)
+/*! BPALCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD41_SHIFT)) & LCD_WF8B_BPALCD41_MASK)
+
+#define LCD_WF8B_BPALCD42_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD42_SHIFT                  (0U)
+/*! BPALCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD42_SHIFT)) & LCD_WF8B_BPALCD42_MASK)
+
+#define LCD_WF8B_BPALCD43_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD43_SHIFT                  (0U)
+/*! BPALCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD43_SHIFT)) & LCD_WF8B_BPALCD43_MASK)
+
+#define LCD_WF8B_BPALCD44_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD44_SHIFT                  (0U)
+/*! BPALCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD44_SHIFT)) & LCD_WF8B_BPALCD44_MASK)
+
+#define LCD_WF8B_BPALCD45_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD45_SHIFT                  (0U)
+/*! BPALCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD45_SHIFT)) & LCD_WF8B_BPALCD45_MASK)
+
+#define LCD_WF8B_BPALCD46_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD46_SHIFT                  (0U)
+/*! BPALCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD46_SHIFT)) & LCD_WF8B_BPALCD46_MASK)
+
+#define LCD_WF8B_BPALCD47_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD47_SHIFT                  (0U)
+/*! BPALCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD47_SHIFT)) & LCD_WF8B_BPALCD47_MASK)
+
+#define LCD_WF8B_BPALCD48_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD48_SHIFT                  (0U)
+/*! BPALCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD48_SHIFT)) & LCD_WF8B_BPALCD48_MASK)
+
+#define LCD_WF8B_BPALCD49_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD49_SHIFT                  (0U)
+/*! BPALCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD49_SHIFT)) & LCD_WF8B_BPALCD49_MASK)
+
+#define LCD_WF8B_BPALCD50_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD50_SHIFT                  (0U)
+/*! BPALCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD50_SHIFT)) & LCD_WF8B_BPALCD50_MASK)
+
+#define LCD_WF8B_BPALCD51_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD51_SHIFT                  (0U)
+/*! BPALCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD51_SHIFT)) & LCD_WF8B_BPALCD51_MASK)
+
+#define LCD_WF8B_BPALCD52_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD52_SHIFT                  (0U)
+/*! BPALCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD52_SHIFT)) & LCD_WF8B_BPALCD52_MASK)
+
+#define LCD_WF8B_BPALCD53_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD53_SHIFT                  (0U)
+/*! BPALCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD53_SHIFT)) & LCD_WF8B_BPALCD53_MASK)
+
+#define LCD_WF8B_BPALCD54_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD54_SHIFT                  (0U)
+/*! BPALCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD54_SHIFT)) & LCD_WF8B_BPALCD54_MASK)
+
+#define LCD_WF8B_BPALCD55_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD55_SHIFT                  (0U)
+/*! BPALCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD55_SHIFT)) & LCD_WF8B_BPALCD55_MASK)
+
+#define LCD_WF8B_BPALCD56_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD56_SHIFT                  (0U)
+/*! BPALCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD56_SHIFT)) & LCD_WF8B_BPALCD56_MASK)
+
+#define LCD_WF8B_BPALCD57_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD57_SHIFT                  (0U)
+/*! BPALCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD57_SHIFT)) & LCD_WF8B_BPALCD57_MASK)
+
+#define LCD_WF8B_BPALCD58_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD58_SHIFT                  (0U)
+/*! BPALCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD58_SHIFT)) & LCD_WF8B_BPALCD58_MASK)
+
+#define LCD_WF8B_BPALCD59_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD59_SHIFT                  (0U)
+/*! BPALCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD59_SHIFT)) & LCD_WF8B_BPALCD59_MASK)
+
+#define LCD_WF8B_BPALCD60_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD60_SHIFT                  (0U)
+/*! BPALCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD60_SHIFT)) & LCD_WF8B_BPALCD60_MASK)
+
+#define LCD_WF8B_BPALCD61_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD61_SHIFT                  (0U)
+/*! BPALCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD61_SHIFT)) & LCD_WF8B_BPALCD61_MASK)
+
+#define LCD_WF8B_BPALCD62_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD62_SHIFT                  (0U)
+/*! BPALCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD62_SHIFT)) & LCD_WF8B_BPALCD62_MASK)
+
+#define LCD_WF8B_BPALCD63_MASK                   (0x1U)
+#define LCD_WF8B_BPALCD63_SHIFT                  (0U)
+/*! BPALCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase A
+ *  0b1..LCD segment on or LCD backplane active for phase A
+ */
+#define LCD_WF8B_BPALCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD63_SHIFT)) & LCD_WF8B_BPALCD63_MASK)
+
+#define LCD_WF8B_BPBLCD0_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD0_SHIFT                   (1U)
+/*! BPBLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD0_SHIFT)) & LCD_WF8B_BPBLCD0_MASK)
+
+#define LCD_WF8B_BPBLCD1_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD1_SHIFT                   (1U)
+/*! BPBLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD1_SHIFT)) & LCD_WF8B_BPBLCD1_MASK)
+
+#define LCD_WF8B_BPBLCD2_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD2_SHIFT                   (1U)
+/*! BPBLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD2_SHIFT)) & LCD_WF8B_BPBLCD2_MASK)
+
+#define LCD_WF8B_BPBLCD3_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD3_SHIFT                   (1U)
+/*! BPBLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD3_SHIFT)) & LCD_WF8B_BPBLCD3_MASK)
+
+#define LCD_WF8B_BPBLCD4_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD4_SHIFT                   (1U)
+/*! BPBLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD4_SHIFT)) & LCD_WF8B_BPBLCD4_MASK)
+
+#define LCD_WF8B_BPBLCD5_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD5_SHIFT                   (1U)
+/*! BPBLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD5_SHIFT)) & LCD_WF8B_BPBLCD5_MASK)
+
+#define LCD_WF8B_BPBLCD6_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD6_SHIFT                   (1U)
+/*! BPBLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD6_SHIFT)) & LCD_WF8B_BPBLCD6_MASK)
+
+#define LCD_WF8B_BPBLCD7_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD7_SHIFT                   (1U)
+/*! BPBLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD7_SHIFT)) & LCD_WF8B_BPBLCD7_MASK)
+
+#define LCD_WF8B_BPBLCD8_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD8_SHIFT                   (1U)
+/*! BPBLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD8_SHIFT)) & LCD_WF8B_BPBLCD8_MASK)
+
+#define LCD_WF8B_BPBLCD9_MASK                    (0x2U)
+#define LCD_WF8B_BPBLCD9_SHIFT                   (1U)
+/*! BPBLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD9_SHIFT)) & LCD_WF8B_BPBLCD9_MASK)
+
+#define LCD_WF8B_BPBLCD10_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD10_SHIFT                  (1U)
+/*! BPBLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD10_SHIFT)) & LCD_WF8B_BPBLCD10_MASK)
+
+#define LCD_WF8B_BPBLCD11_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD11_SHIFT                  (1U)
+/*! BPBLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD11_SHIFT)) & LCD_WF8B_BPBLCD11_MASK)
+
+#define LCD_WF8B_BPBLCD12_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD12_SHIFT                  (1U)
+/*! BPBLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD12_SHIFT)) & LCD_WF8B_BPBLCD12_MASK)
+
+#define LCD_WF8B_BPBLCD13_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD13_SHIFT                  (1U)
+/*! BPBLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD13_SHIFT)) & LCD_WF8B_BPBLCD13_MASK)
+
+#define LCD_WF8B_BPBLCD14_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD14_SHIFT                  (1U)
+/*! BPBLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD14_SHIFT)) & LCD_WF8B_BPBLCD14_MASK)
+
+#define LCD_WF8B_BPBLCD15_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD15_SHIFT                  (1U)
+/*! BPBLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD15_SHIFT)) & LCD_WF8B_BPBLCD15_MASK)
+
+#define LCD_WF8B_BPBLCD16_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD16_SHIFT                  (1U)
+/*! BPBLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD16_SHIFT)) & LCD_WF8B_BPBLCD16_MASK)
+
+#define LCD_WF8B_BPBLCD17_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD17_SHIFT                  (1U)
+/*! BPBLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD17_SHIFT)) & LCD_WF8B_BPBLCD17_MASK)
+
+#define LCD_WF8B_BPBLCD18_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD18_SHIFT                  (1U)
+/*! BPBLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD18_SHIFT)) & LCD_WF8B_BPBLCD18_MASK)
+
+#define LCD_WF8B_BPBLCD19_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD19_SHIFT                  (1U)
+/*! BPBLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD19_SHIFT)) & LCD_WF8B_BPBLCD19_MASK)
+
+#define LCD_WF8B_BPBLCD20_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD20_SHIFT                  (1U)
+/*! BPBLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD20_SHIFT)) & LCD_WF8B_BPBLCD20_MASK)
+
+#define LCD_WF8B_BPBLCD21_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD21_SHIFT                  (1U)
+/*! BPBLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD21_SHIFT)) & LCD_WF8B_BPBLCD21_MASK)
+
+#define LCD_WF8B_BPBLCD22_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD22_SHIFT                  (1U)
+/*! BPBLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD22_SHIFT)) & LCD_WF8B_BPBLCD22_MASK)
+
+#define LCD_WF8B_BPBLCD23_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD23_SHIFT                  (1U)
+/*! BPBLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD23_SHIFT)) & LCD_WF8B_BPBLCD23_MASK)
+
+#define LCD_WF8B_BPBLCD24_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD24_SHIFT                  (1U)
+/*! BPBLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD24_SHIFT)) & LCD_WF8B_BPBLCD24_MASK)
+
+#define LCD_WF8B_BPBLCD25_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD25_SHIFT                  (1U)
+/*! BPBLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD25_SHIFT)) & LCD_WF8B_BPBLCD25_MASK)
+
+#define LCD_WF8B_BPBLCD26_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD26_SHIFT                  (1U)
+/*! BPBLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD26_SHIFT)) & LCD_WF8B_BPBLCD26_MASK)
+
+#define LCD_WF8B_BPBLCD27_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD27_SHIFT                  (1U)
+/*! BPBLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD27_SHIFT)) & LCD_WF8B_BPBLCD27_MASK)
+
+#define LCD_WF8B_BPBLCD28_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD28_SHIFT                  (1U)
+/*! BPBLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD28_SHIFT)) & LCD_WF8B_BPBLCD28_MASK)
+
+#define LCD_WF8B_BPBLCD29_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD29_SHIFT                  (1U)
+/*! BPBLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD29_SHIFT)) & LCD_WF8B_BPBLCD29_MASK)
+
+#define LCD_WF8B_BPBLCD30_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD30_SHIFT                  (1U)
+/*! BPBLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD30_SHIFT)) & LCD_WF8B_BPBLCD30_MASK)
+
+#define LCD_WF8B_BPBLCD31_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD31_SHIFT                  (1U)
+/*! BPBLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD31_SHIFT)) & LCD_WF8B_BPBLCD31_MASK)
+
+#define LCD_WF8B_BPBLCD32_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD32_SHIFT                  (1U)
+/*! BPBLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD32_SHIFT)) & LCD_WF8B_BPBLCD32_MASK)
+
+#define LCD_WF8B_BPBLCD33_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD33_SHIFT                  (1U)
+/*! BPBLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD33_SHIFT)) & LCD_WF8B_BPBLCD33_MASK)
+
+#define LCD_WF8B_BPBLCD34_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD34_SHIFT                  (1U)
+/*! BPBLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD34_SHIFT)) & LCD_WF8B_BPBLCD34_MASK)
+
+#define LCD_WF8B_BPBLCD35_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD35_SHIFT                  (1U)
+/*! BPBLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD35_SHIFT)) & LCD_WF8B_BPBLCD35_MASK)
+
+#define LCD_WF8B_BPBLCD36_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD36_SHIFT                  (1U)
+/*! BPBLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD36_SHIFT)) & LCD_WF8B_BPBLCD36_MASK)
+
+#define LCD_WF8B_BPBLCD37_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD37_SHIFT                  (1U)
+/*! BPBLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD37_SHIFT)) & LCD_WF8B_BPBLCD37_MASK)
+
+#define LCD_WF8B_BPBLCD38_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD38_SHIFT                  (1U)
+/*! BPBLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD38_SHIFT)) & LCD_WF8B_BPBLCD38_MASK)
+
+#define LCD_WF8B_BPBLCD39_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD39_SHIFT                  (1U)
+/*! BPBLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD39_SHIFT)) & LCD_WF8B_BPBLCD39_MASK)
+
+#define LCD_WF8B_BPBLCD40_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD40_SHIFT                  (1U)
+/*! BPBLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD40_SHIFT)) & LCD_WF8B_BPBLCD40_MASK)
+
+#define LCD_WF8B_BPBLCD41_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD41_SHIFT                  (1U)
+/*! BPBLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD41_SHIFT)) & LCD_WF8B_BPBLCD41_MASK)
+
+#define LCD_WF8B_BPBLCD42_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD42_SHIFT                  (1U)
+/*! BPBLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD42_SHIFT)) & LCD_WF8B_BPBLCD42_MASK)
+
+#define LCD_WF8B_BPBLCD43_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD43_SHIFT                  (1U)
+/*! BPBLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD43_SHIFT)) & LCD_WF8B_BPBLCD43_MASK)
+
+#define LCD_WF8B_BPBLCD44_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD44_SHIFT                  (1U)
+/*! BPBLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD44_SHIFT)) & LCD_WF8B_BPBLCD44_MASK)
+
+#define LCD_WF8B_BPBLCD45_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD45_SHIFT                  (1U)
+/*! BPBLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD45_SHIFT)) & LCD_WF8B_BPBLCD45_MASK)
+
+#define LCD_WF8B_BPBLCD46_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD46_SHIFT                  (1U)
+/*! BPBLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD46_SHIFT)) & LCD_WF8B_BPBLCD46_MASK)
+
+#define LCD_WF8B_BPBLCD47_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD47_SHIFT                  (1U)
+/*! BPBLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD47_SHIFT)) & LCD_WF8B_BPBLCD47_MASK)
+
+#define LCD_WF8B_BPBLCD48_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD48_SHIFT                  (1U)
+/*! BPBLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD48_SHIFT)) & LCD_WF8B_BPBLCD48_MASK)
+
+#define LCD_WF8B_BPBLCD49_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD49_SHIFT                  (1U)
+/*! BPBLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD49_SHIFT)) & LCD_WF8B_BPBLCD49_MASK)
+
+#define LCD_WF8B_BPBLCD50_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD50_SHIFT                  (1U)
+/*! BPBLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD50_SHIFT)) & LCD_WF8B_BPBLCD50_MASK)
+
+#define LCD_WF8B_BPBLCD51_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD51_SHIFT                  (1U)
+/*! BPBLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD51_SHIFT)) & LCD_WF8B_BPBLCD51_MASK)
+
+#define LCD_WF8B_BPBLCD52_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD52_SHIFT                  (1U)
+/*! BPBLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD52_SHIFT)) & LCD_WF8B_BPBLCD52_MASK)
+
+#define LCD_WF8B_BPBLCD53_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD53_SHIFT                  (1U)
+/*! BPBLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD53_SHIFT)) & LCD_WF8B_BPBLCD53_MASK)
+
+#define LCD_WF8B_BPBLCD54_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD54_SHIFT                  (1U)
+/*! BPBLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD54_SHIFT)) & LCD_WF8B_BPBLCD54_MASK)
+
+#define LCD_WF8B_BPBLCD55_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD55_SHIFT                  (1U)
+/*! BPBLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD55_SHIFT)) & LCD_WF8B_BPBLCD55_MASK)
+
+#define LCD_WF8B_BPBLCD56_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD56_SHIFT                  (1U)
+/*! BPBLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD56_SHIFT)) & LCD_WF8B_BPBLCD56_MASK)
+
+#define LCD_WF8B_BPBLCD57_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD57_SHIFT                  (1U)
+/*! BPBLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD57_SHIFT)) & LCD_WF8B_BPBLCD57_MASK)
+
+#define LCD_WF8B_BPBLCD58_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD58_SHIFT                  (1U)
+/*! BPBLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD58_SHIFT)) & LCD_WF8B_BPBLCD58_MASK)
+
+#define LCD_WF8B_BPBLCD59_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD59_SHIFT                  (1U)
+/*! BPBLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD59_SHIFT)) & LCD_WF8B_BPBLCD59_MASK)
+
+#define LCD_WF8B_BPBLCD60_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD60_SHIFT                  (1U)
+/*! BPBLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD60_SHIFT)) & LCD_WF8B_BPBLCD60_MASK)
+
+#define LCD_WF8B_BPBLCD61_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD61_SHIFT                  (1U)
+/*! BPBLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD61_SHIFT)) & LCD_WF8B_BPBLCD61_MASK)
+
+#define LCD_WF8B_BPBLCD62_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD62_SHIFT                  (1U)
+/*! BPBLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD62_SHIFT)) & LCD_WF8B_BPBLCD62_MASK)
+
+#define LCD_WF8B_BPBLCD63_MASK                   (0x2U)
+#define LCD_WF8B_BPBLCD63_SHIFT                  (1U)
+/*! BPBLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase B
+ *  0b1..LCD segment on or LCD backplane active for phase B
+ */
+#define LCD_WF8B_BPBLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD63_SHIFT)) & LCD_WF8B_BPBLCD63_MASK)
+
+#define LCD_WF8B_BPCLCD0_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD0_SHIFT                   (2U)
+/*! BPCLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD0_SHIFT)) & LCD_WF8B_BPCLCD0_MASK)
+
+#define LCD_WF8B_BPCLCD1_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD1_SHIFT                   (2U)
+/*! BPCLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD1_SHIFT)) & LCD_WF8B_BPCLCD1_MASK)
+
+#define LCD_WF8B_BPCLCD2_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD2_SHIFT                   (2U)
+/*! BPCLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD2_SHIFT)) & LCD_WF8B_BPCLCD2_MASK)
+
+#define LCD_WF8B_BPCLCD3_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD3_SHIFT                   (2U)
+/*! BPCLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD3_SHIFT)) & LCD_WF8B_BPCLCD3_MASK)
+
+#define LCD_WF8B_BPCLCD4_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD4_SHIFT                   (2U)
+/*! BPCLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD4_SHIFT)) & LCD_WF8B_BPCLCD4_MASK)
+
+#define LCD_WF8B_BPCLCD5_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD5_SHIFT                   (2U)
+/*! BPCLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD5_SHIFT)) & LCD_WF8B_BPCLCD5_MASK)
+
+#define LCD_WF8B_BPCLCD6_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD6_SHIFT                   (2U)
+/*! BPCLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD6_SHIFT)) & LCD_WF8B_BPCLCD6_MASK)
+
+#define LCD_WF8B_BPCLCD7_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD7_SHIFT                   (2U)
+/*! BPCLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD7_SHIFT)) & LCD_WF8B_BPCLCD7_MASK)
+
+#define LCD_WF8B_BPCLCD8_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD8_SHIFT                   (2U)
+/*! BPCLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD8_SHIFT)) & LCD_WF8B_BPCLCD8_MASK)
+
+#define LCD_WF8B_BPCLCD9_MASK                    (0x4U)
+#define LCD_WF8B_BPCLCD9_SHIFT                   (2U)
+/*! BPCLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD9_SHIFT)) & LCD_WF8B_BPCLCD9_MASK)
+
+#define LCD_WF8B_BPCLCD10_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD10_SHIFT                  (2U)
+/*! BPCLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD10_SHIFT)) & LCD_WF8B_BPCLCD10_MASK)
+
+#define LCD_WF8B_BPCLCD11_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD11_SHIFT                  (2U)
+/*! BPCLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD11_SHIFT)) & LCD_WF8B_BPCLCD11_MASK)
+
+#define LCD_WF8B_BPCLCD12_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD12_SHIFT                  (2U)
+/*! BPCLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD12_SHIFT)) & LCD_WF8B_BPCLCD12_MASK)
+
+#define LCD_WF8B_BPCLCD13_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD13_SHIFT                  (2U)
+/*! BPCLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD13_SHIFT)) & LCD_WF8B_BPCLCD13_MASK)
+
+#define LCD_WF8B_BPCLCD14_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD14_SHIFT                  (2U)
+/*! BPCLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD14_SHIFT)) & LCD_WF8B_BPCLCD14_MASK)
+
+#define LCD_WF8B_BPCLCD15_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD15_SHIFT                  (2U)
+/*! BPCLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD15_SHIFT)) & LCD_WF8B_BPCLCD15_MASK)
+
+#define LCD_WF8B_BPCLCD16_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD16_SHIFT                  (2U)
+/*! BPCLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD16_SHIFT)) & LCD_WF8B_BPCLCD16_MASK)
+
+#define LCD_WF8B_BPCLCD17_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD17_SHIFT                  (2U)
+/*! BPCLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD17_SHIFT)) & LCD_WF8B_BPCLCD17_MASK)
+
+#define LCD_WF8B_BPCLCD18_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD18_SHIFT                  (2U)
+/*! BPCLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD18_SHIFT)) & LCD_WF8B_BPCLCD18_MASK)
+
+#define LCD_WF8B_BPCLCD19_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD19_SHIFT                  (2U)
+/*! BPCLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD19_SHIFT)) & LCD_WF8B_BPCLCD19_MASK)
+
+#define LCD_WF8B_BPCLCD20_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD20_SHIFT                  (2U)
+/*! BPCLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD20_SHIFT)) & LCD_WF8B_BPCLCD20_MASK)
+
+#define LCD_WF8B_BPCLCD21_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD21_SHIFT                  (2U)
+/*! BPCLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD21_SHIFT)) & LCD_WF8B_BPCLCD21_MASK)
+
+#define LCD_WF8B_BPCLCD22_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD22_SHIFT                  (2U)
+/*! BPCLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD22_SHIFT)) & LCD_WF8B_BPCLCD22_MASK)
+
+#define LCD_WF8B_BPCLCD23_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD23_SHIFT                  (2U)
+/*! BPCLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD23_SHIFT)) & LCD_WF8B_BPCLCD23_MASK)
+
+#define LCD_WF8B_BPCLCD24_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD24_SHIFT                  (2U)
+/*! BPCLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD24_SHIFT)) & LCD_WF8B_BPCLCD24_MASK)
+
+#define LCD_WF8B_BPCLCD25_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD25_SHIFT                  (2U)
+/*! BPCLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD25_SHIFT)) & LCD_WF8B_BPCLCD25_MASK)
+
+#define LCD_WF8B_BPCLCD26_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD26_SHIFT                  (2U)
+/*! BPCLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD26_SHIFT)) & LCD_WF8B_BPCLCD26_MASK)
+
+#define LCD_WF8B_BPCLCD27_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD27_SHIFT                  (2U)
+/*! BPCLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD27_SHIFT)) & LCD_WF8B_BPCLCD27_MASK)
+
+#define LCD_WF8B_BPCLCD28_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD28_SHIFT                  (2U)
+/*! BPCLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD28_SHIFT)) & LCD_WF8B_BPCLCD28_MASK)
+
+#define LCD_WF8B_BPCLCD29_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD29_SHIFT                  (2U)
+/*! BPCLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD29_SHIFT)) & LCD_WF8B_BPCLCD29_MASK)
+
+#define LCD_WF8B_BPCLCD30_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD30_SHIFT                  (2U)
+/*! BPCLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD30_SHIFT)) & LCD_WF8B_BPCLCD30_MASK)
+
+#define LCD_WF8B_BPCLCD31_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD31_SHIFT                  (2U)
+/*! BPCLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD31_SHIFT)) & LCD_WF8B_BPCLCD31_MASK)
+
+#define LCD_WF8B_BPCLCD32_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD32_SHIFT                  (2U)
+/*! BPCLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD32_SHIFT)) & LCD_WF8B_BPCLCD32_MASK)
+
+#define LCD_WF8B_BPCLCD33_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD33_SHIFT                  (2U)
+/*! BPCLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD33_SHIFT)) & LCD_WF8B_BPCLCD33_MASK)
+
+#define LCD_WF8B_BPCLCD34_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD34_SHIFT                  (2U)
+/*! BPCLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD34_SHIFT)) & LCD_WF8B_BPCLCD34_MASK)
+
+#define LCD_WF8B_BPCLCD35_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD35_SHIFT                  (2U)
+/*! BPCLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD35_SHIFT)) & LCD_WF8B_BPCLCD35_MASK)
+
+#define LCD_WF8B_BPCLCD36_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD36_SHIFT                  (2U)
+/*! BPCLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD36_SHIFT)) & LCD_WF8B_BPCLCD36_MASK)
+
+#define LCD_WF8B_BPCLCD37_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD37_SHIFT                  (2U)
+/*! BPCLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD37_SHIFT)) & LCD_WF8B_BPCLCD37_MASK)
+
+#define LCD_WF8B_BPCLCD38_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD38_SHIFT                  (2U)
+/*! BPCLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD38_SHIFT)) & LCD_WF8B_BPCLCD38_MASK)
+
+#define LCD_WF8B_BPCLCD39_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD39_SHIFT                  (2U)
+/*! BPCLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD39_SHIFT)) & LCD_WF8B_BPCLCD39_MASK)
+
+#define LCD_WF8B_BPCLCD40_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD40_SHIFT                  (2U)
+/*! BPCLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD40_SHIFT)) & LCD_WF8B_BPCLCD40_MASK)
+
+#define LCD_WF8B_BPCLCD41_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD41_SHIFT                  (2U)
+/*! BPCLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD41_SHIFT)) & LCD_WF8B_BPCLCD41_MASK)
+
+#define LCD_WF8B_BPCLCD42_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD42_SHIFT                  (2U)
+/*! BPCLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD42_SHIFT)) & LCD_WF8B_BPCLCD42_MASK)
+
+#define LCD_WF8B_BPCLCD43_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD43_SHIFT                  (2U)
+/*! BPCLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD43_SHIFT)) & LCD_WF8B_BPCLCD43_MASK)
+
+#define LCD_WF8B_BPCLCD44_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD44_SHIFT                  (2U)
+/*! BPCLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD44_SHIFT)) & LCD_WF8B_BPCLCD44_MASK)
+
+#define LCD_WF8B_BPCLCD45_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD45_SHIFT                  (2U)
+/*! BPCLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD45_SHIFT)) & LCD_WF8B_BPCLCD45_MASK)
+
+#define LCD_WF8B_BPCLCD46_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD46_SHIFT                  (2U)
+/*! BPCLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD46_SHIFT)) & LCD_WF8B_BPCLCD46_MASK)
+
+#define LCD_WF8B_BPCLCD47_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD47_SHIFT                  (2U)
+/*! BPCLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD47_SHIFT)) & LCD_WF8B_BPCLCD47_MASK)
+
+#define LCD_WF8B_BPCLCD48_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD48_SHIFT                  (2U)
+/*! BPCLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD48_SHIFT)) & LCD_WF8B_BPCLCD48_MASK)
+
+#define LCD_WF8B_BPCLCD49_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD49_SHIFT                  (2U)
+/*! BPCLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD49_SHIFT)) & LCD_WF8B_BPCLCD49_MASK)
+
+#define LCD_WF8B_BPCLCD50_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD50_SHIFT                  (2U)
+/*! BPCLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD50_SHIFT)) & LCD_WF8B_BPCLCD50_MASK)
+
+#define LCD_WF8B_BPCLCD51_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD51_SHIFT                  (2U)
+/*! BPCLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD51_SHIFT)) & LCD_WF8B_BPCLCD51_MASK)
+
+#define LCD_WF8B_BPCLCD52_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD52_SHIFT                  (2U)
+/*! BPCLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD52_SHIFT)) & LCD_WF8B_BPCLCD52_MASK)
+
+#define LCD_WF8B_BPCLCD53_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD53_SHIFT                  (2U)
+/*! BPCLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD53_SHIFT)) & LCD_WF8B_BPCLCD53_MASK)
+
+#define LCD_WF8B_BPCLCD54_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD54_SHIFT                  (2U)
+/*! BPCLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD54_SHIFT)) & LCD_WF8B_BPCLCD54_MASK)
+
+#define LCD_WF8B_BPCLCD55_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD55_SHIFT                  (2U)
+/*! BPCLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD55_SHIFT)) & LCD_WF8B_BPCLCD55_MASK)
+
+#define LCD_WF8B_BPCLCD56_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD56_SHIFT                  (2U)
+/*! BPCLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD56_SHIFT)) & LCD_WF8B_BPCLCD56_MASK)
+
+#define LCD_WF8B_BPCLCD57_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD57_SHIFT                  (2U)
+/*! BPCLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD57_SHIFT)) & LCD_WF8B_BPCLCD57_MASK)
+
+#define LCD_WF8B_BPCLCD58_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD58_SHIFT                  (2U)
+/*! BPCLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD58_SHIFT)) & LCD_WF8B_BPCLCD58_MASK)
+
+#define LCD_WF8B_BPCLCD59_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD59_SHIFT                  (2U)
+/*! BPCLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD59_SHIFT)) & LCD_WF8B_BPCLCD59_MASK)
+
+#define LCD_WF8B_BPCLCD60_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD60_SHIFT                  (2U)
+/*! BPCLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD60_SHIFT)) & LCD_WF8B_BPCLCD60_MASK)
+
+#define LCD_WF8B_BPCLCD61_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD61_SHIFT                  (2U)
+/*! BPCLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD61_SHIFT)) & LCD_WF8B_BPCLCD61_MASK)
+
+#define LCD_WF8B_BPCLCD62_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD62_SHIFT                  (2U)
+/*! BPCLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD62_SHIFT)) & LCD_WF8B_BPCLCD62_MASK)
+
+#define LCD_WF8B_BPCLCD63_MASK                   (0x4U)
+#define LCD_WF8B_BPCLCD63_SHIFT                  (2U)
+/*! BPCLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase C
+ *  0b1..LCD segment on or LCD backplane active for phase C
+ */
+#define LCD_WF8B_BPCLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPCLCD63_SHIFT)) & LCD_WF8B_BPCLCD63_MASK)
+
+#define LCD_WF8B_BPDLCD0_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD0_SHIFT                   (3U)
+/*! BPDLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD0_SHIFT)) & LCD_WF8B_BPDLCD0_MASK)
+
+#define LCD_WF8B_BPDLCD1_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD1_SHIFT                   (3U)
+/*! BPDLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD1_SHIFT)) & LCD_WF8B_BPDLCD1_MASK)
+
+#define LCD_WF8B_BPDLCD2_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD2_SHIFT                   (3U)
+/*! BPDLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD2_SHIFT)) & LCD_WF8B_BPDLCD2_MASK)
+
+#define LCD_WF8B_BPDLCD3_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD3_SHIFT                   (3U)
+/*! BPDLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD3_SHIFT)) & LCD_WF8B_BPDLCD3_MASK)
+
+#define LCD_WF8B_BPDLCD4_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD4_SHIFT                   (3U)
+/*! BPDLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD4_SHIFT)) & LCD_WF8B_BPDLCD4_MASK)
+
+#define LCD_WF8B_BPDLCD5_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD5_SHIFT                   (3U)
+/*! BPDLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD5_SHIFT)) & LCD_WF8B_BPDLCD5_MASK)
+
+#define LCD_WF8B_BPDLCD6_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD6_SHIFT                   (3U)
+/*! BPDLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD6_SHIFT)) & LCD_WF8B_BPDLCD6_MASK)
+
+#define LCD_WF8B_BPDLCD7_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD7_SHIFT                   (3U)
+/*! BPDLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD7_SHIFT)) & LCD_WF8B_BPDLCD7_MASK)
+
+#define LCD_WF8B_BPDLCD8_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD8_SHIFT                   (3U)
+/*! BPDLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD8_SHIFT)) & LCD_WF8B_BPDLCD8_MASK)
+
+#define LCD_WF8B_BPDLCD9_MASK                    (0x8U)
+#define LCD_WF8B_BPDLCD9_SHIFT                   (3U)
+/*! BPDLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD9_SHIFT)) & LCD_WF8B_BPDLCD9_MASK)
+
+#define LCD_WF8B_BPDLCD10_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD10_SHIFT                  (3U)
+/*! BPDLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD10_SHIFT)) & LCD_WF8B_BPDLCD10_MASK)
+
+#define LCD_WF8B_BPDLCD11_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD11_SHIFT                  (3U)
+/*! BPDLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD11_SHIFT)) & LCD_WF8B_BPDLCD11_MASK)
+
+#define LCD_WF8B_BPDLCD12_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD12_SHIFT                  (3U)
+/*! BPDLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD12_SHIFT)) & LCD_WF8B_BPDLCD12_MASK)
+
+#define LCD_WF8B_BPDLCD13_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD13_SHIFT                  (3U)
+/*! BPDLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD13_SHIFT)) & LCD_WF8B_BPDLCD13_MASK)
+
+#define LCD_WF8B_BPDLCD14_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD14_SHIFT                  (3U)
+/*! BPDLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD14_SHIFT)) & LCD_WF8B_BPDLCD14_MASK)
+
+#define LCD_WF8B_BPDLCD15_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD15_SHIFT                  (3U)
+/*! BPDLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD15_SHIFT)) & LCD_WF8B_BPDLCD15_MASK)
+
+#define LCD_WF8B_BPDLCD16_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD16_SHIFT                  (3U)
+/*! BPDLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD16_SHIFT)) & LCD_WF8B_BPDLCD16_MASK)
+
+#define LCD_WF8B_BPDLCD17_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD17_SHIFT                  (3U)
+/*! BPDLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD17_SHIFT)) & LCD_WF8B_BPDLCD17_MASK)
+
+#define LCD_WF8B_BPDLCD18_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD18_SHIFT                  (3U)
+/*! BPDLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD18_SHIFT)) & LCD_WF8B_BPDLCD18_MASK)
+
+#define LCD_WF8B_BPDLCD19_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD19_SHIFT                  (3U)
+/*! BPDLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD19_SHIFT)) & LCD_WF8B_BPDLCD19_MASK)
+
+#define LCD_WF8B_BPDLCD20_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD20_SHIFT                  (3U)
+/*! BPDLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD20_SHIFT)) & LCD_WF8B_BPDLCD20_MASK)
+
+#define LCD_WF8B_BPDLCD21_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD21_SHIFT                  (3U)
+/*! BPDLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD21_SHIFT)) & LCD_WF8B_BPDLCD21_MASK)
+
+#define LCD_WF8B_BPDLCD22_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD22_SHIFT                  (3U)
+/*! BPDLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD22_SHIFT)) & LCD_WF8B_BPDLCD22_MASK)
+
+#define LCD_WF8B_BPDLCD23_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD23_SHIFT                  (3U)
+/*! BPDLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD23_SHIFT)) & LCD_WF8B_BPDLCD23_MASK)
+
+#define LCD_WF8B_BPDLCD24_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD24_SHIFT                  (3U)
+/*! BPDLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD24_SHIFT)) & LCD_WF8B_BPDLCD24_MASK)
+
+#define LCD_WF8B_BPDLCD25_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD25_SHIFT                  (3U)
+/*! BPDLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD25_SHIFT)) & LCD_WF8B_BPDLCD25_MASK)
+
+#define LCD_WF8B_BPDLCD26_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD26_SHIFT                  (3U)
+/*! BPDLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD26_SHIFT)) & LCD_WF8B_BPDLCD26_MASK)
+
+#define LCD_WF8B_BPDLCD27_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD27_SHIFT                  (3U)
+/*! BPDLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD27_SHIFT)) & LCD_WF8B_BPDLCD27_MASK)
+
+#define LCD_WF8B_BPDLCD28_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD28_SHIFT                  (3U)
+/*! BPDLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD28_SHIFT)) & LCD_WF8B_BPDLCD28_MASK)
+
+#define LCD_WF8B_BPDLCD29_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD29_SHIFT                  (3U)
+/*! BPDLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD29_SHIFT)) & LCD_WF8B_BPDLCD29_MASK)
+
+#define LCD_WF8B_BPDLCD30_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD30_SHIFT                  (3U)
+/*! BPDLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD30_SHIFT)) & LCD_WF8B_BPDLCD30_MASK)
+
+#define LCD_WF8B_BPDLCD31_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD31_SHIFT                  (3U)
+/*! BPDLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD31_SHIFT)) & LCD_WF8B_BPDLCD31_MASK)
+
+#define LCD_WF8B_BPDLCD32_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD32_SHIFT                  (3U)
+/*! BPDLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD32_SHIFT)) & LCD_WF8B_BPDLCD32_MASK)
+
+#define LCD_WF8B_BPDLCD33_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD33_SHIFT                  (3U)
+/*! BPDLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD33_SHIFT)) & LCD_WF8B_BPDLCD33_MASK)
+
+#define LCD_WF8B_BPDLCD34_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD34_SHIFT                  (3U)
+/*! BPDLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD34_SHIFT)) & LCD_WF8B_BPDLCD34_MASK)
+
+#define LCD_WF8B_BPDLCD35_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD35_SHIFT                  (3U)
+/*! BPDLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD35_SHIFT)) & LCD_WF8B_BPDLCD35_MASK)
+
+#define LCD_WF8B_BPDLCD36_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD36_SHIFT                  (3U)
+/*! BPDLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD36_SHIFT)) & LCD_WF8B_BPDLCD36_MASK)
+
+#define LCD_WF8B_BPDLCD37_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD37_SHIFT                  (3U)
+/*! BPDLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD37_SHIFT)) & LCD_WF8B_BPDLCD37_MASK)
+
+#define LCD_WF8B_BPDLCD38_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD38_SHIFT                  (3U)
+/*! BPDLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD38_SHIFT)) & LCD_WF8B_BPDLCD38_MASK)
+
+#define LCD_WF8B_BPDLCD39_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD39_SHIFT                  (3U)
+/*! BPDLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD39_SHIFT)) & LCD_WF8B_BPDLCD39_MASK)
+
+#define LCD_WF8B_BPDLCD40_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD40_SHIFT                  (3U)
+/*! BPDLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD40_SHIFT)) & LCD_WF8B_BPDLCD40_MASK)
+
+#define LCD_WF8B_BPDLCD41_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD41_SHIFT                  (3U)
+/*! BPDLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD41_SHIFT)) & LCD_WF8B_BPDLCD41_MASK)
+
+#define LCD_WF8B_BPDLCD42_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD42_SHIFT                  (3U)
+/*! BPDLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD42_SHIFT)) & LCD_WF8B_BPDLCD42_MASK)
+
+#define LCD_WF8B_BPDLCD43_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD43_SHIFT                  (3U)
+/*! BPDLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD43_SHIFT)) & LCD_WF8B_BPDLCD43_MASK)
+
+#define LCD_WF8B_BPDLCD44_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD44_SHIFT                  (3U)
+/*! BPDLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD44_SHIFT)) & LCD_WF8B_BPDLCD44_MASK)
+
+#define LCD_WF8B_BPDLCD45_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD45_SHIFT                  (3U)
+/*! BPDLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD45_SHIFT)) & LCD_WF8B_BPDLCD45_MASK)
+
+#define LCD_WF8B_BPDLCD46_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD46_SHIFT                  (3U)
+/*! BPDLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD46_SHIFT)) & LCD_WF8B_BPDLCD46_MASK)
+
+#define LCD_WF8B_BPDLCD47_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD47_SHIFT                  (3U)
+/*! BPDLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD47_SHIFT)) & LCD_WF8B_BPDLCD47_MASK)
+
+#define LCD_WF8B_BPDLCD48_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD48_SHIFT                  (3U)
+/*! BPDLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD48_SHIFT)) & LCD_WF8B_BPDLCD48_MASK)
+
+#define LCD_WF8B_BPDLCD49_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD49_SHIFT                  (3U)
+/*! BPDLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD49_SHIFT)) & LCD_WF8B_BPDLCD49_MASK)
+
+#define LCD_WF8B_BPDLCD50_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD50_SHIFT                  (3U)
+/*! BPDLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD50_SHIFT)) & LCD_WF8B_BPDLCD50_MASK)
+
+#define LCD_WF8B_BPDLCD51_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD51_SHIFT                  (3U)
+/*! BPDLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD51_SHIFT)) & LCD_WF8B_BPDLCD51_MASK)
+
+#define LCD_WF8B_BPDLCD52_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD52_SHIFT                  (3U)
+/*! BPDLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD52_SHIFT)) & LCD_WF8B_BPDLCD52_MASK)
+
+#define LCD_WF8B_BPDLCD53_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD53_SHIFT                  (3U)
+/*! BPDLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD53_SHIFT)) & LCD_WF8B_BPDLCD53_MASK)
+
+#define LCD_WF8B_BPDLCD54_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD54_SHIFT                  (3U)
+/*! BPDLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD54_SHIFT)) & LCD_WF8B_BPDLCD54_MASK)
+
+#define LCD_WF8B_BPDLCD55_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD55_SHIFT                  (3U)
+/*! BPDLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD55_SHIFT)) & LCD_WF8B_BPDLCD55_MASK)
+
+#define LCD_WF8B_BPDLCD56_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD56_SHIFT                  (3U)
+/*! BPDLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD56_SHIFT)) & LCD_WF8B_BPDLCD56_MASK)
+
+#define LCD_WF8B_BPDLCD57_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD57_SHIFT                  (3U)
+/*! BPDLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD57_SHIFT)) & LCD_WF8B_BPDLCD57_MASK)
+
+#define LCD_WF8B_BPDLCD58_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD58_SHIFT                  (3U)
+/*! BPDLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD58_SHIFT)) & LCD_WF8B_BPDLCD58_MASK)
+
+#define LCD_WF8B_BPDLCD59_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD59_SHIFT                  (3U)
+/*! BPDLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD59_SHIFT)) & LCD_WF8B_BPDLCD59_MASK)
+
+#define LCD_WF8B_BPDLCD60_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD60_SHIFT                  (3U)
+/*! BPDLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD60_SHIFT)) & LCD_WF8B_BPDLCD60_MASK)
+
+#define LCD_WF8B_BPDLCD61_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD61_SHIFT                  (3U)
+/*! BPDLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD61_SHIFT)) & LCD_WF8B_BPDLCD61_MASK)
+
+#define LCD_WF8B_BPDLCD62_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD62_SHIFT                  (3U)
+/*! BPDLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD62_SHIFT)) & LCD_WF8B_BPDLCD62_MASK)
+
+#define LCD_WF8B_BPDLCD63_MASK                   (0x8U)
+#define LCD_WF8B_BPDLCD63_SHIFT                  (3U)
+/*! BPDLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase D
+ *  0b1..LCD segment on or LCD backplane active for phase D
+ */
+#define LCD_WF8B_BPDLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPDLCD63_SHIFT)) & LCD_WF8B_BPDLCD63_MASK)
+
+#define LCD_WF8B_BPELCD0_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD0_SHIFT                   (4U)
+/*! BPELCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD0_SHIFT)) & LCD_WF8B_BPELCD0_MASK)
+
+#define LCD_WF8B_BPELCD1_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD1_SHIFT                   (4U)
+/*! BPELCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD1_SHIFT)) & LCD_WF8B_BPELCD1_MASK)
+
+#define LCD_WF8B_BPELCD2_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD2_SHIFT                   (4U)
+/*! BPELCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD2_SHIFT)) & LCD_WF8B_BPELCD2_MASK)
+
+#define LCD_WF8B_BPELCD3_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD3_SHIFT                   (4U)
+/*! BPELCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD3_SHIFT)) & LCD_WF8B_BPELCD3_MASK)
+
+#define LCD_WF8B_BPELCD4_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD4_SHIFT                   (4U)
+/*! BPELCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD4_SHIFT)) & LCD_WF8B_BPELCD4_MASK)
+
+#define LCD_WF8B_BPELCD5_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD5_SHIFT                   (4U)
+/*! BPELCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD5_SHIFT)) & LCD_WF8B_BPELCD5_MASK)
+
+#define LCD_WF8B_BPELCD6_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD6_SHIFT                   (4U)
+/*! BPELCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD6_SHIFT)) & LCD_WF8B_BPELCD6_MASK)
+
+#define LCD_WF8B_BPELCD7_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD7_SHIFT                   (4U)
+/*! BPELCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD7_SHIFT)) & LCD_WF8B_BPELCD7_MASK)
+
+#define LCD_WF8B_BPELCD8_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD8_SHIFT                   (4U)
+/*! BPELCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD8_SHIFT)) & LCD_WF8B_BPELCD8_MASK)
+
+#define LCD_WF8B_BPELCD9_MASK                    (0x10U)
+#define LCD_WF8B_BPELCD9_SHIFT                   (4U)
+/*! BPELCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD9_SHIFT)) & LCD_WF8B_BPELCD9_MASK)
+
+#define LCD_WF8B_BPELCD10_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD10_SHIFT                  (4U)
+/*! BPELCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD10_SHIFT)) & LCD_WF8B_BPELCD10_MASK)
+
+#define LCD_WF8B_BPELCD11_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD11_SHIFT                  (4U)
+/*! BPELCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD11_SHIFT)) & LCD_WF8B_BPELCD11_MASK)
+
+#define LCD_WF8B_BPELCD12_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD12_SHIFT                  (4U)
+/*! BPELCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD12_SHIFT)) & LCD_WF8B_BPELCD12_MASK)
+
+#define LCD_WF8B_BPELCD13_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD13_SHIFT                  (4U)
+/*! BPELCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD13_SHIFT)) & LCD_WF8B_BPELCD13_MASK)
+
+#define LCD_WF8B_BPELCD14_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD14_SHIFT                  (4U)
+/*! BPELCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD14_SHIFT)) & LCD_WF8B_BPELCD14_MASK)
+
+#define LCD_WF8B_BPELCD15_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD15_SHIFT                  (4U)
+/*! BPELCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD15_SHIFT)) & LCD_WF8B_BPELCD15_MASK)
+
+#define LCD_WF8B_BPELCD16_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD16_SHIFT                  (4U)
+/*! BPELCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD16_SHIFT)) & LCD_WF8B_BPELCD16_MASK)
+
+#define LCD_WF8B_BPELCD17_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD17_SHIFT                  (4U)
+/*! BPELCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD17_SHIFT)) & LCD_WF8B_BPELCD17_MASK)
+
+#define LCD_WF8B_BPELCD18_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD18_SHIFT                  (4U)
+/*! BPELCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD18_SHIFT)) & LCD_WF8B_BPELCD18_MASK)
+
+#define LCD_WF8B_BPELCD19_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD19_SHIFT                  (4U)
+/*! BPELCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD19_SHIFT)) & LCD_WF8B_BPELCD19_MASK)
+
+#define LCD_WF8B_BPELCD20_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD20_SHIFT                  (4U)
+/*! BPELCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD20_SHIFT)) & LCD_WF8B_BPELCD20_MASK)
+
+#define LCD_WF8B_BPELCD21_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD21_SHIFT                  (4U)
+/*! BPELCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD21_SHIFT)) & LCD_WF8B_BPELCD21_MASK)
+
+#define LCD_WF8B_BPELCD22_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD22_SHIFT                  (4U)
+/*! BPELCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD22_SHIFT)) & LCD_WF8B_BPELCD22_MASK)
+
+#define LCD_WF8B_BPELCD23_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD23_SHIFT                  (4U)
+/*! BPELCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD23_SHIFT)) & LCD_WF8B_BPELCD23_MASK)
+
+#define LCD_WF8B_BPELCD24_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD24_SHIFT                  (4U)
+/*! BPELCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD24_SHIFT)) & LCD_WF8B_BPELCD24_MASK)
+
+#define LCD_WF8B_BPELCD25_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD25_SHIFT                  (4U)
+/*! BPELCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD25_SHIFT)) & LCD_WF8B_BPELCD25_MASK)
+
+#define LCD_WF8B_BPELCD26_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD26_SHIFT                  (4U)
+/*! BPELCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD26_SHIFT)) & LCD_WF8B_BPELCD26_MASK)
+
+#define LCD_WF8B_BPELCD27_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD27_SHIFT                  (4U)
+/*! BPELCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD27_SHIFT)) & LCD_WF8B_BPELCD27_MASK)
+
+#define LCD_WF8B_BPELCD28_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD28_SHIFT                  (4U)
+/*! BPELCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD28_SHIFT)) & LCD_WF8B_BPELCD28_MASK)
+
+#define LCD_WF8B_BPELCD29_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD29_SHIFT                  (4U)
+/*! BPELCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD29_SHIFT)) & LCD_WF8B_BPELCD29_MASK)
+
+#define LCD_WF8B_BPELCD30_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD30_SHIFT                  (4U)
+/*! BPELCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD30_SHIFT)) & LCD_WF8B_BPELCD30_MASK)
+
+#define LCD_WF8B_BPELCD31_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD31_SHIFT                  (4U)
+/*! BPELCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD31_SHIFT)) & LCD_WF8B_BPELCD31_MASK)
+
+#define LCD_WF8B_BPELCD32_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD32_SHIFT                  (4U)
+/*! BPELCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD32_SHIFT)) & LCD_WF8B_BPELCD32_MASK)
+
+#define LCD_WF8B_BPELCD33_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD33_SHIFT                  (4U)
+/*! BPELCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD33_SHIFT)) & LCD_WF8B_BPELCD33_MASK)
+
+#define LCD_WF8B_BPELCD34_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD34_SHIFT                  (4U)
+/*! BPELCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD34_SHIFT)) & LCD_WF8B_BPELCD34_MASK)
+
+#define LCD_WF8B_BPELCD35_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD35_SHIFT                  (4U)
+/*! BPELCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD35_SHIFT)) & LCD_WF8B_BPELCD35_MASK)
+
+#define LCD_WF8B_BPELCD36_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD36_SHIFT                  (4U)
+/*! BPELCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD36_SHIFT)) & LCD_WF8B_BPELCD36_MASK)
+
+#define LCD_WF8B_BPELCD37_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD37_SHIFT                  (4U)
+/*! BPELCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD37_SHIFT)) & LCD_WF8B_BPELCD37_MASK)
+
+#define LCD_WF8B_BPELCD38_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD38_SHIFT                  (4U)
+/*! BPELCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD38_SHIFT)) & LCD_WF8B_BPELCD38_MASK)
+
+#define LCD_WF8B_BPELCD39_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD39_SHIFT                  (4U)
+/*! BPELCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD39_SHIFT)) & LCD_WF8B_BPELCD39_MASK)
+
+#define LCD_WF8B_BPELCD40_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD40_SHIFT                  (4U)
+/*! BPELCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD40_SHIFT)) & LCD_WF8B_BPELCD40_MASK)
+
+#define LCD_WF8B_BPELCD41_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD41_SHIFT                  (4U)
+/*! BPELCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD41_SHIFT)) & LCD_WF8B_BPELCD41_MASK)
+
+#define LCD_WF8B_BPELCD42_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD42_SHIFT                  (4U)
+/*! BPELCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD42_SHIFT)) & LCD_WF8B_BPELCD42_MASK)
+
+#define LCD_WF8B_BPELCD43_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD43_SHIFT                  (4U)
+/*! BPELCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD43_SHIFT)) & LCD_WF8B_BPELCD43_MASK)
+
+#define LCD_WF8B_BPELCD44_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD44_SHIFT                  (4U)
+/*! BPELCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD44_SHIFT)) & LCD_WF8B_BPELCD44_MASK)
+
+#define LCD_WF8B_BPELCD45_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD45_SHIFT                  (4U)
+/*! BPELCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD45_SHIFT)) & LCD_WF8B_BPELCD45_MASK)
+
+#define LCD_WF8B_BPELCD46_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD46_SHIFT                  (4U)
+/*! BPELCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD46_SHIFT)) & LCD_WF8B_BPELCD46_MASK)
+
+#define LCD_WF8B_BPELCD47_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD47_SHIFT                  (4U)
+/*! BPELCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD47_SHIFT)) & LCD_WF8B_BPELCD47_MASK)
+
+#define LCD_WF8B_BPELCD48_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD48_SHIFT                  (4U)
+/*! BPELCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD48_SHIFT)) & LCD_WF8B_BPELCD48_MASK)
+
+#define LCD_WF8B_BPELCD49_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD49_SHIFT                  (4U)
+/*! BPELCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD49_SHIFT)) & LCD_WF8B_BPELCD49_MASK)
+
+#define LCD_WF8B_BPELCD50_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD50_SHIFT                  (4U)
+/*! BPELCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD50_SHIFT)) & LCD_WF8B_BPELCD50_MASK)
+
+#define LCD_WF8B_BPELCD51_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD51_SHIFT                  (4U)
+/*! BPELCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD51_SHIFT)) & LCD_WF8B_BPELCD51_MASK)
+
+#define LCD_WF8B_BPELCD52_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD52_SHIFT                  (4U)
+/*! BPELCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD52_SHIFT)) & LCD_WF8B_BPELCD52_MASK)
+
+#define LCD_WF8B_BPELCD53_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD53_SHIFT                  (4U)
+/*! BPELCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD53_SHIFT)) & LCD_WF8B_BPELCD53_MASK)
+
+#define LCD_WF8B_BPELCD54_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD54_SHIFT                  (4U)
+/*! BPELCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD54_SHIFT)) & LCD_WF8B_BPELCD54_MASK)
+
+#define LCD_WF8B_BPELCD55_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD55_SHIFT                  (4U)
+/*! BPELCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD55_SHIFT)) & LCD_WF8B_BPELCD55_MASK)
+
+#define LCD_WF8B_BPELCD56_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD56_SHIFT                  (4U)
+/*! BPELCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD56_SHIFT)) & LCD_WF8B_BPELCD56_MASK)
+
+#define LCD_WF8B_BPELCD57_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD57_SHIFT                  (4U)
+/*! BPELCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD57_SHIFT)) & LCD_WF8B_BPELCD57_MASK)
+
+#define LCD_WF8B_BPELCD58_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD58_SHIFT                  (4U)
+/*! BPELCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD58_SHIFT)) & LCD_WF8B_BPELCD58_MASK)
+
+#define LCD_WF8B_BPELCD59_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD59_SHIFT                  (4U)
+/*! BPELCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD59_SHIFT)) & LCD_WF8B_BPELCD59_MASK)
+
+#define LCD_WF8B_BPELCD60_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD60_SHIFT                  (4U)
+/*! BPELCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD60_SHIFT)) & LCD_WF8B_BPELCD60_MASK)
+
+#define LCD_WF8B_BPELCD61_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD61_SHIFT                  (4U)
+/*! BPELCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD61_SHIFT)) & LCD_WF8B_BPELCD61_MASK)
+
+#define LCD_WF8B_BPELCD62_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD62_SHIFT                  (4U)
+/*! BPELCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD62_SHIFT)) & LCD_WF8B_BPELCD62_MASK)
+
+#define LCD_WF8B_BPELCD63_MASK                   (0x10U)
+#define LCD_WF8B_BPELCD63_SHIFT                  (4U)
+/*! BPELCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase E
+ *  0b1..LCD segment on or LCD backplane active for phase E
+ */
+#define LCD_WF8B_BPELCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPELCD63_SHIFT)) & LCD_WF8B_BPELCD63_MASK)
+
+#define LCD_WF8B_BPFLCD0_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD0_SHIFT                   (5U)
+/*! BPFLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD0_SHIFT)) & LCD_WF8B_BPFLCD0_MASK)
+
+#define LCD_WF8B_BPFLCD1_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD1_SHIFT                   (5U)
+/*! BPFLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD1_SHIFT)) & LCD_WF8B_BPFLCD1_MASK)
+
+#define LCD_WF8B_BPFLCD2_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD2_SHIFT                   (5U)
+/*! BPFLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD2_SHIFT)) & LCD_WF8B_BPFLCD2_MASK)
+
+#define LCD_WF8B_BPFLCD3_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD3_SHIFT                   (5U)
+/*! BPFLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD3_SHIFT)) & LCD_WF8B_BPFLCD3_MASK)
+
+#define LCD_WF8B_BPFLCD4_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD4_SHIFT                   (5U)
+/*! BPFLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD4_SHIFT)) & LCD_WF8B_BPFLCD4_MASK)
+
+#define LCD_WF8B_BPFLCD5_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD5_SHIFT                   (5U)
+/*! BPFLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD5_SHIFT)) & LCD_WF8B_BPFLCD5_MASK)
+
+#define LCD_WF8B_BPFLCD6_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD6_SHIFT                   (5U)
+/*! BPFLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD6_SHIFT)) & LCD_WF8B_BPFLCD6_MASK)
+
+#define LCD_WF8B_BPFLCD7_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD7_SHIFT                   (5U)
+/*! BPFLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD7_SHIFT)) & LCD_WF8B_BPFLCD7_MASK)
+
+#define LCD_WF8B_BPFLCD8_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD8_SHIFT                   (5U)
+/*! BPFLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD8_SHIFT)) & LCD_WF8B_BPFLCD8_MASK)
+
+#define LCD_WF8B_BPFLCD9_MASK                    (0x20U)
+#define LCD_WF8B_BPFLCD9_SHIFT                   (5U)
+/*! BPFLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD9_SHIFT)) & LCD_WF8B_BPFLCD9_MASK)
+
+#define LCD_WF8B_BPFLCD10_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD10_SHIFT                  (5U)
+/*! BPFLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD10_SHIFT)) & LCD_WF8B_BPFLCD10_MASK)
+
+#define LCD_WF8B_BPFLCD11_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD11_SHIFT                  (5U)
+/*! BPFLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD11_SHIFT)) & LCD_WF8B_BPFLCD11_MASK)
+
+#define LCD_WF8B_BPFLCD12_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD12_SHIFT                  (5U)
+/*! BPFLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD12_SHIFT)) & LCD_WF8B_BPFLCD12_MASK)
+
+#define LCD_WF8B_BPFLCD13_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD13_SHIFT                  (5U)
+/*! BPFLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD13_SHIFT)) & LCD_WF8B_BPFLCD13_MASK)
+
+#define LCD_WF8B_BPFLCD14_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD14_SHIFT                  (5U)
+/*! BPFLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD14_SHIFT)) & LCD_WF8B_BPFLCD14_MASK)
+
+#define LCD_WF8B_BPFLCD15_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD15_SHIFT                  (5U)
+/*! BPFLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD15_SHIFT)) & LCD_WF8B_BPFLCD15_MASK)
+
+#define LCD_WF8B_BPFLCD16_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD16_SHIFT                  (5U)
+/*! BPFLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD16_SHIFT)) & LCD_WF8B_BPFLCD16_MASK)
+
+#define LCD_WF8B_BPFLCD17_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD17_SHIFT                  (5U)
+/*! BPFLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD17_SHIFT)) & LCD_WF8B_BPFLCD17_MASK)
+
+#define LCD_WF8B_BPFLCD18_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD18_SHIFT                  (5U)
+/*! BPFLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD18_SHIFT)) & LCD_WF8B_BPFLCD18_MASK)
+
+#define LCD_WF8B_BPFLCD19_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD19_SHIFT                  (5U)
+/*! BPFLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD19_SHIFT)) & LCD_WF8B_BPFLCD19_MASK)
+
+#define LCD_WF8B_BPFLCD20_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD20_SHIFT                  (5U)
+/*! BPFLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD20_SHIFT)) & LCD_WF8B_BPFLCD20_MASK)
+
+#define LCD_WF8B_BPFLCD21_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD21_SHIFT                  (5U)
+/*! BPFLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD21_SHIFT)) & LCD_WF8B_BPFLCD21_MASK)
+
+#define LCD_WF8B_BPFLCD22_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD22_SHIFT                  (5U)
+/*! BPFLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD22_SHIFT)) & LCD_WF8B_BPFLCD22_MASK)
+
+#define LCD_WF8B_BPFLCD23_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD23_SHIFT                  (5U)
+/*! BPFLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD23_SHIFT)) & LCD_WF8B_BPFLCD23_MASK)
+
+#define LCD_WF8B_BPFLCD24_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD24_SHIFT                  (5U)
+/*! BPFLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD24_SHIFT)) & LCD_WF8B_BPFLCD24_MASK)
+
+#define LCD_WF8B_BPFLCD25_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD25_SHIFT                  (5U)
+/*! BPFLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD25_SHIFT)) & LCD_WF8B_BPFLCD25_MASK)
+
+#define LCD_WF8B_BPFLCD26_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD26_SHIFT                  (5U)
+/*! BPFLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD26_SHIFT)) & LCD_WF8B_BPFLCD26_MASK)
+
+#define LCD_WF8B_BPFLCD27_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD27_SHIFT                  (5U)
+/*! BPFLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD27_SHIFT)) & LCD_WF8B_BPFLCD27_MASK)
+
+#define LCD_WF8B_BPFLCD28_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD28_SHIFT                  (5U)
+/*! BPFLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD28_SHIFT)) & LCD_WF8B_BPFLCD28_MASK)
+
+#define LCD_WF8B_BPFLCD29_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD29_SHIFT                  (5U)
+/*! BPFLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD29_SHIFT)) & LCD_WF8B_BPFLCD29_MASK)
+
+#define LCD_WF8B_BPFLCD30_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD30_SHIFT                  (5U)
+/*! BPFLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD30_SHIFT)) & LCD_WF8B_BPFLCD30_MASK)
+
+#define LCD_WF8B_BPFLCD31_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD31_SHIFT                  (5U)
+/*! BPFLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD31_SHIFT)) & LCD_WF8B_BPFLCD31_MASK)
+
+#define LCD_WF8B_BPFLCD32_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD32_SHIFT                  (5U)
+/*! BPFLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD32_SHIFT)) & LCD_WF8B_BPFLCD32_MASK)
+
+#define LCD_WF8B_BPFLCD33_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD33_SHIFT                  (5U)
+/*! BPFLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD33_SHIFT)) & LCD_WF8B_BPFLCD33_MASK)
+
+#define LCD_WF8B_BPFLCD34_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD34_SHIFT                  (5U)
+/*! BPFLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD34_SHIFT)) & LCD_WF8B_BPFLCD34_MASK)
+
+#define LCD_WF8B_BPFLCD35_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD35_SHIFT                  (5U)
+/*! BPFLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD35_SHIFT)) & LCD_WF8B_BPFLCD35_MASK)
+
+#define LCD_WF8B_BPFLCD36_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD36_SHIFT                  (5U)
+/*! BPFLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD36_SHIFT)) & LCD_WF8B_BPFLCD36_MASK)
+
+#define LCD_WF8B_BPFLCD37_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD37_SHIFT                  (5U)
+/*! BPFLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD37_SHIFT)) & LCD_WF8B_BPFLCD37_MASK)
+
+#define LCD_WF8B_BPFLCD38_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD38_SHIFT                  (5U)
+/*! BPFLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD38_SHIFT)) & LCD_WF8B_BPFLCD38_MASK)
+
+#define LCD_WF8B_BPFLCD39_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD39_SHIFT                  (5U)
+/*! BPFLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD39_SHIFT)) & LCD_WF8B_BPFLCD39_MASK)
+
+#define LCD_WF8B_BPFLCD40_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD40_SHIFT                  (5U)
+/*! BPFLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD40_SHIFT)) & LCD_WF8B_BPFLCD40_MASK)
+
+#define LCD_WF8B_BPFLCD41_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD41_SHIFT                  (5U)
+/*! BPFLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD41_SHIFT)) & LCD_WF8B_BPFLCD41_MASK)
+
+#define LCD_WF8B_BPFLCD42_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD42_SHIFT                  (5U)
+/*! BPFLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD42_SHIFT)) & LCD_WF8B_BPFLCD42_MASK)
+
+#define LCD_WF8B_BPFLCD43_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD43_SHIFT                  (5U)
+/*! BPFLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD43_SHIFT)) & LCD_WF8B_BPFLCD43_MASK)
+
+#define LCD_WF8B_BPFLCD44_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD44_SHIFT                  (5U)
+/*! BPFLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD44_SHIFT)) & LCD_WF8B_BPFLCD44_MASK)
+
+#define LCD_WF8B_BPFLCD45_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD45_SHIFT                  (5U)
+/*! BPFLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD45_SHIFT)) & LCD_WF8B_BPFLCD45_MASK)
+
+#define LCD_WF8B_BPFLCD46_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD46_SHIFT                  (5U)
+/*! BPFLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD46_SHIFT)) & LCD_WF8B_BPFLCD46_MASK)
+
+#define LCD_WF8B_BPFLCD47_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD47_SHIFT                  (5U)
+/*! BPFLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD47_SHIFT)) & LCD_WF8B_BPFLCD47_MASK)
+
+#define LCD_WF8B_BPFLCD48_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD48_SHIFT                  (5U)
+/*! BPFLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD48_SHIFT)) & LCD_WF8B_BPFLCD48_MASK)
+
+#define LCD_WF8B_BPFLCD49_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD49_SHIFT                  (5U)
+/*! BPFLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD49_SHIFT)) & LCD_WF8B_BPFLCD49_MASK)
+
+#define LCD_WF8B_BPFLCD50_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD50_SHIFT                  (5U)
+/*! BPFLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD50_SHIFT)) & LCD_WF8B_BPFLCD50_MASK)
+
+#define LCD_WF8B_BPFLCD51_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD51_SHIFT                  (5U)
+/*! BPFLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD51_SHIFT)) & LCD_WF8B_BPFLCD51_MASK)
+
+#define LCD_WF8B_BPFLCD52_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD52_SHIFT                  (5U)
+/*! BPFLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD52_SHIFT)) & LCD_WF8B_BPFLCD52_MASK)
+
+#define LCD_WF8B_BPFLCD53_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD53_SHIFT                  (5U)
+/*! BPFLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD53_SHIFT)) & LCD_WF8B_BPFLCD53_MASK)
+
+#define LCD_WF8B_BPFLCD54_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD54_SHIFT                  (5U)
+/*! BPFLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD54_SHIFT)) & LCD_WF8B_BPFLCD54_MASK)
+
+#define LCD_WF8B_BPFLCD55_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD55_SHIFT                  (5U)
+/*! BPFLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD55_SHIFT)) & LCD_WF8B_BPFLCD55_MASK)
+
+#define LCD_WF8B_BPFLCD56_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD56_SHIFT                  (5U)
+/*! BPFLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD56_SHIFT)) & LCD_WF8B_BPFLCD56_MASK)
+
+#define LCD_WF8B_BPFLCD57_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD57_SHIFT                  (5U)
+/*! BPFLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD57_SHIFT)) & LCD_WF8B_BPFLCD57_MASK)
+
+#define LCD_WF8B_BPFLCD58_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD58_SHIFT                  (5U)
+/*! BPFLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD58_SHIFT)) & LCD_WF8B_BPFLCD58_MASK)
+
+#define LCD_WF8B_BPFLCD59_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD59_SHIFT                  (5U)
+/*! BPFLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD59_SHIFT)) & LCD_WF8B_BPFLCD59_MASK)
+
+#define LCD_WF8B_BPFLCD60_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD60_SHIFT                  (5U)
+/*! BPFLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD60_SHIFT)) & LCD_WF8B_BPFLCD60_MASK)
+
+#define LCD_WF8B_BPFLCD61_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD61_SHIFT                  (5U)
+/*! BPFLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD61_SHIFT)) & LCD_WF8B_BPFLCD61_MASK)
+
+#define LCD_WF8B_BPFLCD62_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD62_SHIFT                  (5U)
+/*! BPFLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD62_SHIFT)) & LCD_WF8B_BPFLCD62_MASK)
+
+#define LCD_WF8B_BPFLCD63_MASK                   (0x20U)
+#define LCD_WF8B_BPFLCD63_SHIFT                  (5U)
+/*! BPFLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase F
+ *  0b1..LCD segment on or LCD backplane active for phase F
+ */
+#define LCD_WF8B_BPFLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPFLCD63_SHIFT)) & LCD_WF8B_BPFLCD63_MASK)
+
+#define LCD_WF8B_BPGLCD0_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD0_SHIFT                   (6U)
+/*! BPGLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD0_SHIFT)) & LCD_WF8B_BPGLCD0_MASK)
+
+#define LCD_WF8B_BPGLCD1_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD1_SHIFT                   (6U)
+/*! BPGLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD1_SHIFT)) & LCD_WF8B_BPGLCD1_MASK)
+
+#define LCD_WF8B_BPGLCD2_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD2_SHIFT                   (6U)
+/*! BPGLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD2_SHIFT)) & LCD_WF8B_BPGLCD2_MASK)
+
+#define LCD_WF8B_BPGLCD3_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD3_SHIFT                   (6U)
+/*! BPGLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD3_SHIFT)) & LCD_WF8B_BPGLCD3_MASK)
+
+#define LCD_WF8B_BPGLCD4_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD4_SHIFT                   (6U)
+/*! BPGLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD4_SHIFT)) & LCD_WF8B_BPGLCD4_MASK)
+
+#define LCD_WF8B_BPGLCD5_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD5_SHIFT                   (6U)
+/*! BPGLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD5_SHIFT)) & LCD_WF8B_BPGLCD5_MASK)
+
+#define LCD_WF8B_BPGLCD6_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD6_SHIFT                   (6U)
+/*! BPGLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD6_SHIFT)) & LCD_WF8B_BPGLCD6_MASK)
+
+#define LCD_WF8B_BPGLCD7_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD7_SHIFT                   (6U)
+/*! BPGLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD7_SHIFT)) & LCD_WF8B_BPGLCD7_MASK)
+
+#define LCD_WF8B_BPGLCD8_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD8_SHIFT                   (6U)
+/*! BPGLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD8_SHIFT)) & LCD_WF8B_BPGLCD8_MASK)
+
+#define LCD_WF8B_BPGLCD9_MASK                    (0x40U)
+#define LCD_WF8B_BPGLCD9_SHIFT                   (6U)
+/*! BPGLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD9_SHIFT)) & LCD_WF8B_BPGLCD9_MASK)
+
+#define LCD_WF8B_BPGLCD10_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD10_SHIFT                  (6U)
+/*! BPGLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD10_SHIFT)) & LCD_WF8B_BPGLCD10_MASK)
+
+#define LCD_WF8B_BPGLCD11_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD11_SHIFT                  (6U)
+/*! BPGLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD11_SHIFT)) & LCD_WF8B_BPGLCD11_MASK)
+
+#define LCD_WF8B_BPGLCD12_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD12_SHIFT                  (6U)
+/*! BPGLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD12_SHIFT)) & LCD_WF8B_BPGLCD12_MASK)
+
+#define LCD_WF8B_BPGLCD13_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD13_SHIFT                  (6U)
+/*! BPGLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD13_SHIFT)) & LCD_WF8B_BPGLCD13_MASK)
+
+#define LCD_WF8B_BPGLCD14_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD14_SHIFT                  (6U)
+/*! BPGLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD14_SHIFT)) & LCD_WF8B_BPGLCD14_MASK)
+
+#define LCD_WF8B_BPGLCD15_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD15_SHIFT                  (6U)
+/*! BPGLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD15_SHIFT)) & LCD_WF8B_BPGLCD15_MASK)
+
+#define LCD_WF8B_BPGLCD16_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD16_SHIFT                  (6U)
+/*! BPGLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD16_SHIFT)) & LCD_WF8B_BPGLCD16_MASK)
+
+#define LCD_WF8B_BPGLCD17_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD17_SHIFT                  (6U)
+/*! BPGLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD17_SHIFT)) & LCD_WF8B_BPGLCD17_MASK)
+
+#define LCD_WF8B_BPGLCD18_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD18_SHIFT                  (6U)
+/*! BPGLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD18_SHIFT)) & LCD_WF8B_BPGLCD18_MASK)
+
+#define LCD_WF8B_BPGLCD19_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD19_SHIFT                  (6U)
+/*! BPGLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD19_SHIFT)) & LCD_WF8B_BPGLCD19_MASK)
+
+#define LCD_WF8B_BPGLCD20_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD20_SHIFT                  (6U)
+/*! BPGLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD20_SHIFT)) & LCD_WF8B_BPGLCD20_MASK)
+
+#define LCD_WF8B_BPGLCD21_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD21_SHIFT                  (6U)
+/*! BPGLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD21_SHIFT)) & LCD_WF8B_BPGLCD21_MASK)
+
+#define LCD_WF8B_BPGLCD22_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD22_SHIFT                  (6U)
+/*! BPGLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD22_SHIFT)) & LCD_WF8B_BPGLCD22_MASK)
+
+#define LCD_WF8B_BPGLCD23_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD23_SHIFT                  (6U)
+/*! BPGLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD23_SHIFT)) & LCD_WF8B_BPGLCD23_MASK)
+
+#define LCD_WF8B_BPGLCD24_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD24_SHIFT                  (6U)
+/*! BPGLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD24_SHIFT)) & LCD_WF8B_BPGLCD24_MASK)
+
+#define LCD_WF8B_BPGLCD25_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD25_SHIFT                  (6U)
+/*! BPGLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD25_SHIFT)) & LCD_WF8B_BPGLCD25_MASK)
+
+#define LCD_WF8B_BPGLCD26_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD26_SHIFT                  (6U)
+/*! BPGLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD26_SHIFT)) & LCD_WF8B_BPGLCD26_MASK)
+
+#define LCD_WF8B_BPGLCD27_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD27_SHIFT                  (6U)
+/*! BPGLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD27_SHIFT)) & LCD_WF8B_BPGLCD27_MASK)
+
+#define LCD_WF8B_BPGLCD28_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD28_SHIFT                  (6U)
+/*! BPGLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD28_SHIFT)) & LCD_WF8B_BPGLCD28_MASK)
+
+#define LCD_WF8B_BPGLCD29_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD29_SHIFT                  (6U)
+/*! BPGLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD29_SHIFT)) & LCD_WF8B_BPGLCD29_MASK)
+
+#define LCD_WF8B_BPGLCD30_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD30_SHIFT                  (6U)
+/*! BPGLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD30_SHIFT)) & LCD_WF8B_BPGLCD30_MASK)
+
+#define LCD_WF8B_BPGLCD31_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD31_SHIFT                  (6U)
+/*! BPGLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD31_SHIFT)) & LCD_WF8B_BPGLCD31_MASK)
+
+#define LCD_WF8B_BPGLCD32_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD32_SHIFT                  (6U)
+/*! BPGLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD32_SHIFT)) & LCD_WF8B_BPGLCD32_MASK)
+
+#define LCD_WF8B_BPGLCD33_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD33_SHIFT                  (6U)
+/*! BPGLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD33_SHIFT)) & LCD_WF8B_BPGLCD33_MASK)
+
+#define LCD_WF8B_BPGLCD34_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD34_SHIFT                  (6U)
+/*! BPGLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD34_SHIFT)) & LCD_WF8B_BPGLCD34_MASK)
+
+#define LCD_WF8B_BPGLCD35_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD35_SHIFT                  (6U)
+/*! BPGLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD35_SHIFT)) & LCD_WF8B_BPGLCD35_MASK)
+
+#define LCD_WF8B_BPGLCD36_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD36_SHIFT                  (6U)
+/*! BPGLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD36_SHIFT)) & LCD_WF8B_BPGLCD36_MASK)
+
+#define LCD_WF8B_BPGLCD37_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD37_SHIFT                  (6U)
+/*! BPGLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD37_SHIFT)) & LCD_WF8B_BPGLCD37_MASK)
+
+#define LCD_WF8B_BPGLCD38_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD38_SHIFT                  (6U)
+/*! BPGLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD38_SHIFT)) & LCD_WF8B_BPGLCD38_MASK)
+
+#define LCD_WF8B_BPGLCD39_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD39_SHIFT                  (6U)
+/*! BPGLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD39_SHIFT)) & LCD_WF8B_BPGLCD39_MASK)
+
+#define LCD_WF8B_BPGLCD40_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD40_SHIFT                  (6U)
+/*! BPGLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD40_SHIFT)) & LCD_WF8B_BPGLCD40_MASK)
+
+#define LCD_WF8B_BPGLCD41_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD41_SHIFT                  (6U)
+/*! BPGLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD41_SHIFT)) & LCD_WF8B_BPGLCD41_MASK)
+
+#define LCD_WF8B_BPGLCD42_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD42_SHIFT                  (6U)
+/*! BPGLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD42_SHIFT)) & LCD_WF8B_BPGLCD42_MASK)
+
+#define LCD_WF8B_BPGLCD43_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD43_SHIFT                  (6U)
+/*! BPGLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD43_SHIFT)) & LCD_WF8B_BPGLCD43_MASK)
+
+#define LCD_WF8B_BPGLCD44_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD44_SHIFT                  (6U)
+/*! BPGLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD44_SHIFT)) & LCD_WF8B_BPGLCD44_MASK)
+
+#define LCD_WF8B_BPGLCD45_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD45_SHIFT                  (6U)
+/*! BPGLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD45_SHIFT)) & LCD_WF8B_BPGLCD45_MASK)
+
+#define LCD_WF8B_BPGLCD46_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD46_SHIFT                  (6U)
+/*! BPGLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD46_SHIFT)) & LCD_WF8B_BPGLCD46_MASK)
+
+#define LCD_WF8B_BPGLCD47_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD47_SHIFT                  (6U)
+/*! BPGLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD47_SHIFT)) & LCD_WF8B_BPGLCD47_MASK)
+
+#define LCD_WF8B_BPGLCD48_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD48_SHIFT                  (6U)
+/*! BPGLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD48_SHIFT)) & LCD_WF8B_BPGLCD48_MASK)
+
+#define LCD_WF8B_BPGLCD49_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD49_SHIFT                  (6U)
+/*! BPGLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD49_SHIFT)) & LCD_WF8B_BPGLCD49_MASK)
+
+#define LCD_WF8B_BPGLCD50_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD50_SHIFT                  (6U)
+/*! BPGLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD50_SHIFT)) & LCD_WF8B_BPGLCD50_MASK)
+
+#define LCD_WF8B_BPGLCD51_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD51_SHIFT                  (6U)
+/*! BPGLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD51_SHIFT)) & LCD_WF8B_BPGLCD51_MASK)
+
+#define LCD_WF8B_BPGLCD52_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD52_SHIFT                  (6U)
+/*! BPGLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD52_SHIFT)) & LCD_WF8B_BPGLCD52_MASK)
+
+#define LCD_WF8B_BPGLCD53_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD53_SHIFT                  (6U)
+/*! BPGLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD53_SHIFT)) & LCD_WF8B_BPGLCD53_MASK)
+
+#define LCD_WF8B_BPGLCD54_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD54_SHIFT                  (6U)
+/*! BPGLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD54_SHIFT)) & LCD_WF8B_BPGLCD54_MASK)
+
+#define LCD_WF8B_BPGLCD55_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD55_SHIFT                  (6U)
+/*! BPGLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD55_SHIFT)) & LCD_WF8B_BPGLCD55_MASK)
+
+#define LCD_WF8B_BPGLCD56_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD56_SHIFT                  (6U)
+/*! BPGLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD56_SHIFT)) & LCD_WF8B_BPGLCD56_MASK)
+
+#define LCD_WF8B_BPGLCD57_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD57_SHIFT                  (6U)
+/*! BPGLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD57_SHIFT)) & LCD_WF8B_BPGLCD57_MASK)
+
+#define LCD_WF8B_BPGLCD58_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD58_SHIFT                  (6U)
+/*! BPGLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD58_SHIFT)) & LCD_WF8B_BPGLCD58_MASK)
+
+#define LCD_WF8B_BPGLCD59_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD59_SHIFT                  (6U)
+/*! BPGLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD59_SHIFT)) & LCD_WF8B_BPGLCD59_MASK)
+
+#define LCD_WF8B_BPGLCD60_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD60_SHIFT                  (6U)
+/*! BPGLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD60_SHIFT)) & LCD_WF8B_BPGLCD60_MASK)
+
+#define LCD_WF8B_BPGLCD61_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD61_SHIFT                  (6U)
+/*! BPGLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD61_SHIFT)) & LCD_WF8B_BPGLCD61_MASK)
+
+#define LCD_WF8B_BPGLCD62_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD62_SHIFT                  (6U)
+/*! BPGLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD62_SHIFT)) & LCD_WF8B_BPGLCD62_MASK)
+
+#define LCD_WF8B_BPGLCD63_MASK                   (0x40U)
+#define LCD_WF8B_BPGLCD63_SHIFT                  (6U)
+/*! BPGLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase G
+ *  0b1..LCD segment on or LCD backplane active for phase G
+ */
+#define LCD_WF8B_BPGLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPGLCD63_SHIFT)) & LCD_WF8B_BPGLCD63_MASK)
+
+#define LCD_WF8B_BPHLCD0_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD0_SHIFT                   (7U)
+/*! BPHLCD0
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD0(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD0_SHIFT)) & LCD_WF8B_BPHLCD0_MASK)
+
+#define LCD_WF8B_BPHLCD1_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD1_SHIFT                   (7U)
+/*! BPHLCD1
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD1(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD1_SHIFT)) & LCD_WF8B_BPHLCD1_MASK)
+
+#define LCD_WF8B_BPHLCD2_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD2_SHIFT                   (7U)
+/*! BPHLCD2
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD2(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD2_SHIFT)) & LCD_WF8B_BPHLCD2_MASK)
+
+#define LCD_WF8B_BPHLCD3_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD3_SHIFT                   (7U)
+/*! BPHLCD3
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD3(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD3_SHIFT)) & LCD_WF8B_BPHLCD3_MASK)
+
+#define LCD_WF8B_BPHLCD4_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD4_SHIFT                   (7U)
+/*! BPHLCD4
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD4(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD4_SHIFT)) & LCD_WF8B_BPHLCD4_MASK)
+
+#define LCD_WF8B_BPHLCD5_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD5_SHIFT                   (7U)
+/*! BPHLCD5
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD5(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD5_SHIFT)) & LCD_WF8B_BPHLCD5_MASK)
+
+#define LCD_WF8B_BPHLCD6_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD6_SHIFT                   (7U)
+/*! BPHLCD6
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD6(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD6_SHIFT)) & LCD_WF8B_BPHLCD6_MASK)
+
+#define LCD_WF8B_BPHLCD7_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD7_SHIFT                   (7U)
+/*! BPHLCD7
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD7(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD7_SHIFT)) & LCD_WF8B_BPHLCD7_MASK)
+
+#define LCD_WF8B_BPHLCD8_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD8_SHIFT                   (7U)
+/*! BPHLCD8
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD8(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD8_SHIFT)) & LCD_WF8B_BPHLCD8_MASK)
+
+#define LCD_WF8B_BPHLCD9_MASK                    (0x80U)
+#define LCD_WF8B_BPHLCD9_SHIFT                   (7U)
+/*! BPHLCD9
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD9(x)                      (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD9_SHIFT)) & LCD_WF8B_BPHLCD9_MASK)
+
+#define LCD_WF8B_BPHLCD10_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD10_SHIFT                  (7U)
+/*! BPHLCD10
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD10(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD10_SHIFT)) & LCD_WF8B_BPHLCD10_MASK)
+
+#define LCD_WF8B_BPHLCD11_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD11_SHIFT                  (7U)
+/*! BPHLCD11
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD11(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD11_SHIFT)) & LCD_WF8B_BPHLCD11_MASK)
+
+#define LCD_WF8B_BPHLCD12_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD12_SHIFT                  (7U)
+/*! BPHLCD12
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD12(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD12_SHIFT)) & LCD_WF8B_BPHLCD12_MASK)
+
+#define LCD_WF8B_BPHLCD13_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD13_SHIFT                  (7U)
+/*! BPHLCD13
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD13(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD13_SHIFT)) & LCD_WF8B_BPHLCD13_MASK)
+
+#define LCD_WF8B_BPHLCD14_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD14_SHIFT                  (7U)
+/*! BPHLCD14
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD14(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD14_SHIFT)) & LCD_WF8B_BPHLCD14_MASK)
+
+#define LCD_WF8B_BPHLCD15_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD15_SHIFT                  (7U)
+/*! BPHLCD15
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD15(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD15_SHIFT)) & LCD_WF8B_BPHLCD15_MASK)
+
+#define LCD_WF8B_BPHLCD16_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD16_SHIFT                  (7U)
+/*! BPHLCD16
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD16(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD16_SHIFT)) & LCD_WF8B_BPHLCD16_MASK)
+
+#define LCD_WF8B_BPHLCD17_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD17_SHIFT                  (7U)
+/*! BPHLCD17
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD17(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD17_SHIFT)) & LCD_WF8B_BPHLCD17_MASK)
+
+#define LCD_WF8B_BPHLCD18_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD18_SHIFT                  (7U)
+/*! BPHLCD18
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD18(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD18_SHIFT)) & LCD_WF8B_BPHLCD18_MASK)
+
+#define LCD_WF8B_BPHLCD19_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD19_SHIFT                  (7U)
+/*! BPHLCD19
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD19(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD19_SHIFT)) & LCD_WF8B_BPHLCD19_MASK)
+
+#define LCD_WF8B_BPHLCD20_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD20_SHIFT                  (7U)
+/*! BPHLCD20
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD20(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD20_SHIFT)) & LCD_WF8B_BPHLCD20_MASK)
+
+#define LCD_WF8B_BPHLCD21_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD21_SHIFT                  (7U)
+/*! BPHLCD21
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD21(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD21_SHIFT)) & LCD_WF8B_BPHLCD21_MASK)
+
+#define LCD_WF8B_BPHLCD22_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD22_SHIFT                  (7U)
+/*! BPHLCD22
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD22(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD22_SHIFT)) & LCD_WF8B_BPHLCD22_MASK)
+
+#define LCD_WF8B_BPHLCD23_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD23_SHIFT                  (7U)
+/*! BPHLCD23
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD23(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD23_SHIFT)) & LCD_WF8B_BPHLCD23_MASK)
+
+#define LCD_WF8B_BPHLCD24_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD24_SHIFT                  (7U)
+/*! BPHLCD24
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD24(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD24_SHIFT)) & LCD_WF8B_BPHLCD24_MASK)
+
+#define LCD_WF8B_BPHLCD25_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD25_SHIFT                  (7U)
+/*! BPHLCD25
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD25(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD25_SHIFT)) & LCD_WF8B_BPHLCD25_MASK)
+
+#define LCD_WF8B_BPHLCD26_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD26_SHIFT                  (7U)
+/*! BPHLCD26
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD26(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD26_SHIFT)) & LCD_WF8B_BPHLCD26_MASK)
+
+#define LCD_WF8B_BPHLCD27_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD27_SHIFT                  (7U)
+/*! BPHLCD27
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD27(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD27_SHIFT)) & LCD_WF8B_BPHLCD27_MASK)
+
+#define LCD_WF8B_BPHLCD28_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD28_SHIFT                  (7U)
+/*! BPHLCD28
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD28(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD28_SHIFT)) & LCD_WF8B_BPHLCD28_MASK)
+
+#define LCD_WF8B_BPHLCD29_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD29_SHIFT                  (7U)
+/*! BPHLCD29
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD29(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD29_SHIFT)) & LCD_WF8B_BPHLCD29_MASK)
+
+#define LCD_WF8B_BPHLCD30_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD30_SHIFT                  (7U)
+/*! BPHLCD30
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD30(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD30_SHIFT)) & LCD_WF8B_BPHLCD30_MASK)
+
+#define LCD_WF8B_BPHLCD31_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD31_SHIFT                  (7U)
+/*! BPHLCD31
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD31(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD31_SHIFT)) & LCD_WF8B_BPHLCD31_MASK)
+
+#define LCD_WF8B_BPHLCD32_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD32_SHIFT                  (7U)
+/*! BPHLCD32
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD32(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD32_SHIFT)) & LCD_WF8B_BPHLCD32_MASK)
+
+#define LCD_WF8B_BPHLCD33_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD33_SHIFT                  (7U)
+/*! BPHLCD33
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD33(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD33_SHIFT)) & LCD_WF8B_BPHLCD33_MASK)
+
+#define LCD_WF8B_BPHLCD34_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD34_SHIFT                  (7U)
+/*! BPHLCD34
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD34(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD34_SHIFT)) & LCD_WF8B_BPHLCD34_MASK)
+
+#define LCD_WF8B_BPHLCD35_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD35_SHIFT                  (7U)
+/*! BPHLCD35
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD35(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD35_SHIFT)) & LCD_WF8B_BPHLCD35_MASK)
+
+#define LCD_WF8B_BPHLCD36_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD36_SHIFT                  (7U)
+/*! BPHLCD36
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD36(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD36_SHIFT)) & LCD_WF8B_BPHLCD36_MASK)
+
+#define LCD_WF8B_BPHLCD37_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD37_SHIFT                  (7U)
+/*! BPHLCD37
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD37(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD37_SHIFT)) & LCD_WF8B_BPHLCD37_MASK)
+
+#define LCD_WF8B_BPHLCD38_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD38_SHIFT                  (7U)
+/*! BPHLCD38
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD38(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD38_SHIFT)) & LCD_WF8B_BPHLCD38_MASK)
+
+#define LCD_WF8B_BPHLCD39_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD39_SHIFT                  (7U)
+/*! BPHLCD39
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD39(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD39_SHIFT)) & LCD_WF8B_BPHLCD39_MASK)
+
+#define LCD_WF8B_BPHLCD40_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD40_SHIFT                  (7U)
+/*! BPHLCD40
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD40(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD40_SHIFT)) & LCD_WF8B_BPHLCD40_MASK)
+
+#define LCD_WF8B_BPHLCD41_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD41_SHIFT                  (7U)
+/*! BPHLCD41
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD41(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD41_SHIFT)) & LCD_WF8B_BPHLCD41_MASK)
+
+#define LCD_WF8B_BPHLCD42_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD42_SHIFT                  (7U)
+/*! BPHLCD42
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD42(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD42_SHIFT)) & LCD_WF8B_BPHLCD42_MASK)
+
+#define LCD_WF8B_BPHLCD43_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD43_SHIFT                  (7U)
+/*! BPHLCD43
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD43(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD43_SHIFT)) & LCD_WF8B_BPHLCD43_MASK)
+
+#define LCD_WF8B_BPHLCD44_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD44_SHIFT                  (7U)
+/*! BPHLCD44
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD44(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD44_SHIFT)) & LCD_WF8B_BPHLCD44_MASK)
+
+#define LCD_WF8B_BPHLCD45_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD45_SHIFT                  (7U)
+/*! BPHLCD45
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD45(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD45_SHIFT)) & LCD_WF8B_BPHLCD45_MASK)
+
+#define LCD_WF8B_BPHLCD46_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD46_SHIFT                  (7U)
+/*! BPHLCD46
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD46(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD46_SHIFT)) & LCD_WF8B_BPHLCD46_MASK)
+
+#define LCD_WF8B_BPHLCD47_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD47_SHIFT                  (7U)
+/*! BPHLCD47
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD47(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD47_SHIFT)) & LCD_WF8B_BPHLCD47_MASK)
+
+#define LCD_WF8B_BPHLCD48_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD48_SHIFT                  (7U)
+/*! BPHLCD48
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD48(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD48_SHIFT)) & LCD_WF8B_BPHLCD48_MASK)
+
+#define LCD_WF8B_BPHLCD49_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD49_SHIFT                  (7U)
+/*! BPHLCD49
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD49(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD49_SHIFT)) & LCD_WF8B_BPHLCD49_MASK)
+
+#define LCD_WF8B_BPHLCD50_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD50_SHIFT                  (7U)
+/*! BPHLCD50
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD50(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD50_SHIFT)) & LCD_WF8B_BPHLCD50_MASK)
+
+#define LCD_WF8B_BPHLCD51_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD51_SHIFT                  (7U)
+/*! BPHLCD51
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD51(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD51_SHIFT)) & LCD_WF8B_BPHLCD51_MASK)
+
+#define LCD_WF8B_BPHLCD52_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD52_SHIFT                  (7U)
+/*! BPHLCD52
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD52(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD52_SHIFT)) & LCD_WF8B_BPHLCD52_MASK)
+
+#define LCD_WF8B_BPHLCD53_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD53_SHIFT                  (7U)
+/*! BPHLCD53
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD53(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD53_SHIFT)) & LCD_WF8B_BPHLCD53_MASK)
+
+#define LCD_WF8B_BPHLCD54_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD54_SHIFT                  (7U)
+/*! BPHLCD54
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD54(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD54_SHIFT)) & LCD_WF8B_BPHLCD54_MASK)
+
+#define LCD_WF8B_BPHLCD55_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD55_SHIFT                  (7U)
+/*! BPHLCD55
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD55(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD55_SHIFT)) & LCD_WF8B_BPHLCD55_MASK)
+
+#define LCD_WF8B_BPHLCD56_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD56_SHIFT                  (7U)
+/*! BPHLCD56
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD56(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD56_SHIFT)) & LCD_WF8B_BPHLCD56_MASK)
+
+#define LCD_WF8B_BPHLCD57_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD57_SHIFT                  (7U)
+/*! BPHLCD57
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD57(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD57_SHIFT)) & LCD_WF8B_BPHLCD57_MASK)
+
+#define LCD_WF8B_BPHLCD58_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD58_SHIFT                  (7U)
+/*! BPHLCD58
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD58(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD58_SHIFT)) & LCD_WF8B_BPHLCD58_MASK)
+
+#define LCD_WF8B_BPHLCD59_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD59_SHIFT                  (7U)
+/*! BPHLCD59
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD59(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD59_SHIFT)) & LCD_WF8B_BPHLCD59_MASK)
+
+#define LCD_WF8B_BPHLCD60_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD60_SHIFT                  (7U)
+/*! BPHLCD60
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD60(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD60_SHIFT)) & LCD_WF8B_BPHLCD60_MASK)
+
+#define LCD_WF8B_BPHLCD61_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD61_SHIFT                  (7U)
+/*! BPHLCD61
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD61(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD61_SHIFT)) & LCD_WF8B_BPHLCD61_MASK)
+
+#define LCD_WF8B_BPHLCD62_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD62_SHIFT                  (7U)
+/*! BPHLCD62
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD62(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD62_SHIFT)) & LCD_WF8B_BPHLCD62_MASK)
+
+#define LCD_WF8B_BPHLCD63_MASK                   (0x80U)
+#define LCD_WF8B_BPHLCD63_SHIFT                  (7U)
+/*! BPHLCD63
+ *  0b0..LCD segment off or LCD backplane inactive for phase H
+ *  0b1..LCD segment on or LCD backplane active for phase H
+ */
+#define LCD_WF8B_BPHLCD63(x)                     (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPHLCD63_SHIFT)) & LCD_WF8B_BPHLCD63_MASK)
+/*! @} */
+
+/* The count of LCD_WF8B */
+#define LCD_WF8B_COUNT                           (64U)
+
+/*! @name WF - LCD Waveform register */
+/*! @{ */
+
+#define LCD_WF_WF0_MASK                          (0xFFU)
+#define LCD_WF_WF0_SHIFT                         (0U)
+#define LCD_WF_WF0(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF0_SHIFT)) & LCD_WF_WF0_MASK)
+
+#define LCD_WF_WF4_MASK                          (0xFFU)
+#define LCD_WF_WF4_SHIFT                         (0U)
+#define LCD_WF_WF4(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF4_SHIFT)) & LCD_WF_WF4_MASK)
+
+#define LCD_WF_WF8_MASK                          (0xFFU)
+#define LCD_WF_WF8_SHIFT                         (0U)
+#define LCD_WF_WF8(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF8_SHIFT)) & LCD_WF_WF8_MASK)
+
+#define LCD_WF_WF12_MASK                         (0xFFU)
+#define LCD_WF_WF12_SHIFT                        (0U)
+#define LCD_WF_WF12(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF12_SHIFT)) & LCD_WF_WF12_MASK)
+
+#define LCD_WF_WF16_MASK                         (0xFFU)
+#define LCD_WF_WF16_SHIFT                        (0U)
+#define LCD_WF_WF16(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF16_SHIFT)) & LCD_WF_WF16_MASK)
+
+#define LCD_WF_WF20_MASK                         (0xFFU)
+#define LCD_WF_WF20_SHIFT                        (0U)
+#define LCD_WF_WF20(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF20_SHIFT)) & LCD_WF_WF20_MASK)
+
+#define LCD_WF_WF24_MASK                         (0xFFU)
+#define LCD_WF_WF24_SHIFT                        (0U)
+#define LCD_WF_WF24(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF24_SHIFT)) & LCD_WF_WF24_MASK)
+
+#define LCD_WF_WF28_MASK                         (0xFFU)
+#define LCD_WF_WF28_SHIFT                        (0U)
+#define LCD_WF_WF28(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF28_SHIFT)) & LCD_WF_WF28_MASK)
+
+#define LCD_WF_WF32_MASK                         (0xFFU)
+#define LCD_WF_WF32_SHIFT                        (0U)
+#define LCD_WF_WF32(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF32_SHIFT)) & LCD_WF_WF32_MASK)
+
+#define LCD_WF_WF36_MASK                         (0xFFU)
+#define LCD_WF_WF36_SHIFT                        (0U)
+#define LCD_WF_WF36(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF36_SHIFT)) & LCD_WF_WF36_MASK)
+
+#define LCD_WF_WF40_MASK                         (0xFFU)
+#define LCD_WF_WF40_SHIFT                        (0U)
+#define LCD_WF_WF40(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF40_SHIFT)) & LCD_WF_WF40_MASK)
+
+#define LCD_WF_WF44_MASK                         (0xFFU)
+#define LCD_WF_WF44_SHIFT                        (0U)
+#define LCD_WF_WF44(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF44_SHIFT)) & LCD_WF_WF44_MASK)
+
+#define LCD_WF_WF48_MASK                         (0xFFU)
+#define LCD_WF_WF48_SHIFT                        (0U)
+#define LCD_WF_WF48(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF48_SHIFT)) & LCD_WF_WF48_MASK)
+
+#define LCD_WF_WF52_MASK                         (0xFFU)
+#define LCD_WF_WF52_SHIFT                        (0U)
+#define LCD_WF_WF52(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF52_SHIFT)) & LCD_WF_WF52_MASK)
+
+#define LCD_WF_WF56_MASK                         (0xFFU)
+#define LCD_WF_WF56_SHIFT                        (0U)
+#define LCD_WF_WF56(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF56_SHIFT)) & LCD_WF_WF56_MASK)
+
+#define LCD_WF_WF60_MASK                         (0xFFU)
+#define LCD_WF_WF60_SHIFT                        (0U)
+#define LCD_WF_WF60(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF60_SHIFT)) & LCD_WF_WF60_MASK)
+
+#define LCD_WF_WF1_MASK                          (0xFF00U)
+#define LCD_WF_WF1_SHIFT                         (8U)
+#define LCD_WF_WF1(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF1_SHIFT)) & LCD_WF_WF1_MASK)
+
+#define LCD_WF_WF5_MASK                          (0xFF00U)
+#define LCD_WF_WF5_SHIFT                         (8U)
+#define LCD_WF_WF5(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF5_SHIFT)) & LCD_WF_WF5_MASK)
+
+#define LCD_WF_WF9_MASK                          (0xFF00U)
+#define LCD_WF_WF9_SHIFT                         (8U)
+#define LCD_WF_WF9(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF9_SHIFT)) & LCD_WF_WF9_MASK)
+
+#define LCD_WF_WF13_MASK                         (0xFF00U)
+#define LCD_WF_WF13_SHIFT                        (8U)
+#define LCD_WF_WF13(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF13_SHIFT)) & LCD_WF_WF13_MASK)
+
+#define LCD_WF_WF17_MASK                         (0xFF00U)
+#define LCD_WF_WF17_SHIFT                        (8U)
+#define LCD_WF_WF17(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF17_SHIFT)) & LCD_WF_WF17_MASK)
+
+#define LCD_WF_WF21_MASK                         (0xFF00U)
+#define LCD_WF_WF21_SHIFT                        (8U)
+#define LCD_WF_WF21(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF21_SHIFT)) & LCD_WF_WF21_MASK)
+
+#define LCD_WF_WF25_MASK                         (0xFF00U)
+#define LCD_WF_WF25_SHIFT                        (8U)
+#define LCD_WF_WF25(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF25_SHIFT)) & LCD_WF_WF25_MASK)
+
+#define LCD_WF_WF29_MASK                         (0xFF00U)
+#define LCD_WF_WF29_SHIFT                        (8U)
+#define LCD_WF_WF29(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF29_SHIFT)) & LCD_WF_WF29_MASK)
+
+#define LCD_WF_WF33_MASK                         (0xFF00U)
+#define LCD_WF_WF33_SHIFT                        (8U)
+#define LCD_WF_WF33(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF33_SHIFT)) & LCD_WF_WF33_MASK)
+
+#define LCD_WF_WF37_MASK                         (0xFF00U)
+#define LCD_WF_WF37_SHIFT                        (8U)
+#define LCD_WF_WF37(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF37_SHIFT)) & LCD_WF_WF37_MASK)
+
+#define LCD_WF_WF41_MASK                         (0xFF00U)
+#define LCD_WF_WF41_SHIFT                        (8U)
+#define LCD_WF_WF41(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF41_SHIFT)) & LCD_WF_WF41_MASK)
+
+#define LCD_WF_WF45_MASK                         (0xFF00U)
+#define LCD_WF_WF45_SHIFT                        (8U)
+#define LCD_WF_WF45(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF45_SHIFT)) & LCD_WF_WF45_MASK)
+
+#define LCD_WF_WF49_MASK                         (0xFF00U)
+#define LCD_WF_WF49_SHIFT                        (8U)
+#define LCD_WF_WF49(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF49_SHIFT)) & LCD_WF_WF49_MASK)
+
+#define LCD_WF_WF53_MASK                         (0xFF00U)
+#define LCD_WF_WF53_SHIFT                        (8U)
+#define LCD_WF_WF53(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF53_SHIFT)) & LCD_WF_WF53_MASK)
+
+#define LCD_WF_WF57_MASK                         (0xFF00U)
+#define LCD_WF_WF57_SHIFT                        (8U)
+#define LCD_WF_WF57(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF57_SHIFT)) & LCD_WF_WF57_MASK)
+
+#define LCD_WF_WF61_MASK                         (0xFF00U)
+#define LCD_WF_WF61_SHIFT                        (8U)
+#define LCD_WF_WF61(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF61_SHIFT)) & LCD_WF_WF61_MASK)
+
+#define LCD_WF_WF2_MASK                          (0xFF0000U)
+#define LCD_WF_WF2_SHIFT                         (16U)
+#define LCD_WF_WF2(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF2_SHIFT)) & LCD_WF_WF2_MASK)
+
+#define LCD_WF_WF6_MASK                          (0xFF0000U)
+#define LCD_WF_WF6_SHIFT                         (16U)
+#define LCD_WF_WF6(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF6_SHIFT)) & LCD_WF_WF6_MASK)
+
+#define LCD_WF_WF10_MASK                         (0xFF0000U)
+#define LCD_WF_WF10_SHIFT                        (16U)
+#define LCD_WF_WF10(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF10_SHIFT)) & LCD_WF_WF10_MASK)
+
+#define LCD_WF_WF14_MASK                         (0xFF0000U)
+#define LCD_WF_WF14_SHIFT                        (16U)
+#define LCD_WF_WF14(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF14_SHIFT)) & LCD_WF_WF14_MASK)
+
+#define LCD_WF_WF18_MASK                         (0xFF0000U)
+#define LCD_WF_WF18_SHIFT                        (16U)
+#define LCD_WF_WF18(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF18_SHIFT)) & LCD_WF_WF18_MASK)
+
+#define LCD_WF_WF22_MASK                         (0xFF0000U)
+#define LCD_WF_WF22_SHIFT                        (16U)
+#define LCD_WF_WF22(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF22_SHIFT)) & LCD_WF_WF22_MASK)
+
+#define LCD_WF_WF26_MASK                         (0xFF0000U)
+#define LCD_WF_WF26_SHIFT                        (16U)
+#define LCD_WF_WF26(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF26_SHIFT)) & LCD_WF_WF26_MASK)
+
+#define LCD_WF_WF30_MASK                         (0xFF0000U)
+#define LCD_WF_WF30_SHIFT                        (16U)
+#define LCD_WF_WF30(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF30_SHIFT)) & LCD_WF_WF30_MASK)
+
+#define LCD_WF_WF34_MASK                         (0xFF0000U)
+#define LCD_WF_WF34_SHIFT                        (16U)
+#define LCD_WF_WF34(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF34_SHIFT)) & LCD_WF_WF34_MASK)
+
+#define LCD_WF_WF38_MASK                         (0xFF0000U)
+#define LCD_WF_WF38_SHIFT                        (16U)
+#define LCD_WF_WF38(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF38_SHIFT)) & LCD_WF_WF38_MASK)
+
+#define LCD_WF_WF42_MASK                         (0xFF0000U)
+#define LCD_WF_WF42_SHIFT                        (16U)
+#define LCD_WF_WF42(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF42_SHIFT)) & LCD_WF_WF42_MASK)
+
+#define LCD_WF_WF46_MASK                         (0xFF0000U)
+#define LCD_WF_WF46_SHIFT                        (16U)
+#define LCD_WF_WF46(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF46_SHIFT)) & LCD_WF_WF46_MASK)
+
+#define LCD_WF_WF50_MASK                         (0xFF0000U)
+#define LCD_WF_WF50_SHIFT                        (16U)
+#define LCD_WF_WF50(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF50_SHIFT)) & LCD_WF_WF50_MASK)
+
+#define LCD_WF_WF54_MASK                         (0xFF0000U)
+#define LCD_WF_WF54_SHIFT                        (16U)
+#define LCD_WF_WF54(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF54_SHIFT)) & LCD_WF_WF54_MASK)
+
+#define LCD_WF_WF58_MASK                         (0xFF0000U)
+#define LCD_WF_WF58_SHIFT                        (16U)
+#define LCD_WF_WF58(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF58_SHIFT)) & LCD_WF_WF58_MASK)
+
+#define LCD_WF_WF62_MASK                         (0xFF0000U)
+#define LCD_WF_WF62_SHIFT                        (16U)
+#define LCD_WF_WF62(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF62_SHIFT)) & LCD_WF_WF62_MASK)
+
+#define LCD_WF_WF3_MASK                          (0xFF000000U)
+#define LCD_WF_WF3_SHIFT                         (24U)
+#define LCD_WF_WF3(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF3_SHIFT)) & LCD_WF_WF3_MASK)
+
+#define LCD_WF_WF7_MASK                          (0xFF000000U)
+#define LCD_WF_WF7_SHIFT                         (24U)
+#define LCD_WF_WF7(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF7_SHIFT)) & LCD_WF_WF7_MASK)
+
+#define LCD_WF_WF11_MASK                         (0xFF000000U)
+#define LCD_WF_WF11_SHIFT                        (24U)
+#define LCD_WF_WF11(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF11_SHIFT)) & LCD_WF_WF11_MASK)
+
+#define LCD_WF_WF15_MASK                         (0xFF000000U)
+#define LCD_WF_WF15_SHIFT                        (24U)
+#define LCD_WF_WF15(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF15_SHIFT)) & LCD_WF_WF15_MASK)
+
+#define LCD_WF_WF19_MASK                         (0xFF000000U)
+#define LCD_WF_WF19_SHIFT                        (24U)
+#define LCD_WF_WF19(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF19_SHIFT)) & LCD_WF_WF19_MASK)
+
+#define LCD_WF_WF23_MASK                         (0xFF000000U)
+#define LCD_WF_WF23_SHIFT                        (24U)
+#define LCD_WF_WF23(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF23_SHIFT)) & LCD_WF_WF23_MASK)
+
+#define LCD_WF_WF27_MASK                         (0xFF000000U)
+#define LCD_WF_WF27_SHIFT                        (24U)
+#define LCD_WF_WF27(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF27_SHIFT)) & LCD_WF_WF27_MASK)
+
+#define LCD_WF_WF31_MASK                         (0xFF000000U)
+#define LCD_WF_WF31_SHIFT                        (24U)
+#define LCD_WF_WF31(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF31_SHIFT)) & LCD_WF_WF31_MASK)
+
+#define LCD_WF_WF35_MASK                         (0xFF000000U)
+#define LCD_WF_WF35_SHIFT                        (24U)
+#define LCD_WF_WF35(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF35_SHIFT)) & LCD_WF_WF35_MASK)
+
+#define LCD_WF_WF39_MASK                         (0xFF000000U)
+#define LCD_WF_WF39_SHIFT                        (24U)
+#define LCD_WF_WF39(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF39_SHIFT)) & LCD_WF_WF39_MASK)
+
+#define LCD_WF_WF43_MASK                         (0xFF000000U)
+#define LCD_WF_WF43_SHIFT                        (24U)
+#define LCD_WF_WF43(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF43_SHIFT)) & LCD_WF_WF43_MASK)
+
+#define LCD_WF_WF47_MASK                         (0xFF000000U)
+#define LCD_WF_WF47_SHIFT                        (24U)
+#define LCD_WF_WF47(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF47_SHIFT)) & LCD_WF_WF47_MASK)
+
+#define LCD_WF_WF51_MASK                         (0xFF000000U)
+#define LCD_WF_WF51_SHIFT                        (24U)
+#define LCD_WF_WF51(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF51_SHIFT)) & LCD_WF_WF51_MASK)
+
+#define LCD_WF_WF55_MASK                         (0xFF000000U)
+#define LCD_WF_WF55_SHIFT                        (24U)
+#define LCD_WF_WF55(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF55_SHIFT)) & LCD_WF_WF55_MASK)
+
+#define LCD_WF_WF59_MASK                         (0xFF000000U)
+#define LCD_WF_WF59_SHIFT                        (24U)
+#define LCD_WF_WF59(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF59_SHIFT)) & LCD_WF_WF59_MASK)
+
+#define LCD_WF_WF63_MASK                         (0xFF000000U)
+#define LCD_WF_WF63_SHIFT                        (24U)
+#define LCD_WF_WF63(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF63_SHIFT)) & LCD_WF_WF63_MASK)
+/*! @} */
+
+/* The count of LCD_WF */
+#define LCD_WF_COUNT                             (16U)
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE                                 (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD                                      ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS                           { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS                            { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_LCD_IRQS                             { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+/*! @{ */
+
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+/*! @} */
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+/*! @{ */
+
+#define LLWU_PE2_WUPE4_MASK                      (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT                     (0U)
+/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+
+#define LLWU_PE2_WUPE5_MASK                      (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT                     (2U)
+/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+
+#define LLWU_PE2_WUPE6_MASK                      (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT                     (4U)
+/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+
+#define LLWU_PE2_WUPE7_MASK                      (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT                     (6U)
+/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+/*! @} */
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+/*! @{ */
+
+#define LLWU_PE3_WUPE8_MASK                      (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT                     (0U)
+/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+
+#define LLWU_PE3_WUPE9_MASK                      (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT                     (2U)
+/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+
+#define LLWU_PE3_WUPE10_MASK                     (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT                    (4U)
+/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+
+#define LLWU_PE3_WUPE11_MASK                     (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT                    (6U)
+/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+/*! @} */
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+/*! @{ */
+
+#define LLWU_PE4_WUPE12_MASK                     (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT                    (0U)
+/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+
+#define LLWU_PE4_WUPE13_MASK                     (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT                    (2U)
+/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+
+#define LLWU_PE4_WUPE14_MASK                     (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT                    (4U)
+/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+
+#define LLWU_PE4_WUPE15_MASK                     (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT                    (6U)
+/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection
+ *  0b10..External input pin enabled with falling edge detection
+ *  0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+/*! @} */
+
+/*! @name ME - LLWU Module Enable register */
+/*! @{ */
+
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+/*! WUME0 - Wakeup Module Enable For Module 0
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+/*! WUME1 - Wakeup Module Enable for Module 1
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+/*! WUME2 - Wakeup Module Enable For Module 2
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+/*! WUME3 - Wakeup Module Enable For Module 3
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+
+#define LLWU_ME_WUME4_MASK                       (0x10U)
+#define LLWU_ME_WUME4_SHIFT                      (4U)
+/*! WUME4 - Wakeup Module Enable For Module 4
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+/*! WUME5 - Wakeup Module Enable For Module 5
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+/*! WUME6 - Wakeup Module Enable For Module 6
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+/*! WUME7 - Wakeup Module Enable For Module 7
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+/*! @} */
+
+/*! @name F1 - LLWU Flag 1 register */
+/*! @{ */
+
+#define LLWU_F1_WUF0_MASK                        (0x1U)
+#define LLWU_F1_WUF0_SHIFT                       (0U)
+/*! WUF0 - Wakeup Flag For LLWU_P0
+ *  0b0..LLWU_P0 input was not a wakeup source
+ *  0b1..LLWU_P0 input was a wakeup source
+ */
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+
+#define LLWU_F1_WUF1_MASK                        (0x2U)
+#define LLWU_F1_WUF1_SHIFT                       (1U)
+/*! WUF1 - Wakeup Flag For LLWU_P1
+ *  0b0..LLWU_P1 input was not a wakeup source
+ *  0b1..LLWU_P1 input was a wakeup source
+ */
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+
+#define LLWU_F1_WUF2_MASK                        (0x4U)
+#define LLWU_F1_WUF2_SHIFT                       (2U)
+/*! WUF2 - Wakeup Flag For LLWU_P2
+ *  0b0..LLWU_P2 input was not a wakeup source
+ *  0b1..LLWU_P2 input was a wakeup source
+ */
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+
+#define LLWU_F1_WUF3_MASK                        (0x8U)
+#define LLWU_F1_WUF3_SHIFT                       (3U)
+/*! WUF3 - Wakeup Flag For LLWU_P3
+ *  0b0..LLWU_P3 input was not a wake-up source
+ *  0b1..LLWU_P3 input was a wake-up source
+ */
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+
+#define LLWU_F1_WUF4_MASK                        (0x10U)
+#define LLWU_F1_WUF4_SHIFT                       (4U)
+/*! WUF4 - Wakeup Flag For LLWU_P4
+ *  0b0..LLWU_P4 input was not a wakeup source
+ *  0b1..LLWU_P4 input was a wakeup source
+ */
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+
+#define LLWU_F1_WUF5_MASK                        (0x20U)
+#define LLWU_F1_WUF5_SHIFT                       (5U)
+/*! WUF5 - Wakeup Flag For LLWU_P5
+ *  0b0..LLWU_P5 input was not a wakeup source
+ *  0b1..LLWU_P5 input was a wakeup source
+ */
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+
+#define LLWU_F1_WUF6_MASK                        (0x40U)
+#define LLWU_F1_WUF6_SHIFT                       (6U)
+/*! WUF6 - Wakeup Flag For LLWU_P6
+ *  0b0..LLWU_P6 input was not a wakeup source
+ *  0b1..LLWU_P6 input was a wakeup source
+ */
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+
+#define LLWU_F1_WUF7_MASK                        (0x80U)
+#define LLWU_F1_WUF7_SHIFT                       (7U)
+/*! WUF7 - Wakeup Flag For LLWU_P7
+ *  0b0..LLWU_P7 input was not a wakeup source
+ *  0b1..LLWU_P7 input was a wakeup source
+ */
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+/*! @} */
+
+/*! @name F2 - LLWU Flag 2 register */
+/*! @{ */
+
+#define LLWU_F2_WUF8_MASK                        (0x1U)
+#define LLWU_F2_WUF8_SHIFT                       (0U)
+/*! WUF8 - Wakeup Flag For LLWU_P8
+ *  0b0..LLWU_P8 input was not a wakeup source
+ *  0b1..LLWU_P8 input was a wakeup source
+ */
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+
+#define LLWU_F2_WUF9_MASK                        (0x2U)
+#define LLWU_F2_WUF9_SHIFT                       (1U)
+/*! WUF9 - Wakeup Flag For LLWU_P9
+ *  0b0..LLWU_P9 input was not a wakeup source
+ *  0b1..LLWU_P9 input was a wakeup source
+ */
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+
+#define LLWU_F2_WUF10_MASK                       (0x4U)
+#define LLWU_F2_WUF10_SHIFT                      (2U)
+/*! WUF10 - Wakeup Flag For LLWU_P10
+ *  0b0..LLWU_P10 input was not a wakeup source
+ *  0b1..LLWU_P10 input was a wakeup source
+ */
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+
+#define LLWU_F2_WUF11_MASK                       (0x8U)
+#define LLWU_F2_WUF11_SHIFT                      (3U)
+/*! WUF11 - Wakeup Flag For LLWU_P11
+ *  0b0..LLWU_P11 input was not a wakeup source
+ *  0b1..LLWU_P11 input was a wakeup source
+ */
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+
+#define LLWU_F2_WUF12_MASK                       (0x10U)
+#define LLWU_F2_WUF12_SHIFT                      (4U)
+/*! WUF12 - Wakeup Flag For LLWU_P12
+ *  0b0..LLWU_P12 input was not a wakeup source
+ *  0b1..LLWU_P12 input was a wakeup source
+ */
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+
+#define LLWU_F2_WUF13_MASK                       (0x20U)
+#define LLWU_F2_WUF13_SHIFT                      (5U)
+/*! WUF13 - Wakeup Flag For LLWU_P13
+ *  0b0..LLWU_P13 input was not a wakeup source
+ *  0b1..LLWU_P13 input was a wakeup source
+ */
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+
+#define LLWU_F2_WUF14_MASK                       (0x40U)
+#define LLWU_F2_WUF14_SHIFT                      (6U)
+/*! WUF14 - Wakeup Flag For LLWU_P14
+ *  0b0..LLWU_P14 input was not a wakeup source
+ *  0b1..LLWU_P14 input was a wakeup source
+ */
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+
+#define LLWU_F2_WUF15_MASK                       (0x80U)
+#define LLWU_F2_WUF15_SHIFT                      (7U)
+/*! WUF15 - Wakeup Flag For LLWU_P15
+ *  0b0..LLWU_P15 input was not a wakeup source
+ *  0b1..LLWU_P15 input was a wakeup source
+ */
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+/*! @} */
+
+/*! @name F3 - LLWU Flag 3 register */
+/*! @{ */
+
+#define LLWU_F3_MWUF0_MASK                       (0x1U)
+#define LLWU_F3_MWUF0_SHIFT                      (0U)
+/*! MWUF0 - Wakeup flag For module 0
+ *  0b0..Module 0 input was not a wakeup source
+ *  0b1..Module 0 input was a wakeup source
+ */
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+
+#define LLWU_F3_MWUF1_MASK                       (0x2U)
+#define LLWU_F3_MWUF1_SHIFT                      (1U)
+/*! MWUF1 - Wakeup flag For module 1
+ *  0b0..Module 1 input was not a wakeup source
+ *  0b1..Module 1 input was a wakeup source
+ */
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+
+#define LLWU_F3_MWUF2_MASK                       (0x4U)
+#define LLWU_F3_MWUF2_SHIFT                      (2U)
+/*! MWUF2 - Wakeup flag For module 2
+ *  0b0..Module 2 input was not a wakeup source
+ *  0b1..Module 2 input was a wakeup source
+ */
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+
+#define LLWU_F3_MWUF3_MASK                       (0x8U)
+#define LLWU_F3_MWUF3_SHIFT                      (3U)
+/*! MWUF3 - Wakeup flag For module 3
+ *  0b0..Module 3 input was not a wakeup source
+ *  0b1..Module 3 input was a wakeup source
+ */
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+
+#define LLWU_F3_MWUF4_MASK                       (0x10U)
+#define LLWU_F3_MWUF4_SHIFT                      (4U)
+/*! MWUF4 - Wakeup flag For module 4
+ *  0b0..Module 4 input was not a wakeup source
+ *  0b1..Module 4 input was a wakeup source
+ */
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+
+#define LLWU_F3_MWUF5_MASK                       (0x20U)
+#define LLWU_F3_MWUF5_SHIFT                      (5U)
+/*! MWUF5 - Wakeup flag For module 5
+ *  0b0..Module 5 input was not a wakeup source
+ *  0b1..Module 5 input was a wakeup source
+ */
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+
+#define LLWU_F3_MWUF6_MASK                       (0x40U)
+#define LLWU_F3_MWUF6_SHIFT                      (6U)
+/*! MWUF6 - Wakeup flag For module 6
+ *  0b0..Module 6 input was not a wakeup source
+ *  0b1..Module 6 input was a wakeup source
+ */
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+
+#define LLWU_F3_MWUF7_MASK                       (0x80U)
+#define LLWU_F3_MWUF7_SHIFT                      (7U)
+/*! MWUF7 - Wakeup flag For module 7
+ *  0b0..Module 7 input was not a wakeup source
+ *  0b1..Module 7 input was a wakeup source
+ */
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+/*! @} */
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+/*! @{ */
+
+#define LLWU_FILT1_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
+/*! FILTSEL - Filter Pin Select
+ *  0b0000..Select LLWU_P0 for filter
+ *  0b1111..Select LLWU_P15 for filter
+ */
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+
+#define LLWU_FILT1_FILTE_MASK                    (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT                   (5U)
+/*! FILTE - Digital Filter On External Pin
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled
+ *  0b10..Filter negedge detect enabled
+ *  0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+
+#define LLWU_FILT1_FILTF_MASK                    (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT                   (7U)
+/*! FILTF - Filter Detect Flag
+ *  0b0..Pin Filter 1 was not a wakeup source
+ *  0b1..Pin Filter 1 was a wakeup source
+ */
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+/*! @} */
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+/*! @{ */
+
+#define LLWU_FILT2_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
+/*! FILTSEL - Filter Pin Select
+ *  0b0000..Select LLWU_P0 for filter
+ *  0b1111..Select LLWU_P15 for filter
+ */
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+
+#define LLWU_FILT2_FILTE_MASK                    (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT                   (5U)
+/*! FILTE - Digital Filter On External Pin
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled
+ *  0b10..Filter negedge detect enabled
+ *  0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+
+#define LLWU_FILT2_FILTF_MASK                    (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT                   (7U)
+/*! FILTF - Filter Detect Flag
+ *  0b0..Pin Filter 2 was not a wakeup source
+ *  0b1..Pin Filter 2 was a wakeup source
+ */
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+/*! @{ */
+
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..LPTMR is disabled and internal logic is reset.
+ *  0b1..LPTMR is enabled.
+ */
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+/*! TMS - Timer Mode Select
+ *  0b0..Time Counter mode.
+ *  0b1..Pulse Counter mode.
+ */
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+/*! TFC - Timer Free-Running Counter
+ *  0b0..CNR is reset whenever TCF is set.
+ *  0b1..CNR is reset on overflow.
+ */
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+/*! TPP - Timer Pin Polarity
+ *  0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
+ *  0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
+ */
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+/*! TPS - Timer Pin Select
+ *  0b00..Pulse counter input 0 is selected.
+ *  0b01..Pulse counter input 1 is selected.
+ *  0b10..Pulse counter input 2 is selected.
+ *  0b11..Pulse counter input 3 is selected.
+ */
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Timer interrupt disabled.
+ *  0b1..Timer interrupt enabled.
+ */
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+/*! TCF - Timer Compare Flag
+ *  0b0..The value of CNR is not equal to CMR and increments.
+ *  0b1..The value of CNR is equal to CMR and increments.
+ */
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+/*! @} */
+
+/*! @name PSR - Low Power Timer Prescale Register */
+/*! @{ */
+
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+/*! PCS - Prescaler Clock Select
+ *  0b00..Prescaler/glitch filter clock 0 selected.
+ *  0b01..Prescaler/glitch filter clock 1 selected.
+ *  0b10..Prescaler/glitch filter clock 2 selected.
+ *  0b11..Prescaler/glitch filter clock 3 selected.
+ */
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+/*! PBYP - Prescaler Bypass
+ *  0b0..Prescaler/glitch filter is enabled.
+ *  0b1..Prescaler/glitch filter is bypassed.
+ */
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+/*! PRESCALE - Prescale Value
+ *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
+ *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
+ *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
+ *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
+ *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
+ *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
+ *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
+ *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
+ *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
+ *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
+ *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
+ *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
+ *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
+ *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
+ *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
+ *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
+ */
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name CMR - Low Power Timer Compare Register */
+/*! @{ */
+
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+/*! COMPARE - Compare Value */
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+/*! @} */
+
+/*! @name CNR - Low Power Timer Counter Register */
+/*! @{ */
+
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+/*! COUNTER - Counter Value */
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+/*! @{ */
+
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+/*! SBR - Baud Rate Modulo Divisor. */
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+/*! SBNS - Stop Bit Number Select
+ *  0b0..One stop bit.
+ *  0b1..Two stop bits.
+ */
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
+ *  0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
+ */
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
+ *  0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
+ */
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ *  0b0..Resynchronization during received data word is supported
+ *  0b1..Resynchronization during received data word is disabled
+ */
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
+ *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
+ */
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+/*! MATCFG - Match Configuration
+ *  0b00..Address Match Wakeup
+ *  0b01..Idle Match Wakeup
+ *  0b10..Match On and Match Off
+ *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+/*! TDMAE - Transmitter DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+/*! OSR - Over Sampling Ratio */
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+/*! M10 - 10-bit Mode select
+ *  0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
+ *  0b1..Receiver and transmitter use 10-bit data characters.
+ */
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+/*! @} */
+
+/*! @name STAT - LPUART Status Register */
+/*! @{ */
+
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+/*! MA2F - Match 2 Flag
+ *  0b0..Received data is not equal to MA2
+ *  0b1..Received data is equal to MA2
+ */
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+/*! MA1F - Match 1 Flag
+ *  0b0..Received data is not equal to MA1
+ *  0b1..Received data is equal to MA1
+ */
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+/*! PF - Parity Error Flag
+ *  0b0..No parity error.
+ *  0b1..Parity error.
+ */
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+/*! FE - Framing Error Flag
+ *  0b0..No framing error detected. This does not guarantee the framing is correct.
+ *  0b1..Framing error.
+ */
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+/*! NF - Noise Flag
+ *  0b0..No noise detected.
+ *  0b1..Noise detected in the received character in LPUART_DATA.
+ */
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No overrun.
+ *  0b1..Receive overrun (new LPUART data lost).
+ */
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+/*! IDLE - Idle Line Flag
+ *  0b0..No idle line detected.
+ *  0b1..Idle line was detected.
+ */
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..Receive data buffer empty.
+ *  0b1..Receive data buffer full.
+ */
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+/*! TC - Transmission Complete Flag
+ *  0b0..Transmitter active (sending data, a preamble, or a break).
+ *  0b1..Transmitter idle (transmission activity complete).
+ */
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..Transmit data buffer full.
+ *  0b1..Transmit data buffer empty.
+ */
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+/*! RAF - Receiver Active Flag
+ *  0b0..LPUART receiver idle waiting for a start bit.
+ *  0b1..LPUART receiver active (LPUART_RX input not idle).
+ */
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+/*! LBKDE - LIN Break Detection Enable
+ *  0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M =
+ *       0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ *  0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M
+ *       = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
+ */
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+/*! BRK13 - Break Character Generation Length
+ *  0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0
+ *       or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ *  0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0
+ *       or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
+ */
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
+ *       character. During address match wakeup, the IDLE bit does not get set when an address does not match.
+ *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
+ *       address match wakeup, the IDLE bit does get set when an address does not match.
+ */
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Receive data not inverted.
+ *  0b1..Receive data inverted.
+ */
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+/*! MSBF - MSB First
+ *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
+ *       after the start bit is identified as bit0.
+ *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
+ *       the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
+ *       identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
+ */
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+/*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
+ *  0b0..No active edge on the receive pin has occurred.
+ *  0b1..An active edge on the receive pin has occurred.
+ */
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ *  0b0..No LIN break character has been detected.
+ *  0b1..LIN break character has been detected.
+ */
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+/*! @} */
+
+/*! @name CTRL - LPUART Control Register */
+/*! @{ */
+
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity.
+ *  0b1..Odd parity.
+ */
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+/*! PE - Parity Enable
+ *  0b0..No hardware parity generation or checking.
+ *  0b1..Parity enabled.
+ */
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..Idle character bit count starts after start bit.
+ *  0b1..Idle character bit count starts after stop bit.
+ */
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ *  0b0..Configures RWU for idle-line wakeup.
+ *  0b1..Configures RWU with address-mark wakeup.
+ */
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+/*! M - 9-Bit or 8-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit data characters.
+ *  0b1..Receiver and transmitter use 9-bit data characters.
+ */
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
+ *  0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
+ */
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+/*! DOZEEN - Doze Enable
+ *  0b0..LPUART is enabled in Doze mode.
+ *  0b1..LPUART is disabled in Doze mode.
+ */
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
+ *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
+ */
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+/*! IDLECFG - Idle Configuration
+ *  0b000..1 idle character
+ *  0b001..2 idle characters
+ *  0b010..4 idle characters
+ *  0b011..8 idle characters
+ *  0b100..16 idle characters
+ *  0b101..32 idle characters
+ *  0b110..64 idle characters
+ *  0b111..128 idle characters
+ */
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+/*! MA2IE - Match 2 Interrupt Enable
+ *  0b0..MA2F interrupt disabled
+ *  0b1..MA2F interrupt enabled
+ */
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+/*! MA1IE - Match 1 Interrupt Enable
+ *  0b0..MA1F interrupt disabled
+ *  0b1..MA1F interrupt enabled
+ */
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation.
+ *  0b1..Queue break character(s) to be sent.
+ */
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+/*! RWU - Receiver Wakeup Control
+ *  0b0..Normal receiver operation.
+ *  0b1..LPUART receiver in standby waiting for wakeup condition.
+ */
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver disabled.
+ *  0b1..Receiver enabled.
+ */
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter disabled.
+ *  0b1..Transmitter enabled.
+ */
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..Hardware interrupts from IDLE disabled; use polling.
+ *  0b1..Hardware interrupt requested when IDLE flag is 1.
+ */
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+/*! RIE - Receiver Interrupt Enable
+ *  0b0..Hardware interrupts from RDRF disabled; use polling.
+ *  0b1..Hardware interrupt requested when RDRF flag is 1.
+ */
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+/*! TCIE - Transmission Complete Interrupt Enable for
+ *  0b0..Hardware interrupts from TC disabled; use polling.
+ *  0b1..Hardware interrupt requested when TC flag is 1.
+ */
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+/*! TIE - Transmit Interrupt Enable
+ *  0b0..Hardware interrupts from TDRE disabled; use polling.
+ *  0b1..Hardware interrupt requested when TDRE flag is 1.
+ */
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..PF interrupts disabled; use polling).
+ *  0b1..Hardware interrupt requested when PF is set.
+ */
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..FE interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when FE is set.
+ */
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..NF interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when NF is set.
+ */
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+/*! ORIE - Overrun Interrupt Enable
+ *  0b0..OR interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when OR is set.
+ */
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+/*! TXINV - Transmit Data Inversion
+ *  0b0..Transmit data not inverted.
+ *  0b1..Transmit data inverted.
+ */
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+/*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
+ *  0b0..LPUART_TX pin is an input in single-wire mode.
+ *  0b1..LPUART_TX pin is an output in single-wire mode.
+ */
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+/*! R9T8 - Receive Bit 9 / Transmit Bit 8 */
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+/*! R8T9 - Receive Bit 8 / Transmit Bit 9 */
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+/*! @} */
+
+/*! @name DATA - LPUART Data Register */
+/*! @{ */
+
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+/*! IDLINE - Idle Line
+ *  0b0..Receiver was not idle before receiving this character.
+ *  0b1..Receiver was idle before receiving this character.
+ */
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+/*! RXEMPT - Receive Buffer Empty
+ *  0b0..Receive buffer contains valid data.
+ *  0b1..Receive buffer is empty, data returned on read is not valid.
+ */
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+/*! FRETSC - Frame Error / Transmit Special Character
+ *  0b0..The dataword was received without a frame error on read, transmit a normal character on write.
+ *  0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
+ */
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+/*! PARITYE
+ *  0b0..The dataword was received without a parity error.
+ *  0b1..The dataword was received with a parity error.
+ */
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+/*! NOISY
+ *  0b0..The dataword was received without noise.
+ *  0b1..The data was received with noise.
+ */
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+/*! @} */
+
+/*! @name MATCH - LPUART Match Address Register */
+/*! @{ */
+
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+/*! MA1 - Match Address 1 */
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+/*! MA2 - Match Address 2 */
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x40054000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x40055000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control Register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control Register 2, offset: 0x1 */
+       uint8_t RESERVED_0[4];
+  __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_2[11];
+  __I  uint8_t HCTRIM;                             /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
+  __I  uint8_t HTTRIM;                             /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
+  __I  uint8_t HFTRIM;                             /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
+       uint8_t RESERVED_3[1];
+  __IO uint8_t MC;                                 /**< MCG Miscellaneous Control Register, offset: 0x18 */
+  __I  uint8_t LTRIMRNG;                           /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
+  __I  uint8_t LFTRIM;                             /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
+  __I  uint8_t LSTRIM;                             /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control Register 1 */
+/*! @{ */
+
+#define MCG_C1_IREFSTEN_MASK                     (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT                    (0U)
+/*! IREFSTEN - Internal Reference Stop Enable
+ *  0b0..LIRC is disabled in Stop mode.
+ *  0b1..LIRC is enabled in Stop mode, if IRCLKEN is set.
+ */
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+
+#define MCG_C1_IRCLKEN_MASK                      (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT                     (1U)
+/*! IRCLKEN - Internal Reference Clock Enable
+ *  0b0..LIRC is disabled.
+ *  0b1..LIRC is enabled.
+ */
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+
+#define MCG_C1_CLKS_MASK                         (0xC0U)
+#define MCG_C1_CLKS_SHIFT                        (6U)
+/*! CLKS - Clock Source Select
+ *  0b00..Selects HIRC clock as the main clock source. This is HIRC mode.
+ *  0b01..Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.
+ *  0b10..Selects external clock as the main clock source. This is EXT mode.
+ *  0b11..Reserved. Writing 11 takes no effect.
+ */
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+/*! @} */
+
+/*! @name C2 - MCG Control Register 2 */
+/*! @{ */
+
+#define MCG_C2_IRCS_MASK                         (0x1U)
+#define MCG_C2_IRCS_SHIFT                        (0U)
+/*! IRCS - Low-frequency Internal Reference Clock Select
+ *  0b0..LIRC is in 2 MHz mode.
+ *  0b1..LIRC is in 8 MHz mode.
+ */
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+
+#define MCG_C2_EREFS0_MASK                       (0x4U)
+#define MCG_C2_EREFS0_SHIFT                      (2U)
+/*! EREFS0 - External Clock Source Select
+ *  0b0..External clock requested.
+ *  0b1..Oscillator requested.
+ */
+#define MCG_C2_EREFS0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
+
+#define MCG_C2_HGO0_MASK                         (0x8U)
+#define MCG_C2_HGO0_SHIFT                        (3U)
+/*! HGO0 - Crystal Oscillator Operation Mode Select
+ *  0b0..Configure crystal oscillator for low-power operation.
+ *  0b1..Configure crystal oscillator for high-gain operation.
+ */
+#define MCG_C2_HGO0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
+
+#define MCG_C2_RANGE0_MASK                       (0x30U)
+#define MCG_C2_RANGE0_SHIFT                      (4U)
+/*! RANGE0 - External Clock Source Frequency Range Select
+ *  0b00..Low frequency range selected for the crystal oscillator or the external clock source.
+ *  0b01..High frequency range selected for the crystal oscillator or the external clock source.
+ *  0b10..Very high frequency range selected for the crystal oscillator or the external clock source.
+ *  0b11..Very high frequency range selected for the crystal oscillator or the external clock source. Same effect as 10.
+ */
+#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
+/*! @} */
+
+/*! @name S - MCG Status Register */
+/*! @{ */
+
+#define MCG_S_OSCINIT0_MASK                      (0x2U)
+#define MCG_S_OSCINIT0_SHIFT                     (1U)
+/*! OSCINIT0 - OSC Initialization Status
+ *  0b0..OSC is not ready.
+ *  0b1..OSC clock is ready.
+ */
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+
+#define MCG_S_CLKST_MASK                         (0xCU)
+#define MCG_S_CLKST_SHIFT                        (2U)
+/*! CLKST - Clock Mode Status
+ *  0b00..HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.
+ *  0b01..LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.
+ *  0b10..External clock is selected as the main clock source, and MCG_Lite works at EXT mode.
+ *  0b11..Reserved.
+ */
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+/*! @} */
+
+/*! @name SC - MCG Status and Control Register */
+/*! @{ */
+
+#define MCG_SC_FCRDIV_MASK                       (0xEU)
+#define MCG_SC_FCRDIV_SHIFT                      (1U)
+/*! FCRDIV - Low-frequency Internal Reference Clock Divider
+ *  0b000..Division factor is 1.
+ *  0b001..Division factor is 2.
+ *  0b010..Division factor is 4.
+ *  0b011..Division factor is 8.
+ *  0b100..Division factor is 16.
+ *  0b101..Division factor is 32.
+ *  0b110..Division factor is 64.
+ *  0b111..Division factor is 128.
+ */
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+/*! @} */
+
+/*! @name HCTRIM - MCG High-frequency IRC Coarse Trim Register */
+/*! @{ */
+
+#define MCG_HCTRIM_COARSE_TRIM_MASK              (0x3FU)
+#define MCG_HCTRIM_COARSE_TRIM_SHIFT             (0U)
+/*! COARSE_TRIM - High-frequency IRC Coarse Trim */
+#define MCG_HCTRIM_COARSE_TRIM(x)                (((uint8_t)(((uint8_t)(x)) << MCG_HCTRIM_COARSE_TRIM_SHIFT)) & MCG_HCTRIM_COARSE_TRIM_MASK)
+/*! @} */
+
+/*! @name HTTRIM - MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register */
+/*! @{ */
+
+#define MCG_HTTRIM_TEMPCO_TRIM_MASK              (0x1FU)
+#define MCG_HTTRIM_TEMPCO_TRIM_SHIFT             (0U)
+/*! TEMPCO_TRIM - High-frequency IRC Tempco Trim */
+#define MCG_HTTRIM_TEMPCO_TRIM(x)                (((uint8_t)(((uint8_t)(x)) << MCG_HTTRIM_TEMPCO_TRIM_SHIFT)) & MCG_HTTRIM_TEMPCO_TRIM_MASK)
+/*! @} */
+
+/*! @name HFTRIM - MCG High-frequency IRC Fine Trim Register */
+/*! @{ */
+
+#define MCG_HFTRIM_FINE_TRIM_MASK                (0x7FU)
+#define MCG_HFTRIM_FINE_TRIM_SHIFT               (0U)
+/*! FINE_TRIM - High-frequency IRC Fine Trim */
+#define MCG_HFTRIM_FINE_TRIM(x)                  (((uint8_t)(((uint8_t)(x)) << MCG_HFTRIM_FINE_TRIM_SHIFT)) & MCG_HFTRIM_FINE_TRIM_MASK)
+/*! @} */
+
+/*! @name MC - MCG Miscellaneous Control Register */
+/*! @{ */
+
+#define MCG_MC_LIRC_DIV2_MASK                    (0x7U)
+#define MCG_MC_LIRC_DIV2_SHIFT                   (0U)
+/*! LIRC_DIV2 - Second Low-frequency Internal Reference Clock Divider
+ *  0b000..Division factor is 1.
+ *  0b001..Division factor is 2.
+ *  0b010..Division factor is 4.
+ *  0b011..Division factor is 8.
+ *  0b100..Division factor is 16.
+ *  0b101..Division factor is 32.
+ *  0b110..Division factor is 64.
+ *  0b111..Division factor is 128.
+ */
+#define MCG_MC_LIRC_DIV2(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK)
+
+#define MCG_MC_HIRCEN_MASK                       (0x80U)
+#define MCG_MC_HIRCEN_SHIFT                      (7U)
+/*! HIRCEN - High-frequency IRC Enable
+ *  0b0..HIRC source is not enabled.
+ *  0b1..HIRC source is enabled.
+ */
+#define MCG_MC_HIRCEN(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK)
+/*! @} */
+
+/*! @name LTRIMRNG - MCG Low-frequency IRC Trim Range Register */
+/*! @{ */
+
+#define MCG_LTRIMRNG_STRIMRNG_MASK               (0x3U)
+#define MCG_LTRIMRNG_STRIMRNG_SHIFT              (0U)
+/*! STRIMRNG - LIRC Slow TRIM (2 MHz) Range
+ *  0b00..Frequency shift by 10%.
+ *  0b01..No frequency shift.
+ *  0b10..No frequency shift.
+ *  0b11..Frequency shift by -10%.
+ */
+#define MCG_LTRIMRNG_STRIMRNG(x)                 (((uint8_t)(((uint8_t)(x)) << MCG_LTRIMRNG_STRIMRNG_SHIFT)) & MCG_LTRIMRNG_STRIMRNG_MASK)
+
+#define MCG_LTRIMRNG_FTRIMRNG_MASK               (0xCU)
+#define MCG_LTRIMRNG_FTRIMRNG_SHIFT              (2U)
+/*! FTRIMRNG - LIRC Fast TRIM (8 MHz) Range
+ *  0b00..Frequency shift by 10%.
+ *  0b01..No frequency shift.
+ *  0b10..No frequency shift.
+ *  0b11..Frequency shift by -10%.
+ */
+#define MCG_LTRIMRNG_FTRIMRNG(x)                 (((uint8_t)(((uint8_t)(x)) << MCG_LTRIMRNG_FTRIMRNG_SHIFT)) & MCG_LTRIMRNG_FTRIMRNG_MASK)
+/*! @} */
+
+/*! @name LFTRIM - MCG Low-frequency IRC8M Trim Register */
+/*! @{ */
+
+#define MCG_LFTRIM_LIRC_FTRIM_MASK               (0x7FU)
+#define MCG_LFTRIM_LIRC_FTRIM_SHIFT              (0U)
+/*! LIRC_FTRIM - LIRC8M TRIM */
+#define MCG_LFTRIM_LIRC_FTRIM(x)                 (((uint8_t)(((uint8_t)(x)) << MCG_LFTRIM_LIRC_FTRIM_SHIFT)) & MCG_LFTRIM_LIRC_FTRIM_MASK)
+/*! @} */
+
+/*! @name LSTRIM - MCG Low-frequency IRC2M Trim Register */
+/*! @{ */
+
+#define MCG_LSTRIM_LIRC_STRIM_MASK               (0x7FU)
+#define MCG_LSTRIM_LIRC_STRIM_SHIFT              (0U)
+/*! LIRC_STRIM - LIRC2M TRIM */
+#define MCG_LSTRIM_LIRC_STRIM(x)                 (((uint8_t)(((uint8_t)(x)) << MCG_LSTRIM_LIRC_STRIM_SHIFT)) & MCG_LSTRIM_LIRC_STRIM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+/*! @{ */
+
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the
+ *    crossbar switch's slave input port.
+ *  0b00000000..A bus slave connection to AXBS input port n is absent.
+ *  0b00000001..A bus slave connection to AXBS input port n is present.
+ */
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+/*! @} */
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+/*! @{ */
+
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
+ *  0b00000000..A bus master connection to AXBS input port n is absent
+ *  0b00000001..A bus master connection to AXBS input port n is present
+ */
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+/*! @} */
+
+/*! @name PLACR - Platform Control Register */
+/*! @{ */
+
+#define MCM_PLACR_ARB_MASK                       (0x200U)
+#define MCM_PLACR_ARB_SHIFT                      (9U)
+/*! ARB - Arbitration select
+ *  0b0..Fixed-priority arbitration for the crossbar masters
+ *  0b1..Round-robin arbitration for the crossbar masters
+ */
+#define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+
+#define MCM_PLACR_CFCC_MASK                      (0x400U)
+#define MCM_PLACR_CFCC_SHIFT                     (10U)
+/*! CFCC - Clear Flash Controller Cache */
+#define MCM_PLACR_CFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
+
+#define MCM_PLACR_DFCDA_MASK                     (0x800U)
+#define MCM_PLACR_DFCDA_SHIFT                    (11U)
+/*! DFCDA - Disable Flash Controller Data Caching
+ *  0b0..Enable flash controller data caching
+ *  0b1..Disable flash controller data caching.
+ */
+#define MCM_PLACR_DFCDA(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
+
+#define MCM_PLACR_DFCIC_MASK                     (0x1000U)
+#define MCM_PLACR_DFCIC_SHIFT                    (12U)
+/*! DFCIC - Disable Flash Controller Instruction Caching
+ *  0b0..Enable flash controller instruction caching.
+ *  0b1..Disable flash controller instruction caching.
+ */
+#define MCM_PLACR_DFCIC(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
+
+#define MCM_PLACR_DFCC_MASK                      (0x2000U)
+#define MCM_PLACR_DFCC_SHIFT                     (13U)
+/*! DFCC - Disable Flash Controller Cache
+ *  0b0..Enable flash controller cache.
+ *  0b1..Disable flash controller cache.
+ */
+#define MCM_PLACR_DFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
+
+#define MCM_PLACR_EFDS_MASK                      (0x4000U)
+#define MCM_PLACR_EFDS_SHIFT                     (14U)
+/*! EFDS - Enable Flash Data Speculation
+ *  0b0..Disable flash data speculation.
+ *  0b1..Enable flash data speculation.
+ */
+#define MCM_PLACR_EFDS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
+
+#define MCM_PLACR_DFCS_MASK                      (0x8000U)
+#define MCM_PLACR_DFCS_SHIFT                     (15U)
+/*! DFCS - Disable Flash Controller Speculation
+ *  0b0..Enable flash controller speculation.
+ *  0b1..Disable flash controller speculation.
+ */
+#define MCM_PLACR_DFCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
+
+#define MCM_PLACR_ESFC_MASK                      (0x10000U)
+#define MCM_PLACR_ESFC_SHIFT                     (16U)
+/*! ESFC - Enable Stalling Flash Controller
+ *  0b0..Disable stalling flash controller when flash is busy.
+ *  0b1..Enable stalling flash controller when flash is busy.
+ */
+#define MCM_PLACR_ESFC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
+/*! @} */
+
+/*! @name CPO - Compute Operation Control Register */
+/*! @{ */
+
+#define MCM_CPO_CPOREQ_MASK                      (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT                     (0U)
+/*! CPOREQ - Compute Operation Request
+ *  0b0..Request is cleared.
+ *  0b1..Request Compute Operation.
+ */
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+
+#define MCM_CPO_CPOACK_MASK                      (0x2U)
+#define MCM_CPO_CPOACK_SHIFT                     (1U)
+/*! CPOACK - Compute Operation Acknowledge
+ *  0b0..Compute operation entry has not completed or compute operation exit has completed.
+ *  0b1..Compute operation entry has completed or compute operation exit has not completed.
+ */
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+
+#define MCM_CPO_CPOWOI_MASK                      (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT                     (2U)
+/*! CPOWOI - Compute Operation Wake-up on Interrupt
+ *  0b0..No effect.
+ *  0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
+ */
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
+  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
+  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
+  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
+       uint8_t RESERVED_0[3824];
+  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
+       uint8_t RESERVED_1[156];
+  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
+  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
+  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
+  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
+  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/*! @name POSITION - MTB Position Register */
+/*! @{ */
+
+#define MTB_POSITION_WRAP_MASK                   (0x4U)
+#define MTB_POSITION_WRAP_SHIFT                  (2U)
+/*! WRAP - WRAP */
+#define MTB_POSITION_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
+
+#define MTB_POSITION_POINTER_MASK                (0xFFFFFFF8U)
+#define MTB_POSITION_POINTER_SHIFT               (3U)
+/*! POINTER - Trace Packet Address Pointer[28:0] */
+#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
+/*! @} */
+
+/*! @name MASTER - MTB Master Register */
+/*! @{ */
+
+#define MTB_MASTER_MASK_MASK                     (0x1FU)
+#define MTB_MASTER_MASK_SHIFT                    (0U)
+/*! MASK - Mask */
+#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
+
+#define MTB_MASTER_TSTARTEN_MASK                 (0x20U)
+#define MTB_MASTER_TSTARTEN_SHIFT                (5U)
+/*! TSTARTEN - Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
+
+#define MTB_MASTER_TSTOPEN_MASK                  (0x40U)
+#define MTB_MASTER_TSTOPEN_SHIFT                 (6U)
+/*! TSTOPEN - Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
+
+#define MTB_MASTER_SFRWPRIV_MASK                 (0x80U)
+#define MTB_MASTER_SFRWPRIV_SHIFT                (7U)
+/*! SFRWPRIV - Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
+
+#define MTB_MASTER_RAMPRIV_MASK                  (0x100U)
+#define MTB_MASTER_RAMPRIV_SHIFT                 (8U)
+/*! RAMPRIV - RAM Privilege */
+#define MTB_MASTER_RAMPRIV(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
+
+#define MTB_MASTER_HALTREQ_MASK                  (0x200U)
+#define MTB_MASTER_HALTREQ_SHIFT                 (9U)
+/*! HALTREQ - Halt Request */
+#define MTB_MASTER_HALTREQ(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
+
+#define MTB_MASTER_EN_MASK                       (0x80000000U)
+#define MTB_MASTER_EN_SHIFT                      (31U)
+/*! EN - Main Trace Enable */
+#define MTB_MASTER_EN(x)                         (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
+/*! @} */
+
+/*! @name FLOW - MTB Flow Register */
+/*! @{ */
+
+#define MTB_FLOW_AUTOSTOP_MASK                   (0x1U)
+#define MTB_FLOW_AUTOSTOP_SHIFT                  (0U)
+/*! AUTOSTOP - AUTOSTOP */
+#define MTB_FLOW_AUTOSTOP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
+
+#define MTB_FLOW_AUTOHALT_MASK                   (0x2U)
+#define MTB_FLOW_AUTOHALT_SHIFT                  (1U)
+/*! AUTOHALT - AUTOHALT */
+#define MTB_FLOW_AUTOHALT(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
+
+#define MTB_FLOW_WATERMARK_MASK                  (0xFFFFFFF8U)
+#define MTB_FLOW_WATERMARK_SHIFT                 (3U)
+/*! WATERMARK - WATERMARK[28:0] */
+#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
+/*! @} */
+
+/*! @name BASE - MTB Base Register */
+/*! @{ */
+
+#define MTB_BASE_BASEADDR_MASK                   (0xFFFFFFFFU)
+#define MTB_BASE_BASEADDR_SHIFT                  (0U)
+/*! BASEADDR - BASEADDR */
+#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
+/*! @} */
+
+/*! @name MODECTRL - Integration Mode Control Register */
+/*! @{ */
+
+#define MTB_MODECTRL_MODECTRL_MASK               (0xFFFFFFFFU)
+#define MTB_MODECTRL_MODECTRL_SHIFT              (0U)
+/*! MODECTRL - MODECTRL */
+#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
+/*! @} */
+
+/*! @name TAGSET - Claim TAG Set Register */
+/*! @{ */
+
+#define MTB_TAGSET_TAGSET_MASK                   (0xFFFFFFFFU)
+#define MTB_TAGSET_TAGSET_SHIFT                  (0U)
+/*! TAGSET - TAGSET */
+#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
+/*! @} */
+
+/*! @name TAGCLEAR - Claim TAG Clear Register */
+/*! @{ */
+
+#define MTB_TAGCLEAR_TAGCLEAR_MASK               (0xFFFFFFFFU)
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              (0U)
+/*! TAGCLEAR - TAGCLEAR */
+#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
+/*! @} */
+
+/*! @name LOCKACCESS - Lock Access Register */
+/*! @{ */
+
+#define MTB_LOCKACCESS_LOCKACCESS_MASK           (0xFFFFFFFFU)
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          (0U)
+#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
+/*! @} */
+
+/*! @name LOCKSTAT - Lock Status Register */
+/*! @{ */
+
+#define MTB_LOCKSTAT_LOCKSTAT_MASK               (0xFFFFFFFFU)
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              (0U)
+/*! LOCKSTAT - LOCKSTAT */
+#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
+/*! @} */
+
+/*! @name AUTHSTAT - Authentication Status Register */
+/*! @{ */
+
+#define MTB_AUTHSTAT_BIT0_MASK                   (0x1U)
+#define MTB_AUTHSTAT_BIT0_SHIFT                  (0U)
+#define MTB_AUTHSTAT_BIT0(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
+
+#define MTB_AUTHSTAT_BIT1_MASK                   (0x2U)
+#define MTB_AUTHSTAT_BIT1_SHIFT                  (1U)
+/*! BIT1 - BIT1 */
+#define MTB_AUTHSTAT_BIT1(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
+
+#define MTB_AUTHSTAT_BIT2_MASK                   (0x4U)
+#define MTB_AUTHSTAT_BIT2_SHIFT                  (2U)
+/*! BIT2 - BIT2 */
+#define MTB_AUTHSTAT_BIT2(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
+
+#define MTB_AUTHSTAT_BIT3_MASK                   (0x8U)
+#define MTB_AUTHSTAT_BIT3_SHIFT                  (3U)
+/*! BIT3 - BIT3 */
+#define MTB_AUTHSTAT_BIT3(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
+/*! @} */
+
+/*! @name DEVICEARCH - Device Architecture Register */
+/*! @{ */
+
+#define MTB_DEVICEARCH_DEVICEARCH_MASK           (0xFFFFFFFFU)
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          (0U)
+/*! DEVICEARCH - DEVICEARCH */
+#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
+/*! @} */
+
+/*! @name DEVICECFG - Device Configuration Register */
+/*! @{ */
+
+#define MTB_DEVICECFG_DEVICECFG_MASK             (0xFFFFFFFFU)
+#define MTB_DEVICECFG_DEVICECFG_SHIFT            (0U)
+/*! DEVICECFG - DEVICECFG */
+#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
+/*! @} */
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+/*! @{ */
+
+#define MTB_DEVICETYPID_DEVICETYPID_MASK         (0xFFFFFFFFU)
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        (0U)
+/*! DEVICETYPID - DEVICETYPID */
+#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID4_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID5_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID6_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID7_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID0_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID1_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID2_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+
+#define MTB_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID3_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define MTB_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+
+#define MTB_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define MTB_COMPID_COMPID_SHIFT                  (0U)
+/*! COMPID - Component ID */
+#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of MTB_COMPID */
+#define MTB_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE                                 (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB                                      ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS                           { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS                            { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+    __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } COMPARATOR[2];
+       uint8_t RESERVED_1[448];
+  __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+       uint8_t RESERVED_2[3524];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - MTB DWT Control Register */
+/*! @{ */
+
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK              (0xFFFFFFFU)
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             (0U)
+/*! DWTCFGCTRL - DWT configuration controls */
+#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
+
+#define MTBDWT_CTRL_NUMCMP_MASK                  (0xF0000000U)
+#define MTBDWT_CTRL_NUMCMP_SHIFT                 (28U)
+/*! NUMCMP - Number of comparators */
+#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
+/*! @} */
+
+/*! @name COMP - MTB_DWT Comparator Register */
+/*! @{ */
+
+#define MTBDWT_COMP_COMP_MASK                    (0xFFFFFFFFU)
+#define MTBDWT_COMP_COMP_SHIFT                   (0U)
+/*! COMP - Reference value for comparison */
+#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
+/*! @} */
+
+/* The count of MTBDWT_COMP */
+#define MTBDWT_COMP_COUNT                        (2U)
+
+/*! @name MASK - MTB_DWT Comparator Mask Register */
+/*! @{ */
+
+#define MTBDWT_MASK_MASK_MASK                    (0x1FU)
+#define MTBDWT_MASK_MASK_SHIFT                   (0U)
+/*! MASK - MASK */
+#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
+/*! @} */
+
+/* The count of MTBDWT_MASK */
+#define MTBDWT_MASK_COUNT                        (2U)
+
+/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
+/*! @{ */
+
+#define MTBDWT_FCT_FUNCTION_MASK                 (0xFU)
+#define MTBDWT_FCT_FUNCTION_SHIFT                (0U)
+/*! FUNCTION - Function
+ *  0b0000..Disabled.
+ *  0b0100..Instruction fetch.
+ *  0b0101..Data operand read.
+ *  0b0110..Data operand write.
+ *  0b0111..Data operand (read + write).
+ */
+#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
+
+#define MTBDWT_FCT_DATAVMATCH_MASK               (0x100U)
+#define MTBDWT_FCT_DATAVMATCH_SHIFT              (8U)
+/*! DATAVMATCH - Data Value Match
+ *  0b0..Perform address comparison.
+ *  0b1..Perform data value comparison.
+ */
+#define MTBDWT_FCT_DATAVMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
+
+#define MTBDWT_FCT_DATAVSIZE_MASK                (0xC00U)
+#define MTBDWT_FCT_DATAVSIZE_SHIFT               (10U)
+/*! DATAVSIZE - Data Value Size
+ *  0b00..Byte.
+ *  0b01..Halfword.
+ *  0b10..Word.
+ *  0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
+ */
+#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
+
+#define MTBDWT_FCT_DATAVADDR0_MASK               (0xF000U)
+#define MTBDWT_FCT_DATAVADDR0_SHIFT              (12U)
+/*! DATAVADDR0 - Data Value Address 0 */
+#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
+
+#define MTBDWT_FCT_MATCHED_MASK                  (0x1000000U)
+#define MTBDWT_FCT_MATCHED_SHIFT                 (24U)
+/*! MATCHED - Comparator match
+ *  0b0..No match.
+ *  0b1..Match occurred.
+ */
+#define MTBDWT_FCT_MATCHED(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
+/*! @} */
+
+/* The count of MTBDWT_FCT */
+#define MTBDWT_FCT_COUNT                         (2U)
+
+/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
+/*! @{ */
+
+#define MTBDWT_TBCTRL_ACOMP0_MASK                (0x1U)
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT               (0U)
+/*! ACOMP0 - Action based on Comparator 0 match
+ *  0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
+ *  0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
+ */
+#define MTBDWT_TBCTRL_ACOMP0(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
+
+#define MTBDWT_TBCTRL_ACOMP1_MASK                (0x2U)
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT               (1U)
+/*! ACOMP1 - Action based on Comparator 1 match
+ *  0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
+ *  0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
+ */
+#define MTBDWT_TBCTRL_ACOMP1(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
+
+#define MTBDWT_TBCTRL_NUMCOMP_MASK               (0xF0000000U)
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              (28U)
+/*! NUMCOMP - Number of Comparators */
+#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
+/*! @} */
+
+/*! @name DEVICECFG - Device Configuration Register */
+/*! @{ */
+
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK          (0xFFFFFFFFU)
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         (0U)
+/*! DEVICECFG - DEVICECFG */
+#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/*! @} */
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+/*! @{ */
+
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      (0xFFFFFFFFU)
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     (0U)
+/*! DEVICETYPID - DEVICETYPID */
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID4_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID4_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID4_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID5_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID5_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID5_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID6_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID6_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID6_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID7_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID7_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID7_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID0_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID0_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID0_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID1_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID1_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID1_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID2_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID2_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID2_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+
+#define MTBDWT_PERIPHID3_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID3_PERIPHID_SHIFT          (0U)
+/*! PERIPHID - PERIPHID */
+#define MTBDWT_PERIPHID3_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+
+#define MTBDWT_COMPID_COMPID_MASK                (0xFFFFFFFFU)
+#define MTBDWT_COMPID_COMPID_SHIFT               (0U)
+/*! COMPID - Component ID */
+#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of MTBDWT_COMPID */
+#define MTBDWT_COMPID_COUNT                      (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE                              (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS                        { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS                         { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+/*! @{ */
+
+#define NV_BACKKEY3_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+/*! @{ */
+
+#define NV_BACKKEY2_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+/*! @{ */
+
+#define NV_BACKKEY1_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+/*! @{ */
+
+#define NV_BACKKEY0_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+/*! @{ */
+
+#define NV_BACKKEY7_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+/*! @{ */
+
+#define NV_BACKKEY6_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+/*! @{ */
+
+#define NV_BACKKEY5_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+/*! @{ */
+
+#define NV_BACKKEY4_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT                    (0U)
+/*! KEY - Backdoor Comparison Key. */
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+/*! @} */
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+/*! @{ */
+
+#define NV_FPROT3_PROT_MASK                      (0xFFU)
+#define NV_FPROT3_PROT_SHIFT                     (0U)
+/*! PROT - P-Flash Region Protect */
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+/*! @{ */
+
+#define NV_FPROT2_PROT_MASK                      (0xFFU)
+#define NV_FPROT2_PROT_SHIFT                     (0U)
+/*! PROT - P-Flash Region Protect */
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+/*! @{ */
+
+#define NV_FPROT1_PROT_MASK                      (0xFFU)
+#define NV_FPROT1_PROT_SHIFT                     (0U)
+/*! PROT - P-Flash Region Protect */
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+/*! @{ */
+
+#define NV_FPROT0_PROT_MASK                      (0xFFU)
+#define NV_FPROT0_PROT_SHIFT                     (0U)
+/*! PROT - P-Flash Region Protect */
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+/*! @} */
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+/*! @{ */
+
+#define NV_FSEC_SEC_MASK                         (0x3U)
+#define NV_FSEC_SEC_SHIFT                        (0U)
+/*! SEC - Flash Security
+ *  0b10..MCU security status is unsecure
+ *  0b11..MCU security status is secure
+ */
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+
+#define NV_FSEC_FSLACC_MASK                      (0xCU)
+#define NV_FSEC_FSLACC_SHIFT                     (2U)
+/*! FSLACC - Freescale Failure Analysis Access Code
+ *  0b10..Freescale factory access denied
+ *  0b11..Freescale factory access granted
+ */
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+
+#define NV_FSEC_MEEN_MASK                        (0x30U)
+#define NV_FSEC_MEEN_SHIFT                       (4U)
+/*! MEEN
+ *  0b10..Mass erase is disabled
+ *  0b11..Mass erase is enabled
+ */
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+
+#define NV_FSEC_KEYEN_MASK                       (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT                      (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ *  0b10..Backdoor key access enabled
+ *  0b11..Backdoor key access disabled
+ */
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+/*! @{ */
+
+#define NV_FOPT_LPBOOT0_MASK                     (0x1U)
+#define NV_FOPT_LPBOOT0_SHIFT                    (0U)
+/*! LPBOOT0
+ *  0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
+ *  0b1..Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
+ */
+#define NV_FOPT_LPBOOT0(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
+
+#define NV_FOPT_BOOTPIN_OPT_MASK                 (0x2U)
+#define NV_FOPT_BOOTPIN_OPT_SHIFT                (1U)
+/*! BOOTPIN_OPT
+ *  0b0..Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+ *  0b1..Boot source configured by FOPT (BOOTSRC_SEL) bits
+ */
+#define NV_FOPT_BOOTPIN_OPT(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
+
+#define NV_FOPT_NMI_DIS_MASK                     (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT                    (2U)
+/*! NMI_DIS
+ *  0b0..NMI interrupts are always blocked
+ *  0b1..NMI_b pin/interrupts reset default to enabled
+ */
+#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+
+#define NV_FOPT_RESET_PIN_CFG_MASK               (0x8U)
+#define NV_FOPT_RESET_PIN_CFG_SHIFT              (3U)
+/*! RESET_PIN_CFG
+ *  0b0..RESET pin is disabled following a POR and cannot be enabled as reset function
+ *  0b1..RESET_b pin is dedicated
+ */
+#define NV_FOPT_RESET_PIN_CFG(x)                 (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
+
+#define NV_FOPT_LPBOOT1_MASK                     (0x10U)
+#define NV_FOPT_LPBOOT1_SHIFT                    (4U)
+/*! LPBOOT1
+ *  0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
+ *  0b1..Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
+ */
+#define NV_FOPT_LPBOOT1(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
+
+#define NV_FOPT_FAST_INIT_MASK                   (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT                  (5U)
+/*! FAST_INIT
+ *  0b0..Slower initialization
+ *  0b1..Fast Initialization
+ */
+#define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+
+#define NV_FOPT_BOOTSRC_SEL_MASK                 (0xC0U)
+#define NV_FOPT_BOOTSRC_SEL_SHIFT                (6U)
+/*! BOOTSRC_SEL - Boot source selection
+ *  0b00..Boot from Flash
+ *  0b10..Boot from ROM
+ *  0b11..Boot from ROM
+ */
+#define NV_FOPT_BOOTSRC_SEL(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+/*! @{ */
+
+#define OSC_CR_SC16P_MASK                        (0x1U)
+#define OSC_CR_SC16P_SHIFT                       (0U)
+/*! SC16P - Oscillator 16 pF Capacitor Load Configure
+ *  0b0..Disable the selection.
+ *  0b1..Add 16 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+
+#define OSC_CR_SC8P_MASK                         (0x2U)
+#define OSC_CR_SC8P_SHIFT                        (1U)
+/*! SC8P - Oscillator 8 pF Capacitor Load Configure
+ *  0b0..Disable the selection.
+ *  0b1..Add 8 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+
+#define OSC_CR_SC4P_MASK                         (0x4U)
+#define OSC_CR_SC4P_SHIFT                        (2U)
+/*! SC4P - Oscillator 4 pF Capacitor Load Configure
+ *  0b0..Disable the selection.
+ *  0b1..Add 4 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+
+#define OSC_CR_SC2P_MASK                         (0x8U)
+#define OSC_CR_SC2P_SHIFT                        (3U)
+/*! SC2P - Oscillator 2 pF Capacitor Load Configure
+ *  0b0..Disable the selection.
+ *  0b1..Add 2 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+
+#define OSC_CR_EREFSTEN_MASK                     (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT                    (5U)
+/*! EREFSTEN - External Reference Stop Enable
+ *  0b0..External reference clock is disabled in Stop mode.
+ *  0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
+ */
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+
+#define OSC_CR_ERCLKEN_MASK                      (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT                     (7U)
+/*! ERCLKEN - External Reference Enable
+ *  0b0..External reference clock is inactive.
+ *  0b1..External reference clock is enabled.
+ */
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE                                (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0                                     ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[220];
+  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+       uint8_t RESERVED_1[24];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+/*! @{ */
+
+#define PIT_MCR_FRZ_MASK                         (0x1U)
+#define PIT_MCR_FRZ_SHIFT                        (0U)
+/*! FRZ - Freeze
+ *  0b0..Timers continue to run in Debug mode.
+ *  0b1..Timers are stopped in Debug mode.
+ */
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+
+#define PIT_MCR_MDIS_MASK                        (0x2U)
+#define PIT_MCR_MDIS_SHIFT                       (1U)
+/*! MDIS - Module Disable - (PIT section)
+ *  0b0..Clock for standard PIT timers is enabled.
+ *  0b1..Clock for standard PIT timers is disabled.
+ */
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+/*! @{ */
+
+#define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT                    (0U)
+/*! LTH - Life Timer value */
+#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+/*! @} */
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+/*! @{ */
+
+#define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT                    (0U)
+/*! LTL - Life Timer value */
+#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+/*! @} */
+
+/*! @name LDVAL - Timer Load Value Register */
+/*! @{ */
+
+#define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT                      (0U)
+/*! TSV - Timer Start Value */
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+/*! @} */
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT                          (2U)
+
+/*! @name CVAL - Current Timer Value Register */
+/*! @{ */
+
+#define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT                       (0U)
+/*! TVL - Current Timer Value */
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+/*! @} */
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT                           (2U)
+
+/*! @name TCTRL - Timer Control Register */
+/*! @{ */
+
+#define PIT_TCTRL_TEN_MASK                       (0x1U)
+#define PIT_TCTRL_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..Timer n is disabled.
+ *  0b1..Timer n is enabled.
+ */
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+
+#define PIT_TCTRL_TIE_MASK                       (0x2U)
+#define PIT_TCTRL_TIE_SHIFT                      (1U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Interrupt requests from Timer n are disabled.
+ *  0b1..Interrupt will be requested whenever TIF is set.
+ */
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+
+#define PIT_TCTRL_CHN_MASK                       (0x4U)
+#define PIT_TCTRL_CHN_SHIFT                      (2U)
+/*! CHN - Chain Mode
+ *  0b0..Timer is not chained.
+ *  0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
+ */
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+/*! @} */
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT                          (2U)
+
+/*! @name TFLG - Timer Flag Register */
+/*! @{ */
+
+#define PIT_TFLG_TIF_MASK                        (0x1U)
+#define PIT_TFLG_TIF_SHIFT                       (0U)
+/*! TIF - Timer Interrupt Flag
+ *  0b0..Timeout has not yet occurred.
+ *  0b1..Timeout has occurred.
+ */
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+/*! @} */
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT                           (2U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+/*! @{ */
+
+#define PMC_LVDSC1_LVDV_MASK                     (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT                    (0U)
+/*! LVDV - Low-Voltage Detect Voltage Select
+ *  0b00..Low trip point selected (V LVD = V LVDL )
+ *  0b01..High trip point selected (V LVD = V LVDH )
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+
+#define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
+/*! LVDRE - Low-Voltage Detect Reset Enable
+ *  0b0..LVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when LVDF = 1
+ */
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+
+#define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
+/*! LVDIE - Low-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when LVDF = 1
+ */
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+
+#define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
+/*! LVDACK - Low-Voltage Detect Acknowledge */
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+
+#define PMC_LVDSC1_LVDF_MASK                     (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT                    (7U)
+/*! LVDF - Low-Voltage Detect Flag
+ *  0b0..Low-voltage event not detected
+ *  0b1..Low-voltage event detected
+ */
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+/*! @} */
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+/*! @{ */
+
+#define PMC_LVDSC2_LVWV_MASK                     (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT                    (0U)
+/*! LVWV - Low-Voltage Warning Voltage Select
+ *  0b00..Low trip point selected (VLVW = VLVW1)
+ *  0b01..Mid 1 trip point selected (VLVW = VLVW2)
+ *  0b10..Mid 2 trip point selected (VLVW = VLVW3)
+ *  0b11..High trip point selected (VLVW = VLVW4)
+ */
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+
+#define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
+/*! LVWIE - Low-Voltage Warning Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when LVWF = 1
+ */
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+
+#define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
+/*! LVWACK - Low-Voltage Warning Acknowledge */
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+
+#define PMC_LVDSC2_LVWF_MASK                     (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT                    (7U)
+/*! LVWF - Low-Voltage Warning Flag
+ *  0b0..Low-voltage warning event not detected
+ *  0b1..Low-voltage warning event detected
+ */
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+/*! @} */
+
+/*! @name REGSC - Regulator Status And Control register */
+/*! @{ */
+
+#define PMC_REGSC_BGBE_MASK                      (0x1U)
+#define PMC_REGSC_BGBE_SHIFT                     (0U)
+/*! BGBE - Bandgap Buffer Enable
+ *  0b0..Bandgap buffer not enabled
+ *  0b1..Bandgap buffer enabled
+ */
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+
+#define PMC_REGSC_REGONS_MASK                    (0x4U)
+#define PMC_REGSC_REGONS_SHIFT                   (2U)
+/*! REGONS - Regulator In Run Regulation Status
+ *  0b0..Regulator is in stop regulation or in transition to/from it
+ *  0b1..Regulator is in run regulation
+ */
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+
+#define PMC_REGSC_ACKISO_MASK                    (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT                   (3U)
+/*! ACKISO - Acknowledge Isolation
+ *  0b0..Peripherals and I/O pads are in normal run state.
+ *  0b1..Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+
+#define PMC_REGSC_BGEN_MASK                      (0x10U)
+#define PMC_REGSC_BGEN_SHIFT                     (4U)
+/*! BGEN - Bandgap Enable In VLPx Operation
+ *  0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ *  0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { PMC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+/*! @{ */
+
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+/*! PS - Pull Select
+ *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ */
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+/*! PE - Pull Enable
+ *  0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
+ *  0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
+ */
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+
+#define PORT_PCR_SRE_MASK                        (0x4U)
+#define PORT_PCR_SRE_SHIFT                       (2U)
+/*! SRE - Slew Rate Enable
+ *  0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ *  0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+/*! PFE - Passive Filter Enable
+ *  0b0..Passive input filter is disabled on the corresponding pin.
+ *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input.
+ *       Refer to the device data sheet for filter characteristics.
+ */
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+
+#define PORT_PCR_DSE_MASK                        (0x40U)
+#define PORT_PCR_DSE_SHIFT                       (6U)
+/*! DSE - Drive Strength Enable
+ *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ */
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+
+#define PORT_PCR_MUX_MASK                        (0x700U)
+#define PORT_PCR_MUX_SHIFT                       (8U)
+/*! MUX - Pin Mux Control
+ *  0b000..Pin disabled (analog).
+ *  0b001..Alternative 1 (GPIO).
+ *  0b010..Alternative 2 (chip-specific).
+ *  0b011..Alternative 3 (chip-specific).
+ *  0b100..Alternative 4 (chip-specific).
+ *  0b101..Alternative 5 (chip-specific).
+ *  0b110..Alternative 6 (chip-specific).
+ *  0b111..Alternative 7 (chip-specific).
+ */
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+
+#define PORT_PCR_IRQC_MASK                       (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT                      (16U)
+/*! IRQC - Interrupt Configuration
+ *  0b0000..Interrupt/DMA request disabled.
+ *  0b0001..DMA request on rising edge.
+ *  0b0010..DMA request on falling edge.
+ *  0b0011..DMA request on either edge.
+ *  0b1000..Interrupt when logic 0.
+ *  0b1001..Interrupt on rising-edge.
+ *  0b1010..Interrupt on falling-edge.
+ *  0b1011..Interrupt on either edge.
+ *  0b1100..Interrupt when logic 1.
+ */
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+
+#define PORT_PCR_ISF_MASK                        (0x1000000U)
+#define PORT_PCR_ISF_SHIFT                       (24U)
+/*! ISF - Interrupt Status Flag
+ *  0b0..Configured interrupt is not detected.
+ *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
+ *       corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the
+ *       flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive
+ *       interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
+ */
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+/*! @} */
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+/*! @{ */
+
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+/*! GPWD - Global Pin Write Data */
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+/*! GPWE - Global Pin Write Enable
+ *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
+ *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+/*! @} */
+
+/*! @name GPCHR - Global Pin Control High Register */
+/*! @{ */
+
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+/*! GPWD - Global Pin Write Data */
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+/*! GPWE - Global Pin Write Enable
+ *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
+ *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+/*! @} */
+
+/*! @name ISFR - Interrupt Status Flag Register */
+/*! @{ */
+
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+/*! ISF - Interrupt Status Flag
+ *  0b00000000000000000000000000000000..Configured interrupt is not detected.
+ *  0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a
+ *                                      DMA request, then the corresponding flag will be cleared automatically at
+ *                                      the completion of the requested DMA transfer. Otherwise, the flag remains set
+ *                                      until a logic 1 is written to the flag. If the pin is configured for a
+ *                                      level sensitive interrupt and the pin remains asserted, then the flag is set
+ *                                      again immediately after it is cleared.
+ */
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+  __IO uint8_t FM;                                 /**< Force Mode Register, offset: 0x6 */
+  __IO uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+  __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
+  __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+/*! @{ */
+
+#define RCM_SRS0_WAKEUP_MASK                     (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT                    (0U)
+/*! WAKEUP - Low Leakage Wakeup Reset
+ *  0b0..Reset not caused by LLWU module wakeup source
+ *  0b1..Reset caused by LLWU module wakeup source
+ */
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+
+#define RCM_SRS0_LVD_MASK                        (0x2U)
+#define RCM_SRS0_LVD_SHIFT                       (1U)
+/*! LVD - Low-Voltage Detect Reset
+ *  0b0..Reset not caused by LVD trip or POR
+ *  0b1..Reset caused by LVD trip or POR
+ */
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+
+#define RCM_SRS0_WDOG_MASK                       (0x20U)
+#define RCM_SRS0_WDOG_SHIFT                      (5U)
+/*! WDOG - Watchdog
+ *  0b0..Reset not caused by watchdog timeout
+ *  0b1..Reset caused by watchdog timeout
+ */
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+
+#define RCM_SRS0_PIN_MASK                        (0x40U)
+#define RCM_SRS0_PIN_SHIFT                       (6U)
+/*! PIN - External Reset Pin
+ *  0b0..Reset not caused by external reset pin
+ *  0b1..Reset caused by external reset pin
+ */
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+
+#define RCM_SRS0_POR_MASK                        (0x80U)
+#define RCM_SRS0_POR_SHIFT                       (7U)
+/*! POR - Power-On Reset
+ *  0b0..Reset not caused by POR
+ *  0b1..Reset caused by POR
+ */
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+/*! @} */
+
+/*! @name SRS1 - System Reset Status Register 1 */
+/*! @{ */
+
+#define RCM_SRS1_LOCKUP_MASK                     (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT                    (1U)
+/*! LOCKUP - Core Lockup
+ *  0b0..Reset not caused by core LOCKUP event
+ *  0b1..Reset caused by core LOCKUP event
+ */
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+
+#define RCM_SRS1_SW_MASK                         (0x4U)
+#define RCM_SRS1_SW_SHIFT                        (2U)
+/*! SW - Software
+ *  0b0..Reset not caused by software setting of SYSRESETREQ bit
+ *  0b1..Reset caused by software setting of SYSRESETREQ bit
+ */
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+
+#define RCM_SRS1_MDM_AP_MASK                     (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT                    (3U)
+/*! MDM_AP - MDM-AP System Reset Request
+ *  0b0..Reset not caused by host debugger system setting of the System Reset Request bit
+ *  0b1..Reset caused by host debugger system setting of the System Reset Request bit
+ */
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+
+#define RCM_SRS1_SACKERR_MASK                    (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT                   (5U)
+/*! SACKERR - Stop Mode Acknowledge Error Reset
+ *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
+ *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
+ */
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+/*! @} */
+
+/*! @name RPFC - Reset Pin Filter Control register */
+/*! @{ */
+
+#define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
+/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
+ *  0b00..All filtering disabled
+ *  0b01..Bus clock filter enabled for normal operation
+ *  0b10..LPO clock filter enabled for normal operation
+ *  0b11..Reserved
+ */
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+
+#define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
+/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
+ *  0b0..All filtering disabled
+ *  0b1..LPO clock filter enabled
+ */
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+/*! @} */
+
+/*! @name RPFW - Reset Pin Filter Width register */
+/*! @{ */
+
+#define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
+/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
+ *  0b00000..Bus clock filter count is 1
+ *  0b00001..Bus clock filter count is 2
+ *  0b00010..Bus clock filter count is 3
+ *  0b00011..Bus clock filter count is 4
+ *  0b00100..Bus clock filter count is 5
+ *  0b00101..Bus clock filter count is 6
+ *  0b00110..Bus clock filter count is 7
+ *  0b00111..Bus clock filter count is 8
+ *  0b01000..Bus clock filter count is 9
+ *  0b01001..Bus clock filter count is 10
+ *  0b01010..Bus clock filter count is 11
+ *  0b01011..Bus clock filter count is 12
+ *  0b01100..Bus clock filter count is 13
+ *  0b01101..Bus clock filter count is 14
+ *  0b01110..Bus clock filter count is 15
+ *  0b01111..Bus clock filter count is 16
+ *  0b10000..Bus clock filter count is 17
+ *  0b10001..Bus clock filter count is 18
+ *  0b10010..Bus clock filter count is 19
+ *  0b10011..Bus clock filter count is 20
+ *  0b10100..Bus clock filter count is 21
+ *  0b10101..Bus clock filter count is 22
+ *  0b10110..Bus clock filter count is 23
+ *  0b10111..Bus clock filter count is 24
+ *  0b11000..Bus clock filter count is 25
+ *  0b11001..Bus clock filter count is 26
+ *  0b11010..Bus clock filter count is 27
+ *  0b11011..Bus clock filter count is 28
+ *  0b11100..Bus clock filter count is 29
+ *  0b11101..Bus clock filter count is 30
+ *  0b11110..Bus clock filter count is 31
+ *  0b11111..Bus clock filter count is 32
+ */
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+/*! @} */
+
+/*! @name FM - Force Mode Register */
+/*! @{ */
+
+#define RCM_FM_FORCEROM_MASK                     (0x6U)
+#define RCM_FM_FORCEROM_SHIFT                    (1U)
+/*! FORCEROM - Force ROM Boot
+ *  0b00..No effect
+ *  0b01..Force boot from ROM with RCM_MR[1] set.
+ *  0b10..Force boot from ROM with RCM_MR[2] set.
+ *  0b11..Force boot from ROM with RCM_MR[2:1] set.
+ */
+#define RCM_FM_FORCEROM(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
+/*! @} */
+
+/*! @name MR - Mode Register */
+/*! @{ */
+
+#define RCM_MR_BOOTROM_MASK                      (0x6U)
+#define RCM_MR_BOOTROM_SHIFT                     (1U)
+/*! BOOTROM - Boot ROM Configuration
+ *  0b00..Boot from Flash
+ *  0b01..Boot from ROM due to BOOTCFG0 pin assertion
+ *  0b10..Boot form ROM due to FOPT[7] configuration
+ *  0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
+ */
+#define RCM_MR_BOOTROM(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
+/*! @} */
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+/*! @{ */
+
+#define RCM_SSRS0_SWAKEUP_MASK                   (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT                  (0U)
+/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
+ *  0b0..Reset not caused by LLWU module wakeup source
+ *  0b1..Reset caused by LLWU module wakeup source
+ */
+#define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+
+#define RCM_SSRS0_SLVD_MASK                      (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT                     (1U)
+/*! SLVD - Sticky Low-Voltage Detect Reset
+ *  0b0..Reset not caused by LVD trip or POR
+ *  0b1..Reset caused by LVD trip or POR
+ */
+#define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+
+#define RCM_SSRS0_SWDOG_MASK                     (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT                    (5U)
+/*! SWDOG - Sticky Watchdog
+ *  0b0..Reset not caused by watchdog timeout
+ *  0b1..Reset caused by watchdog timeout
+ */
+#define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+
+#define RCM_SSRS0_SPIN_MASK                      (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT                     (6U)
+/*! SPIN - Sticky External Reset Pin
+ *  0b0..Reset not caused by external reset pin
+ *  0b1..Reset caused by external reset pin
+ */
+#define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+
+#define RCM_SSRS0_SPOR_MASK                      (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT                     (7U)
+/*! SPOR - Sticky Power-On Reset
+ *  0b0..Reset not caused by POR
+ *  0b1..Reset caused by POR
+ */
+#define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+/*! @} */
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+/*! @{ */
+
+#define RCM_SSRS1_SLOCKUP_MASK                   (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT                  (1U)
+/*! SLOCKUP - Sticky Core Lockup
+ *  0b0..Reset not caused by core LOCKUP event
+ *  0b1..Reset caused by core LOCKUP event
+ */
+#define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+
+#define RCM_SSRS1_SSW_MASK                       (0x4U)
+#define RCM_SSRS1_SSW_SHIFT                      (2U)
+/*! SSW - Sticky Software
+ *  0b0..Reset not caused by software setting of SYSRESETREQ bit
+ *  0b1..Reset caused by software setting of SYSRESETREQ bit
+ */
+#define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+
+#define RCM_SSRS1_SMDM_AP_MASK                   (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT                  (3U)
+/*! SMDM_AP - Sticky MDM-AP System Reset Request
+ *  0b0..Reset not caused by host debugger system setting of the System Reset Request bit
+ *  0b1..Reset caused by host debugger system setting of the System Reset Request bit
+ */
+#define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+
+#define RCM_SSRS1_SSACKERR_MASK                  (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT                 (5U)
+/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
+ *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
+ *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
+ */
+#define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+/*! @{ */
+
+#define RFSYS_REG_LL_MASK                        (0xFFU)
+#define RFSYS_REG_LL_SHIFT                       (0U)
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+
+#define RFSYS_REG_LH_MASK                        (0xFF00U)
+#define RFSYS_REG_LH_SHIFT                       (8U)
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+
+#define RFSYS_REG_HL_MASK                        (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT                       (16U)
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+
+#define RFSYS_REG_HH_MASK                        (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT                       (24U)
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+/*! @} */
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
+  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
+       uint8_t RESERVED_0[4028];
+  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/*! @name ENTRY - Entry */
+/*! @{ */
+
+#define ROM_ENTRY_ENTRY_MASK                     (0xFFFFFFFFU)
+#define ROM_ENTRY_ENTRY_SHIFT                    (0U)
+/*! ENTRY - ENTRY */
+#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
+/*! @} */
+
+/* The count of ROM_ENTRY */
+#define ROM_ENTRY_COUNT                          (3U)
+
+/*! @name TABLEMARK - End of Table Marker Register */
+/*! @{ */
+
+#define ROM_TABLEMARK_MARK_MASK                  (0xFFFFFFFFU)
+#define ROM_TABLEMARK_MARK_SHIFT                 (0U)
+/*! MARK - MARK */
+#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
+/*! @} */
+
+/*! @name SYSACCESS - System Access Register */
+/*! @{ */
+
+#define ROM_SYSACCESS_SYSACCESS_MASK             (0xFFFFFFFFU)
+#define ROM_SYSACCESS_SYSACCESS_SHIFT            (0U)
+/*! SYSACCESS - SYSACCESS */
+#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID4_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID5_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID6_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID7_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID0_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID1_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID2_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+
+#define ROM_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID3_PERIPHID_SHIFT             (0U)
+/*! PERIPHID - PERIPHID */
+#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+
+#define ROM_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define ROM_COMPID_COMPID_SHIFT                  (0U)
+/*! COMPID - Component ID */
+#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of ROM_COMPID */
+#define ROM_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE                                 (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM                                      ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS                           { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS                            { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+/*! @{ */
+
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+/*! TSR - Time Seconds Register */
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+/*! @} */
+
+/*! @name TPR - RTC Time Prescaler Register */
+/*! @{ */
+
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+/*! TPR - Time Prescaler Register */
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+/*! @} */
+
+/*! @name TAR - RTC Time Alarm Register */
+/*! @{ */
+
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+/*! TAR - Time Alarm Register */
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+/*! @} */
+
+/*! @name TCR - RTC Time Compensation Register */
+/*! @{ */
+
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+/*! TCR - Time Compensation Register
+ *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
+ *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
+ *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
+ *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
+ *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
+ */
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+/*! CIR - Compensation Interval Register */
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+/*! TCV - Time Compensation Value */
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+/*! CIC - Compensation Interval Counter */
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+/*! @} */
+
+/*! @name CR - RTC Control Register */
+/*! @{ */
+
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+/*! SWR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.
+ */
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+/*! WPE - Wakeup Pin Enable
+ *  0b0..Wakeup pin is disabled.
+ *  0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
+ */
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+/*! SUP - Supervisor Access
+ *  0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
+ *  0b1..Non-supervisor mode write accesses are supported.
+ */
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+/*! UM - Update Mode
+ *  0b0..Registers cannot be written when locked.
+ *  0b1..Registers can be written when locked under limited conditions.
+ */
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+
+#define RTC_CR_WPS_MASK                          (0x10U)
+#define RTC_CR_WPS_SHIFT                         (4U)
+/*! WPS - Wakeup Pin Select
+ *  0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
+ *  0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+/*! OSCE - Oscillator Enable
+ *  0b0..32.768 kHz oscillator is disabled.
+ *  0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before
+ *       enabling the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+/*! CLKO - Clock Output
+ *  0b0..The 32 kHz clock is output to other peripherals.
+ *  0b1..The 32 kHz clock is not output to other peripherals.
+ */
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+/*! SC16P - Oscillator 16pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+/*! SC8P - Oscillator 8pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+/*! SC4P - Oscillator 4pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+/*! SC2P - Oscillator 2pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+/*! @} */
+
+/*! @name SR - RTC Status Register */
+/*! @{ */
+
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+/*! TIF - Time Invalid Flag
+ *  0b0..Time is valid.
+ *  0b1..Time is invalid and time counter is read as zero.
+ */
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+/*! TOF - Time Overflow Flag
+ *  0b0..Time overflow has not occurred.
+ *  0b1..Time overflow has occurred and time counter is read as zero.
+ */
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+/*! TAF - Time Alarm Flag
+ *  0b0..Time alarm has not occurred.
+ *  0b1..Time alarm has occurred.
+ */
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+/*! TCE - Time Counter Enable
+ *  0b0..Time counter is disabled.
+ *  0b1..Time counter is enabled.
+ */
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+/*! @} */
+
+/*! @name LR - RTC Lock Register */
+/*! @{ */
+
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+/*! TCL - Time Compensation Lock
+ *  0b0..Time Compensation Register is locked and writes are ignored.
+ *  0b1..Time Compensation Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+/*! CRL - Control Register Lock
+ *  0b0..Control Register is locked and writes are ignored.
+ *  0b1..Control Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+/*! SRL - Status Register Lock
+ *  0b0..Status Register is locked and writes are ignored.
+ *  0b1..Status Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+/*! LRL - Lock Register Lock
+ *  0b0..Lock Register is locked and writes are ignored.
+ *  0b1..Lock Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+/*! @} */
+
+/*! @name IER - RTC Interrupt Enable Register */
+/*! @{ */
+
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+/*! TIIE - Time Invalid Interrupt Enable
+ *  0b0..Time invalid flag does not generate an interrupt.
+ *  0b1..Time invalid flag does generate an interrupt.
+ */
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+/*! TOIE - Time Overflow Interrupt Enable
+ *  0b0..Time overflow flag does not generate an interrupt.
+ *  0b1..Time overflow flag does generate an interrupt.
+ */
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+/*! TAIE - Time Alarm Interrupt Enable
+ *  0b0..Time alarm flag does not generate an interrupt.
+ *  0b1..Time alarm flag does generate an interrupt.
+ */
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+/*! TSIE - Time Seconds Interrupt Enable
+ *  0b0..Seconds interrupt is disabled.
+ *  0b1..Seconds interrupt is enabled.
+ */
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+/*! WPON - Wakeup Pin On
+ *  0b0..No effect.
+ *  0b1..If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+       uint8_t RESERVED_6[4];
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+       uint8_t RESERVED_7[156];
+  __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
+  __O  uint32_t SRVCOP;                            /**< Service COP, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+/*! @{ */
+
+#define SIM_SOPT1_OSC32KOUT_MASK                 (0x30000U)
+#define SIM_SOPT1_OSC32KOUT_SHIFT                (16U)
+/*! OSC32KOUT - 32K oscillator clock output
+ *  0b00..ERCLK32K is not output.
+ *  0b01..ERCLK32K is output on PTE0.
+ *  0b10..ERCLK32K is output on PTE26.
+ *  0b11..Reserved.
+ */
+#define SIM_SOPT1_OSC32KOUT(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
+
+#define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
+/*! OSC32KSEL - 32K Oscillator Clock Select
+ *  0b00..System oscillator (OSC32KCLK)
+ *  0b01..Reserved
+ *  0b10..RTC_CLKIN
+ *  0b11..LPO 1kHz
+ */
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+
+#define SIM_SOPT1_USBVSTBY_MASK                  (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT                 (29U)
+/*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes
+ *  0b0..USB voltage regulator not in standby during VLPR and VLPW modes.
+ *  0b1..USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+
+#define SIM_SOPT1_USBSSTBY_MASK                  (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT                 (30U)
+/*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
+ *  0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
+ *  0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
+ */
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+
+#define SIM_SOPT1_USBREGEN_MASK                  (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT                 (31U)
+/*! USBREGEN - USB voltage regulator enable
+ *  0b0..USB voltage regulator is disabled.
+ *  0b1..USB voltage regulator is enabled.
+ */
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+/*! @} */
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+/*! @{ */
+
+#define SIM_SOPT1CFG_URWE_MASK                   (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT                  (24U)
+/*! URWE - USB voltage regulator enable write enable
+ *  0b0..SOPT1 USBREGEN cannot be written.
+ *  0b1..SOPT1 USBREGEN can be written.
+ */
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+
+#define SIM_SOPT1CFG_UVSWE_MASK                  (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 (25U)
+/*! UVSWE - USB voltage regulator VLP standby write enable
+ *  0b0..SOPT1 USBVSTB cannot be written.
+ *  0b1..SOPT1 USBVSTB can be written.
+ */
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+
+#define SIM_SOPT1CFG_USSWE_MASK                  (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT                 (26U)
+/*! USSWE - USB voltage regulator stop standby write enable
+ *  0b0..SOPT1 USBSSTB cannot be written.
+ *  0b1..SOPT1 USBSSTB can be written.
+ */
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+/*! @} */
+
+/*! @name SOPT2 - System Options Register 2 */
+/*! @{ */
+
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             (4U)
+/*! RTCCLKOUTSEL - RTC Clock Out Select
+ *  0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ *  0b1..OSCERCLK clock is output on the RTC_CLKOUT pin.
+ */
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+
+#define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
+/*! CLKOUTSEL - CLKOUT select
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Bus clock
+ *  0b011..LPO clock (1 kHz)
+ *  0b100..LIRC_CLK
+ *  0b101..Reserved
+ *  0b110..OSCERCLK
+ *  0b111..IRC48M clock (IRC48M clock can be output to PAD only when chip VDD is 2.7-3.6 V)
+ */
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+
+#define SIM_SOPT2_USBSRC_MASK                    (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT                   (18U)
+/*! USBSRC - USB clock source select
+ *  0b0..External bypass clock (USB_CLKIN).
+ *  0b1..IRC48M clock
+ */
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+
+#define SIM_SOPT2_FLEXIOSRC_MASK                 (0xC00000U)
+#define SIM_SOPT2_FLEXIOSRC_SHIFT                (22U)
+/*! FLEXIOSRC - FlexIO Module Clock Source Select
+ *  0b00..Clock disabled
+ *  0b01..IRC48M clock
+ *  0b10..OSCERCLK clock
+ *  0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_FLEXIOSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
+
+#define SIM_SOPT2_TPMSRC_MASK                    (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT                   (24U)
+/*! TPMSRC - TPM Clock Source Select
+ *  0b00..Clock disabled
+ *  0b01..IRC48M clock
+ *  0b10..OSCERCLK clock
+ *  0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+
+#define SIM_SOPT2_LPUART0SRC_MASK                (0xC000000U)
+#define SIM_SOPT2_LPUART0SRC_SHIFT               (26U)
+/*! LPUART0SRC - LPUART0 Clock Source Select
+ *  0b00..Clock disabled
+ *  0b01..IRC48M clock
+ *  0b10..OSCERCLK clock
+ *  0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_LPUART0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
+
+#define SIM_SOPT2_LPUART1SRC_MASK                (0x30000000U)
+#define SIM_SOPT2_LPUART1SRC_SHIFT               (28U)
+/*! LPUART1SRC - LPUART1 Clock Source Select
+ *  0b00..Clock disabled
+ *  0b01..IRC48M clock
+ *  0b10..OSCERCLK clock
+ *  0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_LPUART1SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK)
+/*! @} */
+
+/*! @name SOPT4 - System Options Register 4 */
+/*! @{ */
+
+#define SIM_SOPT4_TPM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT               (18U)
+/*! TPM1CH0SRC - TPM1 channel 0 input capture source select
+ *  0b00..TPM1_CH0 signal
+ *  0b01..CMP0 output
+ *  0b10..Reserved
+ *  0b11..USB start of frame pulse
+ */
+#define SIM_SOPT4_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
+
+#define SIM_SOPT4_TPM2CH0SRC_MASK                (0x100000U)
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT               (20U)
+/*! TPM2CH0SRC - TPM2 Channel 0 Input Capture Source Select
+ *  0b0..TPM2_CH0 signal
+ *  0b1..CMP0 output
+ */
+#define SIM_SOPT4_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
+
+#define SIM_SOPT4_TPM0CLKSEL_MASK                (0x1000000U)
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT               (24U)
+/*! TPM0CLKSEL - TPM0 External Clock Pin Select
+ *  0b0..TPM0 external clock driven by TPM_CLKIN0 pin.
+ *  0b1..TPM0 external clock driven by TPM_CLKIN1 pin.
+ */
+#define SIM_SOPT4_TPM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
+
+#define SIM_SOPT4_TPM1CLKSEL_MASK                (0x2000000U)
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT               (25U)
+/*! TPM1CLKSEL - TPM1 External Clock Pin Select
+ *  0b0..TPM1 external clock driven by TPM_CLKIN0 pin.
+ *  0b1..TPM1 external clock driven by TPM_CLKIN1 pin.
+ */
+#define SIM_SOPT4_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
+
+#define SIM_SOPT4_TPM2CLKSEL_MASK                (0x4000000U)
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT               (26U)
+/*! TPM2CLKSEL - TPM2 External Clock Pin Select
+ *  0b0..TPM2 external clock driven by TPM_CLKIN0 pin.
+ *  0b1..TPM2 external clock driven by TPM_CLKIN1 pin.
+ */
+#define SIM_SOPT4_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
+/*! @} */
+
+/*! @name SOPT5 - System Options Register 5 */
+/*! @{ */
+
+#define SIM_SOPT5_LPUART0TXSRC_MASK              (0x3U)
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT             (0U)
+/*! LPUART0TXSRC - LPUART0 Transmit Data Source Select
+ *  0b00..LPUART0_TX pin
+ *  0b01..LPUART0_TX pin modulated with TPM1 channel 0 output
+ *  0b10..LPUART0_TX pin modulated with TPM2 channel 0 output
+ *  0b11..Reserved
+ */
+#define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+
+#define SIM_SOPT5_LPUART0RXSRC_MASK              (0x4U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT             (2U)
+/*! LPUART0RXSRC - LPUART0 Receive Data Source Select
+ *  0b0..LPUART_RX pin
+ *  0b1..CMP0 output
+ */
+#define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+
+#define SIM_SOPT5_LPUART1TXSRC_MASK              (0x30U)
+#define SIM_SOPT5_LPUART1TXSRC_SHIFT             (4U)
+/*! LPUART1TXSRC - LPUART1 Transmit Data Source Select
+ *  0b00..LPUART1_TX pin
+ *  0b01..LPUART1_TX pin modulated with TPM1 channel 0 output
+ *  0b10..LPUART1_TX pin modulated with TPM2 channel 0 output
+ *  0b11..Reserved
+ */
+#define SIM_SOPT5_LPUART1TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
+
+#define SIM_SOPT5_LPUART1RXSRC_MASK              (0x40U)
+#define SIM_SOPT5_LPUART1RXSRC_SHIFT             (6U)
+/*! LPUART1RXSRC - LPUART1 Receive Data Source Select
+ *  0b0..LPUART1_RX pin
+ *  0b1..CMP0 output
+ */
+#define SIM_SOPT5_LPUART1RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
+
+#define SIM_SOPT5_LPUART0ODE_MASK                (0x10000U)
+#define SIM_SOPT5_LPUART0ODE_SHIFT               (16U)
+/*! LPUART0ODE - LPUART0 Open Drain Enable
+ *  0b0..Open drain is disabled on LPUART0.
+ *  0b1..Open drain is enabled on LPUART0.
+ */
+#define SIM_SOPT5_LPUART0ODE(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
+
+#define SIM_SOPT5_LPUART1ODE_MASK                (0x20000U)
+#define SIM_SOPT5_LPUART1ODE_SHIFT               (17U)
+/*! LPUART1ODE - LPUART1 Open Drain Enable
+ *  0b0..Open drain is disabled on LPUART1.
+ *  0b1..Open drain is enabled on LPUART1
+ */
+#define SIM_SOPT5_LPUART1ODE(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK)
+
+#define SIM_SOPT5_UART2ODE_MASK                  (0x40000U)
+#define SIM_SOPT5_UART2ODE_SHIFT                 (18U)
+/*! UART2ODE - UART2 Open Drain Enable
+ *  0b0..Open drain is disabled on UART2
+ *  0b1..Open drain is enabled on UART2
+ */
+#define SIM_SOPT5_UART2ODE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
+/*! @} */
+
+/*! @name SOPT7 - System Options Register 7 */
+/*! @{ */
+
+#define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
+/*! ADC0TRGSEL - ADC0 Trigger Select
+ *  0b0000..External trigger pin input (EXTRG_IN)
+ *  0b0001..CMP0 output
+ *  0b0010..Reserved
+ *  0b0011..Reserved
+ *  0b0100..PIT trigger 0
+ *  0b0101..PIT trigger 1
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ *  0b1000..TPM0 overflow
+ *  0b1001..TPM1 overflow
+ *  0b1010..TPM2 overflow
+ *  0b1011..Reserved
+ *  0b1100..RTC alarm
+ *  0b1101..RTC seconds
+ *  0b1110..LPTMR0 trigger
+ *  0b1111..Reserved
+ */
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
+/*! ADC0PRETRGSEL - ADC0 Pretrigger Select
+ *  0b0..Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion
+ *       and store the result in ADC0_RA register.
+ *  0b1..Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion
+ *       and store the result in ADC0_RB register.
+ */
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
+/*! ADC0ALTTRGEN - ADC0 Alternate Trigger Enable
+ *  0b0..ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a
+ *       pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and
+ *       store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will
+ *       be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in
+ *       ADCx_RB Register.
+ *  0b1..ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select
+ *       the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result
+ *       regsiter to store the ADC conversion.
+ */
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+/*! @} */
+
+/*! @name SDID - System Device Identification Register */
+/*! @{ */
+
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+/*! PINID - Pincount Identification
+ *  0b0010..32-pin
+ *  0b0100..48-pin
+ *  0b0101..64-pin
+ *  0b1011..Custom pinout (WLCSP)
+ */
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+/*! REVID - Device Revision Number */
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+
+#define SIM_SDID_SRAMSIZE_MASK                   (0xF0000U)
+#define SIM_SDID_SRAMSIZE_SHIFT                  (16U)
+/*! SRAMSIZE - System SRAM Size
+ *  0b0101..16 KB
+ *  0b0110..32 KB
+ */
+#define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
+
+#define SIM_SDID_SERIESID_MASK                   (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT                  (20U)
+/*! SERIESID - Kinetis Series ID
+ *  0b0001..KL family
+ */
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+/*! SUBFAMID - TBD Sub-Family ID
+ *  0b0011..TBD Subfamily
+ */
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+
+#define SIM_SDID_FAMID_MASK                      (0xF0000000U)
+#define SIM_SDID_FAMID_SHIFT                     (28U)
+/*! FAMID
+ *  0b0001..TBD
+ *  0b0010..TBD
+ *  0b0011..TBD
+ *  0b0100..TBD
+ */
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+/*! @} */
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+/*! @{ */
+
+#define SIM_SCGC4_I2C0_MASK                      (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT                     (6U)
+/*! I2C0 - I2C0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+
+#define SIM_SCGC4_I2C1_MASK                      (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT                     (7U)
+/*! I2C1 - I2C1 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+
+#define SIM_SCGC4_UART2_MASK                     (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT                    (12U)
+/*! UART2 - UART2 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+
+#define SIM_SCGC4_USBFS_MASK                     (0x40000U)
+#define SIM_SCGC4_USBFS_SHIFT                    (18U)
+/*! USBFS - USB Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_USBFS(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK)
+
+#define SIM_SCGC4_CMP0_MASK                      (0x80000U)
+#define SIM_SCGC4_CMP0_SHIFT                     (19U)
+/*! CMP0 - Comparator Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK)
+
+#define SIM_SCGC4_VREF_MASK                      (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT                     (20U)
+/*! VREF - VREF Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+#define SIM_SCGC4_SPI0_MASK                      (0x400000U)
+#define SIM_SCGC4_SPI0_SHIFT                     (22U)
+/*! SPI0 - SPI0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
+
+#define SIM_SCGC4_SPI1_MASK                      (0x800000U)
+#define SIM_SCGC4_SPI1_SHIFT                     (23U)
+/*! SPI1 - SPI1 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC4_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
+/*! @} */
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+/*! @{ */
+
+#define SIM_SCGC5_LPTMR_MASK                     (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT                    (0U)
+/*! LPTMR - Low Power Timer Access Control
+ *  0b0..Access disabled
+ *  0b1..Access enabled
+ */
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+
+#define SIM_SCGC5_PORTA_MASK                     (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT                    (9U)
+/*! PORTA - Port A Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+
+#define SIM_SCGC5_PORTB_MASK                     (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT                    (10U)
+/*! PORTB - Port B Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+
+#define SIM_SCGC5_PORTC_MASK                     (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT                    (11U)
+/*! PORTC - Port C Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+
+#define SIM_SCGC5_PORTD_MASK                     (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT                    (12U)
+/*! PORTD - Port D Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+
+#define SIM_SCGC5_PORTE_MASK                     (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT                    (13U)
+/*! PORTE - Port E Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+#define SIM_SCGC5_SLCD_MASK                      (0x80000U)
+#define SIM_SCGC5_SLCD_SHIFT                     (19U)
+/*! SLCD - Segment LCD Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_SLCD(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SLCD_SHIFT)) & SIM_SCGC5_SLCD_MASK)
+
+#define SIM_SCGC5_LPUART0_MASK                   (0x100000U)
+#define SIM_SCGC5_LPUART0_SHIFT                  (20U)
+/*! LPUART0 - LPUART0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
+
+#define SIM_SCGC5_LPUART1_MASK                   (0x200000U)
+#define SIM_SCGC5_LPUART1_SHIFT                  (21U)
+/*! LPUART1 - LPUART1 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_LPUART1(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK)
+
+#define SIM_SCGC5_FLEXIO_MASK                    (0x80000000U)
+#define SIM_SCGC5_FLEXIO_SHIFT                   (31U)
+/*! FLEXIO - FlexIO Module
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC5_FLEXIO(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK)
+/*! @} */
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+/*! @{ */
+
+#define SIM_SCGC6_FTF_MASK                       (0x1U)
+#define SIM_SCGC6_FTF_SHIFT                      (0U)
+/*! FTF - Flash Memory Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+
+#define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
+/*! DMAMUX - DMA Mux Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+
+#define SIM_SCGC6_I2S_MASK                       (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT                      (15U)
+/*! I2S - I2S Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+
+#define SIM_SCGC6_PIT_MASK                       (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT                      (23U)
+/*! PIT - PIT Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+
+#define SIM_SCGC6_TPM0_MASK                      (0x1000000U)
+#define SIM_SCGC6_TPM0_SHIFT                     (24U)
+/*! TPM0 - TPM0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_TPM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
+
+#define SIM_SCGC6_TPM1_MASK                      (0x2000000U)
+#define SIM_SCGC6_TPM1_SHIFT                     (25U)
+/*! TPM1 - TPM1 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_TPM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
+
+#define SIM_SCGC6_TPM2_MASK                      (0x4000000U)
+#define SIM_SCGC6_TPM2_SHIFT                     (26U)
+/*! TPM2 - TPM2 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_TPM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
+
+#define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT                     (27U)
+/*! ADC0 - ADC0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+
+#define SIM_SCGC6_RTC_MASK                       (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT                      (29U)
+/*! RTC - RTC Access Control
+ *  0b0..Access and interrupts disabled
+ *  0b1..Access and interrupts enabled
+ */
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+
+#define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT                     (31U)
+/*! DAC0 - DAC0 Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+/*! @} */
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+/*! @{ */
+
+#define SIM_SCGC7_DMA_MASK                       (0x100U)
+#define SIM_SCGC7_DMA_SHIFT                      (8U)
+/*! DMA - DMA Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+/*! @} */
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+/*! @{ */
+
+#define SIM_CLKDIV1_OUTDIV4_MASK                 (0x70000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
+/*! OUTDIV4 - Clock 4 Output Divider value
+ *  0b000..Divide-by-1.
+ *  0b001..Divide-by-2.
+ *  0b010..Divide-by-3.
+ *  0b011..Divide-by-4.
+ *  0b100..Divide-by-5.
+ *  0b101..Divide-by-6.
+ *  0b110..Divide-by-7.
+ *  0b111..Divide-by-8.
+ */
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+
+#define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
+/*! OUTDIV1 - Clock 1 Output Divider value
+ *  0b0000..Divide-by-1.
+ *  0b0001..Divide-by-2.
+ *  0b0010..Divide-by-3.
+ *  0b0011..Divide-by-4.
+ *  0b0100..Divide-by-5.
+ *  0b0101..Divide-by-6.
+ *  0b0110..Divide-by-7.
+ *  0b0111..Divide-by-8.
+ *  0b1000..Divide-by-9.
+ *  0b1001..Divide-by-10.
+ *  0b1010..Divide-by-11.
+ *  0b1011..Divide-by-12.
+ *  0b1100..Divide-by-13.
+ *  0b1101..Divide-by-14.
+ *  0b1110..Divide-by-15.
+ *  0b1111..Divide-by-16.
+ */
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+/*! @} */
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+/*! @{ */
+
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+/*! FLASHDIS - Flash Disable
+ *  0b0..Flash is enabled.
+ *  0b1..Flash is disabled.
+ */
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+/*! FLASHDOZE - Flash Doze
+ *  0b0..Flash remains enabled during Doze mode.
+ *  0b1..Flash is disabled for the duration of Doze mode.
+ */
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+
+#define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
+/*! PFSIZE - Program Flash Size
+ *  0b0000..8 KB of program flash memory, 1 KB protection region
+ *  0b0001..16 KB of program flash memory, 1 KB protection region
+ *  0b0011..32 KB of program flash memory, 1 KB protection region
+ *  0b0101..64 KB of program flash memory, 2 KB protection region
+ *  0b0111..128 KB of program flash memory, 4 KB protection region
+ *  0b1001..256 KB of program flash memory, 8 KB protection region
+ *  0b1111..256 KB of program flash memory, 8 KB protection region
+ */
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+/*! @} */
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+/*! @{ */
+
+#define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+
+#define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
+/*! MAXADDR0 - Max Address lock */
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+/*! @} */
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+/*! @{ */
+
+#define SIM_UIDMH_UID_MASK                       (0xFFFFU)
+#define SIM_UIDMH_UID_SHIFT                      (0U)
+/*! UID - Unique Identification */
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+/*! @} */
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+/*! @{ */
+
+#define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT                      (0U)
+/*! UID - Unique Identification */
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+/*! @} */
+
+/*! @name UIDL - Unique Identification Register Low */
+/*! @{ */
+
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+/*! UID - Unique Identification */
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+/*! @} */
+
+/*! @name COPC - COP Control Register */
+/*! @{ */
+
+#define SIM_COPC_COPW_MASK                       (0x1U)
+#define SIM_COPC_COPW_SHIFT                      (0U)
+/*! COPW - COP Windowed Mode
+ *  0b0..Normal mode
+ *  0b1..Windowed mode
+ */
+#define SIM_COPC_COPW(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
+
+#define SIM_COPC_COPCLKS_MASK                    (0x2U)
+#define SIM_COPC_COPCLKS_SHIFT                   (1U)
+/*! COPCLKS - COP Clock Select
+ *  0b0..COP configured for short timeout
+ *  0b1..COP configured for long timeout
+ */
+#define SIM_COPC_COPCLKS(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
+
+#define SIM_COPC_COPT_MASK                       (0xCU)
+#define SIM_COPC_COPT_SHIFT                      (2U)
+/*! COPT - COP Watchdog Timeout
+ *  0b00..COP disabled
+ *  0b01..COP timeout after 25 cycles for short timeout or 213 cycles for long timeout
+ *  0b10..COP timeout after 28 cycles for short timeout or 216 cycles for long timeout
+ *  0b11..COP timeout after 210 cycles for short timeout or 218 cycles for long timeout
+ */
+#define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
+
+#define SIM_COPC_COPSTPEN_MASK                   (0x10U)
+#define SIM_COPC_COPSTPEN_SHIFT                  (4U)
+/*! COPSTPEN - COP Stop Enable
+ *  0b0..COP is disabled and the counter is reset in Stop modes
+ *  0b1..COP is enabled in Stop modes
+ */
+#define SIM_COPC_COPSTPEN(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
+
+#define SIM_COPC_COPDBGEN_MASK                   (0x20U)
+#define SIM_COPC_COPDBGEN_SHIFT                  (5U)
+/*! COPDBGEN - COP Debug Enable
+ *  0b0..COP is disabled and the counter is reset in Debug mode
+ *  0b1..COP is enabled in Debug mode
+ */
+#define SIM_COPC_COPDBGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
+
+#define SIM_COPC_COPCLKSEL_MASK                  (0xC0U)
+#define SIM_COPC_COPCLKSEL_SHIFT                 (6U)
+/*! COPCLKSEL - COP Clock Select
+ *  0b00..LPO clock (1 kHz)
+ *  0b01..MCGIRCLK
+ *  0b10..OSCERCLK
+ *  0b11..Bus clock
+ */
+#define SIM_COPC_COPCLKSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
+/*! @} */
+
+/*! @name SRVCOP - Service COP */
+/*! @{ */
+
+#define SIM_SRVCOP_SRVCOP_MASK                   (0xFFU)
+#define SIM_SRVCOP_SRVCOP_SHIFT                  (0U)
+/*! SRVCOP - Service COP Register */
+#define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+/*! @{ */
+
+#define SMC_PMPROT_AVLLS_MASK                    (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (1U)
+/*! AVLLS - Allow Very-Low-Leakage Stop Mode
+ *  0b0..Any VLLSx mode is not allowed
+ *  0b1..Any VLLSx mode is allowed
+ */
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+/*! ALLS - Allow Low-Leakage Stop Mode
+ *  0b0..LLS is not allowed
+ *  0b1..LLS is allowed
+ */
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+/*! AVLP - Allow Very-Low-Power Modes
+ *  0b0..VLPR, VLPW, and VLPS are not allowed.
+ *  0b1..VLPR, VLPW, and VLPS are allowed.
+ */
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control register */
+/*! @{ */
+
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+/*! STOPM - Stop Mode Control
+ *  0b000..Normal Stop (STOP)
+ *  0b001..Reserved
+ *  0b010..Very-Low-Power Stop (VLPS)
+ *  0b011..Low-Leakage Stop (LLS)
+ *  0b100..Very-Low-Leakage Stop (VLLSx)
+ *  0b101..Reserved
+ *  0b110..Reseved
+ *  0b111..Reserved
+ */
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+
+#define SMC_PMCTRL_STOPA_MASK                    (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT                   (3U)
+/*! STOPA - Stop Aborted
+ *  0b0..The previous stop mode entry was successsful.
+ *  0b1..The previous stop mode entry was aborted.
+ */
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+
+#define SMC_PMCTRL_RUNM_MASK                     (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (5U)
+/*! RUNM - Run Mode Control
+ *  0b00..Normal Run mode (RUN)
+ *  0b01..Reserved
+ *  0b10..Very-Low-Power Run mode (VLPR)
+ *  0b11..Reserved
+ */
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+/*! @} */
+
+/*! @name STOPCTRL - Stop Control Register */
+/*! @{ */
+
+#define SMC_STOPCTRL_VLLSM_MASK                  (0x7U)
+#define SMC_STOPCTRL_VLLSM_SHIFT                 (0U)
+/*! VLLSM - VLLS Mode Control
+ *  0b000..VLLS0
+ *  0b001..VLLS1
+ *  0b010..Reserved
+ *  0b011..VLLS3
+ *  0b100..Reserved
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define SMC_STOPCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
+
+#define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
+/*! PORPO - POR Power Option
+ *  0b0..POR detect circuit is enabled in VLLS0
+ *  0b1..POR detect circuit is disabled in VLLS0
+ */
+#define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+
+#define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
+/*! PSTOPO - Partial Stop Option
+ *  0b00..STOP - Normal Stop mode
+ *  0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
+ *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ *  0b11..Reserved
+ */
+#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+/*! @} */
+
+/*! @name PMSTAT - Power Mode Status register */
+/*! @{ */
+
+#define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+/*! PMSTAT - Power Mode Status */
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t S;                                  /**< SPI Status Register, offset: 0x0 */
+  __IO uint8_t BR;                                 /**< SPI Baud Rate Register, offset: 0x1 */
+  __IO uint8_t C2;                                 /**< SPI Control Register 2, offset: 0x2 */
+  __IO uint8_t C1;                                 /**< SPI Control Register 1, offset: 0x3 */
+  __IO uint8_t ML;                                 /**< SPI Match Register low, offset: 0x4 */
+  __IO uint8_t MH;                                 /**< SPI match register high, offset: 0x5 */
+  __IO uint8_t DL;                                 /**< SPI Data Register low, offset: 0x6 */
+  __IO uint8_t DH;                                 /**< SPI data register high, offset: 0x7 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t CI;                                 /**< SPI clear interrupt register, offset: 0xA, available only on: SPI1 (missing on SPI0) */
+  __IO uint8_t C3;                                 /**< SPI control register 3, offset: 0xB, available only on: SPI1 (missing on SPI0) */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name S - SPI Status Register */
+/*! @{ */
+
+#define SPI_S_RFIFOEF_MASK                       (0x1U)
+#define SPI_S_RFIFOEF_SHIFT                      (0U)
+/*! RFIFOEF - SPI read FIFO empty flag
+ *  0b0..Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
+ *  0b1..Read FIFO is empty.
+ */
+#define SPI_S_RFIFOEF(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
+
+#define SPI_S_TXFULLF_MASK                       (0x2U)
+#define SPI_S_TXFULLF_SHIFT                      (1U)
+/*! TXFULLF - Transmit FIFO full flag
+ *  0b0..Transmit FIFO has less than 8 bytes
+ *  0b1..Transmit FIFO has 8 bytes of data
+ */
+#define SPI_S_TXFULLF(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
+
+#define SPI_S_TNEAREF_MASK                       (0x4U)
+#define SPI_S_TNEAREF_SHIFT                      (2U)
+/*! TNEAREF - Transmit FIFO nearly empty flag
+ *  0b0..Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
+ *  0b1..Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits
+ *       (when C3[TNEAREF_MARK] is 1) remaining to transmit
+ */
+#define SPI_S_TNEAREF(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
+
+#define SPI_S_RNFULLF_MASK                       (0x8U)
+#define SPI_S_RNFULLF_SHIFT                      (3U)
+/*! RNFULLF - Receive FIFO nearly full flag
+ *  0b0..Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)
+ *  0b1..Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0)
+ *       or 32 bits (when C3[RNFULLF_MARK] is 1)
+ */
+#define SPI_S_RNFULLF(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
+
+#define SPI_S_MODF_MASK                          (0x10U)
+#define SPI_S_MODF_SHIFT                         (4U)
+/*! MODF - Master Mode Fault Flag
+ *  0b0..No mode fault error
+ *  0b1..Mode fault error detected
+ */
+#define SPI_S_MODF(x)                            (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
+
+#define SPI_S_SPTEF_MASK                         (0x20U)
+#define SPI_S_SPTEF_SHIFT                        (5U)
+/*! SPTEF - SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI
+ *    transmit FIFO empty flag (when FIFO is supported and enabled)
+ *  0b0..SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
+ *  0b1..SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
+ */
+#define SPI_S_SPTEF(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
+
+#define SPI_S_SPMF_MASK                          (0x40U)
+#define SPI_S_SPMF_SHIFT                         (6U)
+/*! SPMF - SPI Match Flag
+ *  0b0..Value in the receive data buffer does not match the value in the MH:ML registers
+ *  0b1..Value in the receive data buffer matches the value in the MH:ML registers
+ */
+#define SPI_S_SPMF(x)                            (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
+
+#define SPI_S_SPRF_MASK                          (0x80U)
+#define SPI_S_SPRF_SHIFT                         (7U)
+/*! SPRF - SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO
+ *    FULL flag (when FIFO is supported and enabled)
+ *  0b0..No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
+ *  0b1..Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
+ */
+#define SPI_S_SPRF(x)                            (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
+/*! @} */
+
+/*! @name BR - SPI Baud Rate Register */
+/*! @{ */
+
+#define SPI_BR_SPR_MASK                          (0xFU)
+#define SPI_BR_SPR_SHIFT                         (0U)
+/*! SPR - SPI Baud Rate Divisor
+ *  0b0000..Baud rate divisor is 2.
+ *  0b0001..Baud rate divisor is 4.
+ *  0b0010..Baud rate divisor is 8.
+ *  0b0011..Baud rate divisor is 16.
+ *  0b0100..Baud rate divisor is 32.
+ *  0b0101..Baud rate divisor is 64.
+ *  0b0110..Baud rate divisor is 128.
+ *  0b0111..Baud rate divisor is 256.
+ *  0b1000..Baud rate divisor is 512.
+ */
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
+
+#define SPI_BR_SPPR_MASK                         (0x70U)
+#define SPI_BR_SPPR_SHIFT                        (4U)
+/*! SPPR - SPI Baud Rate Prescale Divisor
+ *  0b000..Baud rate prescaler divisor is 1.
+ *  0b001..Baud rate prescaler divisor is 2.
+ *  0b010..Baud rate prescaler divisor is 3.
+ *  0b011..Baud rate prescaler divisor is 4.
+ *  0b100..Baud rate prescaler divisor is 5.
+ *  0b101..Baud rate prescaler divisor is 6.
+ *  0b110..Baud rate prescaler divisor is 7.
+ *  0b111..Baud rate prescaler divisor is 8.
+ */
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
+/*! @} */
+
+/*! @name C2 - SPI Control Register 2 */
+/*! @{ */
+
+#define SPI_C2_SPC0_MASK                         (0x1U)
+#define SPI_C2_SPC0_SHIFT                        (0U)
+/*! SPC0 - SPI Pin Control 0
+ *  0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation:
+ *       MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave
+ *       in.
+ *  0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of
+ *       operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In
+ *       slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not
+ *       used by SPI.
+ */
+#define SPI_C2_SPC0(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
+
+#define SPI_C2_SPISWAI_MASK                      (0x2U)
+#define SPI_C2_SPISWAI_SHIFT                     (1U)
+/*! SPISWAI - SPI Stop in Wait Mode
+ *  0b0..SPI clocks continue to operate in Wait mode.
+ *  0b1..SPI clocks stop when the MCU enters Wait mode.
+ */
+#define SPI_C2_SPISWAI(x)                        (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
+
+#define SPI_C2_RXDMAE_MASK                       (0x4U)
+#define SPI_C2_RXDMAE_SHIFT                      (2U)
+/*! RXDMAE - Receive DMA enable
+ *  0b0..DMA request for receive is disabled and interrupt from SPRF is allowed
+ *  0b1..DMA request for receive is enabled and interrupt from SPRF is disabled
+ */
+#define SPI_C2_RXDMAE(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
+
+#define SPI_C2_BIDIROE_MASK                      (0x8U)
+#define SPI_C2_BIDIROE_SHIFT                     (3U)
+/*! BIDIROE - Bidirectional Mode Output Enable
+ *  0b0..Output driver disabled so SPI data I/O pin acts as an input
+ *  0b1..SPI I/O pin enabled as an output
+ */
+#define SPI_C2_BIDIROE(x)                        (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
+
+#define SPI_C2_MODFEN_MASK                       (0x10U)
+#define SPI_C2_MODFEN_SHIFT                      (4U)
+/*! MODFEN - Master Mode-Fault Function Enable
+ *  0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
+ *  0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
+ */
+#define SPI_C2_MODFEN(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
+
+#define SPI_C2_TXDMAE_MASK                       (0x20U)
+#define SPI_C2_TXDMAE_SHIFT                      (5U)
+/*! TXDMAE - Transmit DMA enable
+ *  0b0..DMA request for transmit is disabled and interrupt from SPTEF is allowed
+ *  0b1..DMA request for transmit is enabled and interrupt from SPTEF is disabled
+ */
+#define SPI_C2_TXDMAE(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
+
+#define SPI_C2_SPIMODE_MASK                      (0x40U)
+#define SPI_C2_SPIMODE_SHIFT                     (6U)
+/*! SPIMODE - SPI 8-bit or 16-bit mode
+ *  0b0..8-bit SPI shift register, match register, and buffers
+ *  0b1..16-bit SPI shift register, match register, and buffers
+ */
+#define SPI_C2_SPIMODE(x)                        (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
+
+#define SPI_C2_SPMIE_MASK                        (0x80U)
+#define SPI_C2_SPMIE_SHIFT                       (7U)
+/*! SPMIE - SPI Match Interrupt Enable
+ *  0b0..Interrupts from SPMF inhibited (use polling)
+ *  0b1..When SPMF is 1, requests a hardware interrupt
+ */
+#define SPI_C2_SPMIE(x)                          (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
+/*! @} */
+
+/*! @name C1 - SPI Control Register 1 */
+/*! @{ */
+
+#define SPI_C1_LSBFE_MASK                        (0x1U)
+#define SPI_C1_LSBFE_SHIFT                       (0U)
+/*! LSBFE - LSB First (shifter direction)
+ *  0b0..SPI serial data transfers start with the most significant bit.
+ *  0b1..SPI serial data transfers start with the least significant bit.
+ */
+#define SPI_C1_LSBFE(x)                          (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
+
+#define SPI_C1_SSOE_MASK                         (0x2U)
+#define SPI_C1_SSOE_SHIFT                        (1U)
+/*! SSOE - Slave Select Output Enable
+ *  0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS
+ *       pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for
+ *       mode fault. In slave mode, SS pin function is slave select input.
+ *  0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS
+ *       pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS
+ *       output. In slave mode: SS pin function is slave select input.
+ */
+#define SPI_C1_SSOE(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
+
+#define SPI_C1_CPHA_MASK                         (0x4U)
+#define SPI_C1_CPHA_SHIFT                        (2U)
+/*! CPHA - Clock Phase
+ *  0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
+ *  0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer.
+ */
+#define SPI_C1_CPHA(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
+
+#define SPI_C1_CPOL_MASK                         (0x8U)
+#define SPI_C1_CPOL_SHIFT                        (3U)
+/*! CPOL - Clock Polarity
+ *  0b0..Active-high SPI clock (idles low)
+ *  0b1..Active-low SPI clock (idles high)
+ */
+#define SPI_C1_CPOL(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
+
+#define SPI_C1_MSTR_MASK                         (0x10U)
+#define SPI_C1_MSTR_SHIFT                        (4U)
+/*! MSTR - Master/Slave Mode Select
+ *  0b0..SPI module configured as a slave SPI device
+ *  0b1..SPI module configured as a master SPI device
+ */
+#define SPI_C1_MSTR(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
+
+#define SPI_C1_SPTIE_MASK                        (0x20U)
+#define SPI_C1_SPTIE_SHIFT                       (5U)
+/*! SPTIE - SPI Transmit Interrupt Enable
+ *  0b0..Interrupts from SPTEF inhibited (use polling)
+ *  0b1..When SPTEF is 1, hardware interrupt requested
+ */
+#define SPI_C1_SPTIE(x)                          (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
+
+#define SPI_C1_SPE_MASK                          (0x40U)
+#define SPI_C1_SPE_SHIFT                         (6U)
+/*! SPE - SPI System Enable
+ *  0b0..SPI system inactive
+ *  0b1..SPI system enabled
+ */
+#define SPI_C1_SPE(x)                            (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
+
+#define SPI_C1_SPIE_MASK                         (0x80U)
+#define SPI_C1_SPIE_SHIFT                        (7U)
+/*! SPIE - SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or
+ *    for read FIFO (when FIFO is supported and enabled)
+ *  0b0..Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read
+ *       FIFO Full Interrupts are disabled (when FIFOMODE is 1)
+ *  0b1..Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO
+ *       Full Interrupts are enabled (when FIFOMODE is 1)
+ */
+#define SPI_C1_SPIE(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
+/*! @} */
+
+/*! @name ML - SPI Match Register low */
+/*! @{ */
+
+#define SPI_ML_Bits_MASK                         (0xFFU)
+#define SPI_ML_Bits_SHIFT                        (0U)
+/*! Bits - Hardware compare value (low byte) */
+#define SPI_ML_Bits(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
+/*! @} */
+
+/*! @name MH - SPI match register high */
+/*! @{ */
+
+#define SPI_MH_Bits_MASK                         (0xFFU)
+#define SPI_MH_Bits_SHIFT                        (0U)
+/*! Bits - Hardware compare value (high byte) */
+#define SPI_MH_Bits(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
+/*! @} */
+
+/*! @name DL - SPI Data Register low */
+/*! @{ */
+
+#define SPI_DL_Bits_MASK                         (0xFFU)
+#define SPI_DL_Bits_SHIFT                        (0U)
+/*! Bits - Data (low byte) */
+#define SPI_DL_Bits(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
+/*! @} */
+
+/*! @name DH - SPI data register high */
+/*! @{ */
+
+#define SPI_DH_Bits_MASK                         (0xFFU)
+#define SPI_DH_Bits_SHIFT                        (0U)
+/*! Bits - Data (high byte) */
+#define SPI_DH_Bits(x)                           (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
+/*! @} */
+
+/*! @name CI - SPI clear interrupt register */
+/*! @{ */
+
+#define SPI_CI_SPRFCI_MASK                       (0x1U)
+#define SPI_CI_SPRFCI_SHIFT                      (0U)
+/*! SPRFCI - Receive FIFO full flag clear interrupt */
+#define SPI_CI_SPRFCI(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
+
+#define SPI_CI_SPTEFCI_MASK                      (0x2U)
+#define SPI_CI_SPTEFCI_SHIFT                     (1U)
+/*! SPTEFCI - Transmit FIFO empty flag clear interrupt */
+#define SPI_CI_SPTEFCI(x)                        (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
+
+#define SPI_CI_RNFULLFCI_MASK                    (0x4U)
+#define SPI_CI_RNFULLFCI_SHIFT                   (2U)
+/*! RNFULLFCI - Receive FIFO nearly full flag clear interrupt */
+#define SPI_CI_RNFULLFCI(x)                      (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
+
+#define SPI_CI_TNEAREFCI_MASK                    (0x8U)
+#define SPI_CI_TNEAREFCI_SHIFT                   (3U)
+/*! TNEAREFCI - Transmit FIFO nearly empty flag clear interrupt */
+#define SPI_CI_TNEAREFCI(x)                      (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
+
+#define SPI_CI_RXFOF_MASK                        (0x10U)
+#define SPI_CI_RXFOF_SHIFT                       (4U)
+/*! RXFOF - Receive FIFO overflow flag
+ *  0b0..Receive FIFO overflow condition has not occurred
+ *  0b1..Receive FIFO overflow condition occurred
+ */
+#define SPI_CI_RXFOF(x)                          (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
+
+#define SPI_CI_TXFOF_MASK                        (0x20U)
+#define SPI_CI_TXFOF_SHIFT                       (5U)
+/*! TXFOF - Transmit FIFO overflow flag
+ *  0b0..Transmit FIFO overflow condition has not occurred
+ *  0b1..Transmit FIFO overflow condition occurred
+ */
+#define SPI_CI_TXFOF(x)                          (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
+
+#define SPI_CI_RXFERR_MASK                       (0x40U)
+#define SPI_CI_RXFERR_SHIFT                      (6U)
+/*! RXFERR - Receive FIFO error flag
+ *  0b0..No receive FIFO error occurred
+ *  0b1..A receive FIFO error occurred
+ */
+#define SPI_CI_RXFERR(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
+
+#define SPI_CI_TXFERR_MASK                       (0x80U)
+#define SPI_CI_TXFERR_SHIFT                      (7U)
+/*! TXFERR - Transmit FIFO error flag
+ *  0b0..No transmit FIFO error occurred
+ *  0b1..A transmit FIFO error occurred
+ */
+#define SPI_CI_TXFERR(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
+/*! @} */
+
+/*! @name C3 - SPI control register 3 */
+/*! @{ */
+
+#define SPI_C3_FIFOMODE_MASK                     (0x1U)
+#define SPI_C3_FIFOMODE_SHIFT                    (0U)
+/*! FIFOMODE - FIFO mode enable
+ *  0b0..Buffer mode disabled
+ *  0b1..Data available in the receive data buffer
+ */
+#define SPI_C3_FIFOMODE(x)                       (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
+
+#define SPI_C3_RNFULLIEN_MASK                    (0x2U)
+#define SPI_C3_RNFULLIEN_SHIFT                   (1U)
+/*! RNFULLIEN - Receive FIFO nearly full interrupt enable
+ *  0b0..No interrupt upon RNFULLF being set
+ *  0b1..Enable interrupts upon RNFULLF being set
+ */
+#define SPI_C3_RNFULLIEN(x)                      (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
+
+#define SPI_C3_TNEARIEN_MASK                     (0x4U)
+#define SPI_C3_TNEARIEN_SHIFT                    (2U)
+/*! TNEARIEN - Transmit FIFO nearly empty interrupt enable
+ *  0b0..No interrupt upon TNEAREF being set
+ *  0b1..Enable interrupts upon TNEAREF being set
+ */
+#define SPI_C3_TNEARIEN(x)                       (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
+
+#define SPI_C3_INTCLR_MASK                       (0x8U)
+#define SPI_C3_INTCLR_SHIFT                      (3U)
+/*! INTCLR - Interrupt clearing mechanism select
+ *  0b0..These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs
+ *  0b1..These interrupts are cleared by writing the corresponding bits in the CI register
+ */
+#define SPI_C3_INTCLR(x)                         (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
+
+#define SPI_C3_RNFULLF_MARK_MASK                 (0x10U)
+#define SPI_C3_RNFULLF_MARK_SHIFT                (4U)
+/*! RNFULLF_MARK - Receive FIFO nearly full watermark
+ *  0b0..RNFULLF is set when the receive FIFO has 48 bits or more
+ *  0b1..RNFULLF is set when the receive FIFO has 32 bits or more
+ */
+#define SPI_C3_RNFULLF_MARK(x)                   (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
+
+#define SPI_C3_TNEAREF_MARK_MASK                 (0x20U)
+#define SPI_C3_TNEAREF_MARK_SHIFT                (5U)
+/*! TNEAREF_MARK - Transmit FIFO nearly empty watermark
+ *  0b0..TNEAREF is set when the transmit FIFO has 16 bits or less
+ *  0b1..TNEAREF is set when the transmit FIFO has 32 bits or less
+ */
+#define SPI_C3_TNEAREF_MARK(x)                   (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8, irregular array, not all indices are valid */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8, irregular array, not all indices are valid */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[20];
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+/*! @{ */
+
+#define TPM_SC_PS_MASK                           (0x7U)
+#define TPM_SC_PS_SHIFT                          (0U)
+/*! PS - Prescale Factor Selection
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+
+#define TPM_SC_CMOD_MASK                         (0x18U)
+#define TPM_SC_CMOD_SHIFT                        (3U)
+/*! CMOD - Clock Mode Selection
+ *  0b00..TPM counter is disabled
+ *  0b01..TPM counter increments on every TPM counter clock
+ *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
+ *  0b11..Reserved
+ */
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+
+#define TPM_SC_CPWMS_MASK                        (0x20U)
+#define TPM_SC_CPWMS_SHIFT                       (5U)
+/*! CPWMS - Center-Aligned PWM Select
+ *  0b0..TPM counter operates in up counting mode.
+ *  0b1..TPM counter operates in up-down counting mode.
+ */
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+
+#define TPM_SC_TOIE_MASK                         (0x40U)
+#define TPM_SC_TOIE_SHIFT                        (6U)
+/*! TOIE - Timer Overflow Interrupt Enable
+ *  0b0..Disable TOF interrupts. Use software polling or DMA request.
+ *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+
+#define TPM_SC_TOF_MASK                          (0x80U)
+#define TPM_SC_TOF_SHIFT                         (7U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+
+#define TPM_SC_DMA_MASK                          (0x100U)
+#define TPM_SC_DMA_SHIFT                         (8U)
+/*! DMA - DMA Enable
+ *  0b0..Disables DMA transfers.
+ *  0b1..Enables DMA transfers.
+ */
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+/*! @} */
+
+/*! @name CNT - Counter */
+/*! @{ */
+
+#define TPM_CNT_COUNT_MASK                       (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT                      (0U)
+/*! COUNT - Counter value */
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+/*! @} */
+
+/*! @name MOD - Modulo */
+/*! @{ */
+
+#define TPM_MOD_MOD_MASK                         (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT                        (0U)
+/*! MOD - Modulo value */
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name CnSC - Channel (n) Status and Control */
+/*! @{ */
+
+#define TPM_CnSC_DMA_MASK                        (0x1U)
+#define TPM_CnSC_DMA_SHIFT                       (0U)
+/*! DMA - DMA Enable
+ *  0b0..Disable DMA transfers.
+ *  0b1..Enable DMA transfers.
+ */
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+
+#define TPM_CnSC_ELSA_MASK                       (0x4U)
+#define TPM_CnSC_ELSA_SHIFT                      (2U)
+/*! ELSA - Edge or Level Select */
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+
+#define TPM_CnSC_ELSB_MASK                       (0x8U)
+#define TPM_CnSC_ELSB_SHIFT                      (3U)
+/*! ELSB - Edge or Level Select */
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+
+#define TPM_CnSC_MSA_MASK                        (0x10U)
+#define TPM_CnSC_MSA_SHIFT                       (4U)
+/*! MSA - Channel Mode Select */
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+
+#define TPM_CnSC_MSB_MASK                        (0x20U)
+#define TPM_CnSC_MSB_SHIFT                       (5U)
+/*! MSB - Channel Mode Select */
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+
+#define TPM_CnSC_CHIE_MASK                       (0x40U)
+#define TPM_CnSC_CHIE_SHIFT                      (6U)
+/*! CHIE - Channel Interrupt Enable
+ *  0b0..Disable channel interrupts.
+ *  0b1..Enable channel interrupts.
+ */
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+
+#define TPM_CnSC_CHF_MASK                        (0x80U)
+#define TPM_CnSC_CHF_SHIFT                       (7U)
+/*! CHF - Channel Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+/*! @} */
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT                           (6U)
+
+/*! @name CnV - Channel (n) Value */
+/*! @{ */
+
+#define TPM_CnV_VAL_MASK                         (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT                        (0U)
+/*! VAL - Channel Value */
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+/*! @} */
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT                            (6U)
+
+/*! @name STATUS - Capture and Compare Status */
+/*! @{ */
+
+#define TPM_STATUS_CH0F_MASK                     (0x1U)
+#define TPM_STATUS_CH0F_SHIFT                    (0U)
+/*! CH0F - Channel 0 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+
+#define TPM_STATUS_CH1F_MASK                     (0x2U)
+#define TPM_STATUS_CH1F_SHIFT                    (1U)
+/*! CH1F - Channel 1 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+
+#define TPM_STATUS_CH2F_MASK                     (0x4U)
+#define TPM_STATUS_CH2F_SHIFT                    (2U)
+/*! CH2F - Channel 2 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+
+#define TPM_STATUS_CH3F_MASK                     (0x8U)
+#define TPM_STATUS_CH3F_SHIFT                    (3U)
+/*! CH3F - Channel 3 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+
+#define TPM_STATUS_CH4F_MASK                     (0x10U)
+#define TPM_STATUS_CH4F_SHIFT                    (4U)
+/*! CH4F - Channel 4 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+
+#define TPM_STATUS_CH5F_MASK                     (0x20U)
+#define TPM_STATUS_CH5F_SHIFT                    (5U)
+/*! CH5F - Channel 5 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+
+#define TPM_STATUS_TOF_MASK                      (0x100U)
+#define TPM_STATUS_TOF_SHIFT                     (8U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+/*! @} */
+
+/*! @name POL - Channel Polarity */
+/*! @{ */
+
+#define TPM_POL_POL0_MASK                        (0x1U)
+#define TPM_POL_POL0_SHIFT                       (0U)
+/*! POL0 - Channel 0 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+
+#define TPM_POL_POL1_MASK                        (0x2U)
+#define TPM_POL_POL1_SHIFT                       (1U)
+/*! POL1 - Channel 1 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+
+#define TPM_POL_POL2_MASK                        (0x4U)
+#define TPM_POL_POL2_SHIFT                       (2U)
+/*! POL2 - Channel 2 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
+
+#define TPM_POL_POL3_MASK                        (0x8U)
+#define TPM_POL_POL3_SHIFT                       (3U)
+/*! POL3 - Channel 3 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
+
+#define TPM_POL_POL4_MASK                        (0x10U)
+#define TPM_POL_POL4_SHIFT                       (4U)
+/*! POL4 - Channel Polarity 4
+ *  0b0..The channel polarity is active high
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
+
+#define TPM_POL_POL5_MASK                        (0x20U)
+#define TPM_POL_POL5_SHIFT                       (5U)
+/*! POL5 - Channel 5 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
+/*! @} */
+
+/*! @name CONF - Configuration */
+/*! @{ */
+
+#define TPM_CONF_DOZEEN_MASK                     (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT                    (5U)
+/*! DOZEEN - Doze Enable
+ *  0b0..Internal TPM counter continues in Doze mode.
+ *  0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
+ */
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+
+#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT                   (6U)
+/*! DBGMODE - Debug Mode
+ *  0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
+ *  0b11..TPM counter continues in debug mode.
+ */
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+
+#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
+/*! GTBSYNC - Global Time Base Synchronization
+ *  0b0..Global timebase synchronization disabled.
+ *  0b1..Global timebase synchronization enabled.
+ */
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+
+#define TPM_CONF_GTBEEN_MASK                     (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT                    (9U)
+/*! GTBEEN - Global time base enable
+ *  0b0..All channels use the internally generated TPM counter as their timebase
+ *  0b1..All channels use an externally generated global timebase as their timebase
+ */
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+
+#define TPM_CONF_CSOT_MASK                       (0x10000U)
+#define TPM_CONF_CSOT_SHIFT                      (16U)
+/*! CSOT - Counter Start on Trigger
+ *  0b0..TPM counter starts to increment immediately, once it is enabled.
+ *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
+ *       after it has been enabled or after it has stopped due to overflow.
+ */
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+
+#define TPM_CONF_CSOO_MASK                       (0x20000U)
+#define TPM_CONF_CSOO_SHIFT                      (17U)
+/*! CSOO - Counter Stop On Overflow
+ *  0b0..TPM counter continues incrementing or decrementing after overflow
+ *  0b1..TPM counter stops incrementing or decrementing after overflow.
+ */
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+
+#define TPM_CONF_CROT_MASK                       (0x40000U)
+#define TPM_CONF_CROT_SHIFT                      (18U)
+/*! CROT - Counter Reload On Trigger
+ *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
+ *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
+ */
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+
+#define TPM_CONF_CPOT_MASK                       (0x80000U)
+#define TPM_CONF_CPOT_SHIFT                      (19U)
+/*! CPOT - Counter Pause On Trigger */
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+
+#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT                    (22U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger is active high.
+ *  0b1..Trigger is active low.
+ */
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+
+#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT                    (23U)
+/*! TRGSRC - Trigger Source
+ *  0b0..Trigger source selected by TRGSEL is external.
+ *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
+ */
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+
+#define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT                    (24U)
+/*! TRGSEL - Trigger Select
+ *  0b0001..Channel 0 pin input capture
+ *  0b0010..Channel 1 pin input capture
+ *  0b0011..Channel 0 or Channel 1 pin input capture
+ *  0b0100..Channel 2 pin input capture
+ *  0b0101..Channel 0 or Channel 2 pin input capture
+ *  0b0110..Channel 1 or Channel 2 pin input capture
+ *  0b0111..Channel 0 or Channel 1 or Channel 2 pin input capture
+ *  0b1000..Channel 3 pin input capture
+ *  0b1001..Channel 0 or Channel 3 pin input capture
+ *  0b1010..Channel 1 or Channel 3 pin input capture
+ *  0b1011..Channel 0 or Channel 1 or Channel 3 pin input capture
+ *  0b1100..Channel 2 or Channel 3 pin input capture
+ *  0b1101..Channel 0 or Channel 2 or Channel 3 pin input capture
+ *  0b1110..Channel 1 or Channel 2 or Channel 3 pin input capture
+ *  0b1111..Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
+ */
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+       uint8_t RESERVED_0[12];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  __IO uint8_t WP7816;                             /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+       uint8_t RESERVED_1[26];
+  __IO uint8_t AP7816A_T0;                         /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+  __IO uint8_t AP7816B_T0;                         /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+  union {                                          /* offset: 0x3C */
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T0;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T0;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE0;
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T1;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T1;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE1;
+  };
+  __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+  __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Registers: High */
+/*! @{ */
+
+#define UART_BDH_SBR_MASK                        (0x1FU)
+#define UART_BDH_SBR_SHIFT                       (0U)
+/*! SBR - UART Baud Rate Bits */
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+
+#define UART_BDH_RXEDGIE_MASK                    (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT                   (6U)
+/*! RXEDGIE - RxD Input Active Edge Interrupt Enable
+ *  0b0..Hardware interrupts from RXEDGIF disabled using polling.
+ *  0b1..RXEDGIF interrupt request enabled.
+ */
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+/*! @} */
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+/*! @{ */
+
+#define UART_BDL_SBR_MASK                        (0xFFU)
+#define UART_BDL_SBR_SHIFT                       (0U)
+/*! SBR - UART Baud Rate Bits */
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+/*! @} */
+
+/*! @name C1 - UART Control Register 1 */
+/*! @{ */
+
+#define UART_C1_PT_MASK                          (0x1U)
+#define UART_C1_PT_SHIFT                         (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity.
+ *  0b1..Odd parity.
+ */
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+
+#define UART_C1_PE_MASK                          (0x2U)
+#define UART_C1_PE_SHIFT                         (1U)
+/*! PE - Parity Enable
+ *  0b0..Parity function disabled.
+ *  0b1..Parity function enabled.
+ */
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+
+#define UART_C1_ILT_MASK                         (0x4U)
+#define UART_C1_ILT_SHIFT                        (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..Idle character bit count starts after start bit.
+ *  0b1..Idle character bit count starts after stop bit.
+ */
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+
+#define UART_C1_WAKE_MASK                        (0x8U)
+#define UART_C1_WAKE_SHIFT                       (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ *  0b0..Idle line wakeup.
+ *  0b1..Address mark wakeup.
+ */
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+
+#define UART_C1_M_MASK                           (0x10U)
+#define UART_C1_M_SHIFT                          (4U)
+/*! M - 9-bit or 8-bit Mode Select
+ *  0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
+ *  0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+
+#define UART_C1_RSRC_MASK                        (0x20U)
+#define UART_C1_RSRC_SHIFT                       (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output.
+ *  0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal.
+ */
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+
+#define UART_C1_LOOPS_MASK                       (0x80U)
+#define UART_C1_LOOPS_SHIFT                      (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation.
+ *  0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
+ */
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+/*! @} */
+
+/*! @name C2 - UART Control Register 2 */
+/*! @{ */
+
+#define UART_C2_SBK_MASK                         (0x1U)
+#define UART_C2_SBK_SHIFT                        (0U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation.
+ *  0b1..Queue break characters to be sent.
+ */
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+
+#define UART_C2_RWU_MASK                         (0x2U)
+#define UART_C2_RWU_SHIFT                        (1U)
+/*! RWU - Receiver Wakeup Control
+ *  0b0..Normal operation.
+ *  0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware
+ *       wakes the receiver by automatically clearing RWU.
+ */
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+
+#define UART_C2_RE_MASK                          (0x4U)
+#define UART_C2_RE_SHIFT                         (2U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver off.
+ *  0b1..Receiver on.
+ */
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+
+#define UART_C2_TE_MASK                          (0x8U)
+#define UART_C2_TE_SHIFT                         (3U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter off.
+ *  0b1..Transmitter on.
+ */
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+
+#define UART_C2_ILIE_MASK                        (0x10U)
+#define UART_C2_ILIE_SHIFT                       (4U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..IDLE interrupt requests disabled.
+ *  0b1..IDLE interrupt requests enabled.
+ */
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+
+#define UART_C2_RIE_MASK                         (0x20U)
+#define UART_C2_RIE_SHIFT                        (5U)
+/*! RIE - Receiver Full Interrupt or DMA Transfer Enable
+ *  0b0..RDRF interrupt and DMA transfer requests disabled.
+ *  0b1..RDRF interrupt or DMA transfer requests enabled.
+ */
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+
+#define UART_C2_TCIE_MASK                        (0x40U)
+#define UART_C2_TCIE_SHIFT                       (6U)
+/*! TCIE - Transmission Complete Interrupt Enable
+ *  0b0..TC interrupt requests disabled.
+ *  0b1..TC interrupt requests enabled.
+ */
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+
+#define UART_C2_TIE_MASK                         (0x80U)
+#define UART_C2_TIE_SHIFT                        (7U)
+/*! TIE - Transmitter Interrupt or DMA Transfer Enable.
+ *  0b0..TDRE interrupt and DMA transfer requests disabled.
+ *  0b1..TDRE interrupt or DMA transfer requests enabled.
+ */
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+/*! @} */
+
+/*! @name S1 - UART Status Register 1 */
+/*! @{ */
+
+#define UART_S1_PF_MASK                          (0x1U)
+#define UART_S1_PF_SHIFT                         (0U)
+/*! PF - Parity Error Flag
+ *  0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth
+ *       greater than 1, then there may be data in the receive buffer what was received with a parity error.
+ *  0b1..At least one dataword was received with a parity error since the last time this flag was cleared.
+ */
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+
+#define UART_S1_FE_MASK                          (0x2U)
+#define UART_S1_FE_SHIFT                         (1U)
+/*! FE - Framing Error Flag
+ *  0b0..No framing error detected.
+ *  0b1..Framing error.
+ */
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+
+#define UART_S1_NF_MASK                          (0x4U)
+#define UART_S1_NF_SHIFT                         (2U)
+/*! NF - Noise Flag
+ *  0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater
+ *       than 1 then there may be data in the receiver buffer that was received with noise.
+ *  0b1..At least one dataword was received with noise detected since the last time the flag was cleared.
+ */
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+
+#define UART_S1_OR_MASK                          (0x8U)
+#define UART_S1_OR_SHIFT                         (3U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No overrun has occurred since the last time the flag was cleared.
+ *  0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
+ */
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+
+#define UART_S1_IDLE_MASK                        (0x10U)
+#define UART_S1_IDLE_SHIFT                       (4U)
+/*! IDLE - Idle Line Flag
+ *  0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared.
+ *  0b1..Receiver input has become idle or the flag has not been cleared since it last asserted.
+ */
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+
+#define UART_S1_RDRF_MASK                        (0x20U)
+#define UART_S1_RDRF_SHIFT                       (5U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER.
+ *  0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER
+ *       at some point in time since this flag was last cleared.
+ */
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+
+#define UART_S1_TC_MASK                          (0x40U)
+#define UART_S1_TC_SHIFT                         (6U)
+/*! TC - Transmit Complete Flag
+ *  0b0..Transmitter active (sending data, a preamble, or a break).
+ *  0b1..Transmitter idle (transmission activity complete).
+ */
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+
+#define UART_S1_TDRE_MASK                        (0x80U)
+#define UART_S1_TDRE_SHIFT                       (7U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
+ *  0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER]
+ *       at some point in time since the flag has been cleared.
+ */
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+/*! @} */
+
+/*! @name S2 - UART Status Register 2 */
+/*! @{ */
+
+#define UART_S2_RAF_MASK                         (0x1U)
+#define UART_S2_RAF_SHIFT                        (0U)
+/*! RAF - Receiver Active Flag
+ *  0b0..UART receiver idle/inactive waiting for a start bit.
+ *  0b1..UART receiver active, RxD input not idle.
+ */
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+
+#define UART_S2_BRK13_MASK                       (0x4U)
+#define UART_S2_BRK13_SHIFT                      (2U)
+/*! BRK13 - Break Transmit Character Length
+ *  0b0..Break character is 10, 11, or 12 bits long.
+ *  0b1..Break character is 13 or 14 bits long.
+ */
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+
+#define UART_S2_RWUID_MASK                       (0x8U)
+#define UART_S2_RWUID_SHIFT                      (3U)
+/*! RWUID - Receive Wakeup Idle Detect
+ *  0b0..S1[IDLE] is not set upon detection of an idle character.
+ *  0b1..S1[IDLE] is set upon detection of an idle character.
+ */
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+
+#define UART_S2_RXINV_MASK                       (0x10U)
+#define UART_S2_RXINV_SHIFT                      (4U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Receive data is not inverted.
+ *  0b1..Receive data is inverted.
+ */
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+
+#define UART_S2_MSBF_MASK                        (0x20U)
+#define UART_S2_MSBF_SHIFT                       (5U)
+/*! MSBF - Most Significant Bit First
+ *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
+ *       after the start bit is identified as bit0.
+ *  0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the
+ *       setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8,
+ *       bit7, or bit6, depending on the setting of C1[M] and C1[PE].
+ */
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+
+#define UART_S2_RXEDGIF_MASK                     (0x40U)
+#define UART_S2_RXEDGIF_SHIFT                    (6U)
+/*! RXEDGIF - RxD Pin Active Edge Interrupt Flag
+ *  0b0..No active edge on the receive pin has occurred.
+ *  0b1..An active edge on the receive pin has occurred.
+ */
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+/*! @} */
+
+/*! @name C3 - UART Control Register 3 */
+/*! @{ */
+
+#define UART_C3_PEIE_MASK                        (0x1U)
+#define UART_C3_PEIE_SHIFT                       (0U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..PF interrupt requests are disabled.
+ *  0b1..PF interrupt requests are enabled.
+ */
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+
+#define UART_C3_FEIE_MASK                        (0x2U)
+#define UART_C3_FEIE_SHIFT                       (1U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..FE interrupt requests are disabled.
+ *  0b1..FE interrupt requests are enabled.
+ */
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+
+#define UART_C3_NEIE_MASK                        (0x4U)
+#define UART_C3_NEIE_SHIFT                       (2U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..NF interrupt requests are disabled.
+ *  0b1..NF interrupt requests are enabled.
+ */
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+
+#define UART_C3_ORIE_MASK                        (0x8U)
+#define UART_C3_ORIE_SHIFT                       (3U)
+/*! ORIE - Overrun Error Interrupt Enable
+ *  0b0..OR interrupts are disabled.
+ *  0b1..OR interrupt requests are enabled.
+ */
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+
+#define UART_C3_TXINV_MASK                       (0x10U)
+#define UART_C3_TXINV_SHIFT                      (4U)
+/*! TXINV - Transmit Data Inversion.
+ *  0b0..Transmit data is not inverted.
+ *  0b1..Transmit data is inverted.
+ */
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+
+#define UART_C3_TXDIR_MASK                       (0x20U)
+#define UART_C3_TXDIR_SHIFT                      (5U)
+/*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode
+ *  0b0..TXD pin is an input in single wire mode.
+ *  0b1..TXD pin is an output in single wire mode.
+ */
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+
+#define UART_C3_T8_MASK                          (0x40U)
+#define UART_C3_T8_SHIFT                         (6U)
+/*! T8 - Transmit Bit 8 */
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+
+#define UART_C3_R8_MASK                          (0x80U)
+#define UART_C3_R8_SHIFT                         (7U)
+/*! R8 - Received Bit 8 */
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+/*! @} */
+
+/*! @name D - UART Data Register */
+/*! @{ */
+
+#define UART_D_RT_MASK                           (0xFFU)
+#define UART_D_RT_SHIFT                          (0U)
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+/*! @} */
+
+/*! @name MA1 - UART Match Address Registers 1 */
+/*! @{ */
+
+#define UART_MA1_MA_MASK                         (0xFFU)
+#define UART_MA1_MA_SHIFT                        (0U)
+/*! MA - Match Address */
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+/*! @} */
+
+/*! @name MA2 - UART Match Address Registers 2 */
+/*! @{ */
+
+#define UART_MA2_MA_MASK                         (0xFFU)
+#define UART_MA2_MA_SHIFT                        (0U)
+/*! MA - Match Address */
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+/*! @} */
+
+/*! @name C4 - UART Control Register 4 */
+/*! @{ */
+
+#define UART_C4_BRFA_MASK                        (0x1FU)
+#define UART_C4_BRFA_SHIFT                       (0U)
+/*! BRFA - Baud Rate Fine Adjust */
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+
+#define UART_C4_M10_MASK                         (0x20U)
+#define UART_C4_M10_SHIFT                        (5U)
+/*! M10 - 10-bit Mode select
+ *  0b0..The parity bit is the ninth bit in the serial transmission.
+ *  0b1..The parity bit is the tenth bit in the serial transmission.
+ */
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+
+#define UART_C4_MAEN2_MASK                       (0x40U)
+#define UART_C4_MAEN2_SHIFT                      (6U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..All data received is transferred to the data buffer if MAEN1 is cleared.
+ *  0b1..All data received with the most significant bit cleared, is discarded. All data received with the most
+ *       significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded.
+ *       If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E]
+ *       is set/enabled.
+ */
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+
+#define UART_C4_MAEN1_MASK                       (0x80U)
+#define UART_C4_MAEN1_SHIFT                      (7U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..All data received is transferred to the data buffer if MAEN2 is cleared.
+ *  0b1..All data received with the most significant bit cleared, is discarded. All data received with the most
+ *       significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded.
+ *       If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is
+ *       set/enabled.
+ */
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+/*! @} */
+
+/*! @name C5 - UART Control Register 5 */
+/*! @{ */
+
+#define UART_C5_RDMAS_MASK                       (0x20U)
+#define UART_C5_RDMAS_SHIFT                      (5U)
+/*! RDMAS - Receiver Full DMA Select
+ *  0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
+ *  0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
+ */
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+
+#define UART_C5_TDMAS_MASK                       (0x80U)
+#define UART_C5_TDMAS_SHIFT                      (7U)
+/*! TDMAS - Transmitter DMA Select
+ *  0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
+ *  0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
+ */
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+/*! @} */
+
+/*! @name C7816 - UART 7816 Control Register */
+/*! @{ */
+
+#define UART_C7816_ISO_7816E_MASK                (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT               (0U)
+/*! ISO_7816E - ISO-7816 Functionality Enabled
+ *  0b0..ISO-7816 functionality is turned off/not enabled.
+ *  0b1..ISO-7816 functionality is turned on/enabled.
+ */
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+
+#define UART_C7816_TTYPE_MASK                    (0x2U)
+#define UART_C7816_TTYPE_SHIFT                   (1U)
+/*! TTYPE - Transfer Type
+ *  0b0..T = 0 per the ISO-7816 specification.
+ *  0b1..T = 1 per the ISO-7816 specification.
+ */
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+
+#define UART_C7816_INIT_MASK                     (0x4U)
+#define UART_C7816_INIT_SHIFT                    (2U)
+/*! INIT - Detect Initial Character
+ *  0b0..Normal operating mode. Receiver does not seek to identify initial character.
+ *  0b1..Receiver searches for initial character.
+ */
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+
+#define UART_C7816_ANACK_MASK                    (0x8U)
+#define UART_C7816_ANACK_SHIFT                   (3U)
+/*! ANACK - Generate NACK on Error
+ *  0b0..No NACK is automatically generated.
+ *  0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
+ */
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+
+#define UART_C7816_ONACK_MASK                    (0x10U)
+#define UART_C7816_ONACK_SHIFT                   (4U)
+/*! ONACK - Generate NACK on Overflow
+ *  0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event.
+ *  0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character.
+ */
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+/*! @} */
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+/*! @{ */
+
+#define UART_IE7816_RXTE_MASK                    (0x1U)
+#define UART_IE7816_RXTE_SHIFT                   (0U)
+/*! RXTE - Receive Threshold Exceeded Interrupt Enable
+ *  0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[RXT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+
+#define UART_IE7816_TXTE_MASK                    (0x2U)
+#define UART_IE7816_TXTE_SHIFT                   (1U)
+/*! TXTE - Transmit Threshold Exceeded Interrupt Enable
+ *  0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[TXT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+
+#define UART_IE7816_GTVE_MASK                    (0x4U)
+#define UART_IE7816_GTVE_SHIFT                   (2U)
+/*! GTVE - Guard Timer Violated Interrupt Enable
+ *  0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[GTV] results in the generation of an interrupt.
+ */
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+
+#define UART_IE7816_ADTE_MASK                    (0x8U)
+#define UART_IE7816_ADTE_SHIFT                   (3U)
+/*! ADTE - ATR Duration Timer Interrupt Enable
+ *  0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[ADT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+
+#define UART_IE7816_INITDE_MASK                  (0x10U)
+#define UART_IE7816_INITDE_SHIFT                 (4U)
+/*! INITDE - Initial Character Detected Interrupt Enable
+ *  0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[INITD] results in the generation of an interrupt.
+ */
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+
+#define UART_IE7816_BWTE_MASK                    (0x20U)
+#define UART_IE7816_BWTE_SHIFT                   (5U)
+/*! BWTE - Block Wait Timer Interrupt Enable
+ *  0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[BWT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+
+#define UART_IE7816_CWTE_MASK                    (0x40U)
+#define UART_IE7816_CWTE_SHIFT                   (6U)
+/*! CWTE - Character Wait Timer Interrupt Enable
+ *  0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[CWT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+
+#define UART_IE7816_WTE_MASK                     (0x80U)
+#define UART_IE7816_WTE_SHIFT                    (7U)
+/*! WTE - Wait Timer Interrupt Enable
+ *  0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt.
+ *  0b1..The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+/*! @} */
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+/*! @{ */
+
+#define UART_IS7816_RXT_MASK                     (0x1U)
+#define UART_IS7816_RXT_SHIFT                    (0U)
+/*! RXT - Receive Threshold Exceeded Interrupt
+ *  0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than
+ *       or equal to the value in ET7816[RXTHRESHOLD].
+ *  0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+
+#define UART_IS7816_TXT_MASK                     (0x2U)
+#define UART_IS7816_TXT_SHIFT                    (1U)
+/*! TXT - Transmit Threshold Exceeded Interrupt
+ *  0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
+ *  0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
+ */
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+
+#define UART_IS7816_GTV_MASK                     (0x4U)
+#define UART_IS7816_GTV_SHIFT                    (2U)
+/*! GTV - Guard Timer Violated Interrupt
+ *  0b0..A guard time (GT, CGT, or BGT) has not been violated.
+ *  0b1..A guard time (GT, CGT, or BGT) has been violated.
+ */
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+
+#define UART_IS7816_ADT_MASK                     (0x8U)
+#define UART_IS7816_ADT_SHIFT                    (3U)
+/*! ADT - ATR Duration Time Interrupt
+ *  0b0..ATR Duration time (ADT) has not been violated.
+ *  0b1..ATR Duration time (ADT) has been violated.
+ */
+#define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+
+#define UART_IS7816_INITD_MASK                   (0x10U)
+#define UART_IS7816_INITD_SHIFT                  (4U)
+/*! INITD - Initial Character Detected Interrupt
+ *  0b0..A valid initial character has not been received.
+ *  0b1..A valid initial character has been received.
+ */
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+
+#define UART_IS7816_BWT_MASK                     (0x20U)
+#define UART_IS7816_BWT_SHIFT                    (5U)
+/*! BWT - Block Wait Timer Interrupt
+ *  0b0..Block wait time (BWT) has not been violated.
+ *  0b1..Block wait time (BWT) has been violated.
+ */
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+
+#define UART_IS7816_CWT_MASK                     (0x40U)
+#define UART_IS7816_CWT_SHIFT                    (6U)
+/*! CWT - Character Wait Timer Interrupt
+ *  0b0..Character wait time (CWT) has not been violated.
+ *  0b1..Character wait time (CWT) has been violated.
+ */
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+
+#define UART_IS7816_WT_MASK                      (0x80U)
+#define UART_IS7816_WT_SHIFT                     (7U)
+/*! WT - Wait Timer Interrupt
+ *  0b0..Wait time (WT) has not been violated.
+ *  0b1..Wait time (WT) has been violated.
+ */
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+/*! @} */
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+/*! @{ */
+
+#define UART_WP7816_WTX_MASK                     (0xFFU)
+#define UART_WP7816_WTX_SHIFT                    (0U)
+/*! WTX - Wait Time Multiplier (C7816[TTYPE] = 1) */
+#define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+/*! @} */
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+/*! @{ */
+
+#define UART_WN7816_GTN_MASK                     (0xFFU)
+#define UART_WN7816_GTN_SHIFT                    (0U)
+/*! GTN - Guard Band N */
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+/*! @} */
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+/*! @{ */
+
+#define UART_WF7816_GTFD_MASK                    (0xFFU)
+#define UART_WF7816_GTFD_SHIFT                   (0U)
+/*! GTFD - FD Multiplier */
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+/*! @} */
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+/*! @{ */
+
+#define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
+/*! RXTHRESHOLD - Receive NACK Threshold */
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+
+#define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
+/*! TXTHRESHOLD - Transmit NACK Threshold
+ *  0b0000..TXT asserts on the first NACK that is received.
+ *  0b0001..TXT asserts on the second NACK that is received.
+ */
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+/*! @} */
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+/*! @{ */
+
+#define UART_TL7816_TLEN_MASK                    (0xFFU)
+#define UART_TL7816_TLEN_SHIFT                   (0U)
+/*! TLEN - Transmit Length */
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+/*! @} */
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+/*! @{ */
+
+#define UART_AP7816A_T0_ADTI_H_MASK              (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT             (0U)
+/*! ADTI_H - ATR Duration Time Integer High (C7816[TTYPE] = 0) */
+#define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+/*! @} */
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+/*! @{ */
+
+#define UART_AP7816B_T0_ADTI_L_MASK              (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT             (0U)
+/*! ADTI_L - ATR Duration Time Integer Low (C7816[TTYPE] = 0) */
+#define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+/*! @} */
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+/*! @{ */
+
+#define UART_WP7816A_T0_WI_H_MASK                (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT               (0U)
+/*! WI_H - Wait Time Integer High (C7816[TTYPE] = 0) */
+#define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+/*! @} */
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+/*! @{ */
+
+#define UART_WP7816B_T0_WI_L_MASK                (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT               (0U)
+/*! WI_L - Wait Time Integer Low (C7816[TTYPE] = 0) */
+#define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+/*! @} */
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+/*! @{ */
+
+#define UART_WP7816A_T1_BWI_H_MASK               (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT              (0U)
+/*! BWI_H - Block Wait Time Integer High (C7816[TTYPE] = 1) */
+#define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+/*! @} */
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+/*! @{ */
+
+#define UART_WP7816B_T1_BWI_L_MASK               (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT              (0U)
+/*! BWI_L - Block Wait Time Integer Low (C7816[TTYPE] = 1) */
+#define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+/*! @} */
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+/*! @{ */
+
+#define UART_WGP7816_T1_BGI_MASK                 (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT                (0U)
+/*! BGI - Block Guard Time Integer (C7816[TTYPE] = 1) */
+#define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+
+#define UART_WGP7816_T1_CWI1_MASK                (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT               (4U)
+/*! CWI1 - Character Wait Time Integer 1 (C7816[TTYPE] = 1) */
+#define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+/*! @} */
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+/*! @{ */
+
+#define UART_WP7816C_T1_CWI2_MASK                (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT               (0U)
+/*! CWI2 - Character Wait Time Integer 2 (C7816[TTYPE] = 1) */
+#define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { 0u, 0u, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { (UART_Type *)0u, (UART_Type *)0u, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
+#define UART_ERR_IRQS                            { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[115];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_7[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_11[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_13[11];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_15[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_16[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_19[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_20[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_21[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_22[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_23[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+/*! @{ */
+
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+/*! ID - Peripheral Identification */
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+/*! @} */
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+/*! @{ */
+
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+/*! @} */
+
+/*! @name REV - Peripheral Revision register */
+/*! @{ */
+
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+/*! REV - Revision */
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+/*! @} */
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+/*! @{ */
+
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+/*! @} */
+
+/*! @name ISTAT - Interrupt Status register */
+/*! @{ */
+
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+/*! STALL - Stall Interrupt */
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable register */
+/*! @{ */
+
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+/*! USBRSTEN - USBRST Interrupt Enable
+ *  0b0..Disables the USBRST interrupt.
+ *  0b1..Enables the USBRST interrupt.
+ */
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+/*! ERROREN - ERROR Interrupt Enable
+ *  0b0..Disables the ERROR interrupt.
+ *  0b1..Enables the ERROR interrupt.
+ */
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+/*! SOFTOKEN - SOFTOK Interrupt Enable
+ *  0b0..Disbles the SOFTOK interrupt.
+ *  0b1..Enables the SOFTOK interrupt.
+ */
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+/*! TOKDNEEN - TOKDNE Interrupt Enable
+ *  0b0..Disables the TOKDNE interrupt.
+ *  0b1..Enables the TOKDNE interrupt.
+ */
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+/*! SLEEPEN - SLEEP Interrupt Enable
+ *  0b0..Disables the SLEEP interrupt.
+ *  0b1..Enables the SLEEP interrupt.
+ */
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+/*! RESUMEEN - RESUME Interrupt Enable
+ *  0b0..Disables the RESUME interrupt.
+ *  0b1..Enables the RESUME interrupt.
+ */
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+/*! STALLEN - STALL Interrupt Enable
+ *  0b0..Diasbles the STALL interrupt.
+ *  0b1..Enables the STALL interrupt.
+ */
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+/*! @{ */
+
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+
+#define USB_ERRSTAT_CRC5_MASK                    (0x2U)
+#define USB_ERRSTAT_CRC5_SHIFT                   (1U)
+#define USB_ERRSTAT_CRC5(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK)
+
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+/*! @} */
+
+/*! @name ERREN - Error Interrupt Enable register */
+/*! @{ */
+
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+/*! PIDERREN - PIDERR Interrupt Enable
+ *  0b0..Disables the PIDERR interrupt.
+ *  0b1..Enters the PIDERR interrupt.
+ */
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
+ *  0b0..Disables the CRC5/EOF interrupt.
+ *  0b1..Enables the CRC5/EOF interrupt.
+ */
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+/*! CRC16EN - CRC16 Interrupt Enable
+ *  0b0..Disables the CRC16 interrupt.
+ *  0b1..Enables the CRC16 interrupt.
+ */
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+/*! DFN8EN - DFN8 Interrupt Enable
+ *  0b0..Disables the DFN8 interrupt.
+ *  0b1..Enables the DFN8 interrupt.
+ */
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+/*! BTOERREN - BTOERR Interrupt Enable
+ *  0b0..Disables the BTOERR interrupt.
+ *  0b1..Enables the BTOERR interrupt.
+ */
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+/*! DMAERREN - DMAERR Interrupt Enable
+ *  0b0..Disables the DMAERR interrupt.
+ *  0b1..Enables the DMAERR interrupt.
+ */
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+/*! BTSERREN - BTSERR Interrupt Enable
+ *  0b0..Disables the BTSERR interrupt.
+ *  0b1..Enables the BTSERR interrupt.
+ */
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+/*! @} */
+
+/*! @name STAT - Status register */
+/*! @{ */
+
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+/*! TX - Transmit Indicator
+ *  0b0..The most recent transaction was a receive operation.
+ *  0b1..The most recent transaction was a transmit operation.
+ */
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+/*! @} */
+
+/*! @name CTL - Control register */
+/*! @{ */
+
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+/*! USBENSOFEN - USB Enable
+ *  0b0..Disables the USB Module.
+ *  0b1..Enables the USB Module.
+ */
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+/*! SE0 - Live USB Single Ended Zero signal */
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+/*! JSTATE - Live USB differential receiver JSTATE signal */
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register */
+/*! @{ */
+
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+/*! ADDR - USB Address */
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+/*! @} */
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+/*! @{ */
+
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+/*! @} */
+
+/*! @name FRMNUML - Frame Number register Low */
+/*! @{ */
+
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+/*! @} */
+
+/*! @name FRMNUMH - Frame Number register High */
+/*! @{ */
+
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+/*! @} */
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+/*! @{ */
+
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+/*! @} */
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+/*! @{ */
+
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+/*! @} */
+
+/*! @name ENDPT - Endpoint Control register */
+/*! @{ */
+
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+/*! @} */
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+/*! @{ */
+
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+/*! PDE
+ *  0b0..Weak pulldowns are disabled on D+ and D-.
+ *  0b1..Weak pulldowns are enabled on D+ and D-.
+ */
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+/*! SUSP
+ *  0b0..USB transceiver is not in suspend state.
+ *  0b1..USB transceiver is in suspend state.
+ */
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+/*! @} */
+
+/*! @name OBSERVE - USB OTG Observe register */
+/*! @{ */
+
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+/*! DMPD
+ *  0b0..D- pulldown disabled.
+ *  0b1..D- pulldown enabled.
+ */
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+/*! DPPD
+ *  0b0..D+ pulldown disabled.
+ *  0b1..D+ pulldown enabled.
+ */
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+/*! DPPU
+ *  0b0..D+ pullup disabled.
+ *  0b1..D+ pullup enabled.
+ */
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+/*! @} */
+
+/*! @name CONTROL - USB OTG Control register */
+/*! @{ */
+
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+/*! DPPULLUPNONOTG
+ *  0b0..DP Pullup in non-OTG device mode is not enabled.
+ *  0b1..DP Pullup in non-OTG device mode is enabled.
+ */
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+/*! @} */
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+/*! @{ */
+
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+/*! USB_RESUME_INT - USB Asynchronous Interrupt
+ *  0b0..No interrupt was generated.
+ *  0b1..Interrupt was generated because of the USB asynchronous interrupt.
+ */
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+/*! SYNC_DET - Synchronous USB Interrupt Detect
+ *  0b0..Synchronous interrupt has not been detected.
+ *  0b1..Synchronous interrupt has been detected.
+ */
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
+/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+/*! USBRESMEN - Asynchronous Resume Interrupt Enable
+ *  0b0..USB asynchronous wakeup from suspend mode disabled.
+ *  0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the
+ *       synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+
+ *       and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
+ */
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+/*! USBRESET - USB Reset
+ *  0b0..Normal USB module operation.
+ *  0b1..Returns the USB module to its reset state.
+ */
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+/*! @} */
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+/*! @{ */
+
+#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
+/*! ADJ - Frame Adjustment */
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+/*! @{ */
+
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+/*! RESTART_IFRTRIM_EN - Restart from IFR trim value
+ *  0b0..Trim fine adjustment always works based on the previous updated trim fine value (default)
+ *  0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
+ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
+ *  0b0..Always works in tracking phase after the first time rough to track transition (default)
+ *  0b1..Go back to rough stage whenever bus reset or bus resume occurs
+ */
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+/*! CLOCK_RECOVER_EN - Crystal-less USB enable
+ *  0b0..Disable clock recovery block (default)
+ *  0b1..Enable clock recovery block
+ */
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+/*! @{ */
+
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+/*! IRC_EN - IRC48M enable
+ *  0b0..Disable the IRC48M module (default)
+ *  0b1..Enable the IRC48M module
+ */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+/*! @{ */
+
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+/*! OVF_ERROR_EN
+ *  0b0..The interrupt will be masked
+ *  0b1..The interrupt will be enabled (default)
+ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+/*! @{ */
+
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+/*! OVF_ERROR
+ *  0b0..No interrupt is reported
+ *  0b1..Unmasked interrupt has been generated
+ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+/*! @{ */
+
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+/*! TRIM - Trim bits
+ *  0b000000..Min
+ *  0b111111..Max
+ */
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+/*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the
+ *    internal analog offset will be minimized.
+ *  0b0..Chop oscillator is disabled.
+ *  0b1..Chop oscillator is enabled.
+ */
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+/*! @} */
+
+/*! @name SC - VREF Status and Control Register */
+/*! @{ */
+
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+/*! MODE_LV - Buffer Mode selection
+ *  0b00..Bandgap on only, for stabilization and startup
+ *  0b01..High power buffer mode enabled
+ *  0b10..Low-power buffer mode enabled
+ *  0b11..Reserved
+ */
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+/*! VREFST - Internal Voltage Reference stable
+ *  0b0..The module is disabled or not stable.
+ *  0b1..The module is stable.
+ */
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+/*! ICOMPEN - Second order curvature compensation enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+/*! REGEN - Regulator enable
+ *  0b0..Internal 1.75 V regulator is disabled.
+ *  0b1..Internal 1.75 V regulator is enabled.
+ */
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+/*! VREFEN - Internal Voltage Reference enable
+ *  0b0..The module is disabled.
+ *  0b1..The module is enabled.
+ */
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define I2C_S1_RXAK_MASK                       I2C_S_RXAK_MASK
+#define I2C_S1_RXAK_SHIFT                      I2C_S_RXAK_SHIFT
+#define I2C_S1_IICIF_MASK                      I2C_S_IICIF_MASK
+#define I2C_S1_IICIF_SHIFT                     I2C_S_IICIF_SHIFTFT
+#define I2C_S1_SRW_MASK                        I2C_S_SRW_MASK
+#define I2C_S1_SRW_SHIFT                       I2C_S_SRW_SHIFT
+#define I2C_S1_RAM_MASK                        I2C_S_RAM_MASK
+#define I2C_S1_RAM_SHIFT                       I2C_S_RAM_SHIFT
+#define I2C_S1_ARBL_MASK                       I2C_S_ARBL_MASK
+#define I2C_S1_ARBL_SHIFT                      I2C_S_ARBL_SHIFT
+#define I2C_S1_BUSY_MASK                       I2C_S_BUSY_MASK
+#define I2C_S1_BUSY_SHIFT                      I2C_S_BUSY_SHIFT
+#define I2C_S1_IAAS_MASK                       I2C_S_IAAS_MASK
+#define I2C_S1_IAAS_SHIFT                      I2C_S_IAAS_SHIFT
+#define I2C_S1_TCF_MASK                        I2C_S_TCF_MASK
+#define I2C_S1_TCF_SHIFT                       I2C_S_TCF_SHIFT
+#define I2C_S1_REG(base)                       I2C_S_REG(base)
+#define I2C0_S1                                I2C0_S
+#define I2C1_S1                                I2C1_S
+#define PTA_BASE                               GPIOA_BASE
+#define PTB_BASE                               GPIOB_BASE
+#define PTC_BASE                               GPIOC_BASE
+#define PTD_BASE                               GPIOD_BASE
+#define PTE_BASE                               GPIOE_BASE
+#define PTA                                    GPIOA
+#define PTB                                    GPIOB
+#define PTC                                    GPIOC
+#define PTD                                    GPIOD
+#define PTE                                    GPIOE
+#define UART0_FLEXIO_IRQn                      UART2_FLEXIO_IRQn
+#define UART0_FLEXIO_IRQHandler                UART2_FLEXIO_IRQHandler
+#define SIM_SOPT5_UART0ODE_MASK                SIM_SOPT5_UART2ODE_MASK
+#define SIM_SOPT5_UART0ODE_SHIFT               SIM_SOPT5_UART2ODE_SHIFT
+#define SIM_SCGC4_UART0_MASK                   SIM_SCGC4_UART2_MASK
+#define SIM_SCGC4_UART0_SHIFT                  SIM_SCGC4_UART2_SHIFT
+#define UART0_BASE                             UART2_BASE
+#define UART0_BDH                              UART2_BDH
+#define UART0_BDL                              UART2_BDL
+#define UART0_C1                               UART2_C1
+#define UART0_C2                               UART2_C2
+#define UART0_S1                               UART2_S1
+#define UART0_S2                               UART2_S2
+#define UART0_C3                               UART2_C3
+#define UART0_D                                UART2_D
+#define UART0_MA1                              UART2_MA1
+#define UART0_MA2                              UART2_MA2
+#define UART0_C4                               UART2_C4
+#define UART0_C5                               UART2_C5
+#define UART0_ED                               UART2_ED
+#define UART0_MODEM                            UART2_MODEM
+#define UART0_IR                               UART2_IR
+#define UART0_PFIFO                            UART2_PFIFO
+#define UART0_CFIFO                            UART2_CFIFO
+#define UART0_SFIFO                            UART2_SFIFO
+#define UART0_TWFIFO                           UART2_TWFIFO
+#define UART0_TCFIFO                           UART2_TCFIFO
+#define UART0_RWFIFO                           UART2_RWFIFO
+#define UART0_RCFIFO                           UART2_RCFIFO
+#define UART0_C7816                            UART2_C7816
+#define UART0_IE7816                           UART2_IE7816
+#define UART0_IS7816                           UART2_IS7816
+#define UART0_WP7816                           UART2_WP7816
+#define UART0_WN7816                           UART2_WN7816
+#define UART0_WF7816                           UART2_WF7816
+#define UART0_ET7816                           UART2_ET7816
+#define UART0_TL7816                           UART2_TL7816
+#define UART0_AP7816A_T0                       UART2_AP7816A_T0
+#define UART0_AP7816B_T0                       UART2_AP7816B_T0
+#define UART0_WP7816A_T0                       UART2_WP7816A_T0
+#define UART0_WP7816A_T1                       UART2_WP7816A_T1
+#define UART0_WP7816B_T0                       UART2_WP7816B_T0
+#define UART0_WP7816B_T1                       UART2_WP7816B_T1
+#define UART0_WGP7816_T1                       UART2_WGP7816_T1
+#define UART0_WP7816C_T1                       UART2_WP7816C_T1
+#define I2S0_MDR                               This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_MASK                    This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_SHIFT                   This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE(x)                      This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_MASK                     This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_SHIFT                    This_symb_has_been_deprecated
+#define I2S_MDR_FRACT(x)                       This_symb_has_been_deprecated
+#define I2S_MDR_REG(base)                      This_symb_has_been_deprecated
+#define CTL0                                   OTGCTL
+#define USB0_CTL0                              USB0_OTGCTL
+#define USB_CTL0_REG(base)                     USB_OTGCTL_REG(base)
+#define USB_CTL0_DPHIGH_MASK                   USB_OTGCTL_DPHIGH_MASK
+#define USB_CTL0_DPHIGH_SHIFT                  USB_OTGCTL_DPHIGH_SHIFT
+#define CTL1                                   CTL
+#define USB0_CTL1                              USB0_CTL
+#define USB_CTL1_REG(base)                     USB_CTL_REG(base)
+#define USB_CTL1_USBEN_MASK                    USB_CTL_USBEN_MASK
+#define USB_CTL1_USBEN_SHIFT                   USB_CTL_USBEN_SHIFT
+#define USB_CTL1_ODDRST_MASK                   USB_CTL_ODDRST_MASK
+#define USB_CTL1_ODDRST_SHIFT                  USB_CTL_ODDRST_SHIFT
+#define USB_CTL1_TXSUSPENDTOKENBUSY_MASK       USB_CTL_TXSUSPENDTOKENBUSY_MASK
+#define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT      USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
+#define USB_CTL1_SE0_MASK                      USB_CTL_SE0_MASK
+#define USB_CTL1_SE0_SHIFT                     USB_CTL_SE0_SHIFT
+#define USB_CTL1_JSTATE_MASK                   USB_CTL_JSTATE_MASK
+#define USB_CTL1_JSTATE_SHIFT                  USB_CTL_JSTATE_SHIFT
+#define USB_CTL_USBEN_MASK                     USB_CTL_USBENSOFEN_MASK
+#define USB_CTL_USBEN_SHIFT                    USB_CTL_USBENSOFEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* MCXC444_H_ */
+
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444_features.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444_features.h
new file mode 100644
index 0000000000..e5aa684302
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/MCXC444_features.h
@@ -0,0 +1,1455 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240411
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-11)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _MCXC444_FEATURES_H_
+#define _MCXC444_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (5)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (1)
+/* @brief SLCD availability on the SoC. */
+#define FSL_FEATURE_SOC_SLCD_COUNT (1)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (2)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (1)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (1)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (1)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DMA module features */
+
+/* @brief Number of DMA channels. */
+#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+/* @brief Register CHCFGn width. */
+#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
+
+/* FGPIO module features */
+
+/* No feature definitions */
+
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404)
+/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
+#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2)
+/* @brief Flexio DMA request base channel */
+#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
+
+/* FLASH module features */
+
+/* @brief Is of type FTFA. */
+#define FSL_FEATURE_FLASH_IS_FTFA (1)
+/* @brief Is of type FTFE. */
+#define FSL_FEATURE_FLASH_IS_FTFE (0)
+/* @brief Is of type FTFL. */
+#define FSL_FEATURE_FLASH_IS_FTFL (0)
+/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+/* @brief Has EEPROM region protection (register FEPROT). */
+#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+/* @brief Has data flash region protection (register FDPROT). */
+#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+/* @brief Has flash cache control in FMC module. */
+#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MCM module. */
+#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+/* @brief Has flash cache control in MSCM module. */
+#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+/* @brief Has prefetch speculation control in flash, such as kv5x. */
+#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
+#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+/* @brief P-Flash protection region count. */
+#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+/* @brief Has FlexNVM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+/* @brief Has FlexNVM alias. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
+/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+/* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
+#define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
+/* @brief FlexNVM block count. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+/* @brief FlexNVM block size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+/* @brief FlexNVM sector size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+/* @brief FlexNVM write unit size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+/* @brief FlexNVM data path width. */
+#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+/* @brief Has FlexRAM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+/* @brief FlexRAM size. */
+#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+/* @brief Has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+/* @brief Has 0x01 Read 1s Section command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+/* @brief Has 0x02 Program Check command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+/* @brief Has 0x03 Read Resource command. */
+#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+/* @brief Has 0x06 Program Longword command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+/* @brief Has 0x07 Program Phrase command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+/* @brief Has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+/* @brief Has 0x09 Erase Flash Sector command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+/* @brief Has 0x0B Program Section command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+/* @brief Has 0x40 Read 1s All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x41 Read Once command. */
+#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+/* @brief Has 0x43 Program Once command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+/* @brief Has 0x44 Erase All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x45 Verify Backdoor Access Key command. */
+#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+/* @brief Has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+/* @brief Has 0x49 Erase All Blocks Unsecure command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x4B Erase All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x80 Program Partition command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+/* @brief Has 0x81 Set FlexRAM Function command. */
+#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+/* @brief P-Flash Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Program check command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
+/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
+/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+
+/* GPIO module features */
+
+/* @brief Has GPIO attribute checker register (GACR). */
+#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
+
+/* SAI module features */
+
+/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */
+#define FSL_FEATURE_SAI_HAS_FIFO (0)
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (1)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
+/* @brief Has register of MCR. */
+#define FSL_FEATURE_SAI_HAS_MCR (1)
+/* @brief Has register of MDR */
+#define FSL_FEATURE_SAI_HAS_MDR (0)
+/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
+#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
+/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
+#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0)
+
+/* SLCD module features */
+
+/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]).  */
+#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (1)
+/* @brief Has fast frame rate (register bit GCR[FFR]). */
+#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (1)
+/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */
+#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (0)
+/* @brief Has high reference select (register bit GCR[HREFSEL]). */
+#define FSL_FEATURE_SLCD_HAS_HIGH_REFERENCE_SELECT (0)
+/* @brief Has pad safe (register bit GCR[PADSAFE]). */
+#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (1)
+/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */
+#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0)
+/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */
+#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1)
+/* @brief Total pin number on LCD. */
+#define FSL_FEATURE_SLCD_HAS_PIN_NUM (64)
+/* @brief Total phase number on SLCD. */
+#define FSL_FEATURE_SLCD_HAS_PHASE_NUM (8)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has PF register. */
+#define FSL_FEATURE_LLWU_HAS_PF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+/* @brief Has Version ID Register (LLWU_VERID). */
+#define FSL_FEATURE_LLWU_HAS_VERID (0)
+/* @brief Has Parameter Register (LLWU_PARAM). */
+#define FSL_FEATURE_LLWU_HAS_PARAM (0)
+/* @brief Width of registers of the LLWU. */
+#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+/* @brief Has DMA Enable register (LLWU_DE). */
+#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
+
+/* LPUART module features */
+
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (0)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (0)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (0)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
+
+/* MCGLITE module features */
+
+/* @brief Defines that clock generator is MCG Lite. */
+#define FSL_FEATURE_MCGLITE_MCGLITE (1)
+/* @brief Has Crystal Oscillator Operation Mode Selection. */
+#define FSL_FEATURE_MCGLITE_HAS_HGO0 (1)
+/* @brief Has HCTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HCTRIM (1)
+/* @brief Has HTTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HTTRIM (1)
+/* @brief Has HFTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_HFTRIM (1)
+/* @brief Has LTRIMRNG register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (1)
+/* @brief Has LFTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LFTRIM (1)
+/* @brief Has LSTRIM register available. */
+#define FSL_FEATURE_MCGLITE_HAS_LSTRIM (1)
+/* @brief Has External Clock Source Frequency Range Selection. */
+#define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (1)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (0)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+/* @brief Has timer enable control. */
+#define FSL_FEATURE_PIT_HAS_MDIS (1)
+/* @brief Has ERRATA 7914. */
+#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (0)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (0)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (0)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (1)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (1)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (0)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+/* @brief Has Tamper Interrupt Register (register TIR). */
+#define FSL_FEATURE_RTC_HAS_TIR (0)
+/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
+/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
+/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
+/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
+/* @brief Has Tamper Detect Register (register TDR). */
+#define FSL_FEATURE_RTC_HAS_TDR (0)
+/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
+/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
+/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
+/* @brief Has Tamper Time Seconds Register (register TTSR). */
+#define FSL_FEATURE_RTC_HAS_TTSR (0)
+/* @brief Has Pin Configuration Register (register PCR). */
+#define FSL_FEATURE_RTC_HAS_PCR (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+/* @brief Has UIDH registers. */
+#define FSL_FEATURE_SIM_HAS_UIDH (0)
+/* @brief Has UIDM registers. */
+#define FSL_FEATURE_SIM_HAS_UIDM (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 1(VLLS1). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+/* @brief Width of SMC registers. */
+#define FSL_FEATURE_SMC_REG_WIDTH (8)
+
+/* SPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_SPI_HAS_FIFO (1)
+/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
+#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
+#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
+    (((x) == SPI0) ? (0) : \
+    (((x) == SPI1) ? (4) : (-1)))
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
+/* @brief The data register name has postfix (L as low and H as high). */
+#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    (((x) == TPM0) ? (6) : \
+    (((x) == TPM1) ? (2) : \
+    (((x) == TPM2) ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Whether TRIG register has effect. */
+#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \
+    (((x) == TPM0) ? (1) : \
+    (((x) == TPM1) ? (0) : \
+    (((x) == TPM2) ? (0) : (-1))))
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (0)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Whether POL register has effect. */
+#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (0)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0)
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (0)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0)
+/* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */
+#define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0)
+/* @brief Whether 32 bits counter has effect. */
+#define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (0)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZEn(x) (0)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* USB module features */
+
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+/* @brief Number of endpoints supported */
+#define FSL_FEATURE_USB_ENDPT_COUNT (16)
+/* @brief Has STALL_IL/OL_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
+/* @brief Has STALL_IH/OH_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (0)
+
+#endif /* _MCXC444_FEATURES_H_ */
+
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/arm/startup_MCXC444.S b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/arm/startup_MCXC444.S
new file mode 100644
index 0000000000..f60728f00f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/arm/startup_MCXC444.S
@@ -0,0 +1,315 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_MCXC444.s                                              */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                      */
+/*            MCXC444                                                        */
+/*  @version: 1.0                                                            */
+/*  @date:    2024-3-11                                                      */
+/*  @build:   b240401                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2024 NXP                                                   */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+    .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   Image$$ARM_LIB_STACK$$ZI$$Limit                 /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
+    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
+    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
+    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
+    .long   Reserved20_IRQHandler                           /* Reserved interrupt*/
+    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
+    .long   PMC_IRQHandler                                  /* Low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 single interrupt vector for all sources*/
+    .long   SPI1_IRQHandler                                 /* SPI1 single interrupt vector for all sources*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   UART2_FLEXIO_IRQHandler                         /* UART2 or FLEXIO*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   TPM0_IRQHandler                                 /* TPM0 single interrupt vector for all sources*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   RTC_IRQHandler                                  /* RTC alarm*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   I2S0_IRQHandler                                 /* I2S0 interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   Reserved42_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved43_IRQHandler                           /* Reserved interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
+    .long   LCD_IRQHandler                                  /* LCD interrupt*/
+    .long   PORTA_IRQHandler                                /* PORTA Pin detect*/
+    .long   PORTC_PORTD_IRQHandler                          /* Single interrupt vector for PORTC; PORTD Pin detect*/
+
+    .size    __Vectors, . - __Vectors
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3FFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__Vectors
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+    ldr     r0,=SystemInit
+    blx     r0
+    cpsie   i               /* Unmask interrupts */
+    ldr     r0,=__main
+    bx      r0
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_IRQHandler
+    .type DMA2_IRQHandler, %function
+DMA2_IRQHandler:
+    ldr   r0,=DMA2_DriverIRQHandler
+    bx    r0
+    .size DMA2_IRQHandler, . - DMA2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_IRQHandler
+    .type DMA3_IRQHandler, %function
+DMA3_IRQHandler:
+    ldr   r0,=DMA3_DriverIRQHandler
+    bx    r0
+    .size DMA3_IRQHandler, . - DMA3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C0_IRQHandler
+    .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    ldr   r0,=I2C0_DriverIRQHandler
+    bx    r0
+    .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C1_IRQHandler
+    .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    ldr   r0,=I2C1_DriverIRQHandler
+    bx    r0
+    .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI0_IRQHandler
+    .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    ldr   r0,=SPI0_DriverIRQHandler
+    bx    r0
+    .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI1_IRQHandler
+    .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    ldr   r0,=SPI1_DriverIRQHandler
+    bx    r0
+    .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART0_IRQHandler
+    .type LPUART0_IRQHandler, %function
+LPUART0_IRQHandler:
+    ldr   r0,=LPUART0_DriverIRQHandler
+    bx    r0
+    .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART1_IRQHandler
+    .type LPUART1_IRQHandler, %function
+LPUART1_IRQHandler:
+    ldr   r0,=LPUART1_DriverIRQHandler
+    bx    r0
+    .size LPUART1_IRQHandler, . - LPUART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART2_FLEXIO_IRQHandler
+    .type UART2_FLEXIO_IRQHandler, %function
+UART2_FLEXIO_IRQHandler:
+    ldr   r0,=UART2_FLEXIO_DriverIRQHandler
+    bx    r0
+    .size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2S0_IRQHandler
+    .type I2S0_IRQHandler, %function
+I2S0_IRQHandler:
+    ldr   r0,=I2S0_DriverIRQHandler
+    bx    r0
+    .size I2S0_IRQHandler, . - I2S0_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    DMA0_DriverIRQHandler
+    def_irq_handler    DMA1_DriverIRQHandler
+    def_irq_handler    DMA2_DriverIRQHandler
+    def_irq_handler    DMA3_DriverIRQHandler
+    def_irq_handler    Reserved20_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    I2C0_DriverIRQHandler
+    def_irq_handler    I2C1_DriverIRQHandler
+    def_irq_handler    SPI0_DriverIRQHandler
+    def_irq_handler    SPI1_DriverIRQHandler
+    def_irq_handler    LPUART0_DriverIRQHandler
+    def_irq_handler    LPUART1_DriverIRQHandler
+    def_irq_handler    UART2_FLEXIO_DriverIRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    I2S0_DriverIRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    Reserved42_IRQHandler
+    def_irq_handler    Reserved43_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    LCD_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTC_PORTD_IRQHandler
+
+    .end
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.c
new file mode 100644
index 0000000000..402e564132
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_adc16.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.adc16"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for ADC16 module.
+ *
+ * @param base ADC16 peripheral base address
+ */
+static uint32_t ADC16_GetInstance(ADC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ADC16 bases for each instance. */
+static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to ADC16 clocks for each instance. */
+static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ADC16_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++)
+    {
+        if (s_adc16Bases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_adc16Bases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the ADC16 module.
+ *
+ * param base   ADC16 peripheral base address.
+ * param config Pointer to configuration structure. See "adc16_config_t".
+ */
+void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* ADCx_CFG1. */
+    tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
+    if (kADC16_LongSampleDisabled != config->longSampleMode)
+    {
+        tmp32 |= ADC_CFG1_ADLSMP_MASK;
+    }
+    tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
+    if (true == config->enableLowPower)
+    {
+        tmp32 |= ADC_CFG1_ADLPC_MASK;
+    }
+    base->CFG1 = tmp32;
+
+    /* ADCx_CFG2. */
+    tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
+    if (kADC16_LongSampleDisabled != config->longSampleMode)
+    {
+        tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
+    }
+    if (true == config->enableHighSpeed)
+    {
+        tmp32 |= ADC_CFG2_ADHSC_MASK;
+    }
+    if (true == config->enableAsynchronousClock)
+    {
+        tmp32 |= ADC_CFG2_ADACKEN_MASK;
+    }
+    base->CFG2 = tmp32;
+
+    /* ADCx_SC2. */
+    tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
+    tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
+    base->SC2 = tmp32;
+
+    /* ADCx_SC3. */
+    if (true == config->enableContinuousConversion)
+    {
+        base->SC3 |= ADC_SC3_ADCO_MASK;
+    }
+    else
+    {
+        base->SC3 &= ~ADC_SC3_ADCO_MASK;
+    }
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+    ADC16_SetHardwareAverage(base, config->hardwareAverageMode);
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+}
+
+/*!
+ * brief De-initializes the ADC16 module.
+ *
+ * param base ADC16 peripheral base address.
+ */
+void ADC16_Deinit(ADC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets an available pre-defined settings for the converter's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings. The default values are as
+ * follows.
+ * code
+ *   config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
+ *   config->clockSource                = kADC16_ClockSourceAsynchronousClock;
+ *   config->enableAsynchronousClock    = false;
+ *   config->clockDivider               = kADC16_ClockDivider8;
+ *   config->resolution                 = kADC16_ResolutionSE12Bit;
+ *   config->longSampleMode             = kADC16_LongSampleDisabled;
+ *   config->enableHighSpeed            = false;
+ *   config->enableLowPower             = false;
+ *   config->enableContinuousConversion = false;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
+void ADC16_GetDefaultConfig(adc16_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
+    config->clockSource                = kADC16_ClockSourceAsynchronousClock;
+    config->enableAsynchronousClock    = false;
+    config->clockDivider               = kADC16_ClockDivider8;
+    config->resolution                 = kADC16_ResolutionSE12Bit;
+    config->longSampleMode             = kADC16_LongSampleDisabled;
+    config->enableHighSpeed            = false;
+    config->enableLowPower             = false;
+    config->enableContinuousConversion = false;
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+    config->hardwareAverageMode = kADC16_HardwareAverageDisabled;
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+/*!
+ * brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
+ * Execute the calibration before using the converter. Note that the hardware trigger should be used
+ * during the calibration.
+ *
+ * param  base ADC16 peripheral base address.
+ *
+ * return                 Execution status.
+ * retval kStatus_Success Calibration is done successfully.
+ * retval kStatus_Fail    Calibration has failed.
+ */
+status_t ADC16_DoAutoCalibration(ADC_Type *base)
+{
+    bool bHWTrigger = false;
+    uint32_t tmp32;
+    status_t status = kStatus_Success;
+
+    /* The calibration would be failed when in hardwar mode.
+     * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
+    if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
+    {
+        bHWTrigger = true;
+        base->SC2 &= ~ADC_SC2_ADTRG_MASK;
+    }
+
+    /* Clear the CALF and launch the calibration. */
+    base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
+    while (0U == ((uint32_t)kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
+    {
+        /* Check the CALF when the calibration is active. */
+        if (0U != ((uint32_t)kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
+        {
+            status = kStatus_Fail;
+            break;
+        }
+    }
+    (void)base->R[0]; /* Dummy read to clear COCO caused by calibration. */
+
+    /* Restore the hardware trigger setting if it was enabled before. */
+    if (bHWTrigger)
+    {
+        base->SC2 |= ADC_SC2_ADTRG_MASK;
+    }
+    /* Check the CALF at the end of calibration. */
+    if (0U != ((uint32_t)kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
+    {
+        status = kStatus_Fail;
+    }
+    if (kStatus_Success != status) /* Check if the calibration process is succeed. */
+    {
+        return status;
+    }
+
+    /* Calculate the calibration values. */
+    tmp32 = base->CLP0;
+    tmp32 += base->CLP1;
+    tmp32 += base->CLP2;
+    tmp32 += base->CLP3;
+    tmp32 += base->CLP4;
+    tmp32 += base->CLPS;
+    tmp32    = 0x8000U | (tmp32 >> 1U);
+    base->PG = tmp32;
+
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    tmp32 = base->CLM0;
+    tmp32 += base->CLM1;
+    tmp32 += base->CLM2;
+    tmp32 += base->CLM3;
+    tmp32 += base->CLM4;
+    tmp32 += base->CLMS;
+    tmp32    = 0x8000U | (tmp32 >> 1U);
+    base->MG = tmp32;
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * brief Sets the channel mux mode.
+ *
+ * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
+ * indicated channel.
+ *
+ * param base ADC16 peripheral base address.
+ * param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
+ */
+void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
+{
+    if (kADC16_ChannelMuxA == mode)
+    {
+        base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
+    }
+    else /* kADC16_ChannelMuxB. */
+    {
+        base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
+    }
+}
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
+ * result
+ * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate
+ * reference
+ * manual for more information.
+ *
+ * param base     ADC16 peripheral base address.
+ * param config   Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
+ */
+void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
+{
+    uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
+
+    if (NULL == config) /* Pass "NULL" to disable the feature. */
+    {
+        base->SC2 = tmp32;
+        return;
+    }
+    /* Enable the feature. */
+    tmp32 |= ADC_SC2_ACFE_MASK;
+
+    /* Select the hardware compare working mode. */
+    switch (config->hardwareCompareMode)
+    {
+        case kADC16_HardwareCompareMode0:
+            break;
+        case kADC16_HardwareCompareMode1:
+            tmp32 |= ADC_SC2_ACFGT_MASK;
+            break;
+        case kADC16_HardwareCompareMode2:
+            tmp32 |= ADC_SC2_ACREN_MASK;
+            break;
+        case kADC16_HardwareCompareMode3:
+            tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
+            break;
+        default:
+            assert(false);
+            break;
+    }
+    base->SC2 = tmp32;
+
+    /* Load the compare values. */
+    base->CV1 = ADC_CV1_CV(config->value1);
+    base->CV2 = ADC_CV2_CV(config->value2);
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * brief Sets the hardware average mode.
+ *
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
+ * multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
+ *
+ * param base  ADC16 peripheral base address.
+ * param mode  Setting the hardware average mode. See "adc16_hardware_average_mode_t".
+ */
+void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
+{
+    uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
+
+    if (kADC16_HardwareAverageDisabled != mode)
+    {
+        tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
+    }
+    base->SC3 = tmp32;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * brief Configures the PGA for the converter's front end.
+ *
+ * param base    ADC16 peripheral base address.
+ * param config  Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
+ */
+void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
+{
+    uint32_t tmp32;
+
+    if (!config) /* Passing "NULL" is to disable the feature. */
+    {
+        base->PGA = 0U;
+        return;
+    }
+
+    /* Enable the PGA and set the gain value. */
+    tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
+
+    /* Configure the misc features for PGA. */
+    if (config->enableRunInNormalMode)
+    {
+        tmp32 |= ADC_PGA_PGALPb_MASK;
+    }
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    if (config->disablePgaChopping)
+    {
+        tmp32 |= ADC_PGA_PGACHPb_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    if (config->enableRunInOffsetMeasurement)
+    {
+        tmp32 |= ADC_PGA_PGAOFSM_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+    base->PGA = tmp32;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * brief  Gets the status flags of the converter.
+ *
+ * param  base ADC16 peripheral base address.
+ *
+ * return      Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
+ */
+uint32_t ADC16_GetStatusFlags(ADC_Type *base)
+{
+    uint32_t ret = 0;
+
+    if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
+    {
+        ret |= (uint32_t)kADC16_ActiveFlag;
+    }
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
+    {
+        ret |= (uint32_t)kADC16_CalibrationFailedFlag;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+    return ret;
+}
+
+/*!
+ * brief  Clears the status flags of the converter.
+ *
+ * param  base ADC16 peripheral base address.
+ * param  mask Mask value for the cleared flags. See "_adc16_status_flags".
+ */
+void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    if (0U != (mask & (uint32_t)kADC16_CalibrationFailedFlag))
+    {
+        base->SC3 |= ADC_SC3_CALF_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+}
+
+/*!
+ * brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B
+ * registers. The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
+ * hardware
+ * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for
+ * the
+ * number of SC1n registers (channel groups) specific to this device.  Channel group 1 or greater are not used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * param base          ADC16 peripheral base address.
+ * param channelGroup  Channel group index.
+ * param config        Pointer to the "adc16_channel_config_t" structure for the conversion channel.
+ */
+void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
+{
+    assert(channelGroup < ADC_SC1_COUNT);
+    assert(NULL != config);
+
+    uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
+
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    /* Enable the differential conversion. */
+    if (true == config->enableDifferentialConversion)
+    {
+        sc1 |= ADC_SC1_DIFF_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+    /* Enable the interrupt when the conversion is done. */
+    if (true == config->enableInterruptOnConversionCompleted)
+    {
+        sc1 |= ADC_SC1_AIEN_MASK;
+    }
+    base->SC1[channelGroup] = sc1;
+}
+
+/*!
+ * brief  Gets the status flags of channel.
+ *
+ * param  base         ADC16 peripheral base address.
+ * param  channelGroup Channel group index.
+ *
+ * return              Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
+ */
+uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
+{
+    assert(channelGroup < ADC_SC1_COUNT);
+
+    uint32_t ret = 0U;
+
+    if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
+    {
+        ret |= (uint32_t)kADC16_ChannelConversionDoneFlag;
+    }
+    return ret;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.h
new file mode 100644
index 0000000000..3665e8db7d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_adc16.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_ADC16_H_
+#define FSL_ADC16_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup adc16
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief ADC16 driver version 2.3.0. */
+#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+
+/*! @} */
+
+/*!
+ * @brief Channel status flags.
+ */
+enum _adc16_channel_status_flags
+{
+    kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
+};
+
+/*!
+ * @brief Converter status flags.
+ */
+enum _adc16_status_flags
+{
+    kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
+#endif                                                /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+};
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Channel multiplexer mode for each channel.
+ *
+ * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
+ * are the different channels that share the same channel number.
+ */
+typedef enum _adc_channel_mux_mode
+{
+    kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
+    kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
+} adc16_channel_mux_mode_t;
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Clock divider for the converter.
+ */
+typedef enum _adc16_clock_divider
+{
+    kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
+    kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
+    kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
+    kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
+} adc16_clock_divider_t;
+
+/*!
+ *@brief Converter's resolution.
+ */
+typedef enum _adc16_resolution
+{
+    /* This group of enumeration is for internal use which is related to register setting. */
+    kADC16_Resolution8or9Bit   = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
+    kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
+    kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
+
+    /* This group of enumeration is for a public user. */
+    kADC16_ResolutionSE8Bit  = kADC16_Resolution8or9Bit,   /*!< Single End 8-bit. */
+    kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
+    kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    kADC16_ResolutionDF9Bit  = kADC16_Resolution8or9Bit,   /*!< Differential Sample 9-bit. */
+    kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
+    kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
+#endif                                                     /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
+    /* 16-bit is supported by default. */
+    kADC16_Resolution16Bit   = 3U,                     /*!< Single End 16-bit or Differential Sample 16-bit. */
+    kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
+#endif                                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+#endif                                                 /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
+} adc16_resolution_t;
+
+/*!
+ * @brief Clock source.
+ */
+typedef enum _adc16_clock_source
+{
+    kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
+    kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
+    kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
+    kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
+
+    /* Chip defined clock source */
+    kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
+} adc16_clock_source_t;
+
+/*!
+ * @brief Long sample mode.
+ */
+typedef enum _adc16_long_sample_mode
+{
+    kADC16_LongSampleCycle24  = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
+    kADC16_LongSampleCycle16  = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
+    kADC16_LongSampleCycle10  = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
+    kADC16_LongSampleCycle6   = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
+    kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
+} adc16_long_sample_mode_t;
+
+/*!
+ * @brief Reference voltage source.
+ */
+typedef enum _adc16_reference_voltage_source
+{
+    kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
+    kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
+#if defined(FSL_FEATURE_ADC16_HAS_VREF_BANDGAP) && FSL_FEATURE_ADC16_HAS_VREF_BANDGAP
+    kADC16_ReferenceVoltageSourceBandgap = 2U, /*!< For bandgap voltage from PMC. */
+#endif                                         /* FSL_FEATURE_ADC16_HAS_VREF_BANDGAP */
+} adc16_reference_voltage_source_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Hardware average mode.
+ */
+typedef enum _adc16_hardware_average_mode
+{
+    kADC16_HardwareAverageCount4   = 0U, /*!< For hardware average with 4 samples. */
+    kADC16_HardwareAverageCount8   = 1U, /*!< For hardware average with 8 samples. */
+    kADC16_HardwareAverageCount16  = 2U, /*!< For hardware average with 16 samples. */
+    kADC16_HardwareAverageCount32  = 3U, /*!< For hardware average with 32 samples. */
+    kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
+} adc16_hardware_average_mode_t;
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+/*!
+ * @brief Hardware compare mode.
+ */
+typedef enum _adc16_hardware_compare_mode
+{
+    kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
+    kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
+    kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
+                                           else, value1 > x > value2. */
+    kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
+                                           else x >= value1 || x <= value2. */
+} adc16_hardware_compare_mode_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief PGA's Gain mode.
+ */
+typedef enum _adc16_pga_gain
+{
+    kADC16_PGAGainValueOf1  = 0U, /*!< For amplifier gain of 1.  */
+    kADC16_PGAGainValueOf2  = 1U, /*!< For amplifier gain of 2.  */
+    kADC16_PGAGainValueOf4  = 2U, /*!< For amplifier gain of 4.  */
+    kADC16_PGAGainValueOf8  = 3U, /*!< For amplifier gain of 8.  */
+    kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
+    kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
+    kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
+} adc16_pga_gain_t;
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * @brief ADC16 converter configuration.
+ */
+typedef struct _adc16_config
+{
+    adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
+    adc16_clock_source_t clockSource;                        /*!< Select the input clock source to converter. */
+    bool enableAsynchronousClock;                            /*!< Enable the asynchronous clock output. */
+    adc16_clock_divider_t clockDivider;                      /*!< Select the divider of input clock source. */
+    adc16_resolution_t resolution;                           /*!< Select the sample resolution mode. */
+    adc16_long_sample_mode_t longSampleMode;                 /*!< Select the long sample mode. */
+    bool enableHighSpeed;                                    /*!< Enable the high-speed mode. */
+    bool enableLowPower;                                     /*!< Enable low power. */
+    bool enableContinuousConversion;                         /*!< Enable continuous conversion mode. */
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+    adc16_hardware_average_mode_t hardwareAverageMode; /*!< Set hardware average mode. */
+#endif                                                 /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+} adc16_config_t;
+
+/*!
+ * @brief ADC16 Hardware comparison configuration.
+ */
+typedef struct _adc16_hardware_compare_config
+{
+    adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
+                                                            See "adc16_hardware_compare_mode_t". */
+    int16_t value1;                                    /*!< Setting value1 for hardware compare mode. */
+    int16_t value2;                                    /*!< Setting value2 for hardware compare mode. */
+} adc16_hardware_compare_config_t;
+
+/*!
+ * @brief ADC16 channel conversion configuration.
+ */
+typedef struct _adc16_channel_config
+{
+    uint32_t channelNumber;                    /*!< Setting the conversion channel number. The available range is 0-31.
+                                                    See channel connection information for each chip in Reference
+                                                    Manual document. */
+    bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    bool enableDifferentialConversion; /*!< Using Differential sample mode. */
+#endif                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+} adc16_channel_config_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief ADC16 programmable gain amplifier configuration.
+ */
+typedef struct _adc16_pga_config
+{
+    adc16_pga_gain_t pgaGain;   /*!< Setting PGA gain. */
+    bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    bool disablePgaChopping; /*!< Disable the PGA chopping function.
+                                  The PGA employs chopping to remove/reduce offset and 1/f noise and offers
+                                  an offset measurement configuration that aids the offset calibration. */
+#endif                       /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
+                                            When this feature is enabled, the PGA disconnects itself from the external
+                                            inputs and auto-configures into offset measurement mode. With this field
+                                            set, run the ADC in the recommended settings and enable the maximum hardware
+                                            averaging to get the PGA offset number. The output is the
+                                            (PGA offset * (64+1)) for the given PGA setting. */
+#endif                                 /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+} adc16_pga_config_t;
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the ADC16 module.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param config Pointer to configuration structure. See "adc16_config_t".
+ */
+void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
+
+/*!
+ * @brief De-initializes the ADC16 module.
+ *
+ * @param base ADC16 peripheral base address.
+ */
+void ADC16_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Gets an available pre-defined settings for the converter's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings. The default values are as
+ * follows.
+ * @code
+ *   config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
+ *   config->clockSource                = kADC16_ClockSourceAsynchronousClock;
+ *   config->enableAsynchronousClock    = false;
+ *   config->clockDivider               = kADC16_ClockDivider8;
+ *   config->resolution                 = kADC16_ResolutionSE12Bit;
+ *   config->longSampleMode             = kADC16_LongSampleDisabled;
+ *   config->enableHighSpeed            = false;
+ *   config->enableLowPower             = false;
+ *   config->enableContinuousConversion = false;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void ADC16_GetDefaultConfig(adc16_config_t *config);
+
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+/*!
+ * @brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
+ * Execute the calibration before using the converter. Note that the hardware trigger should be used
+ * during the calibration.
+ *
+ * @param  base ADC16 peripheral base address.
+ *
+ * @return                 Execution status.
+ * @retval kStatus_Success Calibration is done successfully.
+ * @retval kStatus_Fail    Calibration has failed.
+ */
+status_t ADC16_DoAutoCalibration(ADC_Type *base);
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+/*!
+ * @brief Sets the offset value for the conversion result.
+ *
+ * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
+ * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
+ *
+ * @param base  ADC16 peripheral base address.
+ * @param value Setting offset value.
+ */
+static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
+{
+    base->OFS = (uint32_t)(value);
+}
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+
+/*! @} */
+
+/*!
+ * @name Advanced Features
+ * @{
+ */
+
+#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
+/*!
+ * @brief Enables generating the DMA trigger when the conversion is complete.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
+ */
+static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SC2 |= ADC_SC2_DMAEN_MASK;
+    }
+    else
+    {
+        base->SC2 &= ~ADC_SC2_DMAEN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+
+/*!
+ * @brief Enables the hardware trigger mode.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
+ */
+static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SC2 |= ADC_SC2_ADTRG_MASK;
+    }
+    else
+    {
+        base->SC2 &= ~ADC_SC2_ADTRG_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Sets the channel mux mode.
+ *
+ * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
+ * indicated channel.
+ *
+ * @param base ADC16 peripheral base address.
+ * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
+ */
+void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
+ * result
+ * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate
+ * reference
+ * manual for more information.
+ *
+ * @param base     ADC16 peripheral base address.
+ * @param config   Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
+ */
+void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Sets the hardware average mode.
+ *
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
+ * multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
+ *
+ * @param base  ADC16 peripheral base address.
+ * @param mode  Setting the hardware average mode. See "adc16_hardware_average_mode_t".
+ */
+void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief Configures the PGA for the converter's front end.
+ *
+ * @param base    ADC16 peripheral base address.
+ * @param config  Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
+ */
+void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * @brief  Gets the status flags of the converter.
+ *
+ * @param  base ADC16 peripheral base address.
+ *
+ * @return      Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
+ */
+uint32_t ADC16_GetStatusFlags(ADC_Type *base);
+
+/*!
+ * @brief  Clears the status flags of the converter.
+ *
+ * @param  base ADC16 peripheral base address.
+ * @param  mask Mask value for the cleared flags. See "_adc16_status_flags".
+ */
+void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Enable/disable ADC Asynchronous clock output to other modules.
+ *
+ * @param base ADC16 peripheral base address.
+ * @param enable Used to enable/disable ADC ADACK output.
+ *          - \b true Asynchronous clock and clock output is enabled regardless of the state of the ADC.
+ *          - \b false Asynchronous clock output disabled, asynchronous clock is enabled only if it is selected as
+ *                     input clock and a conversion is active.
+ */
+static inline void ADC16_EnableAsynchronousClockOutput(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG2 |= ADC_CFG2_ADACKEN_MASK;
+    }
+    else
+    {
+        base->CFG2 &= ~ADC_CFG2_ADACKEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Conversion Channel
+ * @{
+ */
+
+/*!
+ * @brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B
+ * registers. The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
+ * hardware
+ * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for
+ * the
+ * number of SC1n registers (channel groups) specific to this device.  Channel group 1 or greater are not used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * @param base          ADC16 peripheral base address.
+ * @param channelGroup  Channel group index.
+ * @param config        Pointer to the "adc16_channel_config_t" structure for the conversion channel.
+ */
+void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
+
+/*!
+ * @brief  Gets the conversion value.
+ *
+ * @param  base         ADC16 peripheral base address.
+ * @param  channelGroup Channel group index.
+ *
+ * @return              Conversion value.
+ */
+static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
+{
+    assert(channelGroup < (uint32_t)FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT);
+
+    return base->R[channelGroup];
+}
+
+/*!
+ * @brief  Gets the status flags of channel.
+ *
+ * @param  base         ADC16 peripheral base address.
+ * @param  channelGroup Channel group index.
+ *
+ * @return              Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
+ */
+uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* FSL_ADC16_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.c
new file mode 100644
index 0000000000..ea0fb7f758
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+
+#if (defined(OSC) && !(defined(OSC0)))
+#define OSC0 OSC
+#endif
+
+#define MCG_HIRC_FREQ (48000000U)
+#define MCG_LIRC_FREQ1 (2000000U)
+#define MCG_LIRC_FREQ2 (8000000U)
+
+#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_MC_LIRC_DIV2_VAL ((MCG->MC & MCG_MC_LIRC_DIV2_MASK) >> MCG_MC_LIRC_DIV2_SHIFT)
+#define MCG_C2_IRCS_VAL ((MCG->C2 & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+
+#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External XTAL0 (OSC0) clock frequency. */
+volatile uint32_t g_xtal0Freq;
+/* External XTAL32K clock frequency. */
+volatile uint32_t g_xtal32Freq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the current MCG_Lite LIRC_CLK frequency in Hz.
+ *
+ * This function will return the LIRC_CLK value in frequency(Hz) based
+ * on current MCG_Lite configurations and settings. It is an internal function.
+ *
+ * @return MCG_Lite LIRC_CLK frequency.
+ */
+static uint32_t CLOCK_GetLircClkFreq(void);
+
+/*!
+ * @brief Get RANGE value based on OSC frequency.
+ *
+ * To setup external crystal oscillator, must set the register bits RANGE base
+ * on the crystal frequency. This function returns the RANGE base on the input
+ * frequency. This is an internal function.
+ *
+ * @return RANGE value.
+ */
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t CLOCK_GetLircClkFreq(void)
+{
+    static const uint32_t lircFreqs[] = {MCG_LIRC_FREQ1, MCG_LIRC_FREQ2};
+    uint32_t freq;
+
+    /* Check whether the LIRC is enabled. */
+    if (((MCG->C1 & MCG_C1_IRCLKEN_MASK) != 0U) || ((uint8_t)kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL))
+    {
+        freq = lircFreqs[MCG_C2_IRCS_VAL];
+    }
+    else
+    {
+        freq = 0U;
+    }
+
+    return freq;
+}
+
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
+{
+    uint8_t range;
+
+    if (freq <= 39063U)
+    {
+        range = 0U;
+    }
+    else if (freq <= 8000000U)
+    {
+        range = 1U;
+    }
+    else
+    {
+        range = 2U;
+    }
+
+    return range;
+}
+
+/*!
+ * brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkFreq(void)
+{
+    uint32_t freq;
+
+    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
+    {
+        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+        assert(g_xtal0Freq);
+        freq = g_xtal0Freq;
+    }
+    else
+    {
+        freq = 0U;
+    }
+
+    return freq;
+}
+
+/*!
+ * brief Get the external reference 32K clock frequency (ERCLK32K).
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetEr32kClkFreq(void)
+{
+    uint32_t freq;
+
+    switch (SIM_SOPT1_OSC32KSEL_VAL)
+    {
+        case 0U: /* OSC 32k clock  */
+            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
+            break;
+        case 2U: /* RTC 32k clock  */
+            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
+            assert(g_xtal32Freq);
+            freq = g_xtal32Freq;
+            break;
+        case 3U: /* LPO clock      */
+            freq = LPO_CLK_FREQ;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+/*!
+ * brief Get the platform clock frequency.
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPlatClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+}
+
+/*!
+ * brief Get the flash clock frequency.
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlashClkFreq(void)
+{
+    uint32_t freq;
+
+    freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+    freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1U);
+
+    return freq;
+}
+
+/*!
+ * brief Get the bus clock frequency.
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetBusClkFreq(void)
+{
+    uint32_t freq;
+
+    freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+    freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1U);
+
+    return freq;
+}
+
+/*!
+ * brief Get the core clock or system clock frequency.
+ *
+ * return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+}
+
+/*!
+ * brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ * The MCG must be properly configured before using this function.
+ *
+ * param clockName Clock names defined in clock_name_t
+ * return Clock frequency value in Hertz
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+        case kCLOCK_PlatClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+            break;
+        case kCLOCK_BusClk:
+        case kCLOCK_FlashClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1U);
+            freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1U);
+            break;
+        case kCLOCK_Er32kClk:
+            freq = CLOCK_GetEr32kClkFreq();
+            break;
+        case kCLOCK_Osc0ErClk:
+            freq = CLOCK_GetOsc0ErClkFreq();
+            break;
+        case kCLOCK_McgInternalRefClk:
+            freq = CLOCK_GetInternalRefClkFreq();
+            break;
+        case kCLOCK_McgPeriphClk:
+        case kCLOCK_McgIrc48MClk:
+            freq = CLOCK_GetPeriphClkFreq();
+            break;
+        case kCLOCK_LpoClk:
+            freq = LPO_CLK_FREQ;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*!
+ * brief Set the clock configure in SIM module.
+ *
+ * This function sets system layer clock settings in SIM module.
+ *
+ * param config Pointer to the configure structure.
+ */
+void CLOCK_SetSimConfig(sim_clock_config_t const *config)
+{
+    SIM->CLKDIV1 = config->clkdiv1;
+    CLOCK_SetEr32kClock(config->er32kSrc);
+}
+
+/*! brief Enable USB FS clock.
+ *
+ * param src  USB FS clock source.
+ * param freq The frequency specified by src.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB FS clock.
+ */
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbfs0);
+
+    if (kCLOCK_UsbSrcExt == src)
+    {
+        SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
+    }
+    else
+    {
+        SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
+    }
+
+    CLOCK_EnableClock(kCLOCK_Usbfs0);
+
+    if (kCLOCK_UsbSrcIrc48M == src)
+    {
+        USB0->CLK_RECOVER_IRC_EN = 0x03U;
+        USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+    }
+
+    return ret;
+}
+
+/*!
+ * brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
+ *
+ * This function gets the MCG_Lite internal reference clock frequency in Hz based
+ * on the current MCG register value.
+ *
+ * return The frequency of MCGIRCLK.
+ */
+uint32_t CLOCK_GetInternalRefClkFreq(void)
+{
+    uint8_t divider1 = MCG_SC_FCRDIV_VAL;
+    uint8_t divider2 = MCG_MC_LIRC_DIV2_VAL;
+    /* LIRC internal reference clock is selected*/
+    return CLOCK_GetLircClkFreq() >> (divider1 + divider2);
+}
+
+/*
+ * brief Gets the current MCGPCLK frequency.
+ *
+ * This function gets the MCGPCLK frequency in Hz based on the current MCG_Lite
+ * register settings.
+ *
+ * return The frequency of MCGPCLK.
+ */
+uint32_t CLOCK_GetPeriphClkFreq(void)
+{
+    uint32_t freq;
+
+    /* Check whether the HIRC is enabled. */
+    if (((MCG->MC & MCG_MC_HIRCEN_MASK) != 0U) || ((uint8_t)kMCGLITE_ClkSrcHirc == MCG_S_CLKST_VAL))
+    {
+        freq = MCG_HIRC_FREQ;
+    }
+    else
+    {
+        freq = 0U;
+    }
+
+    return freq;
+}
+
+/*!
+ * brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency.
+ *
+ * This function gets the MCG_Lite output clock frequency in Hz based on the current
+ * MCG_Lite register value.
+ *
+ * return The frequency of MCGOUTCLK.
+ */
+uint32_t CLOCK_GetOutClkFreq(void)
+{
+    uint32_t freq;
+
+    switch (MCG_S_CLKST_VAL)
+    {
+        case (uint8_t)kMCGLITE_ClkSrcHirc:
+            freq = MCG_HIRC_FREQ;
+            break;
+        case (uint8_t)kMCGLITE_ClkSrcLirc:
+            freq = CLOCK_GetLircClkFreq() >> MCG_SC_FCRDIV_VAL;
+            break;
+        case (uint8_t)kMCGLITE_ClkSrcExt:
+            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+            assert(g_xtal0Freq);
+            freq = g_xtal0Freq;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/*!
+ * brief Gets the current MCG_Lite mode.
+ *
+ * This function checks the MCG_Lite registers and determines the current MCG_Lite mode.
+ *
+ * return The current MCG_Lite mode or error code.
+ */
+mcglite_mode_t CLOCK_GetMode(void)
+{
+    mcglite_mode_t mode;
+
+    switch (MCG_S_CLKST_VAL)
+    {
+        case (uint8_t)kMCGLITE_ClkSrcHirc: /* HIRC */
+            mode = kMCGLITE_ModeHirc48M;
+            break;
+        case (uint8_t)kMCGLITE_ClkSrcLirc: /* LIRC */
+            if ((uint8_t)kMCGLITE_Lirc2M == MCG_C2_IRCS_VAL)
+            {
+                mode = kMCGLITE_ModeLirc2M;
+            }
+            else
+            {
+                mode = kMCGLITE_ModeLirc8M;
+            }
+            break;
+        case (uint8_t)kMCGLITE_ClkSrcExt: /* EXT  */
+            mode = kMCGLITE_ModeExt;
+            break;
+        default:
+            mode = kMCGLITE_ModeError;
+            break;
+    }
+
+    return mode;
+}
+
+/*!
+ * brief Sets the MCG_Lite configuration.
+ *
+ * This function configures the MCG_Lite, includes the output clock source, MCGIRCLK
+ * settings, HIRC settings, and so on. See ref mcglite_config_t for details.
+ *
+ * param  targetConfig Pointer to the target MCG_Lite mode configuration structure.
+ * return Error code.
+ */
+status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig)
+{
+    assert(targetConfig);
+
+    /*
+     * If switch between LIRC8M and LIRC2M, need to switch to HIRC mode first,
+     * because could not switch directly.
+     */
+    if (((uint8_t)kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL) && (kMCGLITE_ClkSrcLirc == targetConfig->outSrc) &&
+        (MCG_C2_IRCS_VAL != (uint8_t)(targetConfig->ircs)))
+    {
+        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCGLITE_ClkSrcHirc));
+        while ((uint8_t)kMCGLITE_ClkSrcHirc != MCG_S_CLKST_VAL)
+        {
+        }
+    }
+
+    /* Set configuration now. */
+    MCG->SC = MCG_SC_FCRDIV(targetConfig->fcrdiv);
+    MCG->MC = MCG_MC_HIRCEN(targetConfig->hircEnableInNotHircMode) | MCG_MC_LIRC_DIV2(targetConfig->lircDiv2);
+    MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | MCG_C2_IRCS(targetConfig->ircs));
+    MCG->C1 = MCG_C1_CLKS(targetConfig->outSrc) | targetConfig->irclkEnableMode;
+
+    /*
+     * If external oscillator used and MCG_Lite is set to EXT mode, need to
+     * wait for the OSC stable.
+     */
+    if (((MCG->C2 & MCG_C2_EREFS0_MASK) != 0U) && (kMCGLITE_ClkSrcExt == targetConfig->outSrc))
+    {
+        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
+        {
+        }
+    }
+
+    /* Wait for clock source change completed. */
+    while ((uint8_t)targetConfig->outSrc != MCG_S_CLKST_VAL)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the OSC0.
+ *
+ * This function initializes the OSC0 according to the board configuration.
+ *
+ * param  config Pointer to the OSC0 configuration structure.
+ */
+void CLOCK_InitOsc0(osc_config_t const *config)
+{
+    uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
+
+    OSC_SetCapLoad(OSC0, config->capLoad);
+    OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
+
+    MCG->C2 = ((MCG->C2 & MCG_C2_IRCS_MASK) | MCG_C2_RANGE0(range) | (uint8_t)config->workMode);
+
+    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
+    {
+        /* Wait for stable. */
+        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Deinitializes the OSC0.
+ *
+ * This function deinitializes the OSC0.
+ */
+void CLOCK_DeinitOsc0(void)
+{
+    OSC0->CR = 0U;
+    MCG->C2 &= MCG_C2_IRCS_MASK;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.h
new file mode 100644
index 0000000000..273be79fc5
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_clock.h
@@ -0,0 +1,808 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.0.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief External XTAL0 (OSC0) clock frequency.
+ *
+ * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
+ * if XTAL0 is 8 MHz:
+ * @code
+ * CLOCK_InitOsc0(...);
+ * CLOCK_SetXtal0Freq(80000000);
+ * @endcode
+ *
+ * This is important for the multicore platforms where one core needs to set up the
+ * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
+ * to get a valid clock frequency.
+ */
+extern volatile uint32_t g_xtal0Freq;
+
+/*! @brief The external XTAL32/EXTAL32/RTC_CLKIN clock frequency.
+ *
+ * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal32Freq to set the value in the clock driver.
+ *
+ * This is important for the multicore platforms where one core needs to set up
+ * the clock. All other cores need to call the CLOCK_SetXtal32Freq
+ * to get a valid clock frequency.
+ */
+extern volatile uint32_t g_xtal32Freq;
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (48000000UL)
+#endif
+/*! @brief Clock ip name array for DMAMUX. */
+#define DMAMUX_CLOCKS  \
+    {                  \
+        kCLOCK_Dmamux0 \
+    }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS  \
+    {               \
+        kCLOCK_Rtc0 \
+    }
+
+/*! @brief Clock ip name array for SAI. */
+#define SAI_CLOCKS  \
+    {               \
+        kCLOCK_Sai0 \
+    }
+
+/*! @brief Clock ip name array for SPI. */
+#define SPI_CLOCKS               \
+    {                            \
+        kCLOCK_Spi0, kCLOCK_Spi1 \
+    }
+
+/*! @brief Clock ip name array for SLCD. */
+#define SLCD_CLOCKS  \
+    {                \
+        kCLOCK_Slcd0 \
+    }
+
+/*! @brief Clock ip name array for PIT. */
+#define PIT_CLOCKS  \
+    {               \
+        kCLOCK_Pit0 \
+    }
+
+/*! @brief Clock ip name array for PORT. */
+#define PORT_CLOCKS                                                          \
+    {                                                                        \
+        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
+    }
+
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                  \
+    {                                  \
+        kCLOCK_Lpuart0, kCLOCK_Lpuart1 \
+    }
+
+/*! @brief Clock ip name array for DAC. */
+#define DAC_CLOCKS  \
+    {               \
+        kCLOCK_Dac0 \
+    }
+
+/*! @brief Clock ip name array for LPTMR. */
+#define LPTMR_CLOCKS  \
+    {                 \
+        kCLOCK_Lptmr0 \
+    }
+
+/*! @brief Clock ip name array for ADC16. */
+#define ADC16_CLOCKS \
+    {                \
+        kCLOCK_Adc0  \
+    }
+
+/*! @brief Clock ip name array for FLEXIO. */
+#define FLEXIO_CLOCKS  \
+    {                  \
+        kCLOCK_Flexio0 \
+    }
+
+/*! @brief Clock ip name array for VREF. */
+#define VREF_CLOCKS  \
+    {                \
+        kCLOCK_Vref0 \
+    }
+
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS  \
+    {               \
+        kCLOCK_Dma0 \
+    }
+
+/*! @brief Clock ip name array for UART. */
+#define UART_CLOCKS                                      \
+    {                                                    \
+        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Uart2 \
+    }
+
+/*! @brief Clock ip name array for TPM. */
+#define TPM_CLOCKS                            \
+    {                                         \
+        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
+    }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS               \
+    {                            \
+        kCLOCK_I2c0, kCLOCK_I2c1 \
+    }
+
+/*! @brief Clock ip name array for FTF. */
+#define FTF_CLOCKS  \
+    {               \
+        kCLOCK_Ftf0 \
+    }
+
+/*! @brief Clock ip name array for CMP. */
+#define CMP_CLOCKS  \
+    {               \
+        kCLOCK_Cmp0 \
+    }
+
+/*!
+ * @brief LPO clock frequency.
+ */
+#define LPO_CLK_FREQ 1000U
+
+/*! @brief Peripherals clock source definition. */
+#define SYS_CLK kCLOCK_CoreSysClk
+#define BUS_CLK kCLOCK_BusClk
+
+#define I2C0_CLK_SRC SYS_CLK
+#define I2C1_CLK_SRC SYS_CLK
+#define SPI0_CLK_SRC BUS_CLK
+#define SPI1_CLK_SRC SYS_CLK
+#define UART2_CLK_SRC BUS_CLK
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+
+    /* ----------------------------- System layer clock -------------------------------*/
+    kCLOCK_CoreSysClk,    /*!< Core/system clock                                         */
+    kCLOCK_PlatClk,       /*!< Platform clock                                            */
+    kCLOCK_BusClk,        /*!< Bus clock                                                 */
+    kCLOCK_FlexBusClk,    /*!< FlexBus clock                                             */
+    kCLOCK_FlashClk,      /*!< Flash clock                                               */
+    kCLOCK_FastPeriphClk, /*!< Fast peripheral clock                                     */
+    kCLOCK_PllFllSelClk,  /*!< The clock after SIM[PLLFLLSEL].                           */
+
+    /* ---------------------------------- OSC clock -----------------------------------*/
+    kCLOCK_Er32kClk,       /*!< External reference 32K clock (ERCLK32K)                   */
+    kCLOCK_Osc0ErClk,      /*!< OSC0 external reference clock (OSC0ERCLK)                 */
+    kCLOCK_Osc1ErClk,      /*!< OSC1 external reference clock (OSC1ERCLK)                 */
+    kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
+
+    /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
+    kCLOCK_McgFixedFreqClk,   /*!< MCG fixed frequency clock (MCGFFCLK)                      */
+    kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK)                   */
+    kCLOCK_McgFllClk,         /*!< MCGFLLCLK                                                 */
+    kCLOCK_McgPll0Clk,        /*!< MCGPLL0CLK                                                */
+    kCLOCK_McgPll1Clk,        /*!< MCGPLL1CLK                                                */
+    kCLOCK_McgExtPllClk,      /*!< EXT_PLLCLK                                                */
+    kCLOCK_McgPeriphClk,      /*!< MCG peripheral clock (MCGPCLK)                            */
+    kCLOCK_McgIrc48MClk,      /*!< MCG IRC48M clock                                          */
+
+    /* --------------------------------- Other clock ----------------------------------*/
+    kCLOCK_LpoClk, /*!< LPO clock                                                 */
+
+} clock_name_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U), /*!< Use IRC48M.    */
+    kCLOCK_UsbSrcExt    = SIM_SOPT2_USBSRC(0U)  /*!< Use USB_CLKIN. */
+} clock_usb_src_t;
+/*------------------------------------------------------------------------------
+
+ clock_gate_t definition:
+
+ 31                              16                              0
+ -----------------------------------------------------------------
+ | SIM_SCGC register offset       |   control bit offset in SCGC |
+ -----------------------------------------------------------------
+
+ For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
+ SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
+
+              kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
+
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 16U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                            \
+    ((((uint32_t)(reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((uint32_t)(bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+    kCLOCK_I2c0      = CLK_GATE_DEFINE(0x1034U, 6U),
+    kCLOCK_I2c1      = CLK_GATE_DEFINE(0x1034U, 7U),
+    kCLOCK_Uart2     = CLK_GATE_DEFINE(0x1034U, 12U),
+    kCLOCK_Usbfs0    = CLK_GATE_DEFINE(0x1034U, 18U),
+    kCLOCK_Cmp0      = CLK_GATE_DEFINE(0x1034U, 19U),
+    kCLOCK_Vref0     = CLK_GATE_DEFINE(0x1034U, 20U),
+    kCLOCK_Spi0      = CLK_GATE_DEFINE(0x1034U, 22U),
+    kCLOCK_Spi1      = CLK_GATE_DEFINE(0x1034U, 23U),
+
+    kCLOCK_Lptmr0  = CLK_GATE_DEFINE(0x1038U, 0U),
+    kCLOCK_PortA   = CLK_GATE_DEFINE(0x1038U, 9U),
+    kCLOCK_PortB   = CLK_GATE_DEFINE(0x1038U, 10U),
+    kCLOCK_PortC   = CLK_GATE_DEFINE(0x1038U, 11U),
+    kCLOCK_PortD   = CLK_GATE_DEFINE(0x1038U, 12U),
+    kCLOCK_PortE   = CLK_GATE_DEFINE(0x1038U, 13U),
+    kCLOCK_Slcd0   = CLK_GATE_DEFINE(0x1038U, 19U),
+    kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
+    kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U),
+    kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U),
+
+    kCLOCK_Ftf0    = CLK_GATE_DEFINE(0x103CU, 0U),
+    kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
+    kCLOCK_Sai0    = CLK_GATE_DEFINE(0x103CU, 15U),
+    kCLOCK_Pit0    = CLK_GATE_DEFINE(0x103CU, 23U),
+    kCLOCK_Tpm0    = CLK_GATE_DEFINE(0x103CU, 24U),
+    kCLOCK_Tpm1    = CLK_GATE_DEFINE(0x103CU, 25U),
+    kCLOCK_Tpm2    = CLK_GATE_DEFINE(0x103CU, 26U),
+    kCLOCK_Adc0    = CLK_GATE_DEFINE(0x103CU, 27U),
+    kCLOCK_Rtc0    = CLK_GATE_DEFINE(0x103CU, 29U),
+    kCLOCK_Dac0    = CLK_GATE_DEFINE(0x103CU, 31U),
+
+    kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
+} clock_ip_name_t;
+
+/*!@brief SIM configuration structure for clock setting. */
+typedef struct _sim_clock_config
+{
+    uint8_t er32kSrc; /*!< ERCLK32K source selection.   */
+    uint32_t clkdiv1; /*!< SIM_CLKDIV1.                 */
+} sim_clock_config_t;
+
+/*! @brief Oscillator capacitor load setting.*/
+enum _osc_cap_load
+{
+    kOSC_Cap2P  = OSC_CR_SC2P_MASK, /*!< 2  pF capacitor load */
+    kOSC_Cap4P  = OSC_CR_SC4P_MASK, /*!< 4  pF capacitor load */
+    kOSC_Cap8P  = OSC_CR_SC8P_MASK, /*!< 8  pF capacitor load */
+    kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
+};
+
+/*! @brief OSCERCLK enable mode. */
+enum _oscer_enable_mode
+{
+    kOSC_ErClkEnable       = OSC_CR_ERCLKEN_MASK, /*!< Enable.              */
+    kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
+};
+
+/*! @brief The OSC configuration for OSCERCLK. */
+typedef struct _oscer_config
+{
+    uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of \ref _oscer_enable_mode. */
+
+} oscer_config_t;
+
+/*! @brief The OSC work mode. */
+typedef enum _osc_mode
+{
+    kOSC_ModeExt         = 0U,                                    /*!< Use external clock.   */
+    kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK,                    /*!< Oscillator low power. */
+    kOSC_ModeOscHighGain = MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
+} osc_mode_t;
+
+/*!
+ * @brief OSC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the OSC.
+ * When porting to a new board, set the following members
+ * according to the board settings:
+ * 1. freq: The external frequency.
+ * 2. workMode: The OSC module mode.
+ */
+typedef struct _osc_config
+{
+    uint32_t freq;              /*!< External clock frequency.    */
+    uint8_t capLoad;            /*!< Capacitor load setting.      */
+    osc_mode_t workMode;        /*!< OSC work mode setting.       */
+    oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK.  */
+} osc_config_t;
+
+/*! @brief MCG_Lite clock source selection. */
+typedef enum _mcglite_clkout_src
+{
+    kMCGLITE_ClkSrcHirc, /*!< MCGOUTCLK source is HIRC */
+    kMCGLITE_ClkSrcLirc, /*!< MCGOUTCLK source is LIRC */
+    kMCGLITE_ClkSrcExt,  /*!< MCGOUTCLK source is external clock source */
+    kMCGLITE_ClkSrcReserved
+} mcglite_clkout_src_t;
+
+/*! @brief MCG_Lite LIRC select. */
+typedef enum _mcglite_lirc_mode
+{
+    kMCGLITE_Lirc2M, /*!< Slow internal reference(LIRC) 2 MHz clock selected */
+    kMCGLITE_Lirc8M, /*!< Slow internal reference(LIRC) 8 MHz clock selected */
+} mcglite_lirc_mode_t;
+
+/*! @brief MCG_Lite divider factor selection for clock source*/
+typedef enum _mcglite_lirc_div
+{
+    kMCGLITE_LircDivBy1 = 0U, /*!< Divider is 1    */
+    kMCGLITE_LircDivBy2,      /*!< Divider is 2    */
+    kMCGLITE_LircDivBy4,      /*!< Divider is 4    */
+    kMCGLITE_LircDivBy8,      /*!< Divider is 8    */
+    kMCGLITE_LircDivBy16,     /*!< Divider is 16   */
+    kMCGLITE_LircDivBy32,     /*!< Divider is 32   */
+    kMCGLITE_LircDivBy64,     /*!< Divider is 64   */
+    kMCGLITE_LircDivBy128     /*!< Divider is 128  */
+} mcglite_lirc_div_t;
+
+/*! @brief MCG_Lite clock mode definitions */
+typedef enum _mcglite_mode
+{
+    kMCGLITE_ModeHirc48M, /*!< Clock mode is HIRC 48 M  */
+    kMCGLITE_ModeLirc8M,  /*!< Clock mode is LIRC 8 M   */
+    kMCGLITE_ModeLirc2M,  /*!< Clock mode is LIRC 2 M   */
+    kMCGLITE_ModeExt,     /*!< Clock mode is EXT       */
+    kMCGLITE_ModeError    /*!< Unknown mode            */
+} mcglite_mode_t;
+
+/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
+enum _mcglite_irclk_enable_mode
+{
+    kMCGLITE_IrclkEnable       = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable.              */
+    kMCGLITE_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
+};
+
+/*! @brief MCG_Lite configure structure for mode change. */
+typedef struct _mcglite_config
+{
+    mcglite_clkout_src_t outSrc;  /*!< MCGOUT clock select.                */
+    uint8_t irclkEnableMode;      /*!< MCGIRCLK enable mode, OR'ed value of _mcglite_irclk_enable_mode. */
+    mcglite_lirc_mode_t ircs;     /*!< MCG_C2[IRCS].                       */
+    mcglite_lirc_div_t fcrdiv;    /*!< MCG_SC[FCRDIV].                     */
+    mcglite_lirc_div_t lircDiv2;  /*!< MCG_MC[LIRC_DIV2].                  */
+    bool hircEnableInNotHircMode; /*!< HIRC enable when not in HIRC mode.  */
+} mcglite_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name  Which clock to enable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_EnableClock(clock_ip_name_t name)
+{
+    uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+    (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name  Which clock to disable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_DisableClock(clock_ip_name_t name)
+{
+    uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+    (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Set ERCLK32K source.
+ *
+ * @param src The value to set ERCLK32K clock source.
+ */
+static inline void CLOCK_SetEr32kClock(uint32_t src)
+{
+    SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
+}
+
+/*!
+ * @brief Set LPUART0 clock source.
+ *
+ * @param src The value to set LPUART0 clock source.
+ */
+static inline void CLOCK_SetLpuart0Clock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
+}
+
+/*!
+ * @brief Set LPUART1 clock source.
+ *
+ * @param src The value to set LPUART1 clock source.
+ */
+static inline void CLOCK_SetLpuart1Clock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) | SIM_SOPT2_LPUART1SRC(src));
+}
+
+/*!
+ * @brief Set TPM clock source.
+ *
+ * @param src The value to set TPM clock source.
+ */
+static inline void CLOCK_SetTpmClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
+}
+
+/*!
+ * @brief Set FLEXIO clock source.
+ *
+ * @param src The value to set FLEXIO clock source.
+ */
+static inline void CLOCK_SetFlexio0Clock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src));
+}
+
+/*! @brief Enable USB FS clock.
+ *
+ * @param src  USB FS clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB FS clock.
+ */
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Disable USB FS clock.
+ *
+ * Disable USB FS clock.
+ */
+static inline void CLOCK_DisableUsbfs0Clock(void)
+{
+    CLOCK_DisableClock(kCLOCK_Usbfs0);
+}
+
+/*!
+ * @brief Set CLKOUT source.
+ *
+ * @param src The value to set CLKOUT source.
+ */
+static inline void CLOCK_SetClkOutClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
+}
+
+/*!
+ * @brief Set RTC_CLKOUT source.
+ *
+ * @param src The value to set RTC_CLKOUT source.
+ */
+static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
+}
+
+/*!
+ * @brief System clock divider
+ *
+ * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
+ *
+ * @param outdiv1 Clock 1 output divider value.
+ *
+ * @param outdiv4 Clock 4 output divider value.
+ */
+static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
+{
+    SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
+}
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ * The MCG must be properly configured before using this function.
+ *
+ * @param clockName Clock names defined in clock_name_t
+ * @return Clock frequency value in Hertz
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*!
+ * @brief Get the core clock or system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*!
+ * @brief Get the platform clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPlatClkFreq(void);
+
+/*!
+ * @brief Get the bus clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetBusClkFreq(void);
+
+/*!
+ * @brief Get the flash clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlashClkFreq(void);
+
+/*!
+ * @brief Get the external reference 32K clock frequency (ERCLK32K).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetEr32kClkFreq(void);
+
+/*!
+ * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkFreq(void);
+
+/*!
+ * @brief Set the clock configure in SIM module.
+ *
+ * This function sets system layer clock settings in SIM module.
+ *
+ * @param config Pointer to the configure structure.
+ */
+void CLOCK_SetSimConfig(sim_clock_config_t const *config);
+
+/*!
+ * @brief Set the system clock dividers in SIM to safe value.
+ *
+ * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
+ * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
+ * changes then the system level clocks may be out of range. This function could
+ * be used before MCG mode change, to make sure system level clocks are in allowed
+ * range.
+ */
+static inline void CLOCK_SetSimSafeDivs(void)
+{
+    SIM->CLKDIV1 = 0x10030000U;
+}
+
+/*!
+ * @name MCG_Lite clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency.
+ *
+ * This function gets the MCG_Lite output clock frequency in Hz based on the current
+ * MCG_Lite register value.
+ *
+ * @return The frequency of MCGOUTCLK.
+ */
+uint32_t CLOCK_GetOutClkFreq(void);
+
+/*!
+ * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
+ *
+ * This function gets the MCG_Lite internal reference clock frequency in Hz based
+ * on the current MCG register value.
+ *
+ * @return The frequency of MCGIRCLK.
+ */
+uint32_t CLOCK_GetInternalRefClkFreq(void);
+
+/*!
+ * @brief Gets the current MCGPCLK frequency.
+ *
+ * This function gets the MCGPCLK frequency in Hz based on the current MCG_Lite
+ * register settings.
+ *
+ * @return The frequency of MCGPCLK.
+ */
+uint32_t CLOCK_GetPeriphClkFreq(void);
+
+/*! @}*/
+
+/*!
+ * @name MCG_Lite mode.
+ * @{
+ */
+
+/*!
+ * @brief Gets the current MCG_Lite mode.
+ *
+ * This function checks the MCG_Lite registers and determines the current MCG_Lite mode.
+ *
+ * @return The current MCG_Lite mode or error code.
+ */
+mcglite_mode_t CLOCK_GetMode(void);
+
+/*!
+ * @brief Sets the MCG_Lite configuration.
+ *
+ * This function configures the MCG_Lite, includes the output clock source, MCGIRCLK
+ * settings, HIRC settings, and so on. See @ref mcglite_config_t for details.
+ *
+ * @param  targetConfig Pointer to the target MCG_Lite mode configuration structure.
+ * @return Error code.
+ */
+status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig);
+
+/*! @}*/
+
+/*!
+ * @name OSC configuration
+ * @{
+ */
+
+/*!
+ * @brief Configures the OSC external reference clock (OSCERCLK).
+ *
+ * This function configures the OSC external reference clock (OSCERCLK).
+ * This is an example to enable the OSCERCLK in normal mode and stop mode, and set
+ * the output divider to 1.
+ *
+   @code
+   oscer_config_t config =
+   {
+       .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
+       .erclkDiv   = 1U,
+   };
+
+   OSC_SetExtRefClkConfig(OSC, &config);
+   @endcode
+ *
+ * @param base   OSC peripheral address.
+ * @param config Pointer to the configuration structure.
+ */
+static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
+{
+    uint8_t reg = base->CR;
+
+    reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
+    reg |= config->enableMode;
+
+    base->CR = reg;
+}
+
+/*!
+ * @brief Sets the capacitor load configuration for the oscillator.
+ *
+ * This function sets the specified capacitor configuration for the oscillator.
+ * This should be done in the early system level initialization function call
+ * based on the system configuration.
+ *
+ * @param base   OSC peripheral address.
+ * @param capLoad OR'ed value for the capacitor load option.See \ref _osc_cap_load.
+ *
+ * Example:
+   @code
+   OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
+   @endcode
+ */
+
+static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
+{
+    uint8_t reg = base->CR;
+
+    reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
+    reg |= capLoad;
+
+    base->CR = reg;
+}
+
+/*!
+ * @brief Initializes the OSC0.
+ *
+ * This function initializes the OSC0 according to the board configuration.
+ *
+ * @param  config Pointer to the OSC0 configuration structure.
+ */
+void CLOCK_InitOsc0(osc_config_t const *config);
+
+/*!
+ * @brief Deinitializes the OSC0.
+ *
+ * This function deinitializes the OSC0.
+ */
+void CLOCK_DeinitOsc0(void);
+
+/*! @}*/
+
+/*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Sets the XTAL0 frequency based on board settings.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+    g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
+ *
+ * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+    g_xtal32Freq = freq;
+}
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.c
new file mode 100644
index 0000000000..357f711c77
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cmp.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cmp"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for CMP module.
+ *
+ * @param base CMP peripheral base address
+ */
+static uint32_t CMP_GetInstance(CMP_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to CMP bases for each instance. */
+static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to CMP clocks for each instance. */
+static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static uint32_t CMP_GetInstance(CMP_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
+    {
+        if (s_cmpBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_cmpBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the CMP.
+ *
+ * This function initializes the CMP module. The operations included are as follows.
+ * - Enabling the clock for CMP module.
+ * - Configuring the comparator.
+ * - Enabling the CMP module.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void CMP_Init(CMP_Type *base, const cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure. */
+    CMP_Enable(base, false); /* Disable the CMP module during configuring. */
+    /* CMPx_CR1. */
+    tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK));
+    if (true == config->enableHighSpeed)
+    {
+        tmp8 |= CMP_CR1_PMODE_MASK;
+    }
+    if (true == config->enableInvertOutput)
+    {
+        tmp8 |= CMP_CR1_INV_MASK;
+    }
+    if (true == config->useUnfilteredOutput)
+    {
+        tmp8 |= CMP_CR1_COS_MASK;
+    }
+    if (true == config->enablePinOut)
+    {
+        tmp8 |= CMP_CR1_OPE_MASK;
+    }
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    if (true == config->enableTriggerMode)
+    {
+        tmp8 |= CMP_CR1_TRIGM_MASK;
+    }
+    else
+    {
+        tmp8 &= ~(uint8_t)CMP_CR1_TRIGM_MASK;
+    }
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+    base->CR1 = tmp8;
+
+    /* CMPx_CR0. */
+    tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK;
+    tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
+    base->CR0 = tmp8;
+
+    CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
+}
+
+/*!
+ * brief De-initializes the CMP module.
+ *
+ * This function de-initializes the CMP module. The operations included are as follows.
+ * - Disabling the CMP module.
+ * - Disabling the clock for CMP module.
+ *
+ * This function disables the clock for the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
+ *
+ * param base CMP peripheral base address.
+ */
+void CMP_Deinit(CMP_Type *base)
+{
+    // Disable the CMP module.
+    base->CR0 = 0U;
+    base->CR1 = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * code
+ *   config->enableCmp           = true;
+ *   config->hysteresisMode      = kCMP_HysteresisLevel0;
+ *   config->enableHighSpeed     = false;
+ *   config->enableInvertOutput  = false;
+ *   config->useUnfilteredOutput = false;
+ *   config->enablePinOut        = false;
+ *   config->enableTriggerMode   = false;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableCmp           = true; /* Enable the CMP module after initialization. */
+    config->hysteresisMode      = kCMP_HysteresisLevel0;
+    config->enableHighSpeed     = false;
+    config->enableInvertOutput  = false;
+    config->useUnfilteredOutput = false;
+    config->enablePinOut        = false;
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    config->enableTriggerMode = false;
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+}
+
+/*!
+ * brief  Sets the input channels for the comparator.
+ *
+ * This function sets the input channels for the comparator.
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
+ * from the analog mux to the positive and negative port, the comparator is disabled automatically.
+ *
+ * param  base            CMP peripheral base address.
+ * param  positiveChannel Positive side input channel number. Available range is 0-7.
+ * param  negativeChannel Negative side input channel number. Available range is 0-7.
+ */
+void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
+{
+    uint8_t tmp8 = base->MUXCR;
+
+    tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
+    tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
+    base->MUXCR = tmp8;
+}
+
+#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+/*!
+ * brief Enables/disables the DMA request for rising/falling events.
+ *
+ * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
+ * the CMP
+ * if the DMA is disabled.
+ *
+ * param base CMP peripheral base address.
+ * param enable Enables or disables the feature.
+ */
+void CMP_EnableDMA(CMP_Type *base, bool enable)
+{
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
+
+    if (enable)
+    {
+        tmp8 |= CMP_SCR_DMAEN_MASK;
+    }
+    else
+    {
+        tmp8 &= ~(uint8_t)CMP_SCR_DMAEN_MASK;
+    }
+    base->SCR = tmp8;
+}
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+
+/*!
+ * brief  Configures the filter.
+ *
+ * param  base   CMP peripheral base address.
+ * param  config Pointer to the configuration structure.
+ */
+void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
+    /* Choose the clock source for sampling. */
+    if (config->enableSample)
+    {
+        base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
+    }
+    else
+    {
+        base->CR1 &= (uint8_t)(~CMP_CR1_SE_MASK); /* Choose the internal divided bus clock. */
+    }
+#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
+    /* Set the filter count. */
+    tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK);
+    tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
+    base->CR0 = tmp8;
+    /* Set the filter period. It is used as the divider to bus clock. */
+    base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
+}
+
+/*!
+ * brief Configures the internal DAC.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure. "NULL" disables the feature.
+ */
+void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
+{
+    uint8_t tmp8 = 0U;
+
+    if (NULL == config)
+    {
+        /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
+        base->DACCR = 0U;
+        return;
+    }
+    /* CMPx_DACCR. */
+    tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
+    if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
+    {
+        tmp8 |= CMP_DACCR_VRSEL_MASK;
+    }
+    tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
+
+    base->DACCR = tmp8;
+}
+
+/*!
+ * brief Enables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
+
+    if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
+    {
+        tmp8 |= CMP_SCR_IER_MASK;
+    }
+    if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
+    {
+        tmp8 |= CMP_SCR_IEF_MASK;
+    }
+    base->SCR = tmp8;
+}
+
+/*!
+ * brief Disables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
+
+    if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
+    {
+        tmp8 &= ~(uint8_t)CMP_SCR_IER_MASK;
+    }
+    if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
+    {
+        tmp8 &= ~(uint8_t)CMP_SCR_IEF_MASK;
+    }
+    base->SCR = tmp8;
+}
+
+/*!
+ * brief  Gets the status flags.
+ *
+ * param  base     CMP peripheral base address.
+ *
+ * return          Mask value for the asserted flags. See "_cmp_status_flags".
+ */
+uint32_t CMP_GetStatusFlags(CMP_Type *base)
+{
+    uint32_t ret32 = 0U;
+
+    if (0U != (CMP_SCR_CFR_MASK & base->SCR))
+    {
+        ret32 |= (uint32_t)kCMP_OutputRisingEventFlag;
+    }
+    if (0U != (CMP_SCR_CFF_MASK & base->SCR))
+    {
+        ret32 |= (uint32_t)kCMP_OutputFallingEventFlag;
+    }
+    if (0U != (CMP_SCR_COUT_MASK & base->SCR))
+    {
+        ret32 |= (uint32_t)kCMP_OutputAssertEventFlag;
+    }
+    return ret32;
+}
+
+/*!
+ * brief Clears the status flags.
+ *
+ * param base     CMP peripheral base address.
+ * param mask     Mask value for the flags. See "_cmp_status_flags".
+ */
+void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
+
+    if (0U != ((uint32_t)kCMP_OutputRisingEventFlag & mask))
+    {
+        tmp8 |= CMP_SCR_CFR_MASK;
+    }
+    if (0U != ((uint32_t)kCMP_OutputFallingEventFlag & mask))
+    {
+        tmp8 |= CMP_SCR_CFF_MASK;
+    }
+    base->SCR = tmp8;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.h
new file mode 100644
index 0000000000..ad6d4861b0
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cmp.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_CMP_H_
+#define FSL_CMP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cmp
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief CMP driver version 2.0.3. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*! @} */
+
+/*!
+ * @brief Interrupt enable/disable mask.
+ */
+enum _cmp_interrupt_enable
+{
+    kCMP_OutputRisingInterruptEnable  = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
+    kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
+};
+
+/*!
+ * @brief Status flags' mask.
+ */
+enum _cmp_status_flags
+{
+    kCMP_OutputRisingEventFlag  = CMP_SCR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
+    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK,  /*!< Falling-edge on the comparison output has occurred. */
+    kCMP_OutputAssertEventFlag  = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
+};
+
+/*!
+ * @brief CMP Hysteresis mode.
+ */
+typedef enum _cmp_hysteresis_mode
+{
+    kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */
+    kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */
+    kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */
+    kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */
+} cmp_hysteresis_mode_t;
+
+/*!
+ * @brief CMP Voltage Reference source.
+ */
+typedef enum _cmp_reference_voltage_source
+{
+    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */
+} cmp_reference_voltage_source_t;
+
+/*!
+ * @brief Configures the comparator.
+ */
+typedef struct _cmp_config
+{
+    bool enableCmp;                       /*!< Enable the CMP module. */
+    cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
+    bool enableHighSpeed;                 /*!< Enable High-speed (HS) comparison mode. */
+    bool enableInvertOutput;              /*!< Enable the inverted comparator output. */
+    bool useUnfilteredOutput;             /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */
+    bool enablePinOut;                    /*!< The comparator output is available on the associated pin. */
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    bool enableTriggerMode; /*!< Enable the trigger mode. */
+#endif                      /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+} cmp_config_t;
+
+/*!
+ * @brief Configures the filter.
+ */
+typedef struct _cmp_filter_config
+{
+#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
+    bool enableSample;    /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */
+#endif                    /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
+    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/
+    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */
+} cmp_filter_config_t;
+
+/*!
+ * @brief Configures the internal DAC.
+ */
+typedef struct _cmp_dac_config
+{
+    cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
+    uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
+} cmp_dac_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the CMP.
+ *
+ * This function initializes the CMP module. The operations included are as follows.
+ * - Enabling the clock for CMP module.
+ * - Configuring the comparator.
+ * - Enabling the CMP module.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
+ *
+ * @param base   CMP peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(CMP_Type *base, const cmp_config_t *config);
+
+/*!
+ * @brief De-initializes the CMP module.
+ *
+ * This function de-initializes the CMP module. The operations included are as follows.
+ * - Disabling the CMP module.
+ * - Disabling the clock for CMP module.
+ *
+ * This function disables the clock for the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
+ *
+ * @param base CMP peripheral base address.
+ */
+void CMP_Deinit(CMP_Type *base);
+
+/*!
+ * @brief Enables/disables the CMP module.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enables or disables the module.
+ */
+static inline void CMP_Enable(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR1 |= CMP_CR1_EN_MASK;
+    }
+    else
+    {
+        base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableCmp           = true;
+ *   config->hysteresisMode      = kCMP_HysteresisLevel0;
+ *   config->enableHighSpeed     = false;
+ *   config->enableInvertOutput  = false;
+ *   config->useUnfilteredOutput = false;
+ *   config->enablePinOut        = false;
+ *   config->enableTriggerMode   = false;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config);
+
+/*!
+ * @brief  Sets the input channels for the comparator.
+ *
+ * This function sets the input channels for the comparator.
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
+ * from the analog mux to the positive and negative port, the comparator is disabled automatically.
+ *
+ * @param  base            CMP peripheral base address.
+ * @param  positiveChannel Positive side input channel number. Available range is 0-7.
+ * @param  negativeChannel Negative side input channel number. Available range is 0-7.
+ */
+void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel);
+
+/*! @} */
+
+/*!
+ * @name Advanced Features
+ * @{
+ */
+
+#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+/*!
+ * @brief Enables/disables the DMA request for rising/falling events.
+ *
+ * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
+ * the CMP
+ * if the DMA is disabled.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+void CMP_EnableDMA(CMP_Type *base, bool enable);
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+
+#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE
+/*!
+ * @brief Enables/disables the window mode.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR1 |= CMP_CR1_WE_MASK;
+    }
+    else
+    {
+        base->CR1 &= (uint8_t)(~CMP_CR1_WE_MASK);
+    }
+}
+#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
+
+#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE
+/*!
+ * @brief Enables/disables the pass through mode.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->MUXCR |= CMP_MUXCR_PSTM_MASK;
+    }
+    else
+    {
+        base->MUXCR &= (uint8_t)(~CMP_MUXCR_PSTM_MASK);
+    }
+}
+#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */
+
+/*!
+ * @brief  Configures the filter.
+ *
+ * @param  base   CMP peripheral base address.
+ * @param  config Pointer to the configuration structure.
+ */
+void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
+
+/*!
+ * @brief Configures the internal DAC.
+ *
+ * @param base   CMP peripheral base address.
+ * @param config Pointer to the configuration structure. "NULL" disables the feature.
+ */
+void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
+
+/*!
+ * @brief Enables the interrupts.
+ *
+ * @param base    CMP peripheral base address.
+ * @param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupts.
+ *
+ * @param base    CMP peripheral base address.
+ * @param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Results
+ * @{
+ */
+
+/*!
+ * @brief  Gets the status flags.
+ *
+ * @param  base     CMP peripheral base address.
+ *
+ * @return          Mask value for the asserted flags. See "_cmp_status_flags".
+ */
+uint32_t CMP_GetStatusFlags(CMP_Type *base);
+
+/*!
+ * @brief Clears the status flags.
+ *
+ * @param base     CMP peripheral base address.
+ * @param mask     Mask value for the flags. See "_cmp_status_flags".
+ */
+void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
+
+/*! @} */
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* FSL_CMP_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.c
new file mode 100644
index 0000000000..d3af9fdfc6
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.h
new file mode 100644
index 0000000000..e6d5cce719
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common.h
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_COMMON_H_
+#define FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
+
+/*! @brief Construct the version number for drivers.
+ *
+ * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
+ * and 16-bit platforms(such as DSC).
+ *
+ * @verbatim
+
+   | Unused    || Major Version || Minor Version ||  Bug Fix    |
+   31        25  24           17  16            9  8            0
+
+   @endverbatim
+ */
+#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
+/*! @} */
+
+/*! @name Debug console type definition. */
+/*! @{ */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI      3U  /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC     4U  /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U  /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART      6U  /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART     7U  /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+/*! @} */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic               = 0,   /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH                 = 1,   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI                 = 4,   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI            = 5,   /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI                  = 6,   /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART           = 7,   /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C            = 8,   /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C                 = 9,   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART                  = 10,  /*!< Group number for UART status codes. */
+    kStatusGroup_I2C                   = 11,  /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI                 = 12,  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART                = 13,  /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI                   = 14,  /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC                  = 15,  /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42                = 16,  /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC                  = 17,  /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC                 = 18,  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI                   = 19,  /*!< Group number for SAI status code */
+    kStatusGroup_MCG                   = 20,  /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG                   = 21,  /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI                 = 22,  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S            = 23,  /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD         = 24,  /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP              = 25,  /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C          = 26,  /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S                   = 27,  /*!< Group number for I2S status codes */
+    kStatusGroup_IUART                 = 28,  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI                   = 29,  /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI              = 30,  /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC                = 35,  /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER                 = 39,  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET                  = 40,  /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY                   = 41,  /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX                = 42,  /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD             = 43,  /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM                  = 44,  /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI                  = 45,  /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA                   = 50,  /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA                  = 51,  /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR                = 52,  /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN               = 53,  /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC                   = 54,  /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA         = 55,  /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI               = 56,  /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART             = 57,  /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC                  = 58,  /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF                  = 59,  /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI                 = 60,  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP                   = 61,  /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN                  = 62,  /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM                  = 63,  /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI                 = 64,  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC                 = 65,  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C               = 66,  /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP                   = 67,  /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN                 = 68,  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI                  = 69,  /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI               = 70,  /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC                  = 71,  /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM                   = 72,  /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA                  = 73,  /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS                   = 74,  /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF                 = 75,  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI           = 76,  /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT             = 77,  /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP           = 78,  /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C                   = 79,  /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1             = 97,  /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER              = 98,  /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole          = 99,  /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC                  = 100, /*!< Group number for SEMC status codes. */
+    kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP                   = 102, /*!< Group number for IAP status codes */
+    kStatusGroup_SFA                   = 103, /*!< Group number for SFA status codes*/
+    kStatusGroup_SPC                   = 104, /*!< Group number for SPC status codes. */
+    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
+    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
+    kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+    kStatusGroup_XSPI                  = 108, /*!< Group number for XSPI status codes */
+    kStatusGroup_PNGDEC                = 109, /*!< Group number for PNGDEC status codes */
+    kStatusGroup_JPEGDEC               = 110, /*!< Group number for JPEGDEC status codes */
+
+    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER      = 123, /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI        = 124, /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C        = 125, /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH      = 126, /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */
+    kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
+    kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON         = 138, /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM  = 139, /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL          = 140, /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER    = 141, /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST           = 142, /*!< Group number for List status codes. */
+    kStatusGroup_OSA            = 143, /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK    = 144, /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG            = 145, /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP      = 146, /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC          = 148, /*!< Group number for codec status codes. */
+    kStatusGroup_ASRC           = 149, /*!< Group number for codec status ASRC. */
+    kStatusGroup_OTFAD          = 150, /*!< Group number for codec status codes. */
+    kStatusGroup_SDIOSLV        = 151, /*!< Group number for SDIOSLV status codes. */
+    kStatusGroup_MECC           = 152, /*!< Group number for MECC status codes. */
+    kStatusGroup_ENET_QOS       = 153, /*!< Group number for ENET_QOS status codes. */
+    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
+    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
+    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
+    kStatusGroup_ELEMU          = 157, /*!< Group number for ELEMU status codes. */
+    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
+    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
+    kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
+    kStatusGroup_ELS_PKC        = 161, /*!< Group number for ELS PKC status codes. */
+    kStatusGroup_CSS_PKC        = 162, /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF         = 163, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 164, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 165, /*!< Group number for BMA status codes. */
+    kStatusGroup_NETC           = 166, /*!< Group number for NETC status codes. */
+    kStatusGroup_ELE            = 167, /*!< Group number for ELE status codes. */
+    kStatusGroup_GLIKEY         = 168, /*!< Group number for GLIKEY status codes. */
+};
+
+/*! \public
+ * @brief Generic status return codes.
+ */
+enum
+{
+    kStatus_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+    kStatus_Fail            = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+    kStatus_ReadOnly        = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+    kStatus_OutOfRange      = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+    kStatus_Timeout         = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+    kStatus_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_Generic, 6),            /*!< Generic status for no transfer in progress. */
+    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
+    kStatus_NoData =
+        MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+#ifdef __ZEPHYR__
+#include <zephyr/sys/util.h>
+#else
+/*!
+ * @name Min/max macros
+ * @{
+ */
+#if !defined(MIN)
+/*! Computes the minimum of \a a and \a b. */
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+/*! Computes the maximum of \a a and \a b. */
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/*! @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+#endif /* __ZEPHYR__ */
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/*! @{ */
+#if !defined(UINT16_MAX)
+/*! Max value of uint16_t type. */
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+/*! Max value of uint32_t type. */
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/*! @} */
+
+/*! Macro to get upper 32 bits of a 64-bit value */
+#if !defined(UINT64_H)
+#define UINT64_H(X)        ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
+#endif
+
+/*! Macro to get lower 32 bits of a 64-bit value */
+#if !defined(UINT64_L)
+#define UINT64_L(X)        ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
+#endif
+
+/*!
+ * @def SUPPRESS_FALL_THROUGH_WARNING()
+ *
+ * For switch case code block, if case section ends without "break;" statement, there wil be
+ * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ * case section which misses "break;"statement.
+ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
+
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
+#endif
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XTENSA__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
+#endif /* FSL_COMMON_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.c
new file mode 100644
index 0000000000..e9f32aadf4
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
+
+#define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[(int32_t)irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1UL << intNumber;
+    (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(DWT)
+/* Use WDT. */
+void MSDK_EnableCpuCycleCounter(void)
+{
+    /* Make sure the DWT trace fucntion is enabled. */
+    if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+    {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* CYCCNT not supported on this device. */
+    assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+    /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+    if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+    {
+        DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+}
+
+uint32_t MSDK_GetCpuCycleCount(void)
+{
+    return DWT->CYCCNT;
+}
+#endif /* defined(DWT) */
+
+#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+    SUBS R0, R0, #1
+    CMP  R0, #0
+    BNE  loop
+    BX   LR
+}
+#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    X0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop%=:                        \n"
+        "    SUB    X0, X0, #1          \n"
+        "    CMP    X0, #0              \n"
+
+        "    BNE    loop%=              \n"
+        :
+        :
+        : "r0");
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop%=:                        \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+        "    SUB    R0, R0, #1          \n"
+#else
+        "    SUBS   R0, R0, #1          \n"
+#endif
+        "    CMP    R0, #0              \n"
+
+        "    BNE    loop%=              \n"
+        :
+        :
+        : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ *  effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ *  coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ *  up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+    uint64_t count;
+
+    if (delayTime_us > 0U)
+    {
+        count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+        assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+        MSDK_EnableCpuCycleCounter();
+        /* Calculate the count ticks. */
+        count += MSDK_GetCpuCycleCount();
+
+        if (count > UINT32_MAX)
+        {
+            count -= UINT32_MAX;
+            /* Wait for cyccnt overflow. */
+            while (count < MSDK_GetCpuCycleCount())
+            {
+            }
+        }
+
+        /* Wait for cyccnt reach count value. */
+        while (count > MSDK_GetCpuCycleCount())
+        {
+        }
+#else
+#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
+        /*
+         * Cortex-A53/A55 execution throughput:
+         *  - SUB/CMP: 2 instructions per cycle
+         *  - BNE:     1 instruction per cycle
+         * So, each loop takes 2 CPU cycles.
+         */
+        count = count / 2U;
+#elif (__CORTEX_M == 7)
+        /* Divide value may be different in various environment to ensure delay is precise.
+         * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+         * two instructions in one period, through test here set divide 1.5. Other M cores use
+         * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+         * not matter because other instructions outside while loop is enough to fill the time.
+         */
+        count = count / 3U * 2U;
+#else
+        count = count / 4U;
+#endif
+        DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.h
new file mode 100644
index 0000000000..3d35d76f81
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_common_arm.h
@@ -0,0 +1,898 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_COMMON_ARM_H_
+#define FSL_COMMON_ARM_H_
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*! @name Atomic modification
+ *
+ * These macros are used for atomic access, such as read-modify-write
+ * to the peripheral registers.
+ *
+ * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * means the address of the peripheral register or variable you want to modify
+ * atomically, the parameter @c clearBits is the bits to clear, the parameter
+ * @c setBits it the bits to set.
+ * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
+ *
+ * @code
+   volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
+
+   SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
+   @endcode
+ *
+ * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
+ * register bit1:bit0 = 0b10.
+ *
+ * @note For the platforms don't support exclusive load and store, these macros
+ * disable the global interrupt to pretect the modification.
+ *
+ * @note These macros only guarantee the local processor atomic operations. For
+ * the multi-processor devices, use hardware semaphore such as SEMA42 to
+ * guarantee exclusive access if necessary.
+ *
+ * @{
+ */
+
+/*!
+ * @def SDK_ATOMIC_LOCAL_ADD(addr, val)
+ * Add value \a val from the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SUB(addr, val)
+ * Subtract value \a val to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SET(addr, bits)
+ * Set the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
+ * Clear the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
+ * Toggle the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
+ * For the variable at address \a address, clear the bits specifiled by \a clearBits
+ * and set the bits specifiled by \a setBits.
+ */
+
+/* clang-format off */
+#if ((defined(__ARM_ARCH_7M__     ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined(__ARM_ARCH_7EM__    ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+/* clang-format on */
+
+/* If the LDREX and STREX are supported, use them. */
+#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXB(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXB((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXH(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXH((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXW(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXW((val), (addr)))
+
+static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                 \
+         _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+                                     _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                            \
+         _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                       \
+              _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                             \
+         _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                        \
+              _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)                                                                           \
+    ((1UL == sizeof(*(addr))) ?                                                                                                            \
+         _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) :         \
+         ((2UL == sizeof(*(addr))) ?                                                                                                       \
+              _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
+              _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
+#else
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) += (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) -= (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) |= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) &= ~(bits);                  \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) ^= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+    do                                                           \
+    {                                                            \
+        uint32_t s_atomicOldInt;                                 \
+        s_atomicOldInt = DisableGlobalIRQ();                     \
+        *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
+        EnableGlobalIRQ(s_atomicOldInt);                         \
+    } while (false)
+
+#endif
+/*! @} */
+
+/*! @name Timer utilities */
+/*! @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
+/*! @} */
+
+/*! @name ISR exit barrier
+ * @{
+ *
+ * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ * exception return operation might vector to incorrect interrupt.
+ * For Cortex-M7, if core speed much faster than peripheral register write speed,
+ * the peripheral interrupt flags may be still set after exiting ISR, this results to
+ * the same error similar with errata 83869.
+ */
+#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
+#define SDK_ISR_EXIT_BARRIER __DSB()
+#else
+#define SDK_ISR_EXIT_BARRIER
+#endif
+
+/*! @} */
+
+/*! @name Alignment variable definition macros */
+/*! @{ */
+#if (defined(__ICCARM__))
+/*
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported
+#endif
+
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/*! @} */
+
+/*!
+ * @name Non-cacheable region definition macros
+ *
+ * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable
+ * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+ * these zero-inited variables will be initialized to zero in system startup.
+ *
+ * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ *
+ * @{
+ */
+
+/*!
+ * @def AT_NONCACHEABLE_SECTION(var)
+ * Define a variable \a var, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)
+ * Define a variable \a var, and place it in non-cacheable section, the start address
+ * of the variable is aligned to \a alignbytes.
+ *
+ * @def AT_NONCACHEABLE_SECTION_INIT(var)
+ * Define a variable \a var with initial value, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)
+ * Define a variable \a var with initial value, and place it in non-cacheable section,
+ * the start address of the variable is aligned to \a alignbytes.
+ */
+
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
+     defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+
+#if (defined(__ICCARM__))
+#define AT_NONCACHEABLE_SECTION(var)                   var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var)              var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if (defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif
+
+#else
+
+#define AT_NONCACHEABLE_SECTION(var)                        var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)      SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var)                   var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
+
+#endif
+
+/*! @} */
+
+/*!
+ * @name Time sensitive region
+ * @{
+ */
+
+/*!
+ * @def AT_QUICKACCESS_SECTION_CODE(func)
+ * Place function in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA(var)
+ * Place data in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)
+ * Place data in a section which can be accessed quickly by core, and the variable
+ * address is set to align with \a alignbytes.
+ */
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/*! @} */
+
+/*!
+ * @name Ram Function
+ * @{
+ *
+ * @def RAMFUNCTION_SECTION_CODE(func)
+ * Place function in ram.
+ */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/*! @} */
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        void DefaultISR(void);
+#endif
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+        NVIC_DisableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Enable the IRQ, and also set the interrupt priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to Enable.
+ * @param priNum Priority number set to interrupt controller register.
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Set the IRQ priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to set.
+ * @param priNum Priority number set to interrupt controller register.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Clear the pending IRQ flag.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The flag which IRQ to clear.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_ClearPendingIRQ(interrupt);
+#else
+        NVIC_ClearPendingIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+    uint32_t mask;
+
+#if defined(CPSR_I_Msk)
+    mask = __get_CPSR() & CPSR_I_Msk;
+#elif defined(DAIF_I_BIT)
+    mask = __get_DAIF() & DAIF_I_BIT;
+#else
+    mask = __get_PRIMASK();
+#endif
+    __disable_irq();
+
+    return mask;
+}
+
+/*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#elif defined(DAIF_I_BIT)
+    if (0UL == primask)
+    {
+        __enable_irq();
+    }
+#else
+    __set_PRIMASK(primask);
+#endif
+}
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(DWT)
+/*!
+ * @brief Enable the counter to get CPU cycles.
+ */
+void MSDK_EnableCpuCycleCounter(void);
+
+/*!
+ * @brief Get the current CPU cycle count.
+ *
+ * @return Current CPU cycle count.
+ */
+uint32_t MSDK_GetCpuCycleCount(void);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @} */
+
+#endif /* FSL_COMMON_ARM_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.c
new file mode 100644
index 0000000000..a4e8350c10
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cop.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cop"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Initializes the COP configuration structure.
+ *
+ * This function initializes the COP configuration structure to default values. The default
+ * values are:
+ * code
+ *   copConfig->enableWindowMode = false;
+ *   copConfig->timeoutMode = kCOP_LongTimeoutMode;
+ *   copConfig->enableStop = false;
+ *   copConfig->enableDebug = false;
+ *   copConfig->clockSource = kCOP_LpoClock;
+ *   copConfig->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles;
+ * endcode
+ *
+ * param config Pointer to the COP configuration structure.
+ * see cop_config_t
+ */
+void COP_GetDefaultConfig(cop_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableWindowMode = false;
+#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE
+    config->timeoutMode = kCOP_LongTimeoutMode;
+    config->enableStop  = false;
+    config->enableDebug = false;
+#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */
+    config->clockSource   = kCOP_LpoClock;
+    config->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles;
+}
+
+/*!
+ * brief Initializes the COP module.
+ *
+ * This function configures the COP. After it is called, the COP
+ * starts running according to the configuration.
+ * Because all COP control registers are write-once only, the COP_Init function
+ * and the COP_Disable function can be called only once. A second call has no effect.
+ *
+ * Example:
+ * code
+ *  cop_config_t config;
+ *  COP_GetDefaultConfig(&config);
+ *  config.timeoutCycles = kCOP_2Power8CyclesOr2Power16Cycles;
+ *  COP_Init(sim_base,&config);
+ * endcode
+ *
+ * param base   SIM peripheral base address.
+ * param config The configuration of COP.
+ */
+void COP_Init(SIM_Type *base, const cop_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t value = 0U;
+
+#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE
+    value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->timeoutMode) |
+            SIM_COPC_COPT(config->timeoutCycles) | SIM_COPC_COPSTPEN(config->enableStop) |
+            SIM_COPC_COPDBGEN(config->enableDebug) | SIM_COPC_COPCLKSEL(config->clockSource);
+#else
+    value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->clockSource) |
+            SIM_COPC_COPT(config->timeoutCycles);
+#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */
+    base->COPC = value;
+}
+
+/*!
+ * brief Refreshes the COP timer
+ *
+ * This function feeds the COP.
+ *
+ * param base  SIM peripheral base address.
+ */
+void COP_Refresh(SIM_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->SRVCOP = COP_FIRST_BYTE_OF_REFRESH;
+    base->SRVCOP = COP_SECOND_BYTE_OF_REFRESH;
+    EnableGlobalIRQ(primaskValue);
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.h
new file mode 100644
index 0000000000..0005281ed9
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_cop.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_COP_H_
+#define FSL_COP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cop
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief COP driver version 2.0.1. */
+#define FSL_COP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @} */
+
+/*! @name COP refresh sequence. */
+/*! @{ */
+#define COP_FIRST_BYTE_OF_REFRESH  (0x55U) /*!< First byte of refresh sequence */
+#define COP_SECOND_BYTE_OF_REFRESH (0xAAU) /*!< Second byte of refresh sequence */
+/*! @} */
+
+/*! @brief COP clock source selection. */
+typedef enum _cop_clock_source
+{
+    kCOP_LpoClock = 0U, /*!< COP clock sourced from LPO */
+#if defined(FSL_FEATURE_COP_HAS_MORE_CLKSRC) && FSL_FEATURE_COP_HAS_MORE_CLKSRC
+    kCOP_McgIrClock = 1U, /*!< COP clock sourced from MCGIRCLK */
+    kCOP_OscErClock = 2U, /*!< COP clock sourced from OSCERCLK */
+#endif                    /* FSL_FEATURE_COP_HAS_MORE_CLKSRC */
+    kCOP_BusClock = 3U,   /*!< COP clock sourced from Bus clock */
+} cop_clock_source_t;
+
+/*! @brief Define the COP timeout cycles. */
+typedef enum _cop_timeout_cycles
+{
+    kCOP_2Power5CyclesOr2Power13Cycles  = 1U, /*!< 2^5 or 2^13 clock cycles */
+    kCOP_2Power8CyclesOr2Power16Cycles  = 2U, /*!< 2^8 or 2^16 clock cycles */
+    kCOP_2Power10CyclesOr2Power18Cycles = 3U, /*!< 2^10 or 2^18 clock cycles */
+} cop_timeout_cycles_t;
+
+#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE
+/*! @brief Define the COP timeout mode. */
+typedef enum _cop_timeout_mode
+{
+    kCOP_ShortTimeoutMode = 0U, /*!< COP selects long timeout */
+    kCOP_LongTimeoutMode  = 1U, /*!< COP selects short timeout */
+} cop_timeout_mode_t;
+#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */
+
+/*! @brief Describes COP configuration structure. */
+typedef struct _cop_config
+{
+    bool enableWindowMode; /*!< COP run mode: window mode or normal mode */
+#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE
+    cop_timeout_mode_t timeoutMode;     /*!< COP timeout mode: long timeout or short timeout */
+    bool enableStop;                    /*!< Enable or disable COP in STOP mode */
+    bool enableDebug;                   /*!< Enable or disable COP in DEBUG mode */
+#endif                                  /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */
+    cop_clock_source_t clockSource;     /*!< Set COP clock source */
+    cop_timeout_cycles_t timeoutCycles; /*!< Set COP timeout value */
+} cop_config_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name COP Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes the COP configuration structure.
+ *
+ * This function initializes the COP configuration structure to default values. The default
+ * values are:
+ * @code
+ *   copConfig->enableWindowMode = false;
+ *   copConfig->timeoutMode = kCOP_LongTimeoutMode;
+ *   copConfig->enableStop = false;
+ *   copConfig->enableDebug = false;
+ *   copConfig->clockSource = kCOP_LpoClock;
+ *   copConfig->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles;
+ * @endcode
+ *
+ * @param config Pointer to the COP configuration structure.
+ * @see cop_config_t
+ */
+void COP_GetDefaultConfig(cop_config_t *config);
+
+/*!
+ * @brief Initializes the COP module.
+ *
+ * This function configures the COP. After it is called, the COP
+ * starts running according to the configuration.
+ * Because all COP control registers are write-once only, the COP_Init function
+ * and the COP_Disable function can be called only once. A second call has no effect.
+ *
+ * Example:
+ * @code
+ *  cop_config_t config;
+ *  COP_GetDefaultConfig(&config);
+ *  config.timeoutCycles = kCOP_2Power8CyclesOr2Power16Cycles;
+ *  COP_Init(sim_base,&config);
+ * @endcode
+ *
+ * @param base   SIM peripheral base address.
+ * @param config The configuration of COP.
+ */
+void COP_Init(SIM_Type *base, const cop_config_t *config);
+
+/*!
+ * @brief De-initializes the COP module.
+ * This dedicated function is not provided. Instead, the COP_Disable function can be used to disable the COP.
+ */
+
+/*!
+ * @brief Disables the COP module.
+ *
+ * This function disables the COP Watchdog.
+ * Note: The COP configuration register is a write-once after reset.
+ * To disable the COP Watchdog, call this function first.
+ *
+ * @param base  SIM peripheral base address.
+ */
+static inline void COP_Disable(SIM_Type *base)
+{
+    base->COPC &= ~SIM_COPC_COPT_MASK;
+}
+
+/*!
+ * @brief Refreshes the COP timer
+ *
+ * This function feeds the COP.
+ *
+ * @param base  SIM peripheral base address.
+ */
+void COP_Refresh(SIM_Type *base);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* FSL_COP_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.c
new file mode 100644
index 0000000000..85b5412b48
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dac.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dac"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for DAC module.
+ *
+ * @param base DAC peripheral base address
+ */
+static uint32_t DAC_GetInstance(DAC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to DAC bases for each instance. */
+static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to DAC clocks for each instance. */
+static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static uint32_t DAC_GetInstance(DAC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
+    {
+        if (s_dacBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dacBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the DAC module.
+ *
+ * This function initializes the DAC module including the following operations.
+ *  - Enabling the clock for DAC module.
+ *  - Configuring the DAC converter with a user configuration.
+ *  - Enabling the DAC module.
+ *
+ * param base DAC peripheral base address.
+ * param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_Init(DAC_Type *base, const dac_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure. */
+    /* DACx_C0. */
+    tmp8 = base->C0 & (uint8_t)(~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK));
+    if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource)
+    {
+        tmp8 |= DAC_C0_DACRFS_MASK;
+    }
+    if (config->enableLowPowerMode)
+    {
+        tmp8 |= DAC_C0_LPEN_MASK;
+    }
+    base->C0 = tmp8;
+
+    /* DAC_Enable(base, true); */
+    /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
+}
+
+/*!
+ * brief De-initializes the DAC module.
+ *
+ * This function de-initializes the DAC module including the following operations.
+ *  - Disabling the DAC module.
+ *  - Disabling the clock for the DAC module.
+ *
+ * param base DAC peripheral base address.
+ */
+void DAC_Deinit(DAC_Type *base)
+{
+    DAC_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Initializes the DAC user configuration structure.
+ *
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
+ * code
+ *   config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
+ *   config->enableLowPowerMode = false;
+ * endcode
+ * param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_GetDefaultConfig(dac_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
+    config->enableLowPowerMode     = false;
+}
+
+/*!
+ * brief Configures the CMP buffer.
+ *
+ * param base   DAC peripheral base address.
+ * param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+    /* DACx_C0. */
+    tmp8 = base->C0 & (uint8_t)(~DAC_C0_DACTRGSEL_MASK);
+    if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode)
+    {
+        tmp8 |= DAC_C0_DACTRGSEL_MASK;
+    }
+    base->C0 = tmp8;
+
+    /* DACx_C1. */
+    tmp8 = base->C1 & (uint8_t)(~(
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+                          DAC_C1_DACBFWM_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+                          DAC_C1_DACBFMD_MASK));
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    tmp8 |= DAC_C1_DACBFWM(config->watermark);
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    tmp8 |= DAC_C1_DACBFMD(config->workMode);
+    base->C1 = tmp8;
+
+    /* DACx_C2. */
+    tmp8 = base->C2 & (uint8_t)(~DAC_C2_DACBFUP_MASK);
+    tmp8 |= DAC_C2_DACBFUP(config->upperLimit);
+    base->C2 = tmp8;
+}
+
+/*!
+ * brief Initializes the DAC buffer configuration structure.
+ *
+ * This function initializes the DAC buffer configuration structure to default values. The default values are as
+ * follows.
+ * code
+ *   config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
+ *   config->watermark   = kDAC_BufferWatermark1Word;
+ *   config->workMode    = kDAC_BufferWorkAsNormalMode;
+ *   config->upperLimit  = DAC_DATL_COUNT - 1U;
+ * endcode
+ * param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    config->watermark = kDAC_BufferWatermark1Word;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    config->workMode   = kDAC_BufferWorkAsNormalMode;
+    config->upperLimit = DAC_DATL_COUNT - 1U;
+}
+
+/*!
+ * brief Sets the value for  items in the buffer.
+ *
+ * param base  DAC peripheral base address.
+ * param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC
+ * buffer.
+ * param value Setting the value for items in the buffer. 12-bits are available.
+ */
+void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value)
+{
+    assert(index < DAC_DATL_COUNT);
+
+    base->DAT[index].DATL = (uint8_t)(0xFFU & value);         /* Low 8-bit. */
+    base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */
+}
+
+/*!
+ * brief Sets the current read pointer of the DAC buffer.
+ *
+ * This function sets the current read pointer of the DAC buffer.
+ * The current output value depends on the item indexed by the read pointer. It is updated either by a
+ * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
+ *
+ * param base  DAC peripheral base address.
+ * param index Setting an index value for the pointer.
+ */
+void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index)
+{
+    assert(index < DAC_DATL_COUNT);
+
+    uint8_t tmp8 = base->C2 & (uint8_t)(~DAC_C2_DACBFRP_MASK);
+
+    tmp8 |= DAC_C2_DACBFRP(index);
+    base->C2 = tmp8;
+}
+
+/*!
+ * brief Enables interrupts for the DAC buffer.
+ *
+ * param base DAC peripheral base address.
+ * param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
+ */
+void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_C0_DACBWIEN_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
+    base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */
+}
+
+/*!
+ * brief Disables interrupts for the DAC buffer.
+ *
+ * param base DAC peripheral base address.
+ * param mask Mask value for interrupts. See  "_dac_buffer_interrupt_enable".
+ */
+void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_C0_DACBWIEN_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
+    base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */
+}
+
+/*!
+ * brief Gets the flags of events for the DAC buffer.
+ *
+ * param  base DAC peripheral base address.
+ *
+ * return      Mask value for the asserted flags. See  "_dac_buffer_status_flags".
+ */
+uint8_t DAC_GetBufferStatusFlags(DAC_Type *base)
+{
+    return base->SR & (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+                          DAC_SR_DACBFWMF_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+                          DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK);
+}
+
+/*!
+ * brief Clears the flags of events for the DAC buffer.
+ *
+ * param base DAC peripheral base address.
+ * param mask Mask value for flags. See "_dac_buffer_status_flags_t".
+ */
+void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_SR_DACBFWMF_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK);
+    base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.h
new file mode 100644
index 0000000000..18650deee6
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dac.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_DAC_H_
+#define FSL_DAC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dac
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief DAC driver version 2.0.2. */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @} */
+
+/*!
+ * @brief DAC buffer flags.
+ */
+enum _dac_buffer_status_flags
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+    kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK,                  /*!< DAC Buffer Watermark Flag. */
+#endif                                                                /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+    kDAC_BufferReadPointerTopPositionFlag    = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */
+    kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position
+                                                                           Flag. */
+};
+
+/*!
+ * @brief DAC buffer interrupts.
+ */
+enum _dac_buffer_interrupt_enable
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+    kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK,         /*!< DAC Buffer Watermark Interrupt Enable. */
+#endif                                                                  /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+    kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK,    /*!< DAC Buffer Read Pointer Top Flag Interrupt
+                                                                             Enable. */
+    kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag
+                                                                             Interrupt Enable */
+};
+
+/*!
+ * @brief DAC reference voltage source.
+ */
+typedef enum _dac_reference_voltage_source
+{
+    kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */
+    kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */
+} dac_reference_voltage_source_t;
+
+/*!
+ * @brief DAC buffer trigger mode.
+ */
+typedef enum _dac_buffer_trigger_mode
+{
+    kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */
+    kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */
+} dac_buffer_trigger_mode_t;
+
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+/*!
+ * @brief DAC buffer watermark.
+ */
+typedef enum _dac_buffer_watermark
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD
+    kDAC_BufferWatermark1Word = 0U, /*!< 1 word  away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS
+    kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS
+    kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS
+    kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */
+} dac_buffer_watermark_t;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+
+/*!
+ * @brief DAC buffer work mode.
+ */
+typedef enum _dac_buffer_work_mode
+{
+    kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */
+#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE
+    kDAC_BufferWorkAsSwingMode,       /*!< Swing mode. */
+#endif                                /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */
+    kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */
+#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE
+    kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */
+#endif                         /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */
+} dac_buffer_work_mode_t;
+
+/*!
+ * @brief DAC module configuration.
+ */
+typedef struct _dac_config
+{
+    dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */
+    bool enableLowPowerMode;                               /*!< Enable the low-power mode. */
+} dac_config_t;
+
+/*!
+ * @brief DAC buffer configuration.
+ */
+typedef struct _dac_buffer_config
+{
+    dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */
+#endif                                /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    dac_buffer_work_mode_t workMode;  /*!< Select the buffer's work mode. */
+    uint8_t upperLimit;               /*!< Set the upper limit for the buffer index.
+                                           Normally, 0-15 is available for a buffer with 16 items. */
+} dac_buffer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DAC module.
+ *
+ * This function initializes the DAC module including the following operations.
+ *  - Enabling the clock for DAC module.
+ *  - Configuring the DAC converter with a user configuration.
+ *  - Enabling the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ * @param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_Init(DAC_Type *base, const dac_config_t *config);
+
+/*!
+ * @brief De-initializes the DAC module.
+ *
+ * This function de-initializes the DAC module including the following operations.
+ *  - Disabling the DAC module.
+ *  - Disabling the clock for the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ */
+void DAC_Deinit(DAC_Type *base);
+
+/*!
+ * @brief Initializes the DAC user configuration structure.
+ *
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
+ * @code
+ *   config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
+ *   config->enableLowPowerMode = false;
+ * @endcode
+ * @param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_GetDefaultConfig(dac_config_t *config);
+
+/*!
+ * @brief Enables the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+static inline void DAC_Enable(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C0 |= (uint8_t)DAC_C0_DACEN_MASK;
+    }
+    else
+    {
+        base->C0 &= (uint8_t)(~DAC_C0_DACEN_MASK);
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Buffer
+ * @{
+ */
+
+/*!
+ * @brief Enables the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+static inline void DAC_EnableBuffer(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= (uint8_t)DAC_C1_DACBFEN_MASK;
+    }
+    else
+    {
+        base->C1 &= (uint8_t)(~DAC_C1_DACBFEN_MASK);
+    }
+}
+
+/*!
+ * @brief Configures the CMP buffer.
+ *
+ * @param base   DAC peripheral base address.
+ * @param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config);
+
+/*!
+ * @brief Initializes the DAC buffer configuration structure.
+ *
+ * This function initializes the DAC buffer configuration structure to default values. The default values are as
+ * follows.
+ * @code
+ *   config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
+ *   config->watermark   = kDAC_BufferWatermark1Word;
+ *   config->workMode    = kDAC_BufferWorkAsNormalMode;
+ *   config->upperLimit  = DAC_DATL_COUNT - 1U;
+ * @endcode
+ * @param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config);
+
+/*!
+ * @brief Enables the DMA for DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables or disables the feature.
+ */
+static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= (uint8_t)DAC_C1_DMAEN_MASK;
+    }
+    else
+    {
+        base->C1 &= (uint8_t)(~DAC_C1_DMAEN_MASK);
+    }
+}
+
+/*!
+ * @brief Sets the value for  items in the buffer.
+ *
+ * @param base  DAC peripheral base address.
+ * @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC
+ * buffer.
+ * @param value Setting the value for items in the buffer. 12-bits are available.
+ */
+void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value);
+
+/*!
+ * @brief Triggers the buffer using software and updates the read pointer of the DAC buffer.
+ *
+ * This function triggers the function using software. The read pointer of the DAC buffer is updated with one step
+ * after this function is called. Changing the read pointer depends on the buffer's work mode.
+ *
+ * @param base DAC peripheral base address.
+ */
+static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base)
+{
+    base->C0 |= DAC_C0_DACSWTRG_MASK;
+}
+
+/*!
+ * @brief Gets the current read pointer of the DAC buffer.
+ *
+ * This function gets the current read pointer of the DAC buffer.
+ * The current output value depends on the item indexed by the read pointer. It is updated either
+ * by a software trigger or a hardware trigger.
+ *
+ * @param  base DAC peripheral base address.
+ *
+ * @return      The current read pointer of the DAC buffer.
+ */
+static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
+{
+    return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT);
+}
+
+/*!
+ * @brief Sets the current read pointer of the DAC buffer.
+ *
+ * This function sets the current read pointer of the DAC buffer.
+ * The current output value depends on the item indexed by the read pointer. It is updated either by a
+ * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
+ *
+ * @param base  DAC peripheral base address.
+ * @param index Setting an index value for the pointer.
+ */
+void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index);
+
+/*!
+ * @brief Enables interrupts for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
+ */
+void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables interrupts for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for interrupts. See  "_dac_buffer_interrupt_enable".
+ */
+void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the flags of events for the DAC buffer.
+ *
+ * @param  base DAC peripheral base address.
+ *
+ * @return      Mask value for the asserted flags. See  "_dac_buffer_status_flags".
+ */
+uint8_t DAC_GetBufferStatusFlags(DAC_Type *base);
+
+/*!
+ * @brief Clears the flags of events for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for flags. See "_dac_buffer_status_flags_t".
+ */
+void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* FSL_DAC_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.c
new file mode 100644
index 0000000000..d809406a2b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dma"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMA.
+ *
+ * @param base DMA peripheral base address.
+ */
+static uint32_t DMA_GetInstance(DMA_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMA instance number to base pointer. */
+static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map DMA instance number to clock name. */
+static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Array to map DMA instance number to IRQ number. */
+static const IRQn_Type s_dmaIRQNumber[][FSL_FEATURE_DMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
+
+/*! @brief Pointers to transfer handle for each DMA channel. */
+static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_MODULE_CHANNEL * FSL_FEATURE_SOC_DMA_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t DMA_GetInstance(DMA_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
+    {
+        if (s_dmaBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dmaBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the DMA peripheral.
+ *
+ * This function ungates the DMA clock.
+ *
+ * param base DMA peripheral base address.
+ */
+void DMA_Init(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Deinitializes the DMA peripheral.
+ *
+ * This function gates the DMA clock.
+ *
+ * param base DMA peripheral base address.
+ */
+void DMA_Deinit(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Resets the DMA channel.
+ *
+ * Sets all register values to reset values and enables
+ * the cycle steal and auto stop channel request features.
+ *
+ * param base DMA peripheral base address.
+ * param channel DMA channel number.
+ */
+void DMA_ResetChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    /* clear all status bit */
+    base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true);
+    /* clear all registers */
+    base->DMA[channel].SAR     = 0;
+    base->DMA[channel].DAR     = 0;
+    base->DMA[channel].DSR_BCR = 0;
+    /* enable cycle steal and enable auto disable channel request */
+    base->DMA[channel].DCR = DMA_DCR_D_REQ(true) | DMA_DCR_CS(true);
+}
+
+/*!
+ * brief Configures the DMA transfer attribute.
+ *
+ * This function configures the transfer attribute including the source address,
+ * destination address, transfer size, and so on.
+ * This example shows how to set up the dma_transfer_config_t
+ * parameters and how to call the DMA_ConfigBasicTransfer function.
+ * code
+ *   dma_transfer_config_t transferConfig;
+ *   memset(&transferConfig, 0, sizeof(transferConfig));
+ *   transferConfig.srcAddr = (uint32_t)srcAddr;
+ *   transferConfig.destAddr = (uint32_t)destAddr;
+ *   transferConfig.enbaleSrcIncrement = true;
+ *   transferConfig.enableDestIncrement = true;
+ *   transferConfig.srcSize = kDMA_Transfersize32bits;
+ *   transferConfig.destSize = kDMA_Transfersize32bits;
+ *   transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH;
+ *   DMA_SetTransferConfig(DMA0, 0, &transferConfig);
+ * endcode
+ *
+ * param base DMA peripheral base address.
+ * param channel DMA channel number.
+ * param config Pointer to the DMA transfer configuration structure.
+ */
+void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+    assert(config != NULL);
+
+    uint32_t tmpreg;
+
+    /* Set source address */
+    base->DMA[channel].SAR = config->srcAddr;
+    /* Set destination address */
+    base->DMA[channel].DAR = config->destAddr;
+    /* Set transfer bytes */
+    base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(config->transferSize);
+    /* Set DMA Control Register */
+    tmpreg = base->DMA[channel].DCR;
+    tmpreg &= ~(DMA_DCR_DSIZE_MASK | DMA_DCR_DINC_MASK | DMA_DCR_SSIZE_MASK | DMA_DCR_SINC_MASK);
+    tmpreg |= (DMA_DCR_DSIZE(config->destSize) | DMA_DCR_DINC(config->enableDestIncrement) |
+               DMA_DCR_SSIZE(config->srcSize) | DMA_DCR_SINC(config->enableSrcIncrement));
+    base->DMA[channel].DCR = tmpreg;
+}
+
+/*!
+ * brief Configures the DMA channel link feature.
+ *
+ * This function allows DMA channels to have their transfers linked. The current DMA channel
+ * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link
+ * type.
+ * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2
+ * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2.
+ * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1.
+ * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0.
+ *
+ * param base DMA peripheral base address.
+ * param channel DMA channel number.
+ * param config Pointer to the channel link configuration structure.
+ */
+void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+    assert(config != NULL);
+
+    uint32_t tmpreg;
+
+    tmpreg = base->DMA[channel].DCR;
+    tmpreg &= ~(DMA_DCR_LINKCC_MASK | DMA_DCR_LCH1_MASK | DMA_DCR_LCH2_MASK);
+    tmpreg |= (DMA_DCR_LINKCC(config->linkType) | DMA_DCR_LCH1(config->channel1) | DMA_DCR_LCH2(config->channel2));
+    base->DMA[channel].DCR = tmpreg;
+}
+
+/*!
+ * brief Sets the DMA modulo for the DMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE)
+ * calculation is performed or the original register value. It provides the ability to implement a circular
+ * data queue easily.
+ *
+ * param base DMA peripheral base address.
+ * param channel DMA channel number.
+ * param srcModulo source address modulo.
+ * param destModulo destination address modulo.
+ */
+void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    uint32_t tmpreg;
+
+    tmpreg = base->DMA[channel].DCR;
+    tmpreg &= ~(DMA_DCR_SMOD_MASK | DMA_DCR_DMOD_MASK);
+    tmpreg |= (DMA_DCR_SMOD(srcModulo) | DMA_DCR_DMOD(destModulo));
+    base->DMA[channel].DCR = tmpreg;
+}
+
+/*!
+ * brief Creates the DMA handle.
+ *
+ * This function is called first if using the transactional API for the DMA. This function
+ * initializes the internal state of the DMA handle.
+ *
+ * param handle DMA handle pointer. The DMA handle stores callback function and
+ *               parameters.
+ * param base DMA peripheral base address.
+ * param channel DMA channel number.
+ */
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+    assert(handle != NULL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    uint32_t dmaInstance;
+    uint32_t channelIndex;
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    handle->base    = base;
+    handle->channel = (uint8_t)channel;
+    /* Get the DMA instance number */
+    dmaInstance  = DMA_GetInstance(base);
+    channelIndex = (dmaInstance * (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL) + channel;
+    /* Store handle */
+    s_DMAHandle[channelIndex] = handle;
+    /* Enable NVIC interrupt. */
+    (void)EnableIRQ(s_dmaIRQNumber[dmaInstance][channelIndex]);
+}
+
+/*!
+ * brief Prepares the DMA transfer configuration structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ * The difference between this function and DMA_PrepareTransfer is that this function expose the address increment
+ * parameter to application, but in DMA_PrepareTransfer, only parts of the address increment option can be selected by
+ * dma_transfer_type_t.
+ *
+ * param config Pointer to the user configuration structure of type dma_transfer_config_t.
+ * param srcAddr DMA transfer source address.
+ * param srcWidth DMA transfer source address width (byte).
+ * param destAddr DMA transfer destination address.
+ * param destWidth DMA transfer destination address width (byte).
+ * param transferBytes DMA transfer bytes to be transferred.
+ * param srcIncrement source address increment type.
+ * param destIncrement dest address increment type.
+ */
+void DMA_PrepareTransferConfig(dma_transfer_config_t *config,
+                               void *srcAddr,
+                               uint32_t srcWidth,
+                               void *destAddr,
+                               uint32_t destWidth,
+                               uint32_t transferBytes,
+                               dma_addr_increment_t srcIncrement,
+                               dma_addr_increment_t destIncrement)
+{
+    assert(config != NULL);
+    assert(srcAddr != NULL);
+    assert(destAddr != NULL);
+    assert((srcWidth == 1UL) || (srcWidth == 2UL) || (srcWidth == 4UL));
+    assert((destWidth == 1UL) || (destWidth == 2UL) || (destWidth == 4UL));
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->srcAddr      = (uint32_t)(uint32_t *)srcAddr;
+    config->destAddr     = (uint32_t)(uint32_t *)destAddr;
+    config->transferSize = transferBytes;
+
+    if (srcWidth == 1UL)
+    {
+        config->srcSize = kDMA_Transfersize8bits;
+    }
+    else if (srcWidth == 2UL)
+    {
+        config->srcSize = kDMA_Transfersize16bits;
+    }
+    else
+    {
+        config->srcSize = kDMA_Transfersize32bits;
+    }
+
+    if (destWidth == 1UL)
+    {
+        config->destSize = kDMA_Transfersize8bits;
+    }
+    else if (destWidth == 2UL)
+    {
+        config->destSize = kDMA_Transfersize16bits;
+    }
+    else
+    {
+        config->destSize = kDMA_Transfersize32bits;
+    }
+
+    config->enableSrcIncrement  = srcIncrement == kDMA_AddrNoIncrement ? false : true;
+    config->enableDestIncrement = destIncrement == kDMA_AddrNoIncrement ? false : true;
+}
+
+/*!
+ * brief Prepares the DMA transfer configuration structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * param config Pointer to the user configuration structure of type dma_transfer_config_t.
+ * param srcAddr DMA transfer source address.
+ * param srcWidth DMA transfer source address width (byte).
+ * param destAddr DMA transfer destination address.
+ * param destWidth DMA transfer destination address width (byte).
+ * param transferBytes DMA transfer bytes to be transferred.
+ * param type DMA transfer type.
+ */
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                         void *srcAddr,
+                         uint32_t srcWidth,
+                         void *destAddr,
+                         uint32_t destWidth,
+                         uint32_t transferBytes,
+                         dma_transfer_type_t type)
+{
+    assert(config != NULL);
+    assert(srcAddr != NULL);
+    assert(destAddr != NULL);
+    assert((srcWidth == 1UL) || (srcWidth == 2UL) || (srcWidth == 4UL));
+    assert((destWidth == 1UL) || (destWidth == 2UL) || (destWidth == 4UL));
+
+    dma_addr_increment_t srcIncrement = kDMA_AddrNoIncrement, destIncrement = kDMA_AddrNoIncrement;
+
+    if (type == kDMA_MemoryToMemory)
+    {
+        srcIncrement  = kDMA_AddrIncrementPerTransferWidth;
+        destIncrement = kDMA_AddrIncrementPerTransferWidth;
+    }
+    else if (type == kDMA_PeripheralToMemory)
+    {
+        srcIncrement  = kDMA_AddrNoIncrement;
+        destIncrement = kDMA_AddrIncrementPerTransferWidth;
+    }
+    else
+    {
+        srcIncrement  = kDMA_AddrIncrementPerTransferWidth;
+        destIncrement = kDMA_AddrNoIncrement;
+    }
+
+    DMA_PrepareTransferConfig(config, srcAddr, srcWidth, destAddr, destWidth, transferBytes, srcIncrement,
+                              destIncrement);
+}
+
+/*!
+ * brief Sets the DMA callback function.
+ *
+ * This callback is called in the DMA IRQ handler. Use the callback to do something
+ * after the current transfer complete.
+ *
+ * param handle DMA handle pointer.
+ * param callback DMA callback function pointer.
+ * param userData Parameter for callback function. If it is not needed, just set to NULL.
+ */
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+/*!
+ * brief Submits the DMA transfer request.
+ *
+ * This function submits the DMA transfer request according to the transfer configuration structure.
+ *
+ * param handle DMA handle pointer.
+ * param config Pointer to DMA transfer configuration structure.
+ * param options Additional configurations for transfer. Use
+ *                the defined dma_transfer_options_t type.
+ * retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded.
+ * retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed.
+ * note This function can't process multi transfer request.
+ */
+status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+
+    /* Check if DMA is busy */
+    if ((handle->base->DMA[handle->channel].DSR_BCR & DMA_DSR_BCR_BSY_MASK) != 0UL)
+    {
+        return kStatus_DMA_Busy;
+    }
+    DMA_ResetChannel(handle->base, handle->channel);
+    DMA_SetTransferConfig(handle->base, handle->channel, config);
+    if ((options & (uint32_t)kDMA_EnableInterrupt) != 0UL)
+    {
+        DMA_EnableInterrupts(handle->base, handle->channel);
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief DMA aborts a transfer.
+ *
+ * This function disables the channel request and clears all status bits.
+ * Submit another transfer after calling this API.
+ *
+ * param handle DMA handle pointer.
+ */
+void DMA_AbortTransfer(dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK;
+    /* clear all status bit */
+    handle->base->DMA[handle->channel].DSR_BCR |= DMA_DSR_BCR_DONE(true);
+}
+
+/*!
+ * brief DMA IRQ handler for current transfer complete.
+ *
+ * This function clears the channel interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * param handle DMA handle pointer.
+ */
+void DMA_HandleIRQ(dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Clear interrupt pending bit */
+    DMA_ClearChannelStatusFlags(handle->base, handle->channel, kDMA_TransactionsDoneFlag);
+    if (handle->callback != NULL)
+    {
+        (handle->callback)(handle, handle->userData);
+    }
+}
+
+#if defined(FSL_FEATURE_DMA_MODULE_CHANNEL) && (FSL_FEATURE_DMA_MODULE_CHANNEL == 4U)
+void DMA0_DriverIRQHandler(void);
+void DMA0_DriverIRQHandler(void)
+{
+    DMA_HandleIRQ(s_DMAHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void DMA1_DriverIRQHandler(void);
+void DMA1_DriverIRQHandler(void)
+{
+    DMA_HandleIRQ(s_DMAHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void DMA2_DriverIRQHandler(void);
+void DMA2_DriverIRQHandler(void)
+{
+    DMA_HandleIRQ(s_DMAHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void DMA3_DriverIRQHandler(void);
+void DMA3_DriverIRQHandler(void)
+{
+    DMA_HandleIRQ(s_DMAHandle[3]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* FSL_FEATURE_DMA_MODULE_CHANNEL */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.h
new file mode 100644
index 0000000000..4f33943349
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dma.h
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_DMA_H_
+#define FSL_DMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dma
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief DMA driver version 2.1.2. */
+#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @} */
+
+/*! @brief _dma_channel_status_flags status flag for the DMA driver. */
+enum
+{
+    kDMA_TransactionsBCRFlag = DMA_DSR_BCR_BCR_MASK,        /*!< Contains the number of bytes yet to be
+                                                                 transferred for a given block */
+    kDMA_TransactionsDoneFlag      = DMA_DSR_BCR_DONE_MASK, /*!< Transactions Done */
+    kDMA_TransactionsBusyFlag      = DMA_DSR_BCR_BSY_MASK,  /*!< Transactions Busy */
+    kDMA_TransactionsRequestFlag   = DMA_DSR_BCR_REQ_MASK,  /*!< Transactions Request */
+    kDMA_BusErrorOnDestinationFlag = DMA_DSR_BCR_BED_MASK,  /*!< Bus Error on Destination */
+    kDMA_BusErrorOnSourceFlag      = DMA_DSR_BCR_BES_MASK,  /*!< Bus Error on Source */
+    kDMA_ConfigurationErrorFlag    = DMA_DSR_BCR_CE_MASK,   /*!< Configuration Error */
+};
+
+/*! @brief DMA transfer size type*/
+typedef enum _dma_transfer_size
+{
+    kDMA_Transfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */
+    kDMA_Transfersize8bits,         /*!< 8 bits are transferred for every read/write */
+    kDMA_Transfersize16bits,        /*!< 16b its are transferred for every read/write */
+} dma_transfer_size_t;
+
+/*! @brief Configuration type for the DMA modulo */
+typedef enum _dma_modulo
+{
+    kDMA_ModuloDisable = 0x0U, /*!< Buffer disabled */
+    kDMA_Modulo16Bytes,        /*!< Circular buffer size is 16 bytes. */
+    kDMA_Modulo32Bytes,        /*!< Circular buffer size is 32 bytes. */
+    kDMA_Modulo64Bytes,        /*!< Circular buffer size is 64 bytes. */
+    kDMA_Modulo128Bytes,       /*!< Circular buffer size is 128 bytes. */
+    kDMA_Modulo256Bytes,       /*!< Circular buffer size is 256 bytes. */
+    kDMA_Modulo512Bytes,       /*!< Circular buffer size is 512 bytes. */
+    kDMA_Modulo1KBytes,        /*!< Circular buffer size is 1 KB. */
+    kDMA_Modulo2KBytes,        /*!< Circular buffer size is 2 KB. */
+    kDMA_Modulo4KBytes,        /*!< Circular buffer size is 4 KB. */
+    kDMA_Modulo8KBytes,        /*!< Circular buffer size is 8 KB. */
+    kDMA_Modulo16KBytes,       /*!< Circular buffer size is 16 KB. */
+    kDMA_Modulo32KBytes,       /*!< Circular buffer size is 32 KB. */
+    kDMA_Modulo64KBytes,       /*!< Circular buffer size is 64 KB. */
+    kDMA_Modulo128KBytes,      /*!< Circular buffer size is 128 KB. */
+    kDMA_Modulo256KBytes,      /*!< Circular buffer size is 256 KB. */
+} dma_modulo_t;
+
+/*! @brief DMA channel link type */
+typedef enum _dma_channel_link_type
+{
+    kDMA_ChannelLinkDisable = 0x0U,      /*!< No channel link. */
+    kDMA_ChannelLinkChannel1AndChannel2, /*!< Perform a link to channel LCH1 after each cycle-steal transfer.
+                                              followed by a link to LCH2 after the BCR decrements to 0. */
+    kDMA_ChannelLinkChannel1,            /*!< Perform a link to LCH1 after each cycle-steal transfer. */
+    kDMA_ChannelLinkChannel1AfterBCR0,   /*!< Perform a link to LCH1 after the BCR decrements. */
+} dma_channel_link_type_t;
+
+/*! @brief DMA transfer type */
+typedef enum _dma_transfer_type
+{
+    kDMA_MemoryToMemory = 0x0U, /*!< Memory to Memory transfer. */
+    kDMA_PeripheralToMemory,    /*!< Peripheral to Memory transfer. */
+    kDMA_MemoryToPeripheral,    /*!< Memory to Peripheral transfer. */
+} dma_transfer_type_t;
+
+/*! @brief DMA transfer options */
+typedef enum _dma_transfer_options
+{
+    kDMA_NoOptions = 0x0U, /*!< Transfer without options. */
+    kDMA_EnableInterrupt,  /*!< Enable interrupt while transfer complete. */
+} dma_transfer_options_t;
+
+/*! @brief dma addre increment type */
+typedef enum _dma_addr_increment
+{
+    kDMA_AddrNoIncrement               = 0x0U, /*!< Transfer address not increment. */
+    kDMA_AddrIncrementPerTransferWidth = 0x1U, /*!< Transfer address increment per transfer width */
+} dma_addr_increment_t;
+
+/*! @brief _dma_transfer_status DMA transfer status */
+enum
+{
+    kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< DMA is busy. */
+};
+
+/*! @brief DMA transfer configuration structure */
+typedef struct _dma_transfer_config
+{
+    uint32_t srcAddr;             /*!< DMA transfer source address. */
+    uint32_t destAddr;            /*!< DMA destination address.*/
+    bool enableSrcIncrement;      /*!< Source address increase after each transfer. */
+    dma_transfer_size_t srcSize;  /*!< Source transfer size unit. */
+    bool enableDestIncrement;     /*!< Destination address increase after each transfer. */
+    dma_transfer_size_t destSize; /*!< Destination transfer unit.*/
+    uint32_t transferSize;        /*!< The number of bytes to be transferred. */
+} dma_transfer_config_t;
+
+/*! @brief DMA transfer configuration structure */
+typedef struct _dma_channel_link_config
+{
+    dma_channel_link_type_t linkType; /*!< Channel link type. */
+    uint32_t channel1;                /*!< The index of channel 1. */
+    uint32_t channel2;                /*!< The index of channel 2. */
+} dma_channel_link_config_t;
+
+struct _dma_handle;
+/*! @brief Callback function prototype for the DMA driver. */
+typedef void (*dma_callback)(struct _dma_handle *handle, void *userData);
+
+/*! @brief DMA DMA handle structure */
+typedef struct _dma_handle
+{
+    DMA_Type *base;        /*!< DMA peripheral address. */
+    uint8_t channel;       /*!< DMA channel used. */
+    dma_callback callback; /*!< DMA callback function.*/
+    void *userData;        /*!< Callback parameter. */
+} dma_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMA Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMA peripheral.
+ *
+ * This function ungates the DMA clock.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Init(DMA_Type *base);
+
+/*!
+ * @brief Deinitializes the DMA peripheral.
+ *
+ * This function gates the DMA clock.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Deinit(DMA_Type *base);
+
+/*! @} */
+/*!
+ * @name DMA Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Resets the DMA channel.
+ *
+ * Sets all register values to reset values and enables
+ * the cycle steal and auto stop channel request features.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+void DMA_ResetChannel(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Configures the DMA transfer attribute.
+ *
+ * This function configures the transfer attribute including the source address,
+ * destination address, transfer size, and so on.
+ * This example shows how to set up the dma_transfer_config_t
+ * parameters and how to call the DMA_ConfigBasicTransfer function.
+ * @code
+ *   dma_transfer_config_t transferConfig;
+ *   memset(&transferConfig, 0, sizeof(transferConfig));
+ *   transferConfig.srcAddr = (uint32_t)srcAddr;
+ *   transferConfig.destAddr = (uint32_t)destAddr;
+ *   transferConfig.enbaleSrcIncrement = true;
+ *   transferConfig.enableDestIncrement = true;
+ *   transferConfig.srcSize = kDMA_Transfersize32bits;
+ *   transferConfig.destSize = kDMA_Transfersize32bits;
+ *   transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH;
+ *   DMA_SetTransferConfig(DMA0, 0, &transferConfig);
+ * @endcode
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param config Pointer to the DMA transfer configuration structure.
+ */
+void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config);
+
+/*!
+ * @brief Configures the DMA channel link feature.
+ *
+ * This function allows DMA channels to have their transfers linked. The current DMA channel
+ * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link
+ * type.
+ * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2
+ * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2.
+ * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1.
+ * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param config Pointer to the channel link configuration structure.
+ */
+void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config);
+
+/*!
+ * @brief Sets the DMA source address for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param srcAddr DMA source address.
+ */
+static inline void DMA_SetSourceAddress(DMA_Type *base, uint32_t channel, uint32_t srcAddr)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].SAR = srcAddr;
+}
+
+/*!
+ * @brief Sets the DMA destination address for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param destAddr DMA destination address.
+ */
+static inline void DMA_SetDestinationAddress(DMA_Type *base, uint32_t channel, uint32_t destAddr)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DAR = destAddr;
+}
+
+/*!
+ * @brief Sets the DMA transfer size for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param size The number of bytes to be transferred.
+ */
+static inline void DMA_SetTransferSize(DMA_Type *base, uint32_t channel, uint32_t size)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size);
+}
+
+/*!
+ * @brief Sets the DMA modulo for the DMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE)
+ * calculation is performed or the original register value. It provides the ability to implement a circular
+ * data queue easily.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param srcModulo source address modulo.
+ * @param destModulo destination address modulo.
+ */
+void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo);
+
+/*!
+ * @brief Enables the DMA cycle steal for the DMA transfer.
+ *
+ * If the cycle steal feature is enabled (true), the DMA controller forces a single read/write transfer per request,
+ *  or it continuously makes read/write transfers until the BCR decrements to 0.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param enable The command for enable (true) or disable (false).
+ */
+static inline void DMA_EnableCycleSteal(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable);
+}
+
+/*!
+ * @brief Enables the DMA auto align for the DMA transfer.
+ *
+ * If the auto align feature is enabled (true), the appropriate address register increments
+ * regardless of DINC or SINC.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param enable The command for enable (true) or disable (false).
+ */
+static inline void DMA_EnableAutoAlign(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable);
+}
+
+/*!
+ * @brief Enables the DMA async request for the DMA transfer.
+ *
+ * If the async request feature is enabled (true), the DMA supports asynchronous DREQs
+ * while the MCU is in stop mode.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param enable The command for enable (true) or disable (false).
+ */
+static inline void DMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable);
+}
+
+/*!
+ * @brief Enables an interrupt for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR |= DMA_DCR_EINT(true);
+}
+
+/*!
+ * @brief Disables an interrupt for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK;
+}
+
+/*! @} */
+/*!
+ * @name DMA Channel Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMA hardware channel request.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel The DMA channel number.
+ */
+static inline void DMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK;
+}
+
+/*!
+ * @brief Disables the DMA hardware channel request.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK;
+}
+
+/*!
+ * @brief Starts the DMA transfer with a software trigger.
+ *
+ * This function starts only one read/write iteration.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel The DMA channel number.
+ */
+static inline void DMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    base->DMA[channel].DCR |= DMA_DCR_START_MASK;
+}
+
+/*!
+ * @brief Starts the DMA enable/disable auto disable request.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel The DMA channel number.
+ * @param enable true is enable, false is disable.
+ */
+static inline void DMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    if (enable)
+    {
+        base->DMA[channel].DCR |= DMA_DCR_D_REQ(1);
+    }
+    else
+    {
+        base->DMA[channel].DCR &= ~DMA_DCR_D_REQ_MASK;
+    }
+}
+
+/*! @} */
+/*!
+ * @name DMA Channel Status Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+static inline uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    return (base->DMA[channel].DSR_BCR & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT;
+}
+
+/*!
+ * @brief Gets the DMA channel status flags.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The mask of the channel status. Use the _dma_channel_status_flags
+ *         type to decode the return 32 bit variables.
+ */
+static inline uint32_t DMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    return base->DMA[channel].DSR_BCR;
+}
+
+/*!
+ * @brief Clears the DMA channel status flags.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param mask The mask of the channel status to be cleared. Use
+ *             the defined _dma_channel_status_flags type.
+ */
+static inline void DMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
+
+    if (mask != 0U)
+    {
+        base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true);
+    }
+}
+
+/*! @} */
+/*!
+ * @name DMA Channel Transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Creates the DMA handle.
+ *
+ * This function is called first if using the transactional API for the DMA. This function
+ * initializes the internal state of the DMA handle.
+ *
+ * @param handle DMA handle pointer. The DMA handle stores callback function and
+ *               parameters.
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Sets the DMA callback function.
+ *
+ * This callback is called in the DMA IRQ handler. Use the callback to do something
+ * after the current transfer complete.
+ *
+ * @param handle DMA handle pointer.
+ * @param callback DMA callback function pointer.
+ * @param userData Parameter for callback function. If it is not needed, just set to NULL.
+ */
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the DMA transfer configuration structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ * The difference between this function and DMA_PrepareTransfer is that this function expose the address increment
+ * parameter to application, but in DMA_PrepareTransfer, only parts of the address increment option can be selected by
+ * dma_transfer_type_t.
+ *
+ * @param config Pointer to the user configuration structure of type dma_transfer_config_t.
+ * @param srcAddr DMA transfer source address.
+ * @param srcWidth DMA transfer source address width (byte).
+ * @param destAddr DMA transfer destination address.
+ * @param destWidth DMA transfer destination address width (byte).
+ * @param transferBytes DMA transfer bytes to be transferred.
+ * @param srcIncrement source address increment type.
+ * @param destIncrement dest address increment type.
+ */
+void DMA_PrepareTransferConfig(dma_transfer_config_t *config,
+                               void *srcAddr,
+                               uint32_t srcWidth,
+                               void *destAddr,
+                               uint32_t destWidth,
+                               uint32_t transferBytes,
+                               dma_addr_increment_t srcIncrement,
+                               dma_addr_increment_t destIncrement);
+
+/*!
+ * @brief Prepares the DMA transfer configuration structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config Pointer to the user configuration structure of type dma_transfer_config_t.
+ * @param srcAddr DMA transfer source address.
+ * @param srcWidth DMA transfer source address width (byte).
+ * @param destAddr DMA transfer destination address.
+ * @param destWidth DMA transfer destination address width (byte).
+ * @param transferBytes DMA transfer bytes to be transferred.
+ * @param type DMA transfer type.
+ */
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                         void *srcAddr,
+                         uint32_t srcWidth,
+                         void *destAddr,
+                         uint32_t destWidth,
+                         uint32_t transferBytes,
+                         dma_transfer_type_t type);
+
+/*!
+ * @brief Submits the DMA transfer request.
+ *
+ * This function submits the DMA transfer request according to the transfer configuration structure.
+ *
+ * @param handle DMA handle pointer.
+ * @param config Pointer to DMA transfer configuration structure.
+ * @param options Additional configurations for transfer. Use
+ *                the defined dma_transfer_options_t type.
+ * @retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded.
+ * @retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed.
+ * @note This function can't process multi transfer request.
+ */
+status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options);
+
+/*!
+ * @brief DMA starts a transfer.
+ *
+ * This function enables the channel request. Call this function
+ * after submitting a transfer request.
+ *
+ * @param handle DMA handle pointer.
+ * @retval kStatus_DMA_Success It indicates that the DMA start transfer succeed.
+ * @retval kStatus_DMA_Busy It indicates that the DMA has started a transfer.
+ */
+static inline void DMA_StartTransfer(dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    handle->base->DMA[handle->channel].DCR |= DMA_DCR_ERQ_MASK;
+}
+
+/*!
+ * @brief DMA stops a transfer.
+ *
+ * This function disables the channel request to stop a DMA transfer.
+ * The transfer can be resumed by calling the DMA_StartTransfer.
+ *
+ * @param handle DMA handle pointer.
+ */
+static inline void DMA_StopTransfer(dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK;
+}
+
+/*!
+ * @brief DMA aborts a transfer.
+ *
+ * This function disables the channel request and clears all status bits.
+ * Submit another transfer after calling this API.
+ *
+ * @param handle DMA handle pointer.
+ */
+void DMA_AbortTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief DMA IRQ handler for current transfer complete.
+ *
+ * This function clears the channel interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * @param handle DMA handle pointer.
+ */
+void DMA_HandleIRQ(dma_handle_t *handle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* FSL_DMA_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.c
new file mode 100644
index 0000000000..8bfbe6c367
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dmamux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dmamux"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMAMUX.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMAMUX instance number to base pointer. */
+static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map DMAMUX instance number to clock name. */
+static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
+    {
+        if (s_dmamuxBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dmamuxBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ *
+ */
+void DMAMUX_Init(DMAMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ */
+void DMAMUX_Deinit(DMAMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.h
new file mode 100644
index 0000000000..c28167acf0
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_dmamux.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_DMAMUX_H_
+#define FSL_DMAMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmamux
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief DMAMUX driver version 2.1.0. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMAMUX Initialization and de-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ *
+ */
+void DMAMUX_Init(DMAMUX_Type *base);
+
+/*!
+ * @brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+void DMAMUX_Deinit(DMAMUX_Type *base);
+
+/*! @} */
+/*!
+ * @name DMAMUX Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMAMUX channel.
+ *
+ * This function enables the DMAMUX channel.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
+}
+
+/*!
+ * @brief Disables the DMAMUX channel.
+ *
+ * This function disables the DMAMUX channel.
+ *
+ * @note The user must disable the DMAMUX channel before configuring it.
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+#if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
+    base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
+#else
+    base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
+#endif
+}
+
+/*!
+ * @brief Configures the DMAMUX channel source.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param source Channel source, which is used to trigger the DMA transfer.User need to use the
+ *               dma_request_source_t type as the input parameter.
+ */
+static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, int32_t source)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+#if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
+    base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
+#else
+    base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
+#endif
+}
+
+#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
+/*!
+ * @brief Enables the DMAMUX period trigger.
+ *
+ * This function enables the DMAMUX period trigger feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
+}
+
+/*!
+ * @brief Disables the DMAMUX period trigger.
+ *
+ * This function disables the DMAMUX period trigger.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+#if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
+    base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
+#else
+    base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
+#endif
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
+
+#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
+/*!
+ * @brief Enables the DMA channel to be always ON.
+ *
+ * This function enables the DMAMUX channel always ON feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
+ */
+static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    if (enable)
+    {
+        base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
+    }
+    else
+    {
+        base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
+    }
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* FSL_DMAMUX_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flash.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flash.h
new file mode 100644
index 0000000000..429d33b8af
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flash.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FLASH_H
+#define FSL_FLASH_H
+
+#include "fsl_ftfx_cache.h"
+#include "fsl_ftfx_flash.h"
+#if FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#include "fsl_ftfx_flexnvm.h"
+#endif
+
+/*!
+ * @addtogroup flash_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FLASH_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.c
new file mode 100644
index 0000000000..fbdb4e959c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio"
+#endif
+
+/*< @brief user configurable flexio handle count. */
+#define FLEXIO_HANDLE_COUNT 2
+
+#if defined(FLEXIO_RSTS)
+#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS
+#elif defined(FLEXIO_RSTS_N)
+#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to flexio bases for each instance. */
+FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to flexio clocks for each instance. */
+const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*< @brief pointer to array of FLEXIO handle. */
+static void *s_flexioHandle[FLEXIO_HANDLE_COUNT];
+
+/*< @brief pointer to array of FLEXIO IP types. */
+static void *s_flexioType[FLEXIO_HANDLE_COUNT];
+
+/*< @brief pointer to array of FLEXIO Isr. */
+static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
+
+/* FlexIO common IRQ Handler. */
+static void FLEXIO_CommonIRQHandler(void);
+
+#if defined(FLEXIO_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+/*!
+ * brief Get instance number for FLEXIO module.
+ *
+ * param base FLEXIO peripheral base address.
+ */
+uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++)
+    {
+        if (s_flexioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_flexioBases));
+
+    return instance;
+}
+
+/*!
+ * brief Configures the FlexIO with a FlexIO configuration. The configuration structure
+ * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
+ *
+ * Example
+   code
+   flexio_config_t config = {
+   .enableFlexio = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false
+   };
+   FLEXIO_Configure(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
+{
+    uint32_t ctrlReg = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FLEXIO_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]);
+#endif
+
+    FLEXIO_Reset(base);
+
+    ctrlReg = base->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) |
+                FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio));
+    if (!userConfig->enableInDoze)
+    {
+        ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+
+    base->CTRL = ctrlReg;
+}
+
+/*!
+ * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
+ *
+ * note After calling this API, call the FLEXO_Init to use the FlexIO module.
+ *
+ * param base FlexIO peripheral base address
+ */
+void FLEXIO_Deinit(FLEXIO_Type *base)
+{
+    FLEXIO_Enable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can used directly to call the FLEXIO_Configure().
+ *
+ * Example:
+   code
+   flexio_config_t config;
+   FLEXIO_GetDefaultConfig(&config);
+   endcode
+ *
+ * param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
+{
+    assert(userConfig != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(userConfig, 0, sizeof(*userConfig));
+
+    userConfig->enableFlexio     = true;
+    userConfig->enableInDoze     = false;
+    userConfig->enableInDebug    = true;
+    userConfig->enableFastAccess = false;
+}
+
+/*!
+ * brief Resets the FlexIO module.
+ *
+ * param base FlexIO peripheral base address
+ */
+void FLEXIO_Reset(FLEXIO_Type *base)
+{
+    /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
+    base->CTRL |= FLEXIO_CTRL_SWRST_MASK;
+    base->CTRL = 0;
+}
+
+/*!
+ * brief Gets the shifter buffer address for the DMA transfer usage.
+ *
+ * param base FlexIO peripheral base address
+ * param type Shifter type of flexio_shifter_buffer_type_t
+ * param index Shifter index
+ * return Corresponding shifter buffer index
+ */
+uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
+{
+    assert(index < FLEXIO_SHIFTBUF_COUNT);
+
+    uint32_t address = 0;
+
+    switch (type)
+    {
+        case kFLEXIO_ShifterBuffer:
+            address = (uint32_t) & (base->SHIFTBUF[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferBitSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBIS[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBYS[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferBitByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBBS[index]);
+            break;
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
+        case kFLEXIO_ShifterBufferNibbleByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFNBS[index]);
+            break;
+
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP
+        case kFLEXIO_ShifterBufferHalfWordSwapped:
+            address = (uint32_t) & (base->SHIFTBUFHWS[index]);
+            break;
+
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP
+        case kFLEXIO_ShifterBufferNibbleSwapped:
+            address = (uint32_t) & (base->SHIFTBUFNIS[index]);
+            break;
+
+#endif
+        default:
+            address = (uint32_t) & (base->SHIFTBUF[index]);
+            break;
+    }
+    return address;
+}
+
+/*!
+ * brief Configures the shifter with the shifter configuration. The configuration structure
+ * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
+ * mode, select which timer controls the shifter to shift, whether to generate start bit/stop
+ *  bit, and the polarity of start bit and stop bit.
+ *
+ * Example
+   code
+   flexio_shifter_config_t config = {
+   .timerSelect = 0,
+   .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinPolarity = kFLEXIO_PinActiveLow,
+   .shifterMode = kFLEXIO_ShifterModeTransmit,
+   .inputSource = kFLEXIO_ShifterInputFromPin,
+   .shifterStop = kFLEXIO_ShifterStopBitHigh,
+   .shifterStart = kFLEXIO_ShifterStartBitLow
+   };
+   FLEXIO_SetShifterConfig(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param index Shifter index
+ * param shifterConfig Pointer to flexio_shifter_config_t structure
+*/
+void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
+{
+    base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+                            | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth)
+#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
+                            | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) |
+                            FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart);
+
+    base->SHIFTCTL[index] =
+        FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) |
+        FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) |
+        FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
+}
+
+/*!
+ * brief Configures the timer with the timer configuration. The configuration structure
+ * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
+ * mode, select trigger source for timer and the timer pin output and the timing for timer.
+ *
+ * Example
+   code
+   flexio_timer_config_t config = {
+   .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
+   .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
+   .triggerSource = kFLEXIO_TimerTriggerSourceInternal,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinSelect = 0,
+   .pinPolarity = kFLEXIO_PinActiveHigh,
+   .timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
+   .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
+   .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
+   .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
+   .timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
+   .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
+   .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
+   .timerStart = kFLEXIO_TimerStartBitEnabled
+   };
+   FLEXIO_SetTimerConfig(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param index Timer index
+ * param timerConfig Pointer to the flexio_timer_config_t structure
+*/
+void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
+{
+    base->TIMCFG[index] =
+        FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) |
+        FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) |
+        FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) |
+        FLEXIO_TIMCFG_TSTART(timerConfig->timerStart);
+
+    base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare);
+
+    base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) |
+                          FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) |
+                          FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) |
+                          FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) |
+                          FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
+}
+
+/*!
+ * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * param base Pointer to the FlexIO simulated peripheral type.
+ * param handle Pointer to the handler for FlexIO simulated peripheral.
+ * param isr FlexIO simulated peripheral interrupt handler.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
+{
+    assert(base != NULL);
+    assert(handle != NULL);
+    assert(isr != NULL);
+
+    uint8_t index;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioHandle[index] == NULL)
+        {
+            /* Register FLEXIO simulated driver base, handle and isr. */
+            s_flexioType[index]   = base;
+            s_flexioHandle[index] = handle;
+            s_flexioIsr[index]    = isr;
+            break;
+        }
+    }
+
+    if (index == (uint8_t)FLEXIO_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+/*!
+ * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * param base Pointer to the FlexIO simulated peripheral type.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_UnregisterHandleIRQ(void *base)
+{
+    assert(base != NULL);
+
+    uint8_t index;
+
+    /* Find the index from base address mappings. */
+    for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioType[index] == base)
+        {
+            /* Unregister FLEXIO simulated driver handle and isr. */
+            s_flexioType[index]   = NULL;
+            s_flexioHandle[index] = NULL;
+            s_flexioIsr[index]    = NULL;
+            break;
+        }
+    }
+
+    if (index == (uint8_t)FLEXIO_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+static void FLEXIO_CommonIRQHandler(void)
+{
+    uint8_t index;
+
+    for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioHandle[index] != NULL)
+        {
+            s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]);
+        }
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+/*!
+ * brief Configure a FLEXIO pin used by the board.
+ *
+ * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FLEXIO_SetPinConfig() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * code
+ * Define a digital input pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalInput,
+ *   0U,
+ *   kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
+ * }
+ * Define a digital output pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalOutput,
+ *   0U,
+ *   0U
+ * }
+ * endcode
+ * param base   FlexIO peripheral base address
+ * param pin    FLEXIO pin number.
+ * param config FLEXIO pin configuration pointer.
+ */
+void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)
+{
+    assert(NULL != config);
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    if (config->pinDirection == kFLEXIO_DigitalInput)
+    {
+        base->PINOUTE &= ~(1UL << pin);
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable))
+        {
+            base->PINIEN = 1UL << pin;
+            /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+            NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
+            /* Enable interrupt in NVIC. */
+            (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
+        }
+
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable))
+        {
+            base->PINREN = 1UL << pin;
+        }
+
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable))
+        {
+            base->PINFEN = 1UL << pin;
+        }
+    }
+    else
+    {
+        FLEXIO_EnablePinOutput(base, pin);
+        FLEXIO_PinWrite(base, pin, config->outputLogic);
+    }
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
+
+void FLEXIO_DriverIRQHandler(void);
+void FLEXIO_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void FLEXIO0_DriverIRQHandler(void);
+void FLEXIO0_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void FLEXIO1_DriverIRQHandler(void);
+void FLEXIO1_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void UART2_FLEXIO_DriverIRQHandler(void);
+void UART2_FLEXIO_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void FLEXIO2_DriverIRQHandler(void);
+void FLEXIO2_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void FLEXIO3_DriverIRQHandler(void);
+void FLEXIO3_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.h
new file mode 100644
index 0000000000..1e1bc6278d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_H_
+#define FSL_FLEXIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexio_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO driver version. */
+#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @} */
+
+/*! @brief Calculate FlexIO timer trigger.*/
+#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)   ((uint32_t)(x) << 1U)
+#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U)
+#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)       (((uint32_t)(x) << 2U) | 0x3U)
+
+/*! @brief Define time of timer trigger polarity.*/
+typedef enum _flexio_timer_trigger_polarity
+{
+    kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */
+    kFLEXIO_TimerTriggerPolarityActiveLow  = 0x1U, /*!< Active low. */
+} flexio_timer_trigger_polarity_t;
+
+/*! @brief Define type of timer trigger source.*/
+typedef enum _flexio_timer_trigger_source
+{
+    kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */
+    kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */
+} flexio_timer_trigger_source_t;
+
+/*! @brief Define type of timer/shifter pin configuration.*/
+typedef enum _flexio_pin_config
+{
+    kFLEXIO_PinConfigOutputDisabled         = 0x0U, /*!< Pin output disabled. */
+    kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */
+    kFLEXIO_PinConfigBidirectionOutputData  = 0x2U, /*!< Pin bidirectional output data. */
+    kFLEXIO_PinConfigOutput                 = 0x3U, /*!< Pin output. */
+} flexio_pin_config_t;
+
+/*! @brief Definition of pin polarity.*/
+typedef enum _flexio_pin_polarity
+{
+    kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */
+    kFLEXIO_PinActiveLow  = 0x1U, /*!< Active low. */
+} flexio_pin_polarity_t;
+
+/*! @brief Define type of timer work mode.*/
+typedef enum _flexio_timer_mode
+{
+    kFLEXIO_TimerModeDisabled        = 0x0U, /*!< Timer Disabled. */
+    kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */
+    kFLEXIO_TimerModeDual8BitPWM     = 0x2U, /*!< Dual 8-bit counters PWM mode. */
+    kFLEXIO_TimerModeSingle16Bit     = 0x3U, /*!< Single 16-bit counter mode. */
+} flexio_timer_mode_t;
+
+/*! @brief Define type of timer initial output or timer reset condition.*/
+typedef enum _flexio_timer_output
+{
+    kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U,  /*!< Logic one when enabled and is not affected by timer
+                                                       reset. */
+    kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer
+                                                       reset. */
+    kFLEXIO_TimerOutputOneAffectedByReset  = 0x2U,    /*!< Logic one when enabled and on timer reset. */
+    kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U,    /*!< Logic zero when enabled and on timer reset. */
+} flexio_timer_output_t;
+
+/*! @brief Define type of timer decrement.*/
+typedef enum _flexio_timer_decrement_source
+{
+    kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock
+                                                              equals Timer output. */
+    kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput,       /*!< Decrement counter on Trigger input (both edges),
+                                                                     Shift clock equals Timer output. */
+    kFLEXIO_TimerDecSrcOnPinInputShiftPinInput,              /*!< Decrement counter on Pin input (both edges),
+                                                                     Shift clock equals Pin input. */
+    kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput       /*!< Decrement counter on Trigger input (both edges),
+                                                                     Shift clock equals Trigger input. */
+#if (defined(FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH) && (FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH == 3))
+    ,
+    kFLEXIO_TimerDecSrcDiv16OnFlexIOClockShiftTimerOutput,  /*!< Decrement counter on FlexIO clock divided by 16,
+                                                               Shift clock equals Timer output. */
+    kFLEXIO_TimerDecSrcDiv256OnFlexIOClockShiftTimerOutput, /*!< Decrement counter on FlexIO clock divided by 256,
+                                                                Shift clock equals Timer output. */
+    kFLEXIO_TimerRisSrcOnPinInputShiftPinInput,             /*!< Decrement counter on Pin input (rising edges),
+                                                                     Shift clock equals Pin input. */
+    kFLEXIO_TimerRisSrcOnTriggerInputShiftTriggerInput /*!< Decrement counter on Trigger input (rising edges), Shift
+                                                          clock equals Trigger input. */
+#endif                                                 /* FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH */
+} flexio_timer_decrement_source_t;
+
+/*! @brief Define type of timer reset condition.*/
+typedef enum _flexio_timer_reset_condition
+{
+    kFLEXIO_TimerResetNever                            = 0x0U, /*!< Timer never reset. */
+    kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput     = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */
+    kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to
+                                                                Timer Output. */
+    kFLEXIO_TimerResetOnTimerPinRisingEdge     = 0x4U,         /*!< Timer reset on Timer Pin rising edge. */
+    kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U,         /*!< Timer reset on Trigger rising edge. */
+    kFLEXIO_TimerResetOnTimerTriggerBothEdge   = 0x7U,         /*!< Timer reset on Trigger rising or falling edge. */
+} flexio_timer_reset_condition_t;
+
+/*! @brief Define type of timer disable condition.*/
+typedef enum _flexio_timer_disable_condition
+{
+    kFLEXIO_TimerDisableNever                    = 0x0U, /*!< Timer never disabled. */
+    kFLEXIO_TimerDisableOnPreTimerDisable        = 0x1U, /*!< Timer disabled on Timer N-1 disable. */
+    kFLEXIO_TimerDisableOnTimerCompare           = 0x2U, /*!< Timer disabled on Timer compare. */
+    kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */
+    kFLEXIO_TimerDisableOnPinBothEdge            = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */
+    kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided
+                                                          Trigger is high. */
+    kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U,     /*!< Timer disabled on Trigger falling edge. */
+} flexio_timer_disable_condition_t;
+
+/*! @brief Define type of timer enable condition.*/
+typedef enum _flexio_timer_enable_condition
+{
+    kFLEXIO_TimerEnabledAlways                    = 0x0U, /*!< Timer always enabled. */
+    kFLEXIO_TimerEnableOnPrevTimerEnable          = 0x1U, /*!< Timer enabled on Timer N-1 enable. */
+    kFLEXIO_TimerEnableOnTriggerHigh              = 0x2U, /*!< Timer enabled on Trigger high. */
+    kFLEXIO_TimerEnableOnTriggerHighPinHigh       = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */
+    kFLEXIO_TimerEnableOnPinRisingEdge            = 0x4U, /*!< Timer enabled on Pin rising edge. */
+    kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */
+    kFLEXIO_TimerEnableOnTriggerRisingEdge        = 0x6U, /*!< Timer enabled on Trigger rising edge. */
+    kFLEXIO_TimerEnableOnTriggerBothEdge          = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */
+} flexio_timer_enable_condition_t;
+
+/*! @brief Define type of timer stop bit generate condition.*/
+typedef enum _flexio_timer_stop_bit_condition
+{
+    kFLEXIO_TimerStopBitDisabled                    = 0x0U, /*!< Stop bit disabled. */
+    kFLEXIO_TimerStopBitEnableOnTimerCompare        = 0x1U, /*!< Stop bit is enabled on timer compare. */
+    kFLEXIO_TimerStopBitEnableOnTimerDisable        = 0x2U, /*!< Stop bit is enabled on timer disable. */
+    kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer
+                                                             disable. */
+} flexio_timer_stop_bit_condition_t;
+
+/*! @brief Define type of timer start bit generate condition.*/
+typedef enum _flexio_timer_start_bit_condition
+{
+    kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */
+    kFLEXIO_TimerStartBitEnabled  = 0x1U, /*!< Start bit enabled. */
+} flexio_timer_start_bit_condition_t;
+
+/*! @brief FlexIO as PWM channel output state */
+typedef enum _flexio_timer_output_state
+{
+    kFLEXIO_PwmLow = 0, /*!< The output state of PWM channel is low */
+    kFLEXIO_PwmHigh,    /*!< The output state of PWM channel is high */
+} flexio_timer_output_state_t;
+
+/*! @brief Define type of timer polarity for shifter control. */
+typedef enum _flexio_shifter_timer_polarity
+{
+    kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */
+    kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */
+} flexio_shifter_timer_polarity_t;
+
+/*! @brief Define type of shifter working mode.*/
+typedef enum _flexio_shifter_mode
+{
+    kFLEXIO_ShifterDisabled            = 0x0U, /*!< Shifter is disabled. */
+    kFLEXIO_ShifterModeReceive         = 0x1U, /*!< Receive mode. */
+    kFLEXIO_ShifterModeTransmit        = 0x2U, /*!< Transmit mode. */
+    kFLEXIO_ShifterModeMatchStore      = 0x4U, /*!< Match store mode. */
+    kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
+#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
+    kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
+                                      programmable state attributes. */
+#endif                               /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */
+#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
+    kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing
+                                     programmable logic look up table. */
+#endif                               /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */
+} flexio_shifter_mode_t;
+
+/*! @brief Define type of shifter input source.*/
+typedef enum _flexio_shifter_input_source
+{
+    kFLEXIO_ShifterInputFromPin               = 0x0U, /*!< Shifter input from pin. */
+    kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */
+} flexio_shifter_input_source_t;
+
+/*! @brief Define of STOP bit configuration.*/
+typedef enum _flexio_shifter_stop_bit
+{
+    kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */
+    kFLEXIO_ShifterStopBitLow     = 0x2U, /*!< Set shifter stop bit to logic low level. */
+    kFLEXIO_ShifterStopBitHigh    = 0x3U, /*!< Set shifter stop bit to logic high level. */
+} flexio_shifter_stop_bit_t;
+
+/*! @brief Define type of START bit configuration.*/
+typedef enum _flexio_shifter_start_bit
+{
+    kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads
+                                                             data on enable. */
+    kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U,  /*!< Disable shifter start bit, transmitter loads
+                                                             data on first shift. */
+    kFLEXIO_ShifterStartBitLow  = 0x2U,                     /*!< Set shifter start bit to logic low level. */
+    kFLEXIO_ShifterStartBitHigh = 0x3U,                     /*!< Set shifter start bit to logic high level. */
+} flexio_shifter_start_bit_t;
+
+/*! @brief Define FlexIO shifter buffer type*/
+typedef enum _flexio_shifter_buffer_type
+{
+    kFLEXIO_ShifterBuffer               = 0x0U, /*!< Shifter Buffer N Register. */
+    kFLEXIO_ShifterBufferBitSwapped     = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */
+    kFLEXIO_ShifterBufferByteSwapped    = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */
+    kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
+    kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */
+#endif                                             /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP
+    kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP
+    kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */
+#endif
+} flexio_shifter_buffer_type_t;
+
+/*! @brief Define FlexIO user configuration structure. */
+typedef struct _flexio_config_
+{
+    bool enableFlexio;     /*!< Enable/disable FlexIO module */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode */
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode */
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires
+                           the FlexIO clock to be at least twice the frequency of the bus clock. */
+} flexio_config_t;
+
+/*! @brief Define FlexIO timer configuration structure. */
+typedef struct _flexio_timer_config
+{
+    /* Trigger. */
+    uint32_t triggerSelect;                          /*!< The internal trigger selection number using MACROs. */
+    flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */
+    flexio_timer_trigger_source_t triggerSource;     /*!< Trigger Source, internal (see 'trgsel') or external. */
+    /* Pin. */
+    flexio_pin_config_t pinConfig;     /*!< Timer Pin Configuration. */
+    uint32_t pinSelect;                /*!< Timer Pin number Select. */
+    flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */
+    /* Timer. */
+    flexio_timer_mode_t timerMode;                  /*!< Timer work Mode. */
+    flexio_timer_output_t timerOutput;              /*!< Configures the initial state of the Timer Output and
+                                                    whether it is affected by the Timer reset. */
+    flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the
+                                                    source of the Shift clock. */
+    flexio_timer_reset_condition_t timerReset;      /*!< Configures the condition that causes the timer counter
+                                                    (and optionally the timer output) to be reset. */
+    flexio_timer_disable_condition_t timerDisable;  /*!< Configures the condition that causes the Timer to be
+                                                    disabled and stop decrementing. */
+    flexio_timer_enable_condition_t timerEnable;    /*!< Configures the condition that causes the Timer to be
+                                                    enabled and start decrementing. */
+    flexio_timer_stop_bit_condition_t timerStop;    /*!< Timer STOP Bit generation. */
+    flexio_timer_start_bit_condition_t timerStart;  /*!< Timer STRAT Bit generation. */
+    uint32_t timerCompare;                          /*!< Value for Timer Compare N Register. */
+} flexio_timer_config_t;
+
+/*! @brief Define FlexIO shifter configuration structure. */
+typedef struct _flexio_shifter_config
+{
+    /* Timer. */
+    uint32_t timerSelect;                          /*!< Selects which Timer is used for controlling the
+                                                    logic/shift register and generating the Shift clock. */
+    flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */
+    /* Pin. */
+    flexio_pin_config_t pinConfig;     /*!< Shifter Pin Configuration. */
+    uint32_t pinSelect;                /*!< Shifter Pin number Select. */
+    flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */
+    /* Shifter. */
+    flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+    uint32_t parallelWidth;                    /*!< Configures the parallel width when using parallel mode.*/
+#endif                                         /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
+    flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */
+    flexio_shifter_stop_bit_t shifterStop;     /*!< Shifter STOP bit. */
+    flexio_shifter_start_bit_t shifterStart;   /*!< Shifter START bit. */
+} flexio_shifter_config_t;
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+/*! @brief FLEXIO gpio direction definition */
+typedef enum _flexio_gpio_direction
+{
+    kFLEXIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} flexio_gpio_direction_t;
+
+/*! @brief FLEXIO gpio input config */
+typedef enum _flexio_pin_input_config
+{
+    kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */
+    kFLEXIO_InputInterruptEnable   = 0x1U, /*!< Interrupt request is enable. */
+    kFLEXIO_FlagRisingEdgeEnable   = 0x2U, /*!< Input pin flag on rising edge. */
+    kFLEXIO_FlagFallingEdgeEnable  = 0x4U, /*!< Input pin flag on falling edge. */
+} flexio_pin_input_config_t;
+
+/*!
+ * @brief The FLEXIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, use inputConfig param.
+ * If configured as an output pin, use outputLogic.
+ */
+typedef struct _flexio_gpio_config
+{
+    flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */
+    uint8_t outputLogic;                  /*!< Set a default output logic, which has no use in input */
+    uint8_t inputConfig;                  /*!< Set an input config */
+} flexio_gpio_config_t;
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
+
+/*! @brief typedef for FlexIO simulated driver interrupt handler.*/
+typedef void (*flexio_isr_t)(void *base, void *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to flexio bases for each instance. */
+extern FLEXIO_Type *const s_flexioBases[];
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to flexio clocks for each instance. */
+extern const clock_ip_name_t s_flexioClocks[];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name FlexIO Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can used directly to call the FLEXIO_Configure().
+ *
+ * Example:
+   @code
+   flexio_config_t config;
+   FLEXIO_GetDefaultConfig(&config);
+   @endcode
+ *
+ * @param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig);
+
+/*!
+ * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure
+ * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
+ *
+ * Example
+   @code
+   flexio_config_t config = {
+   .enableFlexio = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false
+   };
+   FLEXIO_Configure(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
+
+/*!
+ * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
+ *
+ * @note After calling this API, call the FLEXO_Init to use the FlexIO module.
+ *
+ * @param base FlexIO peripheral base address
+ */
+void FLEXIO_Deinit(FLEXIO_Type *base);
+
+/*!
+ * @brief Get instance number for FLEXIO module.
+ *
+ * @param base FLEXIO peripheral base address.
+ */
+uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
+
+/*! @} */
+
+/*!
+ * @name FlexIO Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Resets the FlexIO module.
+ *
+ * @param base FlexIO peripheral base address
+ */
+void FLEXIO_Reset(FLEXIO_Type *base);
+
+/*!
+ * @brief Enables the FlexIO module operation.
+ *
+ * @param base FlexIO peripheral base address
+ * @param enable true to enable, false to disable.
+ */
+static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+/*!
+ * @brief Reads the input data on each of the FlexIO pins.
+ *
+ * @param base FlexIO peripheral base address
+ * @return FlexIO pin input data
+ */
+static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
+{
+    return base->PIN;
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE
+/*!
+ * @brief Gets the current state pointer for state mode use.
+ *
+ * @param base FlexIO peripheral base address
+ * @return current State pointer
+ */
+static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)
+{
+    return ((uint8_t)(base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK);
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/
+
+/*!
+ * @brief Configures the shifter with the shifter configuration. The configuration structure
+ * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
+ * mode, select which timer controls the shifter to shift, whether to generate start bit/stop
+ *  bit, and the polarity of start bit and stop bit.
+ *
+ * Example
+   @code
+   flexio_shifter_config_t config = {
+   .timerSelect = 0,
+   .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinPolarity = kFLEXIO_PinActiveLow,
+   .shifterMode = kFLEXIO_ShifterModeTransmit,
+   .inputSource = kFLEXIO_ShifterInputFromPin,
+   .shifterStop = kFLEXIO_ShifterStopBitHigh,
+   .shifterStart = kFLEXIO_ShifterStartBitLow
+   };
+   FLEXIO_SetShifterConfig(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param index Shifter index
+ * @param shifterConfig Pointer to flexio_shifter_config_t structure
+*/
+void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig);
+/*!
+ * @brief Configures the timer with the timer configuration. The configuration structure
+ * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
+ * mode, select trigger source for timer and the timer pin output and the timing for timer.
+ *
+ * Example
+   @code
+   flexio_timer_config_t config = {
+   .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
+   .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
+   .triggerSource = kFLEXIO_TimerTriggerSourceInternal,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinSelect = 0,
+   .pinPolarity = kFLEXIO_PinActiveHigh,
+   .timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
+   .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
+   .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
+   .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
+   .timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
+   .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
+   .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
+   .timerStart = kFLEXIO_TimerStartBitEnabled
+   };
+   FLEXIO_SetTimerConfig(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param index Timer index
+ * @param timerConfig Pointer to the flexio_timer_config_t structure
+*/
+void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig);
+
+/*!
+ * @brief This function set the value of the prescaler on flexio channels
+ *
+ * @param base       Pointer to the FlexIO simulated peripheral type.
+ * @param index      Timer index
+ * @param clocksource  Set clock value
+ */
+static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)
+{
+    uint32_t reg = base->TIMCFG[index];
+
+    reg &= ~FLEXIO_TIMCFG_TIMDEC_MASK;
+
+    reg |= FLEXIO_TIMCFG_TIMDEC(clocksource);
+
+    base->TIMCFG[index] = reg;
+}
+
+/*! @} */
+
+/*!
+ * @name FlexIO Interrupt Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter status mask which can be calculated by (1 << shifter index)
+ * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSIEN |= mask;
+}
+
+/*!
+ * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter status mask which can be calculated by (1 << shifter index)
+ * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSIEN &= ~mask;
+}
+
+/*!
+ * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter error mask which can be calculated by (1 << shifter index)
+ * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTEIEN |= mask;
+}
+
+/*!
+ * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter error mask which can be calculated by (1 << shifter index)
+ * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTEIEN &= ~mask;
+}
+
+/*!
+ * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The timer status mask which can be calculated by (1 << timer index)
+ * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+ */
+static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMIEN |= mask;
+}
+
+/*!
+ * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The timer status mask which can be calculated by (1 << timer index)
+ * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+ */
+static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMIEN &= ~mask;
+}
+
+/*! @} */
+
+/*!
+ * @name FlexIO Status Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the shifter status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return Shifter status flags
+ */
+static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
+{
+    return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK);
+}
+
+/*!
+ * @brief Clears the shifter status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter status mask which can be calculated by (1 << shifter index)
+ * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSTAT = mask;
+}
+
+/*!
+ * @brief Gets the shifter error flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return Shifter error flags
+ */
+static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
+{
+    return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK);
+}
+
+/*!
+ * @brief Clears the shifter error flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter error mask which can be calculated by (1 << shifter index)
+ * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ */
+static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTERR = mask;
+}
+
+/*!
+ * @brief Gets the timer status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return Timer status flags
+ */
+static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
+{
+    return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK);
+}
+
+/*!
+ * @brief Clears the timer status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The timer status mask which can be calculated by (1 << timer index)
+ * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+ */
+static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMSTAT = mask;
+}
+
+/*! @} */
+
+/*!
+ * @name FlexIO DMA Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the shifter status DMA. The DMA request  generates when the corresponding SSF is set.
+ *
+ * @note For multiple shifter status DMA enables, for example, calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask The shifter status mask which can be calculated by (1 << shifter index)
+ * @param enable True to enable, false to disable.
+ */
+static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->SHIFTSDEN |= mask;
+    }
+    else
+    {
+        base->SHIFTSDEN &= ~mask;
+    }
+}
+
+/*!
+ * @brief Gets the shifter buffer address for the DMA transfer usage.
+ *
+ * @param base FlexIO peripheral base address
+ * @param type Shifter type of flexio_shifter_buffer_type_t
+ * @param index Shifter index
+ * @return Corresponding shifter buffer index
+ */
+uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index);
+
+/*!
+ * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * @param base Pointer to the FlexIO simulated peripheral type.
+ * @param handle Pointer to the handler for FlexIO simulated peripheral.
+ * @param isr FlexIO simulated peripheral interrupt handler.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
+
+/*!
+ * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * @param base Pointer to the FlexIO simulated peripheral type.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_UnregisterHandleIRQ(void *base);
+/*! @} */
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+
+/*!
+ * @brief Configure a FLEXIO pin used by the board.
+ *
+ * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FLEXIO_SetPinConfig() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * Define a digital input pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalInput,
+ *   0U,
+ *   kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
+ * }
+ * Define a digital output pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalOutput,
+ *   0U,
+ *   0U
+ * }
+ * @endcode
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @param config FLEXIO pin configuration pointer.
+ */
+void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config);
+
+/*!
+ * @name GPIO Output Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the multiple FLEXIO pins to the logic 0.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTCLR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FLEXIO pins to the logic 1.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTSET = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple FLEXIO pins.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTTOG = mask;
+}
+
+/*!
+ * @brief Sets the output level of the FLEXIO pins to the logic 1 or 0.
+ *
+ * @param base    FlexIO peripheral base address
+ * @param pin     FLEXIO pin number.
+ * @param output  FLEXIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        FLEXIO_ClearPortOutput(base, 1UL << pin);
+    }
+    else
+    {
+        FLEXIO_SetPortOutput(base, 1UL << pin);
+    }
+}
+
+/*!
+ * @brief Enables the FLEXIO output pin function.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ */
+static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)
+{
+    base->PINOUTE |= (1UL << pin);
+}
+/*! @} */
+
+/*!
+ * @name FLEXIO PIN Input Operations
+ * @{
+ */
+
+/*!
+ * @brief  Reads the current input value of the FLEXIO pin.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @retval FLEXIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)
+{
+    return (((base->PIN) >> pin) & 0x01U);
+}
+
+/*!
+ * @brief Gets the FLEXIO input pin status.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @retval FLEXIO port input status
+ *        - 0: corresponding pin input capture no status.
+ *        - 1: corresponding pin input capture rising or falling edge.
+ */
+static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)
+{
+    return (((base->PINSTAT) >> pin) & 0x01U);
+}
+
+/*!
+ * @brief Clears the multiple FLEXIO input pins status.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINSTAT = mask;
+}
+/*! @} */
+
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*! @} */
+
+#endif /*FSL_FLEXIO_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.c
new file mode 100644
index 0000000000..9239527c6f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.c
@@ -0,0 +1,1377 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_i2c_master.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master"
+#endif
+
+/*! @brief  FLEXIO I2C transfer state */
+enum _flexio_i2c_master_transfer_states
+{
+    kFLEXIO_I2C_Idle             = 0x0U, /*!< I2C bus idle */
+    kFLEXIO_I2C_Start            = 0x1U, /*!< I2C start phase */
+    kFLEXIO_I2C_SendCommand      = 0x2U, /*!< Send command byte phase */
+    kFLEXIO_I2C_SendData         = 0x3U, /*!< Send data transfer phase*/
+    kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
+    kFLEXIO_I2C_ReceiveData      = 0x5U, /*!< Receive data transfer phase*/
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Set up master transfer, send slave address and decide the initial
+ * transfer state.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param transfer pointer to flexio_i2c_master_transfer_t structure
+ */
+static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          flexio_i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Master run transfer state machine to perform a byte of transfer.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ * @retval kStatus_Success Successfully run state machine
+ * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer
+ */
+static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
+                                                         flexio_i2c_master_handle_t *handle,
+                                                         uint32_t statusFlags);
+
+/*!
+ * @brief Complete transfer, disable interrupt and call callback.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param status flexio transfer status
+ */
+static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              status_t status);
+
+/*!
+ * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineStart.
+ * This function was deal with Initial state, i2c start state.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ */
+static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle);
+
+/*!
+ * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendCommand.
+ * This function was deal with Check address only needed for transfer with subaddress .
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ *
+ * @return default is true when No abnormality.
+ * @return false when time out.
+ */
+static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base,
+                                                             flexio_i2c_master_handle_t *handle,
+                                                             uint32_t statusFlags);
+
+/*!
+ * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendData.
+ * This function was deal with Send command byte.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ *
+ * @return default is true when No abnormality.
+ * @return false when time out.
+ */
+static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          uint32_t statusFlags);
+
+/*!
+ * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin.
+ * This function was deal with Receive Data Begin.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ *
+ * @return default is true when No abnormality.
+ * @return false when time out.
+ */
+static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base,
+                                                                  flexio_i2c_master_handle_t *handle,
+                                                                  uint32_t statusFlags);
+
+/*!
+ * @brief introduce function Case_kFLEXIO_I2C_ReceiveDataBegin.
+ * This function was deal with Receive Data.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ *
+ * @return default is kStatus_Success when No abnormality.
+ * @return kStatus_FLEXIO_I2C_Nak when ReceiveNakFlag is not set.
+ * @return kStatus_FLEXIO_I2C_Timeout when time out.
+ */
+static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base,
+                                                                 flexio_i2c_master_handle_t *handle,
+                                                                 uint32_t statusFlags);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
+{
+    return FLEXIO_GetInstance(base->flexioBase);
+}
+
+static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          flexio_i2c_master_transfer_t *xfer)
+{
+    bool needRestart;
+    uint32_t byteCount;
+
+    /* Init the handle member. */
+    handle->transfer.slaveAddress   = xfer->slaveAddress;
+    handle->transfer.direction      = xfer->direction;
+    handle->transfer.subaddress     = xfer->subaddress;
+    handle->transfer.subaddressSize = xfer->subaddressSize;
+    handle->transfer.data           = xfer->data;
+    handle->transfer.dataSize       = xfer->dataSize;
+    handle->transfer.flags          = xfer->flags;
+    handle->transferSize            = xfer->dataSize;
+
+    /* Initial state, i2c start state. */
+    handle->state = (uint8_t)kFLEXIO_I2C_Start;
+
+    /* Clear all status before transfer. */
+    FLEXIO_I2C_MasterClearStatusFlags(base, (uint32_t)kFLEXIO_I2C_ReceiveNakFlag);
+
+    /* Calculate whether need to send re-start. */
+    needRestart         = (handle->transfer.subaddressSize != 0U) && (handle->transfer.direction == kFLEXIO_I2C_Read);
+    handle->needRestart = needRestart;
+
+    /* Calculate total byte count in a frame. */
+    byteCount = 1U;
+
+    if (!needRestart)
+    {
+        byteCount += handle->transfer.dataSize;
+    }
+
+    if (handle->transfer.subaddressSize != 0U)
+    {
+        byteCount += handle->transfer.subaddressSize;
+    }
+
+    /* Configure data count. */
+    if (FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)byteCount) != kStatus_Success)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure timer1 disable condition. */
+    uint32_t tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]];
+    tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPreTimerDisable);
+    base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig;
+
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) &&
+           (0U != --waitTimes))
+    {
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_FLEXIO_I2C_Timeout;
+    }
+#else
+    while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])))
+    {
+    }
+#endif
+
+    return kStatus_Success;
+}
+
+static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
+{
+    if (handle->needRestart)
+    {
+        FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write);
+    }
+    else
+    {
+        FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction);
+    }
+    if (handle->transfer.subaddressSize == 0U)
+    {
+        if (handle->transfer.direction == kFLEXIO_I2C_Write)
+        {
+            /* Next state, send data. */
+            handle->state = (uint8_t)kFLEXIO_I2C_SendData;
+        }
+        else
+        {
+            /* Next state, receive data begin. */
+            handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin;
+        }
+    }
+    else
+    {
+        /* Next state, send command byte. */
+        handle->state = (uint8_t)kFLEXIO_I2C_SendCommand;
+    }
+}
+
+static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base,
+                                                             flexio_i2c_master_handle_t *handle,
+                                                             uint32_t statusFlags)
+{
+    if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U)
+    {
+        if (handle->transfer.subaddressSize > 0U)
+        {
+            handle->transfer.subaddressSize--;
+            FLEXIO_I2C_MasterWriteByte(base, ((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)));
+
+            if (handle->transfer.subaddressSize == 0U)
+            {
+                /* Load re-start in advance. */
+                if (handle->transfer.direction == kFLEXIO_I2C_Read)
+                {
+#if I2C_RETRY_TIMES
+                    while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) &&
+                           (0U != --waitTimes))
+                    {
+                    }
+                    if (0U == waitTimes)
+                    {
+                        return false;
+                    }
+#else
+                    while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])))
+                    {
+                    }
+#endif
+                    FLEXIO_I2C_MasterRepeatedStart(base);
+                }
+            }
+        }
+        else
+        {
+            if (handle->transfer.direction == kFLEXIO_I2C_Write)
+            {
+                /* Send first byte of data. */
+                if (handle->transfer.dataSize > 0U)
+                {
+                    /* Next state, send data. */
+                    handle->state = (uint8_t)kFLEXIO_I2C_SendData;
+
+                    FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
+                    handle->transfer.data++;
+                    handle->transfer.dataSize--;
+                }
+                else
+                {
+                    FLEXIO_I2C_MasterStop(base);
+
+#if I2C_RETRY_TIMES
+                    while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) &&
+                           (0U != --waitTimes))
+                    {
+                    }
+                    if (0U == waitTimes)
+                    {
+                        return false;
+                    }
+#else
+                    while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag))
+                    {
+                    }
+#endif
+                    (void)FLEXIO_I2C_MasterReadByte(base);
+
+                    handle->state = (uint8_t)kFLEXIO_I2C_Idle;
+                }
+            }
+            else
+            {
+                (void)FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)(handle->transfer.dataSize + 1U));
+                /* Delay at least one clock cycle so that the restart setup time is up to spec standard. */
+                SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+                FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read);
+
+                /* Next state, receive data begin. */
+                handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin;
+            }
+        }
+    }
+    return true;
+}
+
+static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          uint32_t statusFlags)
+{
+    if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U)
+    {
+        /* Send one byte of data. */
+        if (handle->transfer.dataSize > 0U)
+        {
+            FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
+
+            handle->transfer.data++;
+            handle->transfer.dataSize--;
+        }
+        else
+        {
+            FLEXIO_I2C_MasterStop(base);
+
+#if I2C_RETRY_TIMES
+            while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) &&
+                   (0U != --waitTimes))
+            {
+            }
+            if (0U == waitTimes)
+            {
+                return false;
+            }
+#else
+            while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag))
+            {
+            }
+#endif
+            (void)FLEXIO_I2C_MasterReadByte(base);
+
+            handle->state = (uint8_t)kFLEXIO_I2C_Idle;
+        }
+    }
+    return true;
+}
+
+static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base,
+                                                                  flexio_i2c_master_handle_t *handle,
+                                                                  uint32_t statusFlags)
+{
+    if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U)
+    {
+        handle->state = (uint8_t)kFLEXIO_I2C_ReceiveData;
+        /* Send nak at the last receive byte. */
+        if (handle->transfer.dataSize == 1U)
+        {
+            FLEXIO_I2C_MasterEnableAck(base, false);
+#if I2C_RETRY_TIMES
+            while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) &&
+                   (0U != --waitTimes))
+            {
+            }
+            if (0U == waitTimes)
+            {
+                return false;
+            }
+#else
+            while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])))
+            {
+            }
+#endif
+            FLEXIO_I2C_MasterStop(base);
+        }
+        else
+        {
+            FLEXIO_I2C_MasterEnableAck(base, true);
+        }
+    }
+    else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U)
+    {
+        /* Read one byte of data. */
+        FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+    }
+    else
+    {
+        ; /* Avoid MISRA 2012 rule 15.7 */
+    }
+    return true;
+}
+
+static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base,
+                                                                 flexio_i2c_master_handle_t *handle,
+                                                                 uint32_t statusFlags)
+{
+    if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U)
+    {
+        *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base);
+        handle->transfer.data++;
+        if (0U != handle->transfer.dataSize--)
+        {
+            if (handle->transfer.dataSize == 0U)
+            {
+                FLEXIO_I2C_MasterDisableInterrupts(base, (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable);
+                handle->state = (uint8_t)kFLEXIO_I2C_Idle;
+                /* Return nak if ReceiveNakFlag is not set */
+                if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) == 0U)
+                {
+                    return kStatus_FLEXIO_I2C_Nak;
+                }
+            }
+
+            /* Send nak at the last receive byte. */
+            if (handle->transfer.dataSize == 1U)
+            {
+                FLEXIO_I2C_MasterEnableAck(base, false);
+#if I2C_RETRY_TIMES
+                while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) &&
+                       (0U != --waitTimes))
+                {
+                }
+                if (0U == waitTimes)
+                {
+                    return kStatus_FLEXIO_I2C_Timeout;
+                }
+#else
+                while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])))
+                {
+                }
+#endif
+                FLEXIO_I2C_MasterStop(base);
+            }
+        }
+    }
+    else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U)
+    {
+        if (handle->transfer.dataSize > 1U)
+        {
+            FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+        }
+    }
+    else
+    {
+        ; /* Avoid MISRA 2012 rule 15.7 */
+    }
+    return kStatus_Success;
+}
+
+static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
+                                                         flexio_i2c_master_handle_t *handle,
+                                                         uint32_t statusFlags)
+{
+    status_t status;
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U)
+    {
+        /* Clear receive nak flag. */
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+
+        if ((!((handle->state == (uint8_t)kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) &&
+            (!(((handle->state == (uint8_t)kFLEXIO_I2C_ReceiveData) ||
+                (handle->state == (uint8_t)kFLEXIO_I2C_ReceiveDataBegin)) &&
+               (handle->transfer.dataSize == 1U))))
+        {
+            (void)FLEXIO_I2C_MasterReadByte(base);
+
+            FLEXIO_I2C_MasterAbortStop(base);
+
+            /* Delay one clk cycle to ensure the bus is idle. */
+            SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+            handle->state = (uint8_t)kFLEXIO_I2C_Idle;
+
+            return kStatus_FLEXIO_I2C_Nak;
+        }
+    }
+
+    if (((statusFlags & (uint8_t)kFLEXIO_I2C_RxFullFlag) != 0U) && (handle->state != (uint8_t)kFLEXIO_I2C_ReceiveData))
+    {
+        (void)FLEXIO_I2C_MasterReadByte(base);
+    }
+
+    switch (handle->state)
+    {
+        /* Initial state, i2c start state. */
+        case (uint8_t)kFLEXIO_I2C_Start:
+            /* Send address byte first. */
+            FLEXIO_I2C_MasterTransferStateMachineStart(base, handle);
+            break;
+
+        /* Check address only needed for transfer with subaddress */
+        case (uint8_t)kFLEXIO_I2C_SendCommand:
+            if (false == FLEXIO_I2C_MasterTransferStateMachineSendCommand(base, handle, statusFlags))
+            {
+                return kStatus_FLEXIO_I2C_Timeout;
+            }
+            break;
+
+        /* Send command byte. */
+        case (uint8_t)kFLEXIO_I2C_SendData:
+            if (false == FLEXIO_I2C_MasterTransferStateMachineSendData(base, handle, statusFlags))
+            {
+                return kStatus_FLEXIO_I2C_Timeout;
+            }
+            break;
+
+        case (uint8_t)kFLEXIO_I2C_ReceiveDataBegin:
+            if (false == FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(base, handle, statusFlags))
+            {
+                return kStatus_FLEXIO_I2C_Timeout;
+            }
+            break;
+
+        case (uint8_t)kFLEXIO_I2C_ReceiveData:
+            status = FLEXIO_I2C_MasterTransferStateMachineReceiveData(base, handle, statusFlags);
+            if (kStatus_Success != status)
+            {
+                return status;
+            }
+            break;
+
+        default:
+            /* Add comment to avoid MISRA violation */
+            break;
+    }
+
+    return kStatus_Success;
+}
+
+static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              status_t status)
+{
+    FLEXIO_I2C_MasterDisableInterrupts(
+        base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable);
+
+    if (handle->completionCallback != NULL)
+    {
+        handle->completionCallback(base, handle, status, handle->userData);
+    }
+}
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+/*!
+ * brief Make sure the bus isn't already pulled down.
+ *
+ * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * retval kStatus_Success
+ * retval kStatus_FLEXIO_I2C_Busy
+ */
+status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)
+{
+    uint32_t mask;
+    /* If in certain loops the SDA/SCL is continuously pulled down, then return bus busy status. */
+    /* The loop count is determined by maximum CPU clock frequency */
+    for (uint32_t i = 0U; i < SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 600000U; ++i)
+    {
+        mask = 1UL << base->SDAPinIndex | 1UL << base->SCLPinIndex;
+        if ((FLEXIO_ReadPinInput(base->flexioBase) & mask) == mask)
+        {
+            return kStatus_Success;
+        }
+    }
+    return kStatus_FLEXIO_I2C_Busy;
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
+ * hardware configuration.
+ *
+ * Example
+   code
+   FLEXIO_I2C_Type base = {
+   .flexioBase = FLEXIO,
+   .SDAPinIndex = 0,
+   .SCLPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_i2c_master_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 100000
+   };
+   FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param masterConfig Pointer to flexio_i2c_master_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+ * retval kStatus_Success Initialization successful
+ * retval kStatus_InvalidArgument The source clock exceed upper range limitation
+*/
+status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert((base != NULL) && (masterConfig != NULL));
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t controlVal = 0;
+    uint16_t timerDiv   = 0;
+    status_t result     = kStatus_Success;
+
+    (void)memset(&shifterConfig, 0, sizeof(shifterConfig));
+    (void)memset(&timerConfig, 0, sizeof(timerConfig));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect   = base->timerIndex[2];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    shifterConfig.pinSelect     = base->SDAPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveLow;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect   = base->timerIndex[2];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect     = base->SDAPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitLow;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 and timer 1 for generating bit clock. */
+    /* timer 1 is used to config baudrate */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    timerConfig.pinSelect       = base->SCLPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+
+    /* Set TIMCMP = (baud rate divider / 2) - 1. */
+    timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps) / 2U - 1U;
+    /* Calculate and assign the actual baudrate. */
+    base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U));
+
+    timerConfig.timerCompare = timerDiv;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+
+    /* timer 0 is used to config total shift clock edges */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->SCLPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+
+    /* Set TIMCMP when confinguring transfer bytes. */
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 4. Configure the timer 2 for controlling shifters. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->SCLPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerCompare;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+
+    /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
+    timerConfig.timerCompare = 8U * 2U - 1U;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[2], &timerConfig);
+
+    /* Configure FLEXIO I2C Master. */
+    controlVal = base->flexioBase->CTRL;
+    controlVal &=
+        ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
+                   FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
+    if (!masterConfig->enableInDoze)
+    {
+        controlVal |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+
+    base->flexioBase->CTRL = controlVal;
+    /* Disable internal IRQs. */
+    FLEXIO_I2C_MasterDisableInterrupts(
+        base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable);
+    return result;
+}
+
+/*!
+ * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master
+ * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called.
+ *
+ * param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
+{
+    base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[2]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[2]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[2]]     = 0;
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]);
+    base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]);
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]);
+    base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]);
+    base->flexioBase->TIMSTAT = (1UL << base->timerIndex[2]);
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can be used directly for calling the FLEXIO_I2C_MasterInit().
+ *
+ * Example:
+   code
+   flexio_i2c_master_config_t config;
+   FLEXIO_I2C_MasterGetDefaultConfig(&config);
+   endcode
+ * param masterConfig Pointer to flexio_i2c_master_config_t structure.
+*/
+void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
+{
+    assert(masterConfig != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->enableMaster     = true;
+    masterConfig->enableInDoze     = false;
+    masterConfig->enableInDebug    = true;
+    masterConfig->enableFastAccess = false;
+
+    /* Default baud rate at 100kbps. */
+    masterConfig->baudRate_Bps = 100000U;
+}
+
+/*!
+ * brief Gets the FlexIO I2C master status flags.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
+ */
+
+uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
+{
+    uint32_t status = 0;
+
+    status =
+        ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 1U);
+    status |=
+        (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 2U);
+
+    return status;
+}
+
+/*!
+ * brief Clears the FlexIO I2C master status flags.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_I2C_RxFullFlag
+ *          arg kFLEXIO_I2C_ReceiveNakFlag
+ */
+
+void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+
+    if ((mask & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+
+    if ((mask & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U)
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Enables the FlexIO i2c master interrupt requests.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Interrupt source.
+ *     Currently only one interrupt request source:
+ *     arg kFLEXIO_I2C_TransferCompleteInterruptEnable
+ */
+void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Disables the FlexIO I2C master interrupt requests.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Interrupt source.
+ */
+void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Sets the FlexIO I2C master transfer baudrate.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param baudRate_Bps the baud rate value in HZ
+ * param srcClock_Hz source clock in HZ
+ */
+void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint16_t timerDiv       = 0;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Set TIMCMP = (baud rate divider / 2) - 1.*/
+    timerDiv = (uint16_t)((srcClock_Hz / baudRate_Bps) / 2U - 1U);
+
+    flexioBase->TIMCMP[base->timerIndex[1]] = timerDiv;
+
+    /* Calculate and assign the actual baudrate. */
+    base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U));
+}
+
+/*!
+ * brief Sets the number of bytes to be transferred from a start signal to a stop signal.
+ *
+ * note Call this API before a transfer begins because the timer generates a number of clocks according
+ * to the number of bytes that need to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
+ * retval kStatus_Success Successfully configured the count.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)
+{
+    /* Calculate whether the transfer count is larger than the max value compare register can achieve */
+    if (count > ((0xFFFFUL - 1UL) / (16UL + 1UL + 1UL)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint32_t timerConfig    = 0U;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    flexioBase->TIMCMP[base->timerIndex[0]] = (uint32_t)count * 18U + 1U;
+    timerConfig                             = flexioBase->TIMCFG[base->timerIndex[0]];
+    timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+    flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Sends START + 7-bit address to the bus.
+ *
+ * note This API should be called when the transfer configuration is ready to send a START signal
+ * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
+ * is put into the data register but the address transfer is not finished on the bus. Ensure that
+ * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param address 7-bit address.
+ * param direction transfer direction.
+ *     This parameter is one of the values in flexio_i2c_direction_t:
+ *        arg kFLEXIO_I2C_Write: Transmit
+ *        arg kFLEXIO_I2C_Read:  Receive
+ */
+
+void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
+{
+    uint32_t data;
+
+    data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U);
+
+    FLEXIO_I2C_MasterWriteByte(base, data);
+}
+
+/*!
+ * brief Sends the repeated start signal on the bus.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
+{
+    /* Prepare for RESTART condition, no stop.*/
+    FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+}
+
+/*!
+ * brief Sends the stop signal on the bus.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
+{
+    /* Prepare normal stop. */
+    (void)FLEXIO_I2C_MasterSetTransferCount(base, 0x0U);
+    FLEXIO_I2C_MasterWriteByte(base, 0x0U);
+}
+
+/*!
+ * brief Sends the stop signal when transfer is still on-going.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
+{
+    uint32_t tmpConfig;
+
+    /* Prepare abort stop. */
+    /* Disable timer 0. */
+    tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]];
+    tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
+    base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
+
+    /* Disable timer 1. */
+    tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]];
+    tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
+    base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig;
+}
+
+/*!
+ * brief Configures the sent ACK/NAK for the following byte.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param enable True to configure send ACK, false configure to send NAK.
+ */
+void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
+{
+    uint32_t tmpConfig = 0;
+
+    tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]];
+    tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK;
+    if (enable)
+    {
+        tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow);
+    }
+    else
+    {
+        tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh);
+    }
+    base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
+}
+
+/*!
+ * brief Sends a buffer of data in bytes.
+ *
+ * note This function blocks via polling until all bytes have been sent.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param txBuff The data bytes to send.
+ * param txSize The number of data bytes to send.
+ * retval kStatus_Success Successfully write data.
+ * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
+ * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
+{
+    assert(txBuff != NULL);
+    assert(txSize != 0U);
+
+    uint32_t status;
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    while (0U != txSize--)
+    {
+        FLEXIO_I2C_MasterWriteByte(base, *txBuff++);
+
+        /* Wait until data transfer complete. */
+#if I2C_RETRY_TIMES
+        waitTimes = I2C_RETRY_TIMES;
+        while ((0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) &&
+               (0U != --waitTimes))
+        {
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_FLEXIO_I2C_Timeout;
+        }
+#else
+        while (0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag))
+        {
+        }
+#endif
+
+        if ((status & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U)
+        {
+            FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+            return kStatus_FLEXIO_I2C_Nak;
+        }
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks via polling until all bytes have been received.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param rxBuff The buffer to store the received bytes.
+ * param rxSize The number of data bytes to be received.
+ * retval kStatus_Success Successfully read data.
+ * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
+{
+    assert(rxBuff != NULL);
+    assert(rxSize != 0U);
+
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    while (0U != rxSize--)
+    {
+        /* Wait until data transfer complete. */
+#if I2C_RETRY_TIMES
+        waitTimes = I2C_RETRY_TIMES;
+        while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) &&
+               (0U != --waitTimes))
+        {
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_FLEXIO_I2C_Timeout;
+        }
+#else
+        while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag))
+        {
+        }
+#endif
+        *rxBuff++ = FLEXIO_I2C_MasterReadByte(base);
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a master polling transfer on the I2C bus.
+ *
+ * note The API does not return until the transfer succeeds or fails due
+ * to receiving NAK.
+ *
+ * param base pointer to FLEXIO_I2C_Type structure.
+ * param xfer pointer to flexio_i2c_master_transfer_t structure.
+ * return status of status_t.
+ */
+status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
+{
+    assert(xfer != NULL);
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+    /* Return an error if the bus is already in use not by us.*/
+    status_t status = FLEXIO_I2C_CheckForBusyBus(base);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+    flexio_i2c_master_handle_t tmpHandle;
+    uint32_t statusFlags;
+    status_t result = kStatus_Success;
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    /* Zero the handle. */
+    (void)memset(&tmpHandle, 0, sizeof(tmpHandle));
+
+    /* Set up transfer machine. */
+    result = FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    do
+    {
+        /* Wait either tx empty or rx full flag is asserted. */
+#if I2C_RETRY_TIMES
+        waitTimes = I2C_RETRY_TIMES;
+        while ((0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) &
+                       ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag))) &&
+               (0U != --waitTimes))
+        {
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_FLEXIO_I2C_Timeout;
+        }
+#else
+        while (0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) &
+                      ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag)))
+        {
+        }
+#endif
+        FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1UL << base->timerIndex[0]) | (1UL << base->timerIndex[1])));
+        result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
+
+    } while ((tmpHandle.state != (uint8_t)kFLEXIO_I2C_Idle) && (result == kStatus_Success));
+
+    /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent.
+     */
+    while (0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1UL << base->timerIndex[1])))
+    {
+    }
+
+    return result;
+}
+
+/*!
+ * brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
+ * param callback Pointer to user callback function.
+ * param userData User param passed to the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
+ */
+status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
+                                               flexio_i2c_master_handle_t *handle,
+                                               flexio_i2c_master_transfer_callback_t callback,
+                                               void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+    /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+    NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
+    (void)EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
+}
+
+/*!
+ * brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * note The API returns immediately after the transfer initiates.
+ * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
+ * is finished.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * param xfer pointer to flexio_i2c_master_transfer_t structure
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
+ */
+status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              flexio_i2c_master_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    status_t result = kStatus_Success;
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+    /* Return an error if the bus is already in use not by us.*/
+    result = FLEXIO_I2C_CheckForBusyBus(base);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+    if (handle->state != (uint8_t)kFLEXIO_I2C_Idle)
+    {
+        return kStatus_FLEXIO_I2C_Busy;
+    }
+    else
+    {
+        /* Set up transfer machine. */
+        result = FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        /* Enable both tx empty and rxfull interrupt. */
+        FLEXIO_I2C_MasterEnableInterrupts(
+            base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable);
+
+        return kStatus_Success;
+    }
+}
+
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable interrupts. */
+    FLEXIO_I2C_MasterDisableInterrupts(
+        base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable);
+
+    /* Reset to idle state. */
+    handle->state = (uint8_t)kFLEXIO_I2C_Idle;
+}
+
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
+{
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == (uint8_t)kFLEXIO_I2C_Idle)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferSize - handle->transfer.dataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Master interrupt handler.
+ *
+ * param i2cType Pointer to FLEXIO_I2C_Type structure
+ * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure
+ */
+void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
+{
+    FLEXIO_I2C_Type *base              = (FLEXIO_I2C_Type *)i2cType;
+    flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
+    uint32_t statusFlags;
+    status_t result;
+
+    statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base);
+
+    result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags);
+
+    if (handle->state == (uint8_t)kFLEXIO_I2C_Idle)
+    {
+        FLEXIO_I2C_MasterTransferComplete(base, handle, result);
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.h
new file mode 100644
index 0000000000..6b33abe22c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2c_master.h
@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_I2C_MASTER_H_
+#define FSL_FLEXIO_I2C_MASTER_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_i2c_master
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef I2C_RETRY_TIMES
+#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief FlexIO I2C transfer status*/
+enum
+{
+    kStatus_FLEXIO_I2C_Busy    = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */
+    kStatus_FLEXIO_I2C_Idle    = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */
+    kStatus_FLEXIO_I2C_Nak     = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */
+    kStatus_FLEXIO_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 3), /*!< Timeout polling status flags. */
+};
+
+/*! @brief Define FlexIO I2C master interrupt mask. */
+enum _flexio_i2c_master_interrupt
+{
+    kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */
+    kFLEXIO_I2C_RxFullInterruptEnable  = 0x2U, /*!< Rx buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO I2C master status mask. */
+enum _flexio_i2c_master_status_flags
+{
+    kFLEXIO_I2C_TxEmptyFlag    = 0x1U, /*!< Tx shifter empty flag. */
+    kFLEXIO_I2C_RxFullFlag     = 0x2U, /*!< Rx shifter full/Transfer complete flag. */
+    kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */
+};
+
+/*! @brief Direction of master transfer.*/
+typedef enum _flexio_i2c_direction
+{
+    kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */
+    kFLEXIO_I2C_Read  = 0x1U, /*!< Master receive from slave. */
+} flexio_i2c_direction_t;
+
+/*! @brief Define FlexIO I2C master access structure typedef. */
+typedef struct _flexio_i2c_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t SDAPinIndex;     /*!< Pin select for I2C SDA. */
+    uint8_t SCLPinIndex;     /*!< Pin select for I2C SCL. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */
+    uint8_t timerIndex[3];   /*!< Timer index used in FlexIO I2C. */
+    uint32_t baudrate;       /*!< Master transfer baudrate, used to calculate delay time. */
+} FLEXIO_I2C_Type;
+
+/*! @brief Define FlexIO I2C master user configuration structure. */
+typedef struct _flexio_i2c_master_config
+{
+    bool enableMaster;     /*!< Enables the FlexIO I2C peripheral at initialization time. */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires
+                           the FlexIO clock to be at least twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
+} flexio_i2c_master_config_t;
+
+/*! @brief Define FlexIO I2C master transfer structure. */
+typedef struct _flexio_i2c_master_transfer
+{
+    uint32_t flags;                   /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */
+    uint8_t slaveAddress;             /*!< 7-bit slave address. */
+    flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */
+    uint32_t subaddress;              /*!< Sub address. Transferred MSB first. */
+    uint8_t subaddressSize;           /*!< Size of command buffer. */
+    uint8_t volatile *data;           /*!< Transfer buffer. */
+    volatile size_t dataSize;         /*!< Transfer size. */
+} flexio_i2c_master_transfer_t;
+
+/*! @brief FlexIO I2C master handle typedef. */
+typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t;
+
+/*! @brief FlexIO I2C master transfer callback typedef. */
+typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base,
+                                                      flexio_i2c_master_handle_t *handle,
+                                                      status_t status,
+                                                      void *userData);
+
+/*! @brief Define FlexIO I2C master handle structure. */
+struct _flexio_i2c_master_handle
+{
+    flexio_i2c_master_transfer_t transfer;                    /*!< FlexIO I2C master transfer copy. */
+    size_t transferSize;                                      /*!< Total bytes to be transferred. */
+    uint8_t state;                                            /*!< Transfer state maintained during transfer. */
+    flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */
+                                                              /*!< Callback function called at transfer event. */
+    void *userData;                                           /*!< Callback parameter passed to callback function. */
+    bool needRestart;                                         /*!< Whether master needs to send re-start signal. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+/*!
+ * @brief Make sure the bus isn't already pulled down.
+ *
+ * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure..
+ * @retval kStatus_Success
+ * @retval kStatus_FLEXIO_I2C_Busy
+ */
+status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base);
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
+ * hardware configuration.
+ *
+ * Example
+   @code
+   FLEXIO_I2C_Type base = {
+   .flexioBase = FLEXIO,
+   .SDAPinIndex = 0,
+   .SCLPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_i2c_master_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 100000
+   };
+   FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param masterConfig Pointer to flexio_i2c_master_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+ * @retval kStatus_Success Initialization successful
+ * @retval kStatus_InvalidArgument The source clock exceed upper range limitation
+*/
+status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master
+ * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can be used directly for calling the FLEXIO_I2C_MasterInit().
+ *
+ * Example:
+   @code
+   flexio_i2c_master_config_t config;
+   FLEXIO_I2C_MasterGetDefaultConfig(&config);
+   @endcode
+ * @param masterConfig Pointer to flexio_i2c_master_config_t structure.
+*/
+void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Enables/disables the FlexIO module operation.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param enable Pass true to enable module, false does not have any effect.
+ */
+static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO I2C master status flags.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure
+ * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
+ */
+
+uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Clears the FlexIO I2C master status flags.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_I2C_RxFullFlag
+ *          @arg kFLEXIO_I2C_ReceiveNakFlag
+ */
+
+void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO i2c master interrupt requests.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param mask Interrupt source.
+ *     Currently only one interrupt request source:
+ *     @arg kFLEXIO_I2C_TransferCompleteInterruptEnable
+ */
+void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO I2C master interrupt requests.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param mask Interrupt source.
+ */
+void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the FlexIO I2C master transfer baudrate.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure
+ * @param baudRate_Bps the baud rate value in HZ
+ * @param srcClock_Hz source clock in HZ
+ */
+void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sends START + 7-bit address to the bus.
+ *
+ * @note This API should be called when the transfer configuration is ready to send a START signal
+ * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
+ * is put into the data register but the address transfer is not finished on the bus. Ensure that
+ * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param address 7-bit address.
+ * @param direction transfer direction.
+ *     This parameter is one of the values in flexio_i2c_direction_t:
+ *        @arg kFLEXIO_I2C_Write: Transmit
+ *        @arg kFLEXIO_I2C_Read:  Receive
+ */
+
+void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction);
+
+/*!
+ * @brief Sends the stop signal on the bus.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Sends the repeated start signal on the bus.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Sends the stop signal when transfer is still on-going.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Configures the sent ACK/NAK for the following byte.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param enable True to configure send ACK, false configure to send NAK.
+ */
+void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable);
+
+/*!
+ * @brief Sets the number of bytes to be transferred from a start signal to a stop signal.
+ *
+ * @note Call this API before a transfer begins because the timer generates a number of clocks according
+ * to the number of bytes that need to be transferred.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
+ * @retval kStatus_Success Successfully configured the count.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count);
+
+/*!
+ * @brief Writes one byte of data to the I2C bus.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register but the data transfer is not finished on the bus. Ensure that
+ * the TxEmptyFlag is asserted before calling this API.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param data a byte of data.
+ */
+static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)
+{
+    base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
+}
+
+/*!
+ * @brief Reads one byte of data from the I2C bus.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the data is ready in the register.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @return data byte read.
+ */
+static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)
+{
+    return (uint8_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
+}
+
+/*!
+ * @brief Sends a buffer of data in bytes.
+ *
+ * @note This function blocks via polling until all bytes have been sent.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param txBuff The data bytes to send.
+ * @param txSize The number of data bytes to send.
+ * @retval kStatus_Success Successfully write data.
+ * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
+ * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks via polling until all bytes have been received.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param rxBuff The buffer to store the received bytes.
+ * @param rxSize The number of data bytes to be received.
+ * @retval kStatus_Success Successfully read data.
+ * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to receiving NAK.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param xfer pointer to flexio_i2c_master_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer);
+/*! @} */
+
+/*Transactional APIs*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
+ * @param callback Pointer to user callback function.
+ * @param userData User param passed to the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
+ */
+status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
+                                               flexio_i2c_master_handle_t *handle,
+                                               flexio_i2c_master_transfer_callback_t callback,
+                                               void *userData);
+
+/*!
+ * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * @note The API returns immediately after the transfer initiates.
+ * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
+ * is finished.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure
+ * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to flexio_i2c_master_transfer_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
+ */
+status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              flexio_i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure.
+ * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base Pointer to FLEXIO_I2C_Type structure
+ * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param i2cType Pointer to FLEXIO_I2C_Type structure
+ * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure
+ */
+void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*! @} */
+
+#endif /*FSL_FLEXIO_I2C_MASTER_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.c
new file mode 100644
index 0000000000..087e0d691d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.c
@@ -0,0 +1,903 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_i2s.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+/*!@brief _sai_transfer_state*/
+enum
+{
+    kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
+    kFLEXIO_I2S_Idle,        /*!< Transfer is done. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Receive a piece of data in non-blocking way.
+ *
+ * @param base FLEXIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
+
+/*!
+ * @brief sends a piece of data in non-blocking way.
+ *
+ * @param base FLEXIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
+{
+    return FLEXIO_GetInstance(base->flexioBase);
+}
+
+static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
+{
+    uint32_t i           = 0;
+    uint8_t j            = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data        = 0;
+    uint32_t temp        = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        for (j = 0; j < bytesPerWord; j++)
+        {
+            temp = (uint32_t)(*txData);
+            data |= (temp << (8U * j));
+            txData++;
+        }
+        base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth);
+        data                                                = 0;
+    }
+}
+
+static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
+{
+    uint32_t i           = 0;
+    uint8_t j            = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data        = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]);
+        for (j = 0; j < bytesPerWord; j++)
+        {
+            *rxData = (uint8_t)((data >> (8U * j)) & 0xFFU);
+            rxData++;
+        }
+    }
+}
+
+/*!
+ * brief Initializes the FlexIO I2S.
+ *
+ * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure.
+ * The configuration structure can be filled by the user, or be set with default values by
+ * FLEXIO_I2S_GetDefaultConfig().
+ *
+ * note  This API should be called at the beginning of the application to use
+ * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault
+ * because the clock is not enabled.
+ *
+ * param base FlexIO I2S base pointer
+ * param config FlexIO I2S configure structure.
+ */
+void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
+{
+    assert((base != NULL) && (config != NULL));
+
+    flexio_shifter_config_t shifterConfig = {0};
+    flexio_timer_config_t timerConfig     = {0};
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* reset Flexio */
+    FLEXIO_Reset(base->flexioBase);
+
+    /* Set shifter for I2S Tx data */
+    shifterConfig.timerSelect   = base->bclkTimerIndex;
+    shifterConfig.pinSelect     = base->txPinIndex;
+    shifterConfig.timerPolarity = config->txTimerPolarity;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinPolarity   = config->txPinPolarity;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+    else
+    {
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
+
+    /* Set shifter for I2S Rx Data */
+    shifterConfig.timerSelect   = base->bclkTimerIndex;
+    shifterConfig.pinSelect     = base->rxPinIndex;
+    shifterConfig.timerPolarity = config->rxTimerPolarity;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinPolarity   = config->rxPinPolarity;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
+
+    /* Set Timer to I2S frame sync */
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceExternal;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+        timerConfig.pinSelect       = base->fsPinIndex;
+        timerConfig.pinPolarity     = config->fsPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    }
+    else
+    {
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinSelect       = base->fsPinIndex;
+        timerConfig.pinPolarity     = config->fsPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdge;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    }
+    FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
+
+    /* Set Timer to I2S bit clock */
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect       = base->bclkPinIndex;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+        timerConfig.pinPolarity     = config->bclkPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    }
+    else
+    {
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect       = base->bclkPinIndex;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinPolarity     = config->bclkPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    }
+    FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
+
+    /* If enable flexio I2S */
+    if (config->enableI2S)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*!
+ * brief  Sets the FlexIO I2S configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
+ * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify
+ * some fields of the structure before calling FLEXIO_I2S_Init().
+ *
+ * param config pointer to master configuration structure
+ */
+void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->masterSlave     = kFLEXIO_I2S_Master;
+    config->enableI2S       = true;
+    config->txPinPolarity   = kFLEXIO_PinActiveHigh;
+    config->rxPinPolarity   = kFLEXIO_PinActiveHigh;
+    config->bclkPinPolarity = kFLEXIO_PinActiveHigh;
+    config->fsPinPolarity   = kFLEXIO_PinActiveLow;
+    config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+}
+
+/*!
+ * brief De-initializes the FlexIO I2S.
+ *
+ * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API,
+ * call the FLEXO_I2S_Init to use the FlexIO I2S module.
+ *
+ * param base FlexIO I2S base pointer
+ */
+void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
+{
+    base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
+    base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0;
+    base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0;
+    base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0;
+    base->flexioBase->TIMCFG[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCMP[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCTL[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCFG[base->bclkTimerIndex]   = 0;
+    base->flexioBase->TIMCMP[base->bclkTimerIndex]   = 0;
+    base->flexioBase->TIMCTL[base->bclkTimerIndex]   = 0;
+}
+
+/*!
+ * brief Enables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param mask interrupt source
+ */
+void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) != 0UL)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->txShifterIndex);
+    }
+    if ((mask & (uint32_t)kFLEXIO_I2S_RxDataRegFullInterruptEnable) != 0UL)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->rxShifterIndex);
+    }
+}
+
+/*!
+ * brief Gets the FlexIO I2S status flags.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
+ */
+uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
+{
+    uint32_t status = 0;
+    status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->txShifterIndex)) >> base->txShifterIndex);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->rxShifterIndex)) >> (base->rxShifterIndex))
+         << 1U);
+    return status;
+}
+
+/*!
+ * brief Disables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base pointer to FLEXIO_I2S_Type structure
+ * param mask interrupt source
+ */
+void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) != 0UL)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->txShifterIndex);
+    }
+    if ((mask & (uint32_t)kFLEXIO_I2S_RxDataRegFullInterruptEnable) != 0UL)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->rxShifterIndex);
+    }
+}
+
+/*!
+ * brief Configures the FlexIO I2S audio format in master mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param format Pointer to FlexIO I2S audio data format structure.
+ * param srcClock_Hz I2S master clock source frequency in Hz.
+ */
+void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
+{
+    uint32_t timDiv  = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U);
+    uint32_t bclkDiv = 0;
+
+    /* Shall keep bclk and fs div an integer */
+    if ((timDiv % 2UL) != 0UL)
+    {
+        timDiv += 1U;
+    }
+    /* Set Frame sync timer cmp */
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U);
+
+    /* Set bit clock timer cmp */
+    bclkDiv                                        = ((timDiv / 2U - 1U) | ((format->bitWidth * 2UL - 1UL) << 8U));
+    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
+}
+
+/*!
+ * brief Configures the FlexIO I2S audio format in slave mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param format Pointer to FlexIO I2S audio data format structure.
+ */
+void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
+{
+    /* Set Frame sync timer cmp */
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4UL - 3UL);
+
+    /* Set bit clock timer cmp */
+    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2UL - 1UL);
+}
+
+/*!
+ * brief Sends data using a blocking method.
+ *
+ * note This function blocks via polling until data is ready to be sent.
+ *
+ * param base FlexIO I2S base pointer.
+ * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * param txData Pointer to the data to be written.
+ * param size Bytes to be written.
+ * retval kStatus_Success Successfully write data.
+ * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
+{
+    uint32_t i           = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+#if I2S_RETRY_TIMES
+    uint32_t waitTimes = I2S_RETRY_TIMES;
+#endif
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        /* Wait until it can write data */
+#if I2S_RETRY_TIMES
+        waitTimes = I2S_RETRY_TIMES;
+        while (((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyFlag) == 0UL) &&
+               (--waitTimes != 0U))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_I2S_Timeout;
+        }
+#else
+        while ((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyFlag) == 0UL)
+        {
+        }
+#endif
+
+        FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord);
+        txData = (uint8_t *)((uint32_t)txData + bytesPerWord);
+    }
+
+    /* Wait until the last data is sent */
+#if I2S_RETRY_TIMES
+    waitTimes = I2S_RETRY_TIMES;
+    while (((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyFlag) == 0UL) && (--waitTimes != 0U))
+    {
+    }
+    if (waitTimes == 0U)
+    {
+        return kStatus_FLEXIO_I2S_Timeout;
+    }
+#else
+    while ((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyFlag) == 0UL)
+    {
+    }
+#endif
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a piece of data using a blocking method.
+ *
+ * note This function blocks via polling until data is ready to be sent.
+ *
+ * param base FlexIO I2S base pointer
+ * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * param rxData Pointer to the data to be read.
+ * param size Bytes to be read.
+ * retval kStatus_Success Successfully read data.
+ * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
+{
+    uint32_t i           = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+#if I2S_RETRY_TIMES
+    uint32_t waitTimes = I2S_RETRY_TIMES;
+#endif
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        /* Wait until data is received */
+#if I2S_RETRY_TIMES
+        waitTimes = I2S_RETRY_TIMES;
+        while ((!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->rxShifterIndex)) != 0UL)) &&
+               (--waitTimes != 0U))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_I2S_Timeout;
+        }
+#else
+        while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->rxShifterIndex)) != 0UL))
+        {
+        }
+#endif
+
+        FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord);
+        rxData = (uint8_t *)((uint32_t)rxData + bytesPerWord);
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the FlexIO I2S handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * param callback FlexIO I2S callback function, which is called while finished a block.
+ * param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Store callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    (void)FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ);
+
+    /* Set the TX/RX state. */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
+}
+
+/*!
+ * brief Initializes the FlexIO I2S receive handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * param callback FlexIO I2S callback function, which is called while finished a block.
+ * param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Store callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    (void)FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ);
+
+    /* Set the TX/RX state. */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
+}
+
+/*!
+ * brief Configures the FlexIO I2S audio format.
+ *
+ * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle FlexIO I2S handle pointer.
+ * param format Pointer to audio data format structure.
+ * param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
+ */
+void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
+                                  flexio_i2s_handle_t *handle,
+                                  flexio_i2s_format_t *format,
+                                  uint32_t srcClock_Hz)
+{
+    assert((handle != NULL) && (format != NULL));
+
+    /* Set the bitWidth to handle */
+    handle->bitWidth = format->bitWidth;
+
+    /* Set sample rate */
+    if (srcClock_Hz != 0UL)
+    {
+        /* It is master */
+        FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
+    }
+    else
+    {
+        FLEXIO_I2S_SlaveSetFormat(base, format);
+    }
+}
+
+/*!
+ * brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
+ *
+ * note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param xfer Pointer to flexio_i2s_transfer_t structure
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
+                                            flexio_i2s_handle_t *handle,
+                                            flexio_i2s_transfer_t *xfer)
+{
+    assert(handle != NULL);
+
+    /* Check if the queue is full */
+    if (handle->queue[handle->queueUser].data != NULL)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+    if ((xfer->dataSize == 0U) || (xfer->data == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Add into queue */
+    handle->queue[handle->queueUser].data     = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Set the state to busy */
+    handle->state = (uint32_t)kFLEXIO_I2S_Busy;
+
+    FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
+
+    /* Enable Tx transfer */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
+ *
+ * note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param xfer Pointer to flexio_i2s_transfer_t structure
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
+                                               flexio_i2s_handle_t *handle,
+                                               flexio_i2s_transfer_t *xfer)
+{
+    assert(handle != NULL);
+
+    /* Check if the queue is full */
+    if (handle->queue[handle->queueUser].data != NULL)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    if ((xfer->dataSize == 0U) || (xfer->data == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Add into queue */
+    handle->queue[handle->queueUser].data     = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Set state to busy */
+    handle->state = (uint32_t)kFLEXIO_I2S_Busy;
+
+    /* Enable interrupt */
+    FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
+
+    /* Enable Rx transfer */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Stop Tx transfer and disable interrupt */
+    FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Aborts the current receive.
+ *
+ * note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Stop rx transfer and disable interrupt */
+    FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Gets the remaining bytes to be sent.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param count Bytes sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status     = kStatus_Success;
+    uint8_t queueDriver = handle->queueDriver;
+
+    if (handle->state != (uint32_t)kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[queueDriver] - handle->queue[queueDriver].dataSize);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Gets the remaining bytes to be received.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * return count Bytes received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status     = kStatus_Success;
+    uint8_t queueDriver = handle->queueDriver;
+
+    if (handle->state != (uint32_t)kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[queueDriver] - handle->queue[queueDriver].dataSize);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * param i2sHandle Pointer to flexio_i2s_handle_t structure
+ */
+void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
+{
+    assert(i2sHandle != NULL);
+
+    flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
+    FLEXIO_I2S_Type *base       = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer             = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize            = handle->bitWidth / 8U;
+
+    /* Handle error */
+    if ((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->txShifterIndex)) != 0UL)
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1UL << base->txShifterIndex));
+    }
+    /* Handle transfer */
+    if (((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_TxDataRegEmptyFlag) != 0UL) &&
+        (handle->queue[handle->queueDriver].data != NULL))
+    {
+        FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize);
+
+        /* Update internal counter */
+        handle->queue[handle->queueDriver].dataSize -= dataSize;
+        handle->queue[handle->queueDriver].data =
+            (uint8_t *)((uint32_t)handle->queue[handle->queueDriver].data + dataSize);
+    }
+
+    /* If finished a block, call the callback function */
+    if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
+    {
+        (void)memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->queue[handle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortSend(base, handle);
+    }
+}
+
+/*!
+ * brief Rx interrupt handler.
+ *
+ * param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * param i2sHandle Pointer to flexio_i2s_handle_t structure.
+ */
+void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
+{
+    assert(i2sHandle != NULL);
+
+    flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
+    FLEXIO_I2S_Type *base       = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer             = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize            = handle->bitWidth / 8U;
+
+    /* Handle transfer */
+    if (((FLEXIO_I2S_GetStatusFlags(base) & (uint32_t)kFLEXIO_I2S_RxDataRegFullFlag) != 0UL) &&
+        (handle->queue[handle->queueDriver].data != NULL))
+    {
+        FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize);
+
+        /* Update internal state */
+        handle->queue[handle->queueDriver].dataSize -= dataSize;
+        handle->queue[handle->queueDriver].data =
+            (uint8_t *)((uint32_t)handle->queue[handle->queueDriver].data + dataSize);
+    }
+
+    /* If finished a block, call the callback function */
+    if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
+    {
+        (void)memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->queue[handle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortReceive(base, handle);
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.h
new file mode 100644
index 0000000000..5b260405a9
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s.h
@@ -0,0 +1,560 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_I2S_H_
+#define FSL_FLEXIO_I2S_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_i2s
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO I2S driver version 2.2.0. */
+#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef I2S_RETRY_TIMES
+#define I2S_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief FlexIO I2S transfer status */
+enum
+{
+    kStatus_FLEXIO_I2S_Idle      = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */
+    kStatus_FLEXIO_I2S_TxBusy    = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_RxBusy    = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_Error     = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */
+    kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */
+    kStatus_FLEXIO_I2S_Timeout =
+        MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 5), /*!< FlexIO I2S timeout polling status flags. */
+};
+
+/*! @brief Define FlexIO I2S access structure typedef */
+typedef struct _flexio_i2s_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */
+    uint8_t txPinIndex;      /*!< Tx data pin index in FlexIO pins */
+    uint8_t rxPinIndex;      /*!< Rx data pin index */
+    uint8_t bclkPinIndex;    /*!< Bit clock pin index */
+    uint8_t fsPinIndex;      /*!< Frame sync pin index */
+    uint8_t txShifterIndex;  /*!< Tx data shifter index */
+    uint8_t rxShifterIndex;  /*!< Rx data shifter index */
+    uint8_t bclkTimerIndex;  /*!< Bit clock timer index */
+    uint8_t fsTimerIndex;    /*!< Frame sync timer index */
+} FLEXIO_I2S_Type;
+
+/*! @brief Master or slave mode */
+typedef enum _flexio_i2s_master_slave
+{
+    kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */
+    kFLEXIO_I2S_Slave  = 0x1U  /*!< Slave mode */
+} flexio_i2s_master_slave_t;
+
+/*! @brief _flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask. */
+enum
+{
+    kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_I2S_RxDataRegFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief _flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask. */
+enum
+{
+    kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_I2S_RxDataRegFullFlag  = 0x2U, /*!< Receive buffer full flag. */
+};
+
+/*! @brief FlexIO I2S configure structure */
+typedef struct _flexio_i2s_config
+{
+    bool enableI2S;                                  /*!< Enable FlexIO I2S */
+    flexio_i2s_master_slave_t masterSlave;           /*!< Master or slave */
+    flexio_pin_polarity_t txPinPolarity;             /*!< Tx data pin polarity, active high or low */
+    flexio_pin_polarity_t rxPinPolarity;             /*!< Rx data pin polarity */
+    flexio_pin_polarity_t bclkPinPolarity;           /*!< Bit clock pin polarity */
+    flexio_pin_polarity_t fsPinPolarity;             /*!< Frame sync pin polarity */
+    flexio_shifter_timer_polarity_t txTimerPolarity; /*!< Tx data valid on bclk rising or falling edge */
+    flexio_shifter_timer_polarity_t rxTimerPolarity; /*!< Rx data valid on bclk rising or falling edge */
+} flexio_i2s_config_t;
+
+/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */
+typedef struct _flexio_i2s_format
+{
+    uint8_t bitWidth;       /*!< Bit width of audio data, always 8/16/24/32 bits */
+    uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */
+} flexio_i2s_format_t;
+
+/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */
+#define FLEXIO_I2S_XFER_QUEUE_SIZE (4U)
+
+/*! @brief Audio sample rate */
+typedef enum _flexio_i2s_sample_rate
+{
+    kFLEXIO_I2S_SampleRate8KHz    = 8000U,  /*!< Sample rate 8000Hz */
+    kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
+    kFLEXIO_I2S_SampleRate12KHz   = 12000U, /*!< Sample rate 12000Hz */
+    kFLEXIO_I2S_SampleRate16KHz   = 16000U, /*!< Sample rate 16000Hz */
+    kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
+    kFLEXIO_I2S_SampleRate24KHz   = 24000U, /*!< Sample rate 24000Hz */
+    kFLEXIO_I2S_SampleRate32KHz   = 32000U, /*!< Sample rate 32000Hz */
+    kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
+    kFLEXIO_I2S_SampleRate48KHz   = 48000U, /*!< Sample rate 48000Hz */
+    kFLEXIO_I2S_SampleRate96KHz   = 96000U  /*!< Sample rate 96000Hz */
+} flexio_i2s_sample_rate_t;
+
+/*! @brief Audio word width */
+typedef enum _flexio_i2s_word_width
+{
+    kFLEXIO_I2S_WordWidth8bits  = 8U,  /*!< Audio data width 8 bits */
+    kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
+    kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
+    kFLEXIO_I2S_WordWidth32bits = 32U  /*!< Audio data width 32 bits */
+} flexio_i2s_word_width_t;
+
+/*! @brief Define FlexIO I2S transfer structure. */
+typedef struct _flexio_i2s_transfer
+{
+    uint8_t *data;   /*!< Data buffer start pointer */
+    size_t dataSize; /*!< Bytes to be transferred. */
+} flexio_i2s_transfer_t;
+
+typedef struct _flexio_i2s_handle flexio_i2s_handle_t;
+
+/*! @brief FlexIO I2S xfer callback prototype */
+typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base,
+                                      flexio_i2s_handle_t *handle,
+                                      status_t status,
+                                      void *userData);
+
+/*! @brief Define FlexIO I2S handle structure. */
+struct _flexio_i2s_handle
+{
+    uint32_t state;                                          /*!< Internal state */
+    flexio_i2s_callback_t callback;                          /*!< Callback function called at transfer event*/
+    void *userData;                                          /*!< Callback parameter passed to callback function*/
+    uint8_t bitWidth;                                        /*!< Bit width for transfer, 8/16/24/32bits */
+    flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
+    size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE];         /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                              /*!< Index for user to queue transfer */
+    volatile uint8_t queueDriver;                            /*!< Index for driver to get the transfer data and size */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S.
+ *
+ * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure.
+ * The configuration structure can be filled by the user, or be set with default values by
+ * FLEXIO_I2S_GetDefaultConfig().
+ *
+ * @note  This API should be called at the beginning of the application to use
+ * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault
+ * because the clock is not enabled.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param config FlexIO I2S configure structure.
+ */
+void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config);
+
+/*!
+ * @brief  Sets the FlexIO I2S configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
+ * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify
+ * some fields of the structure before calling FLEXIO_I2S_Init().
+ *
+ * @param config pointer to master configuration structure
+ */
+void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config);
+
+/*!
+ * @brief De-initializes the FlexIO I2S.
+ *
+ * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API,
+ * call the FLEXO_I2S_Init to use the FlexIO I2S module.
+ *
+ * @param base FlexIO I2S base pointer
+ */
+void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
+
+/*!
+ * @brief Enables/disables the FlexIO I2S module operation.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type
+ * @param enable True to enable, false dose not have any effect.
+ */
+static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO I2S status flags.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
+ */
+uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @param mask interrupt source
+ */
+void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param mask interrupt source
+ */
+void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO I2S Tx DMA requests.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->txShifterIndex, enable);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO I2S Rx DMA requests.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->rxShifterIndex, enable);
+}
+
+/*!
+ * @brief Gets the FlexIO I2S send data register address.
+ *
+ * This function returns the I2S data register address, mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @return FlexIO i2s send data register address.
+ */
+static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex);
+}
+
+/*!
+ * @brief Gets the FlexIO I2S receive data register address.
+ *
+ * This function returns the I2S data register address, mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @return FlexIO i2s receive data register address.
+ */
+static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex);
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the FlexIO I2S audio format in master mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @param format Pointer to FlexIO I2S audio data format structure.
+ * @param srcClock_Hz I2S master clock source frequency in Hz.
+ */
+void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures the FlexIO I2S audio format in slave mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @param format Pointer to FlexIO I2S audio data format structure.
+ */
+void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format);
+
+/*!
+ * @brief Sends data using a blocking method.
+ *
+ * @note This function blocks via polling until data is ready to be sent.
+ *
+ * @param base FlexIO I2S base pointer.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param txData Pointer to the data to be written.
+ * @param size Bytes to be written.
+ * @retval kStatus_Success Successfully write data.
+ * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
+
+/*!
+ * @brief Writes data into a data register.
+ *
+ * @param base FlexIO I2S base pointer.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param data Data to be written.
+ */
+static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)
+{
+    base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
+}
+
+/*!
+ * @brief Receives a piece of data using a blocking method.
+ *
+ * @note This function blocks via polling until data is ready to be sent.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param rxData Pointer to the data to be read.
+ * @param size Bytes to be read.
+ * @retval kStatus_Success Successfully read data.
+ * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags.
+ */
+status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
+
+/*!
+ * @brief Reads a data from the data register.
+ *
+ * @param base FlexIO I2S base pointer
+ * @return Data read from data register.
+ */
+static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)
+{
+    return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex];
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure
+ * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * @param callback FlexIO I2S callback function, which is called while finished a block.
+ * @param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData);
+
+/*!
+ * @brief Configures the FlexIO I2S audio format.
+ *
+ * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle FlexIO I2S handle pointer.
+ * @param format Pointer to audio data format structure.
+ * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
+ */
+void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
+                                  flexio_i2s_handle_t *handle,
+                                  flexio_i2s_format_t *format,
+                                  uint32_t srcClock_Hz);
+
+/*!
+ * @brief Initializes the FlexIO I2S receive handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * @param callback FlexIO I2S callback function, which is called while finished a block.
+ * @param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData);
+
+/*!
+ * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
+ *
+ * @note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param xfer Pointer to flexio_i2s_transfer_t structure
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
+                                            flexio_i2s_handle_t *handle,
+                                            flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
+ *
+ * @note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param xfer Pointer to flexio_i2s_transfer_t structure
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
+                                               flexio_i2s_handle_t *handle,
+                                               flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the current send.
+ *
+ * @note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle);
+
+/*!
+ * @brief Aborts the current receive.
+ *
+ * @note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be sent.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the remaining bytes to be received.
+ *
+ * @param base Pointer to FLEXIO_I2S_Type structure.
+ * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param count Bytes recieved.
+ * @return count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Tx interrupt handler.
+ *
+ * @param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * @param i2sHandle Pointer to flexio_i2s_handle_t structure
+ */
+void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle);
+
+/*!
+ * @brief Rx interrupt handler.
+ *
+ * @param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * @param i2sHandle Pointer to flexio_i2s_handle_t structure.
+ */
+void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+
+/*! @} */
+
+#endif /* FSL_FLEXIO_I2S_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.c
new file mode 100644
index 0000000000..f817e2ca5e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_i2s_dma.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_dma"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+
+/*<! Structure definition for flexio_i2s_dma_private_handle_t. The structure is private. */
+typedef struct _flexio_i2s_dma_private_handle
+{
+    FLEXIO_I2S_Type *base;
+    flexio_i2s_dma_handle_t *handle;
+} flexio_i2s_dma_private_handle_t;
+
+/*!brief _flexio_i2s_dma_transfer_state */
+enum
+{
+    kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO I2S is busy */
+    kFLEXIO_I2S_Idle,        /*!< Transfer is done. */
+};
+
+/*<! Private handle only used for internally. */
+static flexio_i2s_dma_private_handle_t s_dmaPrivateHandle[2];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief FLEXIO I2S DMA callback for send.
+ *
+ * @param handle pointer to flexio_i2s_dma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ */
+static void FLEXIO_I2S_TxDMACallback(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief FLEXIO I2S DMA callback for receive.
+ *
+ * @param handle pointer to flexio_i2s_dma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ */
+static void FLEXIO_I2S_RxDMACallback(dma_handle_t *handle, void *userData);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void FLEXIO_I2S_TxDMACallback(dma_handle_t *handle, void *userData)
+{
+    flexio_i2s_dma_private_handle_t *privHandle = (flexio_i2s_dma_private_handle_t *)userData;
+    flexio_i2s_dma_handle_t *flexio_i2sHandle   = privHandle->handle;
+
+    /* If finished a block, call the callback function */
+    (void)memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+    flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    if (flexio_i2sHandle->callback != NULL)
+    {
+        (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortSendDMA(privHandle->base, flexio_i2sHandle);
+    }
+}
+
+static void FLEXIO_I2S_RxDMACallback(dma_handle_t *handle, void *userData)
+{
+    flexio_i2s_dma_private_handle_t *privHandle = (flexio_i2s_dma_private_handle_t *)userData;
+    flexio_i2s_dma_handle_t *flexio_i2sHandle   = privHandle->handle;
+
+    /* If finished a block, call the callback function */
+    (void)memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+    flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    if (flexio_i2sHandle->callback != NULL)
+    {
+        (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortReceiveDMA(privHandle->base, flexio_i2sHandle);
+    }
+}
+
+/*!
+ * brief Initializes the FlexIO I2S DMA handle.
+ *
+ * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
+ * transactional APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param callback FlexIO I2S DMA callback function called while finished a block.
+ * param userData User parameter for callback.
+ * param dmaHandle DMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferTxCreateHandleDMA(FLEXIO_I2S_Type *base,
+                                          flexio_i2s_dma_handle_t *handle,
+                                          flexio_i2s_dma_callback_t callback,
+                                          void *userData,
+                                          dma_handle_t *dmaHandle)
+{
+    assert((handle != NULL) && (dmaHandle != NULL));
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set flexio_i2s base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback  = callback;
+    handle->userData  = userData;
+
+    /* Set FLEXIO I2S state to idle */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    s_dmaPrivateHandle[0].base   = base;
+    s_dmaPrivateHandle[0].handle = handle;
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(dmaHandle, FLEXIO_I2S_TxDMACallback, &s_dmaPrivateHandle[0]);
+}
+
+/*!
+ * brief Initializes the FlexIO I2S Rx DMA handle.
+ *
+ * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
+ * APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param callback FlexIO I2S DMA callback function called while finished a block.
+ * param userData User parameter for callback.
+ * param dmaHandle DMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferRxCreateHandleDMA(FLEXIO_I2S_Type *base,
+                                          flexio_i2s_dma_handle_t *handle,
+                                          flexio_i2s_dma_callback_t callback,
+                                          void *userData,
+                                          dma_handle_t *dmaHandle)
+{
+    assert((handle != NULL) && (dmaHandle != NULL));
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set flexio_i2s base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback  = callback;
+    handle->userData  = userData;
+
+    /* Set FLEXIO I2S state to idle */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+
+    s_dmaPrivateHandle[1].base   = base;
+    s_dmaPrivateHandle[1].handle = handle;
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(dmaHandle, FLEXIO_I2S_RxDMACallback, &s_dmaPrivateHandle[1]);
+}
+
+/*!
+ * brief Configures the FlexIO I2S Tx audio format.
+ *
+ * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets the DMA parameter according to the format.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer
+ * param format Pointer to FlexIO I2S audio data format structure.
+ * param srcClock_Hz FlexIO I2S clock source frequency in Hz. It should be 0 while in slave mode.
+ */
+void FLEXIO_I2S_TransferSetFormatDMA(FLEXIO_I2S_Type *base,
+                                     flexio_i2s_dma_handle_t *handle,
+                                     flexio_i2s_format_t *format,
+                                     uint32_t srcClock_Hz)
+{
+    assert((handle != NULL) && (format != NULL));
+
+    /* Configure the audio format to FLEXIO I2S registers */
+    if (srcClock_Hz != 0U)
+    {
+        /* It is master */
+        FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
+    }
+    else
+    {
+        FLEXIO_I2S_SlaveSetFormat(base, format);
+    }
+
+    /* Get the transfer size from format, this should be used in DMA configuration */
+    handle->bytesPerFrame = format->bitWidth / 8U;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO I2S transfer using DMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether FLEXIO I2S transfer finished.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a FlexIO I2S DMA send successfully.
+ * retval kStatus_InvalidArgument The input arguments is invalid.
+ * retval kStatus_TxBusy FlexIO I2S is busy sending data.
+ */
+status_t FLEXIO_I2S_TransferSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, flexio_i2s_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+
+    dma_transfer_config_t config = {0};
+    uint32_t destAddr            = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4UL - handle->bytesPerFrame);
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->queue[handle->queueUser].data != NULL)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    /* Change the state of handle */
+    handle->state = (uint32_t)kFLEXIO_I2S_Busy;
+
+    /* Update the queue state */
+    handle->queue[handle->queueUser].data     = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    DMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (uint32_t *)destAddr, handle->bytesPerFrame,
+                        xfer->dataSize, kDMA_MemoryToPeripheral);
+
+    /* Configure DMA channel */
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &config, 1UL);
+
+    /* Start DMA transfer */
+    DMA_StartTransfer(handle->dmaHandle);
+
+    /* Enable DMA enable bit */
+    FLEXIO_I2S_TxEnableDMA(base, true);
+
+    /* Enable FLEXIO I2S Tx clock */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO I2S receive using DMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status to check whether the FlexIO I2S transfer is finished.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a FlexIO I2S DMA receive successfully.
+ * retval kStatus_InvalidArgument The input arguments is invalid.
+ * retval kStatus_RxBusy FlexIO I2S is busy receiving data.
+ */
+status_t FLEXIO_I2S_TransferReceiveDMA(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_dma_handle_t *handle,
+                                       flexio_i2s_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+
+    dma_transfer_config_t config = {0};
+    uint32_t srcAddr             = FLEXIO_I2S_RxGetDataRegisterAddress(base);
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->queue[handle->queueUser].data != NULL)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    /* Change the state of handle */
+    handle->state = (uint32_t)kFLEXIO_I2S_Busy;
+
+    /* Update queue state  */
+    handle->queue[handle->queueUser].data     = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1U) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Prepare dma configure */
+    DMA_PrepareTransfer(&config, (uint32_t *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
+                        xfer->dataSize, kDMA_PeripheralToMemory);
+
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &config, 1UL);
+
+    /* Start DMA transfer */
+    DMA_StartTransfer(handle->dmaHandle);
+
+    /* Enable DMA enable bit */
+    FLEXIO_I2S_RxEnableDMA(base, true);
+
+    /* Enable FLEXIO I2S Rx clock */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a FlexIO I2S transfer using DMA.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable DMA enable bit */
+    FLEXIO_I2S_TxEnableDMA(base, false);
+
+    /* Set the handle state */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+}
+
+/*!
+ * brief Aborts a FlexIO I2S receive using DMA.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortReceiveDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable DMA enable bit */
+    FLEXIO_I2S_RxEnableDMA(base, false);
+
+    /* Set the handle state */
+    handle->state = (uint32_t)kFLEXIO_I2S_Idle;
+}
+
+/*!
+ * brief Gets the remaining bytes to be sent.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param count Bytes sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Gets the remaining bytes to be received.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param count Bytes received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.h
new file mode 100644
index 0000000000..9bf6133cea
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_i2s_dma.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_I2S_DMA_H_
+#define FSL_FLEXIO_I2S_DMA_H_
+
+#include "fsl_flexio_i2s.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup flexio_dma_i2s
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO I2S DMA driver version 2.1.7. */
+#define FSL_FLEXIO_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
+/*! @} */
+
+typedef struct _flexio_i2s_dma_handle flexio_i2s_dma_handle_t;
+
+/*! @brief FlexIO I2S DMA transfer callback function for finish and error */
+typedef void (*flexio_i2s_dma_callback_t)(FLEXIO_I2S_Type *base,
+                                          flexio_i2s_dma_handle_t *handle,
+                                          status_t status,
+                                          void *userData);
+
+/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/
+struct _flexio_i2s_dma_handle
+{
+    dma_handle_t *dmaHandle;            /*!< DMA handler for FlexIO I2S send */
+    uint8_t bytesPerFrame;              /*!< Bytes in a frame */
+    uint32_t state;                     /*!< Internal state for FlexIO I2S DMA transfer */
+    flexio_i2s_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                     /*!< User callback parameter */
+    flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
+    size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE];         /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                              /*!< Index for user to queue transfer. */
+    volatile uint8_t queueDriver;                            /*!< Index for driver to get the transfer data and size */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S DMA handle.
+ *
+ * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
+ * transactional APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param callback FlexIO I2S DMA callback function called while finished a block.
+ * @param userData User parameter for callback.
+ * @param dmaHandle DMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferTxCreateHandleDMA(FLEXIO_I2S_Type *base,
+                                          flexio_i2s_dma_handle_t *handle,
+                                          flexio_i2s_dma_callback_t callback,
+                                          void *userData,
+                                          dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the FlexIO I2S Rx DMA handle.
+ *
+ * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
+ * APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param callback FlexIO I2S DMA callback function called while finished a block.
+ * @param userData User parameter for callback.
+ * @param dmaHandle DMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferRxCreateHandleDMA(FLEXIO_I2S_Type *base,
+                                          flexio_i2s_dma_handle_t *handle,
+                                          flexio_i2s_dma_callback_t callback,
+                                          void *userData,
+                                          dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Configures the FlexIO I2S Tx audio format.
+ *
+ * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets the DMA parameter according to the format.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer
+ * @param format Pointer to FlexIO I2S audio data format structure.
+ * @param srcClock_Hz FlexIO I2S clock source frequency in Hz. It should be 0 while in slave mode.
+ */
+void FLEXIO_I2S_TransferSetFormatDMA(FLEXIO_I2S_Type *base,
+                                     flexio_i2s_dma_handle_t *handle,
+                                     flexio_i2s_format_t *format,
+                                     uint32_t srcClock_Hz);
+
+/*!
+ * @brief Performs a non-blocking FlexIO I2S transfer using DMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether FLEXIO I2S transfer finished.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Start a FlexIO I2S DMA send successfully.
+ * @retval kStatus_InvalidArgument The input arguments is invalid.
+ * @retval kStatus_TxBusy FlexIO I2S is busy sending data.
+ */
+status_t FLEXIO_I2S_TransferSendDMA(FLEXIO_I2S_Type *base,
+                                    flexio_i2s_dma_handle_t *handle,
+                                    flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking FlexIO I2S receive using DMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status to check whether the FlexIO I2S transfer is finished.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Start a FlexIO I2S DMA receive successfully.
+ * @retval kStatus_InvalidArgument The input arguments is invalid.
+ * @retval kStatus_RxBusy FlexIO I2S is busy receiving data.
+ */
+status_t FLEXIO_I2S_TransferReceiveDMA(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_dma_handle_t *handle,
+                                       flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO I2S transfer using DMA.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts a FlexIO I2S receive using DMA.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortReceiveDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be sent.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the remaining bytes to be received.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.c
new file mode 100644
index 0000000000..eaf70de644
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.c
@@ -0,0 +1,1565 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_spi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
+#endif
+
+/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _flexio_spi_transfer_states
+{
+    kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */
+    kFLEXIO_SPI_Busy,        /*!< Transmiter/Receive's queue is not finished. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Send a piece of data for SPI.
+ *
+ * This function computes the number of data to be written into D register or Tx FIFO,
+ * and write the data into it. At the same time, this function updates the values in
+ * master handle structure.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*!
+ * @brief Receive a piece of data for SPI master.
+ *
+ * This function computes the number of data to receive from D register or Rx FIFO,
+ * and write the data to destination address. At the same time, this function updates
+ * the values in master handle structure.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
+{
+    return FLEXIO_GetInstance(base->flexioBase);
+}
+
+static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    uint32_t tmpData = FLEXIO_SPI_DUMMYDATA;
+
+    if (handle->txData != NULL)
+    {
+        /* Transmit data and update tx size/buff. */
+        if (handle->bytePerFrame == 1U)
+        {
+            tmpData = (uint32_t) * (handle->txData);
+            handle->txData++;
+        }
+        else if (handle->bytePerFrame == 2U)
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 8U;
+                tmpData += (uint32_t)handle->txData[1];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 2U;
+        }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 24U;
+                tmpData += (uint32_t)(handle->txData[1]) << 16U;
+                tmpData += (uint32_t)(handle->txData[2]) << 8U;
+                tmpData += (uint32_t)handle->txData[3];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[3]) << 24U;
+                tmpData += (uint32_t)(handle->txData[2]) << 16U;
+                tmpData += (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 4U;
+        }
+    }
+    else
+    {
+        tmpData = FLEXIO_SPI_DUMMYDATA;
+    }
+
+    handle->txRemainingBytes -= handle->bytePerFrame;
+
+    FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
+
+    if (0U == handle->txRemainingBytes)
+    {
+        FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
+    }
+}
+
+static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    uint32_t tmpData;
+
+    tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
+
+    if (handle->rxData != NULL)
+    {
+        if (handle->bytePerFrame == 1U)
+        {
+            *handle->rxData = (uint8_t)tmpData;
+        }
+        else if (handle->bytePerFrame == 2U)
+        {
+            if (handle->direction == kFLEXIO_SPI_LsbFirst)
+            {
+                *handle->rxData = (uint8_t)(tmpData >> 8);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)tmpData;
+            }
+            else
+            {
+                *handle->rxData = (uint8_t)tmpData;
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 8);
+            }
+        }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_LsbFirst)
+            {
+                *handle->rxData = (uint8_t)(tmpData >> 24U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 16U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 8U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)tmpData;
+            }
+            else
+            {
+                *handle->rxData = (uint8_t)tmpData;
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 8U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 16U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 24U);
+            }
+        }
+        handle->rxData++;
+    }
+    handle->rxRemainingBytes -= handle->bytePerFrame;
+}
+
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
+ * and configures the FlexIO SPI with FlexIO SPI master configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_MasterGetDefaultConfig().
+ *
+ * note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low.
+ *      2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
+ *        is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud
+ *        rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO
+ *        SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
+ *
+ * Example
+   code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_spi_master_config_t config = {
+   .enableMaster = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 500000,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param masterConfig Pointer to the flexio_spi_master_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+*/
+void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert(base != NULL);
+    assert(masterConfig != NULL);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg  = 0;
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    (void)memset(&shifterConfig, 0, sizeof(shifterConfig));
+    (void)memset(&timerConfig, 0, sizeof(timerConfig));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure FLEXIO SPI Master */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
+                FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
+    if (!masterConfig->enableInDoze)
+    {
+        ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig   = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect   = base->SDOPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+        shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+        shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitLow;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect  = base->timerIndex[0];
+    shifterConfig.pinConfig    = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect    = base->SDIPinIndex;
+    shifterConfig.pinPolarity  = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode  = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource  = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop  = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 for SCK. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect       = base->SCKPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+    /* Low 8-bits are used to configure baudrate. */
+    timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);
+    timerDiv = timerDiv / 2U - 1U;
+    /* High 8-bits are used to configure shift clock edges(transfer width). */
+    timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;
+    timerCmp |= timerDiv;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 4. Configure the timer 1 for CSn. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect       = base->CSnPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+
+    timerConfig.timerCompare = 0xFFFFU; /* Never compare. */
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+}
+
+/*!
+ * brief Resets the FlexIO SPI timer and shifter config.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type.
+ */
+void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
+{
+    base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO SPI master. The configuration
+ * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
+ * Example:
+   code
+   flexio_spi_master_config_t masterConfig;
+   FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
+   endcode
+ * param masterConfig Pointer to the flexio_spi_master_config_t structure.
+*/
+void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
+{
+    assert(masterConfig != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->enableMaster     = true;
+    masterConfig->enableInDoze     = false;
+    masterConfig->enableInDebug    = true;
+    masterConfig->enableFastAccess = false;
+    /* Default baud rate 500kbps. */
+    masterConfig->baudRate_Bps = 500000U;
+    /* Default CPHA = 0. */
+    masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
+    /* Default bit count at 8. */
+    masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
+}
+
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
+ * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_SlaveGetDefaultConfig().
+ *
+ * note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
+ *      2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
+ *      3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
+ *        is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud
+ *        rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO
+ *        SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
+ * Example
+   code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0}
+   };
+   flexio_spi_slave_config_t config = {
+   .enableSlave = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_SlaveInit(&spiDev, &config);
+   endcode
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
+{
+    assert((base != NULL) && (slaveConfig != NULL));
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg = 0;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    (void)memset(&shifterConfig, 0, sizeof(shifterConfig));
+    (void)memset(&timerConfig, 0, sizeof(timerConfig));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure FLEXIO SPI Slave */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) |
+                FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave));
+    if (!slaveConfig->enableInDoze)
+    {
+        ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig   = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect   = base->SDOPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect  = base->timerIndex[0];
+    shifterConfig.pinConfig    = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect    = base->SDIPinIndex;
+    shifterConfig.pinPolarity  = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode  = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource  = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop  = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 for shift clock. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->SCKPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerRisingEdge;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+        timerConfig.timerStart   = kFLEXIO_TimerStartBitDisabled;
+    }
+    else
+    {
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
+        timerConfig.timerStart   = kFLEXIO_TimerStartBitEnabled;
+    }
+
+    timerConfig.timerCompare = (uint32_t)slaveConfig->dataMode * 2U - 1U;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+}
+
+/*!
+ * brief Gates the FlexIO clock.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type.
+ */
+void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
+{
+    FLEXIO_SPI_MasterDeinit(base);
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
+ * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
+ * Example:
+   code
+   flexio_spi_slave_config_t slaveConfig;
+   FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
+   endcode
+ * param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(slaveConfig, 0, sizeof(*slaveConfig));
+
+    slaveConfig->enableSlave      = true;
+    slaveConfig->enableInDoze     = false;
+    slaveConfig->enableInDebug    = true;
+    slaveConfig->enableFastAccess = false;
+    /* Default CPHA = 0. */
+    slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
+    /* Default bit count at 8. */
+    slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
+}
+
+/*!
+ * brief Enables the FlexIO SPI interrupt.
+ *
+ * This function enables the FlexIO SPI interrupt.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask interrupt source. The parameter can be any combination of the following values:
+ *        arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Disables the FlexIO SPI interrupt.
+ *
+ * This function disables the FlexIO SPI interrupt.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask interrupt source The parameter can be any combination of the following values:
+ *        arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
+ * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask SPI DMA source.
+ * param enable True means enable DMA, false means disable DMA.
+ */
+void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
+{
+    if ((mask & (uint32_t)kFLEXIO_SPI_TxDmaEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable);
+    }
+
+    if ((mask & (uint32_t)kFLEXIO_SPI_RxDmaEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable);
+    }
+}
+
+/*!
+ * brief Gets FlexIO SPI status flags.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * return status flag; Use the status flag to AND the following flag mask and get the status.
+ *          arg kFLEXIO_SPI_TxEmptyFlag
+ *          arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
+uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
+{
+    uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
+    uint32_t status        = 0;
+
+    status = ((shifterStatus & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |= (((shifterStatus & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
+
+    return status;
+}
+
+/*!
+ * brief Clears FlexIO SPI status flags.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_SPI_TxEmptyFlag
+ *          arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
+void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param baudRate_Bps Baud Rate needed in Hz.
+ * param srcClockHz SPI source clock frequency in Hz.
+ */
+void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
+{
+    uint16_t timerDiv       = 0;
+    uint16_t timerCmp       = 0;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
+    timerDiv = (uint16_t)(srcClockHz / baudRate_Bps);
+    timerDiv = timerDiv / 2U - 1U;
+
+    timerCmp = (uint16_t)(flexioBase->TIMCMP[base->timerIndex[0]]);
+    timerCmp &= 0xFF00U;
+    timerCmp |= timerDiv;
+
+    flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
+}
+
+/*!
+ * brief Sends a buffer of data bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been sent.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param direction Shift direction of MSB first or LSB first.
+ * param buffer The data bytes to send.
+ * param size The number of data bytes to send.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
+                                  flexio_spi_shift_direction_t direction,
+                                  const uint8_t *buffer,
+                                  size_t size)
+{
+    assert(buffer != NULL);
+    assert(size != 0U);
+
+#if SPI_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != size--)
+    {
+        /* Wait until data transfer complete. */
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag))
+#endif
+        {
+        }
+#if SPI_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_SPI_Timeout;
+        }
+#endif
+        FLEXIO_SPI_WriteData(base, direction, *buffer++);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been received.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param direction Shift direction of MSB first or LSB first.
+ * param buffer The buffer to store the received bytes.
+ * param size The number of data bytes to be received.
+ * param direction Shift direction of MSB first or LSB first.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
+                                 flexio_spi_shift_direction_t direction,
+                                 uint8_t *buffer,
+                                 size_t size)
+{
+    assert(buffer != NULL);
+    assert(size != 0U);
+
+#if SPI_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != size--)
+    {
+        /* Wait until data transfer complete. */
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag))
+#endif
+        {
+        }
+#if SPI_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_SPI_Timeout;
+        }
+#endif
+        *buffer++ = (uint8_t)FLEXIO_SPI_ReadData(base, direction);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks via polling until all bytes have been received.
+ *
+ * param base pointer to FLEXIO_SPI_Type structure
+ * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
+{
+    flexio_spi_shift_direction_t direction;
+    uint8_t bytesPerFrame;
+    uint32_t dataMode  = 0;
+    uint16_t timerCmp  = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]);
+    uint32_t tmpData   = FLEXIO_SPI_DUMMYDATA;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+#if SPI_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    timerCmp &= 0x00FFU;
+
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
+    /* Configure the values in handle. */
+    switch (dataFormat)
+    {
+        case (uint8_t)kFLEXIO_SPI_8bitMsb:
+            dataMode      = (8UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_8bitLsb:
+            dataMode      = (8UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_16bitMsb:
+            dataMode      = (16UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 2U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_16bitLsb:
+            dataMode      = (16UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 2U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode      = (32UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode      = (32UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+
+        default:
+            dataMode      = (8UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    dataMode |= timerCmp;
+
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % bytesPerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    while (xfer->dataSize != 0U)
+    {
+        /* Wait until data transfer complete. */
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag))
+#endif
+        {
+        }
+#if SPI_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_SPI_Timeout;
+        }
+#endif
+        if (xfer->txData != NULL)
+        {
+            /* Transmit data and update tx size/buff. */
+            if (bytesPerFrame == 1U)
+            {
+                tmpData = (uint32_t) * (xfer->txData);
+                xfer->txData++;
+            }
+            else if (bytesPerFrame == 2U)
+            {
+                if (direction == kFLEXIO_SPI_MsbFirst)
+                {
+                    tmpData = (uint32_t)(xfer->txData[0]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[1];
+                }
+                else
+                {
+                    tmpData = (uint32_t)(xfer->txData[1]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[0];
+                }
+                xfer->txData += 2U;
+            }
+            else
+            {
+                if (direction == kFLEXIO_SPI_MsbFirst)
+                {
+                    tmpData = (uint32_t)(xfer->txData[0]) << 24U;
+                    tmpData += (uint32_t)(xfer->txData[1]) << 16U;
+                    tmpData += (uint32_t)(xfer->txData[2]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[3];
+                }
+                else
+                {
+                    tmpData = (uint32_t)(xfer->txData[3]) << 24U;
+                    tmpData += (uint32_t)(xfer->txData[2]) << 16U;
+                    tmpData += (uint32_t)(xfer->txData[1]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[0];
+                }
+                xfer->txData += 4U;
+            }
+        }
+        else
+        {
+            tmpData = FLEXIO_SPI_DUMMYDATA;
+        }
+
+        xfer->dataSize -= bytesPerFrame;
+
+        FLEXIO_SPI_WriteData(base, direction, tmpData);
+
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag))
+#endif
+        {
+        }
+#if SPI_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_FLEXIO_SPI_Timeout;
+        }
+#endif
+        tmpData = FLEXIO_SPI_ReadData(base, direction);
+
+        if (xfer->rxData != NULL)
+        {
+            if (bytesPerFrame == 1U)
+            {
+                *xfer->rxData = (uint8_t)tmpData;
+            }
+            else if (bytesPerFrame == 2U)
+            {
+                if (direction == kFLEXIO_SPI_LsbFirst)
+                {
+                    *xfer->rxData = (uint8_t)(tmpData >> 8);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)tmpData;
+                }
+                else
+                {
+                    *xfer->rxData = (uint8_t)tmpData;
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 8);
+                }
+            }
+            else
+            {
+                if (direction == kFLEXIO_SPI_LsbFirst)
+                {
+                    *xfer->rxData = (uint8_t)(tmpData >> 24U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 16U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 8U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)tmpData;
+                }
+                else
+                {
+                    *xfer->rxData = (uint8_t)tmpData;
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 8U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 16U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 24U);
+                }
+            }
+            xfer->rxData++;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_handle_t *handle,
+                                               flexio_spi_master_transfer_callback_t callback,
+                                               void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+    NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
+}
+
+/*!
+ * brief Master transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_handle_t *handle,
+                                              flexio_spi_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t dataMode  = 0;
+    uint16_t timerCmp  = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint32_t tmpData   = FLEXIO_SPI_DUMMYDATA;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+
+    timerCmp &= 0x00FFU;
+
+    /* Check if SPI is busy. */
+    if (handle->state == (uint32_t)kFLEXIO_SPI_Busy)
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if the argument is legal. */
+    if ((xfer->txData == NULL) && (xfer->rxData == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
+       enables when tx shifter is written and disables when timer compare. The timer compare event causes the
+       transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
+       disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
+       software writes the tx register upon the detection of tx register empty event, the timer enable condition
+       is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
+    /* Configure the values in handle */
+    switch (dataFormat)
+    {
+        case (uint8_t)kFLEXIO_SPI_8bitMsb:
+            dataMode             = (8UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_8bitLsb:
+            dataMode             = (8UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitMsb:
+            dataMode             = (16UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 2U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitLsb:
+            dataMode             = (16UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 2U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode             = (32UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode             = (32UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            dataMode             = (8UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    dataMode |= timerCmp;
+
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % handle->bytePerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    handle->state            = (uint32_t)kFLEXIO_SPI_Busy;
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
+    handle->rxRemainingBytes = xfer->dataSize;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Send first byte of data to trigger the rx interrupt. */
+    if (handle->txData != NULL)
+    {
+        /* Transmit data and update tx size/buff. */
+        if (handle->bytePerFrame == 1U)
+        {
+            tmpData = (uint32_t) * (handle->txData);
+            handle->txData++;
+        }
+        else if (handle->bytePerFrame == 2U)
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 8U;
+                tmpData += (uint32_t)handle->txData[1];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 2U;
+        }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 24U;
+                tmpData += (uint32_t)(handle->txData[1]) << 16U;
+                tmpData += (uint32_t)(handle->txData[2]) << 8U;
+                tmpData += (uint32_t)handle->txData[3];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[3]) << 24U;
+                tmpData += (uint32_t)(handle->txData[2]) << 16U;
+                tmpData += (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 4U;
+        }
+    }
+    else
+    {
+        tmpData = FLEXIO_SPI_DUMMYDATA;
+    }
+
+    handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame;
+
+    FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
+
+    /* Enable transmit and receive interrupt to handle rx. */
+    FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
+
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the data transfer status which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return remaing bytes in different cases. */
+    if (handle->rxData != NULL)
+    {
+        *count = handle->transferSize - handle->rxRemainingBytes;
+    }
+    else
+    {
+        *count = handle->transferSize - handle->txRemainingBytes;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the master data transfer, which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
+    FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
+
+    /* Transfer finished, set the state to idle. */
+    handle->state = (uint32_t)kFLEXIO_SPI_Idle;
+
+    /* Clear the internal state. */
+    handle->rxRemainingBytes = 0;
+    handle->txRemainingBytes = 0;
+}
+
+/*!
+ * brief FlexIO SPI master IRQ handler function.
+ *
+ * param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
+{
+    assert(spiHandle != NULL);
+
+    flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
+    FLEXIO_SPI_Type *base;
+    uint32_t status;
+
+    if (handle->state == (uint32_t)kFLEXIO_SPI_Idle)
+    {
+        return;
+    }
+
+    base   = (FLEXIO_SPI_Type *)spiType;
+    status = FLEXIO_SPI_GetStatusFlags(base);
+
+    /* Receive interrupt. */
+    if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U)
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+        return;
+    }
+
+    /* Handle rx. */
+    if (handle->rxRemainingBytes != 0U)
+    {
+        FLEXIO_SPI_TransferReceiveTransaction(base, handle);
+    }
+
+    /* Handle tx. */
+    if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U))
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+    }
+
+    /* All the transfer finished. */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        FLEXIO_SPI_MasterTransferAbort(base, handle);
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                              flexio_spi_slave_handle_t *handle,
+                                              flexio_spi_slave_transfer_callback_t callback,
+                                              void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+    NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
+}
+
+/*!
+ * brief Slave transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                             flexio_spi_slave_handle_t *handle,
+                                             flexio_spi_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t dataMode  = 0;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+
+    /* Check if SPI is busy. */
+    if (handle->state == (uint32_t)kFLEXIO_SPI_Busy)
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if the argument is legal. */
+    if ((xfer->txData == NULL) && (xfer->rxData == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
+    /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
+       before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
+       timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
+       tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
+    FLEXIO_SPI_FlushShifters(base);
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+    }
+    else
+    {
+        if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
+            FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+        }
+        else
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+        }
+    }
+
+    /* Configure the values in handle */
+    switch (dataFormat)
+    {
+        case (uint8_t)kFLEXIO_SPI_8bitMsb:
+            dataMode             = 8U * 2U - 1U;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_8bitLsb:
+            dataMode             = 8U * 2U - 1U;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitMsb:
+            dataMode             = 16U * 2U - 1U;
+            handle->bytePerFrame = 2U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitLsb:
+            dataMode             = 16U * 2U - 1U;
+            handle->bytePerFrame = 2U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode             = 32UL * 2UL - 1UL;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode             = 32UL * 2UL - 1UL;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            dataMode             = 8UL * 2UL - 1UL;
+            handle->bytePerFrame = 1U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % handle->bytePerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    handle->state            = (uint32_t)kFLEXIO_SPI_Busy;
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
+    handle->txRemainingBytes = xfer->dataSize;
+    handle->rxRemainingBytes = xfer->dataSize;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Enable transmit and receive interrupt to handle tx and rx. */
+    FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
+    FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief FlexIO SPI slave IRQ handler function.
+ *
+ * param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
+{
+    assert(spiHandle != NULL);
+
+    flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
+    FLEXIO_SPI_Type *base;
+    uint32_t status;
+
+    if (handle->state == (uint32_t)kFLEXIO_SPI_Idle)
+    {
+        return;
+    }
+
+    base   = (FLEXIO_SPI_Type *)spiType;
+    status = FLEXIO_SPI_GetStatusFlags(base);
+
+    /* Handle tx. */
+    if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U))
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+    }
+
+    /* Handle rx. */
+    if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U))
+    {
+        FLEXIO_SPI_TransferReceiveTransaction(base, handle);
+    }
+
+    /* All the transfer finished. */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        FLEXIO_SPI_SlaveTransferAbort(base, handle);
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Flush tx/rx shifters.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ */
+void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)
+{
+    /* Disable then re-enable to flush the tx shifter. */
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+    /* Read to flush the rx shifter. */
+    (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.h
new file mode 100644
index 0000000000..cae17a802c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi.h
@@ -0,0 +1,718 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_FLEXIO_SPI_H_
+#define FSL_FLEXIO_SPI_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_spi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO SPI driver version. */
+#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
+/*! @} */
+
+#ifndef FLEXIO_SPI_DUMMYDATA
+/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
+#define FLEXIO_SPI_DUMMYDATA (0x00U)
+#endif
+
+/*! @brief Retry times for waiting flag. */
+#ifndef SPI_RETRY_TIMES
+#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief Get the transfer data format of width and bit order. */
+#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
+
+/*! @brief Error codes for the FlexIO SPI driver. */
+enum
+{
+    kStatus_FLEXIO_SPI_Busy  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
+    kStatus_FLEXIO_SPI_Idle  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
+    kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
+    kStatus_FLEXIO_SPI_Timeout =
+        MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 4), /*!< FlexIO SPI timeout polling status flags. */
+};
+
+/*! @brief FlexIO SPI clock phase configuration. */
+typedef enum _flexio_spi_clock_phase
+{
+    kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U,  /*!< First edge on SPSCK occurs at the middle of the first
+                                              *   cycle of a data transfer. */
+    kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
+                                              *   first cycle of a data transfer. */
+} flexio_spi_clock_phase_t;
+
+/*! @brief FlexIO SPI data shifter direction options. */
+typedef enum _flexio_spi_shift_direction
+{
+    kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */
+    kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */
+} flexio_spi_shift_direction_t;
+
+/*! @brief FlexIO SPI data length mode options. */
+typedef enum _flexio_spi_data_bitcount_mode
+{
+    kFLEXIO_SPI_8BitMode  = 0x08U, /*!< 8-bit data transmission mode. */
+    kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
+    kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
+} flexio_spi_data_bitcount_mode_t;
+
+/*! @brief Define FlexIO SPI interrupt mask. */
+enum _flexio_spi_interrupt_enable
+{
+    kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_SPI_RxFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO SPI status mask. */
+enum _flexio_spi_status_flags
+{
+    kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_SPI_RxBufferFullFlag  = 0x2U, /*!< Receive buffer full flag. */
+};
+
+/*! @brief Define FlexIO SPI DMA mask. */
+enum _flexio_spi_dma_enable
+{
+    kFLEXIO_SPI_TxDmaEnable  = 0x1U, /*!< Tx DMA request source */
+    kFLEXIO_SPI_RxDmaEnable  = 0x2U, /*!< Rx DMA request source */
+    kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
+};
+
+/*! @brief Define FlexIO SPI transfer flags.
+ *  @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
+enum _flexio_spi_transfer_flags
+{
+    kFLEXIO_SPI_8bitMsb      = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
+    kFLEXIO_SPI_8bitLsb      = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
+    kFLEXIO_SPI_16bitMsb     = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
+    kFLEXIO_SPI_16bitLsb     = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
+    kFLEXIO_SPI_32bitMsb     = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
+    kFLEXIO_SPI_32bitLsb     = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
+    kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
+};
+
+/*! @brief Define FlexIO SPI access structure typedef. */
+typedef struct _flexio_spi_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t SDOPinIndex;     /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
+                                GPIO input and disable all pull up/down in application. */
+    uint8_t SDIPinIndex;     /*!< Pin select for data input. */
+    uint8_t SCKPinIndex;     /*!< Pin select for clock. */
+    uint8_t CSnPinIndex;     /*!< Pin select for enable. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */
+    uint8_t timerIndex[2];   /*!< Timer index used in FlexIO SPI. */
+} FLEXIO_SPI_Type;
+
+/*! @brief Define FlexIO SPI master configuration structure. */
+typedef struct _flexio_spi_master_config
+{
+    bool enableMaster;                        /*!< Enable/disable FlexIO SPI master after configuration. */
+    bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
+                                              fast access requires the FlexIO clock to be at least
+                                              twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps;                    /*!< Baud rate in Bps. */
+    flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
+    flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
+} flexio_spi_master_config_t;
+
+/*! @brief Define FlexIO SPI slave configuration structure. */
+typedef struct _flexio_spi_slave_config
+{
+    bool enableSlave;                         /*!< Enable/disable FlexIO SPI slave after configuration. */
+    bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
+                                              fast access requires the FlexIO clock to be at least
+                                              twice the frequency of the bus clock. */
+    flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
+    flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
+} flexio_spi_slave_config_t;
+
+/*! @brief Define FlexIO SPI transfer structure. */
+typedef struct _flexio_spi_transfer
+{
+    const uint8_t *txData; /*!< Send buffer. */
+    uint8_t *rxData; /*!< Receive buffer. */
+    size_t dataSize; /*!< Transfer bytes. */
+    uint8_t flags;   /*!< FlexIO SPI control flag, MSB first  or LSB first. */
+} flexio_spi_transfer_t;
+
+/*! @brief  typedef for flexio_spi_master_handle_t in advance. */
+typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t;
+
+/*! @brief  Slave handle is the same with master handle. */
+typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t;
+
+/*! @brief FlexIO SPI master callback for finished transmit */
+typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                      flexio_spi_master_handle_t *handle,
+                                                      status_t status,
+                                                      void *userData);
+
+/*! @brief FlexIO SPI slave callback for finished transmit */
+typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                     flexio_spi_slave_handle_t *handle,
+                                                     status_t status,
+                                                     void *userData);
+
+/*! @brief Define FlexIO SPI handle structure. */
+struct _flexio_spi_master_handle
+{
+    const uint8_t *txData;                          /*!< Transfer buffer. */
+    uint8_t *rxData;                                /*!< Receive buffer. */
+    size_t transferSize;                            /*!< Total bytes to be transferred. */
+    volatile size_t txRemainingBytes;               /*!< Send data remaining in bytes. */
+    volatile size_t rxRemainingBytes;               /*!< Receive data remaining in bytes. */
+    volatile uint32_t state;                        /*!< FlexIO SPI internal state. */
+    uint8_t bytePerFrame;                           /*!< SPI mode, 2bytes or 1byte in a frame */
+    flexio_spi_shift_direction_t direction;         /*!< Shift direction. */
+    flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */
+    void *userData;                                 /*!< Callback parameter. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name FlexIO SPI Configuration
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
+ * and configures the FlexIO SPI with FlexIO SPI master configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_MasterGetDefaultConfig().
+ *
+ * @note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low.
+ *      2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
+ *        is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud
+ *        rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO
+ *        SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
+ *
+ * Example
+   @code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_spi_master_config_t config = {
+   .enableMaster = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 500000,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+*/
+void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Resets the FlexIO SPI timer and shifter config.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+ */
+void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration
+ * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
+ * Example:
+   @code
+   flexio_spi_master_config_t masterConfig;
+   FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
+   @endcode
+ * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
+*/
+void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig);
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
+ * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_SlaveGetDefaultConfig().
+ *
+ * @note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
+ *      2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
+ *      3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
+ *        is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud
+ *        rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO
+ *        SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
+ * Example
+   @code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0}
+   };
+   flexio_spi_slave_config_t config = {
+   .enableSlave = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_SlaveInit(&spiDev, &config);
+   @endcode
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Gates the FlexIO clock.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+ */
+void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
+ * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
+ * Example:
+   @code
+   flexio_spi_slave_config_t slaveConfig;
+   FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
+   @endcode
+ * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets FlexIO SPI status flags.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @return status flag; Use the status flag to AND the following flag mask and get the status.
+ *          @arg kFLEXIO_SPI_TxEmptyFlag
+ *          @arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
+uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Clears FlexIO SPI status flags.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_SPI_TxEmptyFlag
+ *          @arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
+void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO SPI interrupt.
+ *
+ * This function enables the FlexIO SPI interrupt.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask interrupt source. The parameter can be any combination of the following values:
+ *        @arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO SPI interrupt.
+ *
+ * This function disables the FlexIO SPI interrupt.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask interrupt source The parameter can be any combination of the following values:
+ *        @arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
+ * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask SPI DMA source.
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable);
+
+/*!
+ * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer.
+ *
+ * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return FlexIO SPI transmit data register address.
+ */
+static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped,
+                                              base->shifterIndex[0]) +
+               3U;
+    }
+    else
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
+    }
+}
+
+/*!
+ * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer.
+ *
+ * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return FlexIO SPI receive data register address.
+ */
+static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]);
+    }
+    else
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO SPI module operation.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+ * @param enable True to enable, false does not have any effect.
+ */
+static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*!
+ * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param baudRate_Bps Baud Rate needed in Hz.
+ * @param srcClockHz SPI source clock frequency in Hz.
+ */
+void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz);
+
+/*!
+ * @brief Writes one byte of data, which is sent using the MSB method.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register but the data transfer is not finished on the bus. Ensure that
+ * the TxEmptyFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param data 8/16/32 bit data.
+ */
+static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
+    }
+    else
+    {
+        base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data;
+    }
+}
+
+/*!
+ * @brief Reads 8 bit/16 bit data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the RxFullFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return 8 bit/16 bit data received.
+ */
+static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
+    }
+    else
+    {
+        return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
+    }
+}
+
+/*!
+ * @brief Sends a buffer of data bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been sent.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param buffer The data bytes to send.
+ * @param size The number of data bytes to send.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
+                                  flexio_spi_shift_direction_t direction,
+                                  const uint8_t *buffer,
+                                  size_t size);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been received.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param buffer The buffer to store the received bytes.
+ * @param size The number of data bytes to be received.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
+                                 flexio_spi_shift_direction_t direction,
+                                 uint8_t *buffer,
+                                 size_t size);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks via polling until all bytes have been received.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Flush tx/rx shifters.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ */
+void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
+/*! @} */
+
+/*Transactional APIs*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_handle_t *handle,
+                                               flexio_spi_master_transfer_callback_t callback,
+                                               void *userData);
+
+/*!
+ * @brief Master transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_handle_t *handle,
+                                              flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the master data transfer, which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*!
+ * @brief Gets the data transfer status which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief FlexIO SPI master IRQ handler function.
+ *
+ * @param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle);
+
+/*!
+ * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                              flexio_spi_slave_handle_t *handle,
+                                              flexio_spi_slave_transfer_callback_t callback,
+                                              void *userData);
+
+/*!
+ * @brief Slave transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                             flexio_spi_slave_handle_t *handle,
+                                             flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the slave data transfer which used IRQ, share same API with master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
+static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
+{
+    FLEXIO_SPI_MasterTransferAbort(base, handle);
+}
+/*!
+ * @brief Gets the data transfer status which used IRQ, share same API with master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
+                                                        flexio_spi_slave_handle_t *handle,
+                                                        size_t *count)
+{
+    return FLEXIO_SPI_MasterTransferGetCount(base, handle, count);
+}
+
+/*!
+ * @brief FlexIO SPI slave IRQ handler function.
+ *
+ * @param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*! @} */
+
+#endif /*FSL_FLEXIO_SPI_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.c
new file mode 100644
index 0000000000..f00f9e8d6e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.c
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_spi_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_dma"
+#endif
+
+/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
+typedef struct _flexio_spi_master_dma_private_handle
+{
+    FLEXIO_SPI_Type *base;
+    flexio_spi_master_dma_handle_t *handle;
+} flexio_spi_master_dma_private_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA callback function for FLEXIO SPI send transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_SPI_TxDMACallback(dma_handle_t *handle, void *param);
+
+/*!
+ * @brief DMA callback function for FLEXIO SPI receive transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_SPI_RxDMACallback(dma_handle_t *handle, void *param);
+
+/*!
+ * @brief EDMA config for FLEXIO SPI transfer.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_master_dma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to flexio spi transfer structure.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_InvalidArgument The transfer size is not supported.
+ */
+static status_t FLEXIO_SPI_DMAConfig(FLEXIO_SPI_Type *base,
+                                     flexio_spi_master_dma_handle_t *handle,
+                                     flexio_spi_transfer_t *xfer);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Dummy data used to send */
+static const uint32_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
+
+/*< @brief user configurable flexio spi handle count. */
+#define FLEXIO_SPI_HANDLE_COUNT 2
+
+/*<! Private handle only used for internally. */
+static flexio_spi_master_dma_private_handle_t s_dmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_SPI_TxDMACallback(dma_handle_t *handle, void *param)
+{
+    flexio_spi_master_dma_private_handle_t *spiPrivateHandle = (flexio_spi_master_dma_private_handle_t *)param;
+
+    /* Disable Tx DMA. */
+    FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    /* change the state. */
+    spiPrivateHandle->handle->txInProgress = false;
+
+    /* All finished, call the callback. */
+    if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
+    {
+        if (spiPrivateHandle->handle->callback != NULL)
+        {
+            (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
+                                                 spiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void FLEXIO_SPI_RxDMACallback(dma_handle_t *handle, void *param)
+{
+    flexio_spi_master_dma_private_handle_t *spiPrivateHandle = (flexio_spi_master_dma_private_handle_t *)param;
+
+    /* Disable Rx DMA. */
+    FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    /* change the state. */
+    spiPrivateHandle->handle->rxInProgress = false;
+
+    /* All finished, call the callback. */
+    if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
+    {
+        if (spiPrivateHandle->handle->callback != NULL)
+        {
+            (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
+                                                 spiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static status_t FLEXIO_SPI_DMAConfig(FLEXIO_SPI_Type *base,
+                                     flexio_spi_master_dma_handle_t *handle,
+                                     flexio_spi_transfer_t *xfer)
+{
+    dma_transfer_config_t xferConfig       = {0};
+    flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
+    uint8_t bytesPerFrame;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+
+    /* Configure the values in handle. */
+    switch (dataFormat)
+    {
+        case (uint8_t)kFLEXIO_SPI_8bitMsb:
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_8bitLsb:
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitMsb:
+            bytesPerFrame = 2U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_16bitLsb:
+            bytesPerFrame = 2U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            bytesPerFrame = 1U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % bytesPerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Configure tx transfer DMA. */
+    xferConfig.destAddr            = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
+    xferConfig.enableDestIncrement = false;
+    if (bytesPerFrame == 1U)
+    {
+        xferConfig.srcSize  = kDMA_Transfersize8bits;
+        xferConfig.destSize = kDMA_Transfersize8bits;
+    }
+    else if (bytesPerFrame == 2U)
+    {
+        if (direction == kFLEXIO_SPI_MsbFirst)
+        {
+            xferConfig.destAddr -= 1U;
+        }
+        xferConfig.srcSize  = kDMA_Transfersize16bits;
+        xferConfig.destSize = kDMA_Transfersize16bits;
+    }
+    else
+    {
+        if (direction == kFLEXIO_SPI_MsbFirst)
+        {
+            xferConfig.destAddr -= 3U;
+        }
+        xferConfig.srcSize  = kDMA_Transfersize32bits;
+        xferConfig.destSize = kDMA_Transfersize32bits;
+    }
+
+    /* Configure DMA channel. */
+    if (xfer->txData != NULL)
+    {
+        xferConfig.enableSrcIncrement = true;
+        xferConfig.srcAddr            = (uint32_t)(xfer->txData);
+    }
+    else
+    {
+        /* Disable the source increasement and source set to dummyData. */
+        xferConfig.enableSrcIncrement = false;
+        xferConfig.srcAddr            = (uint32_t)(&s_dummyData);
+    }
+
+    xferConfig.transferSize = xfer->dataSize;
+
+    if (handle->txHandle != NULL)
+    {
+        (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+    }
+
+    /* Configure tx transfer DMA. */
+    if (xfer->rxData != NULL)
+    {
+        xferConfig.srcAddr             = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction);
+        xferConfig.enableSrcIncrement  = false;
+        xferConfig.destAddr            = (uint32_t)(xfer->rxData);
+        xferConfig.enableDestIncrement = true;
+        (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+        handle->rxInProgress = true;
+        FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, true);
+        DMA_StartTransfer(handle->rxHandle);
+    }
+
+    /* Always start Tx transfer. */
+    if (handle->txHandle != NULL)
+    {
+        handle->txInProgress = true;
+        FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true);
+        DMA_StartTransfer(handle->txHandle);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the FLEXO SPI master DMA handle.
+ *
+ * This function initializes the FLEXO SPI master DMA handle which can be used for other FLEXO SPI master transactional
+ * APIs.
+ * Usually, for a specified FLEXO SPI instance, call this API once to get the initialized handle.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_master_dma_handle_t structure to store the transfer state.
+ * param callback SPI callback, NULL means no callback.
+ * param userData callback function parameter.
+ * param txHandle User requested DMA handle for FlexIO SPI RX DMA transfer.
+ * param rxHandle User requested DMA handle for FlexIO SPI TX DMA transfer.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO SPI DMA type/handle table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandleDMA(FLEXIO_SPI_Type *base,
+                                                  flexio_spi_master_dma_handle_t *handle,
+                                                  flexio_spi_master_dma_transfer_callback_t callback,
+                                                  void *userData,
+                                                  dma_handle_t *txHandle,
+                                                  dma_handle_t *rxHandle)
+{
+    assert(handle != NULL);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0U; index < (uint8_t)FLEXIO_SPI_HANDLE_COUNT; index++)
+    {
+        if (s_dmaPrivateHandle[index].base == NULL)
+        {
+            s_dmaPrivateHandle[index].base   = base;
+            s_dmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == (uint8_t)FLEXIO_SPI_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Set spi base to handle. */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle. */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+
+    /* Install callback for Tx/Rx dma channel. */
+    if (handle->txHandle != NULL)
+    {
+        DMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxDMACallback, &s_dmaPrivateHandle[index]);
+    }
+    if (handle->rxHandle != NULL)
+    {
+        DMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxDMACallback, &s_dmaPrivateHandle[index]);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO SPI transfer using DMA.
+ *
+ * note This interface returned immediately after transfer initiates. Call
+ * FLEXIO_SPI_MasterGetTransferCountDMA to poll the transfer status to check
+ * whether the FlexIO SPI transfer is finished.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_master_dma_handle_t structure to store the transfer state.
+ * param xfer Pointer to FlexIO SPI transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferDMA(FLEXIO_SPI_Type *base,
+                                      flexio_spi_master_dma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t dataMode  = 0U;
+    uint16_t timerCmp  = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+
+    timerCmp &= 0x00FFU;
+
+    /* Check if the device is busy. */
+    if ((handle->txInProgress) || (handle->rxInProgress))
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if input parameter invalid. */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
+       enables when tx shifter is written and disables when timer compare. The timer compare event causes the
+       transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
+       disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
+       software writes the tx register upon the detection of tx register empty event, the timer enable condition
+       is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
+    /* configure data mode. */
+    if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
+    {
+        dataMode = (8UL * 2UL - 1UL) << 8U;
+    }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
+    {
+        dataMode = (16UL * 2UL - 1UL) << 8U;
+    }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
+    {
+        dataMode = (32UL * 2UL - 1UL) << 8U;
+    }
+    else
+    {
+        dataMode = (8UL * 2UL - 1UL) << 8U;
+    }
+
+    dataMode |= timerCmp;
+
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    return FLEXIO_SPI_DMAConfig(base, handle, xfer);
+}
+
+/*!
+ * brief Gets the remaining bytes for FlexIO SPI DMA transfer.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle FlexIO SPI DMA handle pointer.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCountDMA(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_dma_handle_t *handle,
+                                              size_t *count)
+{
+    assert(handle != NULL);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->rxInProgress)
+    {
+        *count = (handle->transferSize - DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel));
+    }
+    else
+    {
+        *count = (handle->transferSize - DMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel));
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a FlexIO SPI transfer using DMA.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle FlexIO SPI DMA handle pointer.
+ */
+void FLEXIO_SPI_MasterTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_master_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma. */
+    DMA_AbortTransfer(handle->txHandle);
+    DMA_AbortTransfer(handle->rxHandle);
+
+    /* Disable DMA enable bit. */
+    FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_DmaAllEnable, false);
+
+    /* Set the handle state. */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO SPI transfer using DMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_SlaveGetTransferCountDMA to poll the transfer status and
+ * check whether the FlexIO SPI transfer is finished.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state.
+ * param xfer Pointer to FlexIO SPI transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferDMA(FLEXIO_SPI_Type *base,
+                                     flexio_spi_slave_dma_handle_t *handle,
+                                     flexio_spi_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t dataMode  = 0U;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
+
+    /* Check if the device is busy. */
+    if ((handle->txInProgress) || (handle->rxInProgress))
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if input parameter invalid. */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
+    /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
+       before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
+       timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
+       tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
+    FLEXIO_SPI_FlushShifters(base);
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+    }
+    else
+    {
+        if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
+            FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+        }
+        else
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+        }
+    }
+
+    /* configure data mode. */
+    if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
+    {
+        dataMode = 8UL * 2UL - 1UL;
+    }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
+    {
+        dataMode = 16UL * 2UL - 1UL;
+    }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
+    {
+        dataMode = 32UL * 2UL - 1UL;
+    }
+    else
+    {
+        dataMode = 8UL * 2UL - 1UL;
+    }
+
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    return FLEXIO_SPI_DMAConfig(base, handle, xfer);
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.h
new file mode 100644
index 0000000000..a3c9208081
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_spi_dma.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_SPI_DMA_H_
+#define FSL_FLEXIO_SPI_DMA_H_
+
+#include "fsl_flexio_spi.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup flexio_dma_spi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO SPI DMA driver version 2.3.0. */
+#define FSL_FLEXIO_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*! @} */
+
+/*! @brief  typedef for flexio_spi_master_dma_handle_t in advance. */
+typedef struct _flexio_spi_master_dma_handle flexio_spi_master_dma_handle_t;
+
+/*! @brief  Slave handle is the same with master handle. */
+typedef flexio_spi_master_dma_handle_t flexio_spi_slave_dma_handle_t;
+
+/*! @brief FlexIO SPI master callback for finished transmit */
+typedef void (*flexio_spi_master_dma_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                          flexio_spi_master_dma_handle_t *handle,
+                                                          status_t status,
+                                                          void *userData);
+
+/*! @brief FlexIO SPI slave callback for finished transmit */
+typedef void (*flexio_spi_slave_dma_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                         flexio_spi_slave_dma_handle_t *handle,
+                                                         status_t status,
+                                                         void *userData);
+
+/*! @brief FlexIO SPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _flexio_spi_master_dma_handle
+{
+    size_t transferSize;                                /*!< Total bytes to be transferred. */
+    bool txInProgress;                                  /*!< Send transfer in progress */
+    bool rxInProgress;                                  /*!< Receive transfer in progress */
+    dma_handle_t *txHandle;                             /*!< DMA handler for SPI send */
+    dma_handle_t *rxHandle;                             /*!< DMA handler for SPI receive */
+    flexio_spi_master_dma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;                                     /*!< User Data for SPI DMA callback */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXO SPI master DMA handle.
+ *
+ * This function initializes the FLEXO SPI master DMA handle which can be used for other FLEXO SPI master transactional
+ * APIs.
+ * Usually, for a specified FLEXO SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle Pointer to flexio_spi_master_dma_handle_t structure to store the transfer state.
+ * @param callback SPI callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txHandle User requested DMA handle for FlexIO SPI RX DMA transfer.
+ * @param rxHandle User requested DMA handle for FlexIO SPI TX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO SPI DMA type/handle table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandleDMA(FLEXIO_SPI_Type *base,
+                                                  flexio_spi_master_dma_handle_t *handle,
+                                                  flexio_spi_master_dma_transfer_callback_t callback,
+                                                  void *userData,
+                                                  dma_handle_t *txHandle,
+                                                  dma_handle_t *rxHandle);
+
+/*!
+ * @brief Performs a non-blocking FlexIO SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates. Call
+ * FLEXIO_SPI_MasterGetTransferCountDMA to poll the transfer status to check
+ * whether the FlexIO SPI transfer is finished.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle Pointer to flexio_spi_master_dma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to FlexIO SPI transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferDMA(FLEXIO_SPI_Type *base,
+                                      flexio_spi_master_dma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO SPI transfer using DMA.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI DMA handle pointer.
+ */
+void FLEXIO_SPI_MasterTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_master_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes for FlexIO SPI DMA transfer.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI DMA handle pointer.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCountDMA(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_dma_handle_t *handle,
+                                              size_t *count);
+
+/*!
+ * @brief Initializes the FlexIO SPI slave DMA handle.
+ *
+ * This function initializes the FlexIO SPI slave DMA handle.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle Pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state.
+ * @param callback SPI callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txHandle User requested DMA handle for FlexIO SPI TX DMA transfer.
+ * @param rxHandle User requested DMA handle for FlexIO SPI RX DMA transfer.
+ */
+static inline void FLEXIO_SPI_SlaveTransferCreateHandleDMA(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_slave_dma_handle_t *handle,
+                                                           flexio_spi_slave_dma_transfer_callback_t callback,
+                                                           void *userData,
+                                                           dma_handle_t *txHandle,
+                                                           dma_handle_t *rxHandle)
+{
+    (void)FLEXIO_SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Performs a non-blocking FlexIO SPI transfer using DMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_SlaveGetTransferCountDMA to poll the transfer status and
+ * check whether the FlexIO SPI transfer is finished.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle Pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to FlexIO SPI transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferDMA(FLEXIO_SPI_Type *base,
+                                     flexio_spi_slave_dma_handle_t *handle,
+                                     flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO SPI transfer using DMA.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle Pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state.
+ */
+static inline void FLEXIO_SPI_SlaveTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_dma_handle_t *handle)
+{
+    FLEXIO_SPI_MasterTransferAbortDMA(base, handle);
+}
+
+/*!
+ * @brief Gets the remaining bytes to be transferred for FlexIO SPI DMA.
+ *
+ * @param base Pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI DMA handle pointer.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+static inline status_t FLEXIO_SPI_SlaveTransferGetCountDMA(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_slave_dma_handle_t *handle,
+                                                           size_t *count)
+{
+    return FLEXIO_SPI_MasterTransferGetCountDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.c
new file mode 100644
index 0000000000..13890caee7
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.c
@@ -0,0 +1,1023 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_uart"
+#endif
+
+/*<! @brief uart transfer state. */
+enum _flexio_uart_transfer_states
+{
+    kFLEXIO_UART_TxIdle, /* TX idle. */
+    kFLEXIO_UART_TxBusy, /* TX busy. */
+    kFLEXIO_UART_RxIdle, /* RX idle. */
+    kFLEXIO_UART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle FLEXIO UART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @param handle FLEXIO UART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static uint32_t FLEXIO_UART_GetInstance(FLEXIO_UART_Type *base)
+{
+    return FLEXIO_GetInstance(base->flexioBase);
+}
+
+static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle)
+{
+    size_t size;
+    uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+    uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+    if (rxRingBufferTail > rxRingBufferHead)
+    {
+        size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+    }
+    else
+    {
+        size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+    }
+
+    return size;
+}
+
+static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
+{
+    bool full;
+
+    if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+
+    return full;
+}
+
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
+ * hardware, and configures the FlexIO UART with FlexIO UART configuration.
+ * The configuration structure can be filled by the user or be set with
+ * default values by FLEXIO_UART_GetDefaultConfig().
+ *
+ * Example
+   code
+   FLEXIO_UART_Type base = {
+   .flexioBase = FLEXIO,
+   .TxPinIndex = 0,
+   .RxPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_uart_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 115200U,
+   .bitCountPerChar = 8
+   };
+   FLEXIO_UART_Init(base, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param userConfig Pointer to the flexio_uart_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+ * retval kStatus_Success Configuration success.
+ * retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency.
+*/
+status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
+{
+    assert((base != NULL) && (userConfig != NULL));
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg  = 0;
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+    uint32_t calculatedBaud;
+    uint32_t diff;
+    status_t result = kStatus_Success;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    (void)memset(&shifterConfig, 0, sizeof(shifterConfig));
+    (void)memset(&timerConfig, 0, sizeof(timerConfig));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure FLEXIO UART */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) |
+                FLEXIO_CTRL_FLEXEN(userConfig->enableUart));
+    if (!userConfig->enableInDoze)
+    {
+        ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect   = base->timerIndex[0];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect     = base->TxPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /*2. Configure the timer 0 for tx. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->TxPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+
+    timerDiv = (uint16_t)(srcClock_Hz / userConfig->baudRate_Bps);
+    timerDiv = timerDiv / 2U - 1U;
+
+    if (timerDiv > 0xFFU)
+    {
+        /* Check whether the calculated timerDiv is within allowed range. */
+        return kStatus_FLEXIO_UART_BaudrateNotSupport;
+    }
+    else
+    {
+        /* Check to see if actual baud rate is within 3% of desired baud rate
+         * based on the best calculated timerDiv value */
+        calculatedBaud = srcClock_Hz / (((uint32_t)timerDiv + 1U) * 2U);
+        /* timerDiv cannot be larger than the ideal divider, so calculatedBaud is definitely larger
+           than configured baud */
+        diff = calculatedBaud - userConfig->baudRate_Bps;
+        if (diff > ((userConfig->baudRate_Bps / 100U) * 3U))
+        {
+            return kStatus_FLEXIO_UART_BaudrateNotSupport;
+        }
+    }
+
+    timerCmp = ((uint16_t)userConfig->bitCountPerChar * 2U - 1U) << 8U;
+    timerCmp |= timerDiv;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 3. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect   = base->timerIndex[1];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect     = base->RxPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /* 4. Configure the timer 1 for rx. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceExternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->RxPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetOnTimerPinRisingEdge;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdge;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+
+    return result;
+}
+
+/*!
+ * brief Resets the FlexIO UART shifter and timer config.
+ *
+ * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ */
+void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
+{
+    base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
+    base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]);
+    base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]);
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]);
+    base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]);
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO UART. The configuration
+ * can be used directly for calling the FLEXIO_UART_Init().
+ * Example:
+   code
+   flexio_uart_config_t config;
+   FLEXIO_UART_GetDefaultConfig(&userConfig);
+   endcode
+ * param userConfig Pointer to the flexio_uart_config_t structure.
+*/
+void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
+{
+    assert(userConfig != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(userConfig, 0, sizeof(*userConfig));
+
+    userConfig->enableUart       = true;
+    userConfig->enableInDoze     = false;
+    userConfig->enableInDebug    = true;
+    userConfig->enableFastAccess = false;
+    /* Default baud rate 115200. */
+    userConfig->baudRate_Bps = 115200U;
+    /* Default bit count at 8. */
+    userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
+}
+
+/*!
+ * brief Enables the FlexIO UART interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Interrupt source.
+ */
+void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Disables the FlexIO UART interrupt.
+ *
+ * This function disables the FlexIO UART interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Interrupt source.
+ */
+void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Gets the FlexIO UART status flags.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * return FlexIO UART status flags.
+ */
+
+uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
+{
+    uint32_t status = 0U;
+    status =
+        ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 1U);
+    status |=
+        (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 2U);
+    return status;
+}
+
+/*!
+ * brief Gets the FlexIO UART status flags.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_UART_TxDataRegEmptyFlag
+ *          arg kFLEXIO_UART_RxEmptyFlag
+ *          arg kFLEXIO_UART_RxOverRunFlag
+ */
+
+void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag) != 0U)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+    if ((mask & (uint32_t)kFLEXIO_UART_RxOverRunFlag) != 0U)
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
+    }
+}
+
+/*!
+ * brief Sends a buffer of data bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been sent.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param txData The data bytes to send.
+ * param txSize The number of data bytes to send.
+ * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
+{
+    assert(txData != NULL);
+    assert(txSize != 0U);
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != txSize--)
+    {
+        /* Wait until data transfer complete. */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_FLEXIO_UART_Timeout;
+        }
+#endif
+
+        base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been received.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param rxData The buffer to store the received bytes.
+ * param rxSize The number of data bytes to be received.
+ * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
+{
+    assert(rxData != NULL);
+    assert(rxSize != 0U);
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != rxSize--)
+    {
+        /* Wait until data transfer complete. */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag)) &&
+               (0U != --waitTimes))
+#else
+        while (0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_FLEXIO_UART_Timeout;
+        }
+#endif
+
+        *rxData++ = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the UART handle.
+ *
+ * This function initializes the FlexIO UART handle, which can be used for other FlexIO
+ * UART transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that users can set up
+ * a RX ring buffer optionally. Data received is stored into the ring buffer even when
+ * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
+ * received in the ring buffer, users can get the received data from the ring buffer
+ * directly. The ring buffer is disabled if passing NULL as p ringBuffer.
+ *
+ * param base to FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
+                                          flexio_uart_handle_t *handle,
+                                          flexio_uart_transfer_callback_t callback,
+                                          void *userData)
+{
+    assert(handle != NULL);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle;
+    handle->txState = (uint8_t)kFLEXIO_UART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+    NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]);
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, users can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize Size of the ring buffer.
+ */
+void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
+                                         flexio_uart_handle_t *handle,
+                                         uint8_t *ringBuffer,
+                                         size_t ringBufferSize)
+{
+    assert(handle != NULL);
+
+    /* Setup the ringbuffer address */
+    if (ringBuffer != NULL)
+    {
+        handle->rxRingBuffer     = ringBuffer;
+        handle->rxRingBufferSize = ringBufferSize;
+        handle->rxRingBufferHead = 0U;
+        handle->rxRingBufferTail = 0U;
+
+        /* Enable the interrupt to accept the data when user need the ring buffer. */
+        FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    if (handle->rxState == (uint8_t)kFLEXIO_UART_RxIdle)
+    {
+        FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function,
+ * which returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback
+ * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter.
+ *
+ * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
+ * retval kStatus_Success Successfully starts the data transmission.
+ * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
+ */
+status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
+                                             flexio_uart_handle_t *handle,
+                                             flexio_uart_transfer_t *xfer)
+{
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->txData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState)
+    {
+        status = kStatus_FLEXIO_UART_TxBusy;
+    }
+    else
+    {
+        handle->txData        = xfer->txData;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = (uint8_t)kFLEXIO_UART_TxBusy;
+
+        /* Enable transmiter interrupt. */
+        FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. Get the remainBytes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    /* Disable the transmitter and disable the interrupt. */
+    FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+    handle->txDataSize = 0U;
+    handle->txState    = (uint8_t)kFLEXIO_UART_TxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes sent.
+ *
+ * This function gets the number of bytes sent driven by interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param count Number of bytes sent so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using the interrupt method. This is a non-blocking function,
+ * which returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
+ * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
+ * the 5 bytes are copied to xfer->data. This function returns with the
+ * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param xfer UART transfer structure. See #flexio_uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
+ */
+status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                flexio_uart_transfer_t *xfer,
+                                                size_t *receivedBytes)
+{
+    uint32_t i;
+    status_t status;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->rxData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_UART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */
+            FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle);
+
+            if (bytesToCopy != 0U)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive != 0U)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->rxData + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = xfer->dataSize;
+                handle->rxState       = (uint8_t)kFLEXIO_UART_RxBusy;
+            }
+
+            /* Enable FLEXIO_UART RX IRQ if previously enabled. */
+            FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+
+            /* Call user callback since all data are received. */
+            if (0U == bytesToReceive)
+            {
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData        = xfer->rxData + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = (uint8_t)kFLEXIO_UART_RxBusy;
+
+            /* Enable RX interrupt. */
+            FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+        }
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes != NULL)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the receive data which was using IRQ.
+ *
+ * This function aborts the receive data which was using IRQ.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable RX interrupt. */
+        FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kFLEXIO_UART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received driven by interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param count Number of bytes received so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief FlexIO UART IRQ handler function.
+ *
+ * This function processes the FlexIO UART transmit and receives the IRQ request.
+ *
+ * param uartType Pointer to the FLEXIO_UART_Type structure.
+ * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
+{
+    uint8_t count                = 1;
+    FLEXIO_UART_Type *base       = (FLEXIO_UART_Type *)uartType;
+    flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle;
+    uint16_t rxRingBufferHead;
+
+    /* Read the status back. */
+    uint32_t status = FLEXIO_UART_GetStatusFlags(base);
+
+    /* If RX overrun. */
+    if (((uint32_t)kFLEXIO_UART_RxOverRunFlag & status) != 0U)
+    {
+        /* Clear Overrun flag. */
+        FLEXIO_UART_ClearStatusFlags(base, (uint32_t)kFLEXIO_UART_RxOverRunFlag);
+
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* Receive data register full */
+    if ((((uint32_t)kFLEXIO_UART_RxDataRegFullFlag & status) != 0U) &&
+        ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[1])) != 0U))
+    {
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        if (handle->rxDataSize != 0U)
+        {
+            /* Using non block API to read the data from the registers. */
+            FLEXIO_UART_ReadByte(base, handle->rxData);
+            handle->rxDataSize--;
+            handle->rxData++;
+            count--;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (0U == handle->rxDataSize)
+            {
+                handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle;
+
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+
+        if (handle->rxRingBuffer != NULL)
+        {
+            if (count != 0U)
+            {
+                /* If RX ring buffer is full, trigger callback to notify over run. */
+                if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
+                {
+                    if (handle->callback != NULL)
+                    {
+                        handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData);
+                    }
+                }
+
+                /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
+                {
+                    /* Increase handle->rxRingBufferTail to make room for new data. */
+                    if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+
+                /* Read data. */
+                rxRingBufferHead = handle->rxRingBufferHead;
+                handle->rxRingBuffer[rxRingBufferHead] =
+                    (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
+
+                /* Increase handle->rxRingBufferHead. */
+                if ((uint32_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferHead = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferHead++;
+                }
+            }
+        }
+        /* If no receive requst pending, stop RX interrupt. */
+        else if (0U == handle->rxDataSize)
+        {
+            FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable);
+        }
+        else
+        {
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((((uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag & status) != 0U) &&
+        ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[0])) != 0U))
+    {
+        if (handle->txDataSize != 0U)
+        {
+            /* Using non block API to write the data to the registers. */
+            FLEXIO_UART_WriteByte(base, handle->txData);
+            handle->txData++;
+            handle->txDataSize--;
+
+            /* If all the data are written to data register, TX finished. */
+            if (0U == handle->txDataSize)
+            {
+                handle->txState = (uint8_t)kFLEXIO_UART_TxIdle;
+
+                /* Disable TX register empty interrupt. */
+                FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+                /* Trigger callback. */
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+}
+
+/*!
+ * brief Flush tx/rx shifters.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ */
+void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)
+{
+    /* Disable then re-enable to flush the tx shifter. */
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+    /* Read to flush the rx shifter. */
+    (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.h
new file mode 100644
index 0000000000..d6f36bf323
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart.h
@@ -0,0 +1,588 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_FLEXIO_UART_H_
+#define FSL_FLEXIO_UART_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO UART driver version. */
+#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+#endif
+
+/*! @brief Error codes for the UART driver. */
+enum
+{
+    kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */
+    kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */
+    kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */
+    kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */
+    kStatus_FLEXIO_UART_ERROR  = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */
+    kStatus_FLEXIO_UART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */
+    kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6), /*!< UART RX receiver overrun. */
+    kStatus_FLEXIO_UART_Timeout           = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 7), /*!< UART times out. */
+    kStatus_FLEXIO_UART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_FLEXIO_UART, 8) /*!< Baudrate is not supported in current clock source */
+};
+
+/*! @brief FlexIO UART bit count per char. */
+typedef enum _flexio_uart_bit_count_per_char
+{
+    kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */
+    kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */
+    kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */
+} flexio_uart_bit_count_per_char_t;
+
+/*! @brief Define FlexIO UART interrupt mask. */
+enum _flexio_uart_interrupt_enable
+{
+    kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_UART_RxDataRegFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO UART status mask. */
+enum _flexio_uart_status_flags
+{
+    kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_UART_RxDataRegFullFlag  = 0x2U, /*!< Receive buffer full flag. */
+    kFLEXIO_UART_RxOverRunFlag      = 0x4U, /*!< Receive buffer over run flag. */
+};
+
+/*! @brief Define FlexIO UART access structure typedef. */
+typedef struct _flexio_uart_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t TxPinIndex;      /*!< Pin select for UART_Tx. */
+    uint8_t RxPinIndex;      /*!< Pin select for UART_Rx. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */
+    uint8_t timerIndex[2];   /*!< Timer index used in FlexIO UART. */
+} FLEXIO_UART_Type;
+
+/*! @brief Define FlexIO UART user configuration structure. */
+typedef struct _flexio_uart_config
+{
+    bool enableUart;                                  /*!< Enable/disable FlexIO UART TX & RX. */
+    bool enableInDoze;                                /*!< Enable/disable FlexIO operation in doze mode*/
+    bool enableInDebug;                               /*!< Enable/disable FlexIO operation in debug mode*/
+    bool enableFastAccess;                            /*!< Enable/disable fast access to FlexIO registers,
+                                                       fast access requires the FlexIO clock to be at least
+                                                       twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps;                            /*!< Baud rate in Bps. */
+    flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */
+} flexio_uart_config_t;
+
+/*! @brief Define FlexIO UART transfer structure. */
+typedef struct _flexio_uart_transfer
+{
+    /*
+     * Use separate TX and RX data pointer, because TX data is const data.
+     * The member data is kept for backward compatibility.
+     */
+    union
+    {
+        uint8_t *data;         /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;       /*!< The buffer to receive data. */
+        const uint8_t *txData; /*!< The buffer of data to be sent. */
+    };
+    size_t dataSize; /*!< Transfer size*/
+} flexio_uart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexio_uart_handle flexio_uart_handle_t;
+
+/*! @brief FlexIO UART transfer callback function. */
+typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                status_t status,
+                                                void *userData);
+
+/*! @brief Define FLEXIO UART handle structure*/
+struct _flexio_uart_handle
+{
+    const uint8_t *volatile txData; /*!< Address of remaining data to send. */
+    volatile size_t txDataSize;     /*!< Size of the remaining data to send. */
+    uint8_t *volatile rxData;       /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize;     /*!< Size of the remaining data to receive. */
+    size_t txDataSizeAll;           /*!< Total bytes to be sent. */
+    size_t rxDataSizeAll;           /*!< Total bytes to be received. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    flexio_uart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                           /*!< UART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
+ * hardware, and configures the FlexIO UART with FlexIO UART configuration.
+ * The configuration structure can be filled by the user or be set with
+ * default values by FLEXIO_UART_GetDefaultConfig().
+ *
+ * Example
+   @code
+   FLEXIO_UART_Type base = {
+   .flexioBase = FLEXIO,
+   .TxPinIndex = 0,
+   .RxPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_uart_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 115200U,
+   .bitCountPerChar = 8
+   };
+   FLEXIO_UART_Init(base, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param userConfig Pointer to the flexio_uart_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+ * @retval kStatus_Success Configuration success.
+ * @retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency.
+*/
+status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Resets the FlexIO UART shifter and timer config.
+ *
+ * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ */
+void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO UART. The configuration
+ * can be used directly for calling the FLEXIO_UART_Init().
+ * Example:
+   @code
+   flexio_uart_config_t config;
+   FLEXIO_UART_GetDefaultConfig(&userConfig);
+   @endcode
+ * @param userConfig Pointer to the flexio_uart_config_t structure.
+*/
+void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO UART status flags.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART status flags.
+ */
+
+uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
+
+/*!
+ * @brief Gets the FlexIO UART status flags.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_UART_TxDataRegEmptyFlag
+ *          @arg kFLEXIO_UART_RxEmptyFlag
+ *          @arg kFLEXIO_UART_RxOverRunFlag
+ */
+
+void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO UART interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Interrupt source.
+ */
+void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO UART interrupt.
+ *
+ * This function disables the FlexIO UART interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Interrupt source.
+ */
+void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO UARt transmit data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART transmit data register address.
+ */
+static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
+}
+
+/*!
+ * @brief Gets the FlexIO UART receive data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART receive data register address.
+ */
+static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO UART transmit DMA.
+ * This function enables/disables the FlexIO UART Tx DMA,
+ * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param enable True to enable, false to disable.
+ */
+static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO UART receive DMA.
+ * This function enables/disables the FlexIO UART Rx DMA,
+ * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param enable True to enable, false to disable.
+ */
+static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable);
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO UART module operation.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type.
+ * @param enable True to enable, false does not have any effect.
+ */
+static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*!
+ * @brief Writes one byte of data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register. Ensure that the TxEmptyFlag is asserted before calling
+ * this API.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param buffer The data bytes to send.
+ */
+static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)
+{
+    base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer;
+}
+
+/*!
+ * @brief Reads one byte of data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the RxFullFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param buffer The buffer to store the received bytes.
+ */
+static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)
+{
+    *buffer = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
+}
+
+/*!
+ * @brief Sends a buffer of data bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been sent.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param txData The data bytes to send.
+ * @param txSize The number of data bytes to send.
+ * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been received.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param rxData The buffer to store the received bytes.
+ * @param rxSize The number of data bytes to be received.
+ * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle.
+ *
+ * This function initializes the FlexIO UART handle, which can be used for other FlexIO
+ * UART transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that users can set up
+ * a RX ring buffer optionally. Data received is stored into the ring buffer even when
+ * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
+ * received in the ring buffer, users can get the received data from the ring buffer
+ * directly. The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base to FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
+                                          flexio_uart_handle_t *handle,
+                                          flexio_uart_transfer_callback_t callback,
+                                          void *userData);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, users can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
+ */
+void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
+                                         flexio_uart_handle_t *handle,
+                                         uint8_t *ringBuffer,
+                                         size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function,
+ * which returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback
+ * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter.
+ *
+ * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
+ * @retval kStatus_Success Successfully starts the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
+ */
+status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
+                                             flexio_uart_handle_t *handle,
+                                             flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. Get the remainBytes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes sent.
+ *
+ * This function gets the number of bytes sent driven by interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using the interrupt method. This is a non-blocking function,
+ * which returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter kStatus_UART_RxIdle.
+ * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
+ * the 5 bytes are copied to xfer->data. This function returns with the
+ * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param xfer UART transfer structure. See #flexio_uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
+ */
+status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                flexio_uart_transfer_t *xfer,
+                                                size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the receive data which was using IRQ.
+ *
+ * This function aborts the receive data which was using IRQ.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received driven by interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param count Number of bytes received so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count);
+
+/*!
+ * @brief FlexIO UART IRQ handler function.
+ *
+ * This function processes the FlexIO UART transmit and receives the IRQ request.
+ *
+ * @param uartType Pointer to the FLEXIO_UART_Type structure.
+ * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle);
+
+/*!
+ * @brief Flush tx/rx shifters.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ */
+void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*! @} */
+
+#endif /*FSL_FLEXIO_UART_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.c
new file mode 100644
index 0000000000..269642064d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_uart_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_dma"
+#endif
+
+/*<! @brief Structure definition for DMA callback param pass in. */
+typedef struct _flexio_uart_dma_private_handle
+{
+    FLEXIO_UART_Type *base;
+    flexio_uart_dma_handle_t *handle;
+} flexio_uart_dma_private_handle_t;
+
+/*<! @brief uart transfer state. */
+enum _flexio_uart_dma_transfer_states
+{
+    kFLEXIO_UART_TxIdle, /* TX idle. */
+    kFLEXIO_UART_TxBusy, /* TX busy. */
+    kFLEXIO_UART_RxIdle, /* RX idle. */
+    kFLEXIO_UART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*< @brief user configurable flexio uart handle count. */
+#define FLEXIO_UART_HANDLE_COUNT 2
+
+/*<! Private handle only used for internally. */
+static flexio_uart_dma_private_handle_t s_dmaPrivateHandle[FLEXIO_UART_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO UART DMA send finished callback function.
+ *
+ * This function is called when FLEXIO UART DMA send finished. It disables the UART
+ * TX DMA request and sends @ref kStatus_FLEXIO_UART_TxIdle to FLEXIO UART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_UART_TransferSendDMACallback(dma_handle_t *handle, void *param);
+
+/*!
+ * @brief FLEXIO UART DMA receive finished callback function.
+ *
+ * This function is called when FLEXIO UART DMA receive finished. It disables the FLEXIO
+ * UART RX DMA request and sends @ref kStatus_FLEXIO_UART_RxIdle to UART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_UART_TransferSendDMACallback(dma_handle_t *handle, void *param)
+{
+    flexio_uart_dma_private_handle_t *uartPrivateHandle = (flexio_uart_dma_private_handle_t *)param;
+
+    /* Disable UART TX DMA. */
+    FLEXIO_UART_EnableTxDMA(uartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    uartPrivateHandle->handle->txState = (uint8_t)kFLEXIO_UART_TxIdle;
+
+    if (uartPrivateHandle->handle->callback != NULL)
+    {
+        uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
+                                            kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData);
+    }
+}
+
+static void FLEXIO_UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
+{
+    flexio_uart_dma_private_handle_t *uartPrivateHandle = (flexio_uart_dma_private_handle_t *)param;
+
+    /* Disable UART RX DMA. */
+    FLEXIO_UART_EnableRxDMA(uartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    uartPrivateHandle->handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle;
+
+    if (uartPrivateHandle->handle->callback != NULL)
+    {
+        uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
+                                            kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData);
+    }
+}
+
+/*!
+ * brief Initializes the FLEXIO_UART handle which is used in transactional functions.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure.
+ * param handle Pointer to flexio_uart_dma_handle_t structure.
+ * param callback FlexIO UART callback, NULL means no callback.
+ * param userData User callback function data.
+ * param txDmaHandle User requested DMA handle for TX DMA transfer.
+ * param rxDmaHandle User requested DMA handle for RX DMA transfer.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO UART DMA type/handle table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandleDMA(FLEXIO_UART_Type *base,
+                                             flexio_uart_dma_handle_t *handle,
+                                             flexio_uart_dma_transfer_callback_t callback,
+                                             void *userData,
+                                             dma_handle_t *txDmaHandle,
+                                             dma_handle_t *rxDmaHandle)
+{
+    assert(handle != NULL);
+
+    dma_transfer_config_t dmaXferConfig;
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0U; index < (uint8_t)FLEXIO_UART_HANDLE_COUNT; index++)
+    {
+        if (s_dmaPrivateHandle[index].base == NULL)
+        {
+            s_dmaPrivateHandle[index].base   = base;
+            s_dmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == (uint8_t)FLEXIO_UART_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    (void)memset(handle, 0, sizeof(*handle));
+
+    handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle;
+    handle->txState = (uint8_t)kFLEXIO_UART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Set DMA channel configuration. */
+    (void)memset(&dmaXferConfig, 0, sizeof(dmaXferConfig));
+    dmaXferConfig.srcSize  = kDMA_Transfersize8bits;
+    dmaXferConfig.destSize = kDMA_Transfersize8bits;
+
+    /* Configure TX. */
+    if (txDmaHandle != NULL)
+    {
+        DMA_SetCallback(txDmaHandle, FLEXIO_UART_TransferSendDMACallback, &s_dmaPrivateHandle[index]);
+
+        DMA_ResetChannel(txDmaHandle->base, txDmaHandle->channel);
+
+        dmaXferConfig.destAddr            = FLEXIO_UART_GetTxDataRegisterAddress(base);
+        dmaXferConfig.enableSrcIncrement  = true;
+        dmaXferConfig.enableDestIncrement = false;
+        DMA_SetTransferConfig(txDmaHandle->base, txDmaHandle->channel, &dmaXferConfig);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle != NULL)
+    {
+        DMA_SetCallback(rxDmaHandle, FLEXIO_UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[index]);
+
+        DMA_ResetChannel(rxDmaHandle->base, rxDmaHandle->channel);
+
+        dmaXferConfig.destAddr            = 0U;
+        dmaXferConfig.srcAddr             = FLEXIO_UART_GetRxDataRegisterAddress(base);
+        dmaXferConfig.enableSrcIncrement  = false;
+        dmaXferConfig.enableDestIncrement = true;
+        DMA_SetTransferConfig(rxDmaHandle->base, rxDmaHandle->channel, &dmaXferConfig);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Sends data using DMA.
+ *
+ * This function send data using DMA. This is non-blocking function, which returns
+ * right away. When all data is sent out, the send callback function is called.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ * param xfer FLEXIO_UART DMA transfer structure, see #flexio_uart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferSendDMA(FLEXIO_UART_Type *base,
+                                     flexio_uart_dma_handle_t *handle,
+                                     flexio_uart_transfer_t *xfer)
+{
+    assert(handle->txDmaHandle != NULL);
+
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If previous TX not finished. */
+    if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState)
+    {
+        status = kStatus_FLEXIO_UART_TxBusy;
+    }
+    else
+    {
+        handle->txState       = (uint8_t)kFLEXIO_UART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Set transfer data address and data size. */
+        DMA_SetSourceAddress(handle->txDmaHandle->base, handle->txDmaHandle->channel, (uint32_t)xfer->data);
+        DMA_SetTransferSize(handle->txDmaHandle->base, handle->txDmaHandle->channel, xfer->dataSize);
+
+        /* Enable FLEXIO UART TX DMA. */
+        FLEXIO_UART_EnableTxDMA(base, true);
+
+        /* Enable DMA transfer complete interrupt and start transfer. */
+        DMA_EnableInterrupts(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+        DMA_EnableChannelRequest(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ * param xfer FLEXIO_UART DMA transfer structure, see #flexio_uart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXIO_UART_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferReceiveDMA(FLEXIO_UART_Type *base,
+                                        flexio_uart_dma_handle_t *handle,
+                                        flexio_uart_transfer_t *xfer)
+{
+    assert(handle->rxDmaHandle != NULL);
+
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If previous RX not finished. */
+    if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_UART_RxBusy;
+    }
+    else
+    {
+        handle->rxState       = (uint8_t)kFLEXIO_UART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Set transfer data address and data size. */
+        DMA_SetDestinationAddress(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (uint32_t)xfer->data);
+        DMA_SetTransferSize(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, xfer->dataSize);
+
+        /* Enable FLEXIO UART RX DMA. */
+        FLEXIO_UART_EnableRxDMA(base, true);
+
+        /* Enable DMA transfer complete interrupt and start transfer. */
+        DMA_EnableInterrupts(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+        DMA_EnableChannelRequest(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the sent data which using DMA.
+ *
+ * This function aborts the sent data which using DMA.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortSendDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle)
+{
+    assert(handle->txDmaHandle != NULL);
+
+    /* Disable FLEXIO UART TX DMA. */
+    FLEXIO_UART_EnableTxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_StopTransfer(handle->txDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->txState = (uint8_t)kFLEXIO_UART_TxIdle;
+}
+
+/*!
+ * brief Aborts the receive data which using DMA.
+ *
+ * This function aborts the receive data which using DMA.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortReceiveDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle)
+{
+    assert(handle->rxDmaHandle != NULL);
+
+    /* Disable FLEXIO UART RX DMA. */
+    FLEXIO_UART_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_StopTransfer(handle->rxDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes sent out.
+ *
+ * This function gets the number of bytes sent out.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ * param count Number of bytes sent so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ * param handle Pointer to flexio_uart_dma_handle_t structure
+ * param count Number of bytes received so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.h
new file mode 100644
index 0000000000..b1907f26a8
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_flexio_uart_dma.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXIO_UART_DMA_H_
+#define FSL_FLEXIO_UART_DMA_H_
+
+#include "fsl_flexio_uart.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup flexio_dma_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexIO UART DMA driver version. */
+#define FSL_FLEXIO_UART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*! @} */
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexio_uart_dma_handle flexio_uart_dma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*flexio_uart_dma_transfer_callback_t)(FLEXIO_UART_Type *base,
+                                                    flexio_uart_dma_handle_t *handle,
+                                                    status_t status,
+                                                    void *userData);
+
+/*!
+ * @brief UART DMA handle
+ */
+struct _flexio_uart_dma_handle
+{
+    flexio_uart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                               /*!< UART callback function parameter.*/
+
+    size_t txDataSizeAll; /*!< Total bytes to be sent. */
+    size_t rxDataSizeAll; /*!< Total bytes to be received. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXIO_UART handle which is used in transactional functions.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure.
+ * @param handle Pointer to flexio_uart_dma_handle_t structure.
+ * @param callback FlexIO UART callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param txDmaHandle User requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User requested DMA handle for RX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO UART DMA type/handle table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandleDMA(FLEXIO_UART_Type *base,
+                                             flexio_uart_dma_handle_t *handle,
+                                             flexio_uart_dma_transfer_callback_t callback,
+                                             void *userData,
+                                             dma_handle_t *txDmaHandle,
+                                             dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function send data using DMA. This is non-blocking function, which returns
+ * right away. When all data is sent out, the send callback function is called.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ * @param xfer FLEXIO_UART DMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferSendDMA(FLEXIO_UART_Type *base,
+                                     flexio_uart_dma_handle_t *handle,
+                                     flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ * @param xfer FLEXIO_UART DMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXIO_UART_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferReceiveDMA(FLEXIO_UART_Type *base,
+                                        flexio_uart_dma_handle_t *handle,
+                                        flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data which using DMA.
+ *
+ * This function aborts the sent data which using DMA.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortSendDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data which using DMA.
+ *
+ * This function aborts the receive data which using DMA.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortReceiveDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes sent out.
+ *
+ * This function gets the number of bytes sent out.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received.
+ *
+ * @param base Pointer to FLEXIO_UART_Type structure
+ * @param handle Pointer to flexio_uart_dma_handle_t structure
+ * @param count Number of bytes received so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCountDMA(FLEXIO_UART_Type *base,
+                                                flexio_uart_dma_handle_t *handle,
+                                                size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_UART_DMA_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_adapter.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_adapter.h
new file mode 100644
index 0000000000..94b00fb9a3
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_adapter.h
@@ -0,0 +1,400 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_ADAPTER_H
+#define FSL_FTFX_ADAPTER_H
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define INVALID_REG_MASK    (0)
+#define INVALID_REG_SHIFT   (0)
+#define INVALID_REG_ADDRESS (NULL)
+#define INVALID_REG_VALUE   (0x00U)
+
+/* @brief Flash register access type defines */
+#define FTFx_REG8_ACCESS_TYPE  volatile uint8_t *
+#define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
+
+/*!
+ * @name Common flash register info defines
+ * @{
+ */
+#if defined(FTFA)
+#define FTFx                     FTFA
+#define FTFx_BASE                FTFA_BASE
+#define FTFx_FSTAT_CCIF_MASK     FTFA_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_CCIF_SHIFT    FTFA_FSTAT_CCIF_SHIFT
+#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK   FTFA_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK   FTFA_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK  FTFA_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK       FTFA_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK     FTFA_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFE)
+#define FTFx                     FTFE
+#define FTFx_BASE                FTFE_BASE
+#define FTFx_FSTAT_CCIF_MASK     FTFE_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_CCIF_SHIFT    FTFE_FSTAT_CCIF_SHIFT
+#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK   FTFE_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK   FTFE_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK  FTFE_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK       FTFE_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK     FTFE_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFL)
+#define FTFx                     FTFL
+#define FTFx_BASE                FTFL_BASE
+#define FTFx_FSTAT_CCIF_MASK     FTFL_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_CCIF_SHIFT    FTFL_FSTAT_CCIF_SHIFT
+#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK   FTFL_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK   FTFL_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK  FTFL_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK       FTFL_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK     FTFL_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#else
+#error "Unknown flash controller"
+#endif
+/*! @} */
+
+/*!
+ * @name Common flash register access info defines
+ * @{
+ */
+#define FTFx_FCCOB3_REG (FTFx->FCCOB3)
+#define FTFx_FCCOB5_REG (FTFx->FCCOB5)
+#define FTFx_FCCOB6_REG (FTFx->FCCOB6)
+#define FTFx_FCCOB7_REG (FTFx->FCCOB7)
+
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK)
+#define FTFx_FLASH1_HAS_INT_PROT_REG (1)
+#define FTFx_FPROTSH_REG             (FTFx->FPROTSH)
+#define FTFx_FPROTSL_REG             (FTFx->FPROTSL)
+#else
+#define FTFx_FLASH1_HAS_INT_PROT_REG (0)
+#endif
+#endif
+
+#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK)
+#define FTFx_FLASH0_HAS_HIGH_PROT_REG (1)
+#define FTFx_FPROT_HIGH_REG           (FTFx->FPROTH3)
+#define FTFx_FPROTH3_REG              (FTFx->FPROTH3)
+#define FTFx_FPROTH2_REG              (FTFx->FPROTH2)
+#define FTFx_FPROTH1_REG              (FTFx->FPROTH1)
+#define FTFx_FPROTH0_REG              (FTFx->FPROTH0)
+#else
+#define FTFx_FLASH0_HAS_HIGH_PROT_REG (0)
+#endif
+
+#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3)
+#define FTFx_FPROTL3_REG   (FTFx->FPROTL3)
+#define FTFx_FPROTL2_REG   (FTFx->FPROTL2)
+#define FTFx_FPROTL1_REG   (FTFx->FPROTL1)
+#define FTFx_FPROTL0_REG   (FTFx->FPROTL0)
+#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROT3)
+#define FTFx_FPROTL3_REG   (FTFx->FPROT3)
+#define FTFx_FPROTL2_REG   (FTFx->FPROT2)
+#define FTFx_FPROTL1_REG   (FTFx->FPROT1)
+#define FTFx_FPROTL0_REG   (FTFx->FPROT0)
+#endif
+
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK)
+#define FTFx_FLASH1_HAS_INT_XACC_REG (1)
+#define FTFx_XACCSH_REG              (FTFx->XACCSH)
+#define FTFx_XACCSL_REG              (FTFx->XACCSL)
+#define FTFx_FACSSS_REG              (FTFx->FACSSS)
+#define FTFx_FACSNS_REG              (FTFx->FACSNS)
+#else
+#define FTFx_FLASH1_HAS_INT_XACC_REG (0)
+#endif
+#endif
+
+#if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \
+     defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK))
+#define FTFx_FLASH0_HAS_INT_XACC_REG (1)
+#define FTFx_XACCH3_REG              (FTFx->XACCH3)
+#define FTFx_XACCL3_REG              (FTFx->XACCL3)
+#define FTFx_FACSS_REG               (FTFx->FACSS)
+#define FTFx_FACSN_REG               (FTFx->FACSN)
+#else
+#define FTFx_FLASH0_HAS_INT_XACC_REG (0)
+#endif
+/*! @} */
+
+/*!
+ * @brief MCM cache register access info defines.
+ */
+#if defined(MCM_PLACR_CFCC_MASK)
+    #define MCM_CACHE_CLEAR_MASK  MCM_PLACR_CFCC_MASK
+    #define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT
+#else
+    #define MCM_CACHE_CLEAR_MASK  INVALID_REG_MASK
+    #define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
+#endif
+
+#if defined(MCM0)
+    #define MCM0_CACHE_REG MCM0->PLACR
+#elif defined(MCM) && (!defined(MCM1))
+    #define MCM0_CACHE_REG MCM->PLACR
+#else
+    #define MCM0_CACHE_REG        (INVALID_REG_ADDRESS)
+#endif
+
+#if defined(MCM1)
+    #define MCM1_CACHE_REG MCM1->PLACR
+#elif defined(MCM) && (!defined(MCM0))
+    #define MCM1_CACHE_REG MCM->PLACR
+#else
+    #define MCM1_CACHE_REG        (INVALID_REG_ADDRESS)
+#endif
+
+/*!
+ * @brief FMC cache register access info defines.
+ */
+#if defined(FMC_PFB01CR_S_INV_MASK)
+#define FMC_SPECULATION_INVALIDATE_MASK  FMC_PFB01CR_S_INV_MASK
+#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT
+#define FMC_SPECULATION_INVALIDATE_REG   FMC->PFB01CR
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+#define FMC_SPECULATION_INVALIDATE_MASK  FMC_PFB01CR_S_B_INV_MASK
+#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
+#define FMC_SPECULATION_INVALIDATE_REG   FMC->PFB01CR
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+#define FMC_SPECULATION_INVALIDATE_MASK  FMC_PFB0CR_S_INV_MASK
+#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT
+#define FMC_SPECULATION_INVALIDATE_REG   FMC->PFB0CR
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_SPECULATION_INVALIDATE_MASK  FMC_PFB0CR_S_B_INV_MASK
+#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT
+#define FMC_SPECULATION_INVALIDATE_REG   FMC->PFB0CR
+#else
+#define FMC_SPECULATION_INVALIDATE_MASK  INVALID_REG_MASK
+#define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT
+#define FMC_SPECULATION_INVALIDATE(x)    (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
+#define FMC_SPECULATION_INVALIDATE_REG   (INVALID_REG_ADDRESS)
+#endif
+
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+#define FMC_CACHE_CLEAR_MASK  FMC_PFB01CR_CINV_WAY_MASK
+#define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
+#define FMC_CACHE_CLEAR(x)    FMC_PFB01CR_CINV_WAY(x)
+#elif defined(FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_CACHE_CLEAR_MASK  FMC_PFB0CR_CINV_WAY_MASK
+#define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT
+#define FMC_CACHE_CLEAR(x)    FMC_PFB0CR_CINV_WAY(x)
+#else
+#define FMC_CACHE_CLEAR_MASK  INVALID_REG_MASK
+#define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
+#define FMC_CACHE_CLEAR(x)    (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
+#endif
+
+#if defined(FMC_PFB01CR_B0DPE_MASK)
+#define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
+#define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
+#define FMC_CACHE_REG        FMC->PFB01CR
+#elif defined(FMC_PFB0CR_B0DPE_MASK)
+#define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK
+#define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK
+#define FMC_CACHE_REG        FMC->PFB0CR
+#else
+#define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK
+#define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK
+#define FMC_CACHE_REG        (INVALID_REG_ADDRESS)
+#endif
+
+/*!
+ * @brief MSCM cache register access info defines.
+ */
+#if defined(MSCM_OCMDR_OCM1_MASK)
+#define MSCM_SPECULATION_SET_MASK  MSCM_OCMDR_OCM1_MASK
+#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT
+#define MSCM_SPECULATION_SET(x)    MSCM_OCMDR_OCM1(x)
+#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)
+#define MSCM_SPECULATION_SET_MASK  MSCM_OCMDR0_OCM1_MASK
+#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT
+#define MSCM_SPECULATION_SET(x)    MSCM_OCMDR0_OCM1(x)
+#elif defined(MSCM_OCMDR_OCMC1_MASK)
+#define MSCM_SPECULATION_SET_MASK  MSCM_OCMDR_OCMC1_MASK
+#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT
+#define MSCM_SPECULATION_SET(x)    MSCM_OCMDR_OCMC1(x)
+#else
+#define MSCM_SPECULATION_SET_MASK  INVALID_REG_MASK
+#define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT
+#define MSCM_SPECULATION_SET(x)    (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
+#endif
+
+#if defined(MSCM_OCMDR_OCM2_MASK)
+#define MSCM_CACHE_CLEAR_MASK  MSCM_OCMDR_OCM2_MASK
+#define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT
+#define MSCM_CACHE_CLEAR(x)    MSCM_OCMDR_OCM2(x)
+#else
+#define MSCM_CACHE_CLEAR_MASK  INVALID_REG_MASK
+#define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
+#define MSCM_CACHE_CLEAR(x)    (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
+#endif
+
+#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK)
+#define MSCM_OCMDR0_REG MSCM->OCMDR[0]
+#define MSCM_OCMDR1_REG MSCM->OCMDR[1]
+#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)
+#define MSCM_OCMDR0_REG MSCM->OCMDR0
+#define MSCM_OCMDR1_REG MSCM->OCMDR1
+#else
+#define MSCM_OCMDR0_REG (INVALID_REG_ADDRESS)
+#define MSCM_OCMDR1_REG (INVALID_REG_ADDRESS)
+#endif
+
+/*!
+ * @brief MSCM prefetch speculation defines.
+ */
+#define MSCM_OCMDR_OCMC1_DFDS_MASK  (0x10U)
+#define MSCM_OCMDR_OCMC1_DFCS_MASK  (0x20U)
+#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U)
+#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U)
+
+/*!
+ * @brief SIM PFSIZE register access info defines.
+ */
+#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK)
+#define SIM_FLASH0_PFSIZE_MASK  SIM_FCFG1_CORE0_PFSIZE_MASK
+#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT
+#define SIM_FCFG1_REG           SIM->FCFG1
+#elif defined(SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FLASH0_PFSIZE_MASK  SIM_FCFG1_PFSIZE_MASK
+#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT
+#define SIM_FCFG1_REG           SIM->FCFG1
+#else
+#define SIM_FLASH0_PFSIZE_MASK  INVALID_REG_MASK
+#define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT
+#define SIM_FCFG1_REG           INVALID_REG_VALUE
+#endif
+
+#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK)
+#define SIM_FLASH1_PFSIZE_MASK  SIM_FCFG1_CORE1_PFSIZE_MASK
+#define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT
+#else
+#define SIM_FLASH1_PFSIZE_MASK  INVALID_REG_MASK
+#define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT
+#endif
+
+/*!
+ * @name Dual core/flash configuration
+ * @{
+ */
+/*! @brief Redefines some flash features. */
+#if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID)
+#if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u)
+#define FLASH0_FEATURE_PFLASH_START_ADDRESS                FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT                  FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
+#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE                   FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
+#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT      FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
+#define FLASH1_FEATURE_PFLASH_START_ADDRESS                FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS
+#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT                  FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT
+#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE                   FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE
+#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \
+    defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)
+#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT
+#else
+#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#endif
+#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT
+#elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u)
+#define FLASH0_FEATURE_PFLASH_START_ADDRESS         FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS
+#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT           FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT
+#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE            FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE     FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE
+#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \
+    defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)
+#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT
+#else
+#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#endif
+#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT      FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT
+#define FLASH1_FEATURE_PFLASH_START_ADDRESS                FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT                  FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
+#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE                   FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
+#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT      FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
+#endif
+#else /* undfine FSL_FEATURE_FLASH_CURRENT_CORE_ID */
+#define FLASH0_FEATURE_PFLASH_START_ADDRESS                FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT                  FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
+#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE                   FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
+#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
+#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT      FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#define FLASH1_FEATURE_PFLASH_START_ADDRESS                FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS
+#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT                  FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT
+#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE                   FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE
+#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE
+#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
+#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT      FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
+#else /* undfine FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH or FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS */
+#define FLASH1_FEATURE_PFLASH_START_ADDRESS                0
+#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT                  0
+#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE                   0
+#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE            0
+#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE        0
+#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT  0
+#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0
+#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT      0
+#endif
+#endif
+
+#if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT
+#define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT
+#else
+#define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT
+#endif
+
+/*! @} */
+
+#endif /* FSL_FTFX_ADAPTER_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.c
new file mode 100644
index 0000000000..3912c3de52
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "fsl_ftfx_cache.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash"
+#endif
+
+/*!
+ * @name Flash cache and speculation control defines
+ * @{
+ */
+#if defined(MCM_PLACR_CFCC_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1u)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0u)
+#endif
+
+#define FLASH_CACHE_IS_CONTROLLED_BY_MSCM (0u)
+
+#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1u)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0u)
+#endif
+
+#if defined(MCM_PLACR_DFCS_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1u)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0u)
+#endif
+
+#if defined(MSCM_OCMDR_OCMC1_MASK) || defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR0_OCM1_MASK) || \
+    defined(MSCM_OCMDR1_OCM1_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1u)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0u)
+#endif
+
+#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \
+    defined(FMC_PFB01CR_S_B_INV_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1u)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0u)
+#endif
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC || \
+    FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_FMC || FLASH_CACHE_IS_CONTROLLED_BY_MSCM
+#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (1)
+#else
+#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (0u)
+#endif
+/*@}*/
+
+/*! @brief A function pointer used to point to relocated ftfx_common_bit_operation() */
+typedef void (*callftfxCommonBitOperation_t)(FTFx_REG32_ACCESS_TYPE base,
+                                             uint32_t bitMask,
+                                             uint32_t bitShift,
+                                             uint32_t bitValue);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(ftfx_cache_config_t *config);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
+/*! @brief Performs the cache clear to the flash by MSCM.*/
+void mscm_flash_cache_clear(ftfx_cache_config_t *config);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(ftfx_cache_config_t *config);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && \
+       (FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_MSCM || \
+        FLASH_CACHE_IS_CONTROLLERD_BY_FMC || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || \
+        FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC)
+static void ftfx_common_bit_operation_command_sequence(
+    ftfx_cache_config_t *config, FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t bitValue);
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
+/*! @brief Copy flash_cache_clear_command() to RAM*/
+static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation);
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
+/*!
+ * @brief Position independent code of ftfx_common_bit_operation()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void ftfx_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t
+ * bitValue)
+ *   {
+ *       if (bitMask)
+ *       {
+ *           uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask);
+ *           *base = (*base & (~bitMask)) | value;
+ *       }
+ *
+ *       __ISB();
+ *       __DSB();
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+static const uint32_t s_ftfxCommonBitOperationFunctionCode[] = {
+    0x2900b510u, 0x6804d005u, 0x4093438cu, 0x43214019u, 0xf3bf6001u, 0xf3bf8f6fu, 0xbd108f4fu,
+};
+
+#if (!FTFx_DRIVER_IS_EXPORTED)
+/*! @brief A static buffer used to hold ftfx_common_bit_operation() */
+static uint32_t s_ftfxCommonBitOperation[kFTFx_CACHE_RamFuncMaxSizeInWords];
+#endif /* (!FTFx_DRIVER_IS_EXPORTED) */
+#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t FTFx_CACHE_Init(ftfx_cache_config_t *config)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+/* copy required flash commands to RAM */
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
+    if (NULL == config->bitOperFuncAddr.callFlashCommand)
+    {
+#if FTFx_DRIVER_IS_EXPORTED
+        return kStatus_FTFx_ExecuteInRamFunctionNotReady;
+#else
+        config->bitOperFuncAddr.commadAddr = (uint32_t)s_ftfxCommonBitOperation;
+#endif /* FTFx_DRIVER_IS_EXPORTED */
+    }
+
+    ftfx_copy_common_bit_operation_to_ram((uint32_t *)config->bitOperFuncAddr.commadAddr);
+#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Flash Cache/Prefetch/Speculation Clear Process
+ *
+ * This function is used to perform the cache and prefetch speculation clear process to the flash.
+ */
+status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess)
+{
+    /* We pass the ftfx register address as a parameter to ftfx_common_bit_operation() instead of using
+     * pre-processed MACROs or a global variable in ftfx_common_bit_operation()
+     * to make sure that ftfx_common_bit_operation() will be compiled into position-independent code (PIC). */
+    if (!isPreProcess)
+    {
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+        mcm_flash_cache_clear(config);
+#endif
+#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
+        mscm_flash_cache_clear(config);
+#endif
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+        fmc_flash_cache_clear(config);
+#endif
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(config, true);
+#endif
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+        fmc_flash_prefetch_speculation_clear(config);
+#endif
+    }
+    if (isPreProcess)
+    {
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(config, false);
+#endif
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus)
+{
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        if (true == speculationStatus->instructionOff)
+        {
+            if (false == speculationStatus->dataOff)
+            {
+                return kStatus_FTFx_InvalidSpeculationOption;
+            }
+            else
+            {
+                MCM0_CACHE_REG |= MCM_PLACR_DFCS_MASK;
+            }
+        }
+        else
+        {
+            MCM0_CACHE_REG &= ~MCM_PLACR_DFCS_MASK;
+            if (false == speculationStatus->dataOff)
+            {
+                MCM0_CACHE_REG |= MCM_PLACR_EFDS_MASK;
+            }
+            else
+            {
+                MCM0_CACHE_REG &= ~MCM_PLACR_EFDS_MASK;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        if (false == speculationStatus->instructionOff)
+        {
+            FMC_CACHE_REG |= FMC_CACHE_B0IPE_MASK;
+        }
+        else
+        {
+            FMC_CACHE_REG &= ~FMC_CACHE_B0IPE_MASK;
+        }
+        if (false == speculationStatus->dataOff)
+        {
+            FMC_CACHE_REG |= FMC_CACHE_B0DPE_MASK;
+        }
+        else
+        {
+            FMC_CACHE_REG &= ~FMC_CACHE_B0DPE_MASK;
+        }
+
+        /* Invalidate Prefetch Speculation Buffer */
+        FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK;
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+    {
+        if (true == speculationStatus->instructionOff)
+        {
+            if (false == speculationStatus->dataOff)
+            {
+                return kStatus_FTFx_InvalidSpeculationOption;
+            }
+            else
+            {
+                MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFCS_MASK;
+            }
+        }
+        else
+        {
+            MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFCS_MASK;
+            if (false == speculationStatus->dataOff)
+            {
+                MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFDS_MASK;
+            }
+            else
+            {
+                MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFDS_MASK;
+            }
+        }
+    }
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+
+    return kStatus_FTFx_Success;
+}
+
+status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus)
+{
+    (void)memset(speculationStatus, 0, sizeof(ftfx_prefetch_speculation_status_t));
+
+    /* Assuming that all speculation options are enabled. */
+    speculationStatus->instructionOff = false;
+    speculationStatus->dataOff        = false;
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        uint32_t value = MCM0_CACHE_REG;
+        if (0U != (value & MCM_PLACR_DFCS_MASK))
+        {
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOff = true;
+            speculationStatus->dataOff        = true;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (0U == (value & MCM_PLACR_EFDS_MASK))
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOff = true;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        uint32_t value = FMC_CACHE_REG;
+        if (0U == (value & FMC_CACHE_B0DPE_MASK))
+        {
+            /* Do not prefetch in response to data references. */
+            speculationStatus->dataOff = true;
+        }
+        if (0U == (value & FMC_CACHE_B0IPE_MASK))
+        {
+            /* Do not prefetch in response to instruction fetches. */
+            speculationStatus->instructionOff = true;
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+    {
+        uint32_t value = MSCM_OCMDR0_REG;
+        if (0U != (value & MSCM_OCMDR_OCMC1_DFCS_MASK))
+        {
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOff = true;
+            speculationStatus->dataOff        = true;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (0U != (value & MSCM_OCMDR_OCMC1_DFDS_MASK))
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOff = true;
+            }
+        }
+    }
+#endif
+
+    return kStatus_FTFx_Success;
+}
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
+/*! @brief Copy PIC of ftfx_common_bit_operation() to RAM */
+static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation)
+{
+    assert(sizeof(s_ftfxCommonBitOperationFunctionCode) <= ((uint32_t)kFTFx_CACHE_RamFuncMaxSizeInWords * 4U));
+
+    (void)memcpy(ftfxCommonBitOperation, s_ftfxCommonBitOperationFunctionCode,
+                 sizeof(s_ftfxCommonBitOperationFunctionCode));
+}
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE */
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT && \
+       (FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_MSCM || \
+        FLASH_CACHE_IS_CONTROLLERD_BY_FMC || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || \
+        FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC)
+static void ftfx_common_bit_operation_command_sequence(
+    ftfx_cache_config_t *config, FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t bitValue)
+{
+    uint32_t *ftfxCommonBitOperationAddr;
+    ftfxCommonBitOperationAddr = &config->bitOperFuncAddr.commadAddr;
+    /* Since the value of ARM function pointer is always odd, but the real start
+     * address
+     * of function memory should be even, that's why +1 operation exist. */
+    *ftfxCommonBitOperationAddr += 1UL;
+    callftfxCommonBitOperation_t ftfxCommonBitOperationCommand = config->bitOperFuncAddr.callFlashCommand;
+    /* Workround for some devices which doesn't need this function */
+    ftfxCommonBitOperationCommand((FTFx_REG32_ACCESS_TYPE)base, bitMask, bitShift, bitValue);
+    *ftfxCommonBitOperationAddr -= 1UL;
+}
+#endif /*FTFx_DRIVER_IS_FLASH_RESIDENT*/
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(ftfx_cache_config_t *config)
+{
+    FTFx_REG32_ACCESS_TYPE regBase;
+
+#if defined(MCM0_CACHE_REG)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG;
+#elif defined(MCM1_CACHE_REG)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG;
+#endif
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    /* calling flash command sequence function to execute the command */
+    ftfx_common_bit_operation_command_sequence(config, regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1UL);
+
+#else  /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
+    *regBase |= MCM_CACHE_CLEAR_MASK;
+
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
+/*! @brief Performs the cache clear to the flash by MSCM.*/
+void mscm_flash_cache_clear(ftfx_cache_config_t *config)
+{
+    uint8_t setValue = 0x1U;
+
+/* The OCMDR[0] is always used to cache main Pflash*/
+/* For device with FlexNVM support, the OCMDR[1] is used to cache Dflash.
+ * For device with secondary flash support, the OCMDR[1] is used to cache secondary Pflash. */
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    switch (config->flashMemoryIndex)
+    {
+        case kFLASH_MemoryIndexSecondaryFlash:
+            /* calling flash command sequence function to execute the command */
+            ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG,
+                                                       MSCM_CACHE_CLEAR_MASK, MSCM_CACHE_CLEAR_SHIFT, setValue);
+            break;
+        case kFLASH_MemoryIndexPrimaryFlash:
+        default:
+            /* calling flash command sequence function to execute the command */
+            ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG,
+                                                       MSCM_CACHE_CLEAR_MASK, MSCM_CACHE_CLEAR_SHIFT, setValue);
+            break;
+    }
+#else  /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
+    switch (config->flashMemoryIndex)
+    {
+        case kFLASH_MemoryIndexSecondaryFlash:
+            MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue);
+            /* Each cache clear instruction should be followed by below code*/
+            __ISB();
+            __DSB();
+            break;
+        case kFLASH_MemoryIndexPrimaryFlash:
+        default:
+            MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue);
+            /* Memory barriers for good measure.
+             * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+            __ISB();
+            __DSB();
+            break;
+    }
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(ftfx_cache_config_t *config)
+{
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    /* calling flash command sequence function to execute the command */
+    ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&FMC_CACHE_REG, FMC_CACHE_CLEAR_MASK,
+                                               FMC_CACHE_CLEAR_SHIFT, 0xFUL);
+#else  /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
+    FMC_CACHE_REG = (FMC_CACHE_REG & (~FMC_CACHE_CLEAR_MASK)) | FMC_CACHE_CLEAR(~0);
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable)
+{
+    uint8_t setValue;
+    if (enable)
+    {
+        setValue = 0x0U;
+    }
+    else
+    {
+        setValue = 0x3U;
+    }
+
+/* The OCMDR[0] is always used to prefetch main Pflash*/
+/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash.
+ * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+
+    switch (config->flashMemoryIndex)
+    {
+        case 1:
+            /* calling flash command sequence function to execute the command */
+            ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG,
+                                                       MSCM_SPECULATION_SET_MASK, MSCM_SPECULATION_SET_SHIFT, setValue);
+            break;
+        case 0:
+        default:
+            /* calling flash command sequence function to execute the command */
+            ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG,
+                                                       MSCM_SPECULATION_SET_MASK, MSCM_SPECULATION_SET_SHIFT, setValue);
+            break;
+    }
+#else  /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
+    switch (config->flashMemoryIndex)
+    {
+        case kFLASH_MemoryIndexSecondaryFlash:
+            MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue);
+            /* Each cache clear instruction should be followed by below code*/
+            __ISB();
+            __DSB();
+            break;
+        case kFLASH_MemoryIndexPrimaryFlash:
+        default:
+            MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue);
+            /* Memory barriers for good measure.
+             * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+            __ISB();
+            __DSB();
+            break;
+    }
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config)
+{
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    /* calling flash command sequence function to execute the command */
+    ftfx_common_bit_operation_command_sequence(config, (FTFx_REG32_ACCESS_TYPE)&FMC_SPECULATION_INVALIDATE_REG,
+                                               FMC_SPECULATION_INVALIDATE_MASK, FMC_SPECULATION_INVALIDATE_SHIFT, 1UL);
+#else  /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
+    FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK;
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.h
new file mode 100644
index 0000000000..0bba177d4e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_cache.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_CACHE_H
+#define FSL_FTFX_CACHE_H
+
+#include "fsl_ftfx_controller.h"
+
+/*!
+ * @addtogroup ftfx_cache_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief FTFx prefetch speculation status.
+ */
+typedef struct _flash_prefetch_speculation_status
+{
+    bool instructionOff; /*!< Instruction speculation.*/
+    bool dataOff;        /*!< Data speculation.*/
+} ftfx_prefetch_speculation_status_t;
+
+/*!
+ * @brief Constants for execute-in-RAM flash function.
+ */
+enum _ftfx_cache_ram_func_constants
+{
+    kFTFx_CACHE_RamFuncMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/
+};
+
+typedef union
+{
+    uint32_t commadAddr;
+    void (*callFlashCommand)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t bitValue);
+} function_bit_operation_ptr_t;
+
+/*! @brief FTFx cache driver state information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _ftfx_cache_config
+{
+    uint8_t flashMemoryIndex; /*!< 0 - primary flash; 1 - secondary flash*/
+    uint8_t reserved[3];
+    function_bit_operation_ptr_t bitOperFuncAddr; /*!< An buffer point to the flash execute-in-RAM function. */
+} ftfx_cache_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the global FTFx cache structure members.
+ *
+ * This function checks and initializes the Flash module for the other FTFx cache APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ */
+status_t FTFx_CACHE_Init(ftfx_cache_config_t *config);
+
+/*!
+ * @brief Process the cache/prefetch/speculation to the flash.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param isPreProcess The possible option used to control flash cache/prefetch/speculation
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ */
+status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess);
+
+/*!
+ * @brief Sets the PFlash prefetch speculation to the intended speculation status.
+ *
+ * @param speculationStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidSpeculationOption An invalid speculation option argument is provided.
+ */
+status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus);
+
+/*!
+ * @brief Gets the PFlash prefetch speculation status.
+ *
+ * @param speculationStatus  Speculation status returned by the PFlash IP.
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ */
+status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FTFX_CACHE_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.c
new file mode 100644
index 0000000000..42a322a28e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.c
@@ -0,0 +1,1510 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "fsl_ftfx_controller.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash"
+#endif
+
+/*!
+ * @name Flash controller command numbers
+ * @{
+ */
+#define FTFx_VERIFY_BLOCK                    0x00U /*!< RD1BLK*/
+#define FTFx_VERIFY_SECTION                  0x01U /*!< RD1SEC*/
+#define FTFx_PROGRAM_CHECK                   0x02U /*!< PGMCHK*/
+#define FTFx_READ_RESOURCE                   0x03U /*!< RDRSRC*/
+#define FTFx_PROGRAM_LONGWORD                0x06U /*!< PGM4*/
+#define FTFx_PROGRAM_PHRASE                  0x07U /*!< PGM8*/
+#define FTFx_ERASE_BLOCK                     0x08U /*!< ERSBLK*/
+#define FTFx_ERASE_SECTOR                    0x09U /*!< ERSSCR*/
+#define FTFx_PROGRAM_SECTION                 0x0BU /*!< PGMSEC*/
+#define FTFx_GENERATE_CRC                    0x0CU /*!< CRCGEN*/
+#define FTFx_VERIFY_ALL_BLOCK                0x40U /*!< RD1ALL*/
+#define FTFx_READ_ONCE                       0x41U /*!< RDONCE or RDINDEX*/
+#define FTFx_PROGRAM_ONCE                    0x43U /*!< PGMONCE or PGMINDEX*/
+#define FTFx_ERASE_ALL_BLOCK                 0x44U /*!< ERSALL*/
+#define FTFx_SECURITY_BY_PASS                0x45U /*!< VFYKEY*/
+#define FTFx_SWAP_CONTROL                    0x46U /*!< SWAP*/
+#define FTFx_ERASE_ALL_BLOCK_UNSECURE        0x49U /*!< ERSALLU*/
+#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/
+#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT  0x4BU /*!< ERSXA*/
+#define FTFx_PROGRAM_PARTITION               0x80U /*!< PGMPART*/
+#define FTFx_SET_FLEXRAM_FUNCTION            0x81U /*!< SETRAM*/
+/*@}*/
+
+/*!
+ * @brief Constants for execute-in-RAM flash function.
+ */
+enum _ftfx_ram_func_constants
+{
+    kFTFx_RamFuncMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/
+};
+
+/*! @brief A function pointer used to point to relocated flash_run_command() */
+typedef void (*callFtfxRunCommand_t)(FTFx_REG8_ACCESS_TYPE ftfx_fstat);
+
+/*!
+ * @name Enumeration for Flash security register code
+ * @{
+ */
+enum _ftfx_fsec_register_code
+{
+    kFTFx_FsecRegCode_KEYEN_Enabled = 0x80U,
+    kFTFx_FsecRegCode_SEC_Unsecured = 0x02U
+};
+/*@}*/
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Enumeration for flash config area.
+ */
+enum _ftfx_pflash_config_area_range
+{
+    kFTFx_PflashConfigAreaStart = 0x400U,
+    kFTFx_PflashConfigAreaEnd   = 0x40FU
+};
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*! @brief Init IFR memory related info */
+static void ftfx_init_ifr(ftfx_config_t *config);
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+/*! @brief Copy flash_run_command() to RAM*/
+static void ftfx_copy_run_command_to_ram(uint32_t *ftfxRunCommand);
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Internal function Flash command sequence. Called by driver APIs only*/
+static status_t ftfx_command_sequence(ftfx_config_t *config);
+
+/*! @brief Internal function Flash asynchronous command sequence. Called by driver APIs only*/
+static void ftfx_command_sequence_non_blocking(ftfx_config_t *config);
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t ftfx_check_mem_range(ftfx_config_t *config,
+                                     uint32_t startAddress,
+                                     uint32_t lengthInBytes,
+                                     uint8_t alignmentBaseline);
+
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t ftfx_check_user_key(uint32_t key);
+
+/*! @brief Reads word from byte address.*/
+static uint32_t ftfx_read_word_from_byte_address(const uint8_t *src);
+
+/*! @brief Writes word to byte address.*/
+static void ftfx_write_word_to_byte_address(uint8_t *dst, uint32_t word);
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*! @brief Validates the range of the given resource address.*/
+static status_t ftfx_check_resource_range(ftfx_config_t *config,
+                                          uint32_t start,
+                                          uint32_t lengthInBytes,
+                                          uint32_t alignmentBaseline,
+                                          ftfx_read_resource_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*! @brief Validates the given flexram function option.*/
+static inline status_t ftfx_check_flexram_function_option(ftfx_flexram_func_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*! @brief Validates the given swap control option.*/
+static status_t ftfx_check_swap_control_option(ftfx_swap_control_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Position independent code of flash_run_command
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat)
+ *   {
+ *       *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+ *
+ *       while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+ *       {
+ *       }
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+static const uint32_t s_ftfxRunCommandFunctionCode[] = {
+    0x70012180u,
+    0x420a7802u,
+    0x4770d0fcu,
+};
+#if (!FTFx_DRIVER_IS_EXPORTED)
+/*! @brief A static buffer used to hold flash_run_command() */
+static uint32_t s_ftfxRunCommand[kFTFx_RamFuncMaxSizeInWords];
+#endif /* (!FTFx_DRIVER_IS_EXPORTED) */
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Access to FTFx Registers */
+static volatile uint32_t *const kFCCOBx = (volatile uint32_t *)(uint32_t)&FTFx_FCCOB3_REG;
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+/*! @brief Table of eeprom sizes. */
+static const uint16_t kEepromDensities[16] = {
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101,
+    FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110, FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111};
+/*! @brief Table of dflash sizes. */
+static const uint32_t kDflashDensities[16] = {
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101,
+    FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110, FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111};
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ */
+void FTFx_API_Init(ftfx_config_t *config)
+{
+    if (config == NULL)
+    {
+        return;
+    }
+    config->runCmdFuncAddr.callFlashCommand = NULL;
+    config->flexramBlockBase                = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS;
+    config->flexramTotalSize                = FSL_FEATURE_FLASH_FLEX_RAM_SIZE;
+
+    /* copy required flash command to RAM */
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    config->runCmdFuncAddr.commadAddr = (uint32_t)s_ftfxRunCommand;
+    ftfx_copy_run_command_to_ram((uint32_t *)config->runCmdFuncAddr.commadAddr);
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+    ftfx_init_ifr(config);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+/*!
+ * @brief Updates FlexNVM memory partition status according to data flash 0 IFR.
+ */
+status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config)
+{
+    struct _dflash_ifr_field_config
+    {
+        uint32_t reserved0;
+        uint8_t FlexNVMPartitionCode;
+        uint8_t EEPROMDataSetSize;
+        uint16_t reserved1;
+    } dataIFRReadOut;
+    uint32_t flexnvmInfoIfrAddr;
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    flexnvmInfoIfrAddr =
+        config->ifrDesc.resRange.dflashIfrStart + config->ifrDesc.resRange.ifrMemSize - sizeof(dataIFRReadOut);
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+    /* Get FlexNVM memory partition info from data flash IFR */
+    returnCode = FTFx_CMD_ReadResource(config, flexnvmInfoIfrAddr, (uint8_t *)&dataIFRReadOut, sizeof(dataIFRReadOut),
+                                       kFTFx_ResourceOptionFlashIfr);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return kStatus_FTFx_PartitionStatusUpdateFailure;
+    }
+#else
+#error "Cannot get FlexNVM memory partition info"
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+    /* Fill out partitioned EEPROM size */
+    dataIFRReadOut.EEPROMDataSetSize &= 0x0FU;
+    config->eepromTotalSize = kEepromDensities[dataIFRReadOut.EEPROMDataSetSize];
+
+    /* Fill out partitioned DFlash size */
+    dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU;
+    config->flashDesc.totalSize = kDflashDensities[dataIFRReadOut.FlexNVMPartitionCode];
+
+    return kStatus_FTFx_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+/*!
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
+ */
+status_t FTFx_CMD_Erase(ftfx_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+    uint32_t sectorSize;
+    uint32_t endAddress;      /* storing end address */
+    uint32_t numberOfSectors; /* number of sectors calculated by endAddress */
+    status_t returnCode;
+    uint32_t eraseStart;
+
+    /* Check the supplied address range. */
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, config->opsConfig.addrAligment.sectorCmd);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* Validate the user key */
+    returnCode = ftfx_check_user_key(key);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    eraseStart = config->opsConfig.convertedAddress;
+    sectorSize = config->flashDesc.sectorSize;
+
+    /* Calculate Flash end address */
+    endAddress = eraseStart + lengthInBytes - 1U;
+
+    /* re-calculate the endAddress and align it to the start of the next sector
+     * which will be used in the comparison below */
+    if (0U != (endAddress % sectorSize))
+    {
+        numberOfSectors = endAddress / sectorSize + 1U;
+        endAddress      = numberOfSectors * sectorSize - 1U;
+    }
+
+    /* the start address will increment to the next sector address
+     * until it reaches the endAdddress */
+    while (eraseStart <= endAddress)
+    {
+        /* preparing passing parameter to erase a flash block */
+        kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_SECTOR, eraseStart);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+
+        /* checking the success of command execution */
+        if (kStatus_FTFx_Success != returnCode)
+        {
+            break;
+        }
+        else
+        {
+            /* Increment to the next sector */
+            eraseStart += sectorSize;
+        }
+    }
+
+    return returnCode;
+}
+
+/*!
+ * @brief erases one flash sector size based on the start address.
+ */
+status_t FTFx_CMD_EraseSectorNonBlocking(ftfx_config_t *config, uint32_t start, uint32_t key)
+{
+    uint32_t eraseStart;
+    uint8_t aligmentInBytes;
+    status_t returnCode    = kStatus_FTFx_AddressError;
+    aligmentInBytes        = config->opsConfig.addrAligment.sectorCmd;
+    uint32_t lengthInBytes = config->flashDesc.sectorSize;
+
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+    /* Validate the user key */
+    returnCode = ftfx_check_user_key(key);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    eraseStart = config->opsConfig.convertedAddress;
+
+    /* preparing passing parameter to erase a flash block */
+    kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_SECTOR, eraseStart);
+    /* calling flash command sequence function to execute the command */
+    ftfx_command_sequence_non_blocking(config);
+
+    return returnCode;
+}
+
+/*!
+ * @brief Erases entire flash
+ */
+status_t FTFx_CMD_EraseAll(ftfx_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* preparing passing parameter to erase all flash blocks */
+    kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = ftfx_check_user_key(key);
+    if (kStatus_FTFx_Success != returnCode)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+    /* Data flash IFR will be erased by erase all command, so we need to
+     *  update FlexNVM memory partition status synchronously */
+    if (returnCode == kStatus_FTFx_Success)
+    {
+        if (config->ifrDesc.resRange.dflashIfrStart != config->ifrDesc.resRange.pflashIfrStart)
+        {
+            returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(config);
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+    return returnCode;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flash, including protected sectors.
+ */
+status_t FTFx_CMD_EraseAllUnsecure(ftfx_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Prepare passing parameter to erase all flash blocks (unsecure). */
+    kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = ftfx_check_user_key(key);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+    /* Data flash IFR will be erased by erase all unsecure command, so we need to
+     *  update FlexNVM memory partition status synchronously */
+    if (returnCode == kStatus_FTFx_Success)
+    {
+        if (config->ifrDesc.resRange.dflashIfrStart != config->ifrDesc.resRange.pflashIfrStart)
+        {
+            returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(config);
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+/*!
+ * @brief Erases all program flash execute-only segments defined by the FXACC registers.
+ */
+status_t FTFx_CMD_EraseAllExecuteOnlySegments(ftfx_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* preparing passing parameter to erase all execute-only segments
+     * 1st element for the FCCOB register */
+    kFCCOBx[0] = BYTE2WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = ftfx_check_user_key(key);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+    return returnCode;
+}
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ */
+status_t FTFx_CMD_Program(ftfx_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    uint8_t blockWriteUnitSize = config->opsConfig.addrAligment.blockWriteUnitSize;
+    uint32_t programStart;
+    uint32_t remainingLength;
+    if (src == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Check the supplied address range. */
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, blockWriteUnitSize);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    programStart    = config->opsConfig.convertedAddress;
+    remainingLength = lengthInBytes;
+
+    while (remainingLength > 0U)
+    {
+        /* preparing passing parameter to program the flash block */
+        kFCCOBx[1] = ftfx_read_word_from_byte_address((const uint8_t *)src);
+        src        = &src[4];
+
+        if (4U == blockWriteUnitSize)
+        {
+            kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_LONGWORD, programStart);
+        }
+        else if (8U == blockWriteUnitSize)
+        {
+            kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t *)src);
+            src        = &src[4];
+            kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_PHRASE, programStart);
+        }
+        else
+        {
+            return kStatus_FTFx_InvalidArgument;
+        }
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+
+        /* checking for the success of command execution */
+        if (kStatus_FTFx_Success != returnCode)
+        {
+            break;
+        }
+        else
+        {
+            /* update programStart address for next iteration */
+            programStart += blockWriteUnitSize;
+
+            /* update remainingLength for next iteration */
+            remainingLength -= blockWriteUnitSize;
+        }
+    }
+
+    return returnCode;
+}
+
+/*!
+ * @brief Programs Program Once Field through parameters.
+ */
+status_t FTFx_CMD_ProgramOnce(ftfx_config_t *config, uint32_t index, const uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (src == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* pass parameters to FTFx */
+    kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU);
+
+    kFCCOBx[1] = ftfx_read_word_from_byte_address((const uint8_t *)src);
+
+    /* Note: Have to separate the first index from the rest if it equals 0
+     * to avoid a pointless comparison of unsigned int to 0 compiler warning */
+    if (config->ifrDesc.feature.has8ByteIdxSupport != 0U)
+    {
+        if (config->ifrDesc.feature.has4ByteIdxSupport != 0U)
+        {
+            if (((index == config->ifrDesc.idxInfo.mix8byteIdxStart) ||
+                 ((index >= ((uint32_t)config->ifrDesc.idxInfo.mix8byteIdxStart + 1U)) &&
+                  (index <= config->ifrDesc.idxInfo.mix8byteIdxEnd))) &&
+                (lengthInBytes == 8U))
+            {
+                kFCCOBx[2] = ftfx_read_word_from_byte_address(&src[4]);
+            }
+        }
+        else
+        {
+            kFCCOBx[2] = ftfx_read_word_from_byte_address(&src[4]);
+        }
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+    return returnCode;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ */
+status_t FTFx_CMD_ProgramSection(ftfx_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    uint32_t sectorSize;
+    uint32_t programaddress;
+    uint8_t aligmentInBytes   = config->opsConfig.addrAligment.sectionCmd;
+    const uint8_t *srcaddress = src;
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    bool needSwitchFlexRamMode = false;
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    if (srcaddress == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Check the supplied address range. */
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    programaddress = config->opsConfig.convertedAddress;
+    sectorSize     = config->flashDesc.sectorSize;
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    /* Switch function of FlexRAM if needed */
+    if ((FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK) == 0U)
+    {
+        needSwitchFlexRamMode = true;
+
+        returnCode = FTFx_CMD_SetFlexramFunction(config, kFTFx_FlexramFuncOptAvailableAsRam);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    while (lengthInBytes > 0U)
+    {
+        /* Make sure the write operation doesn't span two sectors */
+        uint32_t endAddressOfCurrentSector = ALIGN_UP(programaddress, sectorSize);
+        uint32_t lengthTobeProgrammedOfCurrentSector;
+        uint32_t currentOffset = 0U;
+
+        if (endAddressOfCurrentSector == programaddress)
+        {
+            endAddressOfCurrentSector += sectorSize;
+        }
+
+        if ((lengthInBytes + programaddress) > endAddressOfCurrentSector)
+        {
+            lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - programaddress;
+        }
+        else
+        {
+            lengthTobeProgrammedOfCurrentSector = lengthInBytes;
+        }
+
+        /* Program Current Sector */
+        while (lengthTobeProgrammedOfCurrentSector > 0U)
+        {
+            /* Make sure the program size doesn't exceeds Acceleration RAM size */
+            uint32_t programSizeOfCurrentPass;
+            uint32_t numberOfPhases;
+
+            if (lengthTobeProgrammedOfCurrentSector > (uint32_t)kFLASH_AccelerationRamSize)
+            {
+                programSizeOfCurrentPass = (uint32_t)kFLASH_AccelerationRamSize;
+            }
+            else
+            {
+                programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector;
+            }
+
+            /* Copy data to FlexRAM */
+            (void)memcpy((uint8_t *)config->flexramBlockBase, &srcaddress[currentOffset], programSizeOfCurrentPass);
+            /* Set programaddress address of the data to be programmed */
+            kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_SECTION, programaddress + currentOffset);
+            /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */
+            numberOfPhases = programSizeOfCurrentPass / aligmentInBytes;
+
+            kFCCOBx[1] = BYTE2WORD_2_2(numberOfPhases, 0xFFFFU);
+
+            /* Peform command sequence */
+            returnCode = ftfx_command_sequence(config);
+
+            if (returnCode != kStatus_FTFx_Success)
+            {
+                return returnCode;
+            }
+
+            lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass;
+            currentOffset += programSizeOfCurrentPass;
+        }
+
+        srcaddress = &srcaddress[currentOffset];
+        programaddress += currentOffset;
+        lengthInBytes -= currentOffset;
+    }
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    /* Restore function of FlexRAM if needed. */
+    if (needSwitchFlexRamMode)
+    {
+        returnCode = FTFx_CMD_SetFlexramFunction(config, kFTFx_FlexramFuncOptAvailableForEeprom);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the
+ * FlexRAM.
+ */
+status_t FTFx_CMD_ProgramPartition(ftfx_config_t *config,
+                                   ftfx_partition_flexram_load_opt_t option,
+                                   uint32_t eepromDataSizeCode,
+                                   uint32_t flexnvmPartitionCode)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0
+     *  or it will cause access error. */
+    /* eepromDataSizeCode bit with 0x3FU;  */
+    /* flexnvmPartitionCode bit with 0x0FU; */
+
+    /* preparing passing parameter to program the flash block */
+    kFCCOBx[0] = BYTE2WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option);
+    kFCCOBx[1] = BYTE2WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+    /* Data flash IFR will be updated by program partition command during reset sequence,
+     * so we just set reserved values for partitioned FlexNVM size here */
+    config->eepromTotalSize     = 0xFFFFU;
+    config->flashDesc.totalSize = 0xFFFFFFFFU;
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+    return (returnCode);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
+
+/*!
+ * @brief Reads the Program Once Field through parameters.
+ */
+status_t FTFx_CMD_ReadOnce(ftfx_config_t *config, uint32_t index, uint8_t *dst, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (dst == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* pass parameters to FTFx */
+    kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = ftfx_command_sequence(config);
+
+    if (returnCode == kStatus_FTFx_Success)
+    {
+        ftfx_write_word_to_byte_address(dst, kFCCOBx[1]);
+        /* Note: Have to separate the first index from the rest if it equals 0
+         *       to avoid a pointless comparison of unsigned int to 0 compiler warning */
+        if (config->ifrDesc.feature.has8ByteIdxSupport != 0U)
+        {
+            if (config->ifrDesc.feature.has4ByteIdxSupport != 0U)
+            {
+                if (((index == config->ifrDesc.idxInfo.mix8byteIdxStart) ||
+                     ((index >= ((uint32_t)config->ifrDesc.idxInfo.mix8byteIdxStart + 1U)) &&
+                      (index <= config->ifrDesc.idxInfo.mix8byteIdxEnd))) &&
+                    (lengthInBytes == 8U))
+                {
+                    ftfx_write_word_to_byte_address(&dst[4], kFCCOBx[2]);
+                }
+            }
+            else
+            {
+                ftfx_write_word_to_byte_address(&dst[4], kFCCOBx[2]);
+            }
+        }
+    }
+
+    return returnCode;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ *
+ * this function can read  date from  program flash IFR, data flash IFR space,
+ * and the Version ID field.
+ */
+status_t FTFx_CMD_ReadResource(
+    ftfx_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option)
+{
+    status_t returnCode;
+    uint32_t readstart;
+    uint8_t *destaddress;
+    uint32_t readlengthBytes;
+    readstart       = start;
+    destaddress     = dst;
+    readlengthBytes = lengthInBytes;
+    if ((config == NULL) || (dst == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    uint8_t aligmentInBytes = config->opsConfig.addrAligment.resourceCmd;
+
+    /* Check the supplied address range. */
+    returnCode = ftfx_check_resource_range(config, readstart, readlengthBytes, aligmentInBytes, option);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    while (readlengthBytes > 0U)
+    {
+        /* preparing passing parameter */
+        kFCCOBx[0] = BYTE2WORD_1_3(FTFx_READ_RESOURCE, readstart);
+        if (aligmentInBytes == 4U)
+        {
+            kFCCOBx[2] = BYTE2WORD_1_3(option, 0xFFFFFFU);
+        }
+        else if (aligmentInBytes == 8U)
+        {
+            kFCCOBx[1] = BYTE2WORD_1_3(option, 0xFFFFFFU);
+        }
+        else
+        {
+            return kStatus_FTFx_InvalidArgument;
+        }
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+
+        if (kStatus_FTFx_Success != returnCode)
+        {
+            break;
+        }
+
+        /* fetch data */
+        ftfx_write_word_to_byte_address(destaddress, kFCCOBx[1]);
+        destaddress = &destaddress[4];
+        if (aligmentInBytes == 8U)
+        {
+            ftfx_write_word_to_byte_address(destaddress, kFCCOBx[2]);
+            destaddress = &destaddress[4];
+        }
+        /* update readstart address for next iteration */
+        readstart += aligmentInBytes;
+        /* update readlengthBytes for next iteration */
+        readlengthBytes -= aligmentInBytes;
+    }
+
+    return (returnCode);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ * to the specified read margin level.
+ */
+status_t FTFx_CMD_VerifyErase(ftfx_config_t *config, uint32_t start, uint32_t lengthInBytes, ftfx_margin_value_t margin)
+{
+    /* Check arguments. */
+    uint32_t blockSize;
+    uint32_t nextBlockStartAddress;
+    uint32_t remainingBytes;
+    uint8_t aligmentInBytes = config->opsConfig.addrAligment.sectionCmd;
+    status_t returnCode;
+    uint32_t erasestart;
+
+    /* Validates the range and alignment of the given address range.*/
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes);
+    if (kStatus_FTFx_Success != returnCode)
+    {
+        return returnCode;
+    }
+
+    erasestart = config->opsConfig.convertedAddress;
+    blockSize  = config->flashDesc.totalSize / config->flashDesc.blockCount;
+
+    /* Calculate the next block start address */
+    nextBlockStartAddress = ALIGN_UP(erasestart, blockSize);
+
+    if (nextBlockStartAddress == erasestart)
+    {
+        nextBlockStartAddress += blockSize;
+    }
+
+    remainingBytes = lengthInBytes;
+
+    while (0U != remainingBytes)
+    {
+        uint32_t numberOfPhrases;
+
+        uint32_t verifyLength = nextBlockStartAddress - erasestart;
+        /* Calculate the size to be verified, this flash does not support erase and program across block. */
+        if (verifyLength > remainingBytes)
+        {
+            verifyLength = remainingBytes;
+        }
+
+        /* Calculate the number of phrases to be verified */
+        numberOfPhrases = verifyLength / aligmentInBytes;
+
+        /* Fill in verify section command parameters. */
+        kFCCOBx[0] = BYTE2WORD_1_3(FTFx_VERIFY_SECTION, erasestart);
+        kFCCOBx[1] = BYTE2WORD_2_1_1(numberOfPhrases, margin, 0xFFU);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+        if (kStatus_FTFx_Success != returnCode)
+        {
+            return returnCode;
+        }
+
+        remainingBytes -= verifyLength;
+        erasestart += verifyLength;
+        nextBlockStartAddress += blockSize;
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ */
+status_t FTFx_CMD_VerifyEraseAll(ftfx_config_t *config, ftfx_margin_value_t margin)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* preparing passing parameter to verify all block command */
+    kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return ftfx_command_sequence(config);
+}
+
+/*!
+ * @brief Verifies whether the program flash execute-only segments have been erased to
+ *  the specified read margin level.
+ */
+status_t FTFx_CMD_VerifyEraseAllExecuteOnlySegments(ftfx_config_t *config, ftfx_margin_value_t margin)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* preparing passing parameter to verify erase all execute-only segments command */
+    kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return ftfx_command_sequence(config);
+}
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ */
+status_t FTFx_CMD_VerifyProgram(ftfx_config_t *config,
+                                uint32_t start,
+                                uint32_t lengthInBytes,
+                                const uint8_t *expectedData,
+                                ftfx_margin_value_t margin,
+                                uint32_t *failedAddress,
+                                uint32_t *failedData)
+{
+    status_t returnCode;
+    uint8_t aligmentInBytes = config->opsConfig.addrAligment.checkCmd;
+    uint32_t programstart;
+    uint32_t programlength;
+    programlength = lengthInBytes;
+    if (expectedData == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Validates the range and alignment of the given address range */
+    returnCode = ftfx_check_mem_range(config, start, lengthInBytes, aligmentInBytes);
+    if (kStatus_FTFx_Success != returnCode)
+    {
+        return returnCode;
+    }
+
+    programstart = config->opsConfig.convertedAddress;
+
+    while (0U != programlength)
+    {
+        /* preparing passing parameter to program check the flash block */
+        kFCCOBx[0] = BYTE2WORD_1_3(FTFx_PROGRAM_CHECK, programstart);
+        kFCCOBx[1] = BYTE2WORD_1_3(margin, 0xFFFFFFU);
+        kFCCOBx[2] = ftfx_read_word_from_byte_address((const uint8_t *)expectedData);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+
+        /* checking for the success of command execution */
+        if (kStatus_FTFx_Success != returnCode)
+        {
+            if (failedAddress != NULL)
+            {
+                *failedAddress = programstart;
+            }
+            if (failedData != NULL)
+            {
+                *failedData = 0U;
+            }
+            break;
+        }
+
+        programlength -= aligmentInBytes;
+        expectedData = &expectedData[aligmentInBytes];
+        programstart += aligmentInBytes;
+    }
+
+    return (returnCode);
+}
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ */
+status_t FTFx_CMD_SecurityBypass(ftfx_config_t *config, const uint8_t *backdoorKey)
+{
+    uint8_t registerValue; /* registerValue */
+    status_t returnCode;   /* return code variable */
+
+    if ((config == NULL) || (backdoorKey == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* set the default return code as kStatus_Success */
+    returnCode = kStatus_FTFx_Success;
+
+    /* Get flash security register value */
+    registerValue = FTFx->FSEC;
+
+    /* Check to see if flash is in secure state (any state other than 0x2)
+     * If not, then skip this since flash is not secure */
+    if (0x02U != (registerValue & 0x03U))
+    {
+        /* preparing passing parameter to erase a flash block */
+        kFCCOBx[0] = BYTE2WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU);
+        kFCCOBx[1] = BYTE2WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]);
+        kFCCOBx[2] = BYTE2WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = ftfx_command_sequence(config);
+    }
+
+    return (returnCode);
+}
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ */
+status_t FTFx_REG_GetSecurityState(ftfx_config_t *config, ftfx_security_state_t *state)
+{
+    /* store data read from flash register */
+    uint8_t registerValue;
+    if ((config == NULL) || (state == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Get flash security register value */
+    registerValue = FTFx->FSEC;
+
+    /* check the status of the flash security bits in the security register */
+    if ((uint8_t)kFTFx_FsecRegCode_SEC_Unsecured == (registerValue & FTFx_FSEC_SEC_MASK))
+    {
+        /* Flash in unsecured state */
+        *state = kFTFx_SecurityStateNotSecure;
+    }
+    else
+    {
+        /* Flash in secured state
+         * check for backdoor key security enable bit */
+        if ((uint8_t)kFTFx_FsecRegCode_KEYEN_Enabled == (registerValue & FTFx_FSEC_KEYEN_MASK))
+        {
+            /* Backdoor key security enabled */
+            *state = kFTFx_SecurityStateBackdoorEnabled;
+        }
+        else
+        {
+            /* Backdoor key security disabled */
+            *state = kFTFx_SecurityStateBackdoorDisabled;
+        }
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ */
+status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_opt_t option)
+{
+    status_t status;
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    status = ftfx_check_flexram_function_option(option);
+    if (kStatus_FTFx_Success != status)
+    {
+        return status;
+    }
+
+    /* preparing passing parameter to verify all block command */
+    kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return ftfx_command_sequence(config);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Configures the Swap function or checks the swap state of the Flash module.
+ */
+status_t FTFx_CMD_SwapControl(ftfx_config_t *config,
+                              uint32_t address,
+                              ftfx_swap_control_opt_t option,
+                              ftfx_swap_state_config_t *returnInfo)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (returnInfo == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    if ((address & ((uint32_t)FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1u)) != 0U)
+    {
+        return kStatus_FTFx_AlignmentError;
+    }
+
+    /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */
+    if ((address >= (config->flashDesc.totalSize / 2u)) ||
+        ((address >= (uint32_t)kFTFx_PflashConfigAreaStart) && (address <= (uint32_t)kFTFx_PflashConfigAreaEnd)))
+    {
+        return kStatus_FTFx_SwapIndicatorAddressError;
+    }
+
+    /* Checking the option. */
+    returnCode = ftfx_check_swap_control_option(option);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    kFCCOBx[0] = BYTE2WORD_1_3(FTFx_SWAP_CONTROL, address);
+    kFCCOBx[1] = BYTE2WORD_1_3(option, 0xFFFFFFU);
+
+    returnCode = ftfx_command_sequence(config);
+
+    returnInfo->flashSwapState         = (ftfx_swap_state_t)FTFx_FCCOB5_REG;
+    returnInfo->currentSwapBlockStatus = (ftfx_swap_block_status_t)FTFx_FCCOB6_REG;
+    returnInfo->nextSwapBlockStatus    = (ftfx_swap_block_status_t)FTFx_FCCOB7_REG;
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+static void ftfx_init_ifr(ftfx_config_t *config)
+{
+#if FSL_FEATURE_FLASH_IS_FTFA
+    /* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */
+    config->ifrDesc.feature.has4ByteIdxSupport = 1U;
+    config->ifrDesc.feature.has8ByteIdxSupport = 1U;
+    config->ifrDesc.idxInfo.mix8byteIdxStart   = 0x10U;
+    config->ifrDesc.idxInfo.mix8byteIdxEnd     = 0x13U;
+#elif FSL_FEATURE_FLASH_IS_FTFE
+    /* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */
+    config->ifrDesc.feature.has4ByteIdxSupport = 0U;
+    config->ifrDesc.feature.has8ByteIdxSupport = 1U;
+#elif FSL_FEATURE_FLASH_IS_FTFL
+    /* FTFL parts(eg. K20) only support 4-bytes unit size */
+    config->ifrDesc.feature.has4ByteIdxSupport = 1U;
+    config->ifrDesc.feature.has8ByteIdxSupport = 0U;
+#endif
+
+    config->ifrDesc.resRange.pflashIfrStart = 0x0000U;
+    config->ifrDesc.resRange.versionIdSize  = 0x08U;
+#if FSL_FEATURE_FLASH_IS_FTFE
+    config->ifrDesc.resRange.versionIdStart = 0x08U;
+    config->ifrDesc.resRange.ifrMemSize     = 0x0400U;
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+    config->ifrDesc.resRange.versionIdStart    = 0x00U;
+    config->ifrDesc.resRange.ifrMemSize        = 0x0100U;
+#endif
+
+#if FSL_FEATURE_FLASH_HAS_FLEX_NVM
+    config->ifrDesc.resRange.dflashIfrStart = 0x800000U;
+#endif
+
+#if FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+#if FSL_FEATURE_FLASH_IS_FTFE
+    config->ifrDesc.resRange.pflashSwapIfrStart = 0x40000U;
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA == 1 */
+    config->ifrDesc.resRange.pflashSwapIfrStart = config->flashDesc.totalSize / 4;
+#endif
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+}
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Copy PIC of flash_run_command() to RAM
+ */
+static void ftfx_copy_run_command_to_ram(uint32_t *ftfxRunCommand)
+{
+    assert(sizeof(s_ftfxRunCommandFunctionCode) <= ((uint32_t)kFTFx_RamFuncMaxSizeInWords * 4U));
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    (void)memcpy(ftfxRunCommand, s_ftfxRunCommandFunctionCode, sizeof(s_ftfxRunCommandFunctionCode));
+}
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+/*!
+ * @brief FTFx Command Sequence
+ *
+ * This function is used to perform the command write sequence to the flash.
+ *
+ * @param driver Pointer to storage for the driver runtime state.
+ * @return An error code or kStatus_FTFx_Success
+ */
+static status_t ftfx_command_sequence(ftfx_config_t *config)
+{
+    uint8_t registerValue;
+
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    config->runCmdFuncAddr.commadAddr += 1UL;
+    callFtfxRunCommand_t callFtfxRunCommand = config->runCmdFuncAddr.callFlashCommand;
+
+    /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
+     * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
+     * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
+    callFtfxRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT));
+    config->runCmdFuncAddr.commadAddr -= 1UL;
+#else
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    /* clear CCIF bit */
+    FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK;
+
+    /* Check CCIF bit of the flash status register, wait till it is set.
+     * IP team indicates that this loop will always complete. */
+    while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK))
+    {
+    }
+#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
+
+    /* Check error bits */
+    /* Get flash status register value */
+    registerValue = FTFx->FSTAT;
+
+    /* checking access error */
+    if (0U != (registerValue & FTFx_FSTAT_ACCERR_MASK))
+    {
+        return kStatus_FTFx_AccessError;
+    }
+    /* checking protection error */
+    else if (0U != (registerValue & FTFx_FSTAT_FPVIOL_MASK))
+    {
+        return kStatus_FTFx_ProtectionViolation;
+    }
+    /* checking MGSTAT0 non-correctable error */
+    else if (0U != (registerValue & FTFx_FSTAT_MGSTAT0_MASK))
+    {
+        return kStatus_FTFx_CommandFailure;
+    }
+    else
+    {
+        return kStatus_FTFx_Success;
+    }
+}
+
+static void ftfx_command_sequence_non_blocking(ftfx_config_t *config)
+{
+#if FTFx_DRIVER_IS_FLASH_RESIDENT
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    config->runCmdFuncAddr.commadAddr += 1UL;
+    callFtfxRunCommand_t callFtfxRunCommand = config->runCmdFuncAddr.callFlashCommand;
+
+    /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
+     * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
+     * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
+    callFtfxRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT));
+    config->runCmdFuncAddr.commadAddr -= 1UL;
+#else
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    /* clear CCIF bit */
+    FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK;
+#endif
+}
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t ftfx_check_mem_range(ftfx_config_t *config,
+                                     uint32_t startAddress,
+                                     uint32_t lengthInBytes,
+                                     uint8_t alignmentBaseline)
+{
+    status_t status = kStatus_FTFx_AddressError;
+
+    /* Verify the start and length are alignmentBaseline aligned. */
+    if ((0U != (startAddress & (uint8_t)(alignmentBaseline - 1U))) ||
+        (0U != (lengthInBytes & (uint8_t)(alignmentBaseline - 1U))))
+    {
+        return kStatus_FTFx_AlignmentError;
+    }
+
+    /* check for valid range of the target addresses */
+    if ((startAddress >= config->flashDesc.blockBase) &&
+        ((startAddress + lengthInBytes) <= (config->flashDesc.blockBase + config->flashDesc.totalSize)))
+    {
+        status = kStatus_FTFx_Success;
+    }
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS) && FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS
+    else if ((startAddress >= config->flashDesc.aliasBlockBase) &&
+             ((startAddress + lengthInBytes) <= (config->flashDesc.aliasBlockBase + config->flashDesc.totalSize)))
+    {
+        status = kStatus_FTFx_Success;
+    }
+    else
+    {
+        status = kStatus_FTFx_AddressError;
+    }
+#endif
+
+    return status;
+}
+
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t ftfx_check_user_key(uint32_t key)
+{
+    /* Validate the user key */
+    if (key != (uint32_t)kFTFx_ApiEraseKey)
+    {
+        return kStatus_FTFx_EraseKeyError;
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*! @brief Reads word from byte address.*/
+static uint32_t ftfx_read_word_from_byte_address(const uint8_t *src)
+{
+    uint32_t word          = 0U;
+    const uint8_t *readsrc = src;
+    /* If the source address is aligned with 4 bytes */
+    if (0U == ((uint32_t)readsrc % 4U))
+    {
+        word = *(const uint32_t *)(uint32_t)readsrc;
+    }
+    /* Read 4 bytes from a non-4-byte aligned address, 1 byte one time */
+    else
+    {
+        for (uint32_t i = 0U; i < 4U; i++)
+        {
+            word |= (uint32_t)(*readsrc) << (i * 8U);
+            readsrc++;
+        }
+    }
+
+    return word;
+}
+
+/*! @brief Writes word to byte address.*/
+static void ftfx_write_word_to_byte_address(uint8_t *dst, uint32_t word)
+{
+    uint8_t *writedst = dst;
+    /* If the source address is aligned with 4 bytes */
+    if (0U == ((uint32_t)writedst % 4U))
+    {
+        *(uint32_t *)(uint32_t)writedst = word;
+    }
+    else
+    {
+        /* Write 4 bytes into a non-4-byte aligned address memory, 1 byte one time */
+        for (uint32_t i = 0U; i < 4U; i++)
+        {
+            *writedst = (uint8_t)((word >> (i * 8U)) & 0xFFU);
+            writedst++;
+        }
+    }
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*! @brief Validates the range of the given resource address.*/
+static status_t ftfx_check_resource_range(ftfx_config_t *config,
+                                          uint32_t start,
+                                          uint32_t lengthInBytes,
+                                          uint32_t alignmentBaseline,
+                                          ftfx_read_resource_opt_t option)
+{
+    status_t status;
+    uint32_t maxReadbleAddress;
+
+    if ((0U != (start & (alignmentBaseline - 1u))) || (0U != (lengthInBytes & (alignmentBaseline - 1u))))
+    {
+        return kStatus_FTFx_AlignmentError;
+    }
+
+    status = kStatus_FTFx_Success;
+
+    maxReadbleAddress = start + lengthInBytes - 1u;
+    /* read resource code from the version ID field */
+    if (option == kFTFx_ResourceOptionVersionId)
+    {
+        if ((start != config->ifrDesc.resRange.versionIdStart) ||
+            (lengthInBytes != config->ifrDesc.resRange.versionIdSize))
+        {
+            status = kStatus_FTFx_InvalidArgument;
+        }
+    }
+    else if (option == kFTFx_ResourceOptionFlashIfr)
+    {
+        /* read resource code from the  program flash IFR space */
+        if ((start >= config->ifrDesc.resRange.pflashIfrStart) &&
+            (maxReadbleAddress < (config->ifrDesc.resRange.pflashIfrStart + config->ifrDesc.resRange.ifrMemSize)))
+        {
+        }
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+        /* read resource code from the  date flash IFR space */
+        else if ((start >= config->ifrDesc.resRange.dflashIfrStart) &&
+                 (maxReadbleAddress < (config->ifrDesc.resRange.dflashIfrStart + config->ifrDesc.resRange.ifrMemSize)))
+        {
+        }
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+        /* read resource code from the  Program Flash Swap IFR space */
+        else if ((start >= config->ifrDesc.resRange.pflashSwapIfrStart) &&
+                 (maxReadbleAddress <
+                  (config->ifrDesc.resRange.pflashSwapIfrStart + config->ifrDesc.resRange.ifrMemSize)))
+        {
+        }
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+        else
+        {
+            status = kStatus_FTFx_InvalidArgument;
+        }
+    }
+    else
+    {
+        status = kStatus_FTFx_InvalidArgument;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*! @brief Validates the given flexram function option.*/
+static inline status_t ftfx_check_flexram_function_option(ftfx_flexram_func_opt_t option)
+{
+    if ((option != kFTFx_FlexramFuncOptAvailableAsRam) && (option != kFTFx_FlexramFuncOptAvailableForEeprom))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    return kStatus_FTFx_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*! @brief Validates the given swap control option.*/
+static status_t ftfx_check_swap_control_option(ftfx_swap_control_opt_t option)
+{
+    if ((option == kFTFx_SwapControlOptionIntializeSystem) || (option == kFTFx_SwapControlOptionSetInUpdateState) ||
+        (option == kFTFx_SwapControlOptionSetInCompleteState) || (option == kFTFx_SwapControlOptionReportStatus) ||
+        (option == kFTFx_SwapControlOptionDisableSystem))
+    {
+        return kStatus_FTFx_Success;
+    }
+
+    return kStatus_FTFx_InvalidArgument;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.h
new file mode 100644
index 0000000000..48567f536d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_controller.h
@@ -0,0 +1,849 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_CONTROLLER_H
+#define FSL_FTFX_CONTROLLER_H
+
+#include "fsl_ftfx_features.h"
+#include "fsl_ftfx_utilities.h"
+
+/*!
+ * @addtogroup ftfx_controller
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name FTFx status
+ * @{
+ */
+
+/*! @cond output_undoc_content */
+/* FTFx driver status group. */
+#if defined(kStatusGroup_FlashDriver)
+#define kStatusGroupGeneric    kStatusGroup_Generic
+#define kStatusGroupFtfxDriver kStatusGroup_FlashDriver
+#elif defined(kStatusGroup_FLASH)
+#define kStatusGroupGeneric    kStatusGroup_Generic
+#define kStatusGroupFtfxDriver kStatusGroup_FLASH
+#else
+#define kStatusGroupGeneric    0
+#define kStatusGroupFtfxDriver 1
+#endif
+/*! @endcond */
+
+/*!
+ * @brief FTFx driver status codes.
+ */
+enum
+{
+    kStatus_FTFx_Success         = MAKE_STATUS(kStatusGroupGeneric, 0),    /*!< API is executed successfully*/
+    kStatus_FTFx_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4),    /*!< Invalid argument*/
+    kStatus_FTFx_SizeError       = MAKE_STATUS(kStatusGroupFtfxDriver, 0), /*!< Error size*/
+    kStatus_FTFx_AlignmentError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
+    kStatus_FTFx_AddressError = MAKE_STATUS(kStatusGroupFtfxDriver, 2), /*!< Address is out of range */
+    kStatus_FTFx_AccessError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
+    kStatus_FTFx_ProtectionViolation = MAKE_STATUS(
+        kStatusGroupFtfxDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
+    kStatus_FTFx_CommandFailure =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 5), /*!< Run-time error during command execution. */
+    kStatus_FTFx_UnknownProperty   = MAKE_STATUS(kStatusGroupFtfxDriver, 6), /*!< Unknown property.*/
+    kStatus_FTFx_EraseKeyError     = MAKE_STATUS(kStatusGroupFtfxDriver, 7), /*!< API erase key is invalid.*/
+    kStatus_FTFx_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFtfxDriver, 8), /*!< The current region is execute-only.*/
+    kStatus_FTFx_ExecuteInRamFunctionNotReady =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 9), /*!< Execute-in-RAM function is not available.*/
+    kStatus_FTFx_PartitionStatusUpdateFailure =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 10), /*!< Failed to update partition status.*/
+    kStatus_FTFx_SetFlexramAsEepromError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/
+    kStatus_FTFx_RecoverFlexramAsRamError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/
+    kStatus_FTFx_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFtfxDriver, 13), /*!< Failed to set FlexRAM as RAM.*/
+    kStatus_FTFx_RecoverFlexramAsEepromError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/
+    kStatus_FTFx_CommandNotSupported = MAKE_STATUS(kStatusGroupFtfxDriver, 15), /*!< Flash API is not supported.*/
+    kStatus_FTFx_SwapSystemNotInUninitialized =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 16), /*!< Swap system is not in an uninitialzed state.*/
+    kStatus_FTFx_SwapIndicatorAddressError =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 17), /*!< The swap indicator address is invalid.*/
+    kStatus_FTFx_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFtfxDriver, 18), /*!< The flash property is read-only.*/
+    kStatus_FTFx_InvalidPropertyValue =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 19), /*!< The flash property value is out of range.*/
+    kStatus_FTFx_InvalidSpeculationOption =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/
+    kStatus_FTFx_CommandOperationInProgress =
+        MAKE_STATUS(kStatusGroupFtfxDriver, 21), /*!< The option of flash command is processing.*/
+};
+/*! @} */
+
+/*!
+ * @name FTFx API key
+ * @{
+ */
+/*!
+ * @brief Enumeration for FTFx driver API keys.
+ *
+ * @note The resulting value is built with a byte order such that the string
+ * being readable in expected order when viewed in a hex editor, if the value
+ * is treated as a 32-bit little endian value.
+ */
+enum _ftfx_driver_api_keys
+{
+    kFTFx_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all FTFx erase APIs.*/
+};
+/*! @} */
+
+/*!
+ * @brief Enumeration for the FlexRAM load during reset option.
+ */
+typedef enum _ftfx_partition_flexram_load_option
+{
+    kFTFx_PartitionFlexramLoadOptLoadedWithValidEepromData =
+        0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/
+    kFTFx_PartitionFlexramLoadOptNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
+} ftfx_partition_flexram_load_opt_t;
+
+/*!
+ * @brief Enumeration for the two possible options of flash read resource command.
+ */
+typedef enum _ftfx_read_resource_opt
+{
+    kFTFx_ResourceOptionFlashIfr =
+        0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */
+    kFTFx_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/
+} ftfx_read_resource_opt_t;
+
+/*!
+ * @brief Enumeration for supported FTFx margin levels.
+ */
+typedef enum _ftfx_margin_value
+{
+    kFTFx_MarginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
+    kFTFx_MarginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
+    kFTFx_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
+    kFTFx_MarginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
+} ftfx_margin_value_t;
+
+/*!
+ * @brief Enumeration for the three possible FTFx security states.
+ */
+typedef enum _ftfx_security_state
+{
+    kFTFx_SecurityStateNotSecure        = (int)0xc33cc33cu, /*!< Flash is not secure.*/
+    kFTFx_SecurityStateBackdoorEnabled  = (int)0x5aa55aa5u, /*!< Flash backdoor is enabled.*/
+    kFTFx_SecurityStateBackdoorDisabled = (int)0x5ac33ca5u  /*!< Flash backdoor is disabled.*/
+} ftfx_security_state_t;
+
+/*!
+ * @brief Enumeration for the two possilbe options of set FlexRAM function command.
+ */
+typedef enum _ftfx_flexram_function_option
+{
+    kFTFx_FlexramFuncOptAvailableAsRam     = 0xFFU, /*!< An option used to make FlexRAM available as RAM */
+    kFTFx_FlexramFuncOptAvailableForEeprom = 0x00U  /*!< An option used to make FlexRAM available for EEPROM */
+} ftfx_flexram_func_opt_t;
+
+/*!
+ * @brief Enumeration for acceleration ram property.
+ */
+enum _flash_acceleration_ram_property
+{
+    kFLASH_AccelerationRamSize = 0x400U
+};
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Enumeration for the possible options of Swap control commands
+ */
+typedef enum _ftfx_swap_control_option
+{
+    kFTFx_SwapControlOptionIntializeSystem    = 0x01U, /*!< An option used to initialize the Swap system */
+    kFTFx_SwapControlOptionSetInUpdateState   = 0x02U, /*!< An option used to set the Swap in an update state */
+    kFTFx_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */
+    kFTFx_SwapControlOptionReportStatus       = 0x08U, /*!< An option used to report the Swap status */
+    kFTFx_SwapControlOptionDisableSystem      = 0x10U  /*!< An option used to disable the Swap status */
+} ftfx_swap_control_opt_t;
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*!
+ * @brief Enumeration for the possible flash Swap status.
+ */
+typedef enum _ftfx_swap_state
+{
+    kFTFx_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/
+    kFTFx_SwapStateReady         = 0x01U, /*!< Flash Swap system is in a ready state.*/
+    kFTFx_SwapStateUpdate        = 0x02U, /*!< Flash Swap system is in an update state.*/
+    kFTFx_SwapStateUpdateErased  = 0x03U, /*!< Flash Swap system is in an updateErased state.*/
+    kFTFx_SwapStateComplete      = 0x04U, /*!< Flash Swap system is in a complete state.*/
+    kFTFx_SwapStateDisabled      = 0x05U  /*!< Flash Swap system is in a disabled state.*/
+} ftfx_swap_state_t;
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Enumeration for the possible flash Swap block status
+ */
+typedef enum _ftfx_swap_block_status
+{
+    kFTFx_SwapBlockStatusLowerHalfProgramBlocksAtZero =
+        0x00U, /*!< Swap block status is that lower half program block at zero.*/
+    kFTFx_SwapBlockStatusUpperHalfProgramBlocksAtZero =
+        0x01U, /*!< Swap block status is that upper half program block at zero.*/
+} ftfx_swap_block_status_t;
+
+/*!
+ * @brief Flash Swap information
+ */
+typedef struct _ftfx_swap_state_config
+{
+    ftfx_swap_state_t flashSwapState;                /*!<The current Swap system status.*/
+    ftfx_swap_block_status_t currentSwapBlockStatus; /*!< The current Swap block status.*/
+    ftfx_swap_block_status_t nextSwapBlockStatus;    /*!< The next Swap block status.*/
+} ftfx_swap_state_config_t;
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*!
+ * @brief Enumeration for FTFx memory type.
+ */
+enum _ftfx_memory_type
+{
+    kFTFx_MemTypePflash  = 0x00U,
+    kFTFx_MemTypeFlexnvm = 0x01U
+};
+
+/*!
+ * @brief ftfx special memory access information.
+ */
+typedef struct _ftfx_special_mem
+{
+    uint32_t base;  /*!< Base address of flash special memory.*/
+    uint32_t size;  /*!< size of flash special memory.*/
+    uint32_t count; /*!< flash special memory count.*/
+} ftfx_spec_mem_t;
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/*!
+ * @brief Flash memory descriptor.
+ */
+typedef struct _ftfx_mem_descriptor
+{
+    struct
+    {
+        uint8_t type;  /*!< Type of flash block.*/
+        uint8_t index; /*!< Index of flash block.*/
+        uint8_t reserved[2];
+    };
+    struct
+    {
+        uint32_t isIndBlock : 1;
+        uint32_t hasIndPfsizeReg : 1;
+        uint32_t hasProtControl : 1;
+        uint32_t hasIndProtReg : 1;
+        uint32_t hasXaccControl : 1;
+        uint32_t hasIndXaccReg : 1;
+        uint32_t : 18;
+        uint32_t ProtRegBits : 8;
+    } feature;
+    uint32_t blockBase; /*!< A base address of the flash block */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS) && FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS
+    uint32_t aliasBlockBase; /*!< A base address of the alias flash block */
+#endif
+    uint32_t totalSize;  /*!< The size of the flash block. */
+    uint32_t sectorSize; /*!< The size in bytes of a sector of flash. */
+    uint32_t blockCount; /*!< A number of flash blocks. */
+    ftfx_spec_mem_t accessSegmentMem;
+    ftfx_spec_mem_t protectRegionMem;
+} ftfx_mem_desc_t;
+
+/*!
+ * @brief Active FTFx information for the current operation.
+ */
+typedef struct _ftfx_ops_config
+{
+    uint32_t convertedAddress; /*!< A converted address for the current flash type.*/
+    struct
+    {
+        uint8_t sectorCmd;
+        uint8_t sectionCmd;
+        uint8_t resourceCmd;
+        uint8_t checkCmd;
+        uint8_t swapCtrlCmd;
+        uint8_t blockWriteUnitSize;
+        uint8_t reserved[2];
+    } addrAligment;
+} ftfx_ops_config_t;
+
+/*!
+ * @brief Flash IFR memory descriptor.
+ */
+typedef struct _ftfx_ifr_descriptor
+{
+    struct
+    {
+        uint32_t has4ByteIdxSupport : 1;
+        uint32_t has8ByteIdxSupport : 1;
+        uint32_t : 30;
+    } feature;
+    struct
+    {
+        uint8_t versionIdStart; /*!< Version ID start address */
+        uint8_t versionIdSize;
+        uint16_t ifrMemSize;
+        uint32_t pflashIfrStart;     /*!< Program Flash 0 IFR start address */
+        uint32_t dflashIfrStart;     /*!< Data Flash 0 IFR start address */
+        uint32_t pflashSwapIfrStart; /*!< Program Flash Swap IFR start address*/
+    } resRange;
+    struct
+    {
+        uint16_t mix8byteIdxStart;
+        uint16_t mix8byteIdxEnd;
+    } idxInfo;
+} ftfx_ifr_desc_t;
+
+typedef union
+{
+    uint32_t commadAddr;
+    void (*callFlashCommand)(FTFx_REG8_ACCESS_TYPE FTMRx_fstat);
+} function_ptr_t;
+
+/*! @brief Flash driver state information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _ftfx_config
+{
+    ftfx_mem_desc_t flashDesc;
+    ftfx_ops_config_t opsConfig;
+    uint32_t flexramBlockBase; /*!< The base address of the FlexRAM/acceleration RAM */
+    uint32_t flexramTotalSize; /*!< The size of the FlexRAM/acceleration RAM */
+    uint16_t eepromTotalSize;  /*!< The size of EEPROM area which was partitioned from FlexRAM */
+    uint16_t reserved;
+    function_ptr_t runCmdFuncAddr; /*!< An buffer point to the flash execute-in-RAM function. */
+    ftfx_ifr_desc_t ifrDesc;
+} ftfx_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ */
+void FTFx_API_Init(ftfx_config_t *config);
+
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+/*!
+ * @brief Updates FlexNVM memory partition status according to data flash 0 IFR.
+ *
+ * This function updates FlexNVM memory partition status.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config);
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+
+/*! @} */
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_Erase(ftfx_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+
+/*!
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
+ *
+ * This function erases one flash sector size based on the start address.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ */
+status_t FTFx_CMD_EraseSectorNonBlocking(ftfx_config_t *config, uint32_t start, uint32_t key);
+
+/*!
+ * @brief Erases entire flash
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FTFx_CMD_EraseAll(ftfx_config_t *config, uint32_t key);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flash, including protected sectors.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FTFx_CMD_EraseAllUnsecure(ftfx_config_t *config, uint32_t key);
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+/*!
+ * @brief Erases all program flash execute-only segments defined by the FXACC registers.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_EraseAllExecuteOnlySegments(ftfx_config_t *config, uint32_t key);
+
+/*! @} */
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_Program(ftfx_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Programs Program Once Field through parameters.
+ *
+ * This function programs the Program Once Field with the desired data for a given
+ * flash area as determined by the index and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating which area of the Program Once Field to be programmed.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the Program Once Field.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_ProgramOnce(ftfx_config_t *config, uint32_t index, const uint8_t *src, uint32_t lengthInBytes);
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_SetFlexramAsRamError Failed to set flexram as RAM.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM.
+ */
+status_t FTFx_CMD_ProgramSection(ftfx_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes);
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the
+ * FlexRAM.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set FlexRAM load behavior during reset.
+ * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems.
+ * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
+ *        memory supporting EEPROM functions.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FTFx_CMD_ProgramPartition(ftfx_config_t *config,
+                                   ftfx_partition_flexram_load_opt_t option,
+                                   uint32_t eepromDataSizeCode,
+                                   uint32_t flexnvmPartitionCode);
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
+
+/*! @} */
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+/*!
+ * @brief Reads the Program Once Field through parameters.
+ *
+ * This function reads the read once feild with given index and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating the area of program once field to be read.
+ * @param dst A pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_ReadOnce(ftfx_config_t *config, uint32_t index, uint8_t *dst, uint32_t lengthInBytes);
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ *
+ * This function reads the flash memory with the desired location for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param dst A pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be read. Must be word-aligned.
+ * @param option The resource option which indicates which area should be read back.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_ReadResource(
+    ftfx_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+/*! @} */
+
+/*!
+ * @name Verification
+ * @{
+ */
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ * to the specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_VerifyErase(ftfx_config_t *config,
+                              uint32_t start,
+                              uint32_t lengthInBytes,
+                              ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ *
+ * This function checks whether the flash is erased to the
+ * specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_VerifyEraseAll(ftfx_config_t *config, ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies whether the program flash execute-only segments have been erased to
+ *  the specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_VerifyEraseAllExecuteOnlySegments(ftfx_config_t *config, ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param expectedData A pointer to the expected data that is to be
+ *        verified against.
+ * @param margin Read margin choice.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
+ *        case, zeros are returned upon failure.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_VerifyProgram(ftfx_config_t *config,
+                                uint32_t start,
+                                uint32_t lengthInBytes,
+                                const uint8_t *expectedData,
+                                ftfx_margin_value_t margin,
+                                uint32_t *failedAddress,
+                                uint32_t *failedData);
+
+/*! @} */
+
+/*!
+ * @name Security
+ * @{
+ */
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ *
+ * This function retrieves the current flash security status, including the
+ * security enabling state and the backdoor key enabling state.
+ *
+ * @param config A pointer to storage for the driver runtime state.
+ * @param state A pointer to the value returned for the current security status code:
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ */
+status_t FTFx_REG_GetSecurityState(ftfx_config_t *config, ftfx_security_state_t *state);
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ *
+ * If the MCU is in secured state, this function unsecures the MCU by
+ * comparing the provided backdoor key with ones in the flash configuration
+ * field.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param backdoorKey A pointer to the user buffer containing the backdoor key.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_SecurityBypass(ftfx_config_t *config, const uint8_t *backdoorKey);
+
+/*! @} */
+
+/*!
+ * @name FlexRAM
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option The option used to set the work mode of FlexRAM.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*! @} */
+
+/*!
+ * @name Swap
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Configures the Swap function or checks the swap state of the Flash module.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param address Address used to configure the flash Swap function.
+ * @param option The possible option used to configure Flash Swap function or check the flash Swap status
+ * @param returnInfo A pointer to the data which is used to return the information of flash Swap.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FTFx_CMD_SwapControl(ftfx_config_t *config,
+                              uint32_t address,
+                              ftfx_swap_control_opt_t option,
+                              ftfx_swap_state_config_t *returnInfo);
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FTFX_CONTROLLER_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_features.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_features.h
new file mode 100644
index 0000000000..f42bf8d0ad
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_features.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_FEATURES_H
+#define FSL_FTFX_FEATURES_H
+
+#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM))
+#include <assert.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+#include "bootloader_common.h"
+#else
+#include "fsl_common.h"
+#endif
+
+#include "fsl_ftfx_adapter.h"
+
+/*!
+ * @addtogroup ftfx_feature
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name FTFx configuration
+ * @{
+ */
+/*! @brief Flash driver location. */
+#if !defined(FTFx_DRIVER_IS_FLASH_RESIDENT)
+#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM))
+#define FTFx_DRIVER_IS_FLASH_RESIDENT 1U /*!< Used for the flash resident application. */
+#else
+#define FTFx_DRIVER_IS_FLASH_RESIDENT 0U /*!< Used for the non-flash resident application. */
+#endif
+#endif
+
+/*! @brief Flash Driver Export option */
+#if !defined(FTFx_DRIVER_IS_EXPORTED)
+#if defined(BL_TARGET_ROM)
+#define FTFx_DRIVER_IS_EXPORTED 1U /*!< Used for the ROM bootloader. */
+#else
+#define FTFx_DRIVER_IS_EXPORTED 0U /*!< Used for the MCUXpresso SDK application. */
+#endif
+#endif
+/*! @} */
+
+/*! @brief Indicates whether the secondary flash is supported in the Flash driver */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#define FTFx_DRIVER_HAS_FLASH1_SUPPORT (1U)
+#define FTFx_FLASH_COUNT               (2U)
+#else
+#define FTFx_DRIVER_HAS_FLASH1_SUPPORT (0U)
+#define FTFx_FLASH_COUNT               (1U)
+#endif
+
+/*!
+ * @name Secondary flash configuration
+ * @{
+ */
+/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK)
+#define FTFx_FLASH1_HAS_PROT_CONTROL (1U)
+#else
+#define FTFx_FLASH1_HAS_PROT_CONTROL (0U)
+#endif
+
+/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK)
+#define FTFx_FLASH1_HAS_XACC_CONTROL (1U)
+#else
+#define FTFx_FLASH1_HAS_XACC_CONTROL (0U)
+#endif
+/*! @} */
+
+#if FTFx_FLASH1_HAS_XACC_CONTROL || FTFx_FLASH1_HAS_PROT_CONTROL
+#define FTFx_FLASH1_IS_INDEPENDENT_BLOCK (1U)
+#else
+#define FTFx_FLASH1_IS_INDEPENDENT_BLOCK (0U)
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FTFX_FEATURES_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.c
new file mode 100644
index 0000000000..f6700ee476
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.c
@@ -0,0 +1,1544 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "fsl_ftfx_flash.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash"
+#endif
+
+/*!
+ * @brief Enumeration for special memory property.
+ */
+enum _ftfx_special_mem_property
+{
+    kFTFx_AccessSegmentUnitSize = 256UL,
+    kFTFx_MinProtectBlockSize   = 1024UL,
+};
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*!
+ * @brief Enumeration for the index of read/program once record
+ */
+enum _k3_flash_read_once_index
+{
+    kFLASH_RecordIndexSwapAddr    = 0xA1U, /*!< Index of Swap indicator address.*/
+    kFLASH_RecordIndexSwapEnable  = 0xA2U, /*!< Index of Swap system enable.*/
+    kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/
+};
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*! @brief init flash features */
+static void flash_init_features(ftfx_config_t *config);
+
+/*! @brief init  protection feature */
+static void flash_protection_init(flash_config_t *config, uint8_t flashIndex);
+
+/*! @brief init access segment feature */
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+static void flash_access_init(flash_config_t *config, uint8_t flashIndex);
+#endif
+
+/*! @brief init flash operation config */
+static void flash_opsonfig_Init(flash_config_t *config, uint8_t flashIndex);
+
+/*! @brief Calculate flash memory size based on given parameter */
+static uint32_t flash_calculate_mem_size(uint32_t pflashBlockCount,
+                                         uint32_t pflashBlockSize,
+                                         uint32_t pfsizeMask,
+                                         uint32_t pfsizeShift);
+
+static uint32_t flash_calculate_prot_segment_size(uint32_t flashSize, uint32_t segmentCount);
+
+/*! @brief Validates the given address to get current flash index */
+static status_t flash_check_range_to_get_index(flash_config_t *config,
+                                               uint32_t start,
+                                               uint32_t lengthInBytes,
+                                               uint8_t *flashIndex);
+
+/*! @brief Decide whether to convert the start address from primary flash to secondary flash based on the current start
+ * address*/
+static void flash_convert_start_address(ftfx_config_t *config, uint32_t start);
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*! @brief Validates the given address to see if it is equal to swap indicator address in pflash swap IFR.*/
+static status_t flash_validate_swap_indicator_address(ftfx_config_t *config, uint32_t address);
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+static volatile uint32_t *const kFPROTL = (volatile uint32_t *)(uint32_t)&FTFx_FPROT_LOW_REG;
+#if defined(FTFx_FLASH0_HAS_HIGH_PROT_REG) && FTFx_FLASH0_HAS_HIGH_PROT_REG
+static volatile uint32_t *const kFPROTH = (volatile uint32_t *)(uint32_t)&FTFx_FPROT_HIGH_REG;
+#endif /* FTFx_FLASH0_HAS_HIGH_PROT_REG */
+#if defined(FTFx_FLASH1_HAS_INT_PROT_REG) && FTFx_FLASH1_HAS_INT_PROT_REG
+volatile uint8_t *const kFPROTSL = (volatile uint8_t *)(uint32_t)&FTFx_FPROTSL_REG;
+volatile uint8_t *const kFPROTSH = (volatile uint8_t *)(uint32_t)&FTFx_FPROTSH_REG;
+#endif /* FTFx_FLASH1_HAS_INT_PROT_REG */
+
+/*!
+ * @brief Table of pflash sizes.
+ *
+ *  The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield.
+ *
+ *  The values in this table have been right shifted 10 bits so that they will all fit within
+ *  an 16-bit integer. To get the actual flash density, you must left shift the looked up value
+ *  by 10 bits.
+ *
+ *  Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is
+ *  reserved.
+ *
+ *  Code to use the table:
+ *  @code
+ *      uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+ *      flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+ *  @endcode
+ */
+#if defined(FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION) && (FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION == 1)
+static const uint16_t kPFlashDensities[] = {
+    0u,    /* 0x0 - undefined */
+    0u,    /* 0x1 - undefined */
+    0u,    /* 0x2 - undefined */
+    0u,    /* 0x3 - undefined */
+    0u,    /* 0x4 - undefined */
+    0u,    /* 0x5 - undefined */
+    0u,    /* 0x6 - undefined */
+    0u,    /* 0x7 - undefined */
+    0u,    /* 0x8 - undefined */
+    0u,    /* 0x9 - undefined */
+    256u,  /* 0xa - 262144, 256KB */
+    512u,  /* 0xb - 524288, 512KB */
+    1024u, /* 0xc - 1048576, 1MB */
+    0u,    /* 0xd - undefined */
+    0u,    /* 0xe - undefined */
+    0u,    /* 0xf - undefined */
+};
+#else
+static const uint16_t kPFlashDensities[] = {
+    8u,    /* 0x0 - 8192, 8KB */
+    16u,   /* 0x1 - 16384, 16KB */
+    24u,   /* 0x2 - 24576, 24KB */
+    32u,   /* 0x3 - 32768, 32KB */
+    48u,   /* 0x4 - 49152, 48KB */
+    64u,   /* 0x5 - 65536, 64KB */
+    96u,   /* 0x6 - 98304, 96KB */
+    128u,  /* 0x7 - 131072, 128KB */
+    192u,  /* 0x8 - 196608, 192KB */
+    256u,  /* 0x9 - 262144, 256KB */
+    384u,  /* 0xa - 393216, 384KB */
+    512u,  /* 0xb - 524288, 512KB */
+    768u,  /* 0xc - 786432, 768KB */
+    1024u, /* 0xd - 1048576, 1MB */
+    1536u, /* 0xe - 1572864, 1.5MB */
+    /* 2048u,  0xf - 2097152, 2MB */
+};
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLASH_Init(flash_config_t *config)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    for (uint8_t flashIndex = 0U; flashIndex < FTFx_FLASH_COUNT; flashIndex++)
+    {
+        /* init flash type, kinetis has Pflash and flxnvm, pflash is often used to store executable code
+         * and flexnvm can be used as date flash to store user data, and can also be configured as eeprom backup space
+         * with flexram.
+         */
+        config->ftfxConfig[flashIndex].flashDesc.type = (uint8_t)kFTFx_MemTypePflash;
+        /* init the current flash index */
+        config->ftfxConfig[flashIndex].flashDesc.index = flashIndex;
+        /* init flash features */
+        flash_init_features(&config->ftfxConfig[flashIndex]);
+        /* init flash Operation Config */
+        flash_opsonfig_Init(config, flashIndex);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+        if (0U != (config->ftfxConfig[flashIndex].flashDesc.feature.hasXaccControl))
+        {
+            /* init access segment feature */
+            flash_access_init(config, flashIndex);
+        }
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+#if (FTFx_FLASH_COUNT > 1U)
+        if (0U != (config->ftfxConfig[flashIndex].flashDesc.feature.hasProtControl))
+#endif
+        {
+            /* init  protection feature */
+            flash_protection_init(config, flashIndex);
+        }
+
+        /* Init FTFx Kernel */
+        FTFx_API_Init(&config->ftfxConfig[flashIndex]);
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the appropriate number of flash sectors based on the
+ *         desired start address and length was erased successfully.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+
+    /* check the supplied address range to get flash index  */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* Decide whether to convert the start address from primary flash to secondary flash based on the current address */
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    return FTFx_CMD_Erase(&config->ftfxConfig[flashIndex], start, lengthInBytes, key);
+}
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ *
+ * This function erases one flash sector size based on the start address, and it is
+ * executed asynchronously.
+ */
+status_t FLASH_EraseSectorNonBlocking(flash_config_t *config, uint32_t start, uint32_t key)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+    uint32_t lengthInBytes = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
+
+    /* check the supplied address range to get flash index  */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* Decide whether to convert the start address from primary flash to secondary flash based on the current address */
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    return FTFx_CMD_EraseSectorNonBlocking(&config->ftfxConfig[flashIndex], start, key);
+}
+
+/*!
+ * @brief Erases entire flexnvm
+ */
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key)
+{
+    return FTFx_CMD_EraseAll(&config->ftfxConfig[0], key);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flexnvm, including protected sectors.
+ */
+status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key)
+{
+    return FTFx_CMD_EraseAllUnsecure(&config->ftfxConfig[0], key);
+}
+#endif
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ */
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+
+    /* check range to get flash index */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+    /* convert the start address from primary flash to secondary flash based on the current address */
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    /* Programs flash */
+    return FTFx_CMD_Program(&config->ftfxConfig[flashIndex], start, src, lengthInBytes);
+}
+
+/*!
+ * @brief Reads the Program Once Field through parameters.
+ */
+status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint8_t *src, uint32_t lengthInBytes)
+{
+    return FTFx_CMD_ProgramOnce(&config->ftfxConfig[0], index, src, lengthInBytes);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ */
+status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+
+    /* Validates the range of the given address range and get flash index */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* convert the start address from primary flash to secondary flash based on the current address */
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    return FTFx_CMD_ProgramSection(&config->ftfxConfig[flashIndex], start, src, lengthInBytes);
+}
+#endif
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ */
+status_t FLASH_ReadResource(
+    flash_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option)
+{
+    return FTFx_CMD_ReadResource(&config->ftfxConfig[0], start, dst, lengthInBytes, option);
+}
+#endif
+
+/*!
+ * @brief Reads the Program Once Field through parameters.
+ */
+status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint8_t *dst, uint32_t lengthInBytes)
+{
+    return FTFx_CMD_ReadOnce(&config->ftfxConfig[0], index, dst, lengthInBytes);
+}
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ * to the specified read margin level.
+ */
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, ftfx_margin_value_t margin)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+
+    /* check range to get flash index */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* convert the start address from primary flash to secondary flash based on the current start address*/
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    return FTFx_CMD_VerifyErase(&config->ftfxConfig[flashIndex], start, lengthInBytes, margin);
+}
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ */
+status_t FLASH_VerifyEraseAll(flash_config_t *config, ftfx_margin_value_t margin)
+{
+    return FTFx_CMD_VerifyEraseAll(&config->ftfxConfig[0], margin);
+}
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programmed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ */
+status_t FLASH_VerifyProgram(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             const uint8_t *expectedData,
+                             ftfx_margin_value_t margin,
+                             uint32_t *failedAddress,
+                             uint32_t *failedData)
+{
+    status_t returnCode;
+    uint8_t flashIndex;
+
+    /* Validates the given address to get current flash index */
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    /* convert the start address from primary flash to secondary flash based on the current start address */
+    flash_convert_start_address(&config->ftfxConfig[flashIndex], start);
+
+    return FTFx_CMD_VerifyProgram(&config->ftfxConfig[flashIndex], start, lengthInBytes, expectedData, margin,
+                                  failedAddress, failedData);
+}
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ */
+status_t FLASH_GetSecurityState(flash_config_t *config, ftfx_security_state_t *state)
+{
+    return FTFx_REG_GetSecurityState(&config->ftfxConfig[0], state);
+}
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ */
+status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey)
+{
+    return FTFx_CMD_SecurityBypass(&config->ftfxConfig[0], backdoorKey);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ */
+status_t FLASH_SetFlexramFunction(flash_config_t *config, ftfx_flexram_func_opt_t option)
+{
+    return FTFx_CMD_SetFlexramFunction(&config->ftfxConfig[0], option);
+}
+#endif
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*!
+ * @brief Swaps the lower half flash with the higher half flash.
+ */
+status_t FLASH_Swap(flash_config_t *config, uint32_t address, bool isSetEnable)
+{
+    status_t returnCode;
+    ftfx_swap_state_config_t returnInfo;
+    ftfx_config_t *ftfxConfig;
+    uint8_t flashIndex;
+
+    returnCode = flash_check_range_to_get_index(config, address, 1U, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    ftfxConfig = &config->ftfxConfig[flashIndex];
+
+    (void)memset(&returnInfo, 0xFF, sizeof(returnInfo));
+
+    do
+    {
+        returnCode = FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionReportStatus, &returnInfo);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+
+        if (!isSetEnable)
+        {
+            if (returnInfo.flashSwapState == kFTFx_SwapStateDisabled)
+            {
+                return kStatus_FTFx_Success;
+            }
+            else if (returnInfo.flashSwapState == kFTFx_SwapStateUninitialized)
+            {
+                /* The swap system changed to the DISABLED state with Program flash block 0
+                 * located at relative flash address 0x0_0000 */
+                returnCode =
+                    FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionDisableSystem, &returnInfo);
+            }
+            else
+            {
+                /* Swap disable should be requested only when swap system is in the uninitialized state */
+                return kStatus_FTFx_SwapSystemNotInUninitialized;
+            }
+        }
+        else
+        {
+            /* When first swap: the initial swap state is Uninitialized, flash swap indicator address is unset,
+             *    the swap procedure should be Uninitialized -> Update-Erased -> Complete.
+             * After the first swap has been completed, the flash swap inidicator address cannot be modified
+             *    unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased ->
+             *    Complete. */
+            switch (returnInfo.flashSwapState)
+            {
+                case kFTFx_SwapStateUninitialized:
+                    /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */
+                    returnCode =
+                        FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionIntializeSystem, &returnInfo);
+                    break;
+                case kFTFx_SwapStateReady:
+                    /* Validate whether the address provided to the swap system is matched to
+                     * swap indicator address in the IFR */
+                    returnCode = flash_validate_swap_indicator_address(ftfxConfig, address);
+                    if (returnCode == kStatus_FTFx_Success)
+                    {
+                        /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */
+                        returnCode = FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionSetInUpdateState,
+                                                          &returnInfo);
+                    }
+                    break;
+                case kFTFx_SwapStateUpdate:
+                    /* If current swap mode is Update, Erase indicator sector in non active block
+                     * to proceed swap system to update-erased state */
+                    returnCode = FLASH_Erase(config, address + (ftfxConfig->flashDesc.totalSize >> 1u),
+                                             ftfxConfig->opsConfig.addrAligment.sectorCmd, (uint32_t)kFTFx_ApiEraseKey);
+                    break;
+                case kFTFx_SwapStateUpdateErased:
+                    /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */
+                    returnCode = FTFx_CMD_SwapControl(ftfxConfig, address, kFTFx_SwapControlOptionSetInCompleteState,
+                                                      &returnInfo);
+                    break;
+                case kFTFx_SwapStateComplete:
+                    break;
+                case kFTFx_SwapStateDisabled:
+                    /* When swap system is in disabled state, We need to clear swap system back to uninitialized
+                     * by issuing EraseAllBlocks command */
+                    returnCode = kStatus_FTFx_SwapSystemNotInUninitialized;
+                    break;
+                default:
+                    returnCode = kStatus_FTFx_InvalidArgument;
+                    break;
+            }
+        }
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            break;
+        }
+    } while (!((kFTFx_SwapStateComplete == returnInfo.flashSwapState) && isSetEnable));
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+/*!
+ * @brief Returns the protection state of the desired flash area via the pointer passed into the function.
+ */
+status_t FLASH_IsProtected(flash_config_t *config,
+                           uint32_t start,
+                           uint32_t lengthInBytes,
+                           flash_prot_state_t *protection_state)
+{
+    status_t returnCode;
+    ftfx_config_t *ftfxConfig;
+    uint8_t flashIndex;
+
+    if (protection_state == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    ftfxConfig = &config->ftfxConfig[flashIndex];
+
+#if (FTFx_FLASH_COUNT > 1U)
+    if (0U != (ftfxConfig->flashDesc.feature.hasProtControl))
+#endif
+    {
+        uint32_t endAddress;           /* end address for protection check */
+        uint32_t regionCheckedCounter; /* increments each time the flash address was checked for
+                                        * protection status */
+        uint32_t regionCounter;        /* incrementing variable used to increment through the flash
+                                        * protection regions */
+        uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */
+        uint8_t flashRegionProtectStatus[MAX_FLASH_PROT_REGION_COUNT]; /* array of the protection
+                                                                        * status for each
+                                                                        * protection region */
+        for (uint32_t i = 0U; i < (uint32_t)MAX_FLASH_PROT_REGION_COUNT;
+             i++)                                        /* The protection register is initialized to the */
+        {                                                /* unprotected state by default. */
+            flashRegionProtectStatus[i] = (uint8_t)0xFF; /* The array is initialized to all 1 */
+        }
+
+        uint32_t
+            flashRegionAddress[MAX_FLASH_PROT_REGION_COUNT + 1U]; /* array of the start addresses for each flash
+                                                                   * protection region. Note this is REGION_COUNT+1
+                                                                   * due to requiring the next start address after
+                                                                   * the end of flash for loop-check purposes below */
+        bool isBreakNeeded = false;
+        /* Calculate Flash end address */
+        endAddress = start + lengthInBytes;
+
+        /* populate the flashRegionAddress array with the start address of each flash region */
+        regionCounter = 0U; /* make sure regionCounter is initialized to 0 first */
+        /* populate up to 33rd element of array, this is the next address after end of flash array */
+        while (regionCounter <= ftfxConfig->flashDesc.protectRegionMem.count)
+        {
+            flashRegionAddress[regionCounter] = ftfxConfig->flashDesc.protectRegionMem.base +
+                                                ftfxConfig->flashDesc.protectRegionMem.size * regionCounter;
+            regionCounter++;
+        }
+
+        /* populate flashRegionProtectStatus array with status information
+         * Protection status for each region is stored in the FPROT[3:0] registers
+         * Each bit represents one region of flash
+         * 4 registers * 8-bits-per-register = 32-bits (32-regions)
+         * The convention is:
+         * FPROT3[bit 0] is the first protection region (start of flash memory)
+         * FPROT0[bit 7] is the last protection region (end of flash memory)
+         * regionCounter is used to determine which FPROT[3:0] register to check for protection status
+         * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+        regionCounter                            = 0U; /* make sure regionCounter is initialized to 0 first */
+        static volatile uint32_t *const kFPROTLx = (volatile uint32_t *)(uint32_t)&FTFx_FPROTL3_REG;
+
+#if defined(FTFx_FLASH0_HAS_HIGH_PROT_REG) && FTFx_FLASH0_HAS_HIGH_PROT_REG
+        static volatile uint32_t *const kFPROTHx = (volatile uint32_t *)(uint32_t)&FTFx_FPROTH3_REG;
+#endif
+
+#if defined(FTFx_FLASH1_HAS_INT_PROT_REG) && FTFx_FLASH1_HAS_INT_PROT_REG
+        static volatile uint16_t *const kFPROTSx = (volatile uint16_t *)(uint32_t)&FTFx_FPROTSL_REG;
+#endif
+        while (regionCounter < ftfxConfig->flashDesc.protectRegionMem.count)
+        {
+#if (FTFx_FLASH_COUNT > 1U)
+            if ((0U == ftfxConfig->flashDesc.index) || (0U != ftfxConfig->flashDesc.feature.hasIndProtReg))
+#endif
+            {
+#if defined(MAX_FLASH_PROT_REGION_COUNT) && (MAX_FLASH_PROT_REGION_COUNT <= 32U)
+                if (regionCounter < (uint32_t)MAX_FLASH_PROT_REGION_COUNT)
+                {
+                    flashRegionProtectStatus[regionCounter] = (uint8_t)(((kFPROTLx[0]) >> regionCounter) & 0x1U);
+                }
+#else
+                if (regionCounter < 32u)
+                {
+                    flashRegionProtectStatus[regionCounter] = (uint8_t)(((kFPROTLx[0]) >> regionCounter) & 0x1U);
+                }
+#endif
+#if defined(MAX_FLASH_PROT_REGION_COUNT) && (MAX_FLASH_PROT_REGION_COUNT == 64u)
+                else if (regionCounter < 64U)
+                {
+                    flashRegionProtectStatus[regionCounter] =
+                        (uint8_t)(((kFPROTHx[0]) >> (regionCounter - 32U)) & 0x1U);
+                }
+#endif
+                else
+                {
+                    isBreakNeeded = true;
+                }
+                regionCounter++;
+            }
+#if defined(FTFx_FLASH1_HAS_INT_PROT_REG) && FTFx_FLASH1_HAS_INT_PROT_REG
+            else if ((1U == ftfxConfig->flashDesc.index) && (0U != ftfxConfig->flashDesc.feature.hasIndProtReg))
+            {
+                /* Note: So far protection region count may be 8/16 */
+                if (regionCounter < 16U)
+                {
+                    flashRegionProtectStatus[regionCounter] = (uint8_t)((kFPROTSx[0] >> regionCounter) & (0x01u));
+                }
+                else
+                {
+                    isBreakNeeded = true;
+                }
+                regionCounter++;
+            }
+#endif /* FTFx_FLASH1_HAS_INT_PROT_REG */
+#if (FTFx_FLASH_COUNT > 1U)
+            else
+            {
+                return kStatus_FTFx_InvalidArgument;
+            }
+#endif
+            if (isBreakNeeded)
+            {
+                break;
+            }
+        }
+
+        /* loop through the flash regions and check
+         * desired flash address range for protection status
+         * loop stops when it is detected that start has exceeded the endAddress */
+        regionCounter        = 0U; /* make sure regionCounter is initialized to 0 first */
+        regionCheckedCounter = 0U;
+        protectStatusCounter = 0U; /* make sure protectStatusCounter is initialized to 0 first */
+        while (start < endAddress)
+        {
+            /* check to see if the address falls within this protection region
+             * Note that if the entire flash is to be checked, the last protection
+             * region checked would consist of the last protection start address and
+             * the start address following the end of flash */
+            if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1U]))
+            {
+                /* increment regionCheckedCounter to indicate this region was checked */
+                regionCheckedCounter++;
+
+                /* check the protection status of this region
+                 * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+                if (0U == flashRegionProtectStatus[regionCounter])
+                {
+                    /* increment protectStatusCounter to indicate this region is protected */
+                    protectStatusCounter++;
+                }
+                start +=
+                    ftfxConfig->flashDesc.protectRegionMem.size; /* increment to an address within the next region */
+            }
+            regionCounter++; /* increment regionCounter to check for the next flash protection region */
+        }
+
+        /* if protectStatusCounter == 0, then no region of the desired flash region is protected */
+        if (protectStatusCounter == 0U)
+        {
+            *protection_state = kFLASH_ProtectionStateUnprotected;
+        }
+        /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */
+        else if (protectStatusCounter == regionCheckedCounter)
+        {
+            *protection_state = kFLASH_ProtectionStateProtected;
+        }
+        /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed
+         * In other words, some regions are protected while others are unprotected */
+        else
+        {
+            *protection_state = kFLASH_ProtectionStateMixed;
+        }
+    }
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        *protection_state = kFLASH_ProtectionStateUnprotected;
+    }
+#endif
+
+    return kStatus_FTFx_Success;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*!
+ * @brief Returns the access state of the desired flash area via the pointer passed into the function.
+ *
+ * This function retrieves the current flash access status for a given
+ * flash area as determined by the start address and length.
+ */
+status_t FLASH_IsExecuteOnly(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             flash_xacc_state_t *access_state)
+{
+    status_t returnCode;
+    ftfx_config_t *ftfxConfig;
+    uint8_t flashIndex;
+
+    if (access_state == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    returnCode = flash_check_range_to_get_index(config, start, lengthInBytes, &flashIndex);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    ftfxConfig = &config->ftfxConfig[flashIndex];
+
+    /* store the execute only segment count */
+    uint32_t executeOnlySegmentCounter = 0U;
+
+    /* Calculate end address */
+    uint32_t endAddress = start + lengthInBytes;
+
+    /* Aligning start address and end address */
+    uint32_t alignedStartAddress = ALIGN_DOWN(start, ftfxConfig->flashDesc.accessSegmentMem.size);
+    uint32_t alignedEndAddress   = ALIGN_UP(endAddress, ftfxConfig->flashDesc.accessSegmentMem.size);
+
+    uint32_t u32flag      = 1U;
+    uint32_t segmentIndex = 0U;
+
+    /* Calculate the execute only segment Count */
+    uint32_t maxSupportedExecuteOnlySegmentCount =
+        (alignedEndAddress - alignedStartAddress) / ftfxConfig->flashDesc.accessSegmentMem.size;
+
+    while (start < endAddress)
+    {
+        uint32_t xacc              = 0U;
+        bool isInvalidSegmentIndex = false;
+
+        /* Calculate which segmentIndex the address is in */
+        segmentIndex =
+            (start - ftfxConfig->flashDesc.accessSegmentMem.base) / ftfxConfig->flashDesc.accessSegmentMem.size;
+
+        if ((0U == ftfxConfig->flashDesc.index) || (0U != ftfxConfig->flashDesc.feature.hasIndXaccReg))
+        {
+            /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size.
+             */
+            if (segmentIndex < 32U)
+            {
+                xacc = *(const volatile uint32_t *)(uint32_t)&FTFx_XACCL3_REG;
+            }
+            else if (segmentIndex < ftfxConfig->flashDesc.accessSegmentMem.count)
+            {
+                xacc = *(const volatile uint32_t *)(uint32_t)&FTFx_XACCH3_REG;
+                segmentIndex -= 32U;
+            }
+            else
+            {
+                isInvalidSegmentIndex = true;
+            }
+        }
+#if defined(FTFx_FLASH1_HAS_INT_XACC_REG) && FTFx_FLASH1_HAS_INT_XACC_REG
+        else if ((ftfxConfig->flashDesc.index == 1U) && (0u != ftfxConfig->flashDesc.feature.hasIndXaccReg))
+        {
+            /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size.
+             */
+            if (segmentIndex < 8U)
+            {
+                xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG;
+            }
+            else if (segmentIndex < ftfxConfig->flashDesc.accessSegmentMem.count)
+            {
+                xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG;
+                segmentIndex -= 8U;
+            }
+            else
+            {
+                isInvalidSegmentIndex = true;
+            }
+        }
+#endif
+        else
+        {
+            return kStatus_FTFx_InvalidArgument;
+        }
+
+        if (isInvalidSegmentIndex)
+        {
+            break;
+        }
+
+        /* Determine if this address range is in a execute-only protection flash segment. */
+        if (0U != ((~xacc) & (u32flag << segmentIndex)))
+        {
+            executeOnlySegmentCounter++;
+        }
+        /* Calculate tne next start address */
+        start += ftfxConfig->flashDesc.accessSegmentMem.size;
+    }
+
+    if (executeOnlySegmentCounter < 1u)
+    {
+        *access_state = kFLASH_AccessStateUnLimited;
+    }
+    else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount)
+    {
+        *access_state = kFLASH_AccessStateMixed;
+    }
+    else
+    {
+        *access_state = kFLASH_AccessStateExecuteOnly;
+    }
+
+    return kStatus_FTFx_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+/*!
+ * @brief Sets the PFlash Protection to the intended protection status.
+ *
+ * @param config A pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * corresponding to protection of 1/32(64) of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of PFlash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Most boards support program flash protect feature, The FPROT registers
+     * define which program flash regions are protected from program and erase operations.
+     * Protected flash regions cannot have their content changed;
+     * that is, these regions cannot be programmed and cannot be erased by any flash command
+     */
+#if (FTFx_FLASH_COUNT > 1U)
+    if (0U != (config->ftfxConfig[0].flashDesc.feature.hasProtControl))
+#endif
+    {
+        if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits >= 32U)
+        {
+            /* set PFlash protection register, unprotected regions are marked with a 1 and
+             * setting PFlash protection register, unprotected regions are marked with a 1 and
+             * protected regions use a 0; each bit of FPROT register can only be changed from 1s to 0s
+             * while all bits with 0s to 1s transitions are ignored.
+             */
+            *kFPROTL = protectStatus->protl;
+            if (protectStatus->protl != *kFPROTL)
+            {
+                return kStatus_FTFx_CommandFailure;
+            }
+        }
+#if defined(FTFx_FLASH0_HAS_HIGH_PROT_REG) && FTFx_FLASH0_HAS_HIGH_PROT_REG
+        /* For primary flash with eight PROT registers allow up to 64 protected segments of equal memory size. */
+        if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 64U)
+        {
+            *kFPROTH = protectStatus->proth;
+            if (protectStatus->proth != *kFPROTH)
+            {
+                return kStatus_FTFx_CommandFailure;
+            }
+        }
+#endif
+    }
+#if defined(FTFx_FLASH1_HAS_INT_PROT_REG) && FTFx_FLASH1_HAS_INT_PROT_REG
+    else if ((0U != config->ftfxConfig[1].flashDesc.feature.hasProtControl) &&
+             (0U != config->ftfxConfig[1].flashDesc.feature.hasIndProtReg))
+    {
+        /* For secondary flash with two FPROT registers allow up to 16 protected segments of equal memory size. */
+        if (config->ftfxConfig[1].flashDesc.feature.ProtRegBits == 16U)
+        {
+            *kFPROTSL = protectStatus->protsl;
+            if (protectStatus->protsl != *kFPROTSL)
+            {
+                return kStatus_FTFx_CommandFailure;
+            }
+            *kFPROTSH = protectStatus->protsh;
+            if (protectStatus->protsh != *kFPROTSH)
+            {
+                return kStatus_FTFx_CommandFailure;
+            }
+        }
+    }
+#endif
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        /*do nothing*/
+    }
+#endif
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Gets the PFlash protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  Protect status returned by the PFlash IP. Each bit is corresponding to the protection of
+ * 1/32(64)
+ * of the total PFlash. The least significant bit corresponds to the lowest address area of the PFlash.
+ * The most significant bit corresponds to the highest address area of PFlash. There are two possible cases as shown
+ * below: 0: this area is protected. 1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ */
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+#if (FTFx_FLASH_COUNT > 1U)
+    if (0U != (config->ftfxConfig[0].flashDesc.feature.hasProtControl))
+#endif
+    {
+        /* get the flash protect status */
+        if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits >= 32U)
+        {
+            protectStatus->protl = *kFPROTL;
+        }
+#if defined(FTFx_FLASH0_HAS_HIGH_PROT_REG) && FTFx_FLASH0_HAS_HIGH_PROT_REG
+        /* For primary flash with eight PROT registers allow up to 64 protected segments of equal memory size. */
+        if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 64U)
+        {
+            protectStatus->proth = *kFPROTH;
+        }
+#endif
+    }
+#if defined(FTFx_FLASH1_HAS_INT_PROT_REG) && FTFx_FLASH1_HAS_INT_PROT_REG
+    /* For secondary flash with two FPROT registers allow up to 16 protected segments of equal memory size. */
+    else if ((0U != config->ftfxConfig[1].flashDesc.feature.hasProtControl) &&
+             (0U != config->ftfxConfig[1].flashDesc.feature.hasIndProtReg))
+    {
+        if (config->ftfxConfig[0].flashDesc.feature.ProtRegBits == 16U)
+        {
+            protectStatus->protsl = *kFPROTSL;
+            protectStatus->protsh = *kFPROTSH;
+        }
+    }
+#endif
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        /*do nothing*/
+    }
+#endif
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Returns the desired flash property.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value A pointer to the value returned for the desired flash property.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_UnknownProperty An unknown property tag.
+ */
+status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
+{
+    if ((config == NULL) || (value == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    status_t status = kStatus_FTFx_Success;
+
+    switch (whichProperty)
+    {
+        /* gat Pflash0 sector size */
+        case kFLASH_PropertyPflash0SectorSize:
+            *value = config->ftfxConfig[0].flashDesc.sectorSize;
+            break;
+        /* gat Pflash0 total size */
+        case kFLASH_PropertyPflash0TotalSize:
+            *value = config->ftfxConfig[0].flashDesc.totalSize;
+            break;
+        /* gat Pflash0 block size */
+        case kFLASH_PropertyPflash0BlockSize:
+            *value = config->ftfxConfig[0].flashDesc.totalSize / config->ftfxConfig[0].flashDesc.blockCount;
+            break;
+        /* gat Pflash0 block cont */
+        case kFLASH_PropertyPflash0BlockCount:
+            *value = config->ftfxConfig[0].flashDesc.blockCount;
+            break;
+        /* gat Pflash0 block base address */
+        case kFLASH_PropertyPflash0BlockBaseAddr:
+            *value = config->ftfxConfig[0].flashDesc.blockBase;
+            break;
+        /* gat Pflash0 fac support feature */
+        case kFLASH_PropertyPflash0FacSupport:
+            *value = (uint32_t)config->ftfxConfig[0].flashDesc.feature.hasXaccControl;
+            break;
+        /* gat Pflash0 access segment size feature */
+        case kFLASH_PropertyPflash0AccessSegmentSize:
+            *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.size;
+            break;
+        /* gat Pflash0 access segment count feature */
+        case kFLASH_PropertyPflash0AccessSegmentCount:
+            *value = config->ftfxConfig[0].flashDesc.accessSegmentMem.count;
+            break;
+
+#if defined(FTFx_DRIVER_HAS_FLASH1_SUPPORT) && FTFx_DRIVER_HAS_FLASH1_SUPPORT
+        case kFLASH_PropertyPflash1SectorSize:
+            *value = config->ftfxConfig[1].flashDesc.sectorSize;
+            break;
+        case kFLASH_PropertyPflash1TotalSize:
+            *value = config->ftfxConfig[1].flashDesc.totalSize;
+            break;
+        case kFLASH_PropertyPflash1BlockSize:
+            *value = config->ftfxConfig[1].flashDesc.totalSize / config->ftfxConfig[1].flashDesc.blockCount;
+            break;
+        case kFLASH_PropertyPflash1BlockCount:
+            *value = config->ftfxConfig[1].flashDesc.blockCount;
+            break;
+        case kFLASH_PropertyPflash1BlockBaseAddr:
+            *value = config->ftfxConfig[1].flashDesc.blockBase;
+            break;
+        case kFLASH_PropertyPflash1FacSupport:
+            *value = (uint32_t)config->ftfxConfig[1].flashDesc.feature.hasXaccControl;
+            break;
+        case kFLASH_PropertyPflash1AccessSegmentSize:
+            *value = config->ftfxConfig[1].flashDesc.accessSegmentMem.size;
+            break;
+        case kFLASH_PropertyPflash1AccessSegmentCount:
+            *value = config->ftfxConfig[1].flashDesc.accessSegmentMem.count;
+            break;
+#endif
+        /* gat FlexRam block base addrese */
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+            *value = config->ftfxConfig[0].flexramBlockBase;
+            break;
+        /* gat FlexRam total size  */
+        case kFLASH_PropertyFlexRamTotalSize:
+            *value = config->ftfxConfig[0].flexramTotalSize;
+            break;
+
+        default: /* catch inputs that are not recognized */
+            status = kStatus_FTFx_UnknownProperty;
+            break;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief init flash FPROT, XACC registers and Independent flash block
+ */
+static void flash_init_features(ftfx_config_t *config)
+{
+    /* Initialize whether flash0 has independent block, protection registers and
+     * execute only access registers */
+#if (FTFx_FLASH_COUNT > 1U)
+    if (config->flashDesc.index == 0U)
+#endif
+    {
+        config->flashDesc.feature.isIndBlock      = 1U;
+        config->flashDesc.feature.hasIndPfsizeReg = 1U;
+        config->flashDesc.feature.hasIndProtReg   = 1U;
+        config->flashDesc.feature.hasIndXaccReg   = 1U;
+    }
+    /* if another flash exists */
+#if defined(FTFx_DRIVER_HAS_FLASH1_SUPPORT) && FTFx_DRIVER_HAS_FLASH1_SUPPORT
+    else if (config->flashDesc.index == 1U)
+    {
+        config->flashDesc.feature.isIndBlock      = FTFx_FLASH1_IS_INDEPENDENT_BLOCK;
+        config->flashDesc.feature.hasIndPfsizeReg = config->flashDesc.feature.isIndBlock;
+        config->flashDesc.feature.hasIndProtReg   = FTFx_FLASH1_HAS_INT_PROT_REG;
+        config->flashDesc.feature.hasIndXaccReg   = FTFx_FLASH1_HAS_INT_XACC_REG;
+    }
+#endif
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        /*do nothing*/
+    }
+#endif
+    /* init  protection Registers feature*/
+    config->flashDesc.feature.hasProtControl = 1U;
+    /* init  Execute-only Access Registers feature*/
+    config->flashDesc.feature.hasXaccControl = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL;
+}
+
+/*!
+ * @brief Initializes the flash operation config.
+ */
+static void flash_opsonfig_Init(flash_config_t *config, uint8_t flashIndex)
+{
+    uint32_t pflashStartAddress;
+    uint32_t pflashBlockSize;
+    uint32_t pflashBlockCount;
+    uint32_t pflashBlockSectorSize;
+    uint32_t pfsizeMask;
+    uint32_t pfsizeShift;
+    uint32_t pflashBlockWriteUnitSize;  /* store P-Flash write unit size */
+    uint32_t pflashSectorCmdAlignment;  /* store P-Flash Erase sector command address alignment */
+    uint32_t pflashSectionCmdAlignment; /* store Rrogram/Verify section command address alignment */
+
+#if (FTFx_FLASH_COUNT > 1U)
+    if (flashIndex == 1U)
+    {
+        pflashStartAddress        = FLASH1_FEATURE_PFLASH_START_ADDRESS;
+        pflashBlockSize           = FLASH1_FEATURE_PFLASH_BLOCK_SIZE;
+        pflashBlockCount          = FLASH1_FEATURE_PFLASH_BLOCK_COUNT;
+        pflashBlockSectorSize     = FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE;
+        pflashBlockWriteUnitSize  = FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+        pflashSectorCmdAlignment  = FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
+        pflashSectionCmdAlignment = FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
+        pfsizeMask                = SIM_FLASH1_PFSIZE_MASK;
+        pfsizeShift               = SIM_FLASH1_PFSIZE_SHIFT;
+    }
+    else
+#endif
+    {
+        pflashStartAddress        = FLASH0_FEATURE_PFLASH_START_ADDRESS; /* get P-Flash start address */
+        pflashBlockSize           = FLASH0_FEATURE_PFLASH_BLOCK_SIZE;
+        pflashBlockCount          = FLASH0_FEATURE_PFLASH_BLOCK_COUNT;
+        pflashBlockSectorSize     = FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE;
+        pflashBlockWriteUnitSize  = FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+        pflashSectorCmdAlignment  = FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
+        pflashSectionCmdAlignment = FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
+        pfsizeMask                = SIM_FLASH0_PFSIZE_MASK;
+        pfsizeShift               = SIM_FLASH0_PFSIZE_SHIFT;
+    }
+    /* init current flash start address */
+    config->ftfxConfig[flashIndex].flashDesc.blockBase = pflashStartAddress;
+    /* init current flash block count */
+    config->ftfxConfig[flashIndex].flashDesc.blockCount = pflashBlockCount;
+    /* init current flash block sector size */
+    config->ftfxConfig[flashIndex].flashDesc.sectorSize = pflashBlockSectorSize;
+
+#if (FTFx_FLASH_COUNT > 1U)
+    if ((0U != config->ftfxConfig[flashIndex].flashDesc.feature.isIndBlock) &&
+        (0U != config->ftfxConfig[flashIndex].flashDesc.feature.hasIndPfsizeReg))
+#endif
+    {
+        /* Calculate flash memory size based on given parameter */
+        config->ftfxConfig[flashIndex].flashDesc.totalSize =
+            flash_calculate_mem_size(pflashBlockCount, pflashBlockSize, pfsizeMask, pfsizeShift);
+    }
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        config->ftfxConfig[flashIndex].flashDesc.totalSize = pflashBlockCount * pflashBlockSize;
+    }
+#endif
+
+    /* init P-Flash write unit size */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.blockWriteUnitSize = (uint8_t)pflashBlockWriteUnitSize;
+    /* init P-Flash Erase sector command address alignment */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.sectorCmd = (uint8_t)pflashSectorCmdAlignment;
+    /* init P-Flash Rrogram/Verify section command address alignment */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.sectionCmd = (uint8_t)pflashSectionCmdAlignment;
+    /* init P-Flash Read resource command address alignment. */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.resourceCmd =
+        (uint8_t)FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT;
+    /* init P-Flash Program check command address alignment. */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.checkCmd =
+        (uint8_t)FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT;
+    /* init P-Flash swap command address alignment */
+    config->ftfxConfig[flashIndex].opsConfig.addrAligment.swapCtrlCmd =
+        (uint8_t)FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*! @brief init access segment feature */
+static void flash_access_init(flash_config_t *config, uint8_t flashIndex)
+{
+    ftfx_spec_mem_t *specMem;
+
+    /* start to initialize the structure of access segment */
+#if defined(FTFx_FLASH1_HAS_INT_XACC_REG) && FTFx_FLASH1_HAS_INT_XACC_REG
+    specMem = &config->ftfxConfig[flashIndex].flashDesc.accessSegmentMem;
+    if (flashIndex == 1U)
+    {
+        specMem->base  = config->ftfxConfig[flashIndex].flashDesc.blockBase;
+        specMem->size  = (uint32_t)kFTFx_AccessSegmentUnitSize << FTFx_FACSSS_REG;
+        specMem->count = FTFx_FACSNS_REG;
+    }
+    else
+#else
+    specMem = &config->ftfxConfig[0].flashDesc.accessSegmentMem;
+#endif /* FTFx_FLASH1_HAS_INT_XACC_REG */
+    {
+        specMem->base  = config->ftfxConfig[0].flashDesc.blockBase;
+        specMem->size  = (uint32_t)kFTFx_AccessSegmentUnitSize << FTFx_FACSS_REG;
+        specMem->count = FTFx_FACSN_REG;
+    }
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+/*! @brief init protection feature */
+static void flash_protection_init(flash_config_t *config, uint8_t flashIndex)
+{
+    uint32_t pflashProtectionRegionCount;
+#if (FTFx_FLASH_COUNT > 1U)
+    uint8_t i;
+
+    if (flashIndex == 1U)
+    {
+        /* store flash0 Protection region count */
+        pflashProtectionRegionCount = FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT;
+    }
+    else
+#endif // #if (FTFx_FLASH_COUNT > 1U)
+    {
+        /* store flash0 Protection region count */
+        pflashProtectionRegionCount = FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT;
+    }
+
+    /* Start to initialize the structure of protection features */
+    ftfx_spec_mem_t *specMem;
+    specMem = &config->ftfxConfig[flashIndex].flashDesc.protectRegionMem;
+#if (FTFx_FLASH_COUNT > 1U)
+    if (0U != (config->ftfxConfig[flashIndex].flashDesc.feature.hasIndProtReg))
+#endif // #if (FTFx_FLASH_COUNT > 1U)
+    {
+        specMem->base  = config->ftfxConfig[flashIndex].flashDesc.blockBase;
+        specMem->count = pflashProtectionRegionCount;
+        /* Calculate flash prot segment size */
+        specMem->size =
+            flash_calculate_prot_segment_size(config->ftfxConfig[flashIndex].flashDesc.totalSize, specMem->count);
+    }
+#if (FTFx_FLASH_COUNT > 1U)
+    else
+    {
+        uint32_t pflashTotalSize = 0U;
+        specMem->base            = config->ftfxConfig[0].flashDesc.blockBase;
+        specMem->count           = FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT;
+        if (flashIndex == FTFx_FLASH_COUNT - 1U)
+        {
+            uint32_t segmentSize; /* store the flash protection region count */
+            for (i = 0U; i < FTFx_FLASH_COUNT; i++)
+            {
+                /* get pflash total size*/
+                pflashTotalSize += config->ftfxConfig[flashIndex].flashDesc.totalSize;
+            }
+            /* get pflash port segment size based on parameters */
+            segmentSize = flash_calculate_prot_segment_size(pflashTotalSize, specMem->count);
+            for (i = 0U; i < FTFx_FLASH_COUNT; i++)
+            {
+                /* init flash0 and flash1 port segment size */
+                config->ftfxConfig[i].flashDesc.protectRegionMem.size = segmentSize;
+            }
+        }
+    }
+#endif // #if (FTFx_FLASH_COUNT > 1U)
+}
+
+/*!
+ * @brief Calculate flash memory size based on given parameter
+ */
+static uint32_t flash_calculate_mem_size(uint32_t pflashBlockCount,
+                                         uint32_t pflashBlockSize,
+                                         uint32_t pfsizeMask,
+                                         uint32_t pfsizeShift)
+{
+    uint8_t pfsize;
+    uint32_t flashDensity;
+
+    /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
+     * We just use the pre-defined flash size in feature file here to support pre-production parts */
+    pfsize = (uint8_t)((SIM_FCFG1_REG & pfsizeMask) >> pfsizeShift);
+    if (pfsize == 0xfU)
+    {
+        flashDensity = pflashBlockCount * pflashBlockSize;
+    }
+    else
+    {
+        flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10U;
+    }
+
+    return flashDensity;
+}
+
+/*!
+ * @brief Calculate flash prot segment size
+ */
+static uint32_t flash_calculate_prot_segment_size(uint32_t flashSize, uint32_t segmentCount)
+{
+    uint32_t segmentSize;
+
+    /* Calculate the size of the flash protection region
+     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
+     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
+    if (flashSize > segmentCount * (uint32_t)kFTFx_MinProtectBlockSize)
+    {
+        segmentSize = flashSize / segmentCount;
+    }
+    else
+    {
+        segmentSize = (uint32_t)kFTFx_MinProtectBlockSize;
+    }
+
+    return segmentSize;
+}
+
+/*!
+ * @brief Validates the given start address and length to get flash index
+ */
+static status_t flash_check_range_to_get_index(flash_config_t *config,
+                                               uint32_t start,
+                                               uint32_t lengthInBytes,
+                                               uint8_t *flashIndex)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Validates the range of the given address */
+    for (uint8_t index = 0U; index < FTFx_FLASH_COUNT; index++)
+    {
+        if ((start >= config->ftfxConfig[index].flashDesc.blockBase) &&
+            ((start + lengthInBytes) <=
+             (config->ftfxConfig[index].flashDesc.blockBase + config->ftfxConfig[index].flashDesc.totalSize)))
+        {
+            *flashIndex = config->ftfxConfig[index].flashDesc.index;
+            return kStatus_FTFx_Success;
+        }
+    }
+
+    return kStatus_FTFx_AddressError;
+}
+
+/*!
+ * @brief Decide whether to convert the start address from primary flash to secondary flash based on the current start
+ * address
+ */
+static void flash_convert_start_address(ftfx_config_t *config, uint32_t start)
+{
+    // The caller will guarantee that the config is valid
+#if (FTFx_FLASH_COUNT > 1U)
+    if ((0U != config->flashDesc.index) && (0U != config->flashDesc.feature.isIndBlock))
+    {
+        /* When required by the command, address bit 23 selects between main flash memory
+         * (=0) and secondary flash memory (=1).*/
+        config->opsConfig.convertedAddress = start - config->flashDesc.blockBase + 0x800000U;
+    }
+    else
+#endif
+    {
+        config->opsConfig.convertedAddress = start;
+    }
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*!
+ * @brief Validates the given address to see if it is equal to swap indicator address in pflash swap IFR.
+ */
+static status_t flash_validate_swap_indicator_address(ftfx_config_t *config, uint32_t address)
+{
+    status_t returnCode;
+    struct _flash_swap_ifr_field_config
+    {
+        uint16_t swapIndicatorAddress; /*!< A Swap indicator address field.*/
+        uint16_t swapEnableWord;       /*!< A Swap enable word field.*/
+        uint8_t reserved0[4];          /*!< A reserved field.*/
+        uint8_t reserved1[2];          /*!< A reserved field.*/
+        uint16_t swapDisableWord;      /*!< A Swap disable word field.*/
+        uint8_t reserved2[4];          /*!< A reserved field.*/
+    } flashSwapIfrFieldData;
+    uint32_t swapIndicatorAddress;
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+    returnCode =
+        FTFx_CMD_ReadResource(config, config->ifrDesc.resRange.pflashSwapIfrStart, (uint8_t *)&flashSwapIfrFieldData,
+                              sizeof(flashSwapIfrFieldData), kFTFx_ResourceOptionFlashIfr);
+
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+#else
+    {
+        /* From RM, the actual info are stored in FCCOB6,7 */
+        uint32_t returnValue[2];
+        returnCode = FTFx_CMD_ReadOnce(config, (uint32_t)kFLASH_RecordIndexSwapAddr, (uint8_t *)returnValue, 4U);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.swapIndicatorAddress = (uint16_t)returnValue[0];
+        returnCode = FTFx_CMD_ReadOnce(config, (uint32_t)kFLASH_RecordIndexSwapEnable, (uint8_t *)returnValue, 4U);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+
+        returnCode = FTFx_CMD_ReadOnce(config, (uint32_t)kFLASH_RecordIndexSwapDisable, (uint8_t *)returnValue, 4U);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return returnCode;
+        }
+    }
+#endif
+
+    /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
+     * the low several bit value of Swap Indicator Address is always 1'b0 */
+    swapIndicatorAddress =
+        (uint32_t)flashSwapIfrFieldData.swapIndicatorAddress * config->opsConfig.addrAligment.swapCtrlCmd;
+    if (address != swapIndicatorAddress)
+    {
+        return kStatus_FTFx_SwapIndicatorAddressError;
+    }
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+status_t FLASH_GetCommandState(void)
+{
+    uint8_t registerValue;
+    uint32_t idleFlag;
+
+    /* Get flash status register value */
+    registerValue = FTFx->FSTAT;
+
+    /* Check DONE bit of the flash status register */
+    idleFlag = ((uint32_t)registerValue & FTFx_FSTAT_CCIF_MASK) >> FTFx_FSTAT_CCIF_SHIFT;
+    if (idleFlag == 0U)
+    {
+        return kStatus_FTFx_CommandOperationInProgress;
+    }
+    else
+    {
+        /* Check error bits */
+        /* checking access error */
+        if (0U != (registerValue & FTFx_FSTAT_ACCERR_MASK))
+        {
+            return kStatus_FTFx_AccessError;
+        }
+        /* checking protection error */
+        else if (0U != (registerValue & FTFx_FSTAT_FPVIOL_MASK))
+        {
+            return kStatus_FTFx_ProtectionViolation;
+        }
+        /* checking MGSTAT0 non-correctable error */
+        else if (0U != (registerValue & FTFx_FSTAT_MGSTAT0_MASK))
+        {
+            return kStatus_FTFx_CommandFailure;
+        }
+        else
+        {
+            return kStatus_FTFx_Success;
+        }
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.h
new file mode 100644
index 0000000000..8d5b92aa67
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flash.h
@@ -0,0 +1,705 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_FLASH_H
+#define FSL_FTFX_FLASH_H
+
+#include "fsl_ftfx_controller.h"
+
+/*!
+ * @addtogroup ftfx_flash_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define kStatus_FLASH_Success kStatus_FTFx_Success
+#define kFLASH_ApiEraseKey    kFTFx_ApiEraseKey
+
+/*!
+ * @name Flash version
+ * @{
+ */
+/*! @brief Flash driver version for SDK*/
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(3U, 1U, 3U)) /*!< Version 3.1.3. */
+
+/*! @brief Flash driver version for ROM*/
+#define FSL_FLASH_DRIVER_VERSION_ROM (MAKE_VERSION(3U, 0U, 0U)) /*!< Version 3.0.0. */
+
+/*! @} */
+
+/*!
+ * @brief Enumeration for the three possible flash protection levels.
+ */
+typedef enum _flash_protection_state
+{
+    kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/
+    kFLASH_ProtectionStateProtected,   /*!< Flash region is protected.*/
+    kFLASH_ProtectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
+} flash_prot_state_t;
+
+/*!
+ * @brief PFlash protection status
+ */
+typedef union _pflash_protection_status
+{
+    uint32_t protl; /*!< PROT[31:0] .*/
+    uint32_t proth; /*!< PROT[63:32].*/
+    uint8_t protsl; /*!< PROTS[7:0] .*/
+    uint8_t protsh; /*!< PROTS[15:8] .*/
+    uint8_t reserved[2];
+} pflash_prot_status_t;
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*!
+ * @brief Enumeration for the three possible flash execute access levels.
+ */
+typedef enum _flash_execute_only_access_state
+{
+    kFLASH_AccessStateUnLimited,   /*!< Flash region is unlimited.*/
+    kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/
+    kFLASH_AccessStateMixed        /*!< Flash is mixed with unlimited and execute only region.*/
+} flash_xacc_state_t;
+#endif /* not define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+/*!
+ * @brief Enumeration for various flash properties.
+ */
+typedef enum _flash_property_tag
+{
+    kFLASH_PropertyPflash0SectorSize         = 0x00U, /*!< Pflash sector size property.*/
+    kFLASH_PropertyPflash0TotalSize          = 0x01U, /*!< Pflash total size property.*/
+    kFLASH_PropertyPflash0BlockSize          = 0x02U, /*!< Pflash block size property.*/
+    kFLASH_PropertyPflash0BlockCount         = 0x03U, /*!< Pflash block count property.*/
+    kFLASH_PropertyPflash0BlockBaseAddr      = 0x04U, /*!< Pflash block base address property.*/
+    kFLASH_PropertyPflash0FacSupport         = 0x05U, /*!< Pflash fac support property.*/
+    kFLASH_PropertyPflash0AccessSegmentSize  = 0x06U, /*!< Pflash access segment size property.*/
+    kFLASH_PropertyPflash0AccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
+
+    kFLASH_PropertyPflash1SectorSize         = 0x10U, /*!< Pflash sector size property.*/
+    kFLASH_PropertyPflash1TotalSize          = 0x11U, /*!< Pflash total size property.*/
+    kFLASH_PropertyPflash1BlockSize          = 0x12U, /*!< Pflash block size property.*/
+    kFLASH_PropertyPflash1BlockCount         = 0x13U, /*!< Pflash block count property.*/
+    kFLASH_PropertyPflash1BlockBaseAddr      = 0x14U, /*!< Pflash block base address property.*/
+    kFLASH_PropertyPflash1FacSupport         = 0x15U, /*!< Pflash fac support property.*/
+    kFLASH_PropertyPflash1AccessSegmentSize  = 0x16U, /*!< Pflash access segment size property.*/
+    kFLASH_PropertyPflash1AccessSegmentCount = 0x17U, /*!< Pflash access segment count property.*/
+
+    kFLASH_PropertyFlexRamBlockBaseAddr = 0x20U, /*!< FlexRam block base address property.*/
+    kFLASH_PropertyFlexRamTotalSize     = 0x21U, /*!< FlexRam total size property.*/
+} flash_property_tag_t;
+
+/*! @brief Flash driver state information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _flash_config
+{
+    ftfx_config_t ftfxConfig[FTFx_FLASH_COUNT];
+} flash_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLASH_Init(flash_config_t *config);
+
+/*! @} */
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the appropriate number of flash sectors based on the
+ *         desired start address and length were erased successfully.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ *
+ * This function erases one flash sector size based on the start address, and it is
+ * executed asynchronously.
+ *
+ * NOTE: This function can only erase one flash sector at a time, and the other commands
+ *       can be executed after the previous command has been completed.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ */
+status_t FLASH_EraseSectorNonBlocking(flash_config_t *config, uint32_t start, uint32_t key);
+
+/*!
+ * @brief Erases entire flexnvm
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the all pflash and flexnvm were erased successfully,
+ *         the swap and eeprom have been reset to unconfigured state.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flexnvm, including protected sectors.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully;
+ *         the protected sectors of flash were reset to unprotected status.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+/*! @} */
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired data were programed successfully
+ *         into flash based on desired start address and length.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Program the Program-Once-Field through parameters.
+ *
+ * This function Program the Program-once-feild with given index and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating the area of program once field to be read.
+ * @param src A pointer to the source buffer of data that is used to store
+ *        data to be write.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; The index indicating the area
+ *         of program once field was programed successfully.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint8_t *src, uint32_t lengthInBytes);
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired data have been programed successfully into
+ *         flash based on start address and length.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_SetFlexramAsRamError Failed to set flexram as RAM.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM.
+ */
+status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+/*! @} */
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ *
+ * This function reads the flash memory with the desired location for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param dst A pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be read. Must be word-aligned.
+ * @param option The resource option which indicates which area should be read back.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully;  the data have been read successfully from
+ *         program flash IFR, data flash IFR space, and the Version ID field.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_ReadResource(
+    flash_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+/*!
+ * @brief Reads the Program Once Field through parameters.
+ *
+ * This function reads the read once feild with given index and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating the area of program once field to be read.
+ * @param dst A pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the data have been successfuly
+ *         read form Program flash0 IFR map and Program Once field based on index and length.
+
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint8_t *dst, uint32_t lengthInBytes);
+
+/*! @} */
+
+/*!
+ * @name Verification
+ * @{
+ */
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ * to the specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the specified FLASH region has been erased.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ *
+ * This function checks whether the flash is erased to the
+ * specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; all program flash and flexnvm were in erased state.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_VerifyEraseAll(flash_config_t *config, ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programmed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param expectedData A pointer to the expected data that is to be
+ *        verified against.
+ * @param margin Read margin choice.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
+ *        case, zeros are returned upon failure.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired data have been successfully programed into
+ *         specified FLASH region.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_VerifyProgram(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             const uint8_t *expectedData,
+                             ftfx_margin_value_t margin,
+                             uint32_t *failedAddress,
+                             uint32_t *failedData);
+
+/*! @} */
+
+/*!
+ * @name Security
+ * @{
+ */
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ *
+ * This function retrieves the current flash security status, including the
+ * security enabling state and the backdoor key enabling state.
+ *
+ * @param config A pointer to storage for the driver runtime state.
+ * @param state A pointer to the value returned for the current security status code:
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the security state of flash was stored to state.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ */
+status_t FLASH_GetSecurityState(flash_config_t *config, ftfx_security_state_t *state);
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ *
+ * If the MCU is in secured state, this function unsecures the MCU by
+ * comparing the provided backdoor key with ones in the flash configuration
+ * field.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param backdoorKey A pointer to the user buffer containing the backdoor key.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey);
+
+/*! @} */
+
+/*!
+ * @name FlexRAM
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option The option used to set the work mode of FlexRAM.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the FlexRAM has been successfully configured as RAM or
+ * EEPROM.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_SetFlexramFunction(flash_config_t *config, ftfx_flexram_func_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*! @} */
+
+/*!
+ * @name Swap
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*!
+ * @brief Swaps the lower half flash with the higher half flash.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param address Address used to configure the flash swap function
+ * @param isSetEnable The possible option used to configure the Flash Swap function or check the flash Swap status.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the lower half flash and higher half flash have been
+ * swaped.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_SwapSystemNotInUninitialized Swap system is not in an uninitialized state.
+ */
+status_t FLASH_Swap(flash_config_t *config, uint32_t address, bool isSetEnable);
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+/*! @} */
+
+/*!
+ * @name Protection
+ * @{
+ */
+
+/*!
+ * @brief Returns the protection state of the desired flash area via the pointer passed into the function.
+ *
+ * This function retrieves the current flash protect status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be checked.  Must be word-aligned.
+ * @param protection_state A pointer to the value returned for the current
+ *        protection status code for the desired flash area.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the protection state of specified FLASH region was
+ * stored to protection_state.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ */
+status_t FLASH_IsProtected(flash_config_t *config,
+                           uint32_t start,
+                           uint32_t lengthInBytes,
+                           flash_prot_state_t *protection_state);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*!
+ * @brief Returns the access state of the desired flash area via the pointer passed into the function.
+ *
+ * This function retrieves the current flash access status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be checked.  Must be word-aligned.
+ * @param access_state A pointer to the value returned for the current
+ *        access status code for the desired flash area.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the executeOnly state of specified FLASH region was
+ * stored to access_state.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned to the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ */
+status_t FLASH_IsExecuteOnly(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             flash_xacc_state_t *access_state);
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+/*!
+ * @brief Sets the PFlash Protection to the intended protection status.
+ *
+ * @param config A pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * corresponding to protection of 1/32(64) of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of PFlash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the specified FLASH region is protected.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus);
+
+/*!
+ * @brief Gets the PFlash protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  Protect status returned by the PFlash IP. Each bit is corresponding to the protection of
+ * 1/32(64)
+ * of the
+ * total PFlash. The least significant bit corresponds to the lowest address area of the PFlash. The most significant
+ * bit corresponds to the highest address area of PFlash. There are two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the Protection state was stored to protectStatus;
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ */
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_prot_status_t *protectStatus);
+
+/*! @} */
+
+/*!
+ * @name Properties
+ * @{
+ */
+
+/*!
+ * @brief Returns the desired flash property.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value A pointer to the value returned for the desired flash property.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the flash property was stored to value.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_UnknownProperty An unknown property tag.
+ */
+status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
+
+/*! @} */
+
+/*!
+ * @name commantStatus
+ * @{
+ */
+
+/*!
+ * @brief Get previous command status.
+ *
+ * This function is used to obtain the execution status of the previous command.
+ *
+ * @retval #kStatus_FTFx_Success The previous command is executed successfully.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLASH_GetCommandState(void);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FTFX_FLASH_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.c
new file mode 100644
index 0000000000..d8b2743f47
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "fsl_ftfx_flexnvm.h"
+
+#if FSL_FEATURE_FLASH_HAS_FLEX_NVM
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*! @brief Convert address for Flexnvm dflash.*/
+static status_t flexnvm_convert_start_address(flexnvm_config_t *config, uint32_t start);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t FLEXNVM_Init(flexnvm_config_t *config)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    config->ftfxConfig.flashDesc.type  = (uint8_t)kFTFx_MemTypeFlexnvm;
+    config->ftfxConfig.flashDesc.index = 0U;
+
+    /* Set Flexnvm memory operation parameters */
+    config->ftfxConfig.opsConfig.addrAligment.blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE;
+    config->ftfxConfig.opsConfig.addrAligment.sectorCmd   = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT;
+    config->ftfxConfig.opsConfig.addrAligment.sectionCmd  = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT;
+    config->ftfxConfig.opsConfig.addrAligment.resourceCmd = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT;
+    config->ftfxConfig.opsConfig.addrAligment.checkCmd    = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT;
+
+    /* Set Flexnvm memory properties */
+    config->ftfxConfig.flashDesc.blockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS;
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS) && FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS
+    config->ftfxConfig.flashDesc.aliasBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS;
+#endif
+    config->ftfxConfig.flashDesc.sectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
+    config->ftfxConfig.flashDesc.blockCount = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
+
+    /* Init FTFx Kernel */
+    FTFx_API_Init(&config->ftfxConfig);
+
+    returnCode = FTFx_API_UpdateFlexnvmPartitionStatus(&config->ftfxConfig);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ */
+status_t FLEXNVM_DflashErase(flexnvm_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+    status_t returnCode;
+    returnCode = flexnvm_convert_start_address(config, start);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return FTFx_CMD_Erase(&config->ftfxConfig, start, lengthInBytes, key);
+}
+
+/*!
+ * @brief Erases entire flexnvm
+ */
+status_t FLEXNVM_EraseAll(flexnvm_config_t *config, uint32_t key)
+{
+    return FTFx_CMD_EraseAll(&config->ftfxConfig, key);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flexnvm, including protected sectors.
+ */
+status_t FLEXNVM_EraseAllUnsecure(flexnvm_config_t *config, uint32_t key)
+{
+    return FTFx_CMD_EraseAllUnsecure(&config->ftfxConfig, key);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ */
+status_t FLEXNVM_DflashProgram(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    returnCode = flexnvm_convert_start_address(config, start);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return FTFx_CMD_Program(&config->ftfxConfig, start, src, lengthInBytes);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ */
+status_t FLEXNVM_DflashProgramSection(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    /* Convert address for Flexnvm dflash */
+    returnCode = flexnvm_convert_start_address(config, start);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return FTFx_CMD_ProgramSection(&config->ftfxConfig, start, src, lengthInBytes);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination
+ * of both and initializes the FlexRAM.
+ */
+status_t FLEXNVM_ProgramPartition(flexnvm_config_t *config,
+                                  ftfx_partition_flexram_load_opt_t option,
+                                  uint32_t eepromDataSizeCode,
+                                  uint32_t flexnvmPartitionCode)
+{
+    return FTFx_CMD_ProgramPartition(&config->ftfxConfig, option, eepromDataSizeCode, flexnvmPartitionCode);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ */
+status_t FLEXNVM_ReadResource(
+    flexnvm_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option)
+{
+    return FTFx_CMD_ReadResource(&config->ftfxConfig, start, dst, lengthInBytes, option);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ */
+status_t FLEXNVM_DflashVerifyErase(flexnvm_config_t *config,
+                                   uint32_t start,
+                                   uint32_t lengthInBytes,
+                                   ftfx_margin_value_t margin)
+{
+    status_t returnCode;
+    returnCode = flexnvm_convert_start_address(config, start);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return FTFx_CMD_VerifyErase(&config->ftfxConfig, start, lengthInBytes, margin);
+}
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ */
+status_t FLEXNVM_VerifyEraseAll(flexnvm_config_t *config, ftfx_margin_value_t margin)
+{
+    return FTFx_CMD_VerifyEraseAll(&config->ftfxConfig, margin);
+}
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ */
+status_t FLEXNVM_DflashVerifyProgram(flexnvm_config_t *config,
+                                     uint32_t start,
+                                     uint32_t lengthInBytes,
+                                     const uint8_t *expectedData,
+                                     ftfx_margin_value_t margin,
+                                     uint32_t *failedAddress,
+                                     uint32_t *failedData)
+{
+    status_t returnCode;
+    returnCode = flexnvm_convert_start_address(config, start);
+    if (returnCode != kStatus_FTFx_Success)
+    {
+        return returnCode;
+    }
+
+    return FTFx_CMD_VerifyProgram(&config->ftfxConfig, start, lengthInBytes, expectedData, margin, failedAddress,
+                                  failedData);
+}
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ */
+status_t FLEXNVM_GetSecurityState(flexnvm_config_t *config, ftfx_security_state_t *state)
+{
+    return FTFx_REG_GetSecurityState(&config->ftfxConfig, state);
+}
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ */
+status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoorKey)
+{
+    return FTFx_CMD_SecurityBypass(&config->ftfxConfig, backdoorKey);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ */
+status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_opt_t option)
+{
+    return FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, option);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*!
+ * @brief Programs the EEPROM with data at locations passed in through parameters.
+ */
+status_t FLEXNVM_EepromWrite(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    bool needSwitchFlexRamMode = false;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* Validates the range of the given address */
+    if ((start < config->ftfxConfig.flexramBlockBase) ||
+        ((start + lengthInBytes) > (config->ftfxConfig.flexramBlockBase + config->ftfxConfig.eepromTotalSize)))
+    {
+        return kStatus_FTFx_AddressError;
+    }
+
+    returnCode = kStatus_FTFx_Success;
+
+    /* Switch function of FlexRAM if needed */
+    if (0U == (FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+    {
+        needSwitchFlexRamMode = true;
+
+        returnCode = FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, kFTFx_FlexramFuncOptAvailableForEeprom);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return kStatus_FTFx_SetFlexramAsEepromError;
+        }
+    }
+
+    /* Write data to FlexRAM when it is used as EEPROM emulator */
+    while (lengthInBytes > 0U)
+    {
+        if ((0U == (start & 0x3U)) && (0U == ((uint32_t)src & 0x3U)) && (lengthInBytes >= 4U))
+        {
+            *(uint32_t *)start = *(uint32_t *)(uint32_t)src;
+            start += 4U;
+            src = &src[4];
+            lengthInBytes -= 4U;
+        }
+        else if ((0U == (start & 0x1U)) && (0U == ((uint32_t)src & 0x1U)) && (lengthInBytes >= 2U))
+        {
+            *(uint16_t *)start = *(uint16_t *)(uint32_t)src;
+            start += 2U;
+            src = &src[2];
+            lengthInBytes -= 2U;
+        }
+        else
+        {
+            *(uint8_t *)start = *src;
+            start += 1U;
+            src = &src[1];
+            lengthInBytes -= 1U;
+        }
+        /* Wait till EEERDY bit is set */
+        while (0U == (FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+        {
+        }
+
+        /* Check for protection violation error */
+        if (0U != (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK))
+        {
+            return kStatus_FTFx_ProtectionViolation;
+        }
+    }
+
+    /* Switch function of FlexRAM if needed */
+    if (needSwitchFlexRamMode)
+    {
+        returnCode = FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, kFTFx_FlexramFuncOptAvailableAsRam);
+        if (returnCode != kStatus_FTFx_Success)
+        {
+            return kStatus_FTFx_RecoverFlexramAsRamError;
+        }
+    }
+
+    return returnCode;
+}
+
+/*!
+ * @brief Sets the DFlash protection to the intended protection status.
+ */
+status_t FLEXNVM_DflashSetProtection(flexnvm_config_t *config, uint8_t protectStatus)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    if ((config->ftfxConfig.flashDesc.totalSize == 0U) || (config->ftfxConfig.flashDesc.totalSize == 0xFFFFFFFFU))
+    {
+        return kStatus_FTFx_CommandNotSupported;
+    }
+
+    /* Individual data flash regions will be protected from program and erase operations by setting the
+     * associated DPROT bit to the protected state. Each FDPROT bit only be changed from 1s to 0s,
+     * meaning the protection can only be increased */
+    FTFx->FDPROT = protectStatus;
+
+    if (FTFx->FDPROT != protectStatus)
+    {
+        return kStatus_FTFx_CommandFailure;
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Gets the DFlash protection status.
+ */
+status_t FLEXNVM_DflashGetProtection(flexnvm_config_t *config, uint8_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    if ((config->ftfxConfig.flashDesc.totalSize == 0U) || (config->ftfxConfig.flashDesc.totalSize == 0xFFFFFFFFU))
+    {
+        return kStatus_FTFx_CommandNotSupported;
+    }
+
+    /* return the flexnvm DFlash protection status */
+    *protectStatus = FTFx->FDPROT;
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Sets the EEPROM protection to the intended protection status.
+ */
+status_t FLEXNVM_EepromSetProtection(flexnvm_config_t *config, uint8_t protectStatus)
+{
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    if ((config->ftfxConfig.eepromTotalSize == 0U) || (config->ftfxConfig.eepromTotalSize == 0xFFFFU))
+    {
+        return kStatus_FTFx_CommandNotSupported;
+    }
+    /* Individual data flash regions will be protected from program and erase operations by setting the
+     * associated FEPROT bit to the protected state; Each FEPROT bit only be changed from 1s to 0s,
+     * meaning the protection can only be increased. */
+    FTFx->FEPROT = protectStatus;
+
+    if (FTFx->FEPROT != protectStatus)
+    {
+        return kStatus_FTFx_CommandFailure;
+    }
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Gets the EEPROM protection status.
+ */
+status_t FLEXNVM_EepromGetProtection(flexnvm_config_t *config, uint8_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    if ((config->ftfxConfig.eepromTotalSize == 0U) || (config->ftfxConfig.eepromTotalSize == 0xFFFFU))
+    {
+        return kStatus_FTFx_CommandNotSupported;
+    }
+
+    /* return EEPROM protection status */
+    *protectStatus = FTFx->FEPROT;
+
+    return kStatus_FTFx_Success;
+}
+
+/*!
+ * @brief Returns the desired flexnvm property.
+ */
+status_t FLEXNVM_GetProperty(flexnvm_config_t *config, flexnvm_property_tag_t whichProperty, uint32_t *value)
+{
+    if ((config == NULL) || (value == NULL))
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    status_t status = kStatus_FTFx_Success;
+
+    switch (whichProperty)
+    {
+        /* get flexnvm date flash sector size */
+        case kFLEXNVM_PropertyDflashSectorSize:
+            *value = config->ftfxConfig.flashDesc.sectorSize;
+            break;
+        /* get flexnvm date flash total size */
+        case kFLEXNVM_PropertyDflashTotalSize:
+            *value = config->ftfxConfig.flashDesc.totalSize;
+            break;
+        /* get flexnvm date flash block size */
+        case kFLEXNVM_PropertyDflashBlockSize:
+            *value = config->ftfxConfig.flashDesc.totalSize / config->ftfxConfig.flashDesc.blockCount;
+            break;
+        /* get flexnvm date flash block cont */
+        case kFLEXNVM_PropertyDflashBlockCount:
+            *value = config->ftfxConfig.flashDesc.blockCount;
+            break;
+        /* get flexnvm date flash block base address */
+        case kFLEXNVM_PropertyDflashBlockBaseAddr:
+            *value = config->ftfxConfig.flashDesc.blockBase;
+            break;
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS) && FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS
+        case kFLEXNVM_PropertyAliasDflashBlockBaseAddr:
+            *value = config->ftfxConfig.flashDesc.aliasBlockBase;
+            break;
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS */
+        case kFLEXNVM_PropertyFlexRamBlockBaseAddr:
+            *value = config->ftfxConfig.flexramBlockBase;
+            break;
+        /* get flexram total size */
+        case kFLEXNVM_PropertyFlexRamTotalSize:
+            *value = config->ftfxConfig.flexramTotalSize;
+            break;
+        /* get flexnvm eeprom total size */
+        case kFLEXNVM_PropertyEepromTotalSize:
+            *value = config->ftfxConfig.eepromTotalSize;
+            break;
+        /* catch inputs that are not recognized */
+        default:
+            status = kStatus_FTFx_UnknownProperty;
+            break;
+    }
+    return status;
+}
+
+/*! @brief Convert address for Flexnvm dflash.*/
+static status_t flexnvm_convert_start_address(flexnvm_config_t *config, uint32_t start)
+{
+    status_t status = kStatus_FTFx_AddressError;
+
+    if (config == NULL)
+    {
+        return kStatus_FTFx_InvalidArgument;
+    }
+
+    /* From Spec: When required by the command, address bit 23 selects between program flash memory
+     * (=0) and data flash memory (=1).*/
+    if (start >= config->ftfxConfig.flashDesc.blockBase)
+    {
+        config->ftfxConfig.opsConfig.convertedAddress = start - config->ftfxConfig.flashDesc.blockBase + 0x800000U;
+        status                                        = kStatus_FTFx_Success;
+    }
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS) && FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS
+    /* for MKW39/38/37 which have alias blockBase */
+    else if (start >= config->ftfxConfig.flashDesc.aliasBlockBase)
+    {
+        config->ftfxConfig.opsConfig.convertedAddress = start - config->ftfxConfig.flashDesc.aliasBlockBase + 0x800000U;
+        status                                        = kStatus_FTFx_Success;
+    }
+    else
+    {
+        status = kStatus_FTFx_Success;
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS */
+
+    return status;
+}
+
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.h
new file mode 100644
index 0000000000..57d044ff39
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_flexnvm.h
@@ -0,0 +1,564 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_FLEXNVM_H
+#define FSL_FTFX_FLEXNVM_H
+
+#include "fsl_ftfx_controller.h"
+
+/*!
+ * @addtogroup ftfx_flexnvm_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Enumeration for various flexnvm properties.
+ */
+typedef enum _flexnvm_property_tag
+{
+    kFLEXNVM_PropertyDflashSectorSize         = 0x00U, /*!< Dflash sector size property.*/
+    kFLEXNVM_PropertyDflashTotalSize          = 0x01U, /*!< Dflash total size property.*/
+    kFLEXNVM_PropertyDflashBlockSize          = 0x02U, /*!< Dflash block size property.*/
+    kFLEXNVM_PropertyDflashBlockCount         = 0x03U, /*!< Dflash block count property.*/
+    kFLEXNVM_PropertyDflashBlockBaseAddr      = 0x04U, /*!< Dflash block base address property.*/
+    kFLEXNVM_PropertyAliasDflashBlockBaseAddr = 0x05U, /*!< Dflash block base address Alias property.*/
+    kFLEXNVM_PropertyFlexRamBlockBaseAddr     = 0x06U, /*!< FlexRam block base address property.*/
+    kFLEXNVM_PropertyFlexRamTotalSize         = 0x07U, /*!< FlexRam total size property.*/
+    kFLEXNVM_PropertyEepromTotalSize          = 0x08U, /*!< EEPROM total size property.*/
+} flexnvm_property_tag_t;
+
+/*! @brief Flexnvm driver state information.
+ *
+ * An instance of this structure is allocated by the user of the Flexnvm driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _flexnvm_config
+{
+    ftfx_config_t ftfxConfig;
+} flexnvm_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLEXNVM_Init(flexnvm_config_t *config);
+
+/*! @} */
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erases the Dflash sectors encompassed by parameters passed into function.
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the appropriate number of date flash sectors based on
+ * the desired start address and length were erased successfully.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError The address is out of range.
+ * @retval #kStatus_FTFx_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_DflashErase(flexnvm_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+
+/*!
+ * @brief Erases entire flexnvm
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the entire flexnvm has been erased successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLEXNVM_EraseAll(flexnvm_config_t *config, uint32_t key);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+/*!
+ * @brief Erases the entire flexnvm, including protected sectors.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the flexnvm is not in securityi state.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_PartitionStatusUpdateFailure Failed to update the partition status.
+ */
+status_t FLEXNVM_EraseAllUnsecure(flexnvm_config_t *config, uint32_t key);
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+/*! @} */
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired date have been successfully
+ *         programed into specified date flash region.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_DflashProgram(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired date have been successfully
+ *         programed into specified date flash area.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_SetFlexramAsRamError Failed to set flexram as RAM.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FTFx_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM.
+ */
+status_t FLEXNVM_DflashProgramSection(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the
+ * FlexRAM.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set FlexRAM load behavior during reset.
+ * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems.
+ * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
+ *        memory supporting EEPROM functions.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the FlexNVM block for use as data flash, EEPROM backup,
+ *         or a combination of both have been Prepared.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FLEXNVM_ProgramPartition(flexnvm_config_t *config,
+                                  ftfx_partition_flexram_load_opt_t option,
+                                  uint32_t eepromDataSizeCode,
+                                  uint32_t flexnvmPartitionCode);
+
+/*! @} */
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*!
+ * @brief Reads the resource with data at locations passed in through parameters.
+ *
+ * This function reads the flash memory with the desired location for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param dst A pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be read. Must be word-aligned.
+ * @param option The resource option which indicates which area should be read back.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the data have been read successfully from
+ *         program flash IFR, data flash IFR space, and the Version ID field
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_ReadResource(
+    flexnvm_config_t *config, uint32_t start, uint8_t *dst, uint32_t lengthInBytes, ftfx_read_resource_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+/*! @} */
+
+/*!
+ * @name Verification
+ * @{
+ */
+
+/*!
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ * to the specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the specified data flash region is in erased state.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_DflashVerifyErase(flexnvm_config_t *config,
+                                   uint32_t start,
+                                   uint32_t lengthInBytes,
+                                   ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies erasure of the entire flash at a specified margin level.
+ *
+ * This function checks whether the flash is erased to the
+ * specified read margin level.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the entire flexnvm region is in erased state.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_VerifyEraseAll(flexnvm_config_t *config, ftfx_margin_value_t margin);
+
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programmed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param expectedData A pointer to the expected data that is to be
+ *        verified against.
+ * @param margin Read margin choice.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
+ *        case, zeros are returned upon failure.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desired data hve been programed successfully into
+ *         specified data flash region.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_DflashVerifyProgram(flexnvm_config_t *config,
+                                     uint32_t start,
+                                     uint32_t lengthInBytes,
+                                     const uint8_t *expectedData,
+                                     ftfx_margin_value_t margin,
+                                     uint32_t *failedAddress,
+                                     uint32_t *failedData);
+
+/*! @} */
+
+/*!
+ * @name Security
+ * @{
+ */
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function.
+ *
+ * This function retrieves the current flash security status, including the
+ * security enabling state and the backdoor key enabling state.
+ *
+ * @param config A pointer to storage for the driver runtime state.
+ * @param state A pointer to the value returned for the current security status code:
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully;
+ *         the security state of flexnvm was stored to state.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ */
+status_t FLEXNVM_GetSecurityState(flexnvm_config_t *config, ftfx_security_state_t *state);
+
+/*!
+ * @brief Allows users to bypass security with a backdoor key.
+ *
+ * If the MCU is in secured state, this function unsecures the MCU by
+ * comparing the provided backdoor key with ones in the flash configuration
+ * field.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param backdoorKey A pointer to the user buffer containing the backdoor key.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoorKey);
+
+/*! @} */
+
+/*!
+ * @name FlexRAM
+ * @{
+ */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*!
+ * @brief Sets the FlexRAM function command.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option The option used to set the work mode of FlexRAM.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully;
+ *         the FlexRAM has been successfully configured as RAM or EEPROM
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution.
+ */
+status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_opt_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*! @} */
+
+/*!
+ * @brief Programs the EEPROM with data at locations passed in through parameters.
+ *
+ * This function programs the emulated EEPROM with the desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the desires data have been successfully programed
+ *         into specified eeprom region.
+ *
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FTFx_SetFlexramAsEepromError Failed to set flexram as eeprom.
+ * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FTFx_RecoverFlexramAsRamError Failed to recover the FlexRAM as RAM.
+ */
+status_t FLEXNVM_EepromWrite(flexnvm_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @name Flash Protection Utilities
+ * @{
+ */
+
+/*!
+ * @brief Sets the DFlash protection to the intended protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the DFlash protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total DFlash. The least significant bit corresponds to the lowest
+ * address area of the DFlash. The most significant bit corresponds to the highest address area of  the DFlash. There
+ * are
+ * two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully; the specified DFlash region is protected.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FLEXNVM_DflashSetProtection(flexnvm_config_t *config, uint8_t protectStatus);
+
+/*!
+ * @brief Gets the DFlash protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total DFlash. The least significant bit corresponds to the lowest address area of the DFlash. The most
+ * significant bit corresponds to the highest address area of the DFlash, and so on. There are two possible cases as
+ * below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported.
+ */
+status_t FLEXNVM_DflashGetProtection(flexnvm_config_t *config, uint8_t *protectStatus);
+
+/*!
+ * @brief Sets the EEPROM protection to the intended protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the EEPROM protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total EEPROM. The least significant bit corresponds to the lowest
+ * address area of the EEPROM. The most significant bit corresponds to the highest address area of EEPROM, and so on.
+ * There are two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported.
+ * @retval #kStatus_FTFx_CommandFailure Run-time error during command execution.
+ */
+status_t FLEXNVM_EepromSetProtection(flexnvm_config_t *config, uint8_t protectStatus);
+
+/*!
+ * @brief Gets the EEPROM protection status.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total EEPROM. The least significant bit corresponds to the lowest address area of the EEPROM. The most
+ * significant bit corresponds to the highest address area of the EEPROM. There are two possible cases as below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_CommandNotSupported Flash API is not supported.
+ */
+status_t FLEXNVM_EepromGetProtection(flexnvm_config_t *config, uint8_t *protectStatus);
+
+/*! @} */
+
+/*!
+ * @name Properties
+ * @{
+ */
+
+/*!
+ * @brief Returns the desired flexnvm property.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flexnvm_property_tag_t
+ * @param value A pointer to the value returned for the desired flexnvm property.
+ *
+ * @retval #kStatus_FTFx_Success API was executed successfully.
+ * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FTFx_UnknownProperty An unknown property tag.
+ */
+status_t FLEXNVM_GetProperty(flexnvm_config_t *config, flexnvm_property_tag_t whichProperty, uint32_t *value);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FTFX_FLEXNVM_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_utilities.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_utilities.h
new file mode 100644
index 0000000000..a3f9a84f64
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_ftfx_utilities.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_FTFX_UTILITIES_H
+#define FSL_FTFX_UTILITIES_H
+
+/*!
+ * @addtogroup ftfx_utilities
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Constructs the version number for drivers. */
+#if !defined(MAKE_VERSION)
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+#endif
+
+/*! @brief Constructs a status code value from a group and a code number. */
+#if !defined(MAKE_STATUS)
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+#endif
+
+/*! @brief Constructs the four character code for the Flash driver API key. */
+#if !defined(FOUR_CHAR_CODE)
+#define FOUR_CHAR_CODE(a, b, c, d) \
+    (((uint32_t)(d) << 24u) | ((uint32_t)(c) << 16u) | ((uint32_t)(b) << 8u) | ((uint32_t)(a)))
+#endif
+
+//! @name Alignment macros
+//! @{
+/*! @brief Alignment(down) utility. */
+#if !defined(ALIGN_DOWN)
+#define ALIGN_DOWN(x, a) (((uint32_t)(x)) & ~((uint32_t)(a)-1u))
+#endif
+
+/*! @brief Alignment(up) utility. */
+#if !defined(ALIGN_UP)
+#define ALIGN_UP(x, a) ALIGN_DOWN((uint32_t)(x) + (uint32_t)(a)-1u, a)
+#endif
+//! @}
+
+/*! @brief bytes2word utility. */
+#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24U)
+#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16U)
+#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8U)
+#define B1P1(b) ((uint32_t)(b)&0xFFU)
+#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16U)
+#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8U)
+#define B2P1(b) ((uint32_t)(b)&0xFFFFU)
+#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8U)
+#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU)
+
+#define BYTE2WORD_1_3(x, y)           (B1P4(x) | B3P1(y))
+#define BYTE2WORD_2_2(x, y)           (B2P3(x) | B2P1(y))
+#define BYTE2WORD_3_1(x, y)           (B3P2(x) | B1P1(y))
+#define BYTE2WORD_1_1_2(x, y, z)      (B1P4(x) | B1P3(y) | B2P1(z))
+#define BYTE2WORD_1_2_1(x, y, z)      (B1P4(x) | B2P2(y) | B1P1(z))
+#define BYTE2WORD_2_1_1(x, y, z)      (B2P3(x) | B1P2(y) | B1P1(z))
+#define BYTE2WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w))
+
+/*! @}*/
+
+#endif /* FSL_FTFX_UTILITIES_H */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.c
new file mode 100644
index 0000000000..3e32730d1c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpio"
+#endif
+
+#if defined(GPIO_RSTS)
+#define GPIO_RESETS_ARRAY GPIO_RSTS
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#else
+#if defined(GPIO_RESETS_ARRAY)
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(GPIO_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * @brief Gets the GPIO instance according to the GPIO base
+ *
+ * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval GPIO instance
+ */
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gpioBases));
+
+    return instance;
+}
+#endif
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param pin    GPIO port pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(NULL != config);
+
+#if defined(GPIO_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
+#endif
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
+    }
+    else
+    {
+        GPIO_PinWrite(base, pin, config->outputLogic);
+        base->PDDR |= GPIO_FIT_REG((1UL << pin));
+    }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
+void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
+{
+    info->feature = (uint16_t)base->VERID;
+    info->minor   = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT);
+    info->major   = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Reads the GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = (uint8_t)GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+#else
+/*!
+ * brief Read the GPIO interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * return The current GPIO's interrupt status flag.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)
+{
+    return base->ISFR[0];
+}
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ *
+ * return The current GPIO's interrupt status flag based on the selected interrupt channel.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)
+{
+    assert(channel < 2U);
+    return base->ISFR[channel];
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
+/*!
+ * brief Read individual pin's interrupt status flag.
+ *
+ * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
+ * param pin GPIO specific pin number.
+ * return The current selected pin's interrupt status flag.
+ */
+uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
+{
+    return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT);
+}
+#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance       = (uint8_t)GPIO_GetInstance(base);
+    portBase       = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+#else
+/*!
+ * brief Clears GPIO pin interrupt status flags.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ */
+void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    base->ISFR[0] = GPIO_FIT_REG(mask);
+}
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param mask GPIO pin number macro
+ * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ */
+void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)
+{
+    assert(channel < 2U);
+    base->ISFR[channel] = GPIO_FIT_REG(mask);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
+/*!
+ * brief Clear GPIO individual pin's interrupt status flag.
+ *
+ * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
+ * param pin GPIO specific pin number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)
+{
+    base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U));
+}
+#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
+ * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
+ * endian data convention.
+ *
+ * param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * param attribute GPIO checker attribute
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
+    base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT);
+#else
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */
+}
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * @brief Gets the FGPIO instance according to the GPIO base
+ *
+ * @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval FGPIO instance
+ */
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
+
+    return instance;
+}
+#endif
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+/*!
+ * brief Initializes the FGPIO peripheral.
+ *
+ * This function ungates the FGPIO clock.
+ *
+ * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ */
+void FGPIO_PortInit(FGPIO_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate FGPIO periphral clock */
+    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+/*!
+ * brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param pin    FGPIO port pin number
+ * param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(NULL != config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1UL << pin);
+    }
+    else
+    {
+        FGPIO_PinWrite(base, pin, config->outputLogic);
+        base->PDDR |= (1UL << pin);
+    }
+}
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * brief Reads the FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = (uint8_t)FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+/*!
+ * brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param mask FGPIO pin number macro
+ */
+void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = (uint8_t)FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase       = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+#endif
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * param attribute FGPIO checker attribute
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.h
new file mode 100644
index 0000000000..a91fa403ef
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_gpio.h
@@ -0,0 +1,799 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_GPIO_H_
+#define FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
+/*! @} */
+
+#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
+#define GPIO_FIT_REG(value) \
+    ((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */
+#else
+#define GPIO_FIT_REG(value) ((uint32_t)(value))
+#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/
+
+/*! @brief GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*! @brief GPIO checker attribute */
+typedef enum _gpio_checker_attribute
+{
+    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
+        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
+        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
+        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
+        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
+        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
+        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
+        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
+        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
+    kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
+} gpio_checker_attribute_t;
+#endif
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ * Note that in some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig().
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations; ignore if configured as an input pin */
+    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
+     !(defined(FSL_FEATURE_SOC_PORT_COUNT))
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _gpio_interrupt_config
+{
+    kGPIO_InterruptStatusFlagDisabled   = 0x0U,  /*!< Interrupt status flag is disabled. */
+    kGPIO_DMARisingEdge                 = 0x1U,  /*!< ISF flag and DMA request on rising edge. */
+    kGPIO_DMAFallingEdge                = 0x2U,  /*!< ISF flag and DMA request on falling edge. */
+    kGPIO_DMAEitherEdge                 = 0x3U,  /*!< ISF flag and DMA request on either edge. */
+    kGPIO_FlagRisingEdge                = 0x05U, /*!< Flag sets on rising edge. */
+    kGPIO_FlagFallingEdge               = 0x06U, /*!< Flag sets on falling edge. */
+    kGPIO_FlagEitherEdge                = 0x07U, /*!< Flag sets on either edge. */
+    kGPIO_InterruptLogicZero            = 0x8U,  /*!< Interrupt when logic zero. */
+    kGPIO_InterruptRisingEdge           = 0x9U,  /*!< Interrupt on rising edge. */
+    kGPIO_InterruptFallingEdge          = 0xAU,  /*!< Interrupt on falling edge. */
+    kGPIO_InterruptEitherEdge           = 0xBU,  /*!< Interrupt on either edge. */
+    kGPIO_InterruptLogicOne             = 0xCU,  /*!< Interrupt when logic one. */
+    kGPIO_ActiveHighTriggerOutputEnable = 0xDU,  /*!< Enable active high-trigger output. */
+    kGPIO_ActiveLowTriggerOutputEnable  = 0xEU,  /*!< Enable active low-trigger output. */
+} gpio_interrupt_config_t;
+#endif
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*! @brief Configures the selection of interrupt/DMA request/trigger output. */
+typedef enum _gpio_interrupt_selection
+{
+    kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
+    kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
+} gpio_interrupt_selection_t;
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
+
+#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
+/*! @brief GPIO version information. */
+typedef struct _gpio_version_info
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor Version Number. */
+    uint8_t major;    /*!< Major Version Number. */
+} gpio_version_info_t;
+#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
+
+#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
+/*! @brief GPIO pin and interrupt control. */
+typedef enum
+{
+    kGPIO_PinControlNonSecure          = 0x01U, /*!< Pin Control Non-Secure. */
+    kGPIO_InterruptControlNonSecure    = 0x02U, /*!< Interrupt Control Non-Secure. */
+    kGPIO_PinControlNonPrivilege       = 0x04U, /*!< Pin Control Non-Privilege. */
+    kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */
+} gpio_pin_interrupt_control_t;
+#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*! @name GPIO Configuration */
+/*! @{ */
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin    GPIO port pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
+/*!
+ * @brief Get GPIO version information.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param info GPIO version information
+ */
+void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info);
+#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
+
+#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
+/*!
+ * @brief lock or unlock secure privilege.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask pin or interrupt macro
+ */
+static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)
+{
+    base->LOCK |= GPIO_FIT_REG(mask);
+}
+
+/*!
+ * @brief Enable Pin Control Non-Secure.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
+{
+    base->PCNS |= GPIO_FIT_REG(mask);
+}
+
+/*!
+ * @brief Disable Pin Control Non-Secure.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
+{
+    base->PCNS &= GPIO_FIT_REG(~mask);
+}
+
+/*!
+ * @brief Enable Pin Control Non-Privilege.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
+{
+    base->PCNP |= GPIO_FIT_REG(mask);
+}
+
+/*!
+ * @brief Disable Pin Control Non-Privilege.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
+{
+    base->PCNP &= GPIO_FIT_REG(~mask);
+}
+
+/*!
+ * @brief Enable Interrupt Control Non-Secure.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
+{
+    base->ICNS |= GPIO_FIT_REG(mask);
+}
+
+/*!
+ * @brief Disable Interrupt Control Non-Secure.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
+{
+    base->ICNS &= GPIO_FIT_REG(~mask);
+}
+
+/*!
+ * @brief Enable Interrupt Control Non-Privilege.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
+{
+    base->ICNP |= GPIO_FIT_REG(mask);
+}
+
+/*!
+ * @brief Disable Interrupt Control Non-Privilege.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
+{
+    base->ICNP &= GPIO_FIT_REG(~mask);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
+
+#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL
+/*!
+ * @brief Enable port input.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)
+{
+    base->PIDR &= GPIO_FIT_REG(~mask);
+}
+
+/*!
+ * @brief Disable port input.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
+{
+    base->PIDR |= GPIO_FIT_REG(mask);
+}
+#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
+
+/*! @} */
+
+/*! @name GPIO Output Operations */
+/*! @{ */
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
+    if (output == 0U)
+    {
+        base->PCOR = GPIO_FIT_REG(1UL << pin);
+    }
+    else
+    {
+        base->PSOR = GPIO_FIT_REG(1UL << pin);
+    }
+#else
+    if (output == 0U)
+    {
+        base->PDOR |= GPIO_FIT_REG(1UL << pin);
+    }
+    else
+    {
+        base->PDOR &= ~GPIO_FIT_REG(1UL << pin);
+    }
+#endif
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
+{
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
+    base->PSOR = GPIO_FIT_REG(mask);
+#else
+    base->PDOR |= GPIO_FIT_REG(mask);
+#endif
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
+{
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
+    base->PCOR = GPIO_FIT_REG(mask);
+#else
+    base->PDOR &= ~GPIO_FIT_REG(mask);
+#endif
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
+{
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
+    base->PTOR = GPIO_FIT_REG(mask);
+#else
+    base->PDOR ^= GPIO_FIT_REG(mask);
+#endif
+}
+
+/*! @} */
+
+/*! @name GPIO Input Operations */
+/*! @{ */
+
+/*!
+ * @brief Reads the current input value of the GPIO port.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
+{
+    return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
+}
+
+/*! @} */
+
+/*! @name GPIO Interrupt */
+/*! @{ */
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+/*!
+ * @brief Reads the GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base);
+
+/*!
+ * @brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask);
+#else
+/*!
+ * @brief Configures the gpio pin interrupt/DMA request.
+ *
+ * @param base    GPIO peripheral base pointer.
+ * @param pin     GPIO pin number.
+ * @param config  GPIO pin interrupt configuration.
+ *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
+ *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
+ */
+static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)
+{
+    assert(base);
+
+    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config));
+}
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection.
+ *
+ * @param base    GPIO peripheral base pointer.
+ * @param pin     GPIO pin number.
+ * @param selection  GPIO pin interrupt output selection.
+ *        - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
+ *        - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.
+ */
+static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)
+{
+    assert(base);
+
+    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection));
+}
+#endif
+/*!
+ * @brief Read the GPIO interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * @return The current GPIO's interrupt status flag.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base);
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
+ *
+ * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ * @return The current GPIO's interrupt status flag based on the selected interrupt channel.
+ *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
+ *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
+ */
+uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel);
+#endif
+/*!
+ * @brief Read individual pin's interrupt status flag.
+ *
+ * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
+ * @param pin GPIO specific pin number.
+ * @return The current selected pin's interrupt status flag.
+ */
+uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin);
+
+/*!
+ * @brief Clears GPIO pin interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask);
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
+/*!
+ * @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
+ */
+void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel);
+#endif
+/*!
+ * @brief Clear GPIO individual pin's interrupt status flag.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
+ * @param pin GPIO specific pin number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin);
+
+/*!
+ * @brief Reads the GPIO DMA request flags.
+ *        The corresponding flag will be cleared automatically at the completion of the requested
+ *        DMA transfer
+ */
+static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base)
+{
+    assert(base);
+    return (base->ISFR[1]);
+}
+
+/*!
+ * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param mask   GPIO pin number macro.
+ * @param config  GPIO pin interrupt configuration.
+ *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
+ *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
+ */
+static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)
+{
+    assert(base);
+
+    if (0UL != (mask & 0xffffUL))
+    {
+        base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
+    }
+    mask = mask >> 16U;
+    if (mask != 0UL)
+    {
+        base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
+    }
+}
+#endif
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
+ * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
+ * endian data convention.
+ *
+ * @param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param attribute GPIO checker attribute
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
+/*! @} */
+/*! @} */
+
+/*!
+ * @addtogroup fgpio_driver
+ * @{
+ */
+
+/*
+ * Introduces the FGPIO feature.
+ *
+ * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
+ * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
+ */
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*! @name FGPIO Configuration */
+/*! @{ */
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+/*!
+ * @brief Initializes the FGPIO peripheral.
+ *
+ * This function ungates the FGPIO clock.
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ */
+void FGPIO_PortInit(FGPIO_Type *base);
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+/*!
+ * @brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration:
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin    FGPIO port pin number
+ * @param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*! @} */
+
+/*! @name FGPIO Output Operations */
+/*! @{ */
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
+ *
+ * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin     FGPIO pin number
+ * @param output  FGPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1UL << pin;
+    }
+    else
+    {
+        base->PSOR = 1UL << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple FGPIO pins.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*! @} */
+
+/*! @name FGPIO Input Operations */
+/*! @{ */
+
+/*!
+ * @brief Reads the current input value of the FGPIO port.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin  FGPIO pin number
+ * @retval FGPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*! @} */
+
+/*! @name FGPIO Interrupt */
+/*! @{ */
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
+
+/*!
+ * @brief Reads the FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base);
+
+/*!
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
+#endif
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param attribute FGPIO checker attribute
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
+
+/*! @} */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* FSL_GPIO_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.c
new file mode 100644
index 0000000000..cbae6fd0e4
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.c
@@ -0,0 +1,2419 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.i2c"
+#endif
+
+/*! @brief i2c transfer state. */
+enum _i2c_transfer_states
+{
+    kIdleState             = 0x0U, /*!< I2C bus idle. */
+    kCheckAddressState     = 0x1U, /*!< 7-bit address check state. */
+    kSendCommandState      = 0x2U, /*!< Send command byte phase. */
+    kSendDataState         = 0x3U, /*!< Send data transfer phase. */
+    kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */
+    kReceiveDataState      = 0x5U, /*!< Receive data transfer phase. */
+};
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
+
+/*! @brief static variable to keep current configured baudrate. */
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+static uint32_t g_baudrate = 100000;
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the
+ * closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop
+ * hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided,
+ * assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT
+ * value, then the related SDA hold time, SCL start and SCL stop hold time is used.
+ *
+ * @param base I2C peripheral base address.
+ * @param sourceClock_Hz I2C functional clock frequency in Hertz.
+ * @param sclStopHoldTime_ns SCL stop hold time in ns.
+ */
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz);
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+/*!
+ * @brief I2C master manually ack byte.
+ *
+ * @param base I2C peripheral base address.
+ */
+static void I2C_MasterAckByte(I2C_Type *base);
+#endif
+
+/*!
+ * @brief Set up master transfer, send slave address and decide the initial
+ * transfer state.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Check and clear status operation.
+ *
+ * @param base I2C peripheral base address.
+ * @param status current i2c hardware status.
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ */
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief Master run transfer state machine to perform a byte of transfer.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ * @param isDone input param to get whether the thing is done, true is done
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ */
+static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone);
+
+/*!
+ * @brief I2C common interrupt handler.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to i2c handles for each instance. */
+static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT];
+
+/*! @brief SCL clock divider used to calculate baudrate. */
+static const uint16_t s_i2cDividerTable[] = {
+    20,  22,  24,  26,   28,   30,   34,   40,   28,   32,   36,   40,   44,   48,   56,   68,
+    48,  56,  64,  72,   80,   88,   104,  128,  80,   96,   112,  128,  144,  160,  192,  240,
+    160, 192, 224, 256,  288,  320,  384,  480,  320,  384,  448,  512,  576,  640,  768,  960,
+    640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
+
+/*! @brief Pointers to i2c IRQ number for each instance. */
+static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to i2c clocks for each instance. */
+static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointer to master IRQ handler for each instance. */
+static i2c_isr_t s_i2cMasterIsr;
+
+/*! @brief Pointer to slave IRQ handler for each instance. */
+static i2c_isr_t s_i2cSlaveIsr;
+
+/*! @brief Pointers to i2c bases for each instance. */
+static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+/*!
+ * brief Get instance number for I2C module.
+ *
+ * param base I2C peripheral base address.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++)
+    {
+        if (s_i2cBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_i2cBases));
+
+    return instance;
+}
+
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz)
+{
+    uint32_t multiplier;
+    uint32_t computedSclHoldTime;
+    uint32_t absError;
+    uint32_t bestError = UINT32_MAX;
+    uint32_t bestMult  = 0u;
+    uint32_t bestIcr   = 0u;
+    uint32_t u32flag   = 1u;
+    uint8_t mult;
+    uint8_t i;
+
+    /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
+     * and ranges from 0-2. It selects the multiplier factor for the divider. */
+    /* SDA hold time = bus period (s) * mul * SDA hold value. */
+    /* SCL start hold time = bus period (s) * mul * SCL start hold value. */
+    /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */
+
+    for (mult = 0u; mult <= 2u; ++mult)
+    {
+        if (bestError == 0u)
+        {
+            break;
+        }
+
+        multiplier = u32flag << mult;
+
+        /* Scan table to find best match. */
+        for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i)
+        {
+            /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */
+            computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000U) / (sourceClock_Hz / 1000U);
+            absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) :
+                                                                  (computedSclHoldTime - sclStopHoldTime_ns);
+
+            if (absError < bestError)
+            {
+                bestMult  = mult;
+                bestIcr   = i;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching because we won't find a better match. */
+                if (absError == 0u)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set frequency register based on best settings. */
+    base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
+}
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+static void I2C_MasterAckByte(I2C_Type *base)
+{
+    /* Clear the TXAK flag. */
+    base->C1 &= ~(uint8_t)I2C_C1_TXAK_MASK;
+
+    /* Delay at least one bit time */
+    SDK_DelayAtLeastUs(1000000 / g_baudrate, SystemCoreClock);
+
+    /* Do dummy read. */
+    (void)base->D;
+}
+#endif
+
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result           = kStatus_Success;
+    i2c_direction_t direction = xfer->direction;
+
+    /* Initialize the handle transfer information. */
+    handle->transfer = *xfer;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Initial transfer state. */
+    if (handle->transfer.subaddressSize > 0u)
+    {
+        if (xfer->direction == kI2C_Read)
+        {
+            direction = kI2C_Write;
+        }
+    }
+
+    handle->state = (uint8_t)kCheckAddressState;
+
+    /* Clear all status before transfer. */
+    I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
+
+    /* Handle no start option. */
+    if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferNoStartFlag))
+    {
+        /* No need to send start flag, directly go to send command or data */
+        if (handle->transfer.subaddressSize > 0u)
+        {
+            handle->state = (uint8_t)kSendCommandState;
+        }
+        else
+        {
+            if (direction == kI2C_Write)
+            {
+                /* Next state, send data. */
+                handle->state = (uint8_t)kSendDataState;
+            }
+            else
+            {
+                /* Only support write with no stop signal. */
+                return kStatus_InvalidArgument;
+            }
+        }
+
+        /* Wait for TCF bit and manually trigger tx interrupt. */
+#if I2C_RETRY_TIMES != 0U
+        uint32_t waitTimes = I2C_RETRY_TIMES;
+        while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
+        {
+        }
+#endif
+        I2C_MasterTransferHandleIRQ(base, handle);
+    }
+    /* If repeated start is requested, send repeated start. */
+    else if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferRepeatedStartFlag))
+    {
+        result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
+    }
+    else /* For normal transfer, send start. */
+    {
+        result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
+    }
+
+    return result;
+}
+
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
+{
+    status_t result = kStatus_Success;
+
+    /* Check arbitration lost. */
+    if (0U != (status & (uint32_t)kI2C_ArbitrationLostFlag))
+    {
+        /* Clear arbitration lost flag. */
+        base->S = (uint8_t)kI2C_ArbitrationLostFlag;
+        result  = kStatus_I2C_ArbitrationLost;
+    }
+    /* Check NAK */
+    else if (0U != (status & (uint32_t)kI2C_ReceiveNakFlag))
+    {
+        result = kStatus_I2C_Nak;
+    }
+    else
+    {
+        /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */
+    }
+
+    return result;
+}
+
+static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+    status_t result      = kStatus_Success;
+    uint32_t statusFlags = base->S;
+    *isDone              = false;
+    uint32_t tmpDataSize = handle->transfer.dataSize;
+    bool ignoreNak       = ((handle->state == (uint8_t)kSendDataState) && (tmpDataSize == 0U)) ||
+                     ((handle->state == (uint8_t)kReceiveDataState) && (tmpDataSize == 1U));
+    uint8_t tmpdata;
+
+    /* Check & clear error flags. */
+    result = I2C_CheckAndClearError(base, statusFlags);
+
+    /* Ignore Nak when it's appeared for last byte. */
+    if ((result == kStatus_I2C_Nak) && ignoreNak)
+    {
+        result = kStatus_Success;
+    }
+
+    /* Handle Check address state to check the slave address is Acked in slave
+       probe application. */
+    if (handle->state == (uint8_t)kCheckAddressState)
+    {
+        if (0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag))
+        {
+            result = kStatus_I2C_Addr_Nak;
+        }
+        else
+        {
+            if (handle->transfer.subaddressSize > 0U)
+            {
+                handle->state = (uint8_t)kSendCommandState;
+            }
+            else
+            {
+                if (handle->transfer.direction == kI2C_Write)
+                {
+                    /* Next state, send data. */
+                    handle->state = (uint8_t)kSendDataState;
+                }
+                else
+                {
+                    /* Next state, receive data begin. */
+                    handle->state = (uint8_t)kReceiveDataBeginState;
+                }
+            }
+        }
+    }
+
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* Run state machine. */
+    switch (handle->state)
+    {
+        /* Send I2C command. */
+        case (uint8_t)kSendCommandState:
+            if (0U != (handle->transfer.subaddressSize))
+            {
+                handle->transfer.subaddressSize--;
+                base->D = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize));
+            }
+            else
+            {
+                if (handle->transfer.direction == kI2C_Write)
+                {
+                    /* Send first byte of data. */
+                    if (handle->transfer.dataSize > 0U)
+                    {
+                        /* Next state, send data. */
+                        handle->state = (uint8_t)kSendDataState;
+                        base->D       = *handle->transfer.data;
+                        handle->transfer.data++;
+                        handle->transfer.dataSize--;
+                    }
+                    else
+                    {
+                        *isDone = true;
+                    }
+                }
+                else
+                {
+                    /* Send repeated start and slave address. */
+                    result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
+
+                    /* Next state, receive data begin. */
+                    handle->state = (uint8_t)kReceiveDataBeginState;
+                }
+            }
+            break;
+
+        /* Send I2C data. */
+        case (uint8_t)kSendDataState:
+            /* Send one byte of data. */
+            if (handle->transfer.dataSize > 0U)
+            {
+                base->D = *handle->transfer.data;
+                handle->transfer.data++;
+                handle->transfer.dataSize--;
+            }
+            else
+            {
+                *isDone = true;
+            }
+            break;
+
+        /* Start I2C data receive. */
+        case (uint8_t)kReceiveDataBeginState:
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+            base->SMB |= I2C_SMB_FACK_MASK;
+#endif
+
+            base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release the bus. */
+            (void)base->D;
+
+            if (handle->transfer.dataSize == 1U)
+            {
+                /* Issue NACK on read. */
+                base->C1 |= I2C_C1_TXAK_MASK;
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+                base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
+#endif
+            }
+
+            /* Next state, receive data. */
+            handle->state = (uint8_t)kReceiveDataState;
+            break;
+
+        /* Receive I2C data. */
+        case (uint8_t)kReceiveDataState:
+            /* Receive one byte of data. */
+            if (0U != (handle->transfer.dataSize--))
+            {
+                if (handle->transfer.dataSize == 0U)
+                {
+                    *isDone = true;
+
+                    /* Send stop if kI2C_TransferNoStop is not asserted. */
+                    if (0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag))
+                    {
+                        result = I2C_MasterStop(base);
+                    }
+                    else
+                    {
+                        base->C1 |= I2C_C1_TX_MASK;
+                    }
+                }
+
+                /* Read the data byte into the transfer buffer. */
+                tmpdata                = base->D;
+                *handle->transfer.data = tmpdata;
+                handle->transfer.data++;
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+                if (handle->transfer.dataSize != 0U)
+                {
+                    I2C_MasterAckByte(base);
+                }
+#endif
+                if (handle->transfer.dataSize == 1U)
+                {
+                    /* Issue NACK on read. */
+                    base->C1 |= I2C_C1_TXAK_MASK;
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+                    base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
+#endif
+                }
+            }
+
+            break;
+
+        default:
+            /* Add this to fix MISRA C2012 rule 16.4 issue: Empty default. */
+            assert(false);
+            break;
+    }
+
+    return result;
+}
+
+static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)
+{
+    uint8_t tmpS  = base->S;
+    uint8_t tmpC1 = base->C1;
+
+    /* Check if master interrupt. */
+    if ((0U != (tmpC1 & I2C_C1_MST_MASK)) || (0U != (tmpS & (uint8_t)kI2C_ArbitrationLostFlag)))
+    {
+        s_i2cMasterIsr(base, handle);
+    }
+    else
+    {
+        s_i2cSlaveIsr(base, handle);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+/*!
+ * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and configure the I2C with master configuration.
+ *
+ * note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can be custom filled
+ * or it can be set with default values by using the I2C_MasterGetDefaultConfig().
+ * After calling this API, the master is ready to transfer.
+ * This is an example.
+ * code
+ * i2c_master_config_t config = {
+ * .enableMaster = true,
+ * .enableStopHold = false,
+ * .highDrive = false,
+ * .baudRate_Bps = 100000,
+ * .glitchFilterWidth = 0
+ * };
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * endcode
+ *
+ * param base I2C base pointer
+ * param masterConfig A pointer to the master configuration structure
+ * param srcClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert(NULL != masterConfig);
+    assert(0U != srcClock_Hz);
+
+    /* Temporary register for filter read. */
+    uint8_t fltReg;
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    uint8_t s2Reg;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable I2C clock. */
+    CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F  = 0;
+    base->C1 = 0;
+    base->S  = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
+
+    /* Disable I2C prior to configuring it. */
+    base->C1 &= ~(uint8_t)(I2C_C1_IICEN_MASK);
+
+    /* Clear all flags. */
+    I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
+
+    /* Configure baud rate. */
+    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
+
+    /* Read out the FLT register. */
+    fltReg = base->FLT;
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    /* Configure the stop / hold enable. */
+    fltReg &= ~(uint8_t)(I2C_FLT_SHEN_MASK);
+    fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold);
+#endif
+
+    /* Configure the glitch filter value. */
+    fltReg &= ~(uint8_t)(I2C_FLT_FLT_MASK);
+    fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth);
+
+    /* Write the register value back to the filter register. */
+    base->FLT = fltReg;
+
+    /* Enable the I2C peripheral based on the configuration. */
+    base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
+
+    /* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    s2Reg    = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK));
+    base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
+#endif
+}
+
+/*!
+ * brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
+ * The I2C master module can't work unless the I2C_MasterInit is called.
+ * param base I2C base pointer
+ */
+void I2C_MasterDeinit(I2C_Type *base)
+{
+    /* Disable I2C module. */
+    I2C_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable I2C clock. */
+    CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief  Sets the I2C master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
+ * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify
+ * the structure before calling the I2C_MasterConfigure().
+ * This is an example.
+ * code
+ * i2c_master_config_t config;
+ * I2C_MasterGetDefaultConfig(&config);
+ * endcode
+ * param masterConfig A pointer to the master configuration structure.
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+    assert(NULL != masterConfig);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
+    /* Default baud rate at 100kbps. */
+    masterConfig->baudRate_Bps = 100000U;
+
+/* Default stop hold enable is disabled. */
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    masterConfig->enableStopHold = false;
+#endif
+
+    /* Default glitch filter value is no filter. */
+    masterConfig->glitchFilterWidth = 0U;
+
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    masterConfig->enableDoubleBuffering = true;
+#endif
+
+    /* Enable the I2C peripheral. */
+    masterConfig->enableMaster = true;
+}
+
+/*!
+ * brief Enables I2C interrupt requests.
+ *
+ * param base I2C base pointer
+ * param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     arg kI2C_GlobalInterruptEnable
+ *     arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
+{
+#ifdef I2C_HAS_STOP_DETECT
+    uint8_t fltReg;
+#endif
+
+    if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable))
+    {
+        base->C1 |= I2C_C1_IICIE_MASK;
+    }
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable))
+    {
+        fltReg = base->FLT;
+
+        /* Keep STOPF flag. */
+        fltReg &= ~I2C_FLT_STOPF_MASK;
+
+        /* Stop detect enable. */
+        fltReg |= I2C_FLT_STOPIE_MASK;
+        base->FLT = fltReg;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable))
+    {
+        fltReg = base->FLT;
+
+        /* Keep STARTF and STOPF flags. */
+        fltReg &= ~(uint8_t)(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+
+        /* Start and stop detect enable. */
+        fltReg |= I2C_FLT_SSIE_MASK;
+        base->FLT = fltReg;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+}
+
+/*!
+ * brief Disables I2C interrupt requests.
+ *
+ * param base I2C base pointer
+ * param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     arg kI2C_GlobalInterruptEnable
+ *     arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)
+{
+    if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable))
+    {
+        base->C1 &= ~(uint8_t)I2C_C1_IICIE_MASK;
+    }
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable))
+    {
+        base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
+    }
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable))
+    {
+        base->FLT &= ~(uint8_t)(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+}
+
+/*!
+ * brief Sets the I2C master transfer baud rate.
+ *
+ * param base I2C base pointer
+ * param baudRate_Bps the baud rate value in bps
+ * param srcClock_Hz Source clock
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t multiplier;
+    uint32_t computedRate;
+    uint32_t absError;
+    uint32_t bestError = UINT32_MAX;
+    uint32_t bestMult  = 0u;
+    uint32_t bestIcr   = 0u;
+    uint32_t u32flag   = 1u;
+    uint8_t mult;
+    uint8_t i;
+
+    /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
+     * and ranges from 0-2. It selects the multiplier factor for the divider. */
+    for (mult = 0u; mult <= 2u; ++mult)
+    {
+        if (bestError == 0u)
+        {
+            break;
+        }
+
+        multiplier = u32flag << mult;
+
+        /* Scan table to find best match. */
+        for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i)
+        {
+            computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]);
+            absError     = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps);
+
+            if (absError < bestError)
+            {
+                bestMult  = mult;
+                bestIcr   = i;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching because we won't find a better match. */
+                if (absError == 0u)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+    g_baudrate = baudRate_Bps;
+#endif
+    /* Set frequency register based on best settings. */
+    base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
+}
+
+/*!
+ * brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * param base I2C peripheral base pointer
+ * param address 7-bit slave device address.
+ * param direction Master transfer directions(transmit/receive).
+ * retval kStatus_Success Successfully send the start signal.
+ * retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    status_t result      = kStatus_Success;
+    uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
+
+    /* Return an error if the bus is already in use. */
+    if (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag))
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Send the START signal. */
+        base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
+
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+#if I2C_RETRY_TIMES != 0U
+        uint32_t waitTimes = I2C_RETRY_TIMES;
+        while ((0U == (base->S2 & I2C_S2_EMPTY_MASK)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        while (0U == (base->S2 & I2C_S2_EMPTY_MASK))
+        {
+        }
+#endif
+#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
+
+        base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
+    }
+
+    return result;
+}
+
+/*!
+ * brief Sends a REPEATED START on the I2C bus.
+ *
+ * param base I2C peripheral base pointer
+ * param address 7-bit slave device address.
+ * param direction Master transfer directions(transmit/receive).
+ * retval kStatus_Success Successfully send the start signal.
+ * retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    status_t result = kStatus_Success;
+    uint8_t savedMult;
+    uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
+    uint8_t timeDelay    = 6;
+
+    /* Return an error if the bus is already in use, but not by us. */
+    if ((0U == (base->C1 & I2C_C1_MST_MASK)) && (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag)))
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        savedMult = base->F;
+        base->F   = savedMult & (~(uint8_t)I2C_F_MULT_MASK);
+
+        /* We are already in a transfer, so send a repeated start. */
+        base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK;
+
+        /* Restore the multiplier factor. */
+        base->F = savedMult;
+
+        /* Add some delay to wait the Re-Start signal. */
+        while (0U != (timeDelay--))
+        {
+            __NOP();
+        }
+
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+#if I2C_RETRY_TIMES != 0U
+        uint32_t waitTimes = I2C_RETRY_TIMES;
+        while ((0U == (base->S2 & I2C_S2_EMPTY_MASK)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        while (0U == (base->S2 & I2C_S2_EMPTY_MASK))
+        {
+        }
+#endif
+#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
+
+        base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
+    }
+
+    return result;
+}
+
+/*!
+ * brief Sends a STOP signal on the I2C bus.
+ *
+ * retval kStatus_Success Successfully send the stop signal.
+ * retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base)
+{
+    status_t result = kStatus_Success;
+
+    /* Issue the STOP command on the bus. */
+    base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait until bus not busy. */
+    while ((0U != (base->S & (uint8_t)kI2C_BusBusyFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+
+    if (0U == waitTimes)
+    {
+        result = kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait until data transfer complete. */
+    while (0U != (base->S & (uint8_t)kI2C_BusBusyFlag))
+    {
+    }
+#endif
+
+    return result;
+}
+
+/*!
+ * brief Gets the I2C status flags.
+ *
+ * param base I2C base pointer
+ * return status flag, use status flag to AND #_i2c_flags to get the related status.
+ */
+uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
+{
+    uint32_t statusFlags = base->S;
+
+#ifdef I2C_HAS_STOP_DETECT
+    /* Look up the STOPF bit from the filter register. */
+    if (0U != (base->FLT & I2C_FLT_STOPF_MASK))
+    {
+        statusFlags |= (uint32_t)kI2C_StopDetectFlag;
+    }
+#endif
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Look up the STARTF bit from the filter register. */
+    if (0U != (base->FLT & I2C_FLT_STARTF_MASK))
+    {
+        statusFlags |= (uint32_t)kI2C_StartDetectFlag;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    return statusFlags;
+}
+
+/*!
+ * brief Performs a polling send transaction on the I2C bus.
+ *
+ * param base  The I2C peripheral base pointer.
+ * param txBuff The pointer to the data to be transferred.
+ * param txSize The length in bytes of the data to be transferred.
+ * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+ *  to issue a stop and kI2C_TransferNoStop to not send a stop.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
+{
+    status_t result     = kStatus_Success;
+    uint8_t statusFlags = 0;
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait until the data register is ready for transmit. */
+    while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait until the data register is ready for transmit. */
+    while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
+    {
+    }
+#endif
+
+    /* Clear the IICIF flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+
+    /* Setup the I2C peripheral to transmit data. */
+    base->C1 |= I2C_C1_TX_MASK;
+
+    while (0U != (txSize--))
+    {
+        /* Send a byte of data. */
+        base->D = *txBuff++;
+
+#if I2C_RETRY_TIMES != 0U
+        waitTimes = I2C_RETRY_TIMES;
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+        statusFlags = base->S;
+
+        /* Clear the IICIF flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */
+        if (0U != (statusFlags & (uint8_t)kI2C_ArbitrationLostFlag))
+        {
+            base->S = (uint8_t)kI2C_ArbitrationLostFlag;
+            result  = kStatus_I2C_ArbitrationLost;
+        }
+
+        if ((0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag)) && (0U != txSize))
+        {
+            base->S = (uint8_t)kI2C_ReceiveNakFlag;
+            result  = kStatus_I2C_Nak;
+        }
+
+        if (result != kStatus_Success)
+        {
+            /* Breaking out of the send loop. */
+            break;
+        }
+    }
+
+    if (((result == kStatus_Success) && (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))) ||
+        (result == kStatus_I2C_Nak))
+    {
+        /* Clear the IICIF flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Send stop. */
+        result = I2C_MasterStop(base);
+    }
+
+    return result;
+}
+
+/*!
+ * brief Performs a polling receive transaction on the I2C bus.
+ *
+ * note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
+ * Without stopping the bus prior for the final read, the bus issues another read, resulting
+ * in garbage data being read into the data register.
+ *
+ * param base I2C peripheral base pointer.
+ * param rxBuff The pointer to the data to store the received data.
+ * param rxSize The length in bytes of the data to be received.
+ * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+ *  to issue a stop and kI2C_TransferNoStop to not send a stop.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
+{
+    status_t result = kStatus_Success;
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait until the data register is ready for transmit. */
+    while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait until the data register is ready for transmit. */
+    while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
+    {
+    }
+#endif
+
+    /* Clear the IICIF flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+    base->SMB |= I2C_SMB_FACK_MASK;
+#endif
+
+    /* Setup the I2C peripheral to receive data. */
+    base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Do dummy read. */
+    (void)base->D;
+
+    if (rxSize == 1U)
+    {
+        /* Issue NACK on read. */
+        base->C1 |= I2C_C1_TXAK_MASK;
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+        base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
+#endif
+    }
+
+    while (0U != (rxSize--))
+    {
+#if I2C_RETRY_TIMES != 0U
+        waitTimes = I2C_RETRY_TIMES;
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+
+        if (rxSize == 0U)
+        {
+            if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))
+            {
+                /* Issue STOP command before reading last byte. */
+                result = I2C_MasterStop(base);
+            }
+            else
+            {
+                /* Change direction to Tx to avoid extra clocks. */
+                base->C1 |= I2C_C1_TX_MASK;
+            }
+        }
+
+        /* Clear the IICIF flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Read from the data register. */
+        *rxBuff++ = base->D;
+
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+        if (rxSize != 0U)
+        {
+            I2C_MasterAckByte(base);
+        }
+#endif
+
+        if (rxSize == 1U)
+        {
+            base->C1 |= I2C_C1_TXAK_MASK;
+#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
+            /* Issue NACK on read. */
+            base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
+#endif
+        }
+    }
+
+    return result;
+}
+
+/*!
+ * brief Performs a master polling transfer on the I2C bus.
+ *
+ * note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * param base I2C peripheral base address.
+ * param xfer Pointer to the transfer structure.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_Busy Previous transmission still not finished.
+ * retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
+{
+    assert(NULL != xfer);
+
+    i2c_direction_t direction = xfer->direction;
+    status_t result           = kStatus_Success;
+
+    /* Clear all status before transfer. */
+    I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait until the data register is ready for transmit. */
+    while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait until the data register is ready for transmit. */
+    while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
+    {
+    }
+#endif
+
+    /* Change to send write address when it's a read operation with command. */
+    if ((xfer->subaddressSize > 0U) && (xfer->direction == kI2C_Read))
+    {
+        direction = kI2C_Write;
+    }
+
+    /* Handle no start option, only support write with no start signal. */
+    if (0U != (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag))
+    {
+        if (direction == kI2C_Read)
+        {
+            return kStatus_InvalidArgument;
+        }
+    }
+    /* If repeated start is requested, send repeated start. */
+    else if (0U != (xfer->flags & (uint32_t)kI2C_TransferRepeatedStartFlag))
+    {
+        result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction);
+    }
+    else /* For normal transfer, send start. */
+    {
+        result = I2C_MasterStart(base, xfer->slaveAddress, direction);
+    }
+
+    if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag))
+    {
+        /* Return if error. */
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+
+#if I2C_RETRY_TIMES != 0U
+        waitTimes = I2C_RETRY_TIMES;
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+        /* Check if there's transfer error. */
+        result = I2C_CheckAndClearError(base, base->S);
+
+        /* Return if error. */
+        if (kStatus_Success != result)
+        {
+            if (result == kStatus_I2C_Nak)
+            {
+                result = kStatus_I2C_Addr_Nak;
+
+                (void)I2C_MasterStop(base);
+            }
+
+            return result;
+        }
+    }
+
+    /* Send subaddress. */
+    if (0U != (xfer->subaddressSize))
+    {
+        do
+        {
+            /* Clear interrupt pending flag. */
+            base->S = (uint8_t)kI2C_IntPendingFlag;
+
+            xfer->subaddressSize--;
+            base->D = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize));
+
+#if I2C_RETRY_TIMES != 0U
+            waitTimes = I2C_RETRY_TIMES;
+            /* Wait until data transfer complete. */
+            while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+            {
+                waitTimes--;
+            }
+            if (0U == waitTimes)
+            {
+                return kStatus_I2C_Timeout;
+            }
+#else
+            /* Wait until data transfer complete. */
+            while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+            {
+            }
+#endif
+
+            /* Check if there's transfer error. */
+            result = I2C_CheckAndClearError(base, base->S);
+
+            if (0 != result)
+            {
+                if (result == kStatus_I2C_Nak)
+                {
+                    (void)I2C_MasterStop(base);
+                }
+
+                return result;
+            }
+
+        } while (xfer->subaddressSize > 0u);
+
+        if (xfer->direction == kI2C_Read)
+        {
+            /* Clear pending flag. */
+            base->S = (uint8_t)kI2C_IntPendingFlag;
+
+            /* Send repeated start and slave address. */
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
+
+            /* Return if error. */
+            if (kStatus_Success != result)
+            {
+                return result;
+            }
+
+#if I2C_RETRY_TIMES != 0U
+            waitTimes = I2C_RETRY_TIMES;
+            /* Wait until data transfer complete. */
+            while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+            {
+                waitTimes--;
+            }
+            if (0U == waitTimes)
+            {
+                return kStatus_I2C_Timeout;
+            }
+#else
+            /* Wait until data transfer complete. */
+            while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+            {
+            }
+#endif
+
+            /* Check if there's transfer error. */
+            result = I2C_CheckAndClearError(base, base->S);
+
+            if (kStatus_Success != result)
+            {
+                if (result == kStatus_I2C_Nak)
+                {
+                    result = kStatus_I2C_Addr_Nak;
+
+                    (void)I2C_MasterStop(base);
+                }
+
+                return result;
+            }
+        }
+    }
+
+    /* Transmit data. */
+    if (xfer->direction == kI2C_Write)
+    {
+        if (xfer->dataSize > 0U)
+        {
+            uint8_t *tmpData   = xfer->data;
+            size_t tmpDataSize = xfer->dataSize;
+            uint32_t tmpFlags  = xfer->flags;
+            /* Send Data. */
+            result = I2C_MasterWriteBlocking(base, tmpData, tmpDataSize, tmpFlags);
+        }
+        else if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStopFlag))
+        {
+            /* Send stop. */
+            result = I2C_MasterStop(base);
+        }
+        else
+        {
+            /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */
+        }
+    }
+
+    /* Receive Data. */
+    if ((xfer->dataSize > 0u) && (xfer->direction == kI2C_Read))
+    {
+        uint8_t *tmpData   = xfer->data;
+        size_t tmpDataSize = xfer->dataSize;
+        uint32_t tmpFlags  = xfer->flags;
+
+        result = I2C_MasterReadBlocking(base, tmpData, tmpDataSize, tmpFlags);
+    }
+
+    return result;
+}
+
+/*!
+ * brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure to store the transfer state.
+ * param callback pointer to user callback function.
+ * param userData user parameter passed to the callback function.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData)
+{
+    assert(NULL != handle);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_i2cHandle[instance] = handle;
+
+    /* Save master interrupt handler. */
+    s_i2cMasterIsr = I2C_MasterTransferHandleIRQ;
+
+    /* Enable NVIC interrupt. */
+    (void)EnableIRQ(s_i2cIrqs[instance]);
+}
+
+/*!
+ * brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * note Calling the API returns immediately after transfer initiates. The user needs
+ * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
+ * is finished.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * param xfer pointer to i2c_master_transfer_t structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_I2C_Busy Previous transmission still not finished.
+ * retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    assert(NULL != handle);
+    assert(NULL != xfer);
+
+    status_t result = kStatus_Success;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (handle->state != (uint8_t)kIdleState)
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Start up the master transfer state machine. */
+        result = I2C_InitTransferStateMachine(base, handle, xfer);
+
+        if (result == kStatus_Success)
+        {
+            /* Enable the I2C interrupts. */
+            I2C_EnableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
+        }
+    }
+
+    return result;
+}
+
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ * retval kStatus_I2C_Timeout Timeout during polling flag.
+ * retval kStatus_Success Successfully abort the transfer.
+ */
+status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    assert(NULL != handle);
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    /* Disable interrupt. */
+    I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
+
+    /* Reset the state to idle. */
+    handle->state = (uint8_t)kIdleState;
+
+    /* If the bus is already in use, but not by us */
+    if (0U == (base->C1 & I2C_C1_MST_MASK))
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Send STOP signal. */
+    if (handle->transfer.direction == kI2C_Read)
+    {
+        base->C1 |= I2C_C1_TXAK_MASK;
+
+#if I2C_RETRY_TIMES != 0U
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+        (void)base->D;
+    }
+    else
+    {
+#if I2C_RETRY_TIMES != 0U
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+        base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    *count = handle->transferSize - handle->transfer.dataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Master interrupt handler.
+ *
+ * param base I2C base pointer.
+ * param i2cHandle pointer to i2c_master_handle_t structure.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+    assert(NULL != i2cHandle);
+
+    i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle;
+    status_t result             = kStatus_Success;
+    bool isDone;
+
+    /* Clear the interrupt flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+
+    /* Check transfer complete flag. */
+    result = I2C_MasterTransferRunStateMachine(base, handle, &isDone);
+
+    if ((true == isDone) || (0 != result))
+    {
+        /* Send stop command if transfer done or received Nak. */
+        if ((0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) ||
+            (result == kStatus_I2C_Addr_Nak))
+        {
+            /* Ensure stop command is a need. */
+            if (0U != (base->C1 & I2C_C1_MST_MASK))
+            {
+                if (I2C_MasterStop(base) != kStatus_Success)
+                {
+                    result = kStatus_I2C_Timeout;
+                }
+            }
+        }
+
+        /* Restore handle to idle state. */
+        handle->state = (uint8_t)kIdleState;
+
+        /* Disable interrupt. */
+        I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
+
+        /* Call the callback function after the function has completed. */
+        if (NULL != (handle->completionCallback))
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and initialize the I2C with the slave configuration.
+ *
+ * note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can partly be set
+ * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user.
+ * This is an example.
+ * code
+ * i2c_slave_config_t config = {
+ * .enableSlave = true,
+ * .enableGeneralCall = false,
+ * .addressingMode = kI2C_Address7bit,
+ * .slaveAddress = 0x1DU,
+ * .enableWakeUp = false,
+ * .enablehighDrive = false,
+ * .enableBaudRateCtl = false,
+ * .sclStopHoldTime_ns = 4000
+ * };
+ * I2C_SlaveInit(I2C0, &config, 12000000U);
+ * endcode
+ *
+ * param base I2C base pointer
+ * param slaveConfig A pointer to the slave configuration structure
+ * param srcClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
+{
+    assert(NULL != slaveConfig);
+
+    uint8_t tmpReg;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F  = 0;
+    base->C1 = 0;
+    base->S  = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
+
+    /* Configure addressing mode. */
+    switch (slaveConfig->addressingMode)
+    {
+        case kI2C_Address7bit:
+            base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U);
+            break;
+
+        case kI2C_RangeMatch:
+            assert(slaveConfig->slaveAddress < slaveConfig->upperAddress);
+            base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U);
+            base->RA = (uint8_t)(((uint32_t)(slaveConfig->upperAddress)) << 1U);
+            base->C2 |= I2C_C2_RMEN_MASK;
+            break;
+
+        default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            assert(false);
+            break;
+    }
+
+    /* Configure low power wake up feature. */
+    tmpReg = base->C1;
+    tmpReg &= ~(uint8_t)I2C_C1_WUEN_MASK;
+    base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
+
+    /* Configure general call & baud rate control. */
+    tmpReg = base->C2;
+    tmpReg &= ~(uint8_t)(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
+    tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
+    base->C2 = tmpReg;
+
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    tmpReg   = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK));
+    base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
+#endif
+
+    /* Set hold time. */
+    I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz);
+}
+
+/*!
+ * brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock.
+ * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.
+ * param base I2C base pointer
+ */
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+    /* Disable I2C module. */
+    I2C_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable I2C clock. */
+    CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief  Sets the I2C slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure().
+ * Modify fields of the structure before calling the I2C_SlaveConfigure().
+ * This is an example.
+ * code
+ * i2c_slave_config_t config;
+ * I2C_SlaveGetDefaultConfig(&config);
+ * endcode
+ * param slaveConfig A pointer to the slave configuration structure.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+    assert(NULL != slaveConfig);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(slaveConfig, 0, sizeof(*slaveConfig));
+
+    /* By default slave is addressed with 7-bit address. */
+    slaveConfig->addressingMode = kI2C_Address7bit;
+
+    /* General call mode is disabled by default. */
+    slaveConfig->enableGeneralCall = false;
+
+    /* Slave address match waking up MCU from low power mode is disabled. */
+    slaveConfig->enableWakeUp = false;
+
+    /* Independent slave mode baud rate at maximum frequency is disabled. */
+    slaveConfig->enableBaudRateCtl = false;
+
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    slaveConfig->enableDoubleBuffering = true;
+#endif
+
+    /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */
+    slaveConfig->sclStopHoldTime_ns = 4000;
+
+    /* Enable the I2C peripheral. */
+    slaveConfig->enableSlave = true;
+}
+
+/*!
+ * brief Performs a polling send transaction on the I2C bus.
+ *
+ * param base  The I2C peripheral base pointer.
+ * param txBuff The pointer to the data to be transferred.
+ * param txSize The length in bytes of the data to be transferred.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    status_t result = kStatus_Success;
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (0U == (base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait until data transfer complete. */
+    while ((0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait for address match flag. */
+    while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag))
+    {
+    }
+#endif
+    /* Read dummy to release bus. */
+    (void)base->D;
+
+    result = I2C_MasterWriteBlocking(base, txBuff, txSize, (uint32_t)kI2C_TransferNoStopFlag);
+
+    /* Switch to receive mode. */
+    base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Read dummy to release bus. */
+    (void)base->D;
+
+    return result;
+}
+
+/*!
+ * brief Performs a polling receive transaction on the I2C bus.
+ *
+ * param base I2C peripheral base pointer.
+ * param rxBuff The pointer to the data to store the received data.
+ * param rxSize The length in bytes of the data to be received.
+ * retval kStatus_Success Successfully complete data receive.
+ * retval kStatus_I2C_Timeout Wait status flag timeout.
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    status_t result = kStatus_Success;
+
+/* Wait until address match. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (0U == (base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+#if I2C_RETRY_TIMES != 0U
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+    /* Wait for address match and int pending flag. */
+    while ((0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+
+    waitTimes = I2C_RETRY_TIMES;
+    while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+    {
+        waitTimes--;
+    }
+    if (0U == waitTimes)
+    {
+        return kStatus_I2C_Timeout;
+    }
+#else
+    /* Wait for address match and int pending flag. */
+    while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag))
+    {
+    }
+    while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+    {
+    }
+#endif
+
+    /* Read dummy to release bus. */
+    (void)base->D;
+
+    /* Clear the IICIF flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+
+    /* Setup the I2C peripheral to receive data. */
+    base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK);
+
+    while (0U != (rxSize--))
+    {
+#if I2C_RETRY_TIMES != 0U
+        waitTimes = I2C_RETRY_TIMES;
+        /* Wait until data transfer complete. */
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
+        {
+            waitTimes--;
+        }
+        if (0U == waitTimes)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        /* Wait until data transfer complete. */
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+        /* Clear the IICIF flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Read from the data register. */
+        *rxBuff++ = base->D;
+    }
+
+    return result;
+}
+
+/*!
+ * brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_slave_handle_t structure to store the transfer state.
+ * param callback pointer to user callback function.
+ * param userData user parameter passed to the callback function.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData)
+{
+    assert(NULL != handle);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_i2cHandle[instance] = handle;
+
+    /* Save slave interrupt handler. */
+    s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ;
+
+    /* Enable NVIC interrupt. */
+    (void)EnableIRQ(s_i2cIrqs[instance]);
+}
+
+/*!
+ * brief Starts accepting slave transfers.
+ *
+ * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * param base The I2C peripheral base address.
+ * param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * retval #kStatus_Success Slave transfers were successfully started.
+ * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
+{
+    assert(NULL != handle);
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (true == handle->isBusy)
+    {
+        return kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Disable LPI2C IRQ sources while we configure stuff. */
+        I2C_DisableInterrupts(base, (uint32_t)kIrqFlags);
+
+        /* Clear transfer in handle. */
+        (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
+
+        /* Record that we're busy. */
+        handle->isBusy = true;
+
+        /* Set up event mask. tx and rx are always enabled. */
+        handle->eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent |
+                            (uint32_t)kI2C_SlaveGenaralcallEvent;
+
+        /* Clear all flags. */
+        I2C_SlaveClearStatusFlags(base, (uint32_t)kClearFlags);
+
+        /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
+        I2C_EnableInterrupts(base, (uint32_t)kIrqFlags);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the slave transfer.
+ *
+ * note This API can be called at any time to stop slave for handling the bus events.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    if (true == handle->isBusy)
+    {
+        /* Disable interrupts. */
+        I2C_DisableInterrupts(base, (uint32_t)kIrqFlags);
+
+        /* Reset transfer info. */
+        (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
+
+        /* Reset the state to idle. */
+        handle->isBusy = false;
+    }
+}
+
+/*!
+ * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_slave_handle_t structure.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (false == handle->isBusy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* For an active transfer, just return the count from the handle. */
+    *count = handle->transfer.transferredCount;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Slave interrupt handler.
+ *
+ * param base I2C base pointer.
+ * param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+    assert(NULL != i2cHandle);
+
+    uint16_t status;
+    bool doTransmit            = false;
+    i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle;
+    i2c_slave_transfer_t *xfer;
+    size_t tmpDataSize = 0;
+
+    status = (uint16_t)I2C_SlaveGetStatusFlags(base);
+    xfer   = &(handle->transfer);
+
+#ifdef I2C_HAS_STOP_DETECT
+    /* Check stop flag. */
+    if (0U != (status & (uint16_t)kI2C_StopDetectFlag))
+    {
+        I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StopDetectFlag);
+
+        /* Clear the interrupt flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Call slave callback if this is the STOP of the transfer. */
+        if (true == handle->isBusy)
+        {
+            xfer->event            = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy         = false;
+
+            if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+        }
+
+        if (0U == (status & (uint16_t)kI2C_AddressMatchFlag))
+        {
+            return;
+        }
+    }
+#endif /* I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    if (0U != (status & (uint16_t)kI2C_StartDetectFlag))
+    {
+        I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StartDetectFlag);
+
+        /* Clear the interrupt flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        xfer->event = kI2C_SlaveStartEvent;
+
+        if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+
+        if (0U == (status & (uint16_t)kI2C_AddressMatchFlag))
+        {
+            return;
+        }
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Clear the interrupt flag. */
+    base->S = (uint8_t)kI2C_IntPendingFlag;
+
+    /* Check NAK */
+    if (0U != (status & (uint16_t)kI2C_ReceiveNakFlag))
+    {
+        /* Set receive mode. */
+        base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+        /* Read dummy. */
+        (void)base->D;
+
+        if (handle->transfer.dataSize != 0u)
+        {
+            xfer->event            = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_I2C_Nak;
+            handle->isBusy         = false;
+
+            if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+        }
+        else
+        {
+#ifndef I2C_HAS_STOP_DETECT
+            xfer->event            = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy         = false;
+
+            if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+        }
+    }
+    /* Check address match. */
+    else if (0U != (status & (uint16_t)kI2C_AddressMatchFlag))
+    {
+        handle->isBusy = true;
+        xfer->event    = kI2C_SlaveAddressMatchEvent;
+
+        /* Slave transmit, master reading from slave. */
+        if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag))
+        {
+            /* Change direction to send data. */
+            base->C1 |= I2C_C1_TX_MASK;
+
+            doTransmit = true;
+        }
+        else
+        {
+            /* Slave receive, master writing to slave. */
+            base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release the bus and check the address master issued. */
+            if (base->D == 0u)
+            {
+                xfer->event = kI2C_SlaveGenaralcallEvent;
+            }
+        }
+
+        if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+    }
+    /* Check transfer complete flag. */
+    else if (0U != (status & (uint16_t)kI2C_TransferCompleteFlag))
+    {
+        /* Slave transmit, master reading from slave. */
+        if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag))
+        {
+            doTransmit = true;
+        }
+        else
+        {
+            tmpDataSize = xfer->dataSize;
+            /* If we're out of data, invoke callback to get more. */
+            if ((NULL == xfer->data) || (0U == tmpDataSize))
+            {
+                xfer->event = kI2C_SlaveReceiveEvent;
+
+                if (NULL != handle->callback)
+                {
+                    handle->callback(base, xfer, handle->userData);
+                }
+
+                /* Clear the transferred count now that we have a new buffer. */
+                xfer->transferredCount = 0;
+            }
+
+            /* Slave receive, master writing to slave. */
+            uint8_t data = base->D;
+
+            if (0U != (handle->transfer.dataSize))
+            {
+                /* Receive data. */
+                *handle->transfer.data++ = data;
+                handle->transfer.dataSize--;
+                xfer->transferredCount++;
+                if (0U == handle->transfer.dataSize)
+                {
+#ifndef I2C_HAS_STOP_DETECT
+                    xfer->event            = kI2C_SlaveCompletionEvent;
+                    xfer->completionStatus = kStatus_Success;
+                    handle->isBusy         = false;
+
+                    /* Proceed receive complete event. */
+                    if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL))
+                    {
+                        handle->callback(base, xfer, handle->userData);
+                    }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Read dummy to release bus. */
+        (void)base->D;
+    }
+
+    /* Send data if there is the need. */
+    if (doTransmit)
+    {
+        tmpDataSize = xfer->dataSize;
+        /* If we're out of data, invoke callback to get more. */
+        if ((NULL == xfer->data) || (0U == tmpDataSize))
+        {
+            xfer->event = kI2C_SlaveTransmitEvent;
+
+            if (NULL != handle->callback)
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+
+            /* Clear the transferred count now that we have a new buffer. */
+            xfer->transferredCount = 0;
+        }
+
+        if (0U != (handle->transfer.dataSize))
+        {
+            /* Send data. */
+            base->D = *handle->transfer.data++;
+            handle->transfer.dataSize--;
+            xfer->transferredCount++;
+        }
+        else
+        {
+            /* Switch to receive mode. */
+            base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release bus. */
+            (void)base->D;
+
+#ifndef I2C_HAS_STOP_DETECT
+            xfer->event            = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy         = false;
+
+            /* Proceed txdone event. */
+            if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+        }
+    }
+}
+
+#if defined(FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1
+void I2C0_I2C1_DriverIRQHandler(void);
+void I2C0_I2C1_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 0U; instance < 2U; instance++)
+    {
+        if (s_i2cHandle[instance] != NULL)
+        {
+            I2C_TransferCommonIRQHandler(s_i2cBases[instance], s_i2cHandle[instance]);
+        }
+    }
+}
+#else
+#if defined(I2C0)
+void I2C0_DriverIRQHandler(void);
+void I2C0_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
+}
+#endif
+
+#if defined(I2C1)
+void I2C1_DriverIRQHandler(void);
+void I2C1_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
+}
+#endif
+#endif
+
+#if defined(I2C2)
+void I2C2_DriverIRQHandler(void);
+void I2C2_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
+}
+#endif
+
+#if defined(I2C3)
+void I2C3_DriverIRQHandler(void);
+void I2C3_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.h
new file mode 100644
index 0000000000..cf4b231bf2
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c.h
@@ -0,0 +1,807 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_I2C_H_
+#define FSL_I2C_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup i2c_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief I2C driver version. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 9))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef I2C_RETRY_TIMES
+#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief Mater Fast ack control, control if master needs to manually write ack, this is used to
+low the speed of transfer for SoCs with feature FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
+#ifndef I2C_MASTER_FACK_CONTROL
+#define I2C_MASTER_FACK_CONTROL 0U /* Default defines to zero means master will send ack automatically. */
+#endif
+
+#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \
+     defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT)
+#define I2C_HAS_STOP_DETECT
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+/*! @brief  I2C status return codes. */
+enum
+{
+    kStatus_I2C_Busy            = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */
+    kStatus_I2C_Idle            = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */
+    kStatus_I2C_Nak             = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */
+    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */
+    kStatus_I2C_Timeout         = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Timeout polling status flags. */
+    kStatus_I2C_Addr_Nak        = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */
+};
+
+/*!
+ * @brief I2C peripheral flags
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask.
+ *
+ */
+enum _i2c_flags
+{
+    kI2C_ReceiveNakFlag        = I2C_S_RXAK_MASK,  /*!< I2C receive NAK flag. */
+    kI2C_IntPendingFlag        = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. This flag can be cleared. */
+    kI2C_TransferDirectionFlag = I2C_S_SRW_MASK,   /*!< I2C transfer direction flag. */
+    kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK,   /*!< I2C range address match flag. */
+    kI2C_ArbitrationLostFlag   = I2C_S_ARBL_MASK,  /*!< I2C arbitration lost flag. This flag can be cleared. */
+    kI2C_BusBusyFlag           = I2C_S_BUSY_MASK,  /*!< I2C bus busy flag. */
+    kI2C_AddressMatchFlag      = I2C_S_IAAS_MASK,  /*!< I2C address match flag. */
+    kI2C_TransferCompleteFlag  = I2C_S_TCF_MASK,   /*!< I2C transfer complete flag. */
+#ifdef I2C_HAS_STOP_DETECT
+    kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. This flag can be cleared. */
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. This flag can be cleared. */
+#endif                                               /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+};
+
+/*! @brief I2C feature interrupt source. */
+enum _i2c_interrupt_enable
+{
+    kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */
+#endif                                                    /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */
+#endif                                                       /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+};
+
+/*! @brief The direction of master and slave transfers. */
+typedef enum _i2c_direction
+{
+    kI2C_Write = 0x0U, /*!< Master transmits to the slave. */
+    kI2C_Read  = 0x1U, /*!< Master receives from the slave. */
+} i2c_direction_t;
+
+/*! @brief Addressing mode. */
+typedef enum _i2c_slave_address_mode
+{
+    kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */
+    kI2C_RangeMatch  = 0X2U, /*!< Range address match addressing mode. */
+} i2c_slave_address_mode_t;
+
+/*! @brief I2C transfer control flag. */
+enum _i2c_master_transfer_flags
+{
+    kI2C_TransferDefaultFlag = 0x0U,       /*!< A transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x1U,       /*!< A transfer starts without a start signal, only support write only or
+                                        write+read with no start flag, do not support read only with no start flag. */
+    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */
+    kI2C_TransferNoStopFlag        = 0x4U, /*!< A transfer ends without a stop signal. */
+};
+
+/*!
+ * @brief Set of events sent to the callback for nonblocking slave transfers.
+ *
+ * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
+ * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable.
+ * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
+ * parameter.
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask of events.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
+    kI2C_SlaveTransmitEvent     = 0x02U, /*!< A callback is requested to provide data to transmit
+                                                (slave-transmitter role). */
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< A callback is requested to provide a buffer in which to place received
+                                                 data (slave-receiver role). */
+    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< A callback needs to either transmit an ACK or NACK. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
+#endif
+    kI2C_SlaveCompletionEvent  = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */
+    kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */
+
+    /*! A bit mask of all available events. */
+    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+                          kI2C_SlaveStartEvent |
+#endif
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent,
+} i2c_slave_transfer_event_t;
+
+/*! @brief Common sets of flags used by the driver. */
+enum
+{
+/*! All flags which are cleared by the driver upon starting a transfer. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag,
+    kIrqFlags   = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable,
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag,
+    kIrqFlags   = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable,
+#else
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag,
+    kIrqFlags   = kI2C_GlobalInterruptEnable,
+#endif
+};
+
+/*! @brief I2C master user configuration. */
+typedef struct _i2c_master_config
+{
+    bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    bool enableStopHold; /*!< Controls the stop hold enable. */
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
+#endif
+    uint32_t baudRate_Bps;     /*!< Baud rate configuration of I2C peripheral. */
+    uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */
+} i2c_master_config_t;
+
+/*! @brief I2C slave user configuration. */
+typedef struct _i2c_slave_config
+{
+    bool enableSlave;       /*!< Enables the I2C peripheral at initialization time. */
+    bool enableGeneralCall; /*!< Enables the general call addressing mode. */
+    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low-power mode. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
+#endif
+    bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */
+    uint16_t slaveAddress;  /*!< A slave address configuration. */
+    uint16_t upperAddress;  /*!< A maximum boundary slave address used in a range matching mode. */
+    i2c_slave_address_mode_t
+        addressingMode;          /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */
+    uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+                                    data) while SCL is high (stop condition), SDA hold time and SCL start hold time
+                                    are also configured according to the SCL stop hold time. */
+} i2c_slave_config_t;
+
+/*! @brief I2C master handle typedef. */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*! @brief I2C master transfer callback typedef. */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+                                               i2c_master_handle_t *handle,
+                                               status_t status,
+                                               void *userData);
+
+/*! @brief I2C slave handle typedef. */
+typedef struct _i2c_slave_handle i2c_slave_handle_t;
+
+/*! @brief I2C master transfer structure. */
+typedef struct _i2c_master_transfer
+{
+    uint32_t flags;            /*!< A transfer flag which controls the transfer. */
+    uint8_t slaveAddress;      /*!< 7-bit slave address. */
+    i2c_direction_t direction; /*!< A transfer direction, read or write. */
+    uint32_t subaddress;       /*!< A sub address. Transferred MSB first. */
+    uint8_t subaddressSize;    /*!< A size of the command buffer. */
+    uint8_t *volatile data;    /*!< A transfer buffer. */
+    volatile size_t dataSize;  /*!< A transfer size. */
+} i2c_master_transfer_t;
+
+/*! @brief I2C master handle structure. */
+struct _i2c_master_handle
+{
+    i2c_master_transfer_t transfer;                    /*!< I2C master transfer copy. */
+    size_t transferSize;                               /*!< Total bytes to be transferred. */
+    uint8_t state;                                     /*!< A transfer state maintained during transfer. */
+    i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */
+    void *userData;                                    /*!< A callback parameter passed to the callback function. */
+};
+
+/*! @brief I2C slave transfer structure. */
+typedef struct _i2c_slave_transfer
+{
+    i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */
+    uint8_t *volatile data;           /*!< A transfer buffer. */
+    volatile size_t dataSize;         /*!< A transfer size. */
+    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
+                                         #kI2C_SlaveCompletionEvent. */
+    size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated
+                                start. */
+} i2c_slave_transfer_t;
+
+/*! @brief I2C slave transfer callback typedef. */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData);
+
+/*! @brief I2C slave handle structure. */
+struct _i2c_slave_handle
+{
+    volatile bool isBusy;                   /*!< Indicates whether a transfer is busy. */
+    i2c_slave_transfer_t transfer;          /*!< I2C slave transfer copy. */
+    uint32_t eventMask;                     /*!< A mask of enabled events. */
+    i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */
+    void *userData;                         /*!< A callback parameter passed to the callback. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and configure the I2C with master configuration.
+ *
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can be custom filled
+ * or it can be set with default values by using the I2C_MasterGetDefaultConfig().
+ * After calling this API, the master is ready to transfer.
+ * This is an example.
+ * @code
+ * i2c_master_config_t config = {
+ * .enableMaster = true,
+ * .enableStopHold = false,
+ * .highDrive = false,
+ * .baudRate_Bps = 100000,
+ * .glitchFilterWidth = 0
+ * };
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param masterConfig A pointer to the master configuration structure
+ * @param srcClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and initialize the I2C with the slave configuration.
+ *
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can partly be set
+ * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user.
+ * This is an example.
+ * @code
+ * i2c_slave_config_t config = {
+ * .enableSlave = true,
+ * .enableGeneralCall = false,
+ * .addressingMode = kI2C_Address7bit,
+ * .slaveAddress = 0x1DU,
+ * .enableWakeUp = false,
+ * .enablehighDrive = false,
+ * .enableBaudRateCtl = false,
+ * .sclStopHoldTime_ns = 4000
+ * };
+ * I2C_SlaveInit(I2C0, &config, 12000000U);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param slaveConfig A pointer to the slave configuration structure
+ * @param srcClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
+ * The I2C master module can't work unless the I2C_MasterInit is called.
+ * @param base I2C base pointer
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock.
+ * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.
+ * @param base I2C base pointer
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+
+/*!
+ * @brief Get instance number for I2C module.
+ *
+ * @param base I2C peripheral base address.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*!
+ * @brief  Sets the I2C master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
+ * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify
+ * the structure before calling the I2C_MasterConfigure().
+ * This is an example.
+ * @code
+ * i2c_master_config_t config;
+ * I2C_MasterGetDefaultConfig(&config);
+ * @endcode
+ * @param masterConfig A pointer to the master configuration structure.
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief  Sets the I2C slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure().
+ * Modify fields of the structure before calling the I2C_SlaveConfigure().
+ * This is an example.
+ * @code
+ * i2c_slave_config_t config;
+ * I2C_SlaveGetDefaultConfig(&config);
+ * @endcode
+ * @param slaveConfig A pointer to the slave configuration structure.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Enables or disables the I2C peripheral operation.
+ *
+ * @param base I2C base pointer
+ * @param enable Pass true to enable and false to disable the module.
+ */
+static inline void I2C_Enable(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= I2C_C1_IICEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~(uint8_t)I2C_C1_IICEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * @param base I2C base pointer
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
+ */
+uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * @param base I2C base pointer
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
+ */
+static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
+{
+    return I2C_MasterGetStatusFlags(base);
+}
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag.
+ *
+ * @param base I2C base pointer
+ * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
+ *      The parameter can be any combination of the following values:
+ *          @arg kI2C_StartDetectFlag (if available)
+ *          @arg kI2C_StopDetectFlag (if available)
+ *          @arg kI2C_ArbitrationLostFlag
+ *          @arg kI2C_IntPendingFlagFlag
+ */
+static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+/* Must clear the STARTF / STOPF bits prior to clearing IICIF */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if ((uint32_t)kI2C_StartDetectFlag == (statusMask & (uint32_t)kI2C_StartDetectFlag))
+    {
+        /* Shift the odd-ball flags back into place. */
+        base->FLT |= (uint8_t)(statusMask >> 8U);
+    }
+#endif
+
+#ifdef I2C_HAS_STOP_DETECT
+    if ((uint32_t)kI2C_StopDetectFlag == (statusMask & (uint32_t)kI2C_StopDetectFlag))
+    {
+        /* Shift the odd-ball flags back into place. */
+        base->FLT |= (uint8_t)(statusMask >> 8U);
+    }
+#endif
+
+    base->S = (uint8_t)statusMask;
+}
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ *
+ * @param base I2C base pointer
+ * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
+ *      The parameter can be any combination of the following values:
+ *          @arg kI2C_StartDetectFlag (if available)
+ *          @arg kI2C_StopDetectFlag (if available)
+ *          @arg kI2C_ArbitrationLostFlag
+ *          @arg kI2C_IntPendingFlagFlag
+ */
+static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    I2C_MasterClearStatusFlags(base, statusMask);
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables I2C interrupt requests.
+ *
+ * @param base I2C base pointer
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kI2C_GlobalInterruptEnable
+ *     @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     @arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables I2C interrupt requests.
+ *
+ * @param base I2C base pointer
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kI2C_GlobalInterruptEnable
+ *     @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     @arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask);
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT
+/*!
+ * @brief Enables/disables the I2C DMA interrupt.
+ *
+ * @param base I2C base pointer
+ * @param enable true to enable, false to disable
+ */
+static inline void I2C_EnableDMA(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= I2C_C1_DMAEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~(uint8_t)I2C_C1_DMAEN_MASK;
+    }
+}
+
+#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */
+
+/*!
+ * @brief  Gets the I2C tx/rx data register address. This API is used to provide a transfer address
+ * for I2C DMA transfer configuration.
+ *
+ * @param base I2C base pointer
+ * @return data register address
+ */
+static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base)
+{
+    return (uint32_t)(&(base->D));
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the I2C master transfer baud rate.
+ *
+ * @param base I2C base pointer
+ * @param baudRate_Bps the baud rate value in bps
+ * @param srcClock_Hz Source clock
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * @retval kStatus_Success Successfully send the stop signal.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base);
+
+/*!
+ * @brief Sends a REPEATED START on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+ *  to issue a stop and kI2C_TransferNoStop to not send a stop.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus.
+ *
+ * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
+ * Without stopping the bus prior for the final read, the bus issues another read, resulting
+ * in garbage data being read into the data register.
+ *
+ * @param base I2C peripheral base pointer.
+ * @param rxBuff The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+ *  to issue a stop and kI2C_TransferNoStop to not send a stop.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags);
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer.
+ * @param rxBuff The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ * @retval kStatus_Success Successfully complete data receive.
+ * @retval kStatus_I2C_Timeout Wait status flag timeout.
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C peripheral base address.
+ * @param xfer Pointer to the transfer structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * @note Calling the API returns immediately after transfer initiates. The user needs
+ * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
+ * is finished.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ * @retval kStatus_I2C_Timeout Timeout during polling flag.
+ * @retval kStatus_Success Successfully abort the transfer.
+ */
+status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_master_handle_t structure.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The kI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
+
+/*!
+ * @brief Aborts the slave transfer.
+ *
+ * @note This API can be called at any time to stop slave for handling the bus events.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*!
+ * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Slave interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*! @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*! @} */
+
+#endif /* FSL_I2C_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.c
new file mode 100644
index 0000000000..0337f11764
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.c
@@ -0,0 +1,608 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_i2c_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.i2c_dma"
+#endif
+
+/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
+typedef struct _i2c_master_dma_private_handle
+{
+    I2C_Type *base;
+    i2c_master_dma_handle_t *handle;
+} i2c_master_dma_private_handle_t;
+
+/*! @brief i2c master DMA transfer state. */
+enum _i2c_master_dma_transfer_states
+{
+    kIdleState         = 0x0U, /*!< I2C bus idle. */
+    kTransferDataState = 0x1U, /*!< 7-bit address check state. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA callback for I2C master DMA driver.
+ *
+ * @param handle DMA handler for I2C master DMA driver
+ * @param userData user param passed to the callback function
+ */
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief Check and clear status operation.
+ *
+ * @param base I2C peripheral base address.
+ * @param status current i2c hardware status
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ */
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief DMA config for I2C master driver.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
+ */
+static void I2C_MasterTransferDMAConfig(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/*!
+ * @brief Set up master transfer, send slave address and sub address(if any), wait until the
+ * wait until address sent status return.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
+{
+    i2c_master_dma_private_handle_t *i2cPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
+    status_t result                                   = kStatus_Success;
+    uint32_t tmpsize                                  = (uint32_t)i2cPrivateHandle->handle->transfer.dataSize;
+    uint8_t tmpdata;
+
+    /* Disable DMA. */
+    I2C_EnableDMA(i2cPrivateHandle->base, false);
+
+    /* Send stop if kI2C_TransferNoStop flag is not asserted. */
+    if (0U == (i2cPrivateHandle->handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag))
+    {
+        if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read)
+        {
+            /* Change to send NAK at the last byte. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK;
+
+            /* Wait the last data to be received. */
+            while (0U == (i2cPrivateHandle->base->S & (uint8_t)kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Send stop signal. */
+            result = I2C_MasterStop(i2cPrivateHandle->base);
+
+            /* Read the last data byte. */
+            tmpdata                                                   = i2cPrivateHandle->base->D;
+            *(i2cPrivateHandle->handle->transfer.data + tmpsize - 1U) = tmpdata;
+        }
+        else
+        {
+            /* Wait the last data to be sent. */
+            while (0U == (i2cPrivateHandle->base->S & (uint8_t)kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Send stop signal. */
+            result = I2C_MasterStop(i2cPrivateHandle->base);
+        }
+    }
+    else
+    {
+        if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read)
+        {
+            /* Change to send NAK at the last byte. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK;
+
+            /* Wait the last data to be received. */
+            while (0U == (i2cPrivateHandle->base->S & (uint8_t)kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Change direction to send. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK;
+
+            /* Read the last data byte. */
+            tmpdata                                                   = i2cPrivateHandle->base->D;
+            *(i2cPrivateHandle->handle->transfer.data + tmpsize - 1U) = tmpdata;
+        }
+    }
+
+    i2cPrivateHandle->handle->state = (uint8_t)kIdleState;
+
+    if (i2cPrivateHandle->handle->completionCallback != NULL)
+    {
+        i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result,
+                                                     i2cPrivateHandle->handle->userData);
+    }
+}
+
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
+{
+    status_t result = kStatus_Success;
+
+    /* Check arbitration lost. */
+    if ((status & (uint32_t)kI2C_ArbitrationLostFlag) != 0U)
+    {
+        /* Clear arbitration lost flag. */
+        base->S = (uint8_t)kI2C_ArbitrationLostFlag;
+        result  = kStatus_I2C_ArbitrationLost;
+    }
+    /* Check NAK */
+    else if ((status & (uint32_t)kI2C_ReceiveNakFlag) != 0U)
+    {
+        result = kStatus_I2C_Nak;
+    }
+    else
+    {
+        /* Avoid MISRA 2012 rule 15.7 */
+    }
+
+    return result;
+}
+
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    /* Set up transfer first. */
+    i2c_direction_t direction = xfer->direction;
+    status_t result           = kStatus_Success;
+#if I2C_RETRY_TIMES
+    uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+
+    if (handle->state != (uint8_t)kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Init the handle member. */
+        handle->transfer = *xfer;
+
+        /* Save total transfer size. */
+        handle->transferSize = xfer->dataSize;
+
+        handle->state = (uint8_t)kTransferDataState;
+
+        /* Clear all status before transfer. */
+        I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
+
+        /* Change to send write address when it's a read operation with command. */
+        if ((xfer->subaddressSize > 0U) && (xfer->direction == kI2C_Read))
+        {
+            direction = kI2C_Write;
+        }
+
+        /* If repeated start is requested, send repeated start. */
+        if ((handle->transfer.flags & (uint32_t)kI2C_TransferRepeatedStartFlag) != 0U)
+        {
+            result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
+        }
+        else /* For normal transfer, send start. */
+        {
+            result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
+        }
+
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+#if I2C_RETRY_TIMES
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != --waitTimes))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+
+        /* Check if there's transfer error. */
+        result = I2C_CheckAndClearError(base, base->S);
+
+        /* Return if error. */
+        if (result != kStatus_Success)
+        {
+            if (result == kStatus_I2C_Nak)
+            {
+                result = kStatus_I2C_Addr_Nak;
+
+                if (I2C_MasterStop(base) != kStatus_Success)
+                {
+                    result = kStatus_I2C_Timeout;
+                }
+
+                if (handle->completionCallback != NULL)
+                {
+                    (handle->completionCallback)(base, handle, result, handle->userData);
+                }
+            }
+
+            return result;
+        }
+
+        /* Send subaddress. */
+        if (handle->transfer.subaddressSize != 0U)
+        {
+            do
+            {
+                /* Clear interrupt pending flag. */
+                base->S = (uint8_t)kI2C_IntPendingFlag;
+
+                handle->transfer.subaddressSize--;
+                base->D = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize));
+
+                /* Wait until data transfer complete. */
+#if I2C_RETRY_TIMES
+                waitTimes = I2C_RETRY_TIMES;
+                while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != --waitTimes))
+                {
+                }
+                if (waitTimes == 0U)
+                {
+                    return kStatus_I2C_Timeout;
+                }
+#else
+                while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+                {
+                }
+#endif
+
+                /* Check if there's transfer error. */
+                result = I2C_CheckAndClearError(base, base->S);
+
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+
+            } while (handle->transfer.subaddressSize > 0U);
+
+            if (handle->transfer.direction == kI2C_Read)
+            {
+                /* Clear pending flag. */
+                base->S = (uint8_t)kI2C_IntPendingFlag;
+
+                /* Send repeated start and slave address. */
+                result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
+
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+
+                /* Wait until data transfer complete. */
+#if I2C_RETRY_TIMES
+                waitTimes = I2C_RETRY_TIMES;
+                while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != --waitTimes))
+                {
+                }
+                if (waitTimes == 0U)
+                {
+                    return kStatus_I2C_Timeout;
+                }
+#else
+                while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+                {
+                }
+#endif
+
+                /* Check if there's transfer error. */
+                result = I2C_CheckAndClearError(base, base->S);
+
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+        }
+
+        /* Clear pending flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+    }
+
+    return result;
+}
+
+static void I2C_MasterTransferDMAConfig(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    dma_transfer_config_t transfer_config   = {0};
+    dma_transfer_options_t transfer_options = kDMA_EnableInterrupt;
+
+    if (handle->transfer.direction == kI2C_Read)
+    {
+        transfer_config.srcAddr             = (uint32_t)I2C_GetDataRegAddr(base);
+        transfer_config.destAddr            = (uint32_t)(handle->transfer.data);
+        transfer_config.transferSize        = (handle->transfer.dataSize - 1U);
+        transfer_config.srcSize             = kDMA_Transfersize8bits;
+        transfer_config.enableSrcIncrement  = false;
+        transfer_config.destSize            = kDMA_Transfersize8bits;
+        transfer_config.enableDestIncrement = true;
+    }
+    else
+    {
+        transfer_config.srcAddr             = (uint32_t)(handle->transfer.data + 1U);
+        transfer_config.destAddr            = (uint32_t)I2C_GetDataRegAddr(base);
+        transfer_config.transferSize        = (handle->transfer.dataSize - 1U);
+        transfer_config.srcSize             = kDMA_Transfersize8bits;
+        transfer_config.enableSrcIncrement  = true;
+        transfer_config.destSize            = kDMA_Transfersize8bits;
+        transfer_config.enableDestIncrement = false;
+    }
+
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &transfer_config, (uint32_t)transfer_options);
+    DMA_StartTransfer(handle->dmaHandle);
+}
+
+/*!
+ * brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * param base I2C peripheral base address
+ * param handle Pointer to the i2c_master_dma_handle_t structure
+ * param callback Pointer to the user callback function
+ * param userData A user parameter passed to the callback function
+ * param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle)
+{
+    assert(handle != NULL);
+    assert(dmaHandle != NULL);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set the user callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+    /* Set the handle for DMA. */
+    handle->dmaHandle = dmaHandle;
+
+    s_dmaPrivateHandle[instance].base   = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
+}
+
+/*!
+ * brief Performs a master DMA non-blocking transfer on the I2C bus.
+ *
+ * param base I2C peripheral base address
+ * param handle A pointer to the i2c_master_dma_handle_t structure
+ * param xfer A pointer to the transfer structure of the i2c_master_transfer_t
+ * retval kStatus_Success Successfully completes the data transmission.
+ * retval kStatus_I2C_Busy A previous transmission is still not finished.
+ * retval kStatus_I2C_Timeout A transfer error, waits for the signal timeout.
+ * retval kStatus_I2C_ArbitrationLost A transfer error, arbitration lost.
+ * retval kStataus_I2C_Nak A transfer error, receives NAK during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    status_t result;
+    uint8_t tmpReg;
+    uint8_t tmpdata;
+
+    /* Disable dma transfer. */
+    I2C_EnableDMA(base, false);
+
+    /* Send address and command buffer(if there is), until senddata phase or receive data phase. */
+    result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
+
+    if (result != kStatus_Success)
+    {
+        /* Send stop if received Nak. */
+        if (result == kStatus_I2C_Nak)
+        {
+            if (I2C_MasterStop(base) != kStatus_Success)
+            {
+                result = kStatus_I2C_Timeout;
+            }
+        }
+
+        /* Reset the state to idle state. */
+        handle->state = (uint8_t)kIdleState;
+
+        return result;
+    }
+
+    /* Configure dma transfer. */
+    /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read,
+    need to send stop before reading the last byte, so the dma transfer size should
+    be (xSize - 1). */
+    if (handle->transfer.dataSize > 1U)
+    {
+        I2C_MasterTransferDMAConfig(base, handle);
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            /* Change direction for receive. */
+            base->C1 &= ~((uint8_t)I2C_C1_TX_MASK | (uint8_t)I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release the bus. */
+            (void)base->D;
+
+            /* Enabe dma transfer. */
+            I2C_EnableDMA(base, true);
+        }
+        else
+        {
+            /* Enabe dma transfer. */
+            I2C_EnableDMA(base, true);
+
+            /* Send the first data. */
+            base->D = *handle->transfer.data;
+        }
+    }
+    else /* If transfer size is 1, use polling method. */
+    {
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            tmpReg = base->C1;
+
+            /* Change direction to Rx. */
+            tmpReg &= ~(uint8_t)I2C_C1_TX_MASK;
+
+            /* Configure send NAK */
+            tmpReg |= I2C_C1_TXAK_MASK;
+
+            base->C1 = tmpReg;
+
+            /* Read dummy to release the bus. */
+            (void)base->D;
+        }
+        else
+        {
+            base->D = *handle->transfer.data;
+        }
+
+        /* Wait until data transfer complete. */
+#if I2C_RETRY_TIMES
+        uint32_t waitTimes = I2C_RETRY_TIMES;
+        while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != --waitTimes))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_I2C_Timeout;
+        }
+#else
+        while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
+        {
+        }
+#endif
+
+        /* Clear pending flag. */
+        base->S = (uint8_t)kI2C_IntPendingFlag;
+
+        /* Send stop if kI2C_TransferNoStop flag is not asserted. */
+        if (0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag))
+        {
+            result = I2C_MasterStop(base);
+        }
+        else
+        {
+            /* Change direction to send. */
+            base->C1 |= I2C_C1_TX_MASK;
+        }
+
+        /* Read the last byte of data. */
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            tmpdata                = base->D;
+            *handle->transfer.data = tmpdata;
+        }
+
+        /* Reset the state to idle. */
+        handle->state = (uint8_t)kIdleState;
+
+        /* Call the callback function after the function has completed. */
+        if (handle->completionCallback != NULL)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+
+    return result;
+}
+
+/*!
+ * brief Gets a master transfer status during a DMA non-blocking transfer.
+ *
+ * param base I2C peripheral base address
+ * param handle A pointer to the i2c_master_dma_handle_t structure
+ * param count A number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((uint8_t)kIdleState != handle->state)
+    {
+        *count = (handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->transferSize;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a master DMA non-blocking transfer early.
+ *
+ * param base I2C peripheral base address
+ * param handle A pointer to the i2c_master_dma_handle_t structure.
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable dma transfer. */
+    I2C_EnableDMA(base, false);
+
+    /* Reset the state to idle. */
+    handle->state = (uint8_t)kIdleState;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.h
new file mode 100644
index 0000000000..45fb19faac
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_i2c_dma.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_I2C_DMA_H_
+#define FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup i2c_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief I2C DMA driver version. */
+#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 9))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef I2C_RETRY_TIMES
+#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief I2C master DMA handle typedef. */
+typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
+
+/*! @brief I2C master DMA transfer callback typedef. */
+typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
+                                                   i2c_master_dma_handle_t *handle,
+                                                   status_t status,
+                                                   void *userData);
+
+/*! @brief I2C master DMA transfer structure. */
+struct _i2c_master_dma_handle
+{
+    i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */
+    size_t transferSize;            /*!< Total bytes to be transferred. */
+    uint8_t state;                  /*!< I2C master transfer status. */
+    dma_handle_t *dmaHandle;        /*!< The DMA handler used. */
+    i2c_master_dma_transfer_callback_t
+        completionCallback; /*!< A callback function called after the DMA transfer finished. */
+    void *userData;         /*!< A callback parameter passed to the callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block DMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base I2C peripheral base address
+ * @param handle Pointer to the i2c_master_dma_handle_t structure
+ * @param callback Pointer to the user callback function
+ * @param userData A user parameter passed to the callback function
+ * @param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a master DMA non-blocking transfer on the I2C bus.
+ *
+ * @param base I2C peripheral base address
+ * @param handle A pointer to the i2c_master_dma_handle_t structure
+ * @param xfer A pointer to the transfer structure of the i2c_master_transfer_t
+ * @retval kStatus_Success Successfully completes the data transmission.
+ * @retval kStatus_I2C_Busy A previous transmission is still not finished.
+ * @retval kStatus_I2C_Timeout A transfer error, waits for the signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost A transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak A transfer error, receives NAK during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Gets a master transfer status during a DMA non-blocking transfer.
+ *
+ * @param base I2C peripheral base address
+ * @param handle A pointer to the i2c_master_dma_handle_t structure
+ * @param count A number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts a master DMA non-blocking transfer early.
+ *
+ * @param base I2C peripheral base address
+ * @param handle A pointer to the i2c_master_dma_handle_t structure.
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/*! @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*! @} */
+#endif /*FSL_I2C_DMA_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.c
new file mode 100644
index 0000000000..08e5dc1190
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_llwu.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.llwu"
+#endif
+
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN)
+/*!
+ * brief Sets the external input pin source mode.
+ *
+ * This function sets the external input pin source mode that is used
+ * as a wake up source.
+ *
+ * param base LLWU peripheral base address.
+ * param pinIndex A pin index to be enabled as an external wakeup source starting from 1.
+ * param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t.
+ */
+void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    volatile uint32_t *regBase;
+    uint32_t regOffset;
+    uint32_t reg;
+
+    switch (pinIndex >> 4U)
+    {
+        case 0U:
+            regBase = &base->PE1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 1U:
+            regBase = &base->PE2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (NULL != regBase)
+    {
+        reg       = *regBase;
+        regOffset = ((pinIndex & 0x0FU) << 1U);
+        reg &= LLWU_REG_VAL(~(3UL << regOffset));
+        reg |= ((uint32_t)pinMode << regOffset);
+        *regBase = reg;
+    }
+#else
+    volatile uint8_t *regBase;
+    uint8_t regOffset;
+    uint8_t reg;
+    switch (pinIndex >> 2U)
+    {
+        case 0U:
+            regBase = &base->PE1;
+            break;
+        case 1U:
+            regBase = &base->PE2;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 2U:
+            regBase = &base->PE3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12))
+        case 3U:
+            regBase = &base->PE4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 4U:
+            regBase = &base->PE5;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20))
+        case 5U:
+            regBase = &base->PE6;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 6U:
+            regBase = &base->PE7;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28))
+        case 7U:
+            regBase = &base->PE8;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (NULL != regBase)
+    {
+        reg       = *regBase;
+        regOffset = (uint8_t)((pinIndex & 0x03U) << 1U);
+        reg &= LLWU_REG_VAL(~(3UL << regOffset));
+        reg |= (uint8_t)((uint32_t)pinMode << regOffset);
+        *regBase = reg;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */
+}
+
+/*!
+ * brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the MCU is
+ * woken up by the specific pin.
+ *
+ * param base LLWU peripheral base address.
+ * param pinIndex     A pin index, which starts from 1.
+ * return True if the specific pin is a wakeup source.
+ */
+bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    return (0U != (base->PF & (1UL << pinIndex)));
+#else
+    bool ret;
+    volatile uint8_t *regBase;
+
+    switch (pinIndex >> 3U)
+    {
+#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+        case 0U:
+            regBase = &base->PF1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->PF2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->PF3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->PF4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#else
+        case 0U:
+            regBase = &base->F1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->F2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->F3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->F4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (NULL != regBase)
+    {
+        if (0U != (*regBase & (1U << pinIndex % 8U)))
+        {
+            ret = true;
+        }
+        else
+        {
+            ret = false;
+        }
+    }
+    else
+    {
+        ret = false;
+    }
+
+    return ret;
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+/*!
+ * brief Clears the external wakeup source flag.
+ *
+ * This function clears the external wakeup source flag for a specific pin.
+ *
+ * param base LLWU peripheral base address.
+ * param pinIndex A pin index, which starts from 1.
+ */
+void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    base->PF = (1UL << pinIndex);
+#else
+    volatile uint8_t *regBase;
+    switch (pinIndex >> 3U)
+    {
+#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+        case 0U:
+            regBase = &base->PF1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->PF2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->PF3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->PF4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#else
+        case 0U:
+            regBase = &base->F1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->F2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->F3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->F4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
+        default:
+            regBase = NULL;
+            break;
+    }
+    if (NULL != regBase)
+    {
+        *regBase = (1U << pinIndex % 8U);
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+/*!
+ * brief Sets the pin filter configuration.
+ *
+ * This function sets the pin filter configuration.
+ *
+ * param base LLWU peripheral base address.
+ * param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1.
+ * param filterMode A filter mode configuration
+ */
+void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    uint32_t filt;
+    uint32_t shiftInReg;
+
+    if ((filterIndex > 0U) && (filterIndex <= (uint32_t)FSL_FEATURE_LLWU_HAS_PIN_FILTER))
+    {
+        shiftInReg = (filterIndex - 1U) * 8U;
+
+        filt = base->FILT;
+        /* Clean the W1C bits, in case the flags are cleared by mistake. */
+        filt &= ~(((uint32_t)LLWU_FILT_FILTF1_MASK << 0U) | ((uint32_t)LLWU_FILT_FILTF1_MASK << 8U) |
+                  ((uint32_t)LLWU_FILT_FILTF1_MASK << 16U) | ((uint32_t)LLWU_FILT_FILTF1_MASK << 24U));
+
+        filt &= ~(((uint32_t)LLWU_FILT_FILTSEL1_MASK | (uint32_t)LLWU_FILT_FILTE1_MASK) << shiftInReg);
+
+        filt |=
+            ((LLWU_FILT_FILTSEL1(filterMode.pinIndex) | LLWU_FILT_FILTE1(filterMode.filterMode) | LLWU_FILT_FILTF1_MASK)
+             << shiftInReg);
+
+        base->FILT = filt;
+    }
+#else
+    volatile uint8_t *regBase;
+
+    switch (filterIndex)
+    {
+        case 1U:
+            regBase = &base->FILT1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2U:
+            regBase = &base->FILT2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3U:
+            regBase = &base->FILT3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4U:
+            regBase = &base->FILT4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (NULL != regBase)
+    {
+        *regBase = (uint8_t)((*regBase & ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK)) |
+                             LLWU_FILT1_FILTSEL(filterMode.pinIndex) | LLWU_FILT1_FILTE(filterMode.filterMode) |
+                             LLWU_FILT1_FILTF_MASK) /* W1C to clear the FILTF flag bit. */
+            ;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+/*!
+ * brief Gets the pin filter configuration.
+ *
+ * This function gets the pin filter flag.
+ *
+ * param base LLWU peripheral base address.
+ * param filterIndex A pin filter index, which starts from 1.
+ * return True if the flag is a source of the existing low-leakage power mode.
+ */
+bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    return (0U != (base->FILT & (1UL << (filterIndex * 8U - 1U))));
+#else
+    bool status = false;
+
+    switch (filterIndex)
+    {
+        case 1:
+            status = ((base->FILT1 & LLWU_FILT1_FILTF_MASK) != 0U);
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2:
+            status = ((base->FILT2 & LLWU_FILT2_FILTF_MASK) != 0U);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3:
+            status = ((base->FILT3 & LLWU_FILT3_FILTF_MASK) != 0U);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4:
+            status = ((base->FILT4 & LLWU_FILT4_FILTF_MASK) != 0U);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            status = false;
+            break;
+    }
+
+    return status;
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+/*!
+ * brief Clears the pin filter configuration.
+ *
+ * This function clears the pin filter flag.
+ *
+ * param base LLWU peripheral base address.
+ * param filterIndex A pin filter index to clear the flag, starting from 1.
+ */
+void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 0))
+    uint32_t reg;
+
+    if ((filterIndex > 0U) && (filterIndex <= (uint32_t)FSL_FEATURE_LLWU_HAS_PIN_FILTER))
+    {
+        reg = base->FILT;
+
+        /* Clean the W1C bits, in case the flags are cleared by mistake. */
+        reg &= ~(((uint32_t)LLWU_FILT_FILTF1_MASK << 0U) | ((uint32_t)LLWU_FILT_FILTF1_MASK << 8U) |
+                 ((uint32_t)LLWU_FILT_FILTF1_MASK << 16U) | ((uint32_t)LLWU_FILT_FILTF1_MASK << 24U));
+
+        reg |= ((uint32_t)LLWU_FILT_FILTF1_MASK << ((filterIndex - 1U) * 8U));
+
+        base->FILT = reg;
+    }
+
+#endif
+
+    return;
+#else
+    volatile uint8_t *regBase;
+    uint8_t reg;
+
+    switch (filterIndex)
+    {
+        case 1:
+            regBase = &base->FILT1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2:
+            regBase = &base->FILT2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3:
+            regBase = &base->FILT3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4:
+            regBase = &base->FILT4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (NULL != regBase)
+    {
+        reg = *regBase;
+        reg |= LLWU_FILT1_FILTF_MASK;
+        *regBase = reg;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE)
+/*!
+ * brief Sets the reset pin mode.
+ *
+ * This function determines how the reset pin is used as a low leakage mode exit source.
+ *
+ * param pinEnable       Enable reset the pin filter
+ * param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode.
+ */
+void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable)
+{
+    uint8_t reg;
+
+    reg = base->RST;
+
+    reg &= (uint8_t)(~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK));
+
+    if (pinEnable)
+    {
+        reg |= LLWU_RST_LLRSTE_MASK;
+    }
+
+    if (pinFilterEnable)
+    {
+        reg |= LLWU_RST_RSTFILT_MASK;
+    }
+
+    base->RST = reg;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.h
new file mode 100644
index 0000000000..35b19b14ae
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_llwu.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_LLWU_H_
+#define FSL_LLWU_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup llwu */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief LLWU driver version. */
+#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*! @} */
+
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+#define LLWU_REG_VAL(x) ((uint32_t)(x))
+#else
+#define LLWU_REG_VAL(x) ((uint8_t)(x))
+#endif
+
+/*!
+ * @brief External input pin control modes
+ */
+typedef enum _llwu_external_pin_mode
+{
+    kLLWU_ExternalPinDisable     = 0U, /*!< Pin disabled as a wakeup input.           */
+    kLLWU_ExternalPinRisingEdge  = 1U, /*!< Pin enabled with the rising edge detection. */
+    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/
+    kLLWU_ExternalPinAnyEdge     = 3U  /*!< Pin enabled with any change detection.  */
+} llwu_external_pin_mode_t;
+
+/*!
+ * @brief Digital filter control modes
+ */
+typedef enum _llwu_pin_filter_mode
+{
+    kLLWU_PinFilterDisable     = 0U, /*!< Filter disabled.               */
+    kLLWU_PinFilterRisingEdge  = 1U, /*!< Filter positive edge detection.*/
+    kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/
+    kLLWU_PinFilterAnyEdge     = 3U  /*!< Filter any edge detection.     */
+} llwu_pin_filter_mode_t;
+
+#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _llwu_version_id
+{
+    uint16_t feature; /*!< A feature specification number. */
+    uint8_t minor;    /*!< The minor version number.         */
+    uint8_t major;    /*!< The major version number.         */
+} llwu_version_id_t;
+#endif /* FSL_FEATURE_LLWU_HAS_VERID */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM)
+/*!
+ * @brief IP parameter definition.
+ */
+typedef struct _llwu_param
+{
+    uint8_t filters; /*!< A number of the pin filter.      */
+    uint8_t dmas;    /*!< A number of the wakeup DMA.      */
+    uint8_t modules; /*!< A number of the wakeup module.   */
+    uint8_t pins;    /*!< A number of the wake up pin.     */
+} llwu_param_t;
+#endif /* FSL_FEATURE_LLWU_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+/*!
+ * @brief An external input pin filter control structure
+ */
+typedef struct _llwu_external_pin_filter_mode
+{
+    uint32_t pinIndex;                 /*!< A pin number  */
+    llwu_pin_filter_mode_t filterMode; /*!< Filter mode */
+} llwu_external_pin_filter_mode_t;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Low-Leakage Wakeup Unit Control APIs
+ * @{
+ */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID)
+/*!
+ * @brief Gets the LLWU version ID.
+ *
+ * This function gets the LLWU version ID, including the major version number,
+ * the minor version number, and the feature specification number.
+ *
+ * @param base LLWU peripheral base address.
+ * @param versionId     A pointer to the version ID structure.
+ */
+static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId)
+{
+    union
+    {
+        llwu_version_id_t vid;
+        uint32_t u32;
+    } llwuVID;
+
+    llwuVID.u32 = base->VERID;
+
+    *versionId = llwuVID.vid;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_VERID */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM)
+/*!
+ * @brief Gets the LLWU parameter.
+ *
+ * This function gets the LLWU parameter, including a wakeup pin number, a module
+ * number, a DMA number, and a pin filter number.
+ *
+ * @param base LLWU peripheral base address.
+ * @param param         A pointer to the LLWU parameter structure.
+ */
+static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param)
+{
+    union
+    {
+        llwu_param_t param;
+        uint32_t u32;
+    } llwuParam;
+
+    llwuParam.u32 = base->PARAM;
+
+    *param = llwuParam.param;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN)
+/*!
+ * @brief Sets the external input pin source mode.
+ *
+ * This function sets the external input pin source mode that is used
+ * as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1.
+ * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t.
+ */
+void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode);
+
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the MCU is
+ * woken up by the specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex     A pin index, which starts from 1.
+ * @return True if the specific pin is a wakeup source.
+ */
+bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
+
+/*!
+ * @brief Clears the external wakeup source flag.
+ *
+ * This function clears the external wakeup source flag for a specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex A pin index, which starts from 1.
+ */
+void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE)
+/*!
+ * @brief Enables/disables the internal module source.
+ *
+ * This function enables/disables the internal module source mode that is used
+ * as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex   A module index to be enabled as an internal wakeup source starting from 1.
+ * @param enable        An enable or a disable setting
+ */
+static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
+{
+    if (enable)
+    {
+        base->ME |= LLWU_REG_VAL(1UL << moduleIndex);
+    }
+    else
+    {
+        base->ME &= LLWU_REG_VAL(~(1UL << moduleIndex));
+    }
+}
+
+#if (!(defined(FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG) && \
+       FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG))
+/* Re-define the register which includes the internal wakeup module flag. */
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) /* 32-bit LLWU. */
+#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF)
+#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF
+#else
+#error "Unsupported internal module flag register."
+#endif
+#else /* 8-bit LLUW. */
+#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF)
+#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF5
+#elif (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+#define INTERNAL_WAKEUP_MODULE_FLAG_REG PF3
+#elif (!(defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)))
+#define INTERNAL_WAKEUP_MODULE_FLAG_REG F3
+#else
+#error "Unsupported internal module flag register."
+#endif
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the system is
+ * woken up by the specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex  A module index, which starts from 1.
+ * @return True if the specific pin is a wake up source.
+ */
+static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex)
+{
+    return ((1UL << moduleIndex) == ((uint32_t)base->INTERNAL_WAKEUP_MODULE_FLAG_REG & (1UL << moduleIndex)));
+}
+#endif /* FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG */
+#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG)
+/*!
+ * @brief Enables/disables the internal module DMA wakeup source.
+ *
+ * This function enables/disables the internal DMA that is used as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex   An internal module index which is used as a DMA request source, starting from 1.
+ * @param enable        Enable or disable the DMA request source
+ */
+static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
+{
+    if (enable)
+    {
+        base->DE |= LLWU_REG_VAL(1UL << moduleIndex);
+    }
+    else
+    {
+        base->DE &= LLWU_REG_VAL(~(1UL << moduleIndex));
+    }
+}
+#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+/*!
+ * @brief Sets the pin filter configuration.
+ *
+ * This function sets the pin filter configuration.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1.
+ * @param filterMode A filter mode configuration
+ */
+void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode);
+
+/*!
+ * @brief Gets the pin filter configuration.
+ *
+ * This function gets the pin filter flag.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex A pin filter index, which starts from 1.
+ * @return True if the flag is a source of the existing low-leakage power mode.
+ */
+bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
+
+/*!
+ * @brief Clears the pin filter configuration.
+ *
+ * This function clears the pin filter flag.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex A pin filter index to clear the flag, starting from 1.
+ */
+void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
+
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE)
+/*!
+ * @brief Sets the reset pin mode.
+ *
+ * This function determines how the reset pin is used as a low leakage mode exit source.
+ *
+ * @param base            LLWU peripheral base address.
+ * @param pinEnable       Enable reset the pin filter
+ * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode.
+ */
+void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable);
+#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+#endif /* FSL_LLWU_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.c
new file mode 100644
index 0000000000..9e501e7a51
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lptmr.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lptmr"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(LPTMR_CLOCKS)
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The LPTMR instance
+ */
+static uint32_t LPTMR_GetInstance(LPTMR_Type *base);
+#endif /* LPTMR_CLOCKS */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(LPTMR_CLOCKS)
+/*! @brief Pointers to LPTMR bases for each instance. */
+static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to LPTMR clocks for each instance. */
+static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS;
+
+#if defined(LPTMR_PERIPH_CLOCKS)
+/* Array of LPTMR functional clock name. */
+static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* LPTMR_CLOCKS */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(LPTMR_CLOCKS)
+static uint32_t LPTMR_GetInstance(LPTMR_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++)
+    {
+        if (s_lptmrBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_lptmrBases));
+
+    return instance;
+}
+#endif /* LPTMR_CLOCKS */
+
+/*!
+ * brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
+ *
+ * note This API should be called at the beginning of the application using the LPTMR driver.
+ *
+ * param base   LPTMR peripheral base address
+ * param config A pointer to the LPTMR configuration structure.
+ */
+void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)
+{
+    assert(NULL != config);
+
+#if defined(LPTMR_CLOCKS)
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    uint32_t instance = LPTMR_GetInstance(base);
+
+    /* Ungate the LPTMR clock*/
+    CLOCK_EnableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* LPTMR_CLOCKS */
+
+    /* Configure the timers operation mode and input pin setup */
+    base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) |
+                 LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect));
+
+    /* Configure the prescale value and clock source */
+    base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) |
+                 LPTMR_PSR_PCS(config->prescalerClockSource));
+}
+
+/*!
+ * brief Gates the LPTMR clock.
+ *
+ * param base LPTMR peripheral base address
+ */
+void LPTMR_Deinit(LPTMR_Type *base)
+{
+    /* Disable the LPTMR and reset the internal logic */
+    base->CSR &= ~LPTMR_CSR_TEN_MASK;
+
+#if defined(LPTMR_CLOCKS)
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    uint32_t instance = LPTMR_GetInstance(base);
+
+    /* Gate the LPTMR clock*/
+    CLOCK_DisableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* LPTMR_CLOCKS */
+}
+
+/*!
+ * brief Fills in the LPTMR configuration structure with default settings.
+ *
+ * The default values are as follows.
+ * code
+ *    config->timerMode = kLPTMR_TimerModeTimeCounter;
+ *    config->pinSelect = kLPTMR_PinSelectInput_0;
+ *    config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
+ *    config->enableFreeRunning = false;
+ *    config->bypassPrescaler = true;
+ *    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
+ *    config->value = kLPTMR_Prescale_Glitch_0;
+ * endcode
+ * param config A pointer to the LPTMR configuration structure.
+ */
+void LPTMR_GetDefaultConfig(lptmr_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* Use time counter mode */
+    config->timerMode = kLPTMR_TimerModeTimeCounter;
+    /* Use input 0 as source in pulse counter mode */
+    config->pinSelect = kLPTMR_PinSelectInput_0;
+    /* Pulse input pin polarity is active-high */
+    config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
+    /* Counter resets whenever TCF flag is set */
+    config->enableFreeRunning = false;
+    /* Bypass the prescaler */
+    config->bypassPrescaler = true;
+    /* LPTMR clock source */
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_0;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_2;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_3;
+#else
+#error No valid source
+#endif
+
+    /* Divide the prescaler clock by 2 */
+    config->value = kLPTMR_Prescale_Glitch_0;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.h
new file mode 100644
index 0000000000..b8e473120c
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lptmr.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_LPTMR_H_
+#define FSL_LPTMR_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lptmr
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! Driver Version */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @} */
+
+/*! @brief LPTMR pin selection used in pulse counter mode.*/
+typedef enum _lptmr_pin_select
+{
+    kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
+    kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
+    kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
+    kLPTMR_PinSelectInput_3 = 0x3U  /*!< Pulse counter input 3 is selected */
+} lptmr_pin_select_t;
+
+/*! @brief LPTMR pin polarity used in pulse counter mode.*/
+typedef enum _lptmr_pin_polarity
+{
+    kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
+    kLPTMR_PinPolarityActiveLow  = 0x1U  /*!< Pulse Counter input source is active-low */
+} lptmr_pin_polarity_t;
+
+/*! @brief LPTMR timer mode selection.*/
+typedef enum _lptmr_timer_mode
+{
+    kLPTMR_TimerModeTimeCounter  = 0x0U, /*!< Time Counter mode */
+    kLPTMR_TimerModePulseCounter = 0x1U  /*!< Pulse Counter mode */
+} lptmr_timer_mode_t;
+
+/*! @brief LPTMR prescaler/glitch filter values*/
+typedef enum _lptmr_prescaler_glitch_value
+{
+    kLPTMR_Prescale_Glitch_0  = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */
+    kLPTMR_Prescale_Glitch_1  = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */
+    kLPTMR_Prescale_Glitch_2  = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */
+    kLPTMR_Prescale_Glitch_3  = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */
+    kLPTMR_Prescale_Glitch_4  = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */
+    kLPTMR_Prescale_Glitch_5  = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */
+    kLPTMR_Prescale_Glitch_6  = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */
+    kLPTMR_Prescale_Glitch_7  = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */
+    kLPTMR_Prescale_Glitch_8  = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */
+    kLPTMR_Prescale_Glitch_9  = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/
+    kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
+    kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
+    kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
+    kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
+    kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
+    kLPTMR_Prescale_Glitch_15 = 0xFU  /*!< Prescaler divide 65536, glitch filter 32768 */
+} lptmr_prescaler_glitch_value_t;
+
+/*!
+ * @brief LPTMR prescaler/glitch filter clock select.
+ * @note Clock connections are SoC-specific
+ */
+typedef enum _lptmr_prescaler_clock_select
+{
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
+    kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+#endif
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
+    kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
+#endif                              /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
+    kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+#endif
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
+    kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
+#endif                              /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT */
+} lptmr_prescaler_clock_select_t;
+
+/*! @brief List of the LPTMR interrupts */
+typedef enum _lptmr_interrupt_enable
+{
+    kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
+} lptmr_interrupt_enable_t;
+
+/*! @brief List of the LPTMR status flags */
+typedef enum _lptmr_status_flags
+{
+    kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
+} lptmr_status_flags_t;
+
+/*!
+ * @brief LPTMR config structure
+ *
+ * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
+ * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
+ * pointer to your configuration structure instance.
+ *
+ * The configuration struct can be made constant so it resides in flash.
+ */
+typedef struct _lptmr_config
+{
+    lptmr_timer_mode_t timerMode;     /*!< Time counter mode or pulse counter mode */
+    lptmr_pin_select_t pinSelect;     /*!< LPTMR pulse input pin select; used only in pulse counter mode */
+    lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
+    bool enableFreeRunning;           /*!< True: enable free running, counter is reset on overflow
+                                           False: counter is reset when the compare flag is set */
+    bool bypassPrescaler;             /*!< True: bypass prescaler; false: use clock from prescaler */
+    lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
+    lptmr_prescaler_glitch_value_t value;                /*!< Prescaler or glitch filter value */
+} lptmr_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the LPTMR driver.
+ *
+ * @param base   LPTMR peripheral base address
+ * @param config A pointer to the LPTMR configuration structure.
+ */
+void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
+
+/*!
+ * @brief Gates the LPTMR clock.
+ *
+ * @param base LPTMR peripheral base address
+ */
+void LPTMR_Deinit(LPTMR_Type *base);
+
+/*!
+ * @brief Fills in the LPTMR configuration structure with default settings.
+ *
+ * The default values are as follows.
+ * @code
+ *    config->timerMode = kLPTMR_TimerModeTimeCounter;
+ *    config->pinSelect = kLPTMR_PinSelectInput_0;
+ *    config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
+ *    config->enableFreeRunning = false;
+ *    config->bypassPrescaler = true;
+ *    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
+ *    config->value = kLPTMR_Prescale_Glitch_0;
+ * @endcode
+ * @param config A pointer to the LPTMR configuration structure.
+ */
+void LPTMR_GetDefaultConfig(lptmr_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::lptmr_interrupt_enable_t
+ */
+static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= mask;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Disables the selected LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The interrupts to disable. This is a logical OR of members of the
+ *             enumeration ::lptmr_interrupt_enable_t.
+ */
+static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~mask;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Gets the enabled LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::lptmr_interrupt_enable_t
+ */
+static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
+{
+    return (base->CSR & LPTMR_CSR_TIE_MASK);
+}
+
+/*! @}*/
+
+#if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE)
+/*!
+ * @brief Enable or disable timer DMA request
+ *
+ * @param base base LPTMR peripheral base address
+ * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable.
+ */
+static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CSR |= LPTMR_CSR_TDRE_MASK;
+    }
+    else
+    {
+        base->CSR &= ~(LPTMR_CSR_TDRE_MASK);
+    }
+}
+#endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the LPTMR status flags.
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::lptmr_status_flags_t
+ */
+static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
+{
+    return (base->CSR & LPTMR_CSR_TCF_MASK);
+}
+
+/*!
+ * @brief  Clears the LPTMR status flags.
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::lptmr_status_flags_t.
+ */
+static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
+{
+    base->CSR |= mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the CMR register.
+ *
+ * @note
+ * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
+ * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
+ *
+ * @param base  LPTMR peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
+{
+    assert(ticks > 0U);
+    base->CMR = LPTMR_CMR_COMPARE(ticks - 1U);
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
+{
+    /* Must first write any value to the CNR. This synchronizes and registers the current value
+     * of the CNR into a temporary register which can then be read
+     */
+    base->CNR = 0U;
+    return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer.
+ *
+ * After calling this function, the timer counts up to the CMR register value.
+ * Each time the timer reaches the CMR value and then increments, it generates a
+ * trigger pulse and sets the timeout interrupt flag. An interrupt is also
+ * triggered if the timer interrupt is enabled.
+ *
+ * @param base LPTMR peripheral base address
+ */
+static inline void LPTMR_StartTimer(LPTMR_Type *base)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Stops the timer.
+ *
+ * This function stops the timer and resets the timer's counter register.
+ *
+ * @param base LPTMR peripheral base address
+ */
+static inline void LPTMR_StopTimer(LPTMR_Type *base)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_LPTMR_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.c
new file mode 100644
index 0000000000..5e8de5a894
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.c
@@ -0,0 +1,2742 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lpuart.h"
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification fsl_lpuart_c_ref_1$
+ * (osr > 3) (false) can't be not covered, because osr(osrTemp) is increased from 4U.
+ *
+ * $Justification fsl_lpuart_c_ref_2$
+ * The flag is cleared successfully during test.
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpuart"
+#endif
+
+/* LPUART transfer state. */
+enum
+{
+    kLPUART_TxIdle, /*!< TX idle. */
+    kLPUART_TxBusy, /*!< TX busy. */
+    kLPUART_RxIdle, /*!< RX idle. */
+    kLPUART_RxBusy  /*!< RX busy. */
+};
+
+#if defined(LPUART_RSTS)
+#define LPUART_RESETS_ARRAY LPUART_RSTS
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @userData handle LPUART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+/*!
+ * @brief Write to TX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * The 10bit of data will be writen to TX register DATA.
+ * Please make sure data 10bit is valid and other bit is 0.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+/*!
+ * @brief Read RX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * This function reads 10bit data from the RX register directly and stores to 16bit data.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
+/*!
+ * @brief LPUART_TransferHandleIDLEIsReady handle function.
+ * This function handles when IDLE is ready.
+ *
+ * @param base LPUART peripheral base address.
+ * @param irqHandle LPUART handle pointer.
+ */
+static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART_TransferHandleReceiveDataIsFull handle function.
+ * This function handles when receive data is full.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART_TransferHandleSendDataIsEmpty handle function.
+ * This function handles when send data is empty.
+ *
+ * @param base LPUART peripheral base address.
+ * @param irqHandle LPUART handle pointer.
+ */
+static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART_TransferHandleTransmissionIsComplete handle function.
+ * This function handles Transmission complete and the interrupt is enabled.
+ *
+ * @param base LPUART peripheral base address.
+ * @param irqHandle LPUART handle pointer.
+ */
+static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(LPUART_BASE_PTRS_NS)
+static LPUART_Type *const s_lpuartBases_ns[] = LPUART_BASE_PTRS_NS;
+#endif
+/* Array of LPUART peripheral base address. */
+static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
+/* Array of LPUART handle. */
+void *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)];
+/* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
+const IRQn_Type s_lpuartTxIRQ[]        = LPUART_TX_IRQS;
+#else
+const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of LPUART clock name. */
+static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
+
+#if defined(LPUART_PERIPH_CLOCKS)
+/* Array of LPUART functional clock name. */
+static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* LPUART ISR for transactional APIs. */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)] = {[0 ...(ARRAY_SIZE(s_lpuartBases) - 1)] =
+                                                           (lpuart_isr_t)DefaultISR};
+#else
+lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)];
+#endif
+
+#if defined(LPUART_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_lpuartResets[] = LPUART_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Get the LPUART instance from peripheral base address.
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART instance.
+ */
+uint32_t LPUART_GetInstance(LPUART_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++)
+    {
+        if (s_lpuartBases[instance] == base)
+        {
+            return instance;
+        }
+    }
+#if defined(LPUART_BASE_PTRS_NS)
+    /* Find the instance index from base address mappings. */
+    for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases_ns); instance++)
+    {
+        if (s_lpuartBases_ns[instance] == base)
+        {
+            return instance;
+        }
+    }
+    assert(instance < ARRAY_SIZE(s_lpuartBases_ns));
+#else
+    assert(instance < ARRAY_SIZE(s_lpuartBases));
+#endif
+
+    return instance;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * userData handle LPUART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    size_t size;
+    size_t tmpRxRingBufferSize   = handle->rxRingBufferSize;
+    uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail;
+    uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead;
+
+    if (tmpRxRingBufferTail > tmpRxRingBufferHead)
+    {
+        size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail);
+    }
+    else
+    {
+        size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail);
+    }
+
+    return size;
+}
+
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    bool full;
+
+    if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
+
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl        = base->CTRL;
+    bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
+                            (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
+#endif
+
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            data[i] = (uint8_t)(base->DATA & 0x7FU);
+        }
+        else
+        {
+            data[i] = (uint8_t)base->DATA;
+        }
+#else
+        data[i] = (uint8_t)(base->DATA);
+#endif
+    }
+}
+
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        data[i] = (uint16_t)(base->DATA & 0x03FFU);
+    }
+}
+
+/*!
+ * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param config Pointer to a user-defined configuration structure.
+ * param srcClock_Hz LPUART clock source frequency in HZ.
+ * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(NULL != config);
+    assert(0U < config->baudRate_Bps);
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark);
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark);
+#endif
+
+    status_t status = kStatus_Success;
+    uint32_t temp;
+    uint16_t sbr, sbrTemp;
+    uint8_t osr, osrTemp;
+    uint32_t tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = config->baudRate_Bps;
+    osr      = 0U;
+    sbr      = 0U;
+    for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0U)
+        {
+            sbrTemp = 1U;
+        }
+        else if (sbrTemp > LPUART_BAUD_SBR_MASK)
+        {
+            sbrTemp = LPUART_BAUD_SBR_MASK;
+        }
+        else
+        {
+            /* Avoid MISRA 15.7 */
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp));
+        tempDiff       = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) :
+                                                                 (config->baudRate_Bps - calculatedBaud);
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr      = osrTemp; /* update and store the best OSR value calculated */
+            sbr      = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff > ((config->baudRate_Bps / 100U) * 3U))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        status = kStatus_LPUART_BaudrateNotSupport;
+    }
+    else
+    {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+        uint32_t instance = LPUART_GetInstance(base);
+
+        /* Enable lpuart clock */
+        (void)CLOCK_EnableClock(s_lpuartClock[instance]);
+#if defined(LPUART_PERIPH_CLOCKS)
+        (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(LPUART_RESETS_ARRAY)
+        RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+        /*Reset all internal logic and registers, except the Global Register */
+        LPUART_SoftwareReset(base);
+#else
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+#endif
+
+        temp = base->BAUD;
+
+        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+         * If so, then "BOTHEDGE" sampling must be turned on */
+        /*
+         * $Branch Coverage Justification$
+         * $ref fsl_lpuart_c_ref_1$
+         */
+        if ((osr > 3U) && (osr < 8U))
+        {
+            temp |= LPUART_BAUD_BOTHEDGE_MASK;
+        }
+
+        /* program the osr value (bit value is one less than actual value) */
+        temp &= ~LPUART_BAUD_OSR_MASK;
+        temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL);
+
+        /* write the sbr value to the BAUD registers */
+        temp &= ~LPUART_BAUD_SBR_MASK;
+        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+        /* Set bit count and parity mode. */
+        base->BAUD &= ~LPUART_BAUD_M10_MASK;
+
+        temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
+                              LPUART_CTRL_IDLECFG_MASK);
+
+        temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) |
+                LPUART_CTRL_ILT(config->rxIdleType);
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (kLPUART_SevenDataBits == config->dataBitsCount)
+        {
+            if (kLPUART_ParityDisabled != config->parityMode)
+            {
+                temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
+            }
+            else
+            {
+                temp |= LPUART_CTRL_M7_MASK;
+            }
+        }
+        else
+#endif
+        {
+            if (kLPUART_ParityDisabled != config->parityMode)
+            {
+                temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
+            }
+        }
+
+        base->CTRL = temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+        /* set stop bit per char */
+        temp       = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
+        base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        /* Set tx/rx WATER watermark
+           Note:
+           Take care of the RX FIFO, RX interrupt request only assert when received bytes
+           equal or more than RX water mark, there is potential issue if RX water
+           mark larger than 1.
+           For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+           5 bytes are received. the last byte will be saved in FIFO but not trigger
+           RX interrupt because the water mark is 2.
+         */
+        base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark);
+
+        /* Enable tx/rx FIFO */
+        base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
+
+        /* Flush FIFO */
+        base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
+#endif
+
+        /* Clear all status flags */
+        temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+        temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+        temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+        /* Set the CTS configuration/TX CTS source. */
+        base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
+        if (true == config->enableRxRTS)
+        {
+            /* Enable the receiver RTS(request-to-send) function. */
+            base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
+        }
+        if (true == config->enableTxCTS)
+        {
+            /* Enable the CTS(clear-to-send) function. */
+            base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
+        }
+#endif
+
+        /* Set data bits order. */
+        if (true == config->isMsb)
+        {
+            temp |= LPUART_STAT_MSBF_MASK;
+        }
+        else
+        {
+            temp &= ~LPUART_STAT_MSBF_MASK;
+        }
+
+        base->STAT |= temp;
+
+        /* Enable TX/RX base on configure structure. */
+        temp = base->CTRL;
+        if (true == config->enableTx)
+        {
+            temp |= LPUART_CTRL_TE_MASK;
+        }
+
+        if (true == config->enableRx)
+        {
+            temp |= LPUART_CTRL_RE_MASK;
+        }
+
+        base->CTRL = temp;
+    }
+
+    return status;
+}
+/*!
+ * brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * param base LPUART peripheral base address.
+ */
+void LPUART_Deinit(LPUART_Type *base)
+{
+    uint32_t temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Wait tx FIFO send out*/
+    while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
+    {
+    }
+#endif
+    /* Wait last char shift out */
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
+    {
+    }
+
+    /* Clear all status flags */
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+            LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+    base->STAT |= temp;
+
+    /* Disable the module. */
+    base->CTRL = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = LPUART_GetInstance(base);
+
+    /* Disable lpuart clock */
+    (void)CLOCK_DisableClock(s_lpuartClock[instance]);
+
+#if defined(LPUART_PERIPH_CLOCKS)
+    (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
+ *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * param config Pointer to a configuration structure.
+ */
+void LPUART_GetDefaultConfig(lpuart_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->baudRate_Bps  = 115200U;
+    config->parityMode    = kLPUART_ParityDisabled;
+    config->dataBitsCount = kLPUART_EightDataBits;
+    config->isMsb         = false;
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    config->stopBitCount = kLPUART_OneStopBit;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    config->txFifoWatermark = 0U;
+    config->rxFifoWatermark = 0U;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    config->enableRxRTS = false;
+    config->enableTxCTS = false;
+    config->txCtsConfig = kLPUART_CtsSampleAtStart;
+    config->txCtsSource = kLPUART_CtsSourcePin;
+#endif
+    config->rxIdleType   = kLPUART_IdleTypeStartBit;
+    config->rxIdleConfig = kLPUART_IdleCharacter1;
+    config->enableTx     = false;
+    config->enableRx     = false;
+}
+
+/*!
+ * brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param baudRate_Bps LPUART baudrate to be set.
+ * param srcClock_Hz LPUART clock source frequency in HZ.
+ * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * retval kStatus_Success Set baudrate succeeded.
+ */
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    assert(0U < baudRate_Bps);
+
+    status_t status = kStatus_Success;
+    uint32_t temp, oldCtrl;
+    uint16_t sbr, sbrTemp;
+    uint8_t osr, osrTemp;
+    uint32_t tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = baudRate_Bps;
+    osr      = 0U;
+    sbr      = 0U;
+    for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0U)
+        {
+            sbrTemp = 1U;
+        }
+        else if (sbrTemp > LPUART_BAUD_SBR_MASK)
+        {
+            sbrTemp = LPUART_BAUD_SBR_MASK;
+        }
+        else
+        {
+            /* Avoid MISRA 15.7 */
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp);
+
+        tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud);
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr      = osrTemp; /* update and store the best OSR value calculated */
+            sbr      = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U))
+    {
+        /* Store CTRL before disable Tx and Rx */
+        oldCtrl = base->CTRL;
+
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
+        temp = base->BAUD;
+
+        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+         * If so, then "BOTHEDGE" sampling must be turned on */
+        /*
+         * $Branch Coverage Justification$
+         * $ref fsl_lpuart_c_ref_1$
+         */
+        if ((osr > 3U) && (osr < 8U))
+        {
+            temp |= LPUART_BAUD_BOTHEDGE_MASK;
+        }
+
+        /* program the osr value (bit value is one less than actual value) */
+        temp &= ~LPUART_BAUD_OSR_MASK;
+        temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL);
+
+        /* write the sbr value to the BAUD registers */
+        temp &= ~LPUART_BAUD_SBR_MASK;
+        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+        /* Restore CTRL. */
+        base->CTRL = oldCtrl;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        status = kStatus_LPUART_BaudrateNotSupport;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enable 9-bit data mode for LPUART.
+ *
+ * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base LPUART peripheral base address.
+ * param enable true to enable, flase to disable.
+ */
+void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)
+{
+    assert(base != NULL);
+
+    uint32_t temp = 0U;
+
+    if (enable)
+    {
+        /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */
+        temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK);
+        temp |= (uint32_t)LPUART_CTRL_M_MASK;
+        base->CTRL = temp;
+    }
+    else
+    {
+        /* Clear LPUART_CTRL_M. */
+        base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK;
+    }
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */
+    base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT
+    /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */
+    base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK;
+#endif
+}
+
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base LPUART peripheral base address.
+ * param address LPUART slave address.
+ */
+void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
+{
+    assert(base != NULL);
+
+    uint32_t temp = base->DATA & 0xFFFFFC00UL;
+    temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT));
+    base->DATA = temp;
+}
+
+/*!
+ * brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable.
+ */
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    uint32_t s_atomicOldInt;
+    /* Only consider the real interrupt enable bits. */
+    mask &= (uint32_t)kLPUART_AllInterruptEnable;
+
+    /* Check int enable bits in base->BAUD */
+    uint32_t baudRegMask = 0UL;
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    /* Clear bit 7 from mask */
+    mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
+#endif
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    /* Clear bit 6 from mask */
+    mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD |= baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Check int enable bits in base->FIFO */
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+                 (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
+
+    /* Clear bit 9 and bit 8 from mask */
+    mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
+#endif
+
+    /* Set int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->CTRL |= mask;
+    EnableGlobalIRQ(s_atomicOldInt);
+}
+
+/*!
+ * brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable.
+ */
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    uint32_t s_atomicOldInt;
+    /* Only consider the real interrupt enable bits. */
+    mask &= (uint32_t)kLPUART_AllInterruptEnable;
+
+    /* Clear int enable bits in base->BAUD */
+    uint32_t baudRegMask = 0UL;
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    /* Clear bit 7 from mask */
+    mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
+#endif
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    /* Clear bit 6 from mask */
+    mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD &= ~baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Clear int enable bits in base->FIFO */
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+                 ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
+    /* Clear bit 9 and bit 8 from mask */
+    mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
+#endif
+
+    /* Clear int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->CTRL &= ~mask;
+    EnableGlobalIRQ(s_atomicOldInt);
+}
+
+/*!
+ * brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable.
+ */
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
+{
+    /* Check int enable bits in base->CTRL */
+    uint32_t temp = (uint32_t)(base->CTRL & (uint32_t)kLPUART_AllInterruptEnable);
+
+    /* Check int enable bits in base->BAUD */
+    temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U);
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Check int enable bits in base->FIFO */
+    temp =
+        (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) |
+        (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+#endif
+
+    return temp;
+}
+
+/*!
+ * brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
+{
+    uint32_t temp;
+    temp = base->STAT;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp |= (base->FIFO &
+             (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
+            16U;
+#endif
+    /* Only keeps the status bits */
+    temp &= (uint32_t)kLPUART_AllFlags;
+    return temp;
+}
+
+/*!
+ * brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * param base LPUART peripheral base address.
+ * param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * return 0 succeed, others failed.
+ * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * retval kStatus_Success Status in the mask are cleared.
+ */
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
+{
+    uint32_t temp;
+    status_t status;
+
+    /* Only deal with the clearable flags */
+    mask &= (uint32_t)kLPUART_AllClearFlags;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Status bits in FIFO register */
+    if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U)
+    {
+        /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case
+           they are written 1 accidentally. */
+        temp = (uint32_t)base->FIFO;
+        temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK |
+                             LPUART_FIFO_RXUF_MASK));
+        temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
+        base->FIFO = temp;
+    }
+#endif
+    /* Status bits in STAT register */
+    /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit
+     * that is to be W1C */
+    temp       = (base->STAT & 0x3E000000UL) | mask;
+    base->STAT = temp;
+    /* If some flags still pending. */
+    if (0U != (mask & LPUART_GetStatusFlags(base)))
+    {
+        status = kStatus_LPUART_FlagCannotClearManually;
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Writes to the transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room,
+ * and writes data to the transmitter buffer, then waits for the data to be sent out to bus.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    const uint8_t *dataAddress = data;
+    size_t transferSize        = length;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != transferSize)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes))
+#else
+        while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_LPUART_Timeout;
+        }
+#endif
+        base->DATA = *(dataAddress);
+        dataAddress++;
+        transferSize--;
+    }
+    /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes))
+#else
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_LPUART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+/*!
+ * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    const uint16_t *dataAddress = data;
+    size_t transferSize         = length;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != transferSize)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes))
+#else
+        while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_LPUART_Timeout;
+        }
+#endif
+        base->DATA = *(dataAddress);
+        dataAddress++;
+        transferSize--;
+    }
+    /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes))
+#else
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_LPUART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * brief Reads the receiver data register using a blocking method.
+ *
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    status_t status = kStatus_Success;
+    uint32_t statusFlag;
+    uint8_t *dataAddress = data;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl        = base->CTRL;
+    bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
+                            (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
+#endif
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != (length--))
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+#if UART_RETRY_TIMES
+            if (0U == --waitTimes)
+            {
+                status = kStatus_LPUART_Timeout;
+                break;
+            }
+#endif
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
+                              (kStatus_LPUART_RxHardwareOverrun) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+                /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
+                 * error flags*/
+                break;
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
+                              (kStatus_LPUART_ParityError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
+                              (kStatus_LPUART_FramingError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
+                              (kStatus_LPUART_NoiseError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+            if (kStatus_Success != status)
+            {
+                break;
+            }
+        }
+
+        if (kStatus_Success == status)
+        {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+            if (isSevenDataBits)
+            {
+                *(dataAddress) = (uint8_t)(base->DATA & 0x7FU);
+                dataAddress++;
+            }
+            else
+            {
+                *(dataAddress) = (uint8_t)base->DATA;
+                dataAddress++;
+            }
+#else
+            *(dataAddress) = (uint8_t)base->DATA;
+            dataAddress++;
+#endif
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+/*!
+ * brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * param length Size of the buffer.
+ * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    status_t status = kStatus_Success;
+    uint32_t statusFlag;
+    uint16_t *dataAddress = data;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != (length--))
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+#if UART_RETRY_TIMES
+            if (0U == --waitTimes)
+            {
+                status = kStatus_LPUART_Timeout;
+                break;
+            }
+#endif
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
+                              (kStatus_LPUART_RxHardwareOverrun) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+                /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
+                 * error flags*/
+                break;
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
+                              (kStatus_LPUART_ParityError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
+                              (kStatus_LPUART_FramingError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
+                              (kStatus_LPUART_NoiseError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+            if (kStatus_Success != status)
+            {
+                break;
+            }
+        }
+        if (kStatus_Success == status)
+        {
+            *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU);
+            dataAddress++;
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+/*!
+ * brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as p ringBuffer.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param callback Callback function.
+ * param userData User data.
+ */
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData)
+{
+    assert(NULL != handle);
+
+    uint32_t instance;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl        = base->CTRL;
+    bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
+                            (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
+#endif
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(lpuart_handle_t));
+
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
+    handle->txState = (uint8_t)kLPUART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Initial seven data bits flag */
+    handle->isSevenDataBits = isSevenDataBits;
+#endif
+    handle->is16bitData = false;
+
+    /* Get instance from peripheral base address. */
+    instance = LPUART_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_lpuartHandle[instance] = handle;
+
+    s_lpuartIsr[instance] = LPUART_TransferHandleIRQ;
+
+/* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    (void)EnableIRQ(s_lpuartRxIRQ[instance]);
+    (void)EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
+    (void)EnableIRQ(s_lpuartIRQ[instance]);
+#endif
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize)
+{
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ring buffer address */
+    handle->rxRingBuffer = ringBuffer;
+    if (!handle->is16bitData)
+    {
+        handle->rxRingBufferSize = ringBufferSize;
+    }
+    else
+    {
+        handle->rxRingBufferSize = ringBufferSize / 2U;
+    }
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+
+    /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
+    uint32_t irqMask = DisableGlobalIRQ();
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
+    EnableGlobalIRQ(irqMask);
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    if (handle->rxState == (uint8_t)kLPUART_RxIdle)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
+        EnableGlobalIRQ(irqMask);
+    }
+
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(NULL != handle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->txData);
+    assert(0U != xfer->dataSize);
+
+    status_t status;
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kLPUART_TxBusy == handle->txState)
+    {
+        status = kStatus_LPUART_TxBusy;
+    }
+    else
+    {
+        if (!handle->is16bitData)
+        {
+            handle->txData = xfer->txData;
+        }
+        else
+        {
+            handle->txData16 = xfer->txData16;
+        }
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = (uint8_t)kLPUART_TxBusy;
+
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        /* Enable transmitter interrupt. */
+        base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK;
+        EnableGlobalIRQ(irqMask);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
+    uint32_t irqMask = DisableGlobalIRQ();
+    base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK);
+    EnableGlobalIRQ(irqMask);
+
+    handle->txDataSize = 0;
+    handle->txState    = (uint8_t)kLPUART_TxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by an interrupt method.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    status_t status      = kStatus_Success;
+    size_t tmptxDataSize = handle->txDataSize;
+
+    if ((uint8_t)kLPUART_TxIdle == handle->txState)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        *count = handle->txDataSizeAll - tmptxDataSize -
+                 ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+#else
+        if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U)
+        {
+            *count = handle->txDataSizeAll - tmptxDataSize;
+        }
+        else
+        {
+            *count = handle->txDataSizeAll - tmptxDataSize - 1U;
+        }
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART transfer structure, see #uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes)
+{
+    assert(NULL != handle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->rxData);
+    assert(0U != xfer->dataSize);
+
+    uint32_t i;
+    status_t status;
+    uint32_t irqMask;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to lpuart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to lpuart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if ((uint8_t)kLPUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_LPUART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0;
+
+        /* If RX ring buffer is used. */
+        if (NULL != handle->rxRingBuffer)
+        {
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Disable LPUART RX IRQ, protect ring buffer. */
+            base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
+            EnableGlobalIRQ(irqMask);
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
+
+            if (0U != bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    if (!handle->is16bitData)
+                    {
+                        xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    }
+                    else
+                    {
+                        xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail];
+                    }
+                    bytesCurrentReceived++;
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (0U != bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to LPUART handle. */
+
+                if (!handle->is16bitData)
+                {
+                    handle->rxData = &xfer->rxData[bytesCurrentReceived];
+                }
+                else
+                {
+                    handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+                }
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = xfer->dataSize;
+                handle->rxState       = (uint8_t)kLPUART_RxBusy;
+            }
+
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Re-enable LPUART RX IRQ. */
+            base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
+            EnableGlobalIRQ(irqMask);
+
+            /* Call user callback since all data are received. */
+            if (0U == bytesToReceive)
+            {
+                if (NULL != handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            if (!handle->is16bitData)
+            {
+                handle->rxData = &xfer->rxData[bytesCurrentReceived];
+            }
+            else
+            {
+                handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+            }
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = (uint8_t)kLPUART_RxBusy;
+
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Enable RX interrupt. */
+            base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
+            EnableGlobalIRQ(irqMask);
+        }
+
+        /* Return the how many bytes have read. */
+        if (NULL != receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        /* Disable RX interrupt. */
+        base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
+        EnableGlobalIRQ(irqMask);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kLPUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    status_t status      = kStatus_Success;
+    size_t tmprxDataSize = handle->rxDataSize;
+
+    if ((uint8_t)kLPUART_RxIdle == handle->rxState)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->rxDataSizeAll - tmprxDataSize;
+    }
+
+    return status;
+}
+
+static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    uint32_t irqMask;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    uint8_t count;
+    uint8_t tempCount;
+    count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
+
+    while ((0U != handle->rxDataSize) && (0U != count))
+    {
+        tempCount = (uint8_t)MIN(handle->rxDataSize, count);
+        /* Using non block API to read the data from the registers. */
+        if (!handle->is16bitData)
+        {
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData = &handle->rxData[tempCount];
+        }
+        else
+        {
+            LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+            handle->rxData16 = &handle->rxData16[tempCount];
+        }
+        handle->rxDataSize -= tempCount;
+        count -= tempCount;
+
+        /* If rxDataSize is 0, invoke rx idle callback.*/
+        if (0U == (handle->rxDataSize))
+        {
+            handle->rxState = (uint8_t)kLPUART_RxIdle;
+
+            if (NULL != handle->callback)
+            {
+                handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+            }
+        }
+    }
+#endif
+    /* Clear IDLE flag.*/
+    base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK);
+
+    /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/
+    if (0U == handle->rxDataSize)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+         * read-modify-wrte. */
+        irqMask = DisableGlobalIRQ();
+        base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
+        EnableGlobalIRQ(irqMask);
+    }
+    /* Invoke callback if callback is not NULL and rxDataSize is not 0. */
+    else if (NULL != handle->callback)
+    {
+        handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
+    }
+    else
+    {
+        /* Avoid MISRA 15.7 */
+    }
+}
+
+static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    uint8_t count;
+    uint8_t tempCount;
+    uint16_t tpmRxRingBufferHead;
+    uint32_t tpmData;
+    uint32_t irqMask;
+
+    /* Get the size that can be stored into buffer for this interrupt. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
+#else
+    count = 1;
+#endif
+
+    /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+    while ((0U != handle->rxDataSize) && (0U != count))
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        tempCount = (uint8_t)MIN(handle->rxDataSize, count);
+#else
+        tempCount = 1;
+#endif
+
+        /* Using non block API to read the data from the registers. */
+        if (!handle->is16bitData)
+        {
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData = &handle->rxData[tempCount];
+        }
+        else
+        {
+            LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+            handle->rxData16 = &handle->rxData16[tempCount];
+        }
+        handle->rxDataSize -= tempCount;
+        count -= tempCount;
+
+        /* If all the data required for upper layer is ready, trigger callback. */
+        if (0U == handle->rxDataSize)
+        {
+            handle->rxState = (uint8_t)kLPUART_RxIdle;
+
+            if (NULL != handle->callback)
+            {
+                handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+            }
+        }
+    }
+
+    /* If use RX ring buffer, receive data to ring buffer. */
+    if (NULL != handle->rxRingBuffer)
+    {
+        while (0U != count--)
+        {
+            /* If RX ring buffer is full, trigger callback to notify over run. */
+            if (LPUART_TransferIsRxRingBufferFull(base, handle))
+            {
+                if (NULL != handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
+                }
+            }
+
+            /* If ring buffer is still full after callback function, the oldest data is overridden. */
+            if (LPUART_TransferIsRxRingBufferFull(base, handle))
+            {
+                /* Increase handle->rxRingBufferTail to make room for new data. */
+                if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferTail = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferTail++;
+                }
+            }
+
+            /* Read data. */
+            tpmRxRingBufferHead = handle->rxRingBufferHead;
+            tpmData             = base->DATA;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+            if (handle->isSevenDataBits)
+            {
+                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU);
+            }
+            else
+            {
+                if (!handle->is16bitData)
+                {
+                    handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                }
+                else
+                {
+                    handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+                }
+            }
+#else
+            if (!handle->is16bitData)
+            {
+                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+            }
+            else
+            {
+                handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+            }
+#endif
+
+            /* Increase handle->rxRingBufferHead. */
+            if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize)
+            {
+                handle->rxRingBufferHead = 0U;
+            }
+            else
+            {
+                handle->rxRingBufferHead++;
+            }
+        }
+    }
+    /* If no receive requst pending, stop RX interrupt. */
+    else if (0U == handle->rxDataSize)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+         * read-modify-wrte. */
+        irqMask = DisableGlobalIRQ();
+        base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK);
+        EnableGlobalIRQ(irqMask);
+    }
+    else
+    {
+        /* Avoid MISRA C-2012 15.7 voiation */
+        return;
+    }
+}
+
+static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    uint8_t count;
+    uint8_t tempCount;
+    uint32_t irqMask;
+/* Get the bytes that available at this moment. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
+            (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+#else
+    count = 1;
+#endif
+
+    while ((0U != handle->txDataSize) && (0U != count))
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        tempCount = (uint8_t)MIN(handle->txDataSize, count);
+#else
+        tempCount = 1;
+#endif
+
+        /* Using non block API to write the data to the registers. */
+        if (!handle->is16bitData)
+        {
+            LPUART_WriteNonBlocking(base, handle->txData, tempCount);
+            handle->txData = &handle->txData[tempCount];
+        }
+        else
+        {
+            LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount);
+            handle->txData16 = &handle->txData16[tempCount];
+        }
+        handle->txDataSize -= tempCount;
+        count -= tempCount;
+
+        /* If all the data are written to data register, notify user with the callback, then TX finished. */
+        if (0U == handle->txDataSize)
+        {
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Disable TX register empty interrupt and enable transmission completion interrupt. */
+            base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK;
+            EnableGlobalIRQ(irqMask);
+        }
+    }
+}
+
+static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    uint32_t irqMask;
+    /* Set txState to idle only when all data has been sent out to bus. */
+    handle->txState = (uint8_t)kLPUART_TxIdle;
+
+    /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+     */
+    irqMask = DisableGlobalIRQ();
+    /* Disable transmission complete interrupt. */
+    base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK;
+    EnableGlobalIRQ(irqMask);
+
+    /* Trigger callback. */
+    if (NULL != handle->callback)
+    {
+        handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
+    }
+}
+
+/*!
+ * brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * param base LPUART peripheral base address.
+ * param irqHandle LPUART handle pointer.
+ */
+void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)
+{
+    assert(NULL != irqHandle);
+
+    uint32_t status            = LPUART_GetStatusFlags(base);
+    uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base);
+
+    lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle;
+
+    /* If RX overrun. */
+    if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status))
+    {
+        /* Clear overrun flag, otherwise the RX does not work. */
+        base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
+
+        /* Trigger callback. */
+        if (NULL != (handle->callback))
+        {
+            handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* If IDLE flag is set and the IDLE interrupt is enabled. */
+    if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts)))
+    {
+        LPUART_TransferHandleIDLEReady(base, handle);
+    }
+    /* Receive data register full */
+    if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts)))
+    {
+        LPUART_TransferHandleReceiveDataFull(base, handle);
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)))
+    {
+        LPUART_TransferHandleSendDataEmpty(base, handle);
+    }
+
+    /* Transmission complete and the interrupt is enabled. */
+    if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts)))
+    {
+        LPUART_TransferHandleTransmissionComplete(base, handle);
+    }
+}
+
+/*!
+ * brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * param base LPUART peripheral base address.
+ * param irqHandle LPUART handle pointer.
+ */
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)
+{
+    /* To be implemented by User. */
+}
+#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_LPUART1_RX_DriverIRQHandler(void);
+void LPUART0_LPUART1_RX_DriverIRQHandler(void)
+{
+    /* If handle is registered, treat the transfer function is enabled. */
+    if (NULL != s_lpuartHandle[0])
+    {
+        s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    }
+    if (NULL != s_lpuartHandle[1])
+    {
+        s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART0_LPUART1_TX_DriverIRQHandler(void);
+void LPUART0_LPUART1_TX_DriverIRQHandler(void)
+{
+    /* If handle is registered, treat the transfer function is enabled. */
+    if (NULL != s_lpuartHandle[0])
+    {
+        s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    }
+    if (NULL != s_lpuartHandle[1])
+    {
+        s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART0_LPUART1_DriverIRQHandler(void);
+void LPUART0_LPUART1_DriverIRQHandler(void)
+{
+    /* If handle is registered, treat the transfer function is enabled. */
+    if (NULL != s_lpuartHandle[0])
+    {
+        s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    }
+    if (NULL != s_lpuartHandle[1])
+    {
+        s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART0)
+#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_TX_DriverIRQHandler(void);
+void LPUART0_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART0_RX_DriverIRQHandler(void);
+void LPUART0_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART0_DriverIRQHandler(void);
+void LPUART0_DriverIRQHandler(void)
+{
+    s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+#endif
+
+#if defined(LPUART1)
+#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART1_TX_DriverIRQHandler(void);
+void LPUART1_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART1_RX_DriverIRQHandler(void);
+void LPUART1_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART1_DriverIRQHandler(void);
+void LPUART1_DriverIRQHandler(void)
+{
+    s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+#endif
+
+#if defined(LPUART2)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART2_TX_DriverIRQHandler(void);
+void LPUART2_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART2_RX_DriverIRQHandler(void);
+void LPUART2_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART2_DriverIRQHandler(void);
+void LPUART2_DriverIRQHandler(void)
+{
+    s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART3)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART3_TX_DriverIRQHandler(void);
+void LPUART3_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART3_RX_DriverIRQHandler(void);
+void LPUART3_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART3_DriverIRQHandler(void);
+void LPUART3_DriverIRQHandler(void)
+{
+    s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART4)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART4_TX_DriverIRQHandler(void);
+void LPUART4_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART4_RX_DriverIRQHandler(void);
+void LPUART4_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART4_DriverIRQHandler(void);
+void LPUART4_DriverIRQHandler(void)
+{
+    s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART5)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART5_TX_DriverIRQHandler(void);
+void LPUART5_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART5_RX_DriverIRQHandler(void);
+void LPUART5_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART5_DriverIRQHandler(void);
+void LPUART5_DriverIRQHandler(void)
+{
+    s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART6)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART6_TX_DriverIRQHandler(void);
+void LPUART6_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART6_RX_DriverIRQHandler(void);
+void LPUART6_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART6_DriverIRQHandler(void);
+void LPUART6_DriverIRQHandler(void)
+{
+    s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART7)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART7_TX_DriverIRQHandler(void);
+void LPUART7_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART7_RX_DriverIRQHandler(void);
+void LPUART7_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART7_DriverIRQHandler(void);
+void LPUART7_DriverIRQHandler(void)
+{
+    s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART8)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART8_TX_DriverIRQHandler(void);
+void LPUART8_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART8_RX_DriverIRQHandler(void);
+void LPUART8_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART8_DriverIRQHandler(void);
+void LPUART8_DriverIRQHandler(void)
+{
+    s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART9)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART9_TX_DriverIRQHandler(void);
+void LPUART9_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART9_RX_DriverIRQHandler(void);
+void LPUART9_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART9_DriverIRQHandler(void);
+void LPUART9_DriverIRQHandler(void)
+{
+    s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART10)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART10_TX_DriverIRQHandler(void);
+void LPUART10_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART10_RX_DriverIRQHandler(void);
+void LPUART10_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART10_DriverIRQHandler(void);
+void LPUART10_DriverIRQHandler(void)
+{
+    s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART11)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART11_TX_DriverIRQHandler(void);
+void LPUART11_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART11_RX_DriverIRQHandler(void);
+void LPUART11_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART11_DriverIRQHandler(void);
+void LPUART11_DriverIRQHandler(void)
+{
+    s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(LPUART12)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART12_TX_DriverIRQHandler(void);
+void LPUART12_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
+    SDK_ISR_EXIT_BARRIER;
+}
+void LPUART12_RX_DriverIRQHandler(void);
+void LPUART12_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#else
+void LPUART12_DriverIRQHandler(void);
+void LPUART12_DriverIRQHandler(void)
+{
+    s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(CM4_0__LPUART)
+void M4_0_LPUART_DriverIRQHandler(void);
+void M4_0_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(CM4_0__LPUART)](CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CM4_1__LPUART)
+void M4_1_LPUART_DriverIRQHandler(void);
+void M4_1_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(CM4_1__LPUART)](CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CM4__LPUART)
+void M4_LPUART_DriverIRQHandler(void);
+void M4_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(CM4__LPUART)](CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(DMA__LPUART0)
+void DMA_UART0_INT_DriverIRQHandler(void);
+void DMA_UART0_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(DMA__LPUART0)](DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(DMA__LPUART1)
+void DMA_UART1_INT_DriverIRQHandler(void);
+void DMA_UART1_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(DMA__LPUART1)](DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(DMA__LPUART2)
+void DMA_UART2_INT_DriverIRQHandler(void);
+void DMA_UART2_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(DMA__LPUART2)](DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(DMA__LPUART3)
+void DMA_UART3_INT_DriverIRQHandler(void);
+void DMA_UART3_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(DMA__LPUART3)](DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(DMA__LPUART4)
+void DMA_UART4_INT_DriverIRQHandler(void);
+void DMA_UART4_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(DMA__LPUART4)](DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(ADMA__LPUART0)
+void ADMA_UART0_INT_DriverIRQHandler(void);
+void ADMA_UART0_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART0)](ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(ADMA__LPUART1)
+void ADMA_UART1_INT_DriverIRQHandler(void);
+void ADMA_UART1_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART1)](ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(ADMA__LPUART2)
+void ADMA_UART2_INT_DriverIRQHandler(void);
+void ADMA_UART2_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART2)](ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(ADMA__LPUART3)
+void ADMA_UART3_INT_DriverIRQHandler(void);
+void ADMA_UART3_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART3)](ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.h
new file mode 100644
index 0000000000..13ea2365f6
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart.h
@@ -0,0 +1,1128 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_LPUART_H_
+#define FSL_LPUART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief LPUART driver version. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 8, 2))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+#endif
+
+/*! @brief Error codes for the LPUART driver. */
+enum
+{
+    kStatus_LPUART_TxBusy                  = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
+    kStatus_LPUART_RxBusy                  = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
+    kStatus_LPUART_TxIdle                  = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle                  = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge     = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge     = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error                   = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
+    kStatus_LPUART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
+    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9),  /*!< LPUART RX receiver overrun. */
+    kStatus_LPUART_NoiseError        = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
+    kStatus_LPUART_FramingError      = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
+    kStatus_LPUART_ParityError       = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
+    kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
+    kStatus_LPUART_Timeout          = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */
+};
+
+/*! @brief LPUART parity mode. */
+typedef enum _lpuart_parity_mode
+{
+    kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kLPUART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kLPUART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
+/*! @brief LPUART stop bit count. */
+typedef enum _lpuart_stop_bit_count
+{
+    kLPUART_OneStopBit = 0U, /*!< One stop bit */
+    kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
+} lpuart_stop_bit_count_t;
+
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+/*! @brief LPUART transmit CTS source. */
+typedef enum _lpuart_transmit_cts_source
+{
+    kLPUART_CtsSourcePin         = 0U, /*!< CTS resource is the LPUART_CTS pin. */
+    kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
+} lpuart_transmit_cts_source_t;
+
+/*! @brief LPUART transmit CTS configure. */
+typedef enum _lpuart_transmit_cts_config
+{
+    kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
+    kLPUART_CtsSampleAtIdle  = 1U, /*!< CTS input is sampled when the transmitter is idle */
+} lpuart_transmit_cts_config_t;
+#endif
+
+/*! @brief LPUART idle flag type defines when the receiver starts counting. */
+typedef enum _lpuart_idle_type_select
+{
+    kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
+    kLPUART_IdleTypeStopBit  = 1U, /*!< Start counting after a stop bit. */
+} lpuart_idle_type_select_t;
+
+/*! @brief LPUART idle detected configuration.
+ *  This structure defines the number of idle characters that must be received before
+ *  the IDLE flag is set.
+ */
+typedef enum _lpuart_idle_config
+{
+    kLPUART_IdleCharacter1   = 0U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter2   = 1U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter4   = 2U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter8   = 3U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter16  = 4U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter32  = 5U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter64  = 6U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
+} lpuart_idle_config_t;
+
+/*!
+ * @brief LPUART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all LPUART interrupt configurations.
+ */
+enum _lpuart_interrupt_enable
+{
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U),              /*!< LIN break detect. bit 7 */
+#endif
+    kLPUART_RxActiveEdgeInterruptEnable         = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */
+    kLPUART_TxDataRegEmptyInterruptEnable       = (LPUART_CTRL_TIE_MASK),  /*!< Transmit data register empty. bit 23 */
+    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */
+    kLPUART_RxDataRegFullInterruptEnable        = (LPUART_CTRL_RIE_MASK),  /*!< Receiver data register full. bit 21 */
+    kLPUART_IdleLineInterruptEnable             = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */
+    kLPUART_RxOverrunInterruptEnable            = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */
+    kLPUART_NoiseErrorInterruptEnable           = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */
+    kLPUART_FramingErrorInterruptEnable         = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */
+    kLPUART_ParityErrorInterruptEnable          = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK),              /*!< Parity error flag. bit 15 */
+    kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK),              /*!< Parity error flag. bit 14 */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoOverflowInterruptEnable  = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */
+    kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */
+#endif
+
+    kLPUART_AllInterruptEnable = kLPUART_RxActiveEdgeInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable |
+                                 kLPUART_TransmissionCompleteInterruptEnable | kLPUART_RxDataRegFullInterruptEnable |
+                                 kLPUART_IdleLineInterruptEnable | kLPUART_RxOverrunInterruptEnable |
+                                 kLPUART_NoiseErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable |
+                                 kLPUART_ParityErrorInterruptEnable
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+                                 | kLPUART_LinBreakInterruptEnable
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+                                 | kLPUART_Match1InterruptEnable | kLPUART_Match2InterruptEnable
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+                                 | kLPUART_TxFifoOverflowInterruptEnable | kLPUART_RxFifoUnderflowInterruptEnable
+#endif
+    ,
+};
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the LPUART functions.
+ */
+enum _lpuart_flags
+{
+    kLPUART_TxDataRegEmptyFlag =
+        (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */
+    kLPUART_TransmissionCompleteFlag =
+        (LPUART_STAT_TC_MASK),   /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */
+    kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive
+                                                            data buffer is full. bit 21 */
+    kLPUART_IdleLineFlag  = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */
+    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),   /*!< Receive Overrun, sets when new data is received before data is
+                                                        read from receive register. bit 19 */
+    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK),  /*!< Receive takes 3 samples of each received bit.  If any of these
+                                                        samples differ, noise flag sets. bit 18 */
+    kLPUART_FramingErrorFlag =
+        (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */
+    kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK),      /*!< LIN break detect interrupt flag, sets when LIN break
+                                                              char detected and LIN circuit enabled. bit 31 */
+#endif
+    kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active
+                                                              edge detected. bit 30 */
+    kLPUART_RxActiveFlag =
+        (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLPUART_DataMatch1Flag =
+        LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */
+    kLPUART_DataMatch2Flag =
+        LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoEmptyFlag =
+        (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */
+    kLPUART_RxFifoEmptyFlag =
+        (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */
+    kLPUART_TxFifoOverflowFlag =
+        (LPUART_FIFO_TXOF_MASK >> 16),   /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */
+    kLPUART_RxFifoUnderflowFlag =
+        (LPUART_FIFO_RXUF_MASK >> 16),   /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */
+#endif
+
+    kLPUART_AllClearFlags = kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag |
+                            kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+                            | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+                            | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+                            | kLPUART_LinBreakFlag
+#endif
+    ,
+
+    kLPUART_AllFlags =
+        kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_TxDataRegEmptyFlag |
+        kLPUART_TransmissionCompleteFlag | kLPUART_RxDataRegFullFlag | kLPUART_RxActiveFlag | kLPUART_NoiseErrorFlag |
+        kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+        | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+        | kLPUART_LinBreakFlag
+#endif
+    ,
+};
+
+/*! @brief LPUART configuration structure. */
+typedef struct _lpuart_config
+{
+    uint32_t baudRate_Bps;                /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount;     /*!< Data bits count, eight (default), seven */
+    bool isMsb;                           /*!< Data bits order, LSB (default), MSB */
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    bool enableRxRTS;                         /*!< RX RTS enable */
+    bool enableTxCTS;                         /*!< TX CTS enable */
+    lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
+    lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
+#endif
+    lpuart_idle_type_select_t rxIdleType;     /*!< RX IDLE type. */
+    lpuart_idle_config_t rxIdleConfig;        /*!< RX IDLE configuration. */
+    bool enableTx;                            /*!< Enable TX */
+    bool enableRx;                            /*!< Enable RX */
+} lpuart_config_t;
+
+/*! @brief LPUART transfer structure. */
+typedef struct _lpuart_transfer
+{
+    /*
+     * Use separate TX and RX data pointer, because TX data is const data.
+     * The member data is kept for backward compatibility.
+     */
+    union
+    {
+        uint8_t *data;            /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;          /*!< The buffer to receive data. */
+        uint16_t *rxData16;       /*!< The buffer to receive data. */
+        const uint8_t *txData;    /*!< The buffer of data to be sent. */
+        const uint16_t *txData16; /*!< The buffer of data to be sent. */
+    };
+    size_t dataSize;              /*!< The byte count to be transfer. */
+} lpuart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_handle lpuart_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief LPUART handle structure. */
+struct _lpuart_handle
+{
+    union
+    {
+        const uint8_t *volatile txData;    /*!< Address of remaining data to send. */
+        const uint16_t *volatile txData16; /*!< Address of remaining data to send. */
+    };
+    volatile size_t txDataSize;            /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;                  /*!< Size of the data to send out. */
+    union
+    {
+        uint8_t *volatile rxData;    /*!< Address of remaining data to receive. */
+        uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */
+    };
+    volatile size_t rxDataSize;      /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;            /*!< Size of the data to receive. */
+
+    union
+    {
+        uint8_t *rxRingBuffer;           /*!< Start address of the receiver ring buffer. */
+        uint16_t *rxRingBuffer16;        /*!< Start address of the receiver ring buffer. */
+    };
+    size_t rxRingBufferSize;             /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead;  /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail;  /*!< Index for the user to get data from the ring buffer. */
+
+    lpuart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                      /*!< LPUART callback function parameter.*/
+
+    volatile uint8_t txState;            /*!< TX transfer state. */
+    volatile uint8_t rxState;            /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
+    bool is16bitData;     /*!< 16bit data bits flag, only used for 9bit or 10bit data */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of LPUART handle. */
+extern void *s_lpuartHandle[];
+
+/* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+extern const IRQn_Type s_lpuartTxIRQ[];
+#else
+extern const IRQn_Type s_lpuartIRQ[];
+#endif
+
+/* LPUART ISR for transactional APIs. */
+extern lpuart_isr_t s_lpuartIsr[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+
+/*!
+ * @name Software Reset
+ * @{
+ */
+
+/*!
+ * @brief Resets the LPUART using software.
+ *
+ * This function resets all internal logic and registers except the Global Register.
+ * Remains set until cleared by software.
+ *
+ * @param base LPUART peripheral base address.
+ */
+static inline void LPUART_SoftwareReset(LPUART_Type *base)
+{
+    base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+}
+/*! @} */
+#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * @code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * @param base LPUART peripheral base address.
+ */
+void LPUART_Deinit(LPUART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
+ *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void LPUART_GetDefaultConfig(lpuart_config_t *config);
+/*! @} */
+
+/*!
+ * @name Module configuration
+ * @{
+ */
+/*!
+ * @brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * @code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param baudRate_Bps LPUART baudrate to be set.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 9-bit data mode for LPUART.
+ *
+ * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable true to enable, flase to disable.
+ */
+void LPUART_Enable9bitMode(LPUART_Type *base, bool enable);
+
+/*!
+ * @brief Set the LPUART address.
+ *
+ * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address
+ * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being
+ * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one
+ * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in
+ * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with
+ * unmatched address.
+ *
+ * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the
+ * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
+ *
+ * @param base LPUART peripheral base address.
+ * @param address1 LPUART slave address1.
+ * @param address2 LPUART slave address2.
+ */
+static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)
+{
+    /* Configure match address. */
+    uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL;
+    base->MATCH      = address;
+}
+
+/*!
+ * @brief Enable the LPUART match address feature.
+ *
+ * @param base LPUART peripheral base address.
+ * @param match1 true to enable match address1, false to disable.
+ * @param match2 true to enable match address2, false to disable.
+ */
+static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)
+{
+    /* Configure match address1 enable bit. */
+    if (match1)
+    {
+        base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK;
+    }
+    /* Configure match address2 enable bit. */
+    if (match2)
+    {
+        base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+/*!
+ * @brief Sets the rx FIFO watermark.
+ *
+ * @param base LPUART peripheral base address.
+ * @param water Rx FIFO watermark.
+ */
+static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)
+{
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water);
+    base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water);
+}
+
+/*!
+ * @brief Sets the tx FIFO watermark.
+ *
+ * @param base LPUART peripheral base address.
+ * @param water Tx FIFO watermark.
+ */
+static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)
+{
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water);
+    base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water);
+}
+#endif
+
+/*!
+ * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.
+ *
+ * This function Enable 16bit Data transmit in lpuart_handle_t.
+ *
+ * @param handle LPUART handle pointer.
+ * @param enable true to enable, false to disable.
+ */
+static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)
+{
+    handle->is16bitData = enable;
+}
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
+
+/*!
+ * @brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * @return 0 succeed, others failed.
+ * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask are cleared.
+ */
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable.
+ */
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
+ */
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in @ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * @code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
+ */
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
+/*! @} */
+
+#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @name DMA Configuration
+ * @{
+ */
+/*!
+ * @brief Gets the LPUART data register address.
+ *
+ * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART data register addresses which are used both by the transmitter and receiver.
+ */
+static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
+{
+    return (uintptr_t) & (base->DATA);
+}
+
+/*!
+ * @brief Enables or disables the LPUART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_TDMAE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_RDMAE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
+    }
+}
+/*! @} */
+#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Get the LPUART instance from peripheral base address.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART instance.
+ */
+uint32_t LPUART_GetInstance(LPUART_Type *base);
+
+/*!
+ * @brief Enables or disables the LPUART transmitter.
+ *
+ * This function enables or disables the LPUART transmitter.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_TE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_TE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver.
+ *
+ * This function enables or disables the LPUART receiver.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_RE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_RE_MASK;
+    }
+}
+
+/*!
+ * @brief Writes to the transmitter register.
+ *
+ * This function writes data to the transmitter register directly. The upper layer must
+ * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Data write to the TX register.
+ */
+static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Reads the receiver register.
+ *
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the receiver register is full or that the RX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @return Data read from data register.
+ */
+static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
+{
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    uint8_t result;
+    /*
+     * $Branch Coverage Justification$
+     * (ctrl & LPUART_CTRL_M7_MASK) == 0U) false is not covered.
+     * If ctrl & LPUART_CTRL_M7_MASK is 0, it can't be !0 in next judge.
+     */
+    bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
+                            (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) &&
+                             ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
+
+    if (isSevenDataBits)
+    {
+        result = (uint8_t)(base->DATA & 0x7FU);
+    }
+    else
+    {
+        result = (uint8_t)base->DATA;
+    }
+
+    return result;
+#else
+    return (uint8_t)(base->DATA);
+#endif
+}
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+/*!
+ * @brief Gets the rx FIFO data count.
+ *
+ * @param base LPUART peripheral base address.
+ * @return rx FIFO data count.
+ */
+static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)
+{
+    return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT);
+}
+
+/*!
+ * @brief Gets the tx FIFO data count.
+ *
+ * @param base LPUART peripheral base address.
+ * @return tx FIFO data count.
+ */
+static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)
+{
+    return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+}
+#endif
+
+/*!
+ * @brief Transmit an address frame in 9-bit data mode.
+ *
+ * @param base LPUART peripheral base address.
+ * @param address LPUART slave address.
+ */
+void LPUART_SendAddress(LPUART_Type *base, uint8_t address);
+
+/*!
+ * @brief Writes to the transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room,
+ * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
+
+/*!
+ * @brief Reads the receiver data register using a blocking method.
+ *
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/*!
+ * @brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData);
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by an interrupt method.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param irqHandle LPUART handle pointer.
+ */
+void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle);
+
+/*!
+ * @brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param irqHandle LPUART handle pointer.
+ */
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_LPUART_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.c
new file mode 100644
index 0000000000..04a184df03
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_lpuart_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpuart_dma"
+#endif
+
+/*<! Structure definition for lpuart_dma_handle_t. The structure is private. */
+typedef struct _lpuart_dma_private_handle
+{
+    LPUART_Type *base;
+    lpuart_dma_handle_t *handle;
+} lpuart_dma_private_handle_t;
+
+/* LPUART DMA transfer handle. */
+enum
+{
+    kLPUART_TxIdle, /* TX idle. */
+    kLPUART_TxBusy, /* TX busy. */
+    kLPUART_RxIdle, /* RX idle. */
+    kLPUART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of LPUART handle. */
+#if (defined(LPUART12))
+#define LPUART_HANDLE_ARRAY_SIZE 13
+#else /* LPUART12 */
+#if (defined(LPUART11))
+#define LPUART_HANDLE_ARRAY_SIZE 12
+#else /* LPUART11 */
+#if (defined(LPUART10))
+#define LPUART_HANDLE_ARRAY_SIZE 11
+#else /* LPUART10 */
+#if (defined(LPUART9))
+#define LPUART_HANDLE_ARRAY_SIZE 10
+#else /* LPUART9 */
+#if (defined(LPUART8))
+#define LPUART_HANDLE_ARRAY_SIZE 9
+#else /* LPUART8 */
+#if (defined(LPUART7))
+#define LPUART_HANDLE_ARRAY_SIZE 8
+#else /* LPUART7 */
+#if (defined(LPUART6))
+#define LPUART_HANDLE_ARRAY_SIZE 7
+#else /* LPUART6 */
+#if (defined(LPUART5))
+#define LPUART_HANDLE_ARRAY_SIZE 6
+#else /* LPUART5 */
+#if (defined(LPUART4))
+#define LPUART_HANDLE_ARRAY_SIZE 5
+#else /* LPUART4 */
+#if (defined(LPUART3))
+#define LPUART_HANDLE_ARRAY_SIZE 4
+#else /* LPUART3 */
+#if (defined(LPUART2))
+#define LPUART_HANDLE_ARRAY_SIZE 3
+#else /* LPUART2 */
+#if (defined(LPUART1))
+#define LPUART_HANDLE_ARRAY_SIZE 2
+#else /* LPUART1 */
+#if (defined(LPUART0))
+#define LPUART_HANDLE_ARRAY_SIZE 1
+#else /* LPUART0 */
+#define LPUART_HANDLE_ARRAY_SIZE FSL_FEATURE_SOC_LPUART_COUNT
+#endif /* LPUART 0 */
+#endif /* LPUART 1 */
+#endif /* LPUART 2 */
+#endif /* LPUART 3 */
+#endif /* LPUART 4 */
+#endif /* LPUART 5 */
+#endif /* LPUART 6 */
+#endif /* LPUART 7 */
+#endif /* LPUART 8 */
+#endif /* LPUART 9 */
+#endif /* LPUART 10 */
+#endif /* LPUART 11 */
+#endif /* LPUART 12 */
+
+/*<! Private handle only used for internally. */
+static lpuart_dma_private_handle_t s_dmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART DMA send finished callback function.
+ *
+ * This function is called when LPUART DMA send finished. It disables the LPUART
+ * TX DMA request and sends @ref kStatus_LPUART_TxIdle to LPUART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param);
+
+/*!
+ * @brief LPUART DMA receive finished callback function.
+ *
+ * This function is called when LPUART DMA receive finished. It disables the LPUART
+ * RX DMA request and sends @ref kStatus_LPUART_RxIdle to LPUART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param)
+{
+    assert(handle != NULL);
+    assert(param != NULL);
+
+    lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
+
+    /* Disable LPUART TX DMA. */
+    LPUART_EnableTxDMA(lpuartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base,
+                          lpuartPrivateHandle->handle->txDmaHandle->channel);
+
+    /* Enable tx complete interrupt */
+    LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable);
+}
+
+static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
+{
+    assert(handle != NULL);
+    assert(param != NULL);
+
+    lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
+
+    /* Disable LPUART RX DMA. */
+    LPUART_EnableRxDMA(lpuartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base,
+                          lpuartPrivateHandle->handle->rxDmaHandle->channel);
+
+    lpuartPrivateHandle->handle->rxState = (uint8_t)kLPUART_RxIdle;
+
+    if (lpuartPrivateHandle->handle->callback != NULL)
+    {
+        lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
+                                              kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData);
+    }
+}
+
+/*!
+ * brief Initializes the LPUART handle which is used in transactional functions.
+ *
+ * note This function disables all LPUART interrupts.
+ *
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_dma_handle_t structure.
+ * param callback Callback function.
+ * param userData User data.
+ * param txDmaHandle User-requested DMA handle for TX DMA transfer.
+ * param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+void LPUART_TransferCreateHandleDMA(LPUART_Type *base,
+                                    lpuart_dma_handle_t *handle,
+                                    lpuart_dma_transfer_callback_t callback,
+                                    void *userData,
+                                    dma_handle_t *txDmaHandle,
+                                    dma_handle_t *rxDmaHandle)
+{
+    assert(handle != NULL);
+
+    uint32_t instance = LPUART_GetInstance(base);
+
+    (void)memset(handle, 0, sizeof(lpuart_dma_handle_t));
+
+    s_dmaPrivateHandle[instance].base   = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
+    handle->txState = (uint8_t)kLPUART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Note:
+       Take care of the RX FIFO, DMA request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       DMA transfer because the water mark is 2.
+     */
+    if (rxDmaHandle != NULL)
+    {
+        base->WATER &= (~LPUART_WATER_RXWATER_MASK);
+    }
+#endif
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_lpuartHandle[instance] = handle;
+    /* Set LPUART_TransferDMAHandleIRQ as DMA IRQ handler */
+    s_lpuartIsr[instance] = LPUART_TransferDMAHandleIRQ;
+    /* Disable all LPUART internal interrupts */
+    LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable);
+    /* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    (void)EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
+    (void)EnableIRQ(s_lpuartIRQ[instance]);
+#endif
+
+    /* Configure TX. */
+    if (txDmaHandle != NULL)
+    {
+        DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle != NULL)
+    {
+        DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+}
+
+/*!
+ * brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_LPUART_TxBusy Previous transfer on going.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->data != NULL);
+    assert(xfer->dataSize != 0U);
+
+    status_t status;
+    dma_transfer_config_t xferConfig;
+
+    /* If previous TX not finished. */
+    if ((uint8_t)kLPUART_TxBusy == handle->txState)
+    {
+        status = kStatus_LPUART_TxBusy;
+    }
+    else
+    {
+        handle->txState       = (uint8_t)kLPUART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        uint32_t address = LPUART_GetDataRegisterAddress(base);
+        DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t),
+                            xfer->dataSize, kDMA_MemoryToPeripheral);
+
+        /* Submit transfer. */
+        (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+        DMA_StartTransfer(handle->txDmaHandle);
+
+        /* Enable LPUART TX DMA. */
+        LPUART_EnableTxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_dma_handle_t structure.
+ * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_LPUART_RxBusy Previous transfer on going.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->data != NULL);
+    assert(xfer->dataSize != 0U);
+
+    status_t status;
+    dma_transfer_config_t xferConfig;
+
+    /* If previous RX not finished. */
+    if ((uint8_t)kLPUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_LPUART_RxBusy;
+    }
+    else
+    {
+        handle->rxState       = (uint8_t)kLPUART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        uint32_t address = LPUART_GetDataRegisterAddress(base);
+        DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), xfer->data, sizeof(uint8_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        /* Enable LPUART RX DMA. */
+        LPUART_EnableRxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the sent data using DMA.
+ *
+ * This function aborts send data using DMA.
+ *
+ * param base LPUART peripheral base address
+ * param handle Pointer to lpuart_dma_handle_t structure
+ */
+void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+
+    /* Disable LPUART TX DMA. */
+    LPUART_EnableTxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->txDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->txState = (uint8_t)kLPUART_TxIdle;
+}
+
+/*!
+ * brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * param base LPUART peripheral base address
+ * param handle Pointer to lpuart_dma_handle_t structure
+ */
+void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+
+    /* Disable LPUART RX DMA. */
+    LPUART_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes written to the LPUART TX register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by DMA.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kLPUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the number of received bytes.
+ *
+ * This function gets the number of received bytes.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kLPUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief LPUART DMA IRQ handle function.
+ *
+ * This function handles the LPUART tx complete IRQ request and invoke user callback.
+ * note This function is used as default IRQ handler by double weak mechanism.
+ * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler.
+ *
+ * param base LPUART peripheral base address.
+ * param lpuartDmaHandle LPUART handle pointer.
+ */
+void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle)
+{
+    assert(lpuartDmaHandle != NULL);
+
+    if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U)
+    {
+        lpuart_dma_handle_t *handle = (lpuart_dma_handle_t *)lpuartDmaHandle;
+
+        /* Disable tx complete interrupt */
+        LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable);
+
+        handle->txState = (uint8_t)kLPUART_TxIdle;
+
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
+        }
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.h
new file mode 100644
index 0000000000..992163bbcf
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_lpuart_dma.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_LPUART_DMA_H_
+#define FSL_LPUART_DMA_H_
+
+#include "fsl_lpuart.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup lpuart_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief LPUART DMA driver version. */
+#define FSL_LPUART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
+/*! @} */
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_dma_handle lpuart_dma_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_dma_transfer_callback_t)(LPUART_Type *base,
+                                               lpuart_dma_handle_t *handle,
+                                               status_t status,
+                                               void *userData);
+
+/*!
+ * @brief LPUART DMA handle
+ */
+struct _lpuart_dma_handle
+{
+    lpuart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                          /*!< LPUART callback function parameter.*/
+    size_t rxDataSizeAll;                    /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                    /*!< Size of the data to send out. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle which is used in transactional functions.
+ *
+ * @note This function disables all LPUART interrupts.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param txDmaHandle User-requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+void LPUART_TransferCreateHandleDMA(LPUART_Type *base,
+                                    lpuart_dma_handle_t *handle,
+                                    lpuart_dma_transfer_callback_t callback,
+                                    void *userData,
+                                    dma_handle_t *txDmaHandle,
+                                    dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_LPUART_TxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_dma_handle_t structure.
+ * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_LPUART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts send data using DMA.
+ *
+ * @param base LPUART peripheral base address
+ * @param handle Pointer to lpuart_dma_handle_t structure
+ */
+void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base LPUART peripheral base address
+ * @param handle Pointer to lpuart_dma_handle_t structure
+ */
+void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes written to the LPUART TX register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by DMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of received bytes.
+ *
+ * This function gets the number of received bytes.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief LPUART DMA IRQ handle function.
+ *
+ * This function handles the LPUART tx complete IRQ request and invoke user callback.
+ * @note This function is used as default IRQ handler by double weak mechanism.
+ * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler.
+ *
+ * @param base LPUART peripheral base address.
+ * @param lpuartDmaHandle LPUART handle pointer.
+ */
+void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_LPUART_DMA_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.c
new file mode 100644
index 0000000000..932d52f980
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_pit.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pit"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base PIT peripheral base address
+ *
+ * @return The PIT instance
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static uint32_t PIT_GetInstance(PIT_Type *base);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to PIT bases for each instance. */
+static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
+
+/*! @brief Pointers to PIT clocks for each instance. */
+static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static uint32_t PIT_GetInstance(PIT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
+    {
+        if (s_pitBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_pitBases));
+
+    return instance;
+}
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*!
+ * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
+ *
+ * note This API should be called at the beginning of the application using the PIT driver.
+ *
+ * param base   PIT peripheral base address
+ * param config Pointer to the user's PIT config structure
+ */
+void PIT_Init(PIT_Type *base, const pit_config_t *config)
+{
+    assert(NULL != config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the PIT clock*/
+    CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
+#if defined(FSL_FEATURE_PIT_HAS_ERRATA_7914) && FSL_FEATURE_PIT_HAS_ERRATA_7914
+    /*
+     * If a write to the MCR[MDIS] bit occurs within two bus clock cycles of enabling the PIT clock
+     * in the SIM_CG register, the write will be ignored and the PIT will fail to enable.
+     * Insert a read of the MCR register before writing to the MCR register. This guarantees a minimum
+     * delay of two bus clocks to guarantee the write is not ignored.
+     */
+    (void)base->MCR;
+#endif
+    /* Enable PIT timers */
+    base->MCR &= ~PIT_MCR_MDIS_MASK;
+#endif
+
+#if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT)
+    /* Clear all status bits for all channels to make sure the status of all TCTRL registers is clean. */
+    for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK);
+    }
+#endif /* FSL_FEATURE_PIT_TIMER_COUNT */
+
+    /* Config timer operation when in debug mode */
+    if (true == config->enableRunInDebug)
+    {
+        base->MCR &= ~PIT_MCR_FRZ_MASK;
+    }
+    else
+    {
+        base->MCR |= PIT_MCR_FRZ_MASK;
+    }
+}
+
+/*!
+ * brief Gates the PIT clock and disables the PIT module.
+ *
+ * param base PIT peripheral base address
+ */
+void PIT_Deinit(PIT_Type *base)
+{
+#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
+    /* Disable PIT timers */
+    base->MCR |= PIT_MCR_MDIS_MASK;
+#endif
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the PIT clock*/
+    CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+
+/*!
+ * brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
+ * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
+ * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
+ * has the value of timer 0.
+ *
+ * param base PIT peripheral base address
+ *
+ * return Current lifetime timer value
+ */
+uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
+{
+    uint32_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* LTMR64H should be read before LTMR64L */
+    valueH = base->LTMR64H;
+    valueL = base->LTMR64L;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.h
new file mode 100644
index 0000000000..5d168ffdef
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pit.h
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_PIT_H_
+#define FSL_PIT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pit
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief PIT Driver Version 2.0.5 */
+#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*! @} */
+
+/*!
+ * @brief List of PIT channels
+ * @note Actual number of available channels is SoC dependent
+ */
+typedef enum _pit_chnl
+{
+    kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/
+    kPIT_Chnl_1,      /*!< PIT channel number 1 */
+    kPIT_Chnl_2,      /*!< PIT channel number 2 */
+    kPIT_Chnl_3,      /*!< PIT channel number 3 */
+} pit_chnl_t;
+
+/*! @brief List of PIT interrupts */
+typedef enum _pit_interrupt_enable
+{
+    kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/
+} pit_interrupt_enable_t;
+
+/*! @brief List of PIT status flags */
+typedef enum _pit_status_flags
+{
+    kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */
+} pit_status_flags_t;
+
+/*!
+ * @brief PIT configuration structure
+ *
+ * This structure holds the configuration settings for the PIT peripheral. To initialize this
+ * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _pit_config
+{
+    bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */
+} pit_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
+ *
+ * @note This API should be called at the beginning of the application using the PIT driver.
+ *
+ * @param base   PIT peripheral base address
+ * @param config Pointer to the user's PIT config structure
+ */
+void PIT_Init(PIT_Type *base, const pit_config_t *config);
+
+/*!
+ * @brief Gates the PIT clock and disables the PIT module.
+ *
+ * @param base PIT peripheral base address
+ */
+void PIT_Deinit(PIT_Type *base);
+
+/*!
+ * @brief Fills in the PIT configuration structure with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ *     config->enableRunInDebug = false;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+static inline void PIT_GetDefaultConfig(pit_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Timers are stopped in Debug mode */
+    config->enableRunInDebug = false;
+}
+
+#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE
+
+/*!
+ * @brief Enables or disables chaining a timer with the previous timer.
+ *
+ * When a timer has a chain mode enabled, it only counts after the previous
+ * timer has expired. If the timer n-1 has counted down to 0, counter n
+ * decrements the value by one. Each timer is 32-bits, which allows the developers
+ * to chain timers together and form a longer timer (64-bits and larger). The first timer
+ * (timer 0) can't be chained to any other timer.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number which is chained with the previous timer
+ * @param enable  Enable or disable chain.
+ *                true:  Current timer is chained with the previous timer.
+ *                false: Timer doesn't chain with other timers.
+ */
+static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable)
+{
+    if (enable)
+    {
+        base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK;
+    }
+    else
+    {
+        base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK;
+    }
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to enable. This is a logical OR of members of the
+ *                enumeration ::pit_interrupt_enable_t
+ */
+static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TCTRL |= mask;
+}
+
+/*!
+ * @brief Disables the selected PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to disable. This is a logical OR of members of the
+ *                enumeration ::pit_interrupt_enable_t
+ */
+static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TCTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::pit_interrupt_enable_t
+ */
+static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel)
+{
+    return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the PIT status flags.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::pit_status_flags_t
+ */
+static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel)
+{
+    return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK);
+}
+
+/*!
+ * @brief  Clears the PIT status flags.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::pit_status_flags_t
+ */
+static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TFLG = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function until it reaches 0,
+ * then it generates an interrupt and load this register value again.
+ * Writing a new value to this register does not restart the timer. Instead, the value
+ * is loaded after the timer expires.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param count   Timer period in units of ticks
+ */
+static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count)
+{
+    assert(count != 0U);
+    /* According to RM, the LDVAL trigger = clock ticks -1 */
+    base->CHANNEL[channel].LDVAL = count - 1U;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return Current timer counting value in ticks
+ */
+static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel)
+{
+    return base->CHANNEL[channel].CVAL;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the timeout interrupt flag.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel)
+{
+    base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops every timer counting. Timers reload their periods
+ * respectively after the next time they call the PIT_DRV_StartTimer.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel)
+{
+    base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK;
+}
+
+/*! @}*/
+
+#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+
+/*!
+ * @brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
+ * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
+ * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
+ * has the value of timer 0.
+ *
+ * @param base PIT peripheral base address
+ *
+ * @return Current lifetime timer value
+ */
+uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base);
+
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_PIT_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.c
new file mode 100644
index 0000000000..fb99654bb7
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_pmc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pmc"
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+/*!
+ * brief Gets the PMC parameter.
+ *
+ * This function gets the PMC parameter including the VLPO enable and the HVD enable.
+ *
+ * param base PMC peripheral base address.
+ * param param         Pointer to PMC param structure.
+ */
+void PMC_GetParam(PMC_Type *base, pmc_param_t *param)
+{
+    uint32_t reg = base->PARAM;
+    ;
+    param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK);
+    param->hvdEnable  = (bool)(reg & PMC_PARAM_HVDE_MASK);
+}
+#endif /* FSL_FEATURE_PMC_HAS_PARAM */
+
+/*!
+ * brief Configures the low-voltage detect setting.
+ *
+ * This function configures the low-voltage detect setting, including the trip
+ * point voltage setting, enables or disables the interrupt, enables or disables the system reset.
+ *
+ * param base PMC peripheral base address.
+ * param config  Low-voltage detect configuration structure.
+ */
+void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config)
+{
+    base->LVDSC1 = (uint8_t)((0U |
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+                              ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) |
+#endif
+                              ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) |
+                              ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT)
+                              /* Clear the Low Voltage Detect Flag with previous power detect setting */
+                              | PMC_LVDSC1_LVDACK_MASK));
+}
+
+/*!
+ * brief Configures the low-voltage warning setting.
+ *
+ * This function configures the low-voltage warning setting, including the trip
+ * point voltage setting and enabling or disabling the interrupt.
+ *
+ * param base PMC peripheral base address.
+ * param config  Low-voltage warning configuration structure.
+ */
+void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config)
+{
+    base->LVDSC2 = (uint8_t)((0U |
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+                              ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) |
+#endif
+                              ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT)
+                              /* Clear the Low Voltage Warning Flag with previous power detect setting */
+                              | PMC_LVDSC2_LVWACK_MASK));
+}
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * brief Configures the high-voltage detect setting.
+ *
+ * This function configures the high-voltage detect setting, including the trip
+ * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset.
+ *
+ * param base PMC peripheral base address.
+ * param config  High-voltage detect configuration structure.
+ */
+void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config)
+{
+    base->HVDSC1 = (uint8_t)(((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) |
+                             ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) |
+                             ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT)
+                             /* Clear the High Voltage Detect Flag with previous power detect setting */
+                             | PMC_HVDSC1_HVDACK_MASK);
+}
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+/*!
+ * brief Configures the PMC bandgap.
+ *
+ * This function configures the PMC bandgap, including the drive select and
+ * behavior in low-power mode.
+ *
+ * param base PMC peripheral base address.
+ * param config Pointer to the configuration structure
+ */
+void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config)
+{
+    base->REGSC = (uint8_t)(0U
+#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE)
+                            | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT)
+#endif /* FSL_FEATURE_PMC_HAS_BGBE */
+#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
+                            | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT))
+#endif /* FSL_FEATURE_PMC_HAS_BGEN */
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+                            | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT)
+#endif /* FSL_FEATURE_PMC_HAS_BGBDS */
+    );
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.h
new file mode 100644
index 0000000000..7cbd9b5b9a
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_pmc.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_PMC_H_
+#define FSL_PMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup pmc */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief PMC driver version */
+#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
+/*! @} */
+
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+/*!
+ * @brief Low-voltage Detect Voltage Select
+ */
+typedef enum _pmc_low_volt_detect_volt_select
+{
+    kPMC_LowVoltDetectLowTrip  = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/
+    kPMC_LowVoltDetectHighTrip = 1U  /*!< High-trip point selected (VLVD = VLVDH )*/
+} pmc_low_volt_detect_volt_select_t;
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+/*!
+ * @brief Low-voltage Warning Voltage Select
+ */
+typedef enum _pmc_low_volt_warning_volt_select
+{
+    kPMC_LowVoltWarningLowTrip  = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/
+    kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
+    kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
+    kPMC_LowVoltWarningHighTrip = 3U  /*!< High-trip point selected (VLVW = VLVW4)*/
+} pmc_low_volt_warning_volt_select_t;
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief High-voltage Detect Voltage Select
+ */
+typedef enum _pmc_high_volt_detect_volt_select
+{
+    kPMC_HighVoltDetectLowTrip  = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/
+    kPMC_HighVoltDetectHighTrip = 1U  /*!< High-trip point selected (VHVD = VHVDH )*/
+} pmc_high_volt_detect_volt_select_t;
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+/*!
+ * @brief Bandgap Buffer Drive Select.
+ */
+typedef enum _pmc_bandgap_buffer_drive_select
+{
+    kPMC_BandgapBufferDriveLow  = 0U, /*!< Low-drive.  */
+    kPMC_BandgapBufferDriveHigh = 1U  /*!< High-drive. */
+} pmc_bandgap_buffer_drive_select_t;
+#endif /* FSL_FEATURE_PMC_HAS_BGBDS */
+
+#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO)
+/*!
+ * @brief VLPx Option
+ */
+typedef enum _pmc_vlp_freq_option
+{
+    kPMC_FreqRestrict   = 0U, /*!< Frequency is restricted in VLPx mode. */
+    kPMC_FreqUnrestrict = 1U  /*!< Frequency is unrestricted in VLPx mode. */
+} pmc_vlp_freq_mode_t;
+#endif /* FSL_FEATURE_PMC_HAS_VLPO */
+
+#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID)
+/*!
+ @brief IP version ID definition.
+ */
+typedef struct _pmc_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} pmc_version_id_t;
+#endif /* FSL_FEATURE_PMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+/*! @brief IP parameter definition. */
+typedef struct _pmc_param
+{
+    bool vlpoEnable; /*!< VLPO enable. */
+    bool hvdEnable;  /*!< HVD enable.  */
+} pmc_param_t;
+#endif /* FSL_FEATURE_PMC_HAS_PARAM */
+
+/*!
+ * @brief Low-voltage Detect Configuration Structure
+ */
+typedef struct _pmc_low_volt_detect_config
+{
+    bool enableInt;   /*!< Enable interrupt when Low-voltage detect*/
+    bool enableReset; /*!< Enable system reset when Low-voltage detect*/
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/
+#endif
+} pmc_low_volt_detect_config_t;
+
+/*!
+ * @brief Low-voltage Warning Configuration Structure
+ */
+typedef struct _pmc_low_volt_warning_config
+{
+    bool enableInt; /*!< Enable interrupt when low-voltage warning*/
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/
+#endif
+} pmc_low_volt_warning_config_t;
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief High-voltage Detect Configuration Structure
+ */
+typedef struct _pmc_high_volt_detect_config
+{
+    bool enableInt;                                /*!< Enable interrupt when high-voltage detect*/
+    bool enableReset;                              /*!< Enable system reset when high-voltage detect*/
+    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/
+} pmc_high_volt_detect_config_t;
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+/*!
+ * @brief Bandgap Buffer configuration.
+ */
+typedef struct _pmc_bandgap_buffer_config
+{
+#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE)
+    bool enable; /*!< Enable bandgap buffer.                   */
+#endif
+#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
+    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */
+#endif                         /* FSL_FEATURE_PMC_HAS_BGEN */
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+    pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select.             */
+#endif                                       /* FSL_FEATURE_PMC_HAS_BGBDS */
+} pmc_bandgap_buffer_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Power Management Controller Control APIs*/
+/*! @{ */
+
+#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID)
+/*!
+ * @brief Gets the PMC version ID.
+ *
+ * This function gets the PMC version ID, including major version number,
+ * minor version number, and a feature specification number.
+ *
+ * @param base PMC peripheral base address.
+ * @param versionId     Pointer to version ID structure.
+ */
+static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId)
+{
+    union
+    {
+        pmc_version_id_t vid;
+        uint32_t u32;
+    } pmcVID;
+
+    pmcVID.u32 = base->VERID;
+    *versionId = pmcVID.vid;
+}
+#endif /* FSL_FEATURE_PMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+/*!
+ * @brief Gets the PMC parameter.
+ *
+ * This function gets the PMC parameter including the VLPO enable and the HVD enable.
+ *
+ * @param base PMC peripheral base address.
+ * @param param         Pointer to PMC param structure.
+ */
+void PMC_GetParam(PMC_Type *base, pmc_param_t *param);
+#endif
+
+/*!
+ * @brief Configures the low-voltage detect setting.
+ *
+ * This function configures the low-voltage detect setting, including the trip
+ * point voltage setting, enables or disables the interrupt, enables or disables the system reset.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  Low-voltage detect configuration structure.
+ */
+void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config);
+
+/*!
+ * @brief Gets the Low-voltage Detect Flag status.
+ *
+ * This function  reads the current LVDF status. If it returns 1, a low-voltage event is detected.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current low-voltage detect flag
+ *                - true: Low-voltage detected
+ *                - false: Low-voltage not detected
+ */
+static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base)
+{
+    if (0U != (base->LVDSC1 & PMC_LVDSC1_LVDF_MASK))
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*!
+ * @brief Acknowledges clearing the Low-voltage Detect flag.
+ *
+ * This function acknowledges the low-voltage detection errors (write 1 to
+ * clear LVDF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base)
+{
+    base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK;
+}
+
+/*!
+ * @brief Configures the low-voltage warning setting.
+ *
+ * This function configures the low-voltage warning setting, including the trip
+ * point voltage setting and enabling or disabling the interrupt.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  Low-voltage warning configuration structure.
+ */
+void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config);
+
+/*!
+ * @brief Gets the Low-voltage Warning Flag status.
+ *
+ * This function polls the current LVWF status. When 1 is returned, it
+ * indicates a low-voltage warning event. LVWF is set when V Supply transitions
+ * below the trip point or after reset and V Supply is already below the V LVW.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current LVWF status
+ *                  - true: Low-voltage Warning Flag is set.
+ *                  - false: the  Low-voltage Warning does not happen.
+ */
+static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base)
+{
+    if (0U != (base->LVDSC2 & PMC_LVDSC2_LVWF_MASK))
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/*!
+ * @brief Acknowledges the Low-voltage Warning flag.
+ *
+ * This function acknowledges the low voltage warning errors (write 1 to
+ * clear LVWF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base)
+{
+    base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK;
+}
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief Configures the high-voltage detect setting.
+ *
+ * This function configures the high-voltage detect setting, including the trip
+ * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  High-voltage detect configuration structure.
+ */
+void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config);
+
+/*!
+ * @brief Gets the High-voltage Detect Flag status.
+ *
+ * This function  reads the current HVDF status. If it returns 1, a low
+ * voltage event is detected.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current high-voltage detect flag
+ *                - true: High-voltage detected
+ *                - false: High-voltage not detected
+ */
+static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base)
+{
+    return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK);
+}
+
+/*!
+ * @brief Acknowledges clearing the High-voltage Detect flag.
+ *
+ * This function acknowledges the high-voltage detection errors (write 1 to
+ * clear HVDF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base)
+{
+    base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK;
+}
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+/*!
+ * @brief Configures the PMC bandgap.
+ *
+ * This function configures the PMC bandgap, including the drive select and
+ * behavior in low-power mode.
+ *
+ * @param base PMC peripheral base address.
+ * @param config Pointer to the configuration structure
+ */
+void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config);
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO)
+/*!
+ * @brief Gets the acknowledge Peripherals and I/O pads isolation flag.
+ *
+ * This function  reads the Acknowledge Isolation setting that indicates
+ * whether certain peripherals and the I/O pads are in a latched state as
+ * a result of having been in the VLLS mode.
+ *
+ * @param base PMC peripheral base address.
+ * @param base  Base address for current PMC instance.
+ * @return ACK isolation
+ *               0 - Peripherals and I/O pads are in a normal run state.
+ *               1 - Certain peripherals and I/O pads are in an isolated and
+ *                   latched state.
+ */
+static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base)
+{
+    return (0U != (base->REGSC & PMC_REGSC_ACKISO_MASK)) ? true : false;
+}
+
+/*!
+ * @brief Acknowledges the isolation flag to Peripherals and I/O pads.
+ *
+ * This function  clears the ACK Isolation flag. Writing one to this setting
+ * when it is set releases the I/O pads and certain peripherals to their normal
+ * run mode state.
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base)
+{
+    base->REGSC |= PMC_REGSC_ACKISO_MASK;
+}
+#endif /* FSL_FEATURE_PMC_HAS_ACKISO */
+
+#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS)
+/*!
+ * @brief Gets the regulator regulation status.
+ *
+ * This function  returns the regulator to run a regulation status. It provides
+ * the current status of the internal voltage regulator.
+ *
+ * @param base PMC peripheral base address.
+ * @param base  Base address for current PMC instance.
+ * @return Regulation status
+ *               0 - Regulator is in a stop regulation or in transition to/from the regulation.
+ *               1 - Regulator is in a run regulation.
+ *
+ */
+static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base)
+{
+    if (0U != (base->REGSC & PMC_REGSC_REGONS_MASK))
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif /* FSL_FEATURE_PMC_HAS_REGONS */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* FSL_PMC_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_port.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_port.h
new file mode 100644
index 0000000000..8eb512969d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_port.h
@@ -0,0 +1,684 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022, 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_PORT_H_
+#define FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.port"
+#endif
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief PORT driver version. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
+
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown    = 2U, /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp      = 3U, /*!< Internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
+/*! @brief Internal resistor pull value selection */
+enum _port_pull_value
+{
+    kPORT_LowPullResistor  = 0U, /*!< Low internal pull resistor value is selected. */
+    kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */
+};
+#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Open Drain feature enable/disable */
+enum _port_open_drain_enable
+{
+    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
+    kPORT_OpenDrainEnable  = 1U, /*!< Open drain output is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
+    kPORT_PassiveFilterEnable  = 1U, /*!< Passive input filter is enabled. */
+};
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*! @brief Configures the drive strength. */
+enum _port_drive_strength
+{
+    kPORT_LowDriveStrength  = 0U, /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
+/*! @brief Configures the drive strength1. */
+enum _port_drive_strength1
+{
+    kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */
+    kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */
+};
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
+
+#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
+/*! @brief input buffer disable/enable. */
+enum _port_input_buffer
+{
+    kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */
+    kPORT_InputBufferEnable  = 1U, /*!< Digital input is enabled */
+};
+#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
+
+#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
+/*! @brief Digital input is not inverted or it is inverted. */
+enum _port_invet_input
+{
+    kPORT_InputNormal = 0U, /*!< Digital input is not inverted */
+    kPORT_InputInvert = 1U, /*!< Digital input is inverted */
+};
+#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief Unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+    kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+    kPORT_LockRegister   = 1U, /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief Pin mux selection */
+typedef enum _port_mux
+{
+#if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0)
+    kPORT_MuxAsGpio           = 0U,  /*!< Corresponding pin is configured as GPIO. */
+#else
+    kPORT_PinDisabledOrAnalog = 0U,  /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio           = 1U,  /*!< Corresponding pin is configured as GPIO. */
+#endif
+    kPORT_MuxAlt0             = 0U,  /*!< Chip-specific */
+    kPORT_MuxAlt1             = 1U,  /*!< Chip-specific */
+    kPORT_MuxAlt2             = 2U,  /*!< Chip-specific */
+    kPORT_MuxAlt3             = 3U,  /*!< Chip-specific */
+    kPORT_MuxAlt4             = 4U,  /*!< Chip-specific */
+    kPORT_MuxAlt5             = 5U,  /*!< Chip-specific */
+    kPORT_MuxAlt6             = 6U,  /*!< Chip-specific */
+    kPORT_MuxAlt7             = 7U,  /*!< Chip-specific */
+    kPORT_MuxAlt8             = 8U,  /*!< Chip-specific */
+    kPORT_MuxAlt9             = 9U,  /*!< Chip-specific */
+    kPORT_MuxAlt10            = 10U, /*!< Chip-specific */
+    kPORT_MuxAlt11            = 11U, /*!< Chip-specific */
+    kPORT_MuxAlt12            = 12U, /*!< Chip-specific */
+    kPORT_MuxAlt13            = 13U, /*!< Chip-specific */
+    kPORT_MuxAlt14            = 14U, /*!< Chip-specific */
+    kPORT_MuxAlt15            = 15U, /*!< Chip-specific */
+} port_mux_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _port_interrupt
+{
+    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT)
+    kPORT_DMARisingEdge  = 0x1U, /*!< DMA request on rising edge. */
+    kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
+    kPORT_DMAEitherEdge  = 0x3U, /*!< DMA request on either edge. */
+#endif
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT)
+    kPORT_FlagRisingEdge  = 0x05U, /*!< Flag sets on rising edge. */
+    kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
+    kPORT_FlagEitherEdge  = 0x07U, /*!< Flag sets on either edge. */
+#endif
+    kPORT_InterruptLogicZero   = 0x8U, /*!< Interrupt when logic zero. */
+    kPORT_InterruptRisingEdge  = 0x9U, /*!< Interrupt on rising edge. */
+    kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+    kPORT_InterruptEitherEdge  = 0xBU, /*!< Interrupt on either edge. */
+    kPORT_InterruptLogicOne    = 0xCU, /*!< Interrupt when logic one. */
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT)
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable  = 0xEU, /*!< Enable active low-trigger output. */
+#endif
+} port_interrupt_t;
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection */
+typedef enum _port_digital_filter_clock_source
+{
+    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
+    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition */
+typedef struct _port_digital_filter_config
+{
+    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
+    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief PORT pin configuration structure */
+typedef struct _port_pin_config
+{
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+#else
+    uint16_t : 2;
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
+    uint16_t pullValueSelect : 1; /*!< Pull value select */
+#endif                            /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+#if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE)
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
+#else
+    uint16_t : 1;
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
+    uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
+    uint16_t mux : 3; /*!< Pin mux Configure */
+    uint16_t : 1;
+#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
+    uint16_t mux : 4; /*!< Pin mux Configure */
+#else
+    uint16_t : 4;
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
+    uint16_t inputBuffer : 1; /*!< Input Buffer Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
+
+#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
+    uint16_t invertInput : 1; /*!< Invert Input Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
+/*! @brief PORT version information. */
+typedef struct _port_version_info
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor Version Number. */
+    uint8_t major;    /*!< Major Version Number. */
+} port_version_info_t;
+#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
+
+#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
+/*! @brief PORT voltage range. */
+typedef enum _port_voltage_range
+{
+    kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */
+    kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */
+} port_voltage_range_t;
+#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Configuration */
+/*! @{ */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+
+#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
+/*!
+ * @brief Get PORT version information.
+ *
+ * @param base PORT peripheral base pointer
+ * @param info PORT version information
+ */
+static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)
+{
+    uint32_t verid = base->VERID;
+    info->feature  = (uint16_t)verid;
+    info->minor    = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT);
+    info->major    = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT);
+}
+#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
+
+#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
+/*!
+ * @brief Get PORT version information.
+ *
+ * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and
+ *         PORTC_CONFIG[RANGE] does not take effect.
+ *
+ * @param base PORT peripheral base pointer
+ * @param range port voltage range
+ */
+static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)
+{
+    base->CONFIG = (uint32_t)range;
+}
+#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration.
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param pin    PORT pin number.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+    assert(config);
+    uint32_t addr                = (uint32_t)&base->PCR[pin];
+    *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register for multiple pins.
+ *
+ * This is an example to define input pins or output pins PCR configuration.
+ * @code
+ * Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp ,
+ *      kPORT_PullEnable,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnlockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+    assert(config);
+
+    uint16_t pcrl = *((const uint16_t *)(const void *)config);
+
+    if (0U != (mask & 0xffffU))
+    {
+        base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
+    }
+    if (0U != (mask >> 16))
+    {
+        base->GPCHR = (mask & 0xffff0000U) | pcrl;
+    }
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
+/*!
+ * @brief Sets the port interrupt configuration in PCR register for multiple pins.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
+ */
+static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
+{
+    assert(config);
+
+    if (0U != ((uint32_t)mask & 0xffffU))
+    {
+        base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
+    }
+    mask = mask >> 16;
+    if (0U != mask)
+    {
+        base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
+    }
+}
+#endif
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param pin   PORT pin number.
+ * @param mux   pin muxing slot selection.
+ *        - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ *        - #kPORT_MuxAsGpio          : Set as GPIO.
+ *        - #kPORT_MuxAlt2            : chip-specific.
+ *        - #kPORT_MuxAlt3            : chip-specific.
+ *        - #kPORT_MuxAlt4            : chip-specific.
+ *        - #kPORT_MuxAlt5            : chip-specific.
+ *        - #kPORT_MuxAlt6            : chip-specific.
+ *        - #kPORT_MuxAlt7            : chip-specific.
+ * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
+ *
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+
+/*!
+ * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param mask    PORT pin number macro.
+ * @param enable  PORT digital filter configuration.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+    if (enable == true)
+    {
+        base->DFER |= mask;
+    }
+    else
+    {
+        base->DFER &= ~mask;
+    }
+}
+
+/*!
+ * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+    assert(config);
+
+    base->DFCR = PORT_DFCR_CS(config->clockSource);
+    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+/*! @} */
+
+/*! @name Interrupt */
+/*! @{ */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*!
+ * @brief Configures the port pin drive strength.
+ *
+ * @param base      PORT peripheral base pointer.
+ * @param pin       PORT pin number.
+ * @param strength  PORT pin drive strength
+ *        - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
+ *        - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
+ */
+static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
+}
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
+/*!
+ * @brief Enables the port pin double drive strength.
+ *
+ * @param base      PORT peripheral base pointer.
+ * @param pin       PORT pin number.
+ * @param enable  PORT pin drive strength configuration.
+ */
+static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable);
+}
+#endif
+
+#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
+/*!
+ * @brief Configures the port pin pull value.
+ *
+ * @param base      PORT peripheral base pointer.
+ * @param pin       PORT pin number.
+ * @param value  PORT pin pull value
+ *        - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
+ *        - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.
+ */
+static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value);
+}
+#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
+
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @return Current port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 16 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+    return base->ISFR;
+}
+
+/*!
+ * @brief Clears the multiple pin interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pin number macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+    base->ISFR = mask;
+}
+#endif
+
+#if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT
+/*!
+ * @brief Get EFT detect flags.
+ *
+ * @param base PORT peripheral base pointer
+ * @return EFT detect flags
+ */
+static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)
+{
+    return base->EDFR;
+}
+
+/*!
+ * @brief Enable EFT detect interrupts.
+ *
+ * @param base PORT peripheral base pointer
+ * @param interrupt EFT detect interrupt
+ */
+static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
+{
+    base->EDIER |= interrupt;
+}
+
+/*!
+ * @brief Disable EFT detect interrupts.
+ *
+ * @param base PORT peripheral base pointer
+ * @param interrupt EFT detect interrupt
+ */
+static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
+{
+    base->EDIER &= ~interrupt;
+}
+
+/*!
+ * @brief Clear all low EFT detector.
+ *
+ * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the
+ * PORTB_EDCR does not take effect.
+ * @param base PORT peripheral base pointer
+ * @param interrupt EFT detect interrupt
+ */
+static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)
+{
+    base->EDCR |= PORT_EDCR_EDLC_MASK;
+    base->EDCR &= ~PORT_EDCR_EDLC_MASK;
+}
+
+/*!
+ * @brief Clear all high EFT detector.
+ *
+ * @param base PORT peripheral base pointer
+ * @param interrupt EFT detect interrupt
+ */
+static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
+{
+    base->EDCR |= PORT_EDCR_EDHC_MASK;
+    base->EDCR &= ~PORT_EDCR_EDHC_MASK;
+}
+#endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_PORT_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.c
new file mode 100644
index 0000000000..c3f7158211
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_rcm.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.rcm"
+#endif
+
+/*!
+ * brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the filter source, filter
+ * width, and so on.
+ *
+ * param base RCM peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config)
+{
+    assert(NULL != config);
+
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    uint32_t reg;
+
+    reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait);
+    if (config->filterInRunWait == kRCM_FilterBusClock)
+    {
+        reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT);
+    }
+    base->RPC = reg;
+#else
+    base->RPFC = (((uint8_t)config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait);
+    if (config->filterInRunWait == kRCM_FilterBusClock)
+    {
+        base->RPFW = config->busClockFilterCount;
+    }
+#endif /* FSL_FEATURE_RCM_REG_WIDTH */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * brief Forces the boot from ROM.
+ *
+ * This function forces booting from ROM during all subsequent system resets.
+ *
+ * param base RCM peripheral base address.
+ * param config   Boot configuration.
+ */
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config)
+{
+    uint32_t reg;
+
+    reg = base->FM;
+    reg &= ~RCM_FM_FORCEROM_MASK;
+    reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT);
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    base->FM = reg;
+#else
+    base->FM = (uint8_t)reg;
+#endif /* FSL_FEATURE_RCM_REG_WIDTH == 32 */
+}
+#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.h
new file mode 100644
index 0000000000..7709ab84a5
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rcm.h
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_RCM_H_
+#define FSL_RCM_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup rcm */
+/*! @{*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief RCM driver version 2.0.4. */
+#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*! @} */
+
+/*!
+ * @brief System Reset Source Name definitions
+ */
+typedef enum _rcm_reset_source
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+/* RCM register bit width is 32. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+    kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
+#endif
+    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+    kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
+#endif                                 /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+    kRCM_SourceLol = RCM_SRS_LOL_MASK,   /*!< Loss of lock reset */
+#endif                                   /* FSL_FEATURE_RCM_HAS_LOL */
+    kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */
+    kRCM_SourcePin  = RCM_SRS_PIN_MASK,  /*!< External pin reset */
+    kRCM_SourcePor  = RCM_SRS_POR_MASK,  /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+    kRCM_SourceJtag = RCM_SRS_JTAG_MASK,     /*!< JTAG generated reset */
+#endif                                       /* FSL_FEATURE_RCM_HAS_JTAG */
+    kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */
+    kRCM_SourceSw     = RCM_SRS_SW_MASK,     /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+    kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */
+#endif                                      /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+    kRCM_SourceEzpt = RCM_SRS_EZPT_MASK,       /*!< EzPort reset */
+#endif                                         /* FSL_FEATURE_RCM_HAS_EZPORT */
+    kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */
+
+#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+/* RCM register bit width is 8. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+    kRCM_SourceWakeup  = RCM_SRS0_WAKEUP_MASK,        /*!< Low-leakage wakeup reset */
+#endif
+    kRCM_SourceLvd     = RCM_SRS0_LVD_MASK,           /*!< Low-voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+    kRCM_SourceLoc     = RCM_SRS0_LOC_MASK,           /*!< Loss of clock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+    kRCM_SourceLol     = RCM_SRS0_LOL_MASK,           /*!< Loss of lock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOL */
+    kRCM_SourceWdog    = RCM_SRS0_WDOG_MASK,          /*!< Watchdog reset */
+    kRCM_SourcePin     = RCM_SRS0_PIN_MASK,           /*!< External pin reset */
+    kRCM_SourcePor     = RCM_SRS0_POR_MASK,           /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+    kRCM_SourceJtag    = RCM_SRS1_JTAG_MASK << 8U,    /*!< JTAG generated reset */
+#endif /* FSL_FEATURE_RCM_HAS_JTAG */
+    kRCM_SourceLockup  = RCM_SRS1_LOCKUP_MASK << 8U,  /*!< Core lock up reset */
+    kRCM_SourceSw      = RCM_SRS1_SW_MASK << 8U,      /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+    kRCM_SourceMdmap   = RCM_SRS1_MDM_AP_MASK << 8U,  /*!< MDM-AP system reset */
+#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+    kRCM_SourceEzpt    = RCM_SRS1_EZPT_MASK << 8U,    /*!< EzPort reset */
+#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
+    kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+    kRCM_SourceAll = (int)0xffffffffU,
+} rcm_reset_source_t;
+
+/*!
+ * @brief Reset pin filter select in Run and Wait modes.
+ */
+typedef enum _rcm_run_wait_filter_mode
+{
+    kRCM_FilterDisable  = 0U, /*!< All filtering disabled */
+    kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */
+    kRCM_FilterLpoClock = 2U  /*!< LPO clock filter enabled */
+} rcm_run_wait_filter_mode_t;
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Boot from ROM configuration.
+ */
+typedef enum _rcm_boot_rom_config
+{
+    kRCM_BootFlash   = 0U, /*!< Boot from flash */
+    kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */
+    kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */
+    kRCM_BootRomBoth = 3U  /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */
+} rcm_boot_rom_config_t;
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Maximum delay time from interrupt asserts to system reset.
+ */
+typedef enum _rcm_reset_delay
+{
+    kRCM_ResetDelay8Lpo   = 0U, /*!< Delay 8 LPO cycles.   */
+    kRCM_ResetDelay32Lpo  = 1U, /*!< Delay 32 LPO cycles.  */
+    kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */
+    kRCM_ResetDelay512Lpo = 3U  /*!< Delay 512 LPO cycles. */
+} rcm_reset_delay_t;
+
+/*!
+ * @brief System reset interrupt enable bit definitions.
+ */
+typedef enum _rcm_interrupt_enable
+{
+    kRCM_IntNone           = 0U,                    /*!< No interrupt enabled.           */
+    kRCM_IntLossOfClk      = RCM_SRIE_LOC_MASK,     /*!< Loss of clock interrupt.        */
+    kRCM_IntLossOfLock     = RCM_SRIE_LOL_MASK,     /*!< Loss of lock interrupt.         */
+    kRCM_IntWatchDog       = RCM_SRIE_WDOG_MASK,    /*!< Watch dog interrupt.            */
+    kRCM_IntExternalPin    = RCM_SRIE_PIN_MASK,     /*!< External pin interrupt.         */
+    kRCM_IntGlobal         = RCM_SRIE_GIE_MASK,     /*!< Global interrupts.              */
+    kRCM_IntCoreLockup     = RCM_SRIE_LOCKUP_MASK,  /*!< Core lock up interrupt           */
+    kRCM_IntSoftware       = RCM_SRIE_SW_MASK,      /*!< software interrupt              */
+    kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt.  */
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+    kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt.               */
+#endif
+    kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts.          */
+                  | RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK |
+                  RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+                  | RCM_SRIE_CORE1_MASK
+#endif
+} rcm_interrupt_enable_t;
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _rcm_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} rcm_version_id_t;
+#endif
+
+/*!
+ * @brief Reset pin filter configuration.
+ */
+typedef struct _rcm_reset_pin_filter_config
+{
+    bool enableFilterInStop;                    /*!< Reset pin filter select in stop mode. */
+    rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */
+    uint8_t busClockFilterCount;                /*!< Reset pin bus clock filter width.  */
+} rcm_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Reset Control Module APIs*/
+/*! @{ */
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief Gets the RCM version ID.
+ *
+ * This function gets the RCM version ID including the major version number,
+ * the minor version number, and the feature specification number.
+ *
+ * @param base RCM peripheral base address.
+ * @param versionId     Pointer to the version ID structure.
+ */
+static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
+{
+    uint32_t tmp = base->VERID;
+
+    versionId->feature = (uint16_t)(tmp & 0x0000FFFFUL);
+    versionId->minor   = (uint8_t)((tmp & 0x00FF0000UL) >> 16U);
+    versionId->major   = (uint8_t)((tmp & 0x000000FFUL) >> 24U);
+}
+#endif
+
+#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM)
+/*!
+ * @brief Gets the reset source implemented status.
+ *
+ * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
+ * Use source masks defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * This is an example.
+ * @code
+ * uint32_t status;
+ *
+ * To test whether the MCU is reset using Watchdog.
+ * status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ * @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source implemented status bit map.
+ */
+static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base)
+{
+    return base->PARAM;
+}
+#endif /* FSL_FEATURE_RCM_HAS_PARAM */
+
+/*!
+ * @brief Gets the reset source status which caused a previous reset.
+ *
+ * This function gets the current reset source status. Use source masks
+ * defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * This is an example.
+ * @code
+ * uint32_t resetStatus;
+ *
+ * To get all reset source statuses.
+ * resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll;
+ *
+ * To test whether the MCU is reset using Watchdog.
+ * resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog;
+ *
+ * To test multiple reset sources.
+ * resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ * @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    return base->SRS;
+#else
+    uint8_t tmpSrs0 = base->SRS0;
+    uint8_t tmpSrs1 = base->SRS1;
+    return (uint32_t)((uint32_t)tmpSrs0 | ((uint32_t)tmpSrs1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that has not been cleared
+ * by software for a specific source.
+ *
+ * This is an example.
+ * @code
+ * uint32_t resetStatus;
+ *
+ * To get all reset source statuses.
+ * resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
+ *
+ * To test whether the MCU is reset using Watchdog.
+ * resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog;
+ *
+ * To test multiple reset sources.
+ * resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ * @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    return base->SSRS;
+#else
+    return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+/*!
+ * @brief Clears the sticky reset source status.
+ *
+ * This function clears the sticky system reset flags indicated by source masks.
+ *
+ * This is an example.
+ * @code
+ * Clears multiple reset sources.
+ * RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
+ * @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @param sourceMasks reset source status bit map
+ */
+static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    base->SSRS = sourceMasks;
+#else
+    base->SSRS0 = (uint8_t)(sourceMasks & 0xffU);
+    base->SSRS1 = (uint8_t)((sourceMasks >> 8U) & 0xffU);
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+#endif /* FSL_FEATURE_RCM_HAS_SSRS */
+
+/*!
+ * @brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the filter source, filter
+ * width, and so on.
+ *
+ * @param base RCM peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config);
+
+#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS)
+/*!
+ * @brief Gets the EZP_MS_B pin assert status.
+ *
+ * This function gets the easy port mode status (EZP_MS_B) pin assert status.
+ *
+ * @param base RCM peripheral base address.
+ * @return status  true - asserted, false - reasserted
+ */
+static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base)
+{
+    return (bool)(base->MR & RCM_MR_EZP_MS_MASK);
+}
+#endif /* FSL_FEATURE_RCM_HAS_EZPMS */
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Gets the ROM boot source.
+ *
+ * This function gets the ROM boot source during the last chip reset.
+ *
+ * @param base RCM peripheral base address.
+ * @return The ROM boot source.
+ */
+static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base)
+{
+    return (rcm_boot_rom_config_t)(uint8_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT);
+}
+
+/*!
+ * @brief Clears the ROM boot source flag.
+ *
+ * This function clears the ROM boot source flag.
+ *
+ * @param base     Register base address of RCM
+ */
+static inline void RCM_ClearBootRomSource(RCM_Type *base)
+{
+    base->MR |= RCM_MR_BOOTROM_MASK;
+}
+
+/*!
+ * @brief Forces the boot from ROM.
+ *
+ * This function forces booting from ROM during all subsequent system resets.
+ *
+ * @param base RCM peripheral base address.
+ * @param config   Boot configuration.
+ */
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config);
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Sets the system reset interrupt configuration.
+ *
+ * For a graceful shut down, the RCM supports delaying the assertion of the system
+ * reset for a period of time when the reset interrupt is generated. This function
+ * can be used to enable the interrupt and the delay period. The interrupts
+ * are passed in as bit mask. See rcm_int_t for details. For example, to
+ * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs,
+ * configure as follows:
+ * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo);
+ *
+ * @param base RCM peripheral base address.
+ * @param intMask   Bit mask of the system reset interrupts to enable. See
+ *                  rcm_interrupt_enable_t for details.
+ * @param delay     Bit mask of the system reset interrupts to enable.
+ */
+static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay)
+{
+    base->SRIE = (intMask | (uint32_t)delay);
+}
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* FSL_RCM_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.c
new file mode 100644
index 0000000000..4bc2d38fd1
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.c
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_rtc.h"
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification rtc_c_ref_1$
+ * Month is always under 13 and checked by assert.
+ *
+ * $Justification rtc_c_ref_2$
+ * Can't simulate tamper in unit test environment.
+ *
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.rtc"
+#endif
+
+#define SECONDS_IN_A_DAY    (86400U)
+#define SECONDS_IN_A_HOUR   (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR      (365U)
+#define YEAR_RANGE_START    (1970U)
+#define YEAR_RANGE_END      (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds  Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Check year, month, hour, minute, seconds */
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+    {
+        /* If not correct then error*/
+        return false;
+    }
+
+    /* Adjust the days in February for a leap year */
+    if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /* Check the validity of the day */
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
+    {
+        return false;
+    }
+
+    return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    /* Number of days from begin of the non Leap-year*/
+    /* Number of days from begin of the non Leap-year*/
+    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+    uint32_t seconds;
+
+    /* Compute number of days from 1970 till given year*/
+    seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U));
+    /* Add number of days till given month*/
+    seconds += monthDays[datetime->month];
+    /* Add days in given month. We subtract the current day as it is
+     * represented in the hours, minutes and seconds field*/
+    seconds += ((uint32_t)datetime->day - 1U);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((0U == (datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        seconds--;
+    }
+
+    seconds = (seconds * SECONDS_IN_A_DAY) + ((uint32_t)datetime->hour * SECONDS_IN_A_HOUR) +
+              ((uint32_t)datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+    return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    uint32_t x;
+    uint32_t secondsRemaining, days;
+    uint16_t daysInYear;
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Start with the seconds value that is passed in to be converted to date time format */
+    secondsRemaining = seconds;
+
+    /* Calcuate the number of days, we add 1 for the current day which is represented in the
+     * hours and seconds field
+     */
+    days = secondsRemaining / SECONDS_IN_A_DAY + 1U;
+
+    /* Update seconds left*/
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+    /* Calculate the datetime hour, minute and second fields */
+    datetime->hour   = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR);
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+    datetime->minute = (uint8_t)(secondsRemaining / 60U);
+    datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE);
+
+    /* Calculate year */
+    daysInYear     = DAYS_IN_A_YEAR;
+    datetime->year = YEAR_RANGE_START;
+    while (days > daysInYear)
+    {
+        /* Decrease day count by a year and increment year by 1 */
+        days -= daysInYear;
+        datetime->year++;
+
+        /* Adjust the number of days for a leap year */
+        if (0U != (datetime->year & 3U))
+        {
+            daysInYear = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            daysInYear = DAYS_IN_A_YEAR + 1U;
+        }
+    }
+
+    /* Adjust the days in February for a leap year */
+    if (0U == (datetime->year & 3U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /*
+     * $Branch Coverage Justification$
+     * (x > 12U) not covered. $ref rtc_c_ref_1$.
+     */
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (days <= daysPerMonth[x])
+        {
+            datetime->month = (uint8_t)x;
+            break;
+        }
+        else
+        {
+            days -= daysPerMonth[x];
+        }
+    }
+
+    datetime->day = (uint8_t)days;
+}
+
+/*!
+ * brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function issues a software reset if the timer invalid flag is set.
+ *
+ * note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * param base   RTC peripheral base address
+ * param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t reg;
+
+#if defined(RTC_CLOCKS)
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* RTC_CLOCKS */
+
+    /* Issue a software reset if timer is invalid */
+    if ((uint32_t)kRTC_TimeInvalidFlag == (RTC_GetStatusFlags(base) & (uint32_t)kRTC_TimeInvalidFlag))
+    {
+        RTC_Reset(base);
+    }
+
+    reg = base->CR;
+/* Setup the update mode and supervisor access mode */
+#if !(defined(FSL_FEATURE_RTC_HAS_NO_CR_OSCE) && FSL_FEATURE_RTC_HAS_NO_CR_OSCE)
+    reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK);
+    reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess);
+#else
+    reg &= ~RTC_CR_UM_MASK;
+    reg |= RTC_CR_UM(config->updateMode);
+#endif
+
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION
+    /* Setup the wakeup pin select */
+    reg &= ~(RTC_CR_WPS_MASK);
+    reg |= RTC_CR_WPS(config->wakeupSelect);
+#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */
+    base->CR = reg;
+
+    /* Configure the RTC time compensation register */
+    base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime));
+
+#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC
+    /* Configure RTC timer seconds interrupt to be generated once per second */
+    base->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK);
+#endif
+}
+
+/*!
+ * brief Fills in the RTC config struct with the default settings.
+ *
+ * The default values are as follows.
+ * code
+ *    config->wakeupSelect = false;
+ *    config->updateMode = false;
+ *    config->supervisorAccess = false;
+ *    config->compensationInterval = 0;
+ *    config->compensationTime = 0;
+ * endcode
+ * param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */
+    config->wakeupSelect = false;
+    /* Registers cannot be written when locked */
+    config->updateMode = false;
+    /* Non-supervisor mode write accesses are not supported and will generate a bus error */
+    config->supervisorAccess = false;
+    /* Compensation interval used by the crystal compensation logic */
+    config->compensationInterval = 0;
+    /* Compensation time used by the crystal compensation logic */
+    config->compensationTime = 0;
+}
+
+/*!
+ * brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function because writes to the RTC
+ * seconds register fail if the RTC counter is running.
+ *
+ * param base     RTC peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ *
+ * return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(datetime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set time in seconds */
+    base->TSR = RTC_ConvertDatetimeToSeconds(datetime);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the RTC time and stores it in the given time structure.
+ *
+ * param base     RTC peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    uint32_t seconds = 0;
+
+    seconds = base->TSR;
+    RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+/*!
+ * brief Sets the RTC alarm time.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * param base      RTC peripheral base address
+ * param alarmTime Pointer to the structure where the alarm time is stored.
+ *
+ * return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+    assert(NULL != alarmTime);
+
+    uint32_t alarmSeconds = 0;
+    uint32_t currSeconds  = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(alarmTime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+    /* Get the current time */
+    currSeconds = base->TSR;
+
+    /* Return error if the alarm time has passed */
+    if (alarmSeconds < currSeconds)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set alarm in seconds*/
+    base->TAR = alarmSeconds;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Returns the RTC alarm time.
+ *
+ * param base     RTC peripheral base address
+ * param datetime Pointer to the structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(NULL != datetime);
+
+    uint32_t alarmSeconds = 0;
+
+    /* Get alarm in seconds  */
+    alarmSeconds = base->TAR;
+
+    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}
+
+/*!
+ * brief Enables the selected RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t tmp32 = 0U;
+
+    /* RTC_IER */
+    if (0U != ((uint32_t)kRTC_TimeInvalidInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TIIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_TimeOverflowInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TOIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_AlarmInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TAIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_SecondsInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TSIE_MASK;
+    }
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    if (0U != ((uint32_t)kRTC_MonotonicOverflowInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_MOIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+    base->IER |= tmp32;
+
+#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR)
+    tmp32 = 0U;
+
+    /* RTC_TIR */
+    if (0U != ((uint32_t)kRTC_TestModeInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_TMIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_FlashSecurityInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_FSIE_MASK;
+    }
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE)
+    if (0U != ((uint32_t)kRTC_TamperPinInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_TPIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE)
+    if (0U != ((uint32_t)kRTC_SecurityModuleInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_SIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE)
+    if (0U != ((uint32_t)kRTC_LossOfClockInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_LCIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */
+    base->TIR |= tmp32;
+#endif /* FSL_FEATURE_RTC_HAS_TIR */
+}
+
+/*!
+ * brief Disables the selected RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t tmp32 = 0U;
+
+    /* RTC_IER */
+    if (0U != ((uint32_t)kRTC_TimeInvalidInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TIIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_TimeOverflowInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TOIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_AlarmInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TAIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_SecondsInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_TSIE_MASK;
+    }
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    if (0U != ((uint32_t)kRTC_MonotonicOverflowInterruptEnable & mask))
+    {
+        tmp32 |= RTC_IER_MOIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+    base->IER &= (uint32_t)(~tmp32);
+
+#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR)
+    tmp32 = 0U;
+
+    /* RTC_TIR */
+    if (0U != ((uint32_t)kRTC_TestModeInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_TMIE_MASK;
+    }
+    if (0U != ((uint32_t)kRTC_FlashSecurityInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_FSIE_MASK;
+    }
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE)
+    if (0U != ((uint32_t)kRTC_TamperPinInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_TPIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE)
+    if (0U != ((uint32_t)kRTC_SecurityModuleInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_SIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE)
+    if (0U != ((uint32_t)kRTC_LossOfClockInterruptEnable & mask))
+    {
+        tmp32 |= RTC_TIR_LCIE_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */
+    base->TIR &= (uint32_t)(~tmp32);
+#endif /* FSL_FEATURE_RTC_HAS_TIR */
+}
+
+/*!
+ * brief Gets the enabled RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+    uint32_t tmp32 = 0U;
+
+    /* RTC_IER */
+    if (0U != (RTC_IER_TIIE_MASK & base->IER))
+    {
+        tmp32 |= (uint32_t)kRTC_TimeInvalidInterruptEnable;
+    }
+    if (0U != (RTC_IER_TOIE_MASK & base->IER))
+    {
+        tmp32 |= (uint32_t)kRTC_TimeOverflowInterruptEnable;
+    }
+    if (0U != (RTC_IER_TAIE_MASK & base->IER))
+    {
+        tmp32 |= (uint32_t)kRTC_AlarmInterruptEnable;
+    }
+    if (0U != (RTC_IER_TSIE_MASK & base->IER))
+    {
+        tmp32 |= (uint32_t)kRTC_SecondsInterruptEnable;
+    }
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    if (0U != (RTC_IER_MOIE_MASK & base->IER))
+    {
+        tmp32 |= (uint32_t)kRTC_MonotonicOverflowInterruptEnable;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR)
+    /* RTC_TIR */
+    if (0U != (RTC_TIR_TMIE_MASK & base->TIR))
+    {
+        tmp32 |= (uint32_t)kRTC_TestModeInterruptEnable;
+    }
+    if (0U != (RTC_TIR_FSIE_MASK & base->TIR))
+    {
+        tmp32 |= (uint32_t)kRTC_FlashSecurityInterruptEnable;
+    }
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE)
+    if (0U != (RTC_TIR_TPIE_MASK & base->TIR))
+    {
+        tmp32 |= (uint32_t)kRTC_TamperPinInterruptEnable;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE)
+    if (0U != (RTC_TIR_SIE_MASK & base->TIR))
+    {
+        tmp32 |= (uint32_t)kRTC_SecurityModuleInterruptEnable;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE)
+    if (0U != (RTC_TIR_LCIE_MASK & base->TIR))
+    {
+        tmp32 |= (uint32_t)kRTC_LossOfClockInterruptEnable;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */
+#endif /* FSL_FEATURE_RTC_HAS_TIR */
+
+    return tmp32;
+}
+
+/*!
+ * brief Gets the RTC status flags.
+ *
+ * param base RTC peripheral base address
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+    uint32_t tmp32 = 0U;
+
+    /* RTC_SR */
+    if (0U != (RTC_SR_TIF_MASK & base->SR))
+    {
+        tmp32 |= (uint32_t)kRTC_TimeInvalidFlag;
+    }
+    if (0U != (RTC_SR_TOF_MASK & base->SR))
+    {
+        tmp32 |= (uint32_t)kRTC_TimeOverflowFlag;
+    }
+    if (0U != (RTC_SR_TAF_MASK & base->SR))
+    {
+        tmp32 |= (uint32_t)kRTC_AlarmFlag;
+    }
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    if (0U != (RTC_SR_MOF_MASK & base->SR))
+    {
+        tmp32 |= (uint32_t)kRTC_MonotonicOverflowFlag;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF)
+    /*
+     * $Branch Coverage Justification$
+     * (0U != (RTC_SR_TIDF_MASK & base->SR)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != (RTC_SR_TIDF_MASK & base->SR))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        tmp32 |= (uint32_t)kRTC_TamperInterruptDetectFlag;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_SR_TIDF */
+
+#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR)
+    /* RTC_TDR */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != (RTC_TDR_TMF_MASK & base->TDR)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != (RTC_TDR_TMF_MASK & base->TDR))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        tmp32 |= (uint32_t)kRTC_TestModeFlag;
+    }
+    if (0U != (RTC_TDR_FSF_MASK & base->TDR))
+    {
+        tmp32 |= (uint32_t)kRTC_FlashSecurityFlag;
+    }
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF)
+    /*
+     * $Branch Coverage Justification$
+     * (0U != (RTC_TDR_TPF_MASK & base->TDR)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != (RTC_TDR_TPF_MASK & base->TDR))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        tmp32 |= (uint32_t)kRTC_TamperPinFlag;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF)
+    /*
+     * $Branch Coverage Justification$
+     * (0U != (RTC_TDR_STF_MASK & base->TDR)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != (RTC_TDR_STF_MASK & base->TDR))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        tmp32 |= (uint32_t)kRTC_SecurityTamperFlag;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF)
+    /*
+     * $Branch Coverage Justification$
+     * (0U != (RTC_TDR_LCTF_MASK & base->TDR)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != (RTC_TDR_LCTF_MASK & base->TDR))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        tmp32 |= (uint32_t)kRTC_LossOfClockTamperFlag;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */
+#endif /* FSL_FEATURE_RTC_HAS_TDR */
+
+    return tmp32;
+}
+
+/*!
+ * brief  Clears the RTC status flags.
+ *
+ * param base RTC peripheral base address
+ * param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+    /* The alarm flag is cleared by writing to the TAR register */
+    if (0U != (mask & (uint32_t)kRTC_AlarmFlag))
+    {
+        base->TAR = 0U;
+    }
+
+    /* The timer overflow flag is cleared by initializing the TSR register.
+     * The time counter should be disabled for this write to be successful
+     */
+    if (0U != (mask & (uint32_t)kRTC_TimeOverflowFlag))
+    {
+        base->TSR = 1U;
+    }
+
+    /* The timer overflow flag is cleared by initializing the TSR register.
+     * The time counter should be disabled for this write to be successful
+     */
+    if (0U != (mask & (uint32_t)kRTC_TimeInvalidFlag))
+    {
+        base->TSR = 1U;
+    }
+
+#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR)
+    /* To clear, write logic one to this flag after exiting from all test modes */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != ((uint32_t)kRTC_TestModeFlag & mask)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != ((uint32_t)kRTC_TestModeFlag & mask))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        base->TDR = RTC_TDR_TMF_MASK;
+    }
+    /* To clear, write logic one to this flag after flash security is enabled */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != ((uint32_t)kRTC_FlashSecurityFlag & mask)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != ((uint32_t)kRTC_FlashSecurityFlag & mask))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        base->TDR = RTC_TDR_FSF_MASK;
+    }
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF)
+    /* To clear, write logic one to the corresponding flag after that tamper pin negates */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != ((uint32_t)kRTC_TamperPinFlag & mask)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != ((uint32_t)kRTC_TamperPinFlag & mask))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        base->TDR = RTC_TDR_TPF_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF)
+    /* To clear, write logic one to this flag after security module has negated its tamper detect */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != ((uint32_t)kRTC_SecurityTamperFlag & mask)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != ((uint32_t)kRTC_SecurityTamperFlag & mask))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        base->TDR = RTC_TDR_STF_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF)
+    /* To clear, write logic one to this flag after loss of clock negates */
+    /*
+     * $Branch Coverage Justification$
+     * (0U != ((uint32_t)kRTC_LossOfClockTamperFlag & mask)) not covered. $ref rtc_c_ref_2$.
+     */
+    if (0U != ((uint32_t)kRTC_LossOfClockTamperFlag & mask))
+    {
+        /*
+        * $Line Coverage Justification$
+        * $ref rtc_c_ref_2$.
+        */
+        base->TDR = RTC_TDR_LCTF_MASK;
+    }
+#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */
+#endif /* FSL_FEATURE_RTC_HAS_TDR */
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+/*!
+ * brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ *        them as a single value.
+ *
+ * param base    RTC peripheral base address
+ * param counter Pointer to variable where the value is stored.
+ */
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter)
+{
+    uint64_t u64temp;
+
+    assert(NULL != counter);
+
+    u64temp  = (uint64_t)base->MCLR;
+    *counter = (((uint64_t)base->MCHR << 32U) | u64temp);
+}
+
+/*!
+ * brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ *        the given single value. The Monotonic Overflow Flag in RTC_SR is cleared due to the API.
+ *
+ * param base    RTC peripheral base address
+ * param counter Counter value
+ */
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter)
+{
+    /* Prepare to initialize the register with the new value written */
+    base->MER &= ~RTC_MER_MCE_MASK;
+
+    base->MCHR = (uint32_t)((counter) >> 32);
+    base->MCLR = (uint32_t)(counter);
+}
+
+/*!
+ * brief Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * param base RTC peripheral base address
+ *
+ * return kStatus_Success: success
+ *         kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found
+ */
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base)
+{
+    if (0U != (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Prepare to switch to increment mode */
+    base->MER |= RTC_MER_MCE_MASK;
+    /* Write anything so the counter increments*/
+    base->MCLR = 1U;
+
+    return kStatus_Success;
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.h
new file mode 100644
index 0000000000..33ee4b8234
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_rtc.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2022, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_RTC_H_
+#define FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0 */
+/*! @} */
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+    kRTC_TimeInvalidInterruptEnable  = (1U << 0U), /*!< Time invalid interrupt.*/
+    kRTC_TimeOverflowInterruptEnable = (1U << 1U), /*!< Time overflow interrupt.*/
+    kRTC_AlarmInterruptEnable        = (1U << 2U), /*!< Alarm interrupt.*/
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    kRTC_MonotonicOverflowInterruptEnable = (1U << 3U), /*!< Monotonic Overflow Interrupt Enable */
+#endif                                                  /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+    kRTC_SecondsInterruptEnable      = (1U << 4U), /*!< Seconds interrupt.*/
+#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR)
+    kRTC_TestModeInterruptEnable      = (1U << 5U), /* test mode interrupt */
+    kRTC_FlashSecurityInterruptEnable = (1U << 6U), /* flash security interrupt */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE)
+    kRTC_TamperPinInterruptEnable = (1U << 7U), /* Tamper pin interrupt */
+#endif                                          /* FSL_FEATURE_RTC_HAS_TIR_TPIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE)
+    kRTC_SecurityModuleInterruptEnable = (1U << 8U), /* security module interrupt */
+#endif                                               /* FSL_FEATURE_RTC_HAS_TIR_SIE */
+#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE)
+    kRTC_LossOfClockInterruptEnable = (1U << 9U), /* loss of clock interrupt */
+#endif                                            /* FSL_FEATURE_RTC_HAS_TIR_LCIE */
+#endif                                            /* FSL_FEATURE_RTC_HAS_TIR */
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+    kRTC_TimeInvalidFlag  = (1U << 0U), /*!< Time invalid flag */
+    kRTC_TimeOverflowFlag = (1U << 1U), /*!< Time overflow flag */
+    kRTC_AlarmFlag        = (1U << 2U), /*!< Alarm flag*/
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+    kRTC_MonotonicOverflowFlag = (1U << 3U), /*!< Monotonic Overflow Flag */
+#endif                                       /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF)
+    kRTC_TamperInterruptDetectFlag = (1U << 4U), /*!< Tamper interrupt detect flag */
+#endif                                           /* FSL_FEATURE_RTC_HAS_SR_TIDF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR)
+    kRTC_TestModeFlag      = (1U << 5U), /* Test mode flag */
+    kRTC_FlashSecurityFlag = (1U << 6U), /* Flash security flag */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF)
+    kRTC_TamperPinFlag = (1U << 7U), /* Tamper pin flag */
+#endif                               /* FSL_FEATURE_RTC_HAS_TDR_TPF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF)
+    kRTC_SecurityTamperFlag = (1U << 8U), /* Security tamper flag */
+#endif                                    /* FSL_FEATURE_RTC_HAS_TDR_STF */
+#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF)
+    kRTC_LossOfClockTamperFlag = (1U << 9U), /* Loss of clock flag */
+#endif                                       /* FSL_FEATURE_RTC_HAS_TDR_LCTF */
+#endif                                       /* FSL_FEATURE_RTC_HAS_TDR */
+} rtc_status_flags_t;
+
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
+/*! @brief List of RTC Oscillator capacitor load settings */
+typedef enum _rtc_osc_cap_load
+{
+    kRTC_Capacitor_2p  = RTC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
+    kRTC_Capacitor_4p  = RTC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
+    kRTC_Capacitor_8p  = RTC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
+    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */
+} rtc_osc_cap_load_t;
+
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+    uint16_t year;  /*!< Range from 1970 to 2099.*/
+    uint8_t month;  /*!< Range from 1 to 12.*/
+    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
+    uint8_t hour;   /*!< Range from 0 to 23.*/
+    uint8_t minute; /*!< Range from 0 to 59.*/
+    uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+#if (defined(FSL_FEATURE_RTC_HAS_PCR) && FSL_FEATURE_RTC_HAS_PCR)
+
+/*!
+ * @brief RTC pin config structure
+ */
+typedef struct _rtc_pin_config
+{
+    bool inputLogic;       /*!< true: Tamper pin input data is logic one.
+                                false: Tamper pin input data is logic zero. */
+    bool pinActiveLow;     /*!< true: Tamper pin is active low.
+                                false: Tamper pin is active high. */
+    bool filterEnable;     /*!< true: Input filter is enabled on the tamper pin.
+                                false: Input filter is disabled on the tamper pin. */
+    bool pullSelectNegate; /*!< true: Tamper pin pull resistor direction will negate the tamper pin.
+                                false: Tamper pin pull resistor direction will assert the tamper pin. */
+    bool pullEnable;       /*!< true: Pull resistor is enabled on tamper pin.
+                                false: Pull resistor is disabled on tamper pin. */
+} rtc_pin_config_t;
+
+#endif /* FSL_FEATURE_RTC_HAS_PCR */
+
+/*!
+ * @brief RTC config structure
+ *
+ * This structure holds the configuration settings for the RTC peripheral. To initialize this
+ * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rtc_config
+{
+    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32 KHz clock;
+                                        false:Wakeup pin used to wakeup the chip  */
+    bool updateMode;               /*!< true: Registers can be written even when locked under certain
+                                        conditions, false: No writes allowed when registers are locked */
+    bool supervisorAccess;         /*!< true: Non-supervisor accesses are allowed;
+                                        false: Non-supervisor accesses are not supported */
+    uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */
+    uint32_t compensationTime;     /*!< Compensation time that is written to the TCR field in RTC TCR Register */
+} rtc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function issues a software reset if the timer invalid flag is set.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base   RTC peripheral base address
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config);
+
+/*!
+ * @brief Stops the timer and gate the RTC clock.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+    /* Stop the RTC timer */
+    base->SR &= ~RTC_SR_TCE_MASK;
+
+#if defined(RTC_CLOCKS)
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the module clock */
+    CLOCK_DisableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* RTC_CLOCKS */
+}
+
+/*!
+ * @brief Fills in the RTC config struct with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ *    config->wakeupSelect = false;
+ *    config->updateMode = false;
+ *    config->supervisorAccess = false;
+ *    config->compensationInterval = 0;
+ *    config->compensationTime = 0;
+ * @endcode
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function because writes to the RTC
+ * seconds register fail if the RTC counter is running.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to the structure where the date and time details are stored.
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to the structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base      RTC peripheral base address
+ * @param alarmTime Pointer to the structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to the structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+uint32_t RTC_GetEnabledInterrupts(RTC_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+uint32_t RTC_GetStatusFlags(RTC_Type *base);
+
+/*!
+ * @brief  Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask);
+
+/*! @}*/
+
+/*!
+ * @name Clock Source Configuration
+ * @{
+ */
+
+#if !(defined(FSL_FEATURE_RTC_HAS_NO_CR_OSCE) && FSL_FEATURE_RTC_HAS_NO_CR_OSCE)
+
+/*!
+ * @brief Enable/Disable RTC 32kHz Oscillator clock.
+ *
+ * @param base RTC peripheral base address
+ * @param enable Enable/Disable RTC 32.768 kHz clock
+ *
+ * @note After setting this bit, wait the oscillator startup time before enabling
+ *       the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+static inline void RTC_EnableOscillatorClock(RTC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR |= RTC_CR_OSCE_MASK;
+    }
+    else
+    {
+        base->CR &= ~RTC_CR_OSCE_MASK;
+    }
+}
+
+/*!
+ * @brief Set RTC clock source.
+ * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableOscillatorClock
+
+ * @param base RTC peripheral base address
+ *
+ * @note After setting this bit, wait the oscillator startup time before enabling
+ *       the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+static inline void RTC_SetClockSource(RTC_Type *base)
+{
+    /* Enable the RTC 32KHz oscillator */
+    base->CR |= RTC_CR_OSCE_MASK;
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_NO_CR_OSCE */
+
+#if (defined(FSL_FEATURE_RTC_HAS_LPO_ADJUST) && FSL_FEATURE_RTC_HAS_LPO_ADJUST)
+
+/*!
+ * @brief Enable/Disable RTC 1kHz LPO clock.
+ *
+ * @param base RTC peripheral base address
+ * @param enable Enable/Disable RTC 1kHz LPO clock
+ *
+ * @note After setting this bit, RTC prescaler increments using the LPO 1kHz clock
+ *       and not the RTC 32kHz crystal clock.
+ */
+static inline void RTC_EnableLPOClock(RTC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR |= RTC_CR_LPOS_MASK;
+    }
+    else
+    {
+        base->CR &= ~RTC_CR_LPOS_MASK;
+    }
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_LPO_ADJUST */
+
+/*! @}*/
+
+#if (defined(FSL_FEATURE_RTC_HAS_TTSR) && FSL_FEATURE_RTC_HAS_TTSR)
+
+/*!
+ * @brief Get the RTC tamper time seconds.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline uint32_t RTC_GetTamperTimeSeconds(RTC_Type *base)
+{
+    return base->TTSR;
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_TTSR */
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+    base->SR |= RTC_SR_TCE_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+    base->SR &= ~RTC_SR_TCE_MASK;
+}
+
+/*! @}*/
+
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
+/*!
+ * @brief This function sets the specified capacitor configuration for the RTC oscillator.
+ *
+ * @param base    RTC peripheral base address
+ * @param capLoad Oscillator loads to enable. This is a logical OR of members of the
+ *                enumeration ::rtc_osc_cap_load_t
+ */
+static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad)
+{
+    uint32_t reg = base->CR;
+
+    reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK);
+    reg |= capLoad;
+
+    base->CR = reg;
+}
+
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
+ * registers. The SWR bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+    base->CR |= RTC_CR_SWR_MASK;
+    base->CR &= ~RTC_CR_SWR_MASK;
+
+    /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */
+    base->TSR = 1U;
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+/*!
+ * @name Monotonic counter functions
+ * @{
+ */
+
+/*!
+ * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ *        them as a single value.
+ *
+ * @param base    RTC peripheral base address
+ * @param counter Pointer to variable where the value is stored.
+ */
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter);
+
+/*!
+ * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ *        the given single value. The Monotonic Overflow Flag in RTC_SR is cleared due to the API.
+ *
+ * @param base    RTC peripheral base address
+ * @param counter Counter value
+ */
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter);
+
+/*!
+ * @brief Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return kStatus_Success: success
+ *         kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found
+ */
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base);
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && (FSL_FEATURE_RTC_HAS_WAKEUP_PIN)
+/*!
+ * @brief Enables or disables the RTC Wakeup Pin Operation.
+ *
+ * This function enable or disable RTC Wakeup Pin.
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * @param base RTC_Type base pointer.
+ * @param enable true to enable, false to disable.
+ */
+static inline void RTC_EnableWakeUpPin(RTC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR |= RTC_CR_WPE_MASK;
+    }
+    else
+    {
+        base->CR &= ~RTC_CR_WPE_MASK;
+    }
+}
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_RTC_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.c
new file mode 100644
index 0000000000..6d69f5efb2
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.c
@@ -0,0 +1,3140 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_sai.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sai"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+/*! @brief _sai_transfer_state sai transfer state.*/
+enum
+{
+    kSAI_Busy = 0x0U, /*!< SAI is busy */
+    kSAI_Idle,        /*!< Transfer is done. */
+    kSAI_Error        /*!< Transfer error occurred. */
+};
+
+/*! @brief Typedef for sai tx interrupt handler. */
+typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief Typedef for sai rx interrupt handler. */
+typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
+
+/*! @brief check flag avalibility */
+#define IS_SAI_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL)
+
+#if defined(SAI_RSTS)
+#define SAI_RESETS_ARRAY SAI_RSTS
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief sai get rx enabled interrupt status.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param enableFlag enable flag to check.
+ * @param statusFlag status flag to check.
+ */
+static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag);
+
+/*!
+ * @brief sai get tx enabled interrupt status.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param enableFlag enable flag to check.
+ * @param statusFlag status flag to check.
+ */
+static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag);
+
+/*!
+ * @brief Set the master clock divider.
+ *
+ * This API will compute the master clock divider according to master clock frequency and master
+ * clock source clock source frequency.
+ *
+ * @param base SAI base pointer.
+ * @param mclk_Hz Mater clock frequency in Hz.
+ * @param mclkSrcClock_Hz Master clock source frequency in Hz.
+ */
+static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag);
+
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
+
+/*!
+ * @brief Set the master clock divider.
+ *
+ * This API will compute the master clock divider according to master clock frequency and master
+ * clock source clock source frequency.
+ *
+ * @param base SAI base pointer.
+ * @param mclk_Hz Mater clock frequency in Hz.
+ * @param mclkSrcClock_Hz Master clock source frequency in Hz.
+ */
+static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz);
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+
+/*!
+ * @brief Get the instance number for SAI.
+ *
+ * @param base SAI base pointer.
+ */
+static uint32_t SAI_GetInstance(I2S_Type *base);
+
+/*!
+ * @brief sends a piece of data in non-blocking way.
+ *
+ * @param base SAI base pointer
+ * @param channel start channel number.
+ * @param channelMask enabled channels mask.
+ * @param endChannel end channel numbers.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+static void SAI_WriteNonBlocking(I2S_Type *base,
+                                 uint32_t channel,
+                                 uint32_t channelMask,
+                                 uint32_t endChannel,
+                                 uint8_t bitWidth,
+                                 uint8_t *buffer,
+                                 uint32_t size);
+
+/*!
+ * @brief Receive a piece of data in non-blocking way.
+ *
+ * @param base SAI base pointer
+ * @param channel start channel number.
+ * @param channelMask enabled channels mask.
+ * @param endChannel end channel numbers.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+static void SAI_ReadNonBlocking(I2S_Type *base,
+                                uint32_t channel,
+                                uint32_t channelMask,
+                                uint32_t endChannel,
+                                uint8_t bitWidth,
+                                uint8_t *buffer,
+                                uint32_t size);
+
+/*!
+ * @brief Get classic I2S mode configurations.
+ *
+ * @param config transceiver configurations
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel
+ * @param saiChannelMask channel mask value to enable
+ */
+static void SAI_GetCommonConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Base pointer array */
+static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
+#if defined(SAI_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_saiReset[] = SAI_RESETS_ARRAY;
+#endif
+/*!@brief SAI handle pointer */
+static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
+/* IRQ number array */
+static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS;
+static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Clock name array */
+static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_tx_isr_t s_saiTxIsr;
+/*! @brief Pointer to tx IRQ handler for each instance. */
+static sai_rx_isr_t s_saiRxIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag)
+{
+    uint32_t rcsr = base->RCSR;
+
+    return IS_SAI_FLAG_SET(rcsr, enableFlag) && IS_SAI_FLAG_SET(rcsr, statusFlag);
+}
+
+static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag)
+{
+    uint32_t tcsr = base->TCSR;
+
+    return IS_SAI_FLAG_SET(tcsr, enableFlag) && IS_SAI_FLAG_SET(tcsr, statusFlag);
+}
+
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
+static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz)
+{
+    assert(mclk_Hz <= mclkSrcClock_Hz);
+
+    uint32_t sourceFreq = mclkSrcClock_Hz / 100U; /*In order to prevent overflow */
+    uint32_t targetFreq = mclk_Hz / 100U;         /*In order to prevent overflow */
+
+#if FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV
+    uint32_t postDivider = sourceFreq / targetFreq;
+
+    /* if source equal to target, then disable divider */
+    if (postDivider == 1U)
+    {
+        base->MCR &= ~I2S_MCR_DIVEN_MASK;
+    }
+    else
+    {
+        base->MCR = (base->MCR & (~I2S_MCR_DIV_MASK)) | I2S_MCR_DIV(postDivider / 2U - 1U) | I2S_MCR_DIVEN_MASK;
+    }
+#endif
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
+    uint16_t fract, divide;
+    uint32_t remaind           = 0;
+    uint32_t current_remainder = 0xFFFFFFFFU;
+    uint16_t current_fract     = 0;
+    uint16_t current_divide    = 0;
+    uint32_t mul_freq          = 0;
+    uint32_t max_fract         = 256;
+
+    /* Compute the max fract number */
+    max_fract = targetFreq * 4096U / sourceFreq + 1U;
+    if (max_fract > 256U)
+    {
+        max_fract = 256U;
+    }
+
+    /* Looking for the closet frequency */
+    for (fract = 1; fract < max_fract; fract++)
+    {
+        mul_freq = sourceFreq * fract;
+        remaind  = mul_freq % targetFreq;
+        divide   = (uint16_t)(mul_freq / targetFreq);
+
+        /* Find the exactly frequency */
+        if (remaind == 0U)
+        {
+            current_fract  = fract;
+            current_divide = (uint16_t)(mul_freq / targetFreq);
+            break;
+        }
+
+        /* Closer to next one, set the closest to next data */
+        if (remaind > mclk_Hz / 2U)
+        {
+            remaind = targetFreq - remaind;
+            divide += 1U;
+        }
+
+        /* Update the closest div and fract */
+        if (remaind < current_remainder)
+        {
+            current_fract     = fract;
+            current_divide    = divide;
+            current_remainder = remaind;
+        }
+    }
+
+    /* Fill the computed fract and divider to registers */
+    base->MDR = I2S_MDR_DIVIDE(current_divide - 1UL) | I2S_MDR_FRACT(current_fract - 1UL);
+
+    /* Waiting for the divider updated */
+    while ((base->MCR & I2S_MCR_DUF_MASK) != 0UL)
+    {
+    }
+#endif
+}
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+
+static uint32_t SAI_GetInstance(I2S_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
+    {
+        if (s_saiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_saiBases));
+
+    return instance;
+}
+
+static void SAI_WriteNonBlocking(I2S_Type *base,
+                                 uint32_t channel,
+                                 uint32_t channelMask,
+                                 uint32_t endChannel,
+                                 uint8_t bitWidth,
+                                 uint8_t *buffer,
+                                 uint32_t size)
+{
+    uint32_t i = 0, j = 0U;
+    uint8_t m            = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data        = 0;
+    uint32_t temp        = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        for (j = channel; j <= endChannel; j++)
+        {
+            if (IS_SAI_FLAG_SET((1UL << j), channelMask))
+            {
+                for (m = 0; m < bytesPerWord; m++)
+                {
+                    temp = (uint32_t)(*buffer);
+                    data |= (temp << (8U * m));
+                    buffer++;
+                }
+                base->TDR[j] = data;
+                data         = 0;
+            }
+        }
+    }
+}
+
+static void SAI_ReadNonBlocking(I2S_Type *base,
+                                uint32_t channel,
+                                uint32_t channelMask,
+                                uint32_t endChannel,
+                                uint8_t bitWidth,
+                                uint8_t *buffer,
+                                uint32_t size)
+{
+    uint32_t i = 0, j = 0;
+    uint8_t m            = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data        = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        for (j = channel; j <= endChannel; j++)
+        {
+            if (IS_SAI_FLAG_SET((1UL << j), channelMask))
+            {
+                data = base->RDR[j];
+                for (m = 0; m < bytesPerWord; m++)
+                {
+                    *buffer = (uint8_t)(data >> (8U * m)) & 0xFFU;
+                    buffer++;
+                }
+            }
+        }
+    }
+}
+
+static void SAI_GetCommonConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    (void)memset(config, 0, sizeof(sai_transceiver_t));
+
+    config->channelMask = (uint8_t)saiChannelMask;
+    /* sync mode default configurations */
+    config->syncMode = kSAI_ModeAsync;
+
+    /* master mode default */
+    config->masterSlave = kSAI_Master;
+
+    /* bit default configurations */
+    config->bitClock.bclkSrcSwap    = false;
+    config->bitClock.bclkInputDelay = false;
+    config->bitClock.bclkPolarity   = kSAI_SampleOnRisingEdge;
+    config->bitClock.bclkSource     = kSAI_BclkSourceMclkDiv;
+
+    /* frame sync default configurations */
+    config->frameSync.frameSyncWidth = (uint8_t)bitWidth;
+    config->frameSync.frameSyncEarly = true;
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+    config->frameSync.frameSyncGenerateOnDemand = false;
+#endif
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
+
+    /* serial data default configurations */
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    config->serialData.dataMode = kSAI_DataPinStateOutputZero;
+#endif
+    config->serialData.dataOrder           = kSAI_DataMSB;
+    config->serialData.dataWord0Length     = (uint8_t)bitWidth;
+    config->serialData.dataWordLength      = (uint8_t)bitWidth;
+    config->serialData.dataWordNLength     = (uint8_t)bitWidth;
+    config->serialData.dataFirstBitShifted = (uint8_t)bitWidth;
+    config->serialData.dataWordNum         = 2U;
+    config->serialData.dataMaskedWord      = (uint32_t)mode;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    config->fifo.fifoContinueOneError = true;
+#endif
+}
+
+/*!
+ * brief Initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.
+ *
+ * param base SAI base pointer
+ */
+void SAI_Init(I2S_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(SAI_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_saiReset[SAI_GetInstance(base)]);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    /* disable interrupt and DMA request*/
+    base->TCSR &=
+        ~(I2S_TCSR_FRIE_MASK | I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FRDE_MASK | I2S_TCSR_FWDE_MASK);
+    base->RCSR &=
+        ~(I2S_RCSR_FRIE_MASK | I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FRDE_MASK | I2S_RCSR_FWDE_MASK);
+#else
+    /* disable interrupt and DMA request*/
+    base->TCSR &= ~(I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FWDE_MASK);
+    base->RCSR &= ~(I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FWDE_MASK);
+#endif
+}
+
+/*!
+ * brief De-initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit
+ * or SAI_RxInit is called to enable the clock.
+ *
+ * param base SAI base pointer
+ */
+void SAI_Deinit(I2S_Type *base)
+{
+    SAI_TxEnable(base, false);
+    SAI_RxEnable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    (void)CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Resets the SAI Tx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.
+ *
+ * param base SAI base pointer
+ */
+void SAI_TxReset(I2S_Type *base)
+{
+    /* Set the software reset and FIFO reset to clear internal state */
+    base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK;
+
+    /* Clear software reset bit, this should be done by software */
+    base->TCSR &= ~I2S_TCSR_SR_MASK;
+
+    /* Reset all Tx register values */
+    base->TCR2 = 0;
+    base->TCR3 = 0;
+    base->TCR4 = 0;
+    base->TCR5 = 0;
+    base->TMR  = 0;
+}
+
+/*!
+ * brief Resets the SAI Rx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.
+ *
+ * param base SAI base pointer
+ */
+void SAI_RxReset(I2S_Type *base)
+{
+    /* Set the software reset and FIFO reset to clear internal state */
+    base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK;
+
+    /* Clear software reset bit, this should be done by software */
+    base->RCSR &= ~I2S_RCSR_SR_MASK;
+
+    /* Reset all Rx register values */
+    base->RCR2 = 0;
+    base->RCR3 = 0;
+    base->RCR4 = 0;
+    base->RCR5 = 0;
+    base->RMR  = 0;
+}
+
+/*!
+ * brief Enables/disables the SAI Tx.
+ *
+ * param base SAI base pointer
+ * param enable True means enable SAI Tx, false means disable.
+ */
+void SAI_TxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        /* If clock is sync with Rx, should enable RE bit. */
+        if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U)
+        {
+            base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK);
+        }
+        base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK);
+        /* Also need to clear the FIFO error flag before start */
+        SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag);
+    }
+    else
+    {
+        /* If Rx not in sync with Tx, then disable Tx, otherwise, shall not disable Tx */
+        if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U)
+        {
+            /* Disable TE bit */
+            base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK));
+        }
+    }
+}
+
+/*!
+ * brief Enables/disables the SAI Rx.
+ *
+ * param base SAI base pointer
+ * param enable True means enable SAI Rx, false means disable.
+ */
+void SAI_RxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        /* If clock is sync with Tx, should enable TE bit. */
+        if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U)
+        {
+            base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK);
+        }
+        base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK);
+        /* Also need to clear the FIFO error flag before start */
+        SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag);
+    }
+    else
+    {
+        /* If Tx not in sync with Rx, then disable Rx, otherwise, shall not disable Rx */
+        if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U)
+        {
+            /* Disable RE bit */
+            base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK));
+        }
+    }
+}
+
+/*!
+ * brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like TCR1~TCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * param base SAI base pointer
+ * param resetType Reset type, FIFO reset or software reset
+ */
+void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
+{
+    base->TCSR |= (uint32_t)resetType;
+
+    /* Clear the software reset */
+    base->TCSR &= ~I2S_TCSR_SR_MASK;
+}
+
+/*!
+ * brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like RCR1~RCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * param base SAI base pointer
+ * param resetType Reset type, FIFO reset or software reset
+ */
+void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
+{
+    base->RCSR |= (uint32_t)resetType;
+
+    /* Clear the software reset */
+    base->RCSR &= ~I2S_RCSR_SR_MASK;
+}
+
+/*!
+ * brief Set the Tx channel FIFO enable mask.
+ *
+ * param base SAI base pointer
+ * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
+void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
+{
+    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
+    base->TCR3 |= I2S_TCR3_TCE(mask);
+}
+
+/*!
+ * brief Set the Rx channel FIFO enable mask.
+ *
+ * param base SAI base pointer
+ * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
+void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
+{
+    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
+    base->RCR3 |= I2S_RCR3_RCE(mask);
+}
+
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)
+{
+    uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK);
+
+    val |= I2S_TCR4_MF(order);
+    base->TCR4 = val;
+}
+
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)
+{
+    uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK);
+
+    val |= I2S_RCR4_MF(order);
+    base->RCR4 = val;
+}
+
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK);
+
+    val |= I2S_TCR2_BCP(polarity);
+    base->TCR2 = val;
+}
+
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK);
+
+    val |= I2S_RCR2_BCP(polarity);
+    base->RCR2 = val;
+}
+
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK);
+
+    val |= I2S_TCR4_FSP(polarity);
+    base->TCR4 = val;
+}
+
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
+void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK);
+
+    val |= I2S_RCR4_FSP(polarity);
+    base->RCR4 = val;
+}
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * brief Set Tx FIFO packing feature.
+ *
+ * param base SAI base pointer.
+ * param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
+void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
+{
+    uint32_t val = base->TCR4;
+
+    val &= ~I2S_TCR4_FPACK_MASK;
+    val |= I2S_TCR4_FPACK(pack);
+    base->TCR4 = val;
+}
+
+/*!
+ * brief Set Rx FIFO packing feature.
+ *
+ * param base SAI base pointer.
+ * param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
+void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
+{
+    uint32_t val = base->RCR4;
+
+    val &= ~I2S_RCR4_FPACK_MASK;
+    val |= I2S_RCR4_FPACK(pack);
+    base->RCR4 = val;
+}
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
+
+/*!
+ * brief Transmitter bit clock rate configurations.
+ *
+ * param base SAI base pointer.
+ * param sourceClockHz, bit clock source frequency.
+ * param sampleRate audio data sample rate.
+ * param bitWidth, audio data bitWidth.
+ * param channelNumbers, audio channel numbers.
+ */
+void SAI_TxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
+{
+    uint32_t tcr2         = base->TCR2;
+    uint32_t bitClockDiv  = 0;
+    uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers;
+
+    assert(sourceClockHz >= bitClockFreq);
+
+    tcr2 &= ~I2S_TCR2_DIV_MASK;
+    /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+    bitClockDiv = sourceClockHz / bitClockFreq;
+    /* for the condition where the source clock is smaller than target bclk */
+    if (bitClockDiv == 0U)
+    {
+        bitClockDiv++;
+    }
+    /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+    if ((sourceClockHz / bitClockDiv) > bitClockFreq)
+    {
+        bitClockDiv++;
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+    /* if bclk same with MCLK, bypass the divider */
+    if (bitClockDiv == 1U)
+    {
+        tcr2 |= I2S_TCR2_BYP_MASK;
+    }
+    else
+#endif
+    {
+        tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1UL);
+    }
+
+    base->TCR2 = tcr2;
+}
+
+/*!
+ * brief Receiver bit clock rate configurations.
+ *
+ * param base SAI base pointer.
+ * param sourceClockHz, bit clock source frequency.
+ * param sampleRate audio data sample rate.
+ * param bitWidth, audio data bitWidth.
+ * param channelNumbers, audio channel numbers.
+ */
+void SAI_RxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
+{
+    uint32_t rcr2         = base->RCR2;
+    uint32_t bitClockDiv  = 0;
+    uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers;
+
+    assert(sourceClockHz >= bitClockFreq);
+
+    rcr2 &= ~I2S_RCR2_DIV_MASK;
+    /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+    bitClockDiv = sourceClockHz / bitClockFreq;
+    /* for the condition where the source clock is smaller than target bclk */
+    if (bitClockDiv == 0U)
+    {
+        bitClockDiv++;
+    }
+    /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+    if ((sourceClockHz / bitClockDiv) > bitClockFreq)
+    {
+        bitClockDiv++;
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+    /* if bclk same with MCLK, bypass the divider */
+    if (bitClockDiv == 1U)
+    {
+        rcr2 |= I2S_RCR2_BYP_MASK;
+    }
+    else
+#endif
+    {
+        rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1UL);
+    }
+
+    base->RCR2 = rcr2;
+}
+
+/*!
+ * brief Transmitter Bit clock configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
+{
+    uint32_t tcr2 = base->TCR2;
+
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave))
+    {
+        assert(config != NULL);
+
+        tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK);
+        tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) |
+                I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource);
+    }
+    else
+    {
+        tcr2 &= ~(I2S_TCR2_BCD_MASK);
+        tcr2 |= I2S_TCR2_BCP(config->bclkPolarity);
+    }
+
+    base->TCR2 = tcr2;
+}
+
+/*!
+ * brief Receiver Bit clock configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
+{
+    uint32_t rcr2 = base->RCR2;
+
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave))
+    {
+        assert(config != NULL);
+
+        rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK);
+        rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) |
+                I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource);
+    }
+    else
+    {
+        rcr2 &= ~(I2S_RCR2_BCD_MASK);
+        rcr2 |= I2S_RCR2_BCP(config->bclkPolarity);
+    }
+
+    base->RCR2 = rcr2;
+}
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*!
+ * brief Master clock configurations.
+ *
+ * param base SAI base pointer.
+ * param config master clock configurations.
+ */
+void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)
+{
+    assert(config != NULL);
+
+#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+    uint32_t val = 0;
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    /* Master clock source setting */
+    val       = (base->MCR & ~I2S_MCR_MICS_MASK);
+    base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+#endif
+
+    /* Configure Master clock output enable */
+    val       = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
+#endif /* FSL_FEATURE_SAI_HAS_MCR */
+
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
+    /* Check if master clock divider enabled, then set master clock divider */
+    if (config->mclkOutputEnable)
+    {
+        SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+}
+#endif
+
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+/*!
+ * brief SAI transmitter fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param config fifo configurations.
+ */
+void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
+{
+    assert(config != NULL);
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((config->fifoWatermark == 0U) ||
+        (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base))))
+    {
+        config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U);
+    }
+#endif
+
+    uint32_t tcr4 = base->TCR4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
+    tcr4 &= ~I2S_TCR4_FCOMB_MASK;
+    tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    tcr4 &= ~I2S_TCR4_FCONT_MASK;
+    /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX
+     * not work */
+    if (base->TMR == 0U)
+    {
+        tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError);
+    }
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    tcr4 &= ~I2S_TCR4_FPACK_MASK;
+    tcr4 |= I2S_TCR4_FPACK(config->fifoPacking);
+#endif
+
+    base->TCR4 = tcr4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark);
+#endif
+}
+
+/*!
+ * brief SAI receiver fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param config fifo configurations.
+ */
+void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
+{
+    assert(config != NULL);
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((config->fifoWatermark == 0U) ||
+        (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base))))
+    {
+        config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U);
+    }
+#endif
+    uint32_t rcr4 = base->RCR4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
+    rcr4 &= ~I2S_RCR4_FCOMB_MASK;
+    rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    rcr4 &= ~I2S_RCR4_FCONT_MASK;
+    rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    rcr4 &= ~I2S_RCR4_FPACK_MASK;
+    rcr4 |= I2S_RCR4_FPACK(config->fifoPacking);
+#endif
+
+    base->RCR4 = rcr4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark);
+#endif
+}
+#endif
+
+/*!
+ * brief SAI transmitter Frame sync configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
+{
+    assert(config != NULL);
+    assert((config->frameSyncWidth - 1UL) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT));
+
+    uint32_t tcr4 = base->TCR4;
+
+    tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK);
+
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+    tcr4 &= ~I2S_TCR4_ONDEM_MASK;
+    tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand);
+#endif
+
+    tcr4 |=
+        I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) |
+        I2S_TCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) |
+        I2S_TCR4_SYWD(config->frameSyncWidth - 1UL);
+
+    base->TCR4 = tcr4;
+}
+
+/*!
+ * brief SAI receiver Frame sync configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
+{
+    assert(config != NULL);
+    assert((config->frameSyncWidth - 1UL) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT));
+
+    uint32_t rcr4 = base->RCR4;
+
+    rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK);
+
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+    rcr4 &= ~I2S_RCR4_ONDEM_MASK;
+    rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand);
+#endif
+
+    rcr4 |=
+        I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) |
+        I2S_RCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) |
+        I2S_RCR4_SYWD(config->frameSyncWidth - 1UL);
+
+    base->RCR4 = rcr4;
+}
+
+/*!
+ * brief SAI transmitter Serial data configurations.
+ *
+ * param base SAI base pointer.
+ * param config serial data configurations.
+ */
+void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tcr4 = base->TCR4;
+
+    base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1UL) | I2S_TCR5_W0W(config->dataWord0Length - 1UL) |
+                 I2S_TCR5_FBT(config->dataFirstBitShifted - 1UL);
+    base->TMR = config->dataMaskedWord;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX
+     * not work */
+    if (config->dataMaskedWord > 0U)
+    {
+        tcr4 &= ~I2S_TCR4_FCONT_MASK;
+    }
+#endif
+    tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK);
+    tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1UL) | I2S_TCR4_MF(config->dataOrder);
+
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    tcr4 &= ~I2S_TCR4_CHMOD_MASK;
+    tcr4 |= I2S_TCR4_CHMOD(config->dataMode);
+#endif
+
+    base->TCR4 = tcr4;
+}
+
+/*!
+ * @brief SAI receiver Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t rcr4 = base->RCR4;
+
+    base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1UL) | I2S_RCR5_W0W(config->dataWord0Length - 1UL) |
+                 I2S_RCR5_FBT(config->dataFirstBitShifted - 1UL);
+    base->RMR = config->dataMaskedWord;
+
+    rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK);
+    rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1uL) | I2S_RCR4_MF(config->dataOrder);
+
+    base->RCR4 = rcr4;
+}
+
+/*!
+ * brief SAI transmitter configurations.
+ *
+ * param base SAI base pointer.
+ * param config transmitter configurations.
+ */
+void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)
+{
+    assert(config != NULL);
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint8_t i           = 0U;
+    uint32_t val        = 0U;
+    uint8_t channelNums = 0U;
+
+    /* reset transmitter */
+    SAI_TxReset(base);
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (config->channelMask == 0U)
+    {
+        config->channelMask = 1U << config->startChannel;
+    }
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (IS_SAI_FLAG_SET(1UL << i, config->channelMask))
+        {
+            channelNums++;
+            config->endChannel = i;
+        }
+    }
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (IS_SAI_FLAG_SET((1UL << i), config->channelMask))
+        {
+            config->startChannel = i;
+            break;
+        }
+    }
+
+    config->channelNums = channelNums;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (config->channelNums > 1U)
+    {
+        base->TCR4 &= ~I2S_TCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
+    base->TCR3 |= I2S_TCR3_TCE(config->channelMask);
+
+    if (config->syncMode == kSAI_ModeAsync)
+    {
+        val = base->TCR2;
+        val &= ~I2S_TCR2_SYNC_MASK;
+        base->TCR2 = (val | I2S_TCR2_SYNC(0U));
+    }
+    if (config->syncMode == kSAI_ModeSync)
+    {
+        val = base->TCR2;
+        val &= ~I2S_TCR2_SYNC_MASK;
+        base->TCR2 = (val | I2S_TCR2_SYNC(1U));
+        /* If sync with Rx, should set Rx to async mode */
+        val = base->RCR2;
+        val &= ~I2S_RCR2_SYNC_MASK;
+        base->RCR2 = (val | I2S_RCR2_SYNC(0U));
+    }
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
+    if (config->syncMode == kSAI_ModeSyncWithOtherTx)
+    {
+        val = base->TCR2;
+        val &= ~I2S_TCR2_SYNC_MASK;
+        base->TCR2 = (val | I2S_TCR2_SYNC(2U));
+    }
+    if (config->syncMode == kSAI_ModeSyncWithOtherRx)
+    {
+        val = base->TCR2;
+        val &= ~I2S_TCR2_SYNC_MASK;
+        base->TCR2 = (val | I2S_TCR2_SYNC(3U));
+    }
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
+
+    /* bit clock configurations */
+    SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock);
+    /* serial data configurations */
+    SAI_TxSetSerialDataConfig(base, &config->serialData);
+    /* frame sync configurations */
+    SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync);
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+    /* fifo configurations */
+    SAI_TxSetFifoConfig(base, &config->fifo);
+#endif
+}
+
+/*!
+ * brief SAI transmitter transfer configurations.
+ *
+ * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param config tranmitter configurations.
+ */
+void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+    assert(config->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+
+    handle->bitWidth = config->serialData.dataWordNLength;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((config->fifo.fifoWatermark == 0U) ||
+        (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base))))
+    {
+        config->fifo.fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U);
+    }
+    handle->watermark = config->fifo.fifoWatermark;
+#endif
+
+    /* transmitter configurations */
+    SAI_TxSetConfig(base, config);
+
+    handle->channel = config->startChannel;
+    /* used for multi channel */
+    handle->channelMask = config->channelMask;
+    handle->channelNums = config->channelNums;
+    handle->endChannel  = config->endChannel;
+}
+
+/*!
+ * brief SAI receiver configurations.
+ *
+ * param base SAI base pointer.
+ * param config transmitter configurations.
+ */
+void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)
+{
+    assert(config != NULL);
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint8_t i           = 0U;
+    uint32_t val        = 0U;
+    uint8_t channelNums = 0U;
+
+    /* reset receiver */
+    SAI_RxReset(base);
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (config->channelMask == 0U)
+    {
+        config->channelMask = 1U << config->startChannel;
+    }
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (IS_SAI_FLAG_SET((1UL << i), config->channelMask))
+        {
+            channelNums++;
+            config->endChannel = i;
+        }
+    }
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (IS_SAI_FLAG_SET((1UL << i), config->channelMask))
+        {
+            config->startChannel = i;
+            break;
+        }
+    }
+
+    config->channelNums = channelNums;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (config->channelNums > 1U)
+    {
+        base->RCR4 &= ~I2S_RCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
+    base->RCR3 |= I2S_RCR3_RCE(config->channelMask);
+
+    /* Set Sync mode */
+    if (config->syncMode == kSAI_ModeAsync)
+    {
+        val = base->RCR2;
+        val &= ~I2S_RCR2_SYNC_MASK;
+        base->RCR2 = (val | I2S_RCR2_SYNC(0U));
+    }
+    if (config->syncMode == kSAI_ModeSync)
+    {
+        val = base->RCR2;
+        val &= ~I2S_RCR2_SYNC_MASK;
+        base->RCR2 = (val | I2S_RCR2_SYNC(1U));
+        /* If sync with Tx, should set Tx to async mode */
+        val = base->TCR2;
+        val &= ~I2S_TCR2_SYNC_MASK;
+        base->TCR2 = (val | I2S_TCR2_SYNC(0U));
+    }
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
+    if (config->syncMode == kSAI_ModeSyncWithOtherTx)
+    {
+        val = base->RCR2;
+        val &= ~I2S_RCR2_SYNC_MASK;
+        base->RCR2 = (val | I2S_RCR2_SYNC(2U));
+    }
+    if (config->syncMode == kSAI_ModeSyncWithOtherRx)
+    {
+        val = base->RCR2;
+        val &= ~I2S_RCR2_SYNC_MASK;
+        base->RCR2 = (val | I2S_RCR2_SYNC(3U));
+    }
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
+
+    /* bit clock configurations */
+    SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock);
+    /* serial data configurations */
+    SAI_RxSetSerialDataConfig(base, &config->serialData);
+    /* frame sync configurations */
+    SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync);
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+    /* fifo configurations */
+    SAI_RxSetFifoConfig(base, &config->fifo);
+#endif
+}
+
+/*!
+ * brief SAI receiver transfer configurations.
+ *
+ * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param config tranmitter configurations.
+ */
+void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+
+    handle->bitWidth = config->serialData.dataWordNLength;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((config->fifo.fifoWatermark == 0U) ||
+        (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base))))
+    {
+        config->fifo.fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U);
+    }
+    handle->watermark = config->fifo.fifoWatermark;
+#endif
+
+    /* receiver configurations */
+    SAI_RxSetConfig(base, config);
+
+    handle->channel = config->startChannel;
+    /* used for multi channel */
+    handle->channelMask = config->channelMask;
+    handle->channelNums = config->channelNums;
+    handle->endChannel  = config->endChannel;
+}
+
+/*!
+ * brief Get classic I2S mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetClassicI2SConfig(sai_transceiver_t *config,
+                             sai_word_width_t bitWidth,
+                             sai_mono_stereo_t mode,
+                             uint32_t saiChannelMask)
+{
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+}
+
+/*!
+ * brief Get left justified mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get right justified mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetRightJustifiedConfig(sai_transceiver_t *config,
+                                 sai_word_width_t bitWidth,
+                                 sai_mono_stereo_t mode,
+                                 uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get DSP mode configurations.
+ *
+ * note DSP mode is also called PCM mode which support MODE A and MODE B,
+ * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
+ * code
+ * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+ * config->frameSync.frameSyncEarly    = true;
+ * SAI_TxSetConfig(base, config)
+ * endcode
+ *
+ * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
+ * code
+ * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+ * SAI_TxSetConfig(base, config)
+ * endcode
+ *
+ * param config transceiver configurations.
+ * param frameSyncWidth length of frame sync.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask mask value of the channel to enable.
+ */
+void SAI_GetDSPConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      sai_mono_stereo_t mode,
+                      uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    /* frame sync default configurations */
+    switch (frameSyncWidth)
+    {
+        case kSAI_FrameSyncLenOneBitClk:
+            config->frameSync.frameSyncWidth = 1U;
+            break;
+        default:
+            assert(false);
+            break;
+    }
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get TDM mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetTDMConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      uint32_t dataWordNum,
+                      uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+    assert(dataWordNum <= 32U);
+
+    SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask);
+
+    /* frame sync default configurations */
+    switch (frameSyncWidth)
+    {
+        case kSAI_FrameSyncLenOneBitClk:
+            config->frameSync.frameSyncWidth = 1U;
+            break;
+        case kSAI_FrameSyncLenPerWordWidth:
+            break;
+        default:
+            assert(false);
+            break;
+    }
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+    config->serialData.dataWordNum      = (uint8_t)dataWordNum;
+}
+
+/*!
+ * brief Sends data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
+void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    uint32_t i            = 0;
+    uint32_t bytesPerWord = bitWidth / 8U;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - base->TCR1) * bytesPerWord);
+#endif
+
+    while (i < size)
+    {
+        /* Wait until it can write data */
+        while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)))
+        {
+        }
+
+        SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
+        i += bytesPerWord;
+    }
+
+    /* Wait until the last data is sent */
+    while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)))
+    {
+    }
+}
+
+/*!
+ * brief Sends data to multi channel using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param channelMask channel mask.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
+void SAI_WriteMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t i = 0, j = 0;
+    uint32_t bytesPerWord = bitWidth / 8U;
+    uint32_t channelNums = 0U, endChannel = 0U;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - base->TCR1) * bytesPerWord);
+#endif
+
+    for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++)
+    {
+        if (IS_SAI_FLAG_SET((1UL << i), channelMask))
+        {
+            channelNums++;
+            endChannel = i;
+        }
+    }
+
+    bytesPerWord *= channelNums;
+
+    while (j < size)
+    {
+        /* Wait until it can write data */
+        while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)))
+        {
+        }
+
+        SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
+                             bytesPerWord * channelNums);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
+        j += bytesPerWord * channelNums;
+    }
+
+    /* Wait until the last data is sent */
+    while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)))
+    {
+    }
+}
+
+/*!
+ * brief Receives multi channel data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param channelMask channel mask.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
+void SAI_ReadMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t i = 0, j = 0;
+    uint32_t bytesPerWord = bitWidth / 8U;
+    uint32_t channelNums = 0U, endChannel = 0U;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    bytesPerWord = base->RCR1 * bytesPerWord;
+#endif
+    for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++)
+    {
+        if (IS_SAI_FLAG_SET((1UL << i), channelMask))
+        {
+            channelNums++;
+            endChannel = i;
+        }
+    }
+
+    bytesPerWord *= channelNums;
+
+    while (j < size)
+    {
+        /* Wait until data is received */
+        while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK)))
+        {
+        }
+
+        SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
+                            bytesPerWord * channelNums);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
+        j += bytesPerWord * channelNums;
+    }
+}
+
+/*!
+ * brief Receives data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
+void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    uint32_t i            = 0;
+    uint32_t bytesPerWord = bitWidth / 8U;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    bytesPerWord = base->RCR1 * bytesPerWord;
+#endif
+
+    while (i < size)
+    {
+        /* Wait until data is received */
+        while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK)))
+        {
+        }
+
+        SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
+        i += bytesPerWord;
+    }
+}
+
+/*!
+ * brief Initializes the SAI Tx handle.
+ *
+ * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SAI base pointer
+ * param handle SAI handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function
+ */
+void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
+{
+    assert(handle != NULL);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    s_saiHandle[SAI_GetInstance(base)][0] = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->base     = base;
+
+    /* Set the isr pointer */
+    s_saiTxIsr = SAI_TransferTxHandleIRQ;
+
+    /* Enable Tx irq */
+    (void)EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
+}
+
+/*!
+ * brief Initializes the SAI Rx handle.
+ *
+ * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function.
+ */
+void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
+{
+    assert(handle != NULL);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    s_saiHandle[SAI_GetInstance(base)][1] = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->base     = base;
+
+    /* Set the isr pointer */
+    s_saiRxIsr = SAI_TransferRxHandleIRQ;
+
+    /* Enable Rx irq */
+    (void)EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
+}
+
+/*!
+ * brief Performs an interrupt non-blocking send transfer on SAI.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the sai_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SAI_TxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+
+    /* Check if the queue is full */
+    if (handle->saiQueue[handle->queueUser].data != NULL)
+    {
+        return kStatus_SAI_QueueFull;
+    }
+
+    /* Add into queue */
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
+    handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->queueUser                            = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE;
+
+    /* Set the state to busy */
+    handle->state = (uint32_t)kSAI_Busy;
+
+    /* Enable interrupt */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    /* Use FIFO request interrupt and fifo error*/
+    SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK);
+#else
+    SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    /* Enable Tx transfer */
+    SAI_TxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs an interrupt non-blocking receive transfer on SAI.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * param base SAI base pointer
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the sai_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SAI_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+
+    /* Check if the queue is full */
+    if (handle->saiQueue[handle->queueUser].data != NULL)
+    {
+        return kStatus_SAI_QueueFull;
+    }
+
+    /* Add into queue */
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
+    handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->queueUser                            = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE;
+
+    /* Set state to busy */
+    handle->state = (uint32_t)kSAI_Busy;
+
+/* Enable interrupt */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    /* Use FIFO request interrupt and fifo error*/
+    SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK);
+#else
+    SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    /* Enable Rx transfer */
+    SAI_RxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets a set byte count.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param count Bytes count sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status           = kStatus_Success;
+    uint32_t queueDriverIndex = handle->queueDriver;
+
+    if (handle->state != (uint32_t)kSAI_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Gets a received byte count.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param count Bytes count received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status           = kStatus_Success;
+    uint32_t queueDriverIndex = handle->queueDriver;
+
+    if (handle->state != (uint32_t)kSAI_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
+void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Stop Tx transfer and disable interrupt */
+    SAI_TxEnable(base, false);
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    /* Use FIFO request interrupt and fifo error */
+    SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK);
+#else
+    SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    handle->state = (uint32_t)kSAI_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Aborts the current IRQ receive.
+ *
+ * note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SAI base pointer
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
+void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Stop Tx transfer and disable interrupt */
+    SAI_RxEnable(base, false);
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    /* Use FIFO request interrupt and fifo error */
+    SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK);
+#else
+    SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    handle->state = (uint32_t)kSAI_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Terminate all SAI send.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortSend.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
+void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Abort the current transfer */
+    SAI_TransferAbortSend(base, handle);
+
+    /* Clear all the internal information */
+    (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue));
+    (void)memset(handle->transferSize, 0, sizeof(handle->transferSize));
+
+    handle->queueUser   = 0U;
+    handle->queueDriver = 0U;
+}
+
+/*!
+ * brief Terminate all SAI receive.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortReceive.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
+void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Abort the current transfer */
+    SAI_TransferAbortReceive(base, handle);
+
+    /* Clear all the internal information */
+    (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue));
+    (void)memset(handle->transferSize, 0, sizeof(handle->transferSize));
+
+    handle->queueUser   = 0U;
+    handle->queueDriver = 0U;
+}
+
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure.
+ */
+void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    uint8_t *buffer   = handle->saiQueue[handle->queueDriver].data;
+    uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums;
+
+    /* Handle Error */
+    if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FEF_MASK))
+    {
+        /* Clear FIFO error flag to continue transfer */
+        SAI_TxClearStatusFlags(base, I2S_TCSR_FEF_MASK);
+
+        /* Reset FIFO for safety */
+        SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO);
+
+        /* Call the callback */
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData);
+        }
+    }
+
+/* Handle transfer */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FRF_MASK))
+    {
+        /* Judge if the data need to transmit is less than space */
+        size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize),
+                          (size_t)(((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - handle->watermark) * dataSize));
+
+        /* Copy the data from sai buffer to FIFO */
+        SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                             size);
+
+        /* Update the internal counter */
+        handle->saiQueue[handle->queueDriver].dataSize -= size;
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
+    }
+#else
+    if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))
+    {
+        size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
+
+        SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                             size);
+
+        /* Update internal counter */
+        handle->saiQueue[handle->queueDriver].dataSize -= size;
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    /* If finished a block, call the callback function */
+    if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
+    {
+        (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE;
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->saiQueue[handle->queueDriver].data == NULL)
+    {
+        SAI_TransferAbortSend(base, handle);
+    }
+}
+
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure.
+ */
+void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    uint8_t *buffer   = handle->saiQueue[handle->queueDriver].data;
+    uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums;
+
+    /* Handle Error */
+    if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FEF_MASK))
+    {
+        /* Clear FIFO error flag to continue transfer */
+        SAI_RxClearStatusFlags(base, I2S_TCSR_FEF_MASK);
+
+        /* Reset FIFO for safety */
+        SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO);
+
+        /* Call the callback */
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData);
+        }
+    }
+
+/* Handle transfer */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FRF_MASK))
+    {
+        /* Judge if the data need to transmit is less than space */
+        size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), handle->watermark * dataSize);
+
+        /* Copy the data from sai buffer to FIFO */
+        SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                            size);
+
+        /* Update the internal counter */
+        handle->saiQueue[handle->queueDriver].dataSize -= size;
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
+    }
+#else
+    if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))
+    {
+        size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
+
+        SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                            size);
+
+        /* Update internal state */
+        handle->saiQueue[handle->queueDriver].dataSize -= size;
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    /* If finished a block, call the callback function */
+    if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
+    {
+        (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE;
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->saiQueue[handle->queueDriver].data == NULL)
+    {
+        SAI_TransferAbortReceive(base, handle);
+    }
+}
+
+#if defined(I2S0)
+void I2S0_DriverIRQHandler(void);
+void I2S0_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S0, s_saiHandle[0][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S0, s_saiHandle[0][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S0_Tx_DriverIRQHandler(void);
+void I2S0_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[0][0] != NULL);
+    s_saiTxIsr(I2S0, s_saiHandle[0][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S0_Rx_DriverIRQHandler(void);
+void I2S0_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[0][1] != NULL);
+    s_saiRxIsr(I2S0, s_saiHandle[0][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* I2S0*/
+
+#if defined(I2S1)
+void I2S1_DriverIRQHandler(void);
+void I2S1_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S1, s_saiHandle[1][1]);
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S1, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S1_Tx_DriverIRQHandler(void);
+void I2S1_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[1][0] != NULL);
+    s_saiTxIsr(I2S1, s_saiHandle[1][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S1_Rx_DriverIRQHandler(void);
+void I2S1_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[1][1] != NULL);
+    s_saiRxIsr(I2S1, s_saiHandle[1][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* I2S1*/
+
+#if defined(I2S2)
+void I2S2_DriverIRQHandler(void);
+void I2S2_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S2_Tx_DriverIRQHandler(void);
+void I2S2_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][0] != NULL);
+    s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S2_Rx_DriverIRQHandler(void);
+void I2S2_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][1] != NULL);
+    s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* I2S2*/
+
+#if defined(I2S3)
+void I2S3_DriverIRQHandler(void);
+void I2S3_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S3_Tx_DriverIRQHandler(void);
+void I2S3_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][0] != NULL);
+    s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S3_Rx_DriverIRQHandler(void);
+void I2S3_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][1] != NULL);
+    s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* I2S3*/
+
+#if defined(I2S4)
+void I2S4_DriverIRQHandler(void);
+void I2S4_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S4, s_saiHandle[4][1]);
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S4, s_saiHandle[4][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S4_Tx_DriverIRQHandler(void);
+void I2S4_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[4][0] != NULL);
+    s_saiTxIsr(I2S4, s_saiHandle[4][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S4_Rx_DriverIRQHandler(void);
+void I2S4_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[4][1] != NULL);
+    s_saiRxIsr(I2S4, s_saiHandle[4][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \
+    defined(I2S6)
+void I2S56_DriverIRQHandler(void);
+void I2S56_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    I2S_Type *base = s_saiHandle[5][1]->base;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(base, s_saiHandle[5][1]);
+    }
+
+    base = s_saiHandle[5][0]->base;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(base, s_saiHandle[5][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S56_Tx_DriverIRQHandler(void);
+void I2S56_Tx_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    assert(s_saiHandle[5][0] != NULL);
+    s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S56_Rx_DriverIRQHandler(void);
+void I2S56_Rx_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    assert(s_saiHandle[5][1] != NULL);
+    s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+#else
+
+#if defined(I2S5)
+void I2S5_DriverIRQHandler(void);
+void I2S5_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S5, s_saiHandle[5][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S5, s_saiHandle[5][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S5_Tx_DriverIRQHandler(void);
+void I2S5_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[5][0] != NULL);
+    s_saiTxIsr(I2S5, s_saiHandle[5][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S5_Rx_DriverIRQHandler(void);
+void I2S5_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[5][1] != NULL);
+    s_saiRxIsr(I2S5, s_saiHandle[5][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(I2S6)
+void I2S6_DriverIRQHandler(void);
+void I2S6_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(I2S6, s_saiHandle[6][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(I2S6, s_saiHandle[6][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S6_Tx_DriverIRQHandler(void);
+void I2S6_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[6][0] != NULL);
+    s_saiTxIsr(I2S6, s_saiHandle[6][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void I2S6_Rx_DriverIRQHandler(void);
+void I2S6_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[6][1] != NULL);
+    s_saiRxIsr(I2S6, s_saiHandle[6][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+
+#if defined(AUDIO__SAI0)
+void AUDIO_SAI0_INT_DriverIRQHandler(void);
+void AUDIO_SAI0_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]);
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* AUDIO__SAI0 */
+
+#if defined(AUDIO__SAI1)
+void AUDIO_SAI1_INT_DriverIRQHandler(void);
+void AUDIO_SAI1_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* AUDIO__SAI1 */
+
+#if defined(AUDIO__SAI2)
+void AUDIO_SAI2_INT_DriverIRQHandler(void);
+void AUDIO_SAI2_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* AUDIO__SAI2 */
+
+#if defined(AUDIO__SAI3)
+void AUDIO_SAI3_INT_DriverIRQHandler(void);
+void AUDIO_SAI3_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(AUDIO__SAI6)
+void AUDIO_SAI6_INT_DriverIRQHandler(void);
+void AUDIO_SAI6_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* AUDIO__SAI6 */
+
+#if defined(AUDIO__SAI7)
+void AUDIO_SAI7_INT_DriverIRQHandler(void);
+void AUDIO_SAI7_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[7][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[7][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[7][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[7][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* AUDIO__SAI7 */
+
+#if defined(ADMA__SAI0)
+void ADMA_SAI0_INT_DriverIRQHandler(void);
+void ADMA_SAI0_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI0 */
+
+#if defined(ADMA__SAI1)
+void ADMA_SAI1_INT_DriverIRQHandler(void);
+void ADMA_SAI1_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI1 */
+
+#if defined(ADMA__SAI2)
+void ADMA_SAI2_INT_DriverIRQHandler(void);
+void ADMA_SAI2_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI2 */
+
+#if defined(ADMA__SAI3)
+void ADMA_SAI3_INT_DriverIRQHandler(void);
+void ADMA_SAI3_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI3 */
+
+#if defined(ADMA__SAI4)
+void ADMA_SAI4_INT_DriverIRQHandler(void);
+void ADMA_SAI4_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]);
+    }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI4 */
+
+#if defined(ADMA__SAI5)
+void ADMA_SAI5_INT_DriverIRQHandler(void);
+void ADMA_SAI5_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) &&
+        SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) &&
+        SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                        (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* ADMA__SAI5 */
+
+#if defined(SAI0)
+void SAI0_DriverIRQHandler(void);
+void SAI0_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI0, s_saiHandle[0][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI0, s_saiHandle[0][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI0 */
+
+#if defined(SAI1)
+void SAI1_DriverIRQHandler(void);
+void SAI1_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI1, s_saiHandle[1][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI1 */
+
+#if defined(SAI2)
+void SAI2_DriverIRQHandler(void);
+void SAI2_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI2, s_saiHandle[2][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI2, s_saiHandle[2][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI2 */
+
+#if defined(SAI3)
+void SAI3_DriverIRQHandler(void);
+void SAI3_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI3, s_saiHandle[3][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI3, s_saiHandle[3][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void SAI3_TX_DriverIRQHandler(void);
+void SAI3_TX_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][0] != NULL);
+    s_saiTxIsr(SAI3, s_saiHandle[3][0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void SAI3_RX_DriverIRQHandler(void);
+void SAI3_RX_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][1] != NULL);
+    s_saiRxIsr(SAI3, s_saiHandle[3][1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI3 */
+
+#if defined(SAI4)
+void SAI4_DriverIRQHandler(void);
+void SAI4_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI4, s_saiHandle[4][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI4, s_saiHandle[4][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI4 */
+
+#if defined(SAI5)
+void SAI5_DriverIRQHandler(void);
+void SAI5_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI5, s_saiHandle[5][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI5, s_saiHandle[5][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI5 */
+
+#if defined(SAI6)
+void SAI6_DriverIRQHandler(void);
+void SAI6_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiRxIsr(SAI6, s_saiHandle[6][1]);
+    }
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK)))
+#else
+    if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK),
+                                                                       (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK)))
+#endif
+    {
+        s_saiTxIsr(SAI6, s_saiHandle[6][0]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* SAI6 */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.h
new file mode 100644
index 0000000000..16da4fd98e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai.h
@@ -0,0 +1,1437 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SAI_H_
+#define FSL_SAI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sai_driver SAI Driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2 */
+/*! @} */
+
+/*! @brief _sai_status_t, SAI return status.*/
+enum
+{
+    kStatus_SAI_TxBusy    = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */
+    kStatus_SAI_RxBusy    = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */
+    kStatus_SAI_TxError   = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */
+    kStatus_SAI_RxError   = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */
+    kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */
+    kStatus_SAI_TxIdle    = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */
+    kStatus_SAI_RxIdle    = MAKE_STATUS(kStatusGroup_SAI, 6)  /*!< SAI Rx is idle */
+};
+
+/*! @brief _sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific */
+enum
+{
+    kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */
+    kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */
+    kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */
+    kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */
+    kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */
+    kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */
+    kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */
+    kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */
+};
+
+/*! @brief Define the SAI bus type */
+typedef enum _sai_protocol
+{
+    kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/
+    kSAI_BusRightJustified,       /*!< Uses right justified format. */
+    kSAI_BusI2S,                  /*!< Uses I2S format. */
+    kSAI_BusPCMA,                 /*!< Uses I2S PCM A format.*/
+    kSAI_BusPCMB                  /*!< Uses I2S PCM B format. */
+} sai_protocol_t;
+
+/*! @brief Master or slave mode */
+typedef enum _sai_master_slave
+{
+    kSAI_Master                      = 0x0U, /*!< Master mode include bclk and frame sync */
+    kSAI_Slave                       = 0x1U, /*!< Slave mode  include bclk and frame sync */
+    kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */
+    kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */
+} sai_master_slave_t;
+
+/*! @brief Mono or stereo audio format */
+typedef enum _sai_mono_stereo
+{
+    kSAI_Stereo = 0x0U, /*!< Stereo sound. */
+    kSAI_MonoRight,     /*!< Only Right channel have sound. */
+    kSAI_MonoLeft       /*!< Only left channel have sound. */
+} sai_mono_stereo_t;
+
+/*! @brief SAI data order, MSB or LSB */
+typedef enum _sai_data_order
+{
+    kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */
+    kSAI_DataMSB         /*!< MSB bit transferred first */
+} sai_data_order_t;
+
+/*! @brief SAI clock polarity, active high or low */
+typedef enum _sai_clock_polarity
+{
+    kSAI_PolarityActiveHigh  = 0x0U, /*!< Drive outputs on rising edge */
+    kSAI_PolarityActiveLow   = 0x1U, /*!< Drive outputs on falling edge */
+    kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */
+    kSAI_SampleOnRisingEdge  = 0x1U, /*!< Sample inputs on rising edge */
+} sai_clock_polarity_t;
+
+/*! @brief Synchronous or asynchronous mode */
+typedef enum _sai_sync_mode
+{
+    kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */
+    kSAI_ModeSync,         /*!< Synchronous mode (with receiver or transmit) */
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
+    kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */
+    kSAI_ModeSyncWithOtherRx  /*!< Synchronous with another SAI receiver */
+#endif                        /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
+} sai_sync_mode_t;
+
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+/*! @brief Mater clock source */
+typedef enum _sai_mclk_source
+{
+    kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */
+    kSAI_MclkSourceSelect1,       /*!< Master clock from source 1 */
+    kSAI_MclkSourceSelect2,       /*!< Master clock from source 2 */
+    kSAI_MclkSourceSelect3        /*!< Master clock from source 3 */
+} sai_mclk_source_t;
+#endif
+
+/*! @brief Bit clock source */
+typedef enum _sai_bclk_source
+{
+    kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */
+    /* General device bit source definition */
+    kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */
+    kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2  */
+    kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */
+    /* Kinetis device bit clock source definition */
+    kSAI_BclkSourceMclkDiv   = 0x1U, /*!< Bit clock using master clock divider */
+    kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device  */
+    kSAI_BclkSourceOtherSai1 = 0x3U  /*!< Bit clock from other SAI device */
+} sai_bclk_source_t;
+
+/*! @brief _sai_interrupt_enable_t, The SAI interrupt enable flag */
+enum
+{
+    kSAI_WordStartInterruptEnable =
+        I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */
+    kSAI_SyncErrorInterruptEnable   = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */
+    kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */
+    kSAI_FIFOErrorInterruptEnable   = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */
+#endif                                                    /* FSL_FEATURE_SAI_HAS_FIFO */
+};
+
+/*! @brief _sai_dma_enable_t, The DMA request sources */
+enum
+{
+    kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */
+#endif                                              /* FSL_FEATURE_SAI_HAS_FIFO */
+};
+
+/*! @brief _sai_flags, The SAI status flag */
+enum
+{
+    kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */
+    kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */
+    kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */
+#endif                                        /* FSL_FEATURE_SAI_HAS_FIFO */
+    kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */
+};
+
+/*! @brief The reset type */
+typedef enum _sai_reset_type
+{
+    kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */
+    kSAI_ResetTypeFIFO     = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */
+    kSAI_ResetAll          = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */
+} sai_reset_type_t;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * @brief The SAI packing mode
+ * The mode includes 8 bit and 16 bit packing.
+ */
+typedef enum _sai_fifo_packing
+{
+    kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */
+    kSAI_FifoPacking8bit     = 0x2U, /*!< 8 bit packing enabled */
+    kSAI_FifoPacking16bit    = 0x3U  /*!< 16bit packing enabled */
+} sai_fifo_packing_t;
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
+
+/*! @brief SAI user configuration structure */
+typedef struct _sai_config
+{
+    sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
+    sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */
+#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+    bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    sai_mclk_source_t mclkSource; /*!< Master Clock source */
+#endif                            /* FSL_FEATURE_SAI_HAS_MCR */
+#endif
+    sai_bclk_source_t bclkSource;   /*!< Bit Clock source */
+    sai_master_slave_t masterSlave; /*!< Master or slave */
+} sai_config_t;
+
+#ifndef SAI_XFER_QUEUE_SIZE
+/*!@brief SAI transfer queue size, user can refine it according to use case. */
+#define SAI_XFER_QUEUE_SIZE (4U)
+#endif
+
+/*! @brief Audio sample rate */
+typedef enum _sai_sample_rate
+{
+    kSAI_SampleRate8KHz    = 8000U,   /*!< Sample rate 8000 Hz */
+    kSAI_SampleRate11025Hz = 11025U,  /*!< Sample rate 11025 Hz */
+    kSAI_SampleRate12KHz   = 12000U,  /*!< Sample rate 12000 Hz */
+    kSAI_SampleRate16KHz   = 16000U,  /*!< Sample rate 16000 Hz */
+    kSAI_SampleRate22050Hz = 22050U,  /*!< Sample rate 22050 Hz */
+    kSAI_SampleRate24KHz   = 24000U,  /*!< Sample rate 24000 Hz */
+    kSAI_SampleRate32KHz   = 32000U,  /*!< Sample rate 32000 Hz */
+    kSAI_SampleRate44100Hz = 44100U,  /*!< Sample rate 44100 Hz */
+    kSAI_SampleRate48KHz   = 48000U,  /*!< Sample rate 48000 Hz */
+    kSAI_SampleRate96KHz   = 96000U,  /*!< Sample rate 96000 Hz */
+    kSAI_SampleRate192KHz  = 192000U, /*!< Sample rate 192000 Hz */
+    kSAI_SampleRate384KHz  = 384000U, /*!< Sample rate 384000 Hz */
+} sai_sample_rate_t;
+
+/*! @brief Audio word width */
+typedef enum _sai_word_width
+{
+    kSAI_WordWidth8bits  = 8U,  /*!< Audio data width 8 bits */
+    kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
+    kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
+    kSAI_WordWidth32bits = 32U  /*!< Audio data width 32 bits */
+} sai_word_width_t;
+
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+/*! @brief sai data pin state definition */
+typedef enum _sai_data_pin_state
+{
+    kSAI_DataPinStateTriState =
+        0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */
+    kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots
+                                             are masked or channel disabled */
+} sai_data_pin_state_t;
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
+/*! @brief sai fifo combine mode definition */
+typedef enum _sai_fifo_combine
+{
+    kSAI_FifoCombineDisabled = 0U,          /*!< sai fifo combine mode disabled */
+    kSAI_FifoCombineModeEnabledOnRead,      /*!< sai fifo combine mode enabled on FIFO reads */
+    kSAI_FifoCombineModeEnabledOnWrite,     /*!< sai fifo combine mode enabled on FIFO write */
+    kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */
+} sai_fifo_combine_t;
+#endif
+
+/*! @brief sai transceiver type */
+typedef enum _sai_transceiver_type
+{
+    kSAI_Transmitter = 0U, /*!< sai transmitter */
+    kSAI_Receiver    = 1U, /*!< sai receiver */
+} sai_transceiver_type_t;
+
+/*! @brief sai frame sync len */
+typedef enum _sai_frame_sync_len
+{
+    kSAI_FrameSyncLenOneBitClk    = 0U, /*!< 1 bit clock frame sync len for DSP mode */
+    kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */
+} sai_frame_sync_len_t;
+
+/*! @brief sai transfer format */
+typedef struct _sai_transfer_format
+{
+    uint32_t sampleRate_Hz;   /*!< Sample rate of audio data */
+    uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32 bits */
+    sai_mono_stereo_t stereo; /*!< Mono or stereo */
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+    uint32_t masterClockHz; /*!< Master clock frequency in Hz */
+#endif                      /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    uint8_t watermark; /*!< Watermark value */
+#endif                 /* FSL_FEATURE_SAI_HAS_FIFO */
+
+    /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
+     * other parameter carefully, such as
+     * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
+     * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
+     * for the single channel usage, user can provide channel or channel mask only, such as,
+     * channel = 0 or channelMask = kSAI_Channel0Mask.
+     */
+    uint8_t channel;     /*!< Transfer start channel */
+    uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */
+    uint8_t endChannel;  /*!< end channel number */
+    uint8_t channelNums; /*!< Total enabled channel numbers */
+
+    sai_protocol_t protocol; /*!< Which audio protocol used */
+    bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame
+                                sync length is 64 times of bit clock. */
+} sai_transfer_format_t;
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*! @brief master clock configurations */
+typedef struct _sai_master_clock
+{
+#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+    bool mclkOutputEnable; /*!< master clock output enable */
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    sai_mclk_source_t mclkSource; /*!< Master Clock source */
+#endif
+#endif
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+    uint32_t mclkHz;          /*!< target mclk frequency */
+    uint32_t mclkSourceClkHz; /*!< mclk source frequency*/
+#endif
+} sai_master_clock_t;
+#endif
+
+/*! @brief sai fifo feature*/
+#if (defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) || \
+    (defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) ||                 \
+    (defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING) ||                           \
+    (defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO))
+#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 1
+#else
+#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 0
+#endif
+
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+/*! @brief sai fifo configurations */
+typedef struct _sai_fifo
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    bool fifoContinueOneError; /*!< fifo continues when error occur */
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
+    sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */
+#endif
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    uint8_t fifoWatermark; /*!< fifo watermark */
+#endif
+} sai_fifo_t;
+#endif
+
+/*! @brief sai bit clock configurations */
+typedef struct _sai_bit_clock
+{
+    bool bclkSrcSwap;    /*!< bit clock source swap */
+    bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay,
+                           this has effect of decreasing the data input setup time, but increasing the data output valid
+                           time .*/
+    sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */
+    sai_bclk_source_t bclkSource;      /*!< bit Clock source */
+} sai_bit_clock_t;
+
+/*! @brief sai frame sync configurations */
+typedef struct _sai_frame_sync
+{
+    uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */
+    bool frameSyncEarly;    /*!< TRUE is frame sync assert one bit before the first bit of frame
+                                FALSE is frame sync assert with the first bit of the frame */
+
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
+    bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */
+#endif
+
+    sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */
+
+} sai_frame_sync_t;
+
+/*! @brief sai serial data configurations */
+typedef struct _sai_serial_data
+{
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */
+#endif
+
+    sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */
+    uint8_t dataWord0Length;    /*!< configure the number of bits in the first word in each frame */
+    uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */
+    uint8_t dataWordLength;  /*!< used to record the data length for dma transfer */
+    uint8_t
+        dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */
+    uint8_t dataWordNum;     /*!< configure the number of words in each frame */
+    uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */
+} sai_serial_data_t;
+
+/*! @brief sai transceiver configurations */
+typedef struct _sai_transceiver
+{
+    sai_serial_data_t serialData; /*!< serial data configurations */
+    sai_frame_sync_t frameSync;   /*!< ws configurations */
+    sai_bit_clock_t bitClock;     /*!< bit clock configurations */
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+    sai_fifo_t fifo; /*!< fifo configurations */
+#endif
+    sai_master_slave_t masterSlave; /*!< transceiver is master or slave */
+
+    sai_sync_mode_t syncMode; /*!< transceiver sync mode */
+
+    uint8_t startChannel; /*!< Transfer start channel */
+    uint8_t channelMask;  /*!< enabled channel mask value, reference _sai_channel_mask */
+    uint8_t endChannel;   /*!< end channel number */
+    uint8_t channelNums;  /*!< Total enabled channel numbers */
+
+} sai_transceiver_t;
+
+/*! @brief SAI transfer structure */
+typedef struct _sai_transfer
+{
+    uint8_t *data;   /*!< Data start address to transfer. */
+    size_t dataSize; /*!< Transfer size. */
+} sai_transfer_t;
+
+typedef struct _sai_handle sai_handle_t;
+
+/*! @brief SAI transfer callback prototype */
+typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SAI handle structure */
+struct _sai_handle
+{
+    I2S_Type *base; /*!< base address */
+
+    uint32_t state;                   /*!< Transfer status */
+    sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/
+    void *userData;                   /*!< Callback parameter passed to callback function*/
+    uint8_t bitWidth;                 /*!< Bit width for transfer, 8/16/24/32 bits */
+
+    /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
+     * other parameter carefully, such as
+     * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
+     * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
+     * for the single channel usage, user can provide channel or channel mask only, such as,
+     * channel = 0 or channelMask = kSAI_Channel0Mask.
+     */
+    uint8_t channel;     /*!< Transfer start channel */
+    uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */
+    uint8_t endChannel;  /*!< end channel number */
+    uint8_t channelNums; /*!< Total enabled channel numbers */
+
+    sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
+    size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                   /*!< Index for user to queue transfer */
+    volatile uint8_t queueDriver;                 /*!< Index for driver to get the transfer data and size */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    uint8_t watermark; /*!< Watermark value */
+#endif
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.
+ *
+ * @param base SAI base pointer.
+ */
+void SAI_Init(I2S_Type *base);
+
+/*!
+ * @brief De-initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit
+ * or SAI_RxInit is called to enable the clock.
+ *
+ * @param base SAI base pointer.
+ */
+void SAI_Deinit(I2S_Type *base);
+
+/*!
+ * @brief Resets the SAI Tx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.
+ *
+ * @param base SAI base pointer
+ */
+void SAI_TxReset(I2S_Type *base);
+
+/*!
+ * @brief Resets the SAI Rx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.
+ *
+ * @param base SAI base pointer
+ */
+void SAI_RxReset(I2S_Type *base);
+
+/*!
+ * @brief Enables/disables the SAI Tx.
+ *
+ * @param base SAI base pointer.
+ * @param enable True means enable SAI Tx, false means disable.
+ */
+void SAI_TxEnable(I2S_Type *base, bool enable);
+
+/*!
+ * @brief Enables/disables the SAI Rx.
+ *
+ * @param base SAI base pointer.
+ * @param enable True means enable SAI Rx, false means disable.
+ */
+void SAI_RxEnable(I2S_Type *base, bool enable);
+
+/*!
+ * @brief Set Rx bit clock direction.
+ *
+ * Select bit clock direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->TCR2 |= I2S_TCR2_BCD_MASK;
+    }
+    else
+    {
+        base->TCR2 &= ~I2S_TCR2_BCD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Rx bit clock direction.
+ *
+ * Select bit clock direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->RCR2 |= I2S_RCR2_BCD_MASK;
+    }
+    else
+    {
+        base->RCR2 &= ~I2S_RCR2_BCD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Rx frame sync direction.
+ *
+ * Select frame sync direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->RCR4 |= I2S_RCR4_FSD_MASK;
+    }
+    else
+    {
+        base->RCR4 &= ~I2S_RCR4_FSD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Tx frame sync direction.
+ *
+ * Select frame sync direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->TCR4 |= I2S_TCR4_FSD_MASK;
+    }
+    else
+    {
+        base->TCR4 &= ~I2S_TCR4_FSD_MASK;
+    }
+}
+
+/*!
+ * @brief Transmitter bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz Bit clock source frequency.
+ * @param sampleRate Audio data sample rate.
+ * @param bitWidth Audio data bitWidth.
+ * @param channelNumbers Audio channel numbers.
+ */
+void SAI_TxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
+/*!
+ * @brief Receiver bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz Bit clock source frequency.
+ * @param sampleRate Audio data sample rate.
+ * @param bitWidth Audio data bitWidth.
+ * @param channelNumbers Audio channel numbers.
+ */
+void SAI_RxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
+/*!
+ * @brief Transmitter Bit clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
+
+/*!
+ * @brief Receiver Bit clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*!
+ * @brief Master clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config master clock configurations.
+ */
+void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config);
+#endif
+
+#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
+/*!
+ * @brief SAI transmitter fifo configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config fifo configurations.
+ */
+void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
+
+/*!
+ * @brief SAI receiver fifo configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config fifo configurations.
+ */
+void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
+#endif
+
+/*!
+ * @brief SAI transmitter Frame sync configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
+
+/*!
+ * @brief SAI receiver Frame sync configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
+
+/*!
+ * @brief SAI transmitter Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
+
+/*!
+ * @brief SAI receiver Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
+
+/*!
+ * @brief SAI transmitter configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config transmitter configurations.
+ */
+void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config);
+
+/*!
+ * @brief SAI receiver configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config receiver configurations.
+ */
+void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config);
+
+/*!
+ * @brief Get classic I2S mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetClassicI2SConfig(sai_transceiver_t *config,
+                             sai_word_width_t bitWidth,
+                             sai_mono_stereo_t mode,
+                             uint32_t saiChannelMask);
+
+/*!
+ * @brief Get left justified mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask);
+
+/*!
+ * @brief Get right justified mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetRightJustifiedConfig(sai_transceiver_t *config,
+                                 sai_word_width_t bitWidth,
+                                 sai_mono_stereo_t mode,
+                                 uint32_t saiChannelMask);
+
+/*!
+ * @brief Get TDM mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param frameSyncWidth length of frame sync.
+ * @param bitWidth audio data word width.
+ * @param dataWordNum word number in one frame.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetTDMConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      uint32_t dataWordNum,
+                      uint32_t saiChannelMask);
+
+/*!
+ * @brief Get DSP mode configurations.
+ *
+ * @note DSP mode is also called PCM mode which support MODE A and MODE B,
+ * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
+ * @code
+ * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+ * config->frameSync.frameSyncEarly    = true;
+ * SAI_TxSetConfig(base, config)
+ * @endcode
+ *
+ * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
+ * @code
+ * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
+ * SAI_TxSetConfig(base, config)
+ * @endcode
+ *
+ * @param config transceiver configurations.
+ * @param frameSyncWidth length of frame sync.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to enable.
+ */
+void SAI_GetDSPConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      sai_mono_stereo_t mode,
+                      uint32_t saiChannelMask);
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the SAI Tx status flag state.
+ *
+ * @param base SAI base pointer
+ * @return SAI Tx status flag value. Use the Status Mask to get the status value needed.
+ */
+static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)
+{
+    return base->TCSR;
+}
+
+/*!
+ * @brief Clears the SAI Tx status flag state.
+ *
+ * @param base SAI base pointer
+ * @param mask State mask. It can be a combination of the following source if defined:
+ *        @arg kSAI_WordStartFlag
+ *        @arg kSAI_SyncErrorFlag
+ *        @arg kSAI_FIFOErrorFlag
+ */
+static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)
+{
+    base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
+}
+
+/*!
+ * @brief Gets the SAI Tx status flag state.
+ *
+ * @param base SAI base pointer
+ * @return SAI Rx status flag value. Use the Status Mask to get the status value needed.
+ */
+static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)
+{
+    return base->RCSR;
+}
+
+/*!
+ * @brief Clears the SAI Rx status flag state.
+ *
+ * @param base SAI base pointer
+ * @param mask State mask. It can be a combination of the following sources if defined.
+ *        @arg kSAI_WordStartFlag
+ *        @arg kSAI_SyncErrorFlag
+ *        @arg kSAI_FIFOErrorFlag
+ */
+static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
+{
+    base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
+}
+
+/*!
+ * @brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like TCR1~TCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * @param base SAI base pointer
+ * @param resetType Reset type, FIFO reset or software reset
+ */
+void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
+
+/*!
+ * @brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like RCR1~RCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * @param base SAI base pointer
+ * @param resetType Reset type, FIFO reset or software reset
+ */
+void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
+
+/*!
+ * @brief Set the Tx channel FIFO enable mask.
+ *
+ * @param base SAI base pointer
+ * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
+void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
+
+/*!
+ * @brief Set the Rx channel FIFO enable mask.
+ *
+ * @param base SAI base pointer
+ * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
+void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
+
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order);
+
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param polarity
+ */
+void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param polarity
+ */
+void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param polarity
+ */
+void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param polarity
+ */
+void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * @brief Set Tx FIFO packing feature.
+ *
+ * @param base SAI base pointer.
+ * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
+void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
+
+/*!
+ * @brief Set Rx FIFO packing feature.
+ *
+ * @param base SAI base pointer.
+ * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
+void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+/*!
+ * @brief Set Tx FIFO error continue.
+ *
+ * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
+ * not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
+ *
+ * @param base SAI base pointer.
+ * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+ */
+static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
+{
+    if (isEnabled)
+    {
+        base->TCR4 |= I2S_TCR4_FCONT_MASK;
+    }
+    else
+    {
+        base->TCR4 &= ~I2S_TCR4_FCONT_MASK;
+    }
+}
+
+/*!
+ * @brief Set Rx FIFO error continue.
+ *
+ * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
+ * not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
+ *
+ * @param base SAI base pointer.
+ * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+ */
+static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
+{
+    if (isEnabled)
+    {
+        base->RCR4 |= I2S_RCR4_FCONT_MASK;
+    }
+    else
+    {
+        base->RCR4 &= ~I2S_RCR4_FCONT_MASK;
+    }
+}
+#endif
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the SAI Tx interrupt requests.
+ *
+ * @param base SAI base pointer
+ * @param mask interrupt source
+ *     The parameter can be a combination of the following sources if defined.
+ *     @arg kSAI_WordStartInterruptEnable
+ *     @arg kSAI_SyncErrorInterruptEnable
+ *     @arg kSAI_FIFOWarningInterruptEnable
+ *     @arg kSAI_FIFORequestInterruptEnable
+ *     @arg kSAI_FIFOErrorInterruptEnable
+ */
+static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)
+{
+    base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
+}
+
+/*!
+ * @brief Enables the SAI Rx interrupt requests.
+ *
+ * @param base SAI base pointer
+ * @param mask interrupt source
+ *     The parameter can be a combination of the following sources if defined.
+ *     @arg kSAI_WordStartInterruptEnable
+ *     @arg kSAI_SyncErrorInterruptEnable
+ *     @arg kSAI_FIFOWarningInterruptEnable
+ *     @arg kSAI_FIFORequestInterruptEnable
+ *     @arg kSAI_FIFOErrorInterruptEnable
+ */
+static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)
+{
+    base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
+}
+
+/*!
+ * @brief Disables the SAI Tx interrupt requests.
+ *
+ * @param base SAI base pointer
+ * @param mask interrupt source
+ *     The parameter can be a combination of the following sources if defined.
+ *     @arg kSAI_WordStartInterruptEnable
+ *     @arg kSAI_SyncErrorInterruptEnable
+ *     @arg kSAI_FIFOWarningInterruptEnable
+ *     @arg kSAI_FIFORequestInterruptEnable
+ *     @arg kSAI_FIFOErrorInterruptEnable
+ */
+static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)
+{
+    base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask));
+}
+
+/*!
+ * @brief Disables the SAI Rx interrupt requests.
+ *
+ * @param base SAI base pointer
+ * @param mask interrupt source
+ *     The parameter can be a combination of the following sources if defined.
+ *     @arg kSAI_WordStartInterruptEnable
+ *     @arg kSAI_SyncErrorInterruptEnable
+ *     @arg kSAI_FIFOWarningInterruptEnable
+ *     @arg kSAI_FIFORequestInterruptEnable
+ *     @arg kSAI_FIFOErrorInterruptEnable
+ */
+static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)
+{
+    base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask));
+}
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the SAI Tx DMA requests.
+ * @param base SAI base pointer
+ * @param mask DMA source
+ *     The parameter can be combination of the following sources if defined.
+ *     @arg kSAI_FIFOWarningDMAEnable
+ *     @arg kSAI_FIFORequestDMAEnable
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
+    }
+    else
+    {
+        base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask));
+    }
+}
+
+/*!
+ * @brief Enables/disables the SAI Rx DMA requests.
+ * @param base SAI base pointer
+ * @param mask DMA source
+ *     The parameter can be a combination of the following sources if defined.
+ *     @arg kSAI_FIFOWarningDMAEnable
+ *     @arg kSAI_FIFORequestDMAEnable
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
+    }
+    else
+    {
+        base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask));
+    }
+}
+
+/*!
+ * @brief  Gets the SAI Tx data register address.
+ *
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
+ *
+ * @param base SAI base pointer.
+ * @param channel Which data channel used.
+ * @return data register address.
+ */
+static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
+{
+    return (uintptr_t)(&(base->TDR)[channel]);
+}
+
+/*!
+ * @brief  Gets the SAI Rx data register address.
+ *
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
+ *
+ * @param base SAI base pointer.
+ * @param channel Which data channel used.
+ * @return data register address.
+ */
+static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
+{
+    return (uintptr_t)(&(base->RDR)[channel]);
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sends data using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
+/*!
+ * @brief Sends data to multi channel using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param channelMask channel mask.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+void SAI_WriteMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
+/*!
+ * @brief Writes data into SAI FIFO.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param data Data needs to be written.
+ */
+static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)
+{
+    base->TDR[channel] = data;
+}
+
+/*!
+ * @brief Receives data using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
+/*!
+ * @brief Receives multi channel data using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param channelMask channel mask.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+void SAI_ReadMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
+/*!
+ * @brief Reads data from the SAI FIFO.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @return Data in SAI FIFO.
+ */
+static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)
+{
+    return base->RDR[channel];
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SAI Tx handle.
+ *
+ * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * @param base SAI base pointer
+ * @param handle SAI handle pointer.
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function
+ */
+void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Initializes the SAI Rx handle.
+ *
+ * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI handle pointer.
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function.
+ */
+void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief SAI transmitter transfer configurations.
+ *
+ * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo
+ * configurations.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI handle pointer.
+ * @param config tranmitter configurations.
+ */
+void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
+
+/*!
+ * @brief SAI receiver transfer configurations.
+ *
+ * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo
+ * configurations.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI handle pointer.
+ * @param config receiver configurations.
+ */
+void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
+
+
+/*!
+ * @brief Performs an interrupt non-blocking send transfer on SAI.
+ *
+ * @note This API returns immediately after the transfer initiates.
+ * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
+ * @retval kStatus_Success Successfully started the data receive.
+ * @retval kStatus_SAI_TxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer);
+
+/*!
+ * @brief Performs an interrupt non-blocking receive transfer on SAI.
+ *
+ * @note This API returns immediately after the transfer initiates.
+ * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * @param base SAI base pointer
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
+ * @retval kStatus_Success Successfully started the data receive.
+ * @retval kStatus_SAI_RxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer);
+
+/*!
+ * @brief Gets a set byte count.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param count Bytes count sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets a received byte count.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param count Bytes count received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts the current send.
+ *
+ * @note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
+void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle);
+
+/*!
+ * @brief Aborts the current IRQ receive.
+ *
+ * @note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base SAI base pointer
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
+void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle);
+
+/*!
+ * @brief Terminate all SAI send.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortSend.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ */
+void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle);
+
+/*!
+ * @brief Terminate all SAI receive.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortReceive.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ */
+void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle);
+
+/*!
+ * @brief Tx interrupt handler.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure.
+ */
+void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
+
+/*!
+ * @brief Tx interrupt handler.
+ *
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure.
+ */
+void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+
+/*! @} */
+
+#endif /* FSL_SAI_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.c
new file mode 100644
index 0000000000..1e78b5aa6f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_sai_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sai_dma"
+#endif
+
+/*<! Structure definition for sai_dma_private_handle_t. The structure is private. */
+typedef struct _sai_dma_private_handle
+{
+    I2S_Type *base;
+    sai_dma_handle_t *handle;
+} sai_dma_private_handle_t;
+
+/*!@brief _sai_dma_states */
+enum
+{
+    kSAI_Idle = 0x0U,
+    kSAI_Busy = 0x1U,
+};
+
+static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
+
+/*<! Private handle only used for internally. */
+static sai_dma_private_handle_t s_dmaPrivateHandle[ARRAY_SIZE(s_saiBases)][2];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the instance number for SAI.
+ *
+ * @param base SAI base pointer.
+ */
+static uint32_t SAI_GetInstance(I2S_Type *base);
+
+/*!
+ * @brief SAI EDMA callback for send.
+ *
+ * @param handle pointer to sai_dma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ */
+static void SAI_TxDMACallback(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief SAI EDMA callback for receive.
+ *
+ * @param handle pointer to sai_dma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ */
+static void SAI_RxDMACallback(dma_handle_t *handle, void *userData);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SAI_GetInstance(I2S_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
+    {
+        if (s_saiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_saiBases));
+
+    return instance;
+}
+
+static void SAI_TxDMACallback(dma_handle_t *handle, void *userData)
+{
+    sai_dma_private_handle_t *privHandle = (sai_dma_private_handle_t *)userData;
+    sai_dma_handle_t *saiHandle          = privHandle->handle;
+
+    /* Update queue counter */
+    (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t));
+    saiHandle->queueDriver = (saiHandle->queueDriver + 1U) % SAI_XFER_QUEUE_SIZE;
+
+    /* Call callback function */
+    if (saiHandle->callback != NULL)
+    {
+        (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL)
+    {
+        SAI_TransferAbortSendDMA(privHandle->base, saiHandle);
+    }
+}
+
+static void SAI_RxDMACallback(dma_handle_t *handle, void *userData)
+{
+    sai_dma_private_handle_t *privHandle = (sai_dma_private_handle_t *)userData;
+    sai_dma_handle_t *saiHandle          = privHandle->handle;
+
+    /* Update queue counter */
+    (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t));
+    saiHandle->queueDriver = (saiHandle->queueDriver + 1U) % SAI_XFER_QUEUE_SIZE;
+
+    /* Call callback function */
+    if (saiHandle->callback != NULL)
+    {
+        (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL)
+    {
+        SAI_TransferAbortReceiveDMA(privHandle->base, saiHandle);
+    }
+}
+
+/*!
+ * brief Initializes the SAI master DMA handle.
+ *
+ * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ * param base SAI peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaHandle DMA handle pointer, this handle shall be static allocated by users.
+ */
+void SAI_TransferTxCreateHandleDMA(
+    I2S_Type *base, sai_dma_handle_t *handle, sai_dma_callback_t callback, void *userData, dma_handle_t *dmaHandle)
+{
+    assert((handle != NULL) && (dmaHandle != NULL));
+
+    uint32_t instance = SAI_GetInstance(base);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set sai base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback  = callback;
+    handle->userData  = userData;
+
+    /* Set SAI state to idle */
+    handle->state = (uint32_t)kSAI_Idle;
+
+    s_dmaPrivateHandle[instance][0].base   = base;
+    s_dmaPrivateHandle[instance][0].handle = handle;
+
+/* Use FIFO error continue nstead of using interrupt to handle error */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && (FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR)
+    base->TCR4 |= I2S_TCR4_FCONT_MASK;
+#endif
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(dmaHandle, SAI_TxDMACallback, &s_dmaPrivateHandle[instance][0]);
+}
+
+/*!
+ * brief Initializes the SAI slave DMA handle.
+ *
+ * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ * param base SAI peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaHandle DMA handle pointer, this handle shall be static allocated by users.
+ */
+void SAI_TransferRxCreateHandleDMA(
+    I2S_Type *base, sai_dma_handle_t *handle, sai_dma_callback_t callback, void *userData, dma_handle_t *dmaHandle)
+{
+    assert((handle != NULL) && (dmaHandle != NULL));
+
+    uint32_t instance = SAI_GetInstance(base);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set sai base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback  = callback;
+    handle->userData  = userData;
+
+    /* Set SAI state to idle */
+    handle->state = (uint32_t)kSAI_Idle;
+
+    s_dmaPrivateHandle[instance][1].base   = base;
+    s_dmaPrivateHandle[instance][1].handle = handle;
+
+/* Use FIFO error continue nstead of using interrupt to handle error */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && (FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR)
+    base->RCR4 |= I2S_RCR4_FCONT_MASK;
+#endif
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(dmaHandle, SAI_RxDMACallback, &s_dmaPrivateHandle[instance][1]);
+}
+
+/*!
+ * @brief Configures the SAI Rx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferRxSetConfigDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transceiver_t *saiConfig)
+{
+    assert((handle != NULL) && (saiConfig != NULL));
+
+    dma_transfer_config_t config = {0};
+
+    /* Configure the audio format to SAI registers */
+    SAI_RxSetConfig(base, saiConfig);
+
+    handle->channel = saiConfig->startChannel;
+
+    /* Configure the data format into DMA register */
+    config.srcAddr             = SAI_RxGetDataRegisterAddress(base, handle->channel);
+    config.enableDestIncrement = true;
+    config.enableSrcIncrement  = false;
+    switch (saiConfig->frameSync.frameSyncWidth)
+    {
+        case 8:
+            config.srcSize        = kDMA_Transfersize8bits;
+            config.destSize       = kDMA_Transfersize8bits;
+            handle->bytesPerFrame = 1U;
+            break;
+        case 16:
+            config.srcSize        = kDMA_Transfersize16bits;
+            config.destSize       = kDMA_Transfersize16bits;
+            handle->bytesPerFrame = 2U;
+            break;
+        default:
+            config.srcSize        = kDMA_Transfersize32bits;
+            config.destSize       = kDMA_Transfersize32bits;
+            handle->bytesPerFrame = 4U;
+            break;
+    }
+
+    /* Configure DMA channel */
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &config, 1UL);
+}
+
+/*!
+ * @brief Configures the SAI Tx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferTxSetConfigDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transceiver_t *saiConfig)
+{
+    assert((handle != NULL) && (saiConfig != NULL));
+
+    dma_transfer_config_t config = {0};
+
+    /* Configure the audio format to SAI registers */
+    SAI_TxSetConfig(base, saiConfig);
+
+    handle->channel = saiConfig->startChannel;
+
+    /* Configure the data format into DMA register */
+    config.destAddr            = SAI_TxGetDataRegisterAddress(base, handle->channel);
+    config.enableDestIncrement = false;
+    config.enableSrcIncrement  = true;
+    switch (saiConfig->frameSync.frameSyncWidth)
+    {
+        case 8:
+            config.srcSize        = kDMA_Transfersize8bits;
+            config.destSize       = kDMA_Transfersize8bits;
+            handle->bytesPerFrame = 1U;
+            break;
+        case 16:
+            config.srcSize        = kDMA_Transfersize16bits;
+            config.destSize       = kDMA_Transfersize16bits;
+            handle->bytesPerFrame = 2U;
+            break;
+        default:
+            config.srcSize        = kDMA_Transfersize32bits;
+            config.destSize       = kDMA_Transfersize32bits;
+            handle->bytesPerFrame = 4U;
+            break;
+    }
+
+    /* Configure DMA channel */
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &config, 1UL);
+}
+
+/*!
+ * brief Performs a non-blocking SAI transfer using DMA.
+ *
+ * note This interface returns immediately after the transfer initiates. Call
+ * the SAI_GetTransferStatus to poll the transfer status to check whether the SAI transfer finished.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_SAI_TxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferSendDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->saiQueue[handle->queueUser].data != NULL)
+    {
+        return kStatus_SAI_QueueFull;
+    }
+
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
+    handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->queueUser                            = (handle->queueUser + 1U) % SAI_XFER_QUEUE_SIZE;
+
+    /* Set the source address */
+    DMA_SetSourceAddress(handle->dmaHandle->base, handle->dmaHandle->channel, (uint32_t)(xfer->data));
+
+    /* Set the transfer size */
+    DMA_SetTransferSize(handle->dmaHandle->base, handle->dmaHandle->channel, xfer->dataSize);
+
+    /* Change the state of handle */
+    handle->state = (uint32_t)kSAI_Busy;
+
+    /* Start DMA transfer */
+    DMA_StartTransfer(handle->dmaHandle);
+
+/* Enable DMA request and start SAI */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
+#else
+    SAI_TxEnableDMA(base, kSAI_FIFOWarningDMAEnable, true);
+#endif
+    SAI_TxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a non-blocking SAI transfer using DMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * SAI_GetTransferStatus to poll the transfer status to check whether the SAI transfer is finished.
+ *
+ * param base SAI base pointer
+ * param handle SAI DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_SAI_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferReceiveDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->saiQueue[handle->queueUser].data != NULL)
+    {
+        return kStatus_SAI_QueueFull;
+    }
+
+    /* Add into queue */
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
+    handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->queueUser                            = (handle->queueUser + 1U) % SAI_XFER_QUEUE_SIZE;
+
+    /* Set the source address */
+    DMA_SetDestinationAddress(handle->dmaHandle->base, handle->dmaHandle->channel, (uint32_t)(xfer->data));
+
+    /* Set the transfer size */
+    DMA_SetTransferSize(handle->dmaHandle->base, handle->dmaHandle->channel, xfer->dataSize);
+
+    /* Change the state of handle */
+    handle->state = (uint32_t)kSAI_Busy;
+
+    /* Start DMA transfer */
+    DMA_StartTransfer(handle->dmaHandle);
+
+/* Enable DMA request and start SAI */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
+#else
+    SAI_RxEnableDMA(base, kSAI_FIFOWarningDMAEnable, true);
+#endif
+    SAI_RxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a SAI transfer using DMA.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ */
+void SAI_TransferAbortSendDMA(I2S_Type *base, sai_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+/* Disable DMA enable bit */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
+#else
+    SAI_TxEnableDMA(base, kSAI_FIFOWarningDMAEnable, false);
+#endif
+
+    /* Disable Tx */
+    SAI_TxEnable(base, false);
+
+    /* Set the handle state */
+    handle->state = (uint32_t)kSAI_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Aborts a SAI transfer using DMA.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ */
+void SAI_TransferAbortReceiveDMA(I2S_Type *base, sai_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+/* Disable DMA enable bit */
+#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
+    SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
+#else
+    SAI_RxEnableDMA(base, kSAI_FIFOWarningDMAEnable, false);
+#endif
+
+    /* Disable Rx */
+    SAI_RxEnable(base, false);
+
+    /* Set the handle state */
+    handle->state = (uint32_t)kSAI_Idle;
+
+    /* Clear the queue */
+    (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser   = 0;
+}
+
+/*!
+ * brief Gets byte count sent by SAI.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ * param count Bytes count sent by SAI.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetSendCountDMA(I2S_Type *base, sai_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kSAI_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Gets byte count received by SAI.
+ *
+ * param base SAI base pointer.
+ * param handle SAI DMA handle pointer.
+ * param count Bytes count received by SAI.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetReceiveCountDMA(I2S_Type *base, sai_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kSAI_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.h
new file mode 100644
index 0000000000..9c3f6f199a
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sai_dma.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_SAI_DMA_H_
+#define FSL_SAI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_sai.h"
+
+/*!
+ * @addtogroup sai_dma SAI DMA Driver
+ * @ingroup sai
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_SAI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*!< Version 2.4.0 */
+/*! @} */
+
+typedef struct _sai_dma_handle sai_dma_handle_t;
+
+/*! @brief Define SAI DMA callback */
+typedef void (*sai_dma_callback_t)(I2S_Type *base, sai_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/
+struct _sai_dma_handle
+{
+    dma_handle_t *dmaHandle;                      /*!< DMA handler for SAI send */
+    uint8_t bytesPerFrame;                        /*!< Bytes in a frame */
+    uint8_t channel;                              /*!< Which Data channel SAI use */
+    uint32_t state;                               /*!< SAI DMA transfer internal state */
+    sai_dma_callback_t callback;                  /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                               /*!< User callback parameter */
+    sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
+    size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                   /*!< Index for user to queue transfer. */
+    volatile uint8_t queueDriver;                 /*!< Index for driver to get the transfer data and size */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SAI master DMA handle.
+ *
+ * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param base SAI peripheral base address.
+ * @param callback Pointer to user callback function.
+ * @param userData User parameter passed to the callback function.
+ * @param dmaHandle DMA handle pointer, this handle shall be static allocated by users.
+ */
+void SAI_TransferTxCreateHandleDMA(
+    I2S_Type *base, sai_dma_handle_t *handle, sai_dma_callback_t callback, void *userData, dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the SAI slave DMA handle.
+ *
+ * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param base SAI peripheral base address.
+ * @param callback Pointer to user callback function.
+ * @param userData User parameter passed to the callback function.
+ * @param dmaHandle DMA handle pointer, this handle shall be static allocated by users.
+ */
+void SAI_TransferRxCreateHandleDMA(
+    I2S_Type *base, sai_dma_handle_t *handle, sai_dma_callback_t callback, void *userData, dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a non-blocking SAI transfer using DMA.
+ *
+ * @note This interface returns immediately after the transfer initiates. Call
+ * the SAI_GetTransferStatus to poll the transfer status to check whether the SAI transfer finished.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_SAI_TxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferSendDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SAI transfer using DMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * SAI_GetTransferStatus to poll the transfer status to check whether the SAI transfer is finished.
+ *
+ * @param base SAI base pointer
+ * @param handle SAI DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_SAI_RxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SAI_TransferReceiveDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a SAI transfer using DMA.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ */
+void SAI_TransferAbortSendDMA(I2S_Type *base, sai_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts a SAI transfer using DMA.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ */
+void SAI_TransferAbortReceiveDMA(I2S_Type *base, sai_dma_handle_t *handle);
+
+/*!
+ * @brief Gets byte count sent by SAI.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param count Bytes count sent by SAI.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetSendCountDMA(I2S_Type *base, sai_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets byte count received by SAI.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param count Bytes count received by SAI.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SAI_TransferGetReceiveCountDMA(I2S_Type *base, sai_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Configures the SAI Tx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferTxSetConfigDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transceiver_t *saiConfig);
+
+/*!
+ * @brief Configures the SAI Rx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI DMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferRxSetConfigDMA(I2S_Type *base, sai_dma_handle_t *handle, sai_transceiver_t *saiConfig);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.c
new file mode 100644
index 0000000000..a444c23d36
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_sim.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sim"
+#endif
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+/*!
+ * brief Sets the USB voltage regulator setting.
+ *
+ * This function configures whether the USB voltage regulator is enabled in
+ * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations
+ * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable
+ * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode,
+ * use:
+ *
+ * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower);
+ *
+ * param mask  USB voltage regulator enable setting.
+ */
+void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask)
+{
+    SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK);
+
+    SIM->SOPT1 = (SIM->SOPT1 & ~(uint32_t)kSIM_UsbVoltRegEnableInAllModes) | mask;
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
+
+/*!
+ * brief Gets the unique identification register value.
+ *
+ * param uid Pointer to the structure to save the UID value.
+ */
+void SIM_GetUniqueId(sim_uid_t *uid)
+{
+#if (defined(FSL_FEATURE_SIM_HAS_UIDH) && FSL_FEATURE_SIM_HAS_UIDH)
+    uid->H = SIM->UIDH;
+#elif defined(SIM_UID0_UID_MASK)
+    uid->H  = SIM->UID0;
+#endif /* FSL_FEATURE_SIM_HAS_UIDH */
+
+#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM)
+    uid->M = SIM->UIDM;
+#else
+
+#if defined(SIM_UID1_UID_MASK)
+    uid->MH = SIM->UID1;
+#else
+    uid->MH = SIM->UIDMH;
+#endif /* SIM_UID1_UID_MASK */
+
+#if defined(SIM_UID2_UID_MASK)
+    uid->ML = SIM->UID2;
+#else
+    uid->ML = SIM->UIDML;
+#endif /* SIM_UID2_UID_MASK */
+
+#endif /* FSL_FEATURE_SIM_HAS_UIDM */
+
+#if defined(SIM_UID3_UID_MASK)
+    uid->L = SIM->UID3;
+#else
+    uid->L  = SIM->UIDL;
+#endif /* SIM_UID3_UID_MASK */
+}
+
+#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR)
+/*!
+ * brief Gets the RF address register value.
+ *
+ * param info Pointer to the structure to save the RF address value.
+ */
+void SIM_GetRfAddr(sim_rf_addr_t *info)
+{
+    info->rfAddrL = SIM->RFADDRL;
+    info->rfAddrH = SIM->RFADDRH;
+}
+#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.h
new file mode 100644
index 0000000000..e24202417b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_sim.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SIM_H_
+#define FSL_SIM_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup sim */
+/*! @{*/
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Driver version. */
+/*! @} */
+
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+/*!@brief USB voltage regulator enable setting. */
+enum _sim_usb_volt_reg_enable_mode
+{
+    kSIM_UsbVoltRegEnable           = (int)SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */
+    kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK,      /*!< Enable voltage regulator in VLPR/VLPW modes. */
+    kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */
+    kSIM_UsbVoltRegEnableInAllModes =
+        (int)(SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK |
+              SIM_SOPT1_USBVSTBY_MASK) /*!< Enable voltage regulator in all power modes. */
+};
+#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */
+
+/*!@brief Unique ID. */
+typedef struct _sim_uid
+{
+#if (defined(FSL_FEATURE_SIM_HAS_UIDH) && FSL_FEATURE_SIM_HAS_UIDH)
+    uint32_t H; /*!< UIDH.  */
+#endif
+
+#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM)
+    uint32_t M; /*!< SIM_UIDM. */
+#else
+    uint32_t MH; /*!< UIDMH. */
+    uint32_t ML; /*!< UIDML. */
+#endif          /* FSL_FEATURE_SIM_HAS_UIDM */
+    uint32_t L; /*!< UIDL.  */
+} sim_uid_t;
+
+#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR)
+/*! @brief RF Mac Address.*/
+typedef struct _sim_rf_addr
+{
+    uint32_t rfAddrL; /*!< RFADDRL. */
+    uint32_t rfAddrH; /*!< RFADDRH. */
+} sim_rf_addr_t;
+#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */
+
+/*!@brief Flash enable mode. */
+enum _sim_flash_mode
+{
+    kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode.   */
+    kSIM_FlashDisable       = SIM_FCFG1_FLASHDIS_MASK   /*!< Disable flash in normal mode. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+/*!
+ * @brief Sets the USB voltage regulator setting.
+ *
+ * This function configures whether the USB voltage regulator is enabled in
+ * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations
+ * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable
+ * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode,
+ * use:
+ *
+ * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower);
+ *
+ * @param mask  USB voltage regulator enable setting.
+ */
+void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask);
+#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
+
+/*!
+ * @brief Gets the unique identification register value.
+ *
+ * @param uid Pointer to the structure to save the UID value.
+ */
+void SIM_GetUniqueId(sim_uid_t *uid);
+
+/*!
+ * @brief Sets the flash enable mode.
+ *
+ * @param mode The mode to set; see \ref _sim_flash_mode for mode details.
+ */
+static inline void SIM_SetFlashMode(uint8_t mode)
+{
+    SIM->FCFG1 = mode;
+}
+
+#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR)
+/*!
+ * @brief Gets the RF address register value.
+ *
+ * @param info Pointer to the structure to save the RF address value.
+ */
+void SIM_GetRfAddr(sim_rf_addr_t *info);
+#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */
+
+#if (defined(FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN) && FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN)
+
+/*!
+ * @brief Enable the Systick clock or not.
+ *
+ * The Systick clock is enabled by default.
+ *
+ * @param enable The switcher for Systick clock.
+ */
+static inline void SIM_EnableSystickClock(bool enable)
+{
+    if (enable)
+    {
+        SIM->MISC2 &= ~SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Clear to enable. */
+    }
+    else
+    {
+        SIM->MISC2 |= SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Set to disable. */
+    }
+}
+
+#endif /* FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* FSL_SIM_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.c
new file mode 100644
index 0000000000..5d66f5b330
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.c
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2021, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_slcd.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.slcd"
+#endif
+
+#define SLCD_WAVEFORM_CONFIG_NUM 16U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the SLCD instance from peripheral base address.
+ *
+ * @param base SLCD peripheral base address.
+ * @return SLCD instance.
+ */
+static uint32_t SLCD_GetInstance(LCD_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to slcd clocks for each instance. */
+static const clock_ip_name_t s_slcdClock[FSL_FEATURE_SOC_SLCD_COUNT] = SLCD_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to slcd bases for each instance. */
+static LCD_Type *const s_slcdBases[] = LCD_BASE_PTRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t SLCD_GetInstance(LCD_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_slcdBases); instance++)
+    {
+        if (s_slcdBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_slcdBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the SLCD, ungates the module clock, initializes the power
+ * setting, enables all used plane pins, and sets with interrupt and work mode
+ * with the configuration.
+ *
+ * param base  SLCD peripheral base address.
+ * param configure SLCD configuration pointer.
+ *   For the configuration structure, many parameters have the default setting
+ *   and the SLCD_Getdefaultconfig() is provided to get them. Use it
+ *   verified for their applications.
+ *   The others have no default settings, such as "clkConfig", and must be provided
+ *   by the application before calling the SLCD_Init() API.
+ */
+void SLCD_Init(LCD_Type *base, slcd_config_t *configure)
+{
+    assert(configure);
+    assert(configure->clkConfig);
+
+    uint32_t gcrReg   = 0;
+    bool intEnabled   = false;
+    uint32_t regNum   = 0;
+    uint32_t instance = SLCD_GetInstance(base);
+
+    /* Bit mask of the LCD_GCR to modify in this function. */
+    uint32_t gcrMsk = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Un-gate the SLCD clock. */
+    CLOCK_EnableClock(s_slcdClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Configure general setting: power supply. */
+    gcrReg = LCD_GCR_RVEN((uint32_t)configure->powerSupply & 0x1U) |
+             LCD_GCR_CPSEL(((uint32_t)configure->powerSupply >> 1U) & 0x1U) |
+             LCD_GCR_VSUPPLY(((uint32_t)configure->powerSupply >> 2U) & 0x1U) |
+             LCD_GCR_LADJ((uint32_t)configure->loadAdjust);
+    /* Configure general setting: clock source. */
+    gcrReg |= LCD_GCR_SOURCE(((uint32_t)configure->clkConfig->clkSource) & 0x1U) |
+              LCD_GCR_LCLK(configure->clkConfig->clkPrescaler) | LCD_GCR_ALTDIV(configure->clkConfig->altClkDivider);
+    /* Configure the duty and set the work for low power wait and stop mode. */
+    gcrReg |= LCD_GCR_DUTY(configure->dutyCycle) | LCD_GCR_LCDSTP((uint32_t)configure->lowPowerBehavior & 0x1U);
+
+    gcrMsk = LCD_GCR_RVEN_MASK | LCD_GCR_CPSEL_MASK | LCD_GCR_VSUPPLY_MASK | LCD_GCR_LADJ_MASK | LCD_GCR_SOURCE_MASK |
+             LCD_GCR_LCLK_MASK | LCD_GCR_ALTDIV_MASK | LCD_GCR_DUTY_MASK | LCD_GCR_LCDSTP_MASK;
+
+#if FSL_FEATURE_SLCD_HAS_LCD_WAIT
+    gcrReg |= LCD_GCR_LCDWAIT(((uint32_t)configure->lowPowerBehavior >> 1U) & 0x1U);
+    gcrMsk |= LCD_GCR_LCDWAIT_MASK;
+#endif
+#if FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE
+    gcrReg |= LCD_GCR_LCDDOZE(((uint32_t)configure->lowPowerBehavior >> 1U) & 0x1U);
+    gcrMsk |= LCD_GCR_LCDDOZE_MASK;
+#endif
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    /* Configure for frame frequency interrupt. */
+    gcrReg |= LCD_GCR_LCDIEN(configure->frameFreqIntEnable);
+    gcrMsk |= LCD_GCR_LCDIEN_MASK;
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+#if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
+    /* Select the alternate clock for alternate clock source. */
+    gcrReg |= LCD_GCR_ALTSOURCE((((uint32_t)configure->clkConfig->clkSource) >> 1U) & 0x1U);
+    gcrMsk |= LCD_GCR_ALTSOURCE_MASK;
+#endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
+#if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
+    /* Configure the for fast frame rate. */
+    gcrReg |= LCD_GCR_FFR(configure->clkConfig->fastFrameRateEnable ? 1U : 0U);
+    gcrMsk |= LCD_GCR_FFR_MASK;
+#endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
+
+    gcrReg |= LCD_GCR_RVTRIM(configure->voltageTrim);
+    gcrMsk |= LCD_GCR_RVTRIM_MASK;
+
+    base->GCR = (base->GCR & ~gcrMsk) | gcrReg;
+
+    /* Set display mode. */
+    base->AR = LCD_AR_ALT((uint32_t)configure->displayMode & 0x1U) |
+               LCD_AR_BLANK(((uint32_t)configure->displayMode >> 1U) & 0x1U);
+
+    /* Configure the front plane and back plane pin setting. */
+    base->BPEN[0] = configure->backPlaneLowPin;
+    base->BPEN[1] = configure->backPlaneHighPin;
+    base->PEN[0]  = configure->slcdLowPinEnabled;
+    base->PEN[1]  = configure->slcdHighPinEnabled;
+
+    /* Set the fault frame detection. */
+    base->FDCR = 0;
+    if (NULL != configure->faultConfig)
+    {
+        /* If fault configure structure is not NULL, the fault detection is enabled. */
+        base->FDCR = LCD_FDCR_FDPRS(configure->faultConfig->faultPrescaler) |
+                     LCD_FDCR_FDSWW(configure->faultConfig->width) |
+                     LCD_FDCR_FDBPEN(configure->faultConfig->faultDetectBackPlaneEnable ? 1U : 0U) |
+                     LCD_FDCR_FDPINID(configure->faultConfig->faultDetectPinIndex) | LCD_FDCR_FDEN_MASK;
+        if (configure->faultConfig->faultDetectIntEnable)
+        {
+            base->GCR |= LCD_GCR_FDCIEN_MASK;
+            intEnabled = true;
+        }
+    }
+
+    /* Initialize the Waveform. */
+    for (regNum = 0; regNum < SLCD_WAVEFORM_CONFIG_NUM; regNum++)
+    {
+        base->WF[regNum] = 0;
+    }
+
+/* Enable the NVIC. */
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    if (configure->frameFreqIntEnable)
+    {
+        intEnabled = true;
+    }
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+    if (intEnabled)
+    {
+        (void)EnableIRQ(LCD_IRQn);
+    }
+}
+
+/*!
+ * brief Deinitializes the SLCD module, gates the module clock, disables an interrupt,
+ * and displays the SLCD.
+ *
+ * param base  SLCD peripheral base address.
+ */
+void SLCD_Deinit(LCD_Type *base)
+{
+    uint32_t instance = SLCD_GetInstance(base);
+
+    /* Stop SLCD display. */
+    SLCD_StopDisplay(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the SLCD clock. */
+    CLOCK_DisableClock(s_slcdClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable NVIC. */
+    (void)DisableIRQ(LCD_IRQn);
+}
+
+/*!
+ * brief Gets the SLCD default configuration structure. The
+ * purpose of this API is to get default parameters of the configuration structure
+ * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init()
+ * or modify fields of the structure before the calling SLCD_Init().
+ * All default parameters of the configure structuration are listed.
+ * code
+   config.displayMode        = kSLCD_NormalMode;
+   config.powerSupply        = kSLCD_InternalVll3UseChargePump;
+   config.voltageTrim        = kSLCD_RegulatedVolatgeTrim00;
+   config.lowPowerBehavior   = kSLCD_EnabledInWaitStop;
+   config.interruptSrc       = 0;
+   config.faultConfig        = NULL;
+   config.frameFreqIntEnable =  false;
+   endcode
+ * param configure The SLCD configuration structure pointer.
+ */
+void SLCD_GetDefaultConfig(slcd_config_t *configure)
+{
+    assert(configure);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(configure, 0, sizeof(*configure));
+
+    /* Get Default parameters for the configuration structure. */
+    /* SLCD in normal mode. */
+    configure->displayMode = kSLCD_NormalMode;
+    /* Power supply default: use charge pump to generate VLL1 and VLL2, VLL3 connected to VDD internally. */
+    configure->powerSupply = kSLCD_InternalVll3UseChargePump;
+    configure->voltageTrim = kSLCD_RegulatedVolatgeTrim08;
+    /* Work in low power mode. */
+    configure->lowPowerBehavior = kSLCD_EnabledInWaitStop;
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    /* No interrupt source is enabled. */
+    configure->frameFreqIntEnable = false;
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+    /* Fault detection is disabled. */
+    configure->faultConfig = NULL;
+}
+
+/*!
+ * brief Starts the SLCD blink mode.
+ *
+ * param base  SLCD peripheral base address.
+ * param mode  SLCD blink mode.
+ * param rate  SLCD blink rate.
+ */
+void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate)
+{
+    uint32_t mask  = LCD_AR_BMODE_MASK | LCD_AR_BRATE_MASK;
+    uint32_t arReg = base->AR;
+
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    mask |= LCD_AR_LCDIF_MASK;
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+
+    arReg &= ~mask;
+    /* Set blink mode and blink rate. */
+    arReg |= LCD_AR_BMODE(mode) | LCD_AR_BRATE(rate);
+    base->AR = arReg;
+
+    /* Enable Blink after setting the blink rate to meet some hardware requirement. */
+    arReg |= LCD_AR_BLINK_MASK;
+    base->AR = arReg;
+}
+
+/*!
+ * brief Enables the SLCD interrupt.
+ * For example, to enable fault detect complete interrupt and frame frequency interrupt,
+ * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
+ * code
+ *     SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
+ * endcode
+ *
+ * param base  SLCD peripheral base address.
+ * param mask  SLCD interrupts to enable. This is a logical OR of the
+ *             enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t gcReg = base->GCR;
+
+    gcReg |= LCD_GCR_FDCIEN(mask & 0x1U);
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    gcReg |= LCD_GCR_LCDIEN((mask >> 1U) & 0x1U);
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+
+    base->GCR = gcReg;
+}
+
+/*!
+ * brief Disables the SLCD interrupt.
+ * For example, to disable fault detect complete interrupt and frame frequency interrupt,
+ * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
+ * code
+ *     SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
+ * endcode
+ *
+ * param base  SLCD peripheral base address.
+ * param mask  SLCD interrupts to disable. This is a logical OR of the
+ *             enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t gcrReg = base->GCR;
+
+    /*!< SLCD fault detection complete interrupt source. */
+    if (0U != (mask & (uint32_t)kSLCD_FaultDetectCompleteInterrupt))
+    {
+        gcrReg &= ~LCD_GCR_FDCIEN_MASK;
+    }
+/*!< SLCD frame frequency interrupt source. */
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    if (0U != (mask & (uint32_t)kSLCD_FrameFreqInterrupt))
+    {
+        gcrReg &= ~LCD_GCR_LCDIEN_MASK;
+    }
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+
+    base->GCR = gcrReg;
+}
+
+/*!
+ * brief Clears the SLCD interrupt events status flag.
+ *
+ * param base  SLCD peripheral base address.
+ * param mask  SLCD interrupt source to be cleared.
+ * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask)
+{
+    /*!< SLCD fault detection complete interrupt source. */
+    if (0U != (mask & (uint32_t)kSLCD_FaultDetectCompleteInterrupt))
+    {
+        base->FDSR |= LCD_FDSR_FDCF_MASK;
+    }
+/*!< SLCD frame frequency interrupt source. */
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    if (0U != (mask & (uint32_t)kSLCD_FrameFreqInterrupt))
+    {
+        base->AR |= LCD_AR_LCDIF_MASK;
+    }
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+}
+
+/*!
+ * brief Gets the SLCD interrupt status flag.
+ *
+ * param base  SLCD peripheral base address.
+ * return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: slcd_interrupt_enable_t.
+ */
+uint32_t SLCD_GetInterruptStatus(LCD_Type *base)
+{
+    uint32_t status = 0;
+
+    /* Get the frame detect complete interrupt status. */
+    status = ((base->FDSR & LCD_FDSR_FDCF_MASK) >> LCD_FDSR_FDCF_SHIFT);
+
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    /* Get the frame frequency interrupt status. */
+    status |= ((base->AR & LCD_AR_LCDIF_MASK) >> (LCD_AR_LCDIF_SHIFT - 1U));
+#endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+
+    return status;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.h
new file mode 100644
index 0000000000..5f9797d845
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_slcd.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019, 2021, 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SLCD_H_
+#define FSL_SLCD_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup slcd
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SLCD driver version. */
+#define FSL_SLCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*! @} */
+
+/*! @brief SLCD power supply option. */
+typedef enum _slcd_power_supply_option
+{
+    kSLCD_InternalVll3UseChargePump =
+        2U, /*!< VLL3 connected to VDD internally, charge pump is used to generate VLL1 and VLL2. */
+    kSLCD_ExternalVll3UseResistorBiasNetwork =
+        4U, /*!< VLL3 is driven externally and resistor bias network is used to generate VLL1 and VLL2. */
+    kSLCD_ExteranlVll3UseChargePump =
+        6U, /*!< VLL3 is driven externally and charge pump is used to generate VLL1 and VLL2. */
+    kSLCD_InternalVll1UseChargePump =
+        7U /*!< VIREG is connected to VLL1 internally and charge pump is used to generate VLL2 and VLL3. */
+} slcd_power_supply_option_t;
+
+/*! @brief SLCD regulated voltage trim parameter, be used to meet the desired contrast. */
+typedef enum _slcd_regulated_voltage_trim
+{
+    kSLCD_RegulatedVolatgeTrim00 = 0U, /*!< Increase the voltage to 0.91 V. */
+    kSLCD_RegulatedVolatgeTrim01,      /*!< Increase the voltage to 1.01 V. */
+    kSLCD_RegulatedVolatgeTrim02,      /*!< Increase the voltage to 0.96 V. */
+    kSLCD_RegulatedVolatgeTrim03,      /*!< Increase the voltage to 1.06 V. */
+    kSLCD_RegulatedVolatgeTrim04,      /*!< Increase the voltage to 0.93 V. */
+    kSLCD_RegulatedVolatgeTrim05,      /*!< Increase the voltage to 1.02 V. */
+    kSLCD_RegulatedVolatgeTrim06,      /*!< Increase the voltage to 0.98 V. */
+    kSLCD_RegulatedVolatgeTrim07,      /*!< Increase the voltage to 1.08 V. */
+    kSLCD_RegulatedVolatgeTrim08,      /*!< Increase the voltage to 0.92 V. */
+    kSLCD_RegulatedVolatgeTrim09,      /*!< Increase the voltage to 1.02 V. */
+    kSLCD_RegulatedVolatgeTrim10,      /*!< Increase the voltage to 0.97 V. */
+    kSLCD_RegulatedVolatgeTrim11,      /*!< Increase the voltage to 1.07 V. */
+    kSLCD_RegulatedVolatgeTrim12,      /*!< Increase the voltage to 0.94 V. */
+    kSLCD_RegulatedVolatgeTrim13,      /*!< Increase the voltage to 1.05 V. */
+    kSLCD_RegulatedVolatgeTrim14,      /*!< Increase the voltage to 0.99 V. */
+    kSLCD_RegulatedVolatgeTrim15       /*!< Increase the voltage to 1.09 V. */
+} slcd_regulated_voltage_trim_t;
+
+/*! @brief SLCD load adjust to handle different LCD glass capacitance or
+ *  configure the LCD charge pump clock source.
+ *  Adjust the LCD glass capacitance if resistor bias network is enabled:
+ *  kSLCD_LowLoadOrFastestClkSrc - Low load (LCD glass capacitance 2000pF or lower.
+ *                 LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
+ *  kSLCD_LowLoadOrIntermediateClkSrc - low load (LCD glass capacitance 2000pF or lower.
+ *                 LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
+ *  kSLCD_HighLoadOrIntermediateClkSrc - high load (LCD glass capacitance 8000pF or lower.
+ *                 LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
+ *  kSLCD_HighLoadOrSlowestClkSrc - high load (LCD glass capacitance 8000pF or lower
+ *                 LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
+ *  Adjust clock for charge pump if charge pump is enabled:
+ *  kSLCD_LowLoadOrFastestClkSrc - Fasten clock source (LCD glass capacitance
+ *                 8000pF or 4000pF or lower if Fast Frame Rate is set)
+ *  kSLCD_LowLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
+ *                 capacitance 4000pF or 2000pF or lower if Fast Frame Rate is set)
+ *  kSLCD_HighLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
+ *                 capacitance 2000pF or 1000pF or lower if Fast Frame Rate is set)
+ *  kSLCD_HighLoadOrSlowestClkSrc - slowest clock source (LCD glass capacitance
+ *                 1000pF or 500pF or lower if Fast Frame Rate is set)
+ */
+typedef enum _slcd_load_adjust
+{
+    kSLCD_LowLoadOrFastestClkSrc = 0U,  /*!< Adjust in low load or selects fastest clock. */
+    kSLCD_LowLoadOrIntermediateClkSrc,  /*!< Adjust in low load or selects intermediate clock. */
+    kSLCD_HighLoadOrIntermediateClkSrc, /*!< Adjust in high load or selects intermediate clock. */
+    kSLCD_HighLoadOrSlowestClkSrc       /*!< Adjust in high load or selects slowest clock. */
+} slcd_load_adjust_t;
+
+/*! @brief SLCD clock source. */
+typedef enum _slcd_clock_src
+{
+    kSLCD_DefaultClk    = 0U, /*!< Select default clock ERCLK32K. */
+    kSLCD_AlternateClk1 = 1U, /*!< Select alternate clock source 1 : MCGIRCLK. */
+#if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
+    kSLCD_AlternateClk2 = 3U /*!< Select alternate clock source 2 : OSCERCLK. */
+#endif                       /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
+} slcd_clock_src_t;
+
+/*! @brief SLCD alternate clock divider. */
+typedef enum _slcd_alt_clock_div
+{
+    kSLCD_AltClkDivFactor1 = 0U, /*!< No divide for alternate clock. */
+    kSLCD_AltClkDivFactor64,     /*!< Divide alternate clock with factor 64. */
+    kSLCD_AltClkDivFactor256,    /*!< Divide alternate clock with factor 256. */
+    kSLCD_AltClkDivFactor512     /*!< Divide alternate clock with factor 512. */
+} slcd_alt_clock_div_t;
+
+/*! @brief SLCD clock prescaler to generate frame frequency. */
+typedef enum _slcd_clock_prescaler
+{
+    kSLCD_ClkPrescaler00 = 0U, /*!< Prescaler 0. */
+    kSLCD_ClkPrescaler01,      /*!< Prescaler 1. */
+    kSLCD_ClkPrescaler02,      /*!< Prescaler 2. */
+    kSLCD_ClkPrescaler03,      /*!< Prescaler 3. */
+    kSLCD_ClkPrescaler04,      /*!< Prescaler 4. */
+    kSLCD_ClkPrescaler05,      /*!< Prescaler 5. */
+    kSLCD_ClkPrescaler06,      /*!< Prescaler 6. */
+    kSLCD_ClkPrescaler07       /*!< Prescaler 7. */
+} slcd_clock_prescaler_t;
+
+/*! @brief SLCD duty cycle. */
+typedef enum _slcd_duty_cycle
+{
+    kSLCD_1Div1DutyCycle = 0U, /*!< LCD use 1 BP 1/1 duty cycle. */
+    kSLCD_1Div2DutyCycle,      /*!< LCD use 2 BP 1/2 duty cycle. */
+    kSLCD_1Div3DutyCycle,      /*!< LCD use 3 BP 1/3 duty cycle. */
+    kSLCD_1Div4DutyCycle,      /*!< LCD use 4 BP 1/4 duty cycle. */
+    kSLCD_1Div5DutyCycle,      /*!< LCD use 5 BP 1/5 duty cycle. */
+    kSLCD_1Div6DutyCycle,      /*!< LCD use 6 BP 1/6 duty cycle. */
+    kSLCD_1Div7DutyCycle,      /*!< LCD use 7 BP 1/7 duty cycle. */
+    kSLCD_1Div8DutyCycle       /*!< LCD use 8 BP 1/8 duty cycle. */
+} slcd_duty_cycle_t;
+
+/*! @brief SLCD segment phase type. */
+typedef enum _slcd_phase_type
+{
+    kSLCD_NoPhaseActivate = 0x00U, /*!< LCD wareform no phase activates. */
+    kSLCD_PhaseAActivate  = 0x01U, /*!< LCD waveform phase A activates. */
+    kSLCD_PhaseBActivate  = 0x02U, /*!< LCD waveform phase B activates. */
+    kSLCD_PhaseCActivate  = 0x04U, /*!< LCD waveform phase C activates. */
+    kSLCD_PhaseDActivate  = 0x08U, /*!< LCD waveform phase D activates. */
+    kSLCD_PhaseEActivate  = 0x10U, /*!< LCD waveform phase E activates. */
+    kSLCD_PhaseFActivate  = 0x20U, /*!< LCD waveform phase F activates. */
+    kSLCD_PhaseGActivate  = 0x40U, /*!< LCD waveform phase G activates. */
+    kSLCD_PhaseHActivate  = 0x80U  /*!< LCD waveform phase H activates. */
+} slcd_phase_type_t;
+
+/*! @brief SLCD segment phase bit index. */
+typedef enum _slcd_phase_index
+{
+    kSLCD_PhaseAIndex = 0x0U, /*!< LCD phase A bit index. */
+    kSLCD_PhaseBIndex = 0x1U, /*!< LCD phase B bit index. */
+    kSLCD_PhaseCIndex = 0x2U, /*!< LCD phase C bit index. */
+    kSLCD_PhaseDIndex = 0x3U, /*!< LCD phase D bit index. */
+    kSLCD_PhaseEIndex = 0x4U, /*!< LCD phase E bit index. */
+    kSLCD_PhaseFIndex = 0x5U, /*!< LCD phase F bit index. */
+    kSLCD_PhaseGIndex = 0x6U, /*!< LCD phase G bit index. */
+    kSLCD_PhaseHIndex = 0x7U  /*!< LCD phase H bit index. */
+} slcd_phase_index_t;
+
+/*! @brief SLCD display mode. */
+typedef enum _slcd_display_mode
+{
+    kSLCD_NormalMode = 0U, /*!< LCD Normal display mode. */
+    kSLCD_AlternateMode,   /*!< LCD Alternate display mode. For four back planes or less. */
+    kSLCD_BlankMode        /*!< LCD Blank display mode. */
+} slcd_display_mode_t;
+
+/*! @brief SLCD blink mode. */
+typedef enum _slcd_blink_mode
+{
+    kSLCD_BlankDisplayBlink = 0U, /*!< Display blank during the blink period. */
+    kSLCD_AltDisplayBlink /*!< Display alternate display during the blink period if duty cycle is lower than 5. */
+} slcd_blink_mode_t;
+
+/*! @brief SLCD blink rate. */
+typedef enum _slcd_blink_rate
+{
+    kSLCD_BlinkRate00 = 0U, /*!< SLCD blink rate is LCD clock/((2^12)). */
+    kSLCD_BlinkRate01,      /*!< SLCD blink rate is LCD clock/((2^13)). */
+    kSLCD_BlinkRate02,      /*!< SLCD blink rate is LCD clock/((2^14)). */
+    kSLCD_BlinkRate03,      /*!< SLCD blink rate is LCD clock/((2^15)). */
+    kSLCD_BlinkRate04,      /*!< SLCD blink rate is LCD clock/((2^16)). */
+    kSLCD_BlinkRate05,      /*!< SLCD blink rate is LCD clock/((2^17)). */
+    kSLCD_BlinkRate06,      /*!< SLCD blink rate is LCD clock/((2^18)). */
+    kSLCD_BlinkRate07       /*!< SLCD blink rate is LCD clock/((2^19)). */
+} slcd_blink_rate_t;
+
+/*! @brief SLCD fault detect clock prescaler. */
+typedef enum _slcd_fault_detect_clock_prescaler
+{
+    kSLCD_FaultSampleFreqDivider1 = 0U, /*!< Fault detect sample clock frequency is 1/1 bus clock. */
+    kSLCD_FaultSampleFreqDivider2,      /*!< Fault detect sample clock frequency is 1/2 bus clock. */
+    kSLCD_FaultSampleFreqDivider4,      /*!< Fault detect sample clock frequency is 1/4 bus clock. */
+    kSLCD_FaultSampleFreqDivider8,      /*!< Fault detect sample clock frequency is 1/8 bus clock. */
+    kSLCD_FaultSampleFreqDivider16,     /*!< Fault detect sample clock frequency is 1/16 bus clock. */
+    kSLCD_FaultSampleFreqDivider32,     /*!< Fault detect sample clock frequency is 1/32 bus clock. */
+    kSLCD_FaultSampleFreqDivider64,     /*!< Fault detect sample clock frequency is 1/64 bus clock. */
+    kSLCD_FaultSampleFreqDivider128     /*!< Fault detect sample clock frequency is 1/128 bus clock. */
+} slcd_fault_detect_clock_prescaler_t;
+
+/*! @brief SLCD fault detect sample window width. */
+typedef enum _slcd_fault_detect_sample_window_width
+{
+    kSLCD_FaultDetectWindowWidth4SampleClk = 0U, /*!< Sample window width is 4 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth8SampleClk,      /*!< Sample window width is 8 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth16SampleClk,     /*!< Sample window width is 16 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth32SampleClk,     /*!< Sample window width is 32 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth64SampleClk,     /*!< Sample window width is 64 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth128SampleClk,    /*!< Sample window width is 128 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth256SampleClk,    /*!< Sample window width is 256 sample clock cycles. */
+    kSLCD_FaultDetectWindowWidth512SampleClk     /*!< Sample window width is 512 sample clock cycles. */
+} slcd_fault_detect_sample_window_width_t;
+
+/*! @brief SLCD interrupt source. */
+typedef enum _slcd_interrupt_enable
+{
+    kSLCD_FaultDetectCompleteInterrupt = 1U, /*!< SLCD fault detection complete interrupt source. */
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    kSLCD_FrameFreqInterrupt = 2U /*!< SLCD frame frequency interrupt source. Not available in all low-power modes. */
+#endif                            /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
+} slcd_interrupt_enable_t;
+
+/*! @brief SLCD behavior in low power mode. */
+typedef enum _slcd_lowpower_behavior
+{
+    kSLCD_EnabledInWaitStop = 0, /*!< SLCD works in wait and stop mode. */
+    kSLCD_EnabledInWaitOnly,     /*!< SLCD works in wait mode and is disabled in stop mode. */
+    kSLCD_EnabledInStopOnly,     /*!< SLCD works in stop mode and is disabled in wait mode. */
+    kSLCD_DisabledInWaitStop     /*!< SLCD is disabled in stop mode and wait mode. */
+} slcd_lowpower_behavior;
+
+/*! @brief SLCD fault frame detection configuration structure. */
+typedef struct _slcd_fault_detect_config
+{
+    bool faultDetectIntEnable;       /*!< Fault frame detection interrupt enable flag.*/
+    bool faultDetectBackPlaneEnable; /*!< True means the pin id fault detected is back plane otherwise front plane. */
+    uint8_t faultDetectPinIndex;     /*!< Fault detected pin id  from 0 to 63. */
+    slcd_fault_detect_clock_prescaler_t faultPrescaler; /*!< Fault detect clock prescaler. */
+    slcd_fault_detect_sample_window_width_t width;      /*!< Fault detect sample window width. */
+} slcd_fault_detect_config_t;
+
+/*! @brief SLCD clock configuration structure. */
+typedef struct _slcd_clock_config
+{
+    slcd_clock_src_t clkSource; /*!< Clock source. "slcd_clock_src_t" is recommended to be used.
+                                  The SLCD is optimized to operate using a 32.768kHz clock input. */
+    slcd_alt_clock_div_t
+        altClkDivider; /*!< The divider to divide the alternate clock used for alternate clock source. */
+    slcd_clock_prescaler_t clkPrescaler; /*!< Clock prescaler. */
+#if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
+    bool fastFrameRateEnable; /*!< Fast frame rate enable flag. */
+#endif                        /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
+} slcd_clock_config_t;
+
+/*! @brief SLCD configuration structure. */
+typedef struct _slcd_config
+{
+    slcd_power_supply_option_t powerSupply;    /*!< Power supply option. */
+    slcd_regulated_voltage_trim_t voltageTrim; /*!< Regulated voltage trim used for the internal regulator VIREG to
+                                                  adjust to facilitate contrast control. */
+    slcd_clock_config_t *clkConfig;            /*!< Clock configure. */
+    slcd_display_mode_t displayMode;           /*!< SLCD display mode. */
+    slcd_load_adjust_t loadAdjust;             /*!< Load adjust to handle glass capacitance. */
+    slcd_duty_cycle_t dutyCycle;               /*!< Duty cycle. */
+    slcd_lowpower_behavior lowPowerBehavior;   /*!< SLCD behavior in low power mode. */
+#if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
+    bool frameFreqIntEnable;    /*!< Frame frequency interrupt enable flag.*/
+#endif                          /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
+    uint32_t slcdLowPinEnabled; /*!< Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n. */
+    uint32_t
+        slcdHighPinEnabled; /*!< Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32). */
+    uint32_t backPlaneLowPin;  /*!< Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back
+                                  plane. It should never have the same bit setting as the frontPlane Pin. */
+    uint32_t backPlaneHighPin; /*!< Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as
+                                  back plane. It should never have the same bit setting as the frontPlane Pin. */
+    slcd_fault_detect_config_t *faultConfig; /*!< Fault frame detection configure. If not requirement, set to NULL. */
+} slcd_config_t;
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SLCD, ungates the module clock, initializes the power
+ * setting, enables all used plane pins, and sets with interrupt and work mode
+ * with the configuration.
+ *
+ * @param base  SLCD peripheral base address.
+ * @param configure SLCD configuration pointer.
+ *   For the configuration structure, many parameters have the default setting
+ *   and the SLCD_Getdefaultconfig() is provided to get them. Use it
+ *   verified for their applications.
+ *   The others have no default settings, such as "clkConfig", and must be provided
+ *   by the application before calling the SLCD_Init() API.
+ */
+void SLCD_Init(LCD_Type *base, slcd_config_t *configure);
+
+/*!
+ * @brief Deinitializes the SLCD module, gates the module clock, disables an interrupt,
+ * and displays the SLCD.
+ *
+ * @param base  SLCD peripheral base address.
+ */
+void SLCD_Deinit(LCD_Type *base);
+
+/*!
+ * @brief Gets the SLCD default configuration structure. The
+ * purpose of this API is to get default parameters of the configuration structure
+ * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init()
+ * or modify fields of the structure before the calling SLCD_Init().
+ * All default parameters of the configure structuration are listed.
+ * @code
+   config.displayMode        = kSLCD_NormalMode;
+   config.powerSupply        = kSLCD_InternalVll3UseChargePump;
+   config.voltageTrim        = kSLCD_RegulatedVolatgeTrim00;
+   config.lowPowerBehavior   = kSLCD_EnabledInWaitStop;
+   config.interruptSrc       = 0;
+   config.faultConfig        = NULL;
+   config.frameFreqIntEnable =  false;
+   @endcode
+ * @param configure The SLCD configuration structure pointer.
+ */
+void SLCD_GetDefaultConfig(slcd_config_t *configure);
+
+/*! @} */
+
+/*!
+ * @name Plane Setting and Display Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the SLCD controller, starts generation, and displays the front plane and back plane waveform.
+ *
+ * @param base  SLCD peripheral base address.
+ */
+static inline void SLCD_StartDisplay(LCD_Type *base)
+{
+    base->GCR |= LCD_GCR_LCDEN_MASK;
+}
+
+/*!
+ * @brief Stops the SLCD controller. There is no waveform generator and all enabled pins
+ * only output a low value.
+ *
+ * @param base  SLCD peripheral base address.
+ */
+static inline void SLCD_StopDisplay(LCD_Type *base)
+{
+    base->GCR &= ~LCD_GCR_LCDEN_MASK;
+}
+
+/*!
+ * @brief Starts the SLCD blink mode.
+ *
+ * @param base  SLCD peripheral base address.
+ * @param mode  SLCD blink mode.
+ * @param rate  SLCD blink rate.
+ */
+void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate);
+
+/*!
+ * @brief Stops the SLCD blink mode.
+ *
+ * @param base  SLCD peripheral base address.
+ */
+static inline void SLCD_StopBlinkMode(LCD_Type *base)
+{
+    base->AR &= ~LCD_AR_BLINK_MASK;
+}
+
+/*!
+ * @brief Sets the SLCD back plane pin phase.
+ *
+ * This function sets the SLCD back plane pin phase. "kSLCD_PhaseXActivate" setting
+ * means the phase X is active for the back plane pin. "kSLCD_NoPhaseActivate" setting
+ * means there is no phase active for the back plane pin.
+ * For example, set the back plane pin 20 for phase A.
+ * @code
+ * SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate);
+ * @endcode
+ *
+ * @param base    SLCD peripheral base address.
+ * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
+ * @param phase   The phase activates for the back plane pin.
+ */
+static inline void SLCD_SetBackPlanePhase(LCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase)
+{
+    base->WF8B[pinIndx] = (uint8_t)phase;
+}
+
+/*!
+ * @brief Sets the SLCD front plane segment operation for a front plane pin.
+ *
+ * This function sets the SLCD front plane segment on or off operation.
+ * Each bit turns on or off the segments associated with the front plane pin in
+ * the following pattern: HGFEDCBA (most significant bit controls segment H and
+ * least significant bit controls segment A).
+ * For example, turn on the front plane pin 20 for phase B and phase C.
+ * @code
+ * SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate));
+ * @endcode
+ *
+ * @param base      SLCD peripheral base address.
+ * @param pinIndx   SLCD back plane pin index. Range from 0 to 63.
+ * @param operation The operation for the segment on the front plane pin.
+ *                  This is a logical OR of the enumeration :: slcd_phase_type_t.
+ */
+static inline void SLCD_SetFrontPlaneSegments(LCD_Type *base, uint32_t pinIndx, uint8_t operation)
+{
+    base->WF8B[pinIndx] = operation;
+}
+
+/*!
+ * @brief Sets one SLCD front plane pin for one phase.
+ *
+ * This function can be used to set one phase on or off for the front plane pin.
+ * It can be call many times to set the plane pin for different phase indexes.
+ * For example, turn on the front plane pin 20 for phase B and phase C.
+ * @code
+ * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true);
+ * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true);
+ * @endcode
+ *
+ * @param base      SLCD peripheral base address.
+ * @param pinIndx   SLCD back plane pin index. Range from 0 to 63.
+ * @param phaseIndx The phase bit index @ref slcd_phase_index_t.
+ * @param enable    True to turn on the segment for phaseIndx phase
+ *                  false to turn off the segment for phaseIndx phase.
+ */
+static inline void SLCD_SetFrontPlaneOnePhase(LCD_Type *base,
+                                              uint32_t pinIndx,
+                                              slcd_phase_index_t phaseIndx,
+                                              bool enable)
+{
+    uint8_t reg = base->WF8B[pinIndx];
+
+    if (enable)
+    {
+        base->WF8B[pinIndx] = (reg | (1U << (uint32_t)phaseIndx));
+    }
+    else
+    {
+        base->WF8B[pinIndx] = (reg & ~(1U << (uint32_t)phaseIndx));
+    }
+}
+
+#if FSL_FEATURE_SLCD_HAS_PAD_SAFE
+/*!
+ * @brief Enables/disables the SLCD pad safe state.
+ *
+ * Forces the safe state on the LCD pad controls. All LCD front plane
+ * and backplane functions are disabled.
+ *
+ * @param base  SLCD peripheral base address.
+ * @param enable True enable, false disable.
+ */
+static inline void SLCD_EnablePadSafeState(LCD_Type *base, bool enable)
+{
+    if (enable)
+    { /* Enable. */
+        base->GCR |= LCD_GCR_PADSAFE_MASK;
+    }
+    else
+    { /* Disable. */
+        base->GCR &= ~LCD_GCR_PADSAFE_MASK;
+    }
+}
+#endif /* FSL_FEATURE_SLCD_HAS_PAD_SAFE */
+
+/*!
+ * @brief Gets the SLCD fault detect counter.
+ *
+ * This function gets the number of samples inside the
+ * fault detection sample window.
+ *
+ * @param base  SLCD peripheral base address.
+ * @return The fault detect counter. The maximum return value is 255.
+ * If the maximum 255 returns, the overflow may happen.
+ * Reconfigure the fault detect sample window and fault detect clock prescaler
+ * for proper sampling.
+ */
+static inline uint32_t SLCD_GetFaultDetectCounter(LCD_Type *base)
+{
+    return base->FDSR & LCD_FDSR_FDCNT_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enables the SLCD interrupt.
+ * For example, to enable fault detect complete interrupt and frame frequency interrupt,
+ * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
+ * @code
+ *     SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
+ * @endcode
+ *
+ * @param base  SLCD peripheral base address.
+ * @param mask  SLCD interrupts to enable. This is a logical OR of the
+ *             enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the SLCD interrupt.
+ * For example, to disable fault detect complete interrupt and frame frequency interrupt,
+ * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
+ * @code
+ *     SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
+ * @endcode
+ *
+ * @param base  SLCD peripheral base address.
+ * @param mask  SLCD interrupts to disable. This is a logical OR of the
+ *             enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the SLCD interrupt status flag.
+ *
+ * @param base  SLCD peripheral base address.
+ * @return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: slcd_interrupt_enable_t.
+ */
+uint32_t SLCD_GetInterruptStatus(LCD_Type *base);
+
+/*!
+ * @brief Clears the SLCD interrupt events status flag.
+ *
+ * @param base  SLCD peripheral base address.
+ * @param mask  SLCD interrupt source to be cleared.
+ * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.
+ */
+void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* FSL_SLCD_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.c
new file mode 100644
index 0000000000..9cda142f47
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_smc.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.smc"
+#endif
+
+#if (defined(FSL_FEATURE_SMC_REG_WIDTH) && (FSL_FEATURE_SMC_REG_WIDTH == 32U))
+typedef uint32_t smc_reg_t;
+#else
+typedef uint8_t smc_reg_t;
+#endif
+
+typedef void (*smc_stop_ram_func_t)(void);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void SMC_EnterStopRamFunc(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static uint32_t g_savedPrimask;
+
+/*
+ * The ram function code is:
+ *
+ *  uint32_t i;
+ *  for (i=0; i<0x8; i++)
+ *  {
+ *      __NOP();
+ *  }
+ *  __DSB();
+ *  __WFI();
+ *  __ISB();
+ *
+ * When entring the stop modes, the flash prefetch might be interrupted, thus
+ * the prefetched code or data might be broken. To make sure the flash is idle
+ * when entring the stop modes, the code is moved to ram. And delay for a while
+ * before WFI to make sure previous flash prefetch is finished.
+ *
+ * Only need to do like this when code is in flash, if code is in rom or ram,
+ * this is not necessary.
+ */
+static uint16_t s_stopRamFuncArray[] = {
+    0x2000,         /* MOVS R0, #0 */
+    0x2808,         /* CMP R0, #8 */
+    0xD202,         /* BCS.N */
+    0xBF00,         /* NOP */
+    0x1C40,         /* ADDS R0, R0, #1 */
+    0xE7FA,         /* B.N */
+    0xF3BF, 0x8F4F, /* DSB */
+    0xBF30,         /* WFI */
+    0xF3BF, 0x8F6F, /* ISB */
+    0x4770,         /* BX LR */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void SMC_EnterStopRamFunc(void)
+{
+    uint32_t ramFuncEntry           = ((uint32_t)(s_stopRamFuncArray)) + 1U;
+    smc_stop_ram_func_t stopRamFunc = (smc_stop_ram_func_t)ramFuncEntry;
+    stopRamFunc();
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * brief Gets the SMC parameter.
+ *
+ * This function gets the SMC parameter including the enabled power mdoes.
+ *
+ * param base SMC peripheral base address.
+ * param param         Pointer to the SMC param structure.
+ */
+void SMC_GetParam(SMC_Type *base, smc_param_t *param)
+{
+    uint32_t reg       = base->PARAM;
+    param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
+    param->llsEnable   = (bool)(reg & SMC_PARAM_ELLS_MASK);
+    param->lls2Enable  = (bool)(reg & SMC_PARAM_ELLS2_MASK);
+    param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
+}
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+/*!
+ * brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void)
+{
+    g_savedPrimask = DisableGlobalIRQ();
+    __ISB();
+}
+
+/*!
+ * brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void)
+{
+    EnableGlobalIRQ(g_savedPrimask);
+    __ISB();
+}
+
+/*!
+ * brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+void SMC_PreEnterWaitModes(void)
+{
+    g_savedPrimask = DisableGlobalIRQ();
+    __ISB();
+}
+
+/*!
+ * brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with ref SMC_PreEnterWaitModes.
+ */
+void SMC_PostExitWaitModes(void)
+{
+    EnableGlobalIRQ(g_savedPrimask);
+    __ISB();
+}
+
+/*!
+ * brief Configures the system to RUN power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base)
+{
+    smc_reg_t reg;
+
+    reg = base->PMCTRL;
+    /* configure Normal RUN mode */
+    reg &= ~(smc_reg_t)SMC_PMCTRL_RUNM_MASK;
+    reg |= ((smc_reg_t)kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+/*!
+ * brief Configures the system to HSRUN power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base)
+{
+    smc_reg_t reg;
+
+    reg = (base->PMCTRL);
+    /* configure High Speed RUN mode */
+    reg &= ~(smc_reg_t)SMC_PMCTRL_RUNM_MASK;
+    reg |= ((smc_reg_t)kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+/*!
+ * brief Configures the system to WAIT power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base)
+{
+    /* configure Normal Wait mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to Stop power mode.
+ *
+ * param base SMC peripheral base address.
+ * param  option Partial Stop mode option.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
+{
+    smc_reg_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
+    /* configure the Partial Stop mode in Normal Stop mode */
+    reg = base->STOPCTRL;
+    reg &= ~(smc_reg_t)SMC_STOPCTRL_PSTOPO_MASK;
+    reg |= ((smc_reg_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
+    base->STOPCTRL = reg;
+#endif
+
+    /* configure Normal Stop mode */
+    reg = base->PMCTRL;
+    reg &= ~(smc_reg_t)SMC_PMCTRL_STOPM_MASK;
+    reg |= ((smc_reg_t)kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    SMC_EnterStopRamFunc();
+
+    /* check whether the power mode enter Stop mode succeed */
+    if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK))
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+/*!
+ * brief Configures the system to VLPR power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+                              ,
+                              bool wakeupMode
+#endif
+)
+{
+    smc_reg_t reg;
+
+    reg = (smc_reg_t)(base->PMCTRL);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    /* configure whether the system remains in VLP mode on an interrupt */
+    if (wakeupMode)
+    {
+        /* exits to RUN mode on an interrupt */
+        reg |= SMC_PMCTRL_LPWUI_MASK;
+    }
+    else
+    {
+        /* remains in VLP mode on an interrupt */
+        reg &= ~(smc_reg_t)SMC_PMCTRL_LPWUI_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+    /* configure VLPR mode */
+    reg &= ~(smc_reg_t)SMC_PMCTRL_RUNM_MASK;
+    reg |= ((smc_reg_t)kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to VLPW power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base)
+{
+    /* configure VLPW mode */
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to VLPS power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base)
+{
+    smc_reg_t reg;
+
+    /* configure VLPS mode */
+    reg = base->PMCTRL;
+    reg &= ~(smc_reg_t)SMC_PMCTRL_STOPM_MASK;
+    reg |= ((smc_reg_t)kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    SMC_EnterStopRamFunc();
+
+    /* check whether the power mode enter VLPS mode succeed */
+    if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK))
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * brief Configures the system to LLS power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+                             ,
+                             const smc_power_mode_lls_config_t *config
+#endif
+)
+{
+    smc_reg_t reg;
+
+    /* configure to LLS mode */
+    reg = base->PMCTRL;
+    reg &= ~(smc_reg_t)SMC_PMCTRL_STOPM_MASK;
+    reg |= ((smc_reg_t)kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+/* configure LLS sub-mode*/
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    reg = base->STOPCTRL;
+    reg &= ~(smc_reg_t)SMC_STOPCTRL_LLSM_MASK;
+    reg |= ((smc_reg_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+    base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    if (config->enableLpoClock)
+    {
+        base->STOPCTRL &= ~(smc_reg_t)SMC_STOPCTRL_LPOPO_MASK;
+    }
+    else
+    {
+        base->STOPCTRL |= (smc_reg_t)SMC_STOPCTRL_LPOPO_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    SMC_EnterStopRamFunc();
+
+    /* check whether the power mode enter LLS mode succeed */
+    if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK))
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * brief Configures the system to VLLS power mode.
+ *
+ * param base SMC peripheral base address.
+ * param  config The VLLS power mode configuration structure.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
+{
+    smc_reg_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    if (config->subMode == kSMC_StopSub0)
+#endif
+    {
+        /* configure whether the Por Detect work in Vlls0 mode */
+        if (true == config->enablePorDetectInVlls0)
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL &= ~(smc_reg_t)SMC_VLLSCTRL_PORPO_MASK;
+#else
+            base->STOPCTRL &= ~(smc_reg_t)SMC_STOPCTRL_PORPO_MASK;
+#endif
+        }
+        else
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
+#else
+            base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
+#endif
+        }
+    }
+#endif /* FSL_FEATURE_SMC_HAS_PORPO */
+
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+    else if (config->subMode == kSMC_StopSub2)
+    {
+        /* configure whether the Por Detect work in Vlls0 mode */
+        if (true == config->enableRam2InVlls2)
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+            base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+        }
+        else
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+            base->STOPCTRL &= ~(smc_reg_t)SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+        }
+    }
+    else
+    {
+        /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */
+    }
+#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~(smc_reg_t)SMC_PMCTRL_STOPM_MASK;
+    reg |= ((smc_reg_t)kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+/* configure the VLLS sub-mode */
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+    reg = base->VLLSCTRL;
+    reg &= ~(smc_reg_t)SMC_VLLSCTRL_VLLSM_MASK;
+    reg |= ((smc_reg_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
+    base->VLLSCTRL = reg;
+#else
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    reg = base->STOPCTRL;
+    reg &= ~(smc_reg_t)SMC_STOPCTRL_LLSM_MASK;
+    reg |= ((smc_reg_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+    base->STOPCTRL = reg;
+#else
+    reg = base->STOPCTRL;
+    reg &= ~(smc_reg_t)SMC_STOPCTRL_VLLSM_MASK;
+    reg |= ((smc_reg_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
+    base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+#endif
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    if (config->enableLpoClock)
+    {
+        base->STOPCTRL &= ~(smc_reg_t)SMC_STOPCTRL_LPOPO_MASK;
+    }
+    else
+    {
+        base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    SMC_EnterStopRamFunc();
+
+    /* check whether the power mode enter LLS mode succeed */
+    if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK))
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.h
new file mode 100644
index 0000000000..f90b549dde
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_smc.h
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SMC_H_
+#define FSL_SMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup smc */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SMC driver version */
+#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
+/*! @} */
+
+/*!
+ * @brief Power Modes Protection
+ */
+typedef enum _smc_power_mode_protection
+{
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode.      */
+#endif                                             /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode.        */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode.        */
+#endif                                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+    kSMC_AllowPowerModeAll = (0U
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+                              | SMC_PMPROT_AVLLS_MASK
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+                              | SMC_PMPROT_ALLS_MASK
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+                              | SMC_PMPROT_AVLP_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+                              | kSMC_AllowPowerModeHsrun
+#endif                          /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+                              ) /*!< Allow all power mode.              */
+} smc_power_mode_protection_t;
+
+/*!
+ * @brief Power Modes in PMSTAT
+ */
+typedef enum _smc_power_state
+{
+    kSMC_PowerStateRun  = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN   */
+    kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP  */
+    kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR  */
+    kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW  */
+    kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS  */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS   */
+#endif                                /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS  */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
+#endif                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_power_state_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode
+{
+    kSMC_RunNormal = 0U, /*!< Normal RUN mode.             */
+    kSMC_RunVlpr   = 2U, /*!< Very-low-power RUN mode.     */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */
+#endif              /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode
+{
+    kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
+    kSMC_StopVlps   = 2U, /*!< Very-low-power STOP mode.   */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_StopLls = 3U, /*!< Low-leakage Stop mode.      */
+#endif                 /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */
+#endif
+} smc_stop_mode_t;
+
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+/*!
+ * @brief VLLS/LLS stop sub mode definition
+ */
+typedef enum _smc_stop_submode
+{
+    kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */
+    kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */
+    kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */
+    kSMC_StopSub3 = 3U  /*!< Stop submode 3, for VLLS3/LLS3. */
+} smc_stop_submode_t;
+#endif
+
+/*!
+ * @brief Partial STOP option
+ */
+typedef enum _smc_partial_stop_mode
+{
+    kSMC_PartialStop  = 0U, /*!< STOP - Normal Stop mode*/
+    kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
+    kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+} smc_partial_stop_option_t;
+
+/*!
+ * @brief _smc_status, SMC configuration status.
+ */
+enum
+{
+    kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/
+};
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _smc_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} smc_version_id_t;
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief IP parameter definition.
+ */
+typedef struct _smc_param
+{
+    bool hsrunEnable; /*!< HSRUN mode enable. */
+    bool llsEnable;   /*!< LLS mode enable.   */
+    bool lls2Enable;  /*!< LLS2 mode enable.  */
+    bool vlls0Enable; /*!< VLLS0 mode enable. */
+} smc_param_t;
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+    (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+/*!
+ * @brief SMC Low-Leakage Stop power mode configuration.
+ */
+typedef struct _smc_power_mode_lls_config
+{
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    bool enableLpoClock; /*!< Enable LPO clock in LLS mode */
+#endif
+} smc_power_mode_lls_config_t;
+#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief SMC Very Low-Leakage Stop power mode configuration.
+ */
+typedef struct _smc_power_mode_vlls_config
+{
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+    bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+    bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */
+#endif
+} smc_power_mode_vlls_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name System mode controller APIs*/
+/*! @{ */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief Gets the SMC version ID.
+ *
+ * This function gets the SMC version ID, including major version number,
+ * minor version number, and feature specification number.
+ *
+ * @param base SMC peripheral base address.
+ * @param versionId     Pointer to the version ID structure.
+ */
+static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
+{
+    *((uint32_t *)(uint32_t)versionId) = base->VERID;
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief Gets the SMC parameter.
+ *
+ * This function gets the SMC parameter including the enabled power mdoes.
+ *
+ * @param base SMC peripheral base address.
+ * @param param         Pointer to the SMC param structure.
+ */
+void SMC_GetParam(SMC_Type *base, smc_param_t *param);
+#endif
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function  configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map. For example, to allow LLS and VLLS,
+ * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps).
+ * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
+ *
+ * @param base SMC peripheral base address.
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
+{
+    base->PMPROT = allowedModes;
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function  returns the current power mode status. After the application
+ * switches the power mode, it should always check the status to check whether it
+ * runs into the specified mode or not. The application  should  check
+ * this mode before switching to a different mode. The system  requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the smc_power_state_t for information about
+ * the power status.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power mode status.
+ */
+static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
+{
+    return (smc_power_state_t)base->PMSTAT;
+}
+
+/*!
+ * @brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with @ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void);
+
+/*!
+ * @brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+void SMC_PreEnterWaitModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with @ref SMC_PreEnterWaitModes.
+ */
+void SMC_PostExitWaitModes(void);
+
+/*!
+ * @brief Configures the system to RUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+/*!
+ * @brief Configures the system to HSRUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+/*!
+ * @brief Configures the system to WAIT power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base);
+
+/*!
+ * @brief Configures the system to Stop power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  option Partial Stop mode option.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+/*!
+ * @brief Configures the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  wakeupMode Enter Normal Run mode if true, else stay in VLPR mode.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode);
+#else
+/*!
+ * @brief Configures the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+/*!
+ * @brief Configures the system to VLPW power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base);
+
+/*!
+ * @brief Configures the system to VLPS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+/*!
+ * @brief Configures the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  config The LLS power mode configuration structure
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config);
+#else
+/*!
+ * @brief Configures the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base);
+#endif
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief Configures the system to VLLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  config The VLLS power mode configuration structure.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config);
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* FSL_SMC_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.c
new file mode 100644
index 0000000000..2561315a2f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.c
@@ -0,0 +1,1520 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_spi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.spi"
+#endif
+
+/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _spi_transfer_states_t
+{
+    kSPI_Idle = 0x0, /*!< SPI is idle state */
+    kSPI_Busy        /*!< SPI is busy tranferring data. */
+};
+
+/*! @brief Typedef for spi master interrupt handler. spi master and slave handle is the same. */
+typedef void (*spi_isr_t)(SPI_Type *base, spi_master_handle_t *spiHandle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Sends a buffer of data bytes in non-blocking way.
+ *
+ * @param base SPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ */
+static void SPI_WriteNonBlocking(SPI_Type *base, const uint8_t *buffer, size_t size);
+
+/*!
+ * @brief Receive a buffer of data bytes in non-blocking way.
+ *
+ * @param base SPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ */
+static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
+
+/*!
+ * @brief Get the waterrmark value for this SPI instance.
+ *
+ * @param base SPI base pointer
+ * @return Watermark value for the SPI instance.
+ */
+static uint8_t SPI_GetWatermark(SPI_Type *base);
+
+/*!
+ * @brief Send a piece of data for SPI.
+ *
+ * This function computes the number of data to be written into D register or Tx FIFO,
+ * and write the data into it. At the same time, this function updates the values in
+ * master handle structure.
+ *
+ * @param base SPI base pointer
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Receive a piece of data for SPI master.
+ *
+ * This function computes the number of data to receive from D register or Rx FIFO,
+ * and write the data to destination address. At the same time, this function updates
+ * the values in master handle structure.
+ *
+ * @param base SPI base pointer
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Common IRQ handler for SPI.
+ *
+ * @param base SPI base pointer.
+ * @param instance SPI instance number.
+ */
+static void SPI_CommonIRQHandler(SPI_Type *base, uint32_t instance);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief SPI internal handle pointer array */
+static spi_master_handle_t *s_spiHandle[FSL_FEATURE_SOC_SPI_COUNT];
+/*! @brief Base pointer array */
+static SPI_Type *const s_spiBases[] = SPI_BASE_PTRS;
+/*! @brief IRQ name array */
+static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Clock array name */
+static const clock_ip_name_t s_spiClock[] = SPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointer to master IRQ handler for each instance. */
+static spi_isr_t s_spiMasterIsr;
+static spi_isr_t s_spiSlaveIsr;
+
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t g_spiDummyData[ARRAY_SIZE(s_spiBases)] = {0};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Get the instance for SPI module.
+ *
+ * param base SPI base address
+ */
+uint32_t SPI_GetInstance(SPI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_spiBases); instance++)
+    {
+        if (s_spiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_spiBases));
+
+    return instance;
+}
+
+/*!
+ * brief Set up the dummy data.
+ *
+ * param base SPI peripheral address.
+ * param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+    uint32_t instance        = SPI_GetInstance(base);
+    g_spiDummyData[instance] = dummyData;
+}
+
+static void SPI_WriteNonBlocking(SPI_Type *base, const uint8_t *buffer, size_t size)
+{
+    uint32_t i            = 0;
+    uint8_t bytesPerFrame = 1U;
+    uint32_t instance     = SPI_GetInstance(base);
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Check if 16 bits or 8 bits */
+    bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#endif
+
+    while (i < size)
+    {
+        if (buffer != NULL)
+        {
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+            base->DL = *buffer++;
+            /*16 bit mode*/
+            if ((base->C2 & SPI_C2_SPIMODE_MASK) != 0U)
+            {
+                base->DH = *buffer++;
+            }
+#else
+            base->D   = *buffer++;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+        }
+        /* Send dummy data */
+        else
+        {
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
+            base->DL = g_spiDummyData[instance] & 0xFFU;
+            base->DH = g_spiDummyData[instance] & 0xFFU;
+#else
+            base->D   = g_spiDummyData[instance] & 0xFFU;
+#endif
+        }
+        i += bytesPerFrame;
+    }
+}
+
+static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size)
+{
+    uint32_t i            = 0U;
+    uint8_t bytesPerFrame = 1U;
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Check if 16 bits or 8 bits */
+    bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#endif
+
+    while (i < size)
+    {
+        if (buffer != NULL)
+        {
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+            *buffer++ = base->DL;
+            /*16 bit mode*/
+            if ((base->C2 & SPI_C2_SPIMODE_MASK) != 0U)
+            {
+                *buffer++ = base->DH;
+            }
+#else
+            *buffer++ = base->D;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+        }
+        else
+        {
+            (void)SPI_ReadData(base);
+        }
+        i += bytesPerFrame;
+    }
+}
+
+/* Get the watermark value of transfer. Please note that the entery width of FIFO is 16 bits. */
+static uint8_t SPI_GetWatermark(SPI_Type *base)
+{
+    uint8_t ret = 0U;
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    uint8_t rxSize = 0U;
+    /* Get the number to be sent if there is FIFO */
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        rxSize = (base->C3 & SPI_C3_RNFULLF_MARK_MASK) >> SPI_C3_RNFULLF_MARK_SHIFT;
+        if (rxSize == 0U)
+        {
+            ret = (uint8_t)FSL_FEATURE_SPI_FIFO_SIZEn(base) * 3U / 4U;
+        }
+        else
+        {
+            ret = (uint8_t)FSL_FEATURE_SPI_FIFO_SIZEn(base) / 2U;
+        }
+    }
+    /* If no FIFO, just set the watermark to 1 */
+    else
+    {
+        ret = 1U;
+    }
+#else
+    ret = 1U;
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+    return ret;
+}
+
+static void SPI_SendInitialTransfer(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint8_t bytestoTransfer = handle->bytePerFrame;
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
+    if (handle->watermark > 1U)
+    {
+        /* In the first time to send data to FIFO, if transfer size is not larger than
+         * the FIFO size, send all data to FIFO, or send data to make the FIFO full.
+         * Besides, The FIFO's entry width is 16 bits, need to translate it to bytes.
+         */
+        int32_t fifosize = FSL_FEATURE_SPI_FIFO_SIZEn(base);
+        assert(fifosize > 0);
+        bytestoTransfer = (uint8_t)MIN(handle->txRemainingBytes, ((uint32_t)fifosize * 2U));
+    }
+#endif
+
+    SPI_WriteNonBlocking(base, handle->txData, bytestoTransfer);
+
+    /* Update handle information */
+    if (handle->txData != NULL)
+    {
+        handle->txData += bytestoTransfer;
+    }
+    handle->txRemainingBytes -= bytestoTransfer;
+}
+
+static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint8_t bytes = handle->bytePerFrame;
+
+    /* Read S register and ensure SPTEF is 1, otherwise the write would be ignored. */
+    if (handle->watermark == 1U)
+    {
+        /* Send data */
+        if ((base->C1 & SPI_C1_MSTR_MASK) != 0U)
+        {
+            /* As a master, only write once */
+            if ((base->S & SPI_S_SPTEF_MASK) != 0U)
+            {
+                SPI_WriteNonBlocking(base, handle->txData, bytes);
+                /* Update handle information */
+                if (handle->txData != NULL)
+                {
+                    handle->txData += bytes;
+                }
+                handle->txRemainingBytes -= bytes;
+            }
+        }
+        else
+        {
+            /* As a slave, send data until SPTEF cleared */
+            while (((base->S & SPI_S_SPTEF_MASK) != 0U) && (handle->txRemainingBytes >= bytes))
+            {
+                SPI_WriteNonBlocking(base, handle->txData, bytes);
+
+                /* Update handle information */
+                if (handle->txData != NULL)
+                {
+                    handle->txData += bytes;
+                }
+                handle->txRemainingBytes -= bytes;
+            }
+        }
+    }
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
+    /* If use FIFO */
+    else
+    {
+        /* The FIFO's entry width is 16 bits, need to translate it to bytes. */
+        uint8_t bytestoTransfer = (uint8_t)handle->watermark * 2U;
+
+        if (handle->txRemainingBytes < 8U)
+        {
+            bytestoTransfer = (uint8_t)handle->txRemainingBytes;
+        }
+
+        SPI_WriteNonBlocking(base, handle->txData, bytestoTransfer);
+
+        /* Update handle information */
+        if (handle->txData != NULL)
+        {
+            handle->txData += bytestoTransfer;
+        }
+        handle->txRemainingBytes -= bytestoTransfer;
+    }
+#endif
+}
+
+static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint8_t bytes = handle->bytePerFrame;
+
+    /* Read S register and ensure SPRF is 1, otherwise the write would be ignored. */
+    if (handle->watermark == 1U)
+    {
+        if ((base->S & SPI_S_SPRF_MASK) != 0U)
+        {
+            SPI_ReadNonBlocking(base, handle->rxData, bytes);
+
+            /* Update information in handle */
+            if (handle->rxData != NULL)
+            {
+                handle->rxData += bytes;
+            }
+            handle->rxRemainingBytes -= bytes;
+        }
+    }
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
+    /* If use FIFO */
+    else
+    {
+        /* While rx fifo not empty and remaining data can also trigger the last interrupt */
+        while ((base->S & SPI_S_RFIFOEF_MASK) == 0U)
+        {
+            SPI_ReadNonBlocking(base, handle->rxData, bytes);
+
+            /* Update information in handle */
+            if (handle->rxData != NULL)
+            {
+                handle->rxData += bytes;
+            }
+            handle->rxRemainingBytes -= bytes;
+
+            /* If the reamining data equals to watermark, leave to last interrupt */
+            if (handle->rxRemainingBytes == ((uint32_t)handle->watermark * 2U))
+            {
+                break;
+            }
+        }
+    }
+#endif
+}
+
+/*!
+ * brief  Sets the SPI master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
+ * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
+ * some fields of the structure before calling SPI_MasterInit(). After calling this API,
+ * the master is ready to transfer.
+ * Example:
+   code
+   spi_master_config_t config;
+   SPI_MasterGetDefaultConfig(&config);
+   endcode
+ *
+ * param config pointer to master config structure
+ */
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)(void) memset(config, 0, sizeof(*config));
+
+    config->enableMaster         = true;
+    config->enableStopInWaitMode = false;
+    config->polarity             = kSPI_ClockPolarityActiveHigh;
+    config->phase                = kSPI_ClockPhaseFirstEdge;
+    config->direction            = kSPI_MsbFirst;
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    config->dataMode = kSPI_8BitMode;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    config->txWatermark = kSPI_TxFifoOneHalfEmpty;
+    config->rxWatermark = kSPI_RxFifoOneHalfFull;
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    config->pinMode      = kSPI_PinModeNormal;
+    config->outputMode   = kSPI_SlaveSelectAutomaticOutput;
+    config->baudRate_Bps = 500000U;
+}
+
+/*!
+ * brief Initializes the SPI with master configuration.
+ *
+ * The configuration structure can be filled by user from scratch, or be set with default
+ * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
+ * Example
+   code
+   spi_master_config_t config = {
+   .baudRate_Bps = 400000,
+   ...
+   };
+   SPI_MasterInit(SPI0, &config);
+   endcode
+ *
+ * param base SPI base pointer
+ * param config pointer to master configuration structure
+ * param srcClock_Hz Source clock frequency.
+ */
+void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
+{
+    assert((config != NULL) && (srcClock_Hz != 0U));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Open clock gate for SPI and open interrupt */
+    CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable SPI before configuration */
+    base->C1 &= (uint8_t)(~SPI_C1_SPE_MASK);
+
+    /* Configure clock polarity and phase, set SPI to master */
+    base->C1 = SPI_C1_MSTR(1U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) |
+               SPI_C1_SSOE((uint8_t)config->outputMode & 1U) | SPI_C1_LSBFE((uint8_t)config->direction);
+
+/* Set data mode, and also pin mode and mode fault settings */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    base->C2 = SPI_C2_MODFEN((uint8_t)config->outputMode >> 1U) | SPI_C2_BIDIROE((uint8_t)config->pinMode >> 1U) |
+               SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0((uint8_t)config->pinMode & 1U) |
+               SPI_C2_SPIMODE(config->dataMode);
+#else
+    base->C2 = SPI_C2_MODFEN((uint8_t)config->outputMode >> 1U) | SPI_C2_BIDIROE((uint8_t)config->pinMode >> 1U) |
+               SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0((uint8_t)config->pinMode & 1U);
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+/* Set watermark, FIFO is enabled */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) |
+                   SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U);
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    /* Set baud rate */
+    SPI_MasterSetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+
+    /* Set the dummy data, this data will usefull when tx buffer is NULL. */
+    SPI_SetDummyData(base, SPI_DUMMYDATA);
+
+    /* Enable SPI */
+    if (config->enableMaster)
+    {
+        base->C1 |= SPI_C1_SPE_MASK;
+    }
+}
+
+/*!
+ * brief  Sets the SPI slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
+ * Modify some fields of the structure before calling SPI_SlaveInit().
+ * Example:
+   code
+   spi_slave_config_t config;
+   SPI_SlaveGetDefaultConfig(&config);
+   endcode
+ *
+ * param config pointer to slave configuration structure
+ */
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)(void) memset(config, 0, sizeof(*config));
+
+    config->enableSlave          = true;
+    config->polarity             = kSPI_ClockPolarityActiveHigh;
+    config->phase                = kSPI_ClockPhaseFirstEdge;
+    config->direction            = kSPI_MsbFirst;
+    config->enableStopInWaitMode = false;
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    config->dataMode = kSPI_8BitMode;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    config->txWatermark = kSPI_TxFifoOneHalfEmpty;
+    config->rxWatermark = kSPI_RxFifoOneHalfFull;
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+    config->pinMode = kSPI_PinModeNormal;
+}
+
+/*!
+ * brief Initializes the SPI with slave configuration.
+ *
+ * The configuration structure can be filled by user from scratch or be set with
+ * default values by SPI_SlaveGetDefaultConfig().
+ * After calling this API, the slave is ready to transfer.
+ * Example
+   code
+    spi_slave_config_t config = {
+    .polarity = kSPIClockPolarity_ActiveHigh;
+    .phase = kSPIClockPhase_FirstEdge;
+    .direction = kSPIMsbFirst;
+    ...
+    };
+    SPI_MasterInit(SPI0, &config);
+   endcode
+ *
+ * param base SPI base pointer
+ * param config pointer to master configuration structure
+ */
+void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
+{
+    assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Open clock gate for SPI and open interrupt */
+    CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable SPI before configuration */
+    base->C1 &= (uint8_t)(~SPI_C1_SPE_MASK);
+
+    /* Configure master and clock polarity and phase */
+    base->C1 =
+        SPI_C1_MSTR(0U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | SPI_C1_LSBFE(config->direction);
+
+/* Configure data mode if needed */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    base->C2 = SPI_C2_SPIMODE(config->dataMode) | SPI_C2_SPISWAI(config->enableStopInWaitMode) |
+               SPI_C2_BIDIROE((uint8_t)config->pinMode >> 1U) | SPI_C2_SPC0((uint8_t)config->pinMode & 1U);
+#else
+    base->C2 = SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_BIDIROE((uint8_t)config->pinMode >> 1U) |
+               SPI_C2_SPC0((uint8_t)config->pinMode & 1U);
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+/* Set watermark */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) |
+                   SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U);
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    /* Set the dummy data, this data will usefull when tx buffer is NULL. */
+    SPI_SetDummyData(base, SPI_DUMMYDATA);
+
+    /* Enable SPI */
+    if (config->enableSlave)
+    {
+        base->C1 |= SPI_C1_SPE_MASK;
+    }
+}
+
+/*!
+ * brief De-initializes the SPI.
+ *
+ * Calling this API resets the SPI module, gates the SPI clock.
+ * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
+ *
+ * param base SPI base pointer
+ */
+void SPI_Deinit(SPI_Type *base)
+{
+    /* Disable SPI module before shutting down */
+    base->C1 &= (uint8_t)(~SPI_C1_SPE_MASK);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the clock */
+    CLOCK_DisableClock(s_spiClock[SPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the status flag.
+ *
+ * param base SPI base pointer
+ * return SPI Status, use status flag to AND #_spi_flags could get the related status.
+ */
+uint32_t SPI_GetStatusFlags(SPI_Type *base)
+{
+    uint32_t status = (uint32_t)base->S;
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        status |= (((uint32_t)base->CI) << 8U);
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+    return status;
+}
+
+/*!
+ * brief Enables the interrupt for the SPI.
+ *
+ * param base SPI base pointer
+ * param mask SPI interrupt source. The parameter can be any combination of the following values:
+ *        arg kSPI_RxFullAndModfInterruptEnable
+ *        arg kSPI_TxEmptyInterruptEnable
+ *        arg kSPI_MatchInterruptEnable
+ *        arg kSPI_RxFifoNearFullInterruptEnable
+ *        arg kSPI_TxFifoNearEmptyInterruptEnable
+ */
+void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask)
+{
+    /* Rx full interrupt */
+    if ((mask & (uint32_t)kSPI_RxFullAndModfInterruptEnable) != 0U)
+    {
+        base->C1 |= SPI_C1_SPIE_MASK;
+    }
+
+    /* Tx empty interrupt */
+    if ((mask & (uint32_t)kSPI_TxEmptyInterruptEnable) != 0U)
+    {
+        base->C1 |= SPI_C1_SPTIE_MASK;
+    }
+
+    /* Data match interrupt */
+    if ((mask & (uint32_t)kSPI_MatchInterruptEnable) != 0U)
+    {
+        base->C2 |= SPI_C2_SPMIE_MASK;
+    }
+
+/* FIFO related interrupts */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        /* Rx FIFO near full interrupt */
+        if ((mask & (uint32_t)kSPI_RxFifoNearFullInterruptEnable) != 0U)
+        {
+            base->C3 |= SPI_C3_RNFULLIEN_MASK;
+        }
+
+        /* Tx FIFO near empty interrupt */
+        if ((mask & (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable) != 0U)
+        {
+            base->C3 |= SPI_C3_TNEARIEN_MASK;
+        }
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+}
+
+/*!
+ * brief Disables the interrupt for the SPI.
+ *
+ * param base SPI base pointer
+ * param mask SPI interrupt source. The parameter can be any combination of the following values:
+ *        arg kSPI_RxFullAndModfInterruptEnable
+ *        arg kSPI_TxEmptyInterruptEnable
+ *        arg kSPI_MatchInterruptEnable
+ *        arg kSPI_RxFifoNearFullInterruptEnable
+ *        arg kSPI_TxFifoNearEmptyInterruptEnable
+ */
+void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
+{
+    /* Rx full interrupt */
+    if ((mask & (uint32_t)kSPI_RxFullAndModfInterruptEnable) != 0U)
+    {
+        base->C1 &= (uint8_t)(~SPI_C1_SPIE_MASK);
+    }
+
+    /* Tx empty interrupt */
+    if ((mask & (uint32_t)kSPI_TxEmptyInterruptEnable) != 0U)
+    {
+        base->C1 &= (uint8_t)(~SPI_C1_SPTIE_MASK);
+    }
+
+    /* Data match interrupt */
+    if ((mask & (uint32_t)kSPI_MatchInterruptEnable) != 0U)
+    {
+        base->C2 &= (uint8_t)(~SPI_C2_SPMIE_MASK);
+    }
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        /* Rx FIFO near full interrupt */
+        if ((mask & (uint32_t)kSPI_RxFifoNearFullInterruptEnable) != 0U)
+        {
+            base->C3 &= (uint8_t)(~SPI_C3_RNFULLIEN_MASK);
+        }
+
+        /* Tx FIFO near empty interrupt */
+        if ((mask & (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable) != 0U)
+        {
+            base->C3 &= (uint8_t)(~SPI_C3_TNEARIEN_MASK);
+        }
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+}
+
+/*!
+ * brief Sets the baud rate for SPI transfer. This is only used in master.
+ *
+ * param base SPI base pointer
+ * param baudRate_Bps baud rate needed in Hz.
+ * param srcClock_Hz SPI source clock frequency in Hz.
+ */
+void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t prescaler;
+    uint32_t bestPrescaler;
+    uint32_t rateDivisor;
+    uint32_t bestDivisor;
+    uint32_t rateDivisorValue;
+    uint32_t realBaudrate;
+    uint32_t diff;
+    uint32_t min_diff;
+    uint32_t freq = baudRate_Bps;
+
+    /* Find combination of prescaler and scaler resulting in baudrate closest to the requested value */
+    min_diff = 0xFFFFFFFFU;
+
+    /* Set the maximum divisor bit settings for each of the following divisors */
+    bestPrescaler = 7U;
+    bestDivisor   = 8U;
+
+    /* In all for loops, if min_diff = 0, the exit for loop*/
+    for (prescaler = 0U; prescaler <= 7U; prescaler++)
+    {
+        if (min_diff == 0U)
+        {
+            break;
+        }
+        /* Initialize to div-by-2 */
+        rateDivisorValue = 2U;
+
+        for (rateDivisor = 0; rateDivisor <= 8U; rateDivisor++)
+        {
+            if (min_diff == 0U)
+            {
+                break;
+            }
+            /* Calculate actual baud rate, note need to add 1 to prescaler */
+            realBaudrate = ((srcClock_Hz) / ((prescaler + 1U) * rateDivisorValue));
+
+            /* Calculate the baud rate difference based on the conditional statement ,that states that the
+            calculated baud rate must not exceed the desired baud rate */
+            if (freq >= realBaudrate)
+            {
+                diff = freq - realBaudrate;
+                if (min_diff > diff)
+                {
+                    /* A better match found */
+                    min_diff      = diff;
+                    bestPrescaler = prescaler;
+                    bestDivisor   = rateDivisor;
+                }
+            }
+
+            /* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */
+            rateDivisorValue *= 2U;
+        }
+    }
+
+    /* Write the best prescalar and baud rate scalar */
+    base->BR = SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler);
+}
+
+/*!
+ * brief Sends a buffer of data bytes using a blocking method.
+ *
+ * note This function blocks via polling until all bytes have been sent.
+ *
+ * param base SPI base pointer
+ * param buffer The data bytes to send
+ * param size The number of data bytes to send
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size)
+{
+    uint32_t i            = 0;
+    uint8_t bytesPerFrame = 1U;
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Check if 16 bits or 8 bits */
+    bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#endif
+
+#if SPI_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (i < size)
+    {
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while (((base->S & SPI_S_SPTEF_MASK) == 0U) && (--waitTimes != 0U))
+#else
+        while ((base->S & SPI_S_SPTEF_MASK) == 0U)
+#endif
+        {
+        }
+#if SPI_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_SPI_Timeout;
+        }
+#endif
+
+        /* Send a frame of data */
+        SPI_WriteNonBlocking(base, buffer, bytesPerFrame);
+
+        i += bytesPerFrame;
+        buffer += bytesPerFrame;
+    }
+
+    return kStatus_Success;
+}
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+/*!
+ * brief Enables or disables the FIFO if there is a FIFO.
+ *
+ * param base SPI base pointer
+ * param enable True means enable FIFO, false means disable FIFO.
+ */
+void SPI_EnableFIFO(SPI_Type *base, bool enable)
+{
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        if (enable)
+        {
+            base->C3 |= SPI_C3_FIFOMODE_MASK;
+        }
+        else
+        {
+            base->C3 &= (uint8_t)(~SPI_C3_FIFOMODE_MASK);
+        }
+    }
+}
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+/*!
+ * brief Writes a data into the SPI data register.
+ *
+ * param base SPI base pointer
+ * param data needs to be write.
+ */
+void SPI_WriteData(SPI_Type *base, uint16_t data)
+{
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
+    base->DL = (uint8_t)data & 0xFFU;
+    base->DH = (uint8_t)(data >> 8U) & 0xFFU;
+#else
+    base->D = (uint8_t)data & 0xFFU;
+#endif
+}
+
+/*!
+ * brief Gets a data from the SPI data register.
+ *
+ * param base SPI base pointer
+ * return Data in the register.
+ */
+uint16_t SPI_ReadData(SPI_Type *base)
+{
+    uint16_t val = 0;
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
+    val = base->DL;
+    val |= (uint16_t)((uint16_t)(base->DH) << 8U);
+#else
+    val = base->D;
+#endif
+    return val;
+}
+
+/*!
+ * brief Transfers a block of data using a polling method.
+ *
+ * param base SPI base pointer
+ * param xfer pointer to spi_xfer_config_t structure
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
+{
+    assert(xfer != NULL);
+
+    uint8_t bytesPerFrame = 1U;
+#if SPI_RETRY_TIMES
+    uint32_t waitTimes = SPI_RETRY_TIMES;
+#endif
+
+    /* Check if the argument is legal */
+    if ((xfer->txData == NULL) && (xfer->rxData == NULL))
+    {
+        return (status_t)kStatus_InvalidArgument;
+    }
+
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    /* Check if 16 bits or 8 bits */
+    bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#endif
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+
+    /* Disable FIFO, as the FIFO may cause data loss if the data size is not integer
+       times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
+       size. */
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        base->C3 &= (uint8_t)(~SPI_C3_FIFOMODE_MASK);
+    }
+
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    /* Begin the polling transfer until all data sent */
+    while (xfer->dataSize > 0U)
+    {
+        /* Data send */
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while (((base->S & SPI_S_SPTEF_MASK) == 0U) && (--waitTimes != 0U))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_SPI_Timeout;
+        }
+#else
+        while ((base->S & SPI_S_SPTEF_MASK) == 0U)
+        {
+        }
+#endif
+        SPI_WriteNonBlocking(base, xfer->txData, bytesPerFrame);
+        if (xfer->txData != NULL)
+        {
+            xfer->txData += bytesPerFrame;
+        }
+
+#if SPI_RETRY_TIMES
+        waitTimes = SPI_RETRY_TIMES;
+        while (((base->S & SPI_S_SPRF_MASK) == 0U) && (--waitTimes != 0U))
+        {
+        }
+        if (waitTimes == 0U)
+        {
+            return kStatus_SPI_Timeout;
+        }
+#else
+        while ((base->S & SPI_S_SPRF_MASK) == 0U)
+        {
+        }
+#endif
+        SPI_ReadNonBlocking(base, xfer->rxData, bytesPerFrame);
+        if (xfer->rxData != NULL)
+        {
+            xfer->rxData += bytesPerFrame;
+        }
+
+        /* Decrease the number */
+        xfer->dataSize -= bytesPerFrame;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the SPI master handle.
+ *
+ * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI handle pointer.
+ * param callback Callback function.
+ * param userData User data.
+ */
+void SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                    spi_master_handle_t *handle,
+                                    spi_master_callback_t callback,
+                                    void *userData)
+{
+    assert(handle != NULL);
+
+    uint32_t instance = SPI_GetInstance(base);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Initialize the handle */
+    s_spiHandle[instance] = handle;
+    handle->callback      = callback;
+    handle->userData      = userData;
+    s_spiMasterIsr        = SPI_MasterTransferHandleIRQ;
+    handle->watermark     = SPI_GetWatermark(base);
+
+/* Get the bytes per frame */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
+    handle->bytePerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#else
+    handle->bytePerFrame = 1U;
+#endif
+
+    /* Enable SPI NVIC */
+    (void)EnableIRQ(s_spiIRQ[instance]);
+}
+
+/*!
+ * brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * note The API immediately returns after transfer initialization is finished.
+ * Call SPI_GetStatusIRQ() to get the transfer status.
+ * note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
+ *
+ * param base SPI peripheral base address.
+ * param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * param xfer pointer to spi_xfer_config_t structure
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+    uint32_t mask = 0U;
+
+    /* Check if SPI is busy */
+    if (handle->state == (uint32_t)kSPI_Busy)
+    {
+        return (status_t)kStatus_SPI_Busy;
+    }
+
+    /* Check if the input arguments valid */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return (status_t)kStatus_InvalidArgument;
+    }
+
+    /* Set the handle information */
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
+    handle->transferSize     = xfer->dataSize;
+    handle->txRemainingBytes = xfer->dataSize;
+    handle->rxRemainingBytes = xfer->dataSize;
+
+    /* Set the SPI state to busy */
+    handle->state = (uint32_t)kSPI_Busy;
+
+    /* Enable Interrupt */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+
+    handle->watermark = SPI_GetWatermark(base);
+
+    /* If the size of the transfer size less than watermark, set watermark to 1 */
+    if (xfer->dataSize < (uint32_t)handle->watermark * 2U)
+    {
+        handle->watermark = 1U;
+    }
+
+    /* According to watermark size, enable interrupts */
+    if (handle->watermark > 1U)
+    {
+        /* Enable Rx near full interrupt */
+        mask = (uint32_t)kSPI_RxFifoNearFullInterruptEnable;
+        /* Enable Tx near full interrupt only if there are data to send */
+        if (handle->txData != NULL)
+        {
+            mask |= (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable;
+        }
+
+        SPI_EnableFIFO(base, true);
+        /* First send a piece of data to Tx Data or FIFO to start a SPI transfer */
+        while ((base->S & SPI_S_TNEAREF_MASK) != SPI_S_TNEAREF_MASK)
+        {
+        }
+        SPI_SendInitialTransfer(base, handle);
+    }
+    else
+    {
+        /* Enable Rx full interrupt */
+        mask = (uint32_t)kSPI_RxFullAndModfInterruptEnable;
+        /* Enable Tx full interrupt only if there are data to send */
+        if (handle->txData != NULL)
+        {
+            mask |= (uint32_t)kSPI_TxEmptyInterruptEnable;
+        }
+
+        SPI_EnableFIFO(base, false);
+        while ((base->S & SPI_S_SPTEF_MASK) != SPI_S_SPTEF_MASK)
+        {
+        }
+        /* First send a piece of data to Tx Data or FIFO to start a SPI transfer */
+        SPI_SendInitialTransfer(base, handle);
+    }
+#else
+    /* Enable Rx full interrupt */
+    mask = (uint32_t)kSPI_RxFullAndModfInterruptEnable;
+    /* Enable Tx full interrupt only if there are data to send */
+    if (handle->txData != NULL)
+    {
+        mask |= (uint32_t)kSPI_TxEmptyInterruptEnable;
+    }
+
+    while ((base->S & SPI_S_SPTEF_MASK) != SPI_S_SPTEF_MASK)
+    {
+    }
+    /* First send a piece of data to Tx Data or FIFO to start a SPI transfer */
+    SPI_SendInitialTransfer(base, handle);
+#endif
+
+    SPI_EnableInterrupts(base, mask);
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the bytes of the SPI interrupt transferred.
+ *
+ * param base SPI peripheral base address.
+ * param handle Pointer to SPI transfer handle, this should be a static variable.
+ * param count Transferred bytes of SPI master.
+ * retval kStatus_SPI_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kSPI_Busy)
+    {
+        status = (status_t)kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        /* Return remaing bytes in different cases */
+        if (handle->rxData != NULL)
+        {
+            *count = handle->transferSize - handle->rxRemainingBytes;
+        }
+        else
+        {
+            *count = handle->transferSize - handle->txRemainingBytes;
+        }
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts an SPI transfer using interrupt.
+ *
+ * param base SPI peripheral base address.
+ * param handle Pointer to SPI transfer handle, this should be a static variable.
+ */
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert(handle != NULL);
+    uint32_t mask = (uint32_t)kSPI_TxEmptyInterruptEnable;
+
+    /* Stop interrupts */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    if (handle->watermark > 1U)
+    {
+        mask |= (uint32_t)kSPI_RxFifoNearFullInterruptEnable | (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable;
+    }
+    else
+    {
+        mask |= (uint32_t)kSPI_RxFullAndModfInterruptEnable | (uint32_t)kSPI_TxEmptyInterruptEnable;
+    }
+#else
+    mask |= (uint32_t)kSPI_RxFullAndModfInterruptEnable | (uint32_t)kSPI_TxEmptyInterruptEnable;
+#endif
+
+    SPI_DisableInterrupts(base, mask);
+    /* Transfer finished, set the state to Done*/
+    handle->state = (uint32_t)kSPI_Idle;
+
+    /* Clear the internal state */
+    handle->rxRemainingBytes = 0;
+    handle->txRemainingBytes = 0;
+}
+
+/*!
+ * brief Interrupts the handler for the SPI.
+ *
+ * param base SPI peripheral base address.
+ * param handle pointer to spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* If needs to receive data, do a receive */
+    if ((handle->rxRemainingBytes) != 0U)
+    {
+        SPI_ReceiveTransfer(base, handle);
+    }
+
+    /* We always need to send a data to make the SPI run */
+    /* To prevent rx overflow, calculate the difference between rxRemainingBytes
+       and txRemainingBytes and make sure the difference is smaller than watermark.
+       The watermark is set according to FIFO size, for instance that does not have
+       FIFO, the watermark is 1. */
+    if (((handle->txRemainingBytes) != 0U) &&
+        ((handle->rxRemainingBytes - handle->txRemainingBytes) < handle->watermark))
+    {
+        SPI_SendTransfer(base, handle);
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+        if (handle->txRemainingBytes == 0U)
+        {
+            SPI_DisableInterrupts(base, (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable);
+            SPI_EnableInterrupts(base, (uint32_t)kSPI_TxEmptyInterruptEnable);
+        }
+#endif
+    }
+
+    /* All the transfer finished */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        if ((SPI_GetStatusFlags(base) & (uint32_t)kSPI_TxBufferEmptyFlag) != 0U)
+        {
+            /* Complete the transfer */
+            SPI_MasterTransferAbort(base, handle);
+
+            if (handle->callback != NULL)
+            {
+                (handle->callback)(base, handle, kStatus_SPI_Idle, handle->userData);
+            }
+        }
+    }
+}
+/*!
+ * brief Initializes the SPI slave handle.
+ *
+ * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI handle pointer.
+ * param callback Callback function.
+ * param userData User data.
+ */
+void SPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                   spi_slave_handle_t *handle,
+                                   spi_slave_callback_t callback,
+                                   void *userData)
+{
+    assert(handle != NULL);
+
+    /* Slave create handle share same logic with master create handle, the only difference
+    is the Isr pointer. */
+    SPI_MasterTransferCreateHandle(base, handle, callback, userData);
+    s_spiSlaveIsr = SPI_SlaveTransferHandleIRQ;
+}
+
+/*!
+ * brief Performs a non-blocking SPI slave interrupt transfer.
+ *
+ * note The API returns immediately after the transfer initialization is finished.
+ * Call SPI_GetStatusIRQ() to get the transfer status.
+ * note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
+ *
+ * param base SPI peripheral base address.
+ * param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ * param xfer pointer to spi_xfer_config_t structure
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+    uint32_t mask = 0U;
+
+    /* Check if SPI is busy */
+    if (handle->state == (uint32_t)kSPI_Busy)
+    {
+        return (status_t)kStatus_SPI_Busy;
+    }
+
+    /* Check if the input arguments valid */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return (status_t)kStatus_InvalidArgument;
+    }
+
+    /* Read out any possible data */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    /* If instance has FIFO and FIFO is enabled. */
+    if ((FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) && ((base->C3 & SPI_C3_FIFOMODE_MASK) != 0U))
+    {
+        while ((SPI_GetStatusFlags(base) & (uint32_t)kSPI_RxFifoEmptyFlag) == 0U)
+        {
+            (void)SPI_ReadData(base);
+        }
+    }
+    else
+    {
+        if ((SPI_GetStatusFlags(base) & (uint32_t)kSPI_RxBufferFullFlag) != 0U)
+        {
+            (void)SPI_ReadData(base);
+        }
+    }
+#else
+    if ((SPI_GetStatusFlags(base) & (uint32_t)kSPI_RxBufferFullFlag) != 0U)
+    {
+        (void)SPI_ReadData(base);
+    }
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    /* Set the handle information */
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
+    handle->transferSize     = xfer->dataSize;
+    handle->txRemainingBytes = (xfer->txData == NULL) ? 0U : xfer->dataSize;
+    handle->rxRemainingBytes = (xfer->rxData == NULL) ? 0U : xfer->dataSize;
+
+    /* Set the SPI state to busy */
+    handle->state = (uint32_t)kSPI_Busy;
+
+    /* Enable Interrupt */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+
+    handle->watermark = SPI_GetWatermark(base);
+
+    /* If the size of the transfer size less than watermark, set watermark to 1 */
+    if (xfer->dataSize < (uint32_t)handle->watermark * 2U)
+    {
+        handle->watermark = 1U;
+    }
+
+    /* According to watermark size, enable interrupts */
+    if (handle->watermark > 1U)
+    {
+        /* Enable Rx near full interrupt */
+
+        if (handle->rxData != NULL)
+        {
+            mask |= (uint32_t)kSPI_RxFifoNearFullInterruptEnable;
+        }
+        /* Enable Tx near full interrupt only if there are data to send */
+        if (handle->txData != NULL)
+        {
+            mask |= (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable;
+        }
+
+        SPI_EnableFIFO(base, true);
+    }
+    else
+    {
+        /* Enable Rx full interrupt */
+        if (handle->rxData != NULL)
+        {
+            mask |= (uint32_t)kSPI_RxFullAndModfInterruptEnable;
+        }
+        /* Enable Tx full interrupt only if there are data to send */
+        if (handle->txData != NULL)
+        {
+            mask |= (uint32_t)kSPI_TxEmptyInterruptEnable;
+        }
+
+        SPI_EnableFIFO(base, false);
+    }
+#else
+    /* Enable Rx full interrupt */
+    if (handle->rxData != NULL)
+    {
+        mask |= (uint32_t)kSPI_RxFullAndModfInterruptEnable;
+    }
+    /* Enable Tx full interrupt only if there are data to send */
+    if (handle->txData != NULL)
+    {
+        mask |= (uint32_t)kSPI_TxEmptyInterruptEnable;
+    }
+#endif
+
+    SPI_EnableInterrupts(base, mask);
+    return kStatus_Success;
+}
+
+/*!
+ * brief Interrupts a handler for the SPI slave.
+ *
+ * param base SPI peripheral base address.
+ * param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ */
+void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* If needs to receive data, do a receive */
+    if ((handle->rxRemainingBytes) != 0U)
+    {
+        SPI_ReceiveTransfer(base, handle);
+    }
+
+    if ((handle->txRemainingBytes) != 0U)
+    {
+        SPI_SendTransfer(base, handle);
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+        if (handle->txRemainingBytes == 0U)
+        {
+            SPI_DisableInterrupts(base, (uint32_t)kSPI_TxFifoNearEmptyInterruptEnable);
+            SPI_EnableInterrupts(base, (uint32_t)kSPI_TxEmptyInterruptEnable);
+        }
+#endif
+    }
+
+    /* All the transfer finished */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        if ((SPI_GetStatusFlags(base) & (uint32_t)kSPI_TxBufferEmptyFlag) != 0U)
+        {
+            /* Complete the transfer */
+            SPI_SlaveTransferAbort(base, handle);
+
+            if (handle->callback != NULL)
+            {
+                handle->callback(base, handle, kStatus_SPI_Idle, handle->userData);
+            }
+        }
+    }
+}
+
+static void SPI_CommonIRQHandler(SPI_Type *base, uint32_t instance)
+{
+    if ((base->C1 & SPI_C1_MSTR_MASK) != 0U)
+    {
+        s_spiMasterIsr(base, s_spiHandle[instance]);
+    }
+    else
+    {
+        s_spiSlaveIsr(base, s_spiHandle[instance]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+#if defined(FSL_FEATURE_SPI_HAS_SHARED_IRQ0_IRQ1_IRQ2) && FSL_FEATURE_SPI_HAS_SHARED_IRQ0_IRQ1_IRQ2
+void SPI0_SPI1_SPI2_DriverIRQHandler(void);
+void SPI0_SPI1_SPI2_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 0U; instance < 3U; instance++)
+    {
+        if (s_spiHandle[instance] != NULL)
+        {
+            SPI_CommonIRQHandler(s_spiBases[instance], instance);
+        }
+    }
+}
+#elif defined(FSL_FEATURE_SPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_SPI_HAS_SHARED_IRQ0_IRQ1
+void SPI0_SPI1_DriverIRQHandler(void);
+void SPI0_SPI1_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 0U; instance < 2U; instance++)
+    {
+        if (s_spiHandle[instance] != NULL)
+        {
+            SPI_CommonIRQHandler(s_spiBases[instance], instance);
+        }
+    }
+}
+#else
+#if defined(SPI0)
+void SPI0_DriverIRQHandler(void);
+void SPI0_DriverIRQHandler(void)
+{
+    assert(s_spiHandle[0] != NULL);
+    SPI_CommonIRQHandler(SPI0, 0);
+}
+#endif
+
+#if defined(SPI1)
+void SPI1_DriverIRQHandler(void);
+void SPI1_DriverIRQHandler(void)
+{
+    assert(s_spiHandle[1] != NULL);
+    SPI_CommonIRQHandler(SPI1, 1);
+}
+#endif
+
+#if defined(SPI2)
+void SPI2_DriverIRQHandler(void);
+void SPI2_DriverIRQHandler(void)
+{
+    assert(s_spiHandle[2] != NULL);
+    SPI_CommonIRQHandler(SPI2, 2);
+}
+#endif
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.h
new file mode 100644
index 0000000000..e97f2ff7b0
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi.h
@@ -0,0 +1,713 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_SPI_H_
+#define FSL_SPI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup spi_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SPI driver version. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @} */
+
+#ifndef SPI_DUMMYDATA
+/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
+#define SPI_DUMMYDATA (0x00U)
+#endif
+
+/*! @brief Retry times for waiting flag. */
+#ifndef SPI_RETRY_TIMES
+#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t g_spiDummyData[];
+
+/*! @brief Return status for the SPI driver.*/
+enum
+{
+    kStatus_SPI_Busy    = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
+    kStatus_SPI_Idle    = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
+    kStatus_SPI_Error   = MAKE_STATUS(kStatusGroup_SPI, 2), /*!< SPI error */
+    kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_SPI, 3)  /*!< SPI timeout polling status flags. */
+};
+
+/*! @brief SPI clock polarity configuration.*/
+typedef enum _spi_clock_polarity
+{
+    kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
+    kSPI_ClockPolarityActiveLow          /*!< Active-low SPI clock (idles high). */
+} spi_clock_polarity_t;
+
+/*! @brief SPI clock phase configuration.*/
+typedef enum _spi_clock_phase
+{
+    kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
+                                      *   cycle of a data transfer. */
+    kSPI_ClockPhaseSecondEdge        /*!< First edge on SPSCK occurs at the start of the
+                                      *   first cycle of a data transfer. */
+} spi_clock_phase_t;
+
+/*! @brief SPI data shifter direction options.*/
+typedef enum _spi_shift_direction
+{
+    kSPI_MsbFirst = 0x0U, /*!< Data transfers start with most significant bit. */
+    kSPI_LsbFirst         /*!< Data transfers start with least significant bit. */
+} spi_shift_direction_t;
+
+/*! @brief SPI slave select output mode options.*/
+typedef enum _spi_ss_output_mode
+{
+    kSPI_SlaveSelectAsGpio          = 0x0U, /*!< Slave select pin configured as GPIO. */
+    kSPI_SlaveSelectFaultInput      = 0x2U, /*!< Slave select pin configured for fault detection. */
+    kSPI_SlaveSelectAutomaticOutput = 0x3U  /*!< Slave select pin configured for automatic SPI output. */
+} spi_ss_output_mode_t;
+
+/*! @brief SPI pin mode options.*/
+typedef enum _spi_pin_mode
+{
+    kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/
+    kSPI_PinModeInput  = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input;
+                                *   Slave: MISO pin is input. */
+    kSPI_PinModeOutput = 0x3U  /*!< Bidirectional mode. Master: MOSI pin is output;
+                                *   Slave: MISO pin is output. */
+} spi_pin_mode_t;
+
+/*! @brief SPI data length mode options.*/
+typedef enum _spi_data_bitcount_mode
+{
+    kSPI_8BitMode = 0x0U, /*!< 8-bit data transmission mode*/
+    kSPI_16BitMode        /*!< 16-bit data transmission mode*/
+} spi_data_bitcount_mode_t;
+
+/*! @brief SPI interrupt sources.*/
+enum _spi_interrupt_enable
+{
+    kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
+    kSPI_TxEmptyInterruptEnable       = 0x2U, /*!< Transmit buffer empty interrupt */
+    kSPI_MatchInterruptEnable         = 0x4U, /*!< Match interrupt */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    kSPI_RxFifoNearFullInterruptEnable  = 0x8U,  /*!< Receive FIFO nearly full interrupt */
+    kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */
+#endif                                           /* FSL_FEATURE_SPI_HAS_FIFO */
+};
+
+/*! @brief SPI status flags.*/
+enum _spi_flags
+{
+    kSPI_RxBufferFullFlag  = SPI_S_SPRF_MASK,  /*!< Read buffer full flag */
+    kSPI_MatchFlag         = SPI_S_SPMF_MASK,  /*!< Match flag */
+    kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */
+    kSPI_ModeFaultFlag     = SPI_S_MODF_MASK,  /*!< Mode fault flag */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    kSPI_RxFifoNearFullFlag  = SPI_S_RNFULLF_MASK,       /*!< Rx FIFO near full */
+    kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK,       /*!< Tx FIFO near empty */
+    kSPI_TxFifoFullFlag      = SPI_S_TXFULLF_MASK,       /*!< Tx FIFO full */
+    kSPI_RxFifoEmptyFlag     = SPI_S_RFIFOEF_MASK,       /*!< Rx FIFO empty */
+    kSPI_TxFifoError         = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */
+    kSPI_RxFifoError         = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO error */
+    kSPI_TxOverflow          = SPI_CI_TXFOF_MASK << 8U,  /*!< Tx FIFO Overflow */
+    kSPI_RxOverflow          = SPI_CI_RXFOF_MASK << 8U   /*!< Rx FIFO Overflow */
+#endif                                                   /* FSL_FEATURE_SPI_HAS_FIFO */
+};
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+/*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
+typedef enum _spi_w1c_interrupt
+{
+    kSPI_RxFifoFullClearInterrupt  = SPI_CI_SPRFCI_MASK,    /*!< Receive FIFO full interrupt */
+    kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK,   /*!< Transmit FIFO empty interrupt */
+    kSPI_RxNearFullClearInterrupt  = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
+    kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK  /*!< Transmit FIFO nearly empty interrupt */
+} spi_w1c_interrupt_t;
+
+/*! @brief SPI TX FIFO watermark settings.*/
+typedef enum _spi_txfifo_watermark
+{
+    kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */
+    kSPI_TxFifoOneHalfEmpty   = 1  /*!< SPI tx watermark at 1/2 FIFO size */
+} spi_txfifo_watermark_t;
+
+/*! @brief SPI RX FIFO watermark settings.*/
+typedef enum _spi_rxfifo_watermark
+{
+    kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */
+    kSPI_RxFifoOneHalfFull      = 1  /*!< SPI rx watermark at 1/2 FIFO size */
+} spi_rxfifo_watermark_t;
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
+/*! @brief SPI DMA source*/
+enum _spi_dma_enable_t
+{
+    kSPI_TxDmaEnable  = SPI_C2_TXDMAE_MASK,                       /*!< Tx DMA request source */
+    kSPI_RxDmaEnable  = SPI_C2_RXDMAE_MASK,                       /*!< Rx DMA request source */
+    kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/
+};
+#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
+
+/*! @brief SPI master user configure structure.*/
+typedef struct _spi_master_config
+{
+    bool enableMaster;               /*!< Enable SPI at initialization time */
+    bool enableStopInWaitMode;       /*!< SPI stop in wait mode */
+    spi_clock_polarity_t polarity;   /*!< Clock polarity */
+    spi_clock_phase_t phase;         /*!< Clock phase */
+    spi_shift_direction_t direction; /*!< MSB or LSB */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
+#endif                                 /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
+    spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
+#endif                                  /* FSL_FEATURE_SPI_HAS_FIFO */
+    spi_ss_output_mode_t outputMode;    /*!< SS pin setting */
+    spi_pin_mode_t pinMode;             /*!< SPI pin mode select */
+    uint32_t baudRate_Bps;              /*!< Baud Rate for SPI in Hz */
+} spi_master_config_t;
+
+/*! @brief SPI slave user configure structure.*/
+typedef struct _spi_slave_config
+{
+    bool enableSlave;                /*!< Enable SPI at initialization time */
+    bool enableStopInWaitMode;       /*!< SPI stop in wait mode */
+    spi_clock_polarity_t polarity;   /*!< Clock polarity */
+    spi_clock_phase_t phase;         /*!< Clock phase */
+    spi_shift_direction_t direction; /*!< MSB or LSB */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
+#endif                                 /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+    spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
+    spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
+#endif                                  /* FSL_FEATURE_SPI_HAS_FIFO */
+    spi_pin_mode_t pinMode;             /*!< SPI pin mode select */
+} spi_slave_config_t;
+
+/*! @brief SPI transfer structure */
+typedef struct _spi_transfer
+{
+    const uint8_t *txData; /*!< Send buffer */
+    uint8_t *rxData; /*!< Receive buffer */
+    size_t dataSize; /*!< Transfer bytes */
+    uint32_t flags;  /*!< SPI control flag, useless to SPI.*/
+} spi_transfer_t;
+
+typedef struct _spi_master_handle spi_master_handle_t;
+
+/*! @brief  Slave handle is the same with master handle  */
+typedef spi_master_handle_t spi_slave_handle_t;
+
+/*! @brief SPI master callback for finished transmit */
+typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI master callback for finished transmit */
+typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI transfer handle structure */
+struct _spi_master_handle
+{
+    const uint8_t *volatile txData;   /*!< Transfer buffer */
+    uint8_t *volatile rxData;         /*!< Receive buffer */
+    volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */
+    volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */
+    volatile uint32_t state;          /*!< SPI internal state */
+    size_t transferSize;              /*!< Bytes to be transferred */
+    uint8_t bytePerFrame;             /*!< SPI mode, 2bytes or 1byte in a frame */
+    uint8_t watermark;                /*!< Watermark value for SPI transfer */
+    spi_master_callback_t callback;   /*!< SPI callback */
+    void *userData;                   /*!< Callback parameter */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief  Sets the SPI master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
+ * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
+ * some fields of the structure before calling SPI_MasterInit(). After calling this API,
+ * the master is ready to transfer.
+ * Example:
+   @code
+   spi_master_config_t config;
+   SPI_MasterGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to master config structure
+ */
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with master configuration.
+ *
+ * The configuration structure can be filled by user from scratch, or be set with default
+ * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+   spi_master_config_t config = {
+   .baudRate_Bps = 400000,
+   ...
+   };
+   SPI_MasterInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to master configuration structure
+ * @param srcClock_Hz Source clock frequency.
+ */
+void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief  Sets the SPI slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
+ * Modify some fields of the structure before calling SPI_SlaveInit().
+ * Example:
+   @code
+   spi_slave_config_t config;
+   SPI_SlaveGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to slave configuration structure
+ */
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with slave configuration.
+ *
+ * The configuration structure can be filled by user from scratch or be set with
+ * default values by SPI_SlaveGetDefaultConfig().
+ * After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+    spi_slave_config_t config = {
+    .polarity = kSPIClockPolarity_ActiveHigh;
+    .phase = kSPIClockPhase_FirstEdge;
+    .direction = kSPIMsbFirst;
+    ...
+    };
+    SPI_MasterInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to master configuration structure
+ */
+void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
+
+/*!
+ * @brief De-initializes the SPI.
+ *
+ * Calling this API resets the SPI module, gates the SPI clock.
+ * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
+ *
+ * @param base SPI base pointer
+ */
+void SPI_Deinit(SPI_Type *base);
+
+/*!
+ * @brief Enables or disables the SPI.
+ *
+ * @param base SPI base pointer
+ * @param enable pass true to enable module, false to disable module
+ */
+static inline void SPI_Enable(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= SPI_C1_SPE_MASK;
+    }
+    else
+    {
+        base->C1 &= (uint8_t)~SPI_C1_SPE_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the status flag.
+ *
+ * @param base SPI base pointer
+ * @return SPI Status, use status flag to AND #_spi_flags could get the related status.
+ */
+uint32_t SPI_GetStatusFlags(SPI_Type *base);
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+/*!
+ * @brief Clear the interrupt if enable INCTLR.
+ *
+ * @param base SPI base pointer
+ * @param mask Interrupt need to be cleared
+ *      The parameter could be any combination of the following values:
+ *          @arg kSPI_RxFullAndModfInterruptEnable
+ *          @arg kSPI_TxEmptyInterruptEnable
+ *          @arg kSPI_MatchInterruptEnable
+ *          @arg kSPI_RxFifoNearFullInterruptEnable
+ *          @arg kSPI_TxFifoNearEmptyInterruptEnable
+ */
+static inline void SPI_ClearInterrupt(SPI_Type *base, uint8_t mask)
+{
+    base->CI |= mask;
+}
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param mask SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxFullAndModfInterruptEnable
+ *        @arg kSPI_TxEmptyInterruptEnable
+ *        @arg kSPI_MatchInterruptEnable
+ *        @arg kSPI_RxFifoNearFullInterruptEnable
+ *        @arg kSPI_TxFifoNearEmptyInterruptEnable
+ */
+void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param mask SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxFullAndModfInterruptEnable
+ *        @arg kSPI_TxEmptyInterruptEnable
+ *        @arg kSPI_MatchInterruptEnable
+ *        @arg kSPI_RxFifoNearFullInterruptEnable
+ *        @arg kSPI_TxFifoNearEmptyInterruptEnable
+ */
+void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
+/*!
+ * @brief Enables the DMA source for SPI.
+ *
+ * @param base SPI base pointer
+ * @param mask SPI DMA source.
+ * @param enable True means enable DMA, false means disable DMA
+ */
+static inline void SPI_EnableDMA(SPI_Type *base, uint8_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->C2 |= mask;
+    }
+    else
+    {
+        base->C2 &= ~mask;
+    }
+}
+#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
+
+/*!
+ * @brief  Gets the SPI tx/rx data register address.
+ *
+ * This API is used to provide a transfer address for the SPI DMA transfer configuration.
+ *
+ * @param base SPI base pointer
+ * @return data register address
+ */
+static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
+{
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    return (uint32_t)(&(base->DL));
+#else
+    return (uint32_t)(&(base->D));
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Get the instance for SPI module.
+ *
+ * @param base SPI base address
+ */
+uint32_t SPI_GetInstance(SPI_Type *base);
+
+/*!
+ * @brief Sets the pin mode for transfer.
+ *
+ * @param base SPI base pointer
+ * @param pinMode pin mode for transfer AND _spi_pin_mode could get the related configuration.
+ */
+static inline void SPI_SetPinMode(SPI_Type *base, spi_pin_mode_t pinMode)
+{
+    /* Clear SPC0 and BIDIROE bit. */
+    base->C2 &= (uint8_t) ~(SPI_C2_BIDIROE_MASK | SPI_C2_SPC0_MASK);
+    /* Set pin mode for transfer. */
+    base->C2 |= SPI_C2_BIDIROE((uint8_t)pinMode >> 1U) | SPI_C2_SPC0((uint8_t)pinMode & 1U);
+}
+
+/*!
+ * @brief Sets the baud rate for SPI transfer. This is only used in master.
+ *
+ * @param base SPI base pointer
+ * @param baudRate_Bps baud rate needed in Hz.
+ * @param srcClock_Hz SPI source clock frequency in Hz.
+ */
+void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sets the match data for SPI.
+ *
+ * The match data is a hardware comparison value. When the value received in the SPI receive data
+ * buffer equals the hardware comparison value, the SPI Match Flag in the S register (S[SPMF]) sets.
+ * This can also generate an interrupt if the enable bit sets.
+ *
+ * @param base SPI base pointer
+ * @param matchData Match data.
+ */
+static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
+{
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
+    base->ML = (uint8_t)matchData & 0xFFU;
+    base->MH = (uint8_t)(matchData >> 8U) & 0xFFU;
+#else
+    base->M = (uint8_t)matchData;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+}
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
+/*!
+ * @brief Enables or disables the FIFO if there is a FIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable FIFO, false means disable FIFO.
+ */
+void SPI_EnableFIFO(SPI_Type *base, bool enable);
+#endif
+
+/*!
+ * @brief Sends a buffer of data bytes using a blocking method.
+ *
+ * @note This function blocks via polling until all bytes have been sent.
+ *
+ * @param base SPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ * @return kStatus_SPI_Timeout The transfer timed out and was aborted.
+ */
+status_t SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
+
+/*!
+ * @brief Writes a data into the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @param data needs to be write.
+ */
+void SPI_WriteData(SPI_Type *base, uint16_t data);
+
+/*!
+ * @brief Gets a data from the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @return Data in the register.
+ */
+uint16_t SPI_ReadData(SPI_Type *base);
+
+/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base SPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPI master handle.
+ *
+ * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                    spi_master_handle_t *handle,
+                                    spi_master_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transfers a block of data using a polling method.
+ *
+ * @param base SPI base pointer
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * @note The API immediately returns after transfer initialization is finished.
+ * Call SPI_GetStatusIRQ() to get the transfer status.
+ * @note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the bytes of the SPI interrupt transferred.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to SPI transfer handle, this should be a static variable.
+ * @param count Transferred bytes of SPI master.
+ * @retval kStatus_SPI_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an SPI transfer using interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to SPI transfer handle, this should be a static variable.
+ */
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Interrupts the handler for the SPI.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Initializes the SPI slave handle.
+ *
+ * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void SPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                   spi_slave_handle_t *handle,
+                                   spi_slave_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Performs a non-blocking SPI slave interrupt transfer.
+ *
+ * @note The API returns immediately after the transfer initialization is finished.
+ * Call SPI_GetStatusIRQ() to get the transfer status.
+ * @note If SPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the bytes of the SPI interrupt transferred.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to SPI transfer handle, this should be a static variable.
+ * @param count Transferred bytes of SPI slave.
+ * @retval kStatus_SPI_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCount(base, handle, count);
+}
+
+/*!
+ * @brief Aborts an SPI slave transfer using interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to SPI transfer handle, this should be a static variable.
+ */
+static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferAbort(base, handle);
+}
+
+/*!
+ * @brief Interrupts a handler for the SPI slave.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ */
+void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* FSL_SPI_H_*/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.c
new file mode 100644
index 0000000000..c3439e6658
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_spi_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.spi_dma"
+#endif
+
+/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
+typedef struct _spi_dma_private_handle
+{
+    SPI_Type *base;
+    spi_dma_handle_t *handle;
+} spi_dma_private_handle_t;
+
+/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _spi_dma_states_t
+{
+    kSPI_Idle = 0x0, /*!< SPI is idle state */
+    kSPI_Busy        /*!< SPI is busy tranferring data. */
+};
+
+/*<! Private handle only used for internally. */
+static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
+
+/* If the RX data is not required, save it to this variable. */
+static uint16_t s_spiDmaRxDrop;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief DMA callback function for SPI send transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief DMA callback function for SPI receive transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle          = privHandle->handle;
+    SPI_Type *base                       = privHandle->base;
+
+    /* Disable Tx dma */
+    SPI_EnableDMA(base, (uint8_t)kSPI_TxDmaEnable, false);
+
+    /* Stop DMA transfer */
+    DMA_StopTransfer(spiHandle->txHandle);
+
+    /* change the state */
+    spiHandle->txInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = (uint32_t)kSPI_Idle;
+        if (spiHandle->callback != NULL)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle          = privHandle->handle;
+    SPI_Type *base                       = privHandle->base;
+
+    /* Disable Tx dma */
+    SPI_EnableDMA(base, (uint8_t)kSPI_RxDmaEnable, false);
+
+    /* Stop DMA transfer */
+    DMA_StopTransfer(spiHandle->rxHandle);
+
+    /* change the state */
+    spiHandle->rxInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = (uint32_t)kSPI_Idle;
+        if (spiHandle->callback != NULL)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Initialize the SPI master DMA handle.
+ *
+ * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI handle pointer.
+ * param callback User callback function called at the end of a transfer.
+ * param userData User data for callback.
+ * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+void SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                       spi_dma_handle_t *handle,
+                                       spi_dma_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txHandle,
+                                       dma_handle_t *rxHandle)
+{
+    assert(handle != NULL);
+    uint32_t instance = SPI_GetInstance(base);
+
+    /* Zero the handle */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set spi base to handle */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle */
+    handle->state = (uint32_t)kSPI_Idle;
+
+    /* Set handle to global state */
+    s_dmaPrivateHandle[instance].base   = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+/* Compute internal state */
+#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
+    handle->bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
+#else
+    handle->bytesPerFrame = 1U;
+#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
+
+#if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
+    /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer
+       times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
+       size. */
+    if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
+    {
+        base->C3 &= (uint8_t)(~SPI_C3_FIFOMODE_MASK);
+    }
+
+#endif /* FSL_FEATURE_SPI_HAS_FIFO */
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
+    DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
+}
+
+/*!
+ * brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI DMA handle pointer.
+ * param xfer Pointer to dma transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    assert((handle != NULL) && (xfer != NULL));
+
+    dma_transfer_config_t config = {0};
+
+    /* Check if the device is busy */
+    if (handle->state == (uint32_t)kSPI_Busy)
+    {
+        return (status_t)kStatus_SPI_Busy;
+    }
+
+    /* Check if input parameter invalid */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return (status_t)kStatus_InvalidArgument;
+    }
+
+    /* Disable SPI and then enable it, this is used to clear S register*/
+    SPI_Enable(base, false);
+    SPI_Enable(base, true);
+
+    /* Configure DMA transfer. */
+    if (handle->bytesPerFrame == 1U)
+    {
+        config.srcSize  = kDMA_Transfersize8bits;
+        config.destSize = kDMA_Transfersize8bits;
+    }
+    else
+    {
+        config.srcSize  = kDMA_Transfersize16bits;
+        config.destSize = kDMA_Transfersize16bits;
+    }
+    config.transferSize = xfer->dataSize;
+
+    /* Configure tx transfer DMA */
+    config.destAddr            = SPI_GetDataRegisterAddress(base);
+    config.enableDestIncrement = false;
+    /* Configure DMA channel */
+    if (xfer->txData != NULL)
+    {
+        config.enableSrcIncrement = true;
+        config.srcAddr            = (uint32_t)(xfer->txData);
+    }
+    else
+    {
+        /* Disable the source increasement and source set to dummyData */
+        config.enableSrcIncrement = false;
+        config.srcAddr            = (uint32_t)(&g_spiDummyData[SPI_GetInstance(base)]);
+    }
+    (void)DMA_SubmitTransfer(handle->txHandle, &config, 1U);
+
+    /*
+     * Configure rx transfer DMA.
+     * To make sure TX data has been sent out to bus, SPI DMA driver
+     * checks the RX data count. When the RX data reaches the
+     * desired count, it means TX data has been sent out to bus.
+     * So DMA RX is enabled even when RX data is not desired,
+     * and the data is saved to variable and dropped.
+     */
+    config.srcAddr            = SPI_GetDataRegisterAddress(base);
+    config.enableSrcIncrement = false;
+
+    if (xfer->rxData != NULL)
+    {
+        config.destAddr            = (uint32_t)(xfer->rxData);
+        config.enableDestIncrement = true;
+    }
+    else
+    {
+        config.destAddr            = (uint32_t)(&s_spiDmaRxDrop);
+        config.enableDestIncrement = false;
+    }
+    (void)DMA_SubmitTransfer(handle->rxHandle, &config, (uint32_t)kDMA_EnableInterrupt);
+
+    /* Change the state of handle */
+    handle->transferSize = xfer->dataSize;
+    handle->state        = (uint32_t)kSPI_Busy;
+
+    /* Start Rx transfer */
+    handle->rxInProgress = true;
+    SPI_EnableDMA(base, (uint8_t)kSPI_RxDmaEnable, true);
+    DMA_StartTransfer(handle->rxHandle);
+
+    /* Always start Tx transfer */
+    handle->txInProgress = true;
+    SPI_EnableDMA(base, (uint8_t)kSPI_TxDmaEnable, true);
+    DMA_StartTransfer(handle->txHandle);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Get the transferred bytes for SPI slave DMA.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI DMA handle pointer.
+ * param count Transferred bytes.
+ * retval kStatus_SPI_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != (uint32_t)kSPI_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        if (handle->rxInProgress)
+        {
+            *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
+        }
+        else
+        {
+            *count = handle->transferSize - DMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel);
+        }
+    }
+
+    return status;
+}
+
+/*!
+ * brief Abort a SPI transfer using DMA.
+ *
+ * param base SPI peripheral base address.
+ * param handle SPI DMA handle pointer.
+ */
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable dma */
+    DMA_StopTransfer(handle->txHandle);
+    DMA_StopTransfer(handle->rxHandle);
+
+    /* Disable DMA enable bit */
+    SPI_EnableDMA(base, (uint8_t)kSPI_DmaAllEnable, false);
+
+    /* Set the handle state */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+    handle->state        = (uint32_t)kSPI_Idle;
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.h
new file mode 100644
index 0000000000..5b42798811
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_spi_dma.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_SPI_DMA_H_
+#define FSL_SPI_DMA_H_
+
+#include "fsl_spi.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup spi_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SPI DMA driver version. */
+#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @} */
+
+typedef struct _spi_dma_handle spi_dma_handle_t;
+
+/*! @brief SPI DMA callback called at the end of transfer. */
+typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spi_dma_handle
+{
+    bool txInProgress;           /*!< Send transfer finished */
+    bool rxInProgress;           /*!< Receive transfer finished */
+    dma_handle_t *txHandle;      /*!< DMA handler for SPI send */
+    dma_handle_t *rxHandle;      /*!< DMA handler for SPI receive */
+    uint8_t bytesPerFrame;       /*!< Bytes in a frame for SPI transfer */
+    spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;              /*!< User Data for SPI DMA callback */
+    uint32_t state;              /*!< Internal state of SPI DMA transfer */
+    size_t transferSize;         /*!< Bytes need to be transfer */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initialize the SPI master DMA handle.
+ *
+ * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+void SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                       spi_dma_handle_t *handle,
+                                       spi_dma_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txHandle,
+                                       dma_handle_t *rxHandle);
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
+
+/*!
+ * @brief Get the transferred bytes for SPI slave DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param count Transferred bytes.
+ * @retval kStatus_SPI_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Initialize the SPI slave DMA handle.
+ *
+ * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+static inline void SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
+                                                    spi_dma_handle_t *handle,
+                                                    spi_dma_callback_t callback,
+                                                    void *userData,
+                                                    dma_handle_t *txHandle,
+                                                    dma_handle_t *rxHandle)
+{
+    SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferDMA(base, handle, xfer);
+}
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    SPI_MasterTransferAbortDMA(base, handle);
+}
+
+/*!
+ * @brief Get the transferred bytes for SPI slave DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param count Transferred bytes.
+ * @retval kStatus_SPI_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCountDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.c
new file mode 100644
index 0000000000..750371361b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.c
@@ -0,0 +1,1144 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_tpm.h"
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification tpm_c_ref_1$
+ * Hardware limitations make this code impossible to implement.
+ *
+ * $Justification tpm_c_ref_2$
+ * Because the incoming base is invalid, the second judgment is not continued after the first condition
+ * is established.
+ *
+ * $Justification tpm_c_ref_3$
+ * Hardware limitations, the 32-bit counter register makes counterMax = 0xffffffffu,
+ * and the mod vlue can't be greater than or equal to counterMax after the operation.
+ *
+ * $Justification tpm_c_ref_4$
+ * If the incoming base can not make (1U == (uint8_t)FSL_FEATURE_TPM_POL_HAS_EFFECTn(base) true,
+ * the subsequent register operation is incorrect.
+ *
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.tpm"
+#endif
+
+#define TPM_COMBINE_SHIFT (8U)
+
+#if defined(TPM_RSTS)
+#define TPM_RESETS_ARRAY TPM_RSTS
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to TPM bases for each instance. */
+static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to TPM clocks for each instance. */
+static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* Array of TPM callback function pointer. */
+static tpm_callback_t s_tpmCallback[ARRAY_SIZE(s_tpmBases)];
+
+/* Array to map TPM instance to IRQ number. */
+static const IRQn_Type s_tpmIRQ[] = TPM_IRQS;
+
+#if defined(TPM_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_tpmResets[] = TPM_RESETS_ARRAY;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Gets the instance from the base address
+ *
+ * param base TPM peripheral base address
+ * return The TPM instance
+ */
+uint32_t TPM_GetInstance(TPM_Type *base)
+{
+    uint32_t instance;
+    uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    /*
+     * $Branch Coverage Justification$
+     * (instance >= tpmArrayCount) not covered.
+     * The peripheral base address is always valid.
+     */
+    for (instance = 0; instance < tpmArrayCount; instance++)
+    {
+        if (s_tpmBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < tpmArrayCount);
+
+    return instance;
+}
+
+/*!
+ * brief Ungates the TPM clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the TPM driver.
+ *
+ * param base   TPM peripheral base address
+ * param config Pointer to user's TPM config structure.
+ */
+void TPM_Init(TPM_Type *base, const tpm_config_t *config)
+{
+    assert(NULL != config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the module clock */
+    (void)CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(TPM_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_tpmResets[TPM_GetInstance(base)]);
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
+    /* TPM reset is available on certain SoC's */
+    TPM_Reset(base);
+#endif
+
+    /* Set the clock prescale factor */
+    base->SC = TPM_SC_PS(config->prescale);
+#if !(defined(FSL_FEATURE_TPM_HAS_NO_CONF) && FSL_FEATURE_TPM_HAS_NO_CONF)
+    /* Setup the counter operation */
+    base->CONF = TPM_CONF_DOZEEN(config->enableDoze) |
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN) && FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN
+                 TPM_CONF_GTBEEN(config->useGlobalTimeBase) |
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC) && FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC
+                 TPM_CONF_GTBSYNC(config->syncGlobalTimeBase) |
+#endif
+                 TPM_CONF_CROT(config->enableReloadOnTrigger) |
+                 TPM_CONF_CSOT(config->enableStartOnTrigger) | TPM_CONF_CSOO(config->enableStopOnOverflow) |
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+                 TPM_CONF_CPOT(config->enablePauseOnTrigger) |
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+                 TPM_CONF_TRGSRC(config->triggerSource) | TPM_CONF_TRGPOL(config->extTriggerPolarity) |
+#endif
+                 TPM_CONF_TRGSEL(config->triggerSelect);
+    if (true == config->enableDebugMode)
+    {
+        base->CONF |= TPM_CONF_DBGMODE_MASK;
+    }
+    else
+    {
+        base->CONF &= ~TPM_CONF_DBGMODE_MASK;
+    }
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    base->POL = config->chnlPolarity;
+#endif
+}
+
+/*!
+ * brief Stops the counter and gates the TPM clock
+ *
+ * param base TPM peripheral base address
+ */
+void TPM_Deinit(TPM_Type *base)
+{
+#if defined(FSL_FEATURE_TPM_HAS_SC_CLKS) && FSL_FEATURE_TPM_HAS_SC_CLKS
+    /* Stop the counter */
+    base->SC &= ~TPM_SC_CLKS_MASK;
+#else
+    /* Stop the counter */
+    base->SC &= ~TPM_SC_CMOD_MASK;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the TPM clock */
+    (void)CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief  Fill in the TPM config struct with the default settings
+ *
+ * The default values are:
+ * code
+ *     config->prescale = kTPM_Prescale_Divide_1;
+ *     config->useGlobalTimeBase = false;
+ *     config->syncGlobalTimeBase = false;
+ *     config->dozeEnable = false;
+ *     config->dbgMode = false;
+ *     config->enableReloadOnTrigger = false;
+ *     config->enableStopOnOverflow = false;
+ *     config->enableStartOnTrigger = false;
+ *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+ *     config->enablePauseOnTrigger = false;
+ *#endif
+ *     config->triggerSelect = kTPM_Trigger_Select_0;
+ *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+ *     config->triggerSource = kTPM_TriggerSource_External;
+ *     config->extTriggerPolarity = kTPM_ExtTrigger_Active_High;
+ *#endif
+ *#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+ *     config->chnlPolarity = 0U;
+ *#endif
+ * endcode
+ * param config Pointer to user's TPM config structure.
+ */
+void TPM_GetDefaultConfig(tpm_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* TPM clock divide by 1 */
+    config->prescale = kTPM_Prescale_Divide_1;
+#if !(defined(FSL_FEATURE_TPM_HAS_NO_CONF) && FSL_FEATURE_TPM_HAS_NO_CONF)
+    /* Use internal TPM counter as timebase */
+    config->useGlobalTimeBase = false;
+    /* Disable internal TPM counter sync with global timebase */
+    config->syncGlobalTimeBase = false;
+    /* TPM counter continues in doze mode */
+    config->enableDoze = false;
+    /* TPM counter pauses when in debug mode */
+    config->enableDebugMode = false;
+    /* TPM counter will not be reloaded on input trigger */
+    config->enableReloadOnTrigger = false;
+    /* TPM counter continues running after overflow */
+    config->enableStopOnOverflow = false;
+    /* TPM counter starts immediately once it is enabled */
+    config->enableStartOnTrigger = false;
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+    config->enablePauseOnTrigger = false;
+#endif
+    /* Choose trigger select 0 as input trigger for controlling counter operation */
+    config->triggerSelect = kTPM_Trigger_Select_0;
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+    /* Choose external trigger source (high active) to control counter operation */
+    config->triggerSource      = kTPM_TriggerSource_External;
+    config->extTriggerPolarity = kTPM_ExtTrigger_Active_High;
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    /* Default channel polarity is active high */
+    config->chnlPolarity = 0U;
+#endif
+#endif
+}
+
+/*!
+ * brief Calculates the counter clock prescaler.
+ *
+ * This function calculates the values for SC[PS].
+ *
+ * param base                TPM peripheral base address
+ * param counterPeriod_Hz    The desired frequency in Hz which corresponding to the time when the counter reaches the
+ * mod value param srcClock_Hz   TPM counter clock in Hz
+ *
+ * return Calculated clock prescaler value.
+ */
+tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)
+{
+    uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base);
+    uint32_t i;
+    assert(((srcClock_Hz / 2U) > counterPeriod_Hz) && ((srcClock_Hz / 128U / counterMax) <= counterPeriod_Hz));
+
+    for (i = 0U; i < (uint32_t)kTPM_Prescale_Divide_128; i++)
+    {
+        if ((srcClock_Hz / (1UL << i) / counterMax) < counterPeriod_Hz)
+        {
+            break;
+        }
+    }
+    return (tpm_clock_prescale_t)i;
+}
+
+/*!
+ * brief Set parameters for PWM duty cycle and edges for a single tpm channel
+ *
+ * User calls this function to configure the mode, duty cycle and edge of a single PWM signal.
+ *
+ * param base        TPM peripheral base address
+ * param mod         PWM period
+ * param mode        PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
+ * param chnlParams  A structure for configuring PWM channel parameters, used to configure the channel.
+ *
+ * return kStatus_Success if the PWM setup was successful,
+ *         kStatus_Error on failure
+ */
+static status_t TPM_SetupSinglePwmChannel(TPM_Type *base,
+                                          uint32_t mod,
+                                          tpm_pwm_mode_t mode,
+                                          tpm_chnl_pwm_signal_param_t chnlParams)
+{
+    uint32_t cnv;
+    uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base);
+    uint8_t controlBits;
+    uint8_t chnlId;
+
+    /* MSnB:MSnA field value always be 10, ELSnB:ELSnA field value should config according to the channel params */
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT
+    controlBits =
+        (uint8_t)((uint32_t)kTPM_ChnlMSBMask | TPM_CnSC_ELSB(chnlParams.pauseLevel) | TPM_CnSC_ELSA(chnlParams.level));
+#else
+    controlBits = ((uint8_t)kTPM_ChnlMSBMask | ((uint8_t)chnlParams.level << TPM_CnSC_ELSA_SHIFT));
+#endif
+    chnlId = (uint8_t)chnlParams.chnlNumber;
+    /* Return error if requested dutycycle/chnlNumber is greater than the max allowed */
+    /*
+     * $Branch Coverage Justification$
+     * (-1 == (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) not covered.
+     * This function is called inside the TPM_SetupPwm() function.
+     * If you enter an invalid base, the function will not work properly.
+     */
+    if ((chnlId >= (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) ||
+        /*
+         * $Branch Coverage Justification$
+         * (chnlId >= (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) not covered.  $ref tpm_c_ref_2$.
+         */
+        (-1 == (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Return error if requested dutycycle is greater than the max allowed or MOD equal to 0xFFFF when it want get a
+     * 100% duty cycle PWM signal*/
+    /*
+     * $Branch Coverage Justification$
+     * (mod == counterMax) not covered. $ref tpm_c_ref_3$.
+     */
+    if (((chnlParams.dutyCyclePercent == 100U) && (mod == counterMax)) || (chnlParams.dutyCyclePercent > 100U))
+    {
+        return kStatus_OutOfRange;
+    }
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if (mode == kTPM_CombinedPwm)
+    {
+        /* Check added for combined mode */
+        /*
+         * $Branch Coverage Justification$
+         * (chnlId >= ((uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U)) not covered. $ref tpm_c_ref_2$.
+         */
+        if ((chnlId >= ((uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U)) ||
+            (1U != (uint8_t)FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)))
+        {
+            /* The instance should support combine mode and the channel number should be the pair number */
+            return kStatus_InvalidArgument;
+        }
+        if (((chnlParams.firstEdgeDelayPercent + chnlParams.dutyCyclePercent) > 100U) ||
+            ((chnlParams.firstEdgeDelayPercent > 0U) && (chnlParams.dutyCyclePercent == 0U)) ||
+            ((chnlParams.firstEdgeDelayPercent == 0U) && (chnlParams.deadTimeValue[0] != 0U)))
+        {
+            /* Return error if the following situation occurs :
+             * firstEdgeDelayPercent + dutyCyclePercent > 100
+             * firstEdgeDelayPercent > 0 and dutyCyclePercent == 0
+             * firstEdgeDelayPercent == 0 and deadTimeValue[0] != 0
+             */
+            return kStatus_OutOfRange;
+        }
+        /* Configure delay of the first edge */
+        uint32_t cnvFirstEdge;
+        /* Configure dutycycle */
+        if (chnlParams.dutyCyclePercent == 0U)
+        {
+            cnvFirstEdge = mod + 1U;
+            cnv          = 0;
+        }
+        else if (chnlParams.dutyCyclePercent == 100U)
+        {
+            cnvFirstEdge = 0U;
+            cnv          = mod + 1U;
+        }
+        else
+        {
+            cnvFirstEdge = (mod * chnlParams.firstEdgeDelayPercent) / 100U;
+            cnv          = (mod * chnlParams.dutyCyclePercent) / 100U;
+        }
+
+        /* Set the combine bit for the channel pair */
+        base->COMBINE |= 1UL << (TPM_COMBINE_SHIFT * chnlId);
+
+        chnlId *= 2U;
+        /* Set deadtime insertion for the channel pair using channel filter register */
+        uint32_t filterVal = base->FILTER;
+        /* Clear the channel pair's filter values */
+        filterVal &=
+            ~(((uint32_t)TPM_FILTER_CH0FVAL_MASK | TPM_FILTER_CH1FVAL_MASK) << (chnlId * TPM_FILTER_CH1FVAL_SHIFT));
+        /* Shift the deadtime insertion value to the right place in the register */
+        filterVal |= (TPM_FILTER_CH0FVAL(chnlParams.deadTimeValue[0]) | TPM_FILTER_CH1FVAL(chnlParams.deadTimeValue[1]))
+                     << (chnlId * TPM_FILTER_CH1FVAL_SHIFT);
+        base->FILTER = filterVal;
+
+        /* When switching mode, disable channel n first */
+        TPM_DisableChannel(base, (tpm_chnl_t)chnlId);
+        /* Set the requested PWM mode for channel n, under combine PWM mode, the active level is opposite of
+         * edge-aligned mode */
+        TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK);
+        /* Set the channel n value */
+        do
+        {
+            base->CONTROLS[chnlId].CnV = cnvFirstEdge;
+            /*
+             * $Branch Coverage Justification$
+             * (cnvFirstEdge != base->CONTROLS[chnlId].CnV) not covered. $ref tpm_c_ref_1$.
+             */
+        } while (cnvFirstEdge != base->CONTROLS[chnlId].CnV);
+
+        chnlId += 1U;
+        /* When switching mode, disable channel n + 1 */
+        TPM_DisableChannel(base, (tpm_chnl_t)chnlId);
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT
+        /* Select the pause level for second channel */
+        controlBits = (uint8_t)((uint32_t)kTPM_ChnlMSBMask | TPM_CnSC_ELSB(chnlParams.secPauseLevel) |
+                                TPM_CnSC_ELSA(chnlParams.level));
+#endif
+        /* Set the requested PWM mode for channel n + 1 */
+        if (chnlParams.enableComplementary)
+        {
+            /* Change the polarity on the second channel get complementary PWM signals */
+            TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits);
+        }
+        else
+        {
+            /* Second channel use same control bits as first channel */
+            TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK);
+        }
+
+        /* Set the channel n+1 value */
+        do
+        {
+            base->CONTROLS[chnlId].CnV = cnvFirstEdge + cnv;
+            /*
+             * $Branch Coverage Justification$
+             * ((cnvFirstEdge + cnv) != base->CONTROLS[chnlId].CnV) not covered. $ref tpm_c_ref_1$.
+             */
+        } while ((cnvFirstEdge + cnv) != base->CONTROLS[chnlId].CnV);
+    }
+    else
+    {
+#endif
+        /* Configure dutycycle */
+        if (chnlParams.dutyCyclePercent == 100U)
+        {
+            cnv = mod + 1U;
+        }
+        else
+        {
+            cnv = (mod * chnlParams.dutyCyclePercent) / 100U;
+        }
+        /* Fix ERROR050050 When TPM is configured in EPWM mode as PS = 0, the compare event is missed on
+        the first reload/overflow after writing 1 to the CnV register and causes an incorrect duty output.*/
+#if (defined(FSL_FEATURE_TPM_HAS_ERRATA_050050) && FSL_FEATURE_TPM_HAS_ERRATA_050050)
+        assert(!(mode == kTPM_EdgeAlignedPwm && cnv == 1U && (base->SC & TPM_SC_PS_MASK) == kTPM_Prescale_Divide_1));
+#endif
+        /* When switching mode, disable channel first */
+        TPM_DisableChannel(base, (tpm_chnl_t)chnlId);
+        /* Set the requested PWM mode, output mode MSnB:MSnA field value set to 10 */
+        TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits);
+        do
+        {
+            base->CONTROLS[chnlId].CnV = cnv;
+            /*
+             * $Branch Coverage Justification$
+             * (cnv != base->CONTROLS[chnlId].CnV) not covered. $ref tpm_c_ref_1$.
+             */
+        } while (cnv != base->CONTROLS[chnlId].CnV);
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    }
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the PWM signal parameters
+ *
+ * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
+ * function to configure all the TPM channels that will be used to output a PWM signal
+ *
+ * param base        TPM peripheral base address
+ * param chnlParams  Array of PWM channel parameters to configure the channel(s)
+ * param numOfChnls  Number of channels to configure, this should be the size of the array passed in
+ * param mode        PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
+ * param pwmFreq_Hz  PWM signal frequency in Hz
+ * param srcClock_Hz TPM counter clock in Hz
+ *
+ * return kStatus_Success if the PWM setup was successful,
+ *         kStatus_Error on failure
+ */
+status_t TPM_SetupPwm(TPM_Type *base,
+                      const tpm_chnl_pwm_signal_param_t *chnlParams,
+                      uint8_t numOfChnls,
+                      tpm_pwm_mode_t mode,
+                      uint32_t pwmFreq_Hz,
+                      uint32_t srcClock_Hz)
+{
+    assert(NULL != chnlParams);
+
+    uint32_t mod        = 0U;
+    uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base);
+    uint32_t tpmClock   = (srcClock_Hz / (1UL << (base->SC & TPM_SC_PS_MASK)));
+    status_t status     = kStatus_Success;
+
+    if ((0U == pwmFreq_Hz) || (0U == srcClock_Hz) || (0U == numOfChnls) || (tpmClock < pwmFreq_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    switch (mode)
+    {
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+        case kTPM_CombinedPwm:
+#endif
+        case kTPM_EdgeAlignedPwm:
+            base->SC &= ~TPM_SC_CPWMS_MASK;
+            mod = (tpmClock / pwmFreq_Hz) - 1U;
+
+            /*
+             * $Branch Coverage Justification$
+             * (mod > counterMax) not covered. $ref tpm_c_tpm_3$.
+             */
+            if ((mod > counterMax) || (mod == 0U))
+            {
+                /*  The MOD greater than the maximum allowed (some instanse only support 16-bit counter) or smaller than
+                1, probably would require changing clock source to get the desired frequency. */
+                status = kStatus_OutOfRange;
+            }
+            break;
+        case kTPM_CenterAlignedPwm:
+            base->SC |= TPM_SC_CPWMS_MASK;
+            mod = tpmClock / (pwmFreq_Hz * 2u);
+            /*
+             * $Branch Coverage Justification$
+             * (mod > counterMax >> 1U) not covered. $ref tpm_c_tpm_3$.
+             */
+            if ((mod > (counterMax >> 1U)) || (mod == 0U))
+            {
+                /* MOD values have additional requirements under center-aligned MODE, it must be kept in the range
+                 * of 0x1 ~ 0x7FFF (under 16-bit counter). */
+                status = kStatus_OutOfRange;
+            }
+            break;
+        default:
+            /* All the cease have been listed above, the default case should not be reached. */
+            status = kStatus_InvalidArgument;
+            break;
+    }
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+    /* Set the PWM period */
+    base->MOD = mod;
+
+    /* Setup each TPM channel */
+    for (uint8_t i = 0; i < numOfChnls; i++)
+    {
+        /* Setup a single PWM channel */
+        status = TPM_SetupSinglePwmChannel(base, mod, mode, *chnlParams);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        chnlParams++;
+    }
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* The TPM's QDCTRL register required to be effective */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base))
+    {
+        /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
+#endif
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Update the duty cycle of an active PWM signal
+ *
+ * param base              TPM peripheral base address
+ * param chnlNumber        The channel number. In combined mode, this represents
+ *                          the channel pair number
+ * param currentPwmMode    The current PWM mode set during PWM setup
+ * param dutyCyclePercent  New PWM pulse width, value should be between 0 to 100
+ *                          0=inactive signal(0% duty cycle)...
+ *                          100=active signal (100% duty cycle)
+ * return kStatus_Success if the PWM setup was successful,
+ *        kStatus_Error on failure
+ */
+status_t TPM_UpdatePwmDutycycle(TPM_Type *base,
+                                tpm_chnl_t chnlNumber,
+                                tpm_pwm_mode_t currentPwmMode,
+                                uint8_t dutyCyclePercent)
+{
+    uint32_t cnv, mod;
+    uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base);
+    uint8_t chnlId      = (uint8_t)chnlNumber;
+
+    /* Return error if requested chnlNumber is greater than the max allowed */
+    /* Return error if requested dutycycle/chnlNumber is greater than the max allowed */
+    if ((chnlId >= (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) ||
+        (-1 == (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Get the PWM period */
+    mod = base->MOD & counterMax;
+    /* Return error if requested dutycycle is greater than the max allowed */
+    if (((dutyCyclePercent == 100U) && (mod == counterMax)) || (dutyCyclePercent > 100U))
+    {
+        /* MOD can't equal to 0xFFFF otherwise it can't get a 100% duty cycle PWM signal. */
+        return kStatus_OutOfRange;
+    }
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if (currentPwmMode == kTPM_CombinedPwm)
+    {
+        /* Check added for combined mode */
+        /*
+         * $Branch Coverage Justification$
+         * (chnlId >= ((uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U)) not covered. $ref tpm_c_ref_2$.
+         */
+        if ((chnlId >= ((uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U)) ||
+            (1U != (uint8_t)FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)))
+        {
+            /* The instance should support combine mode and the channel number should be the pair number */
+            return kStatus_InvalidArgument;
+        }
+        uint32_t cnvFirstEdge;
+        cnv = (mod * dutyCyclePercent) / 100U;
+        if ((base->CONTROLS[chnlId * 2U].CnV & counterMax) > mod)
+        {
+            cnvFirstEdge = 0U;
+        }
+        else
+        {
+            cnvFirstEdge = base->CONTROLS[chnlId * 2U].CnV & counterMax;
+        }
+
+        if (((cnvFirstEdge + cnv) > mod) || ((cnv == 0U) && (cnvFirstEdge > 0U)))
+        {
+            /* Return error if the following situation occurs :
+             * firstEdgeDelayPercent + dutyCyclePercent > 100
+             * firstEdgeDelayPercent > 0 and dutyCyclePercent == 0
+             */
+            return kStatus_OutOfRange;
+        }
+        if (cnv == mod)
+        {
+            /* 100% duty cycle */
+            cnv = mod + 1U;
+        }
+        else if (cnv == 0U)
+        {
+            /* 0% duty cycle */
+            cnvFirstEdge = mod + 1U;
+        }
+        else
+        {
+            ; /* Intentional empty */
+        }
+
+        do
+        {
+            base->CONTROLS[chnlId * 2U].CnV = cnvFirstEdge;
+            /*
+             * $Branch Coverage Justification$
+             * (cnvFirstEdge != base->CONTROLS[chnlId * 2U].CnV) not covered. $ref tpm_c_ref_1$.
+             */
+        } while (cnvFirstEdge != base->CONTROLS[chnlId * 2U].CnV);
+        do
+        {
+            base->CONTROLS[(chnlId * 2U) + 1U].CnV = cnvFirstEdge + cnv;
+        } while ((cnvFirstEdge + cnv) != base->CONTROLS[(chnlId * 2U) + 1U].CnV);
+    }
+    else
+    {
+#endif
+        if (dutyCyclePercent == 100U)
+        {
+            cnv = mod + 1U;
+        }
+        else
+        {
+            cnv = (mod * dutyCyclePercent) / 100U;
+        }
+        /* Fix ERROR050050 */
+#if (defined(FSL_FEATURE_TPM_HAS_ERRATA_050050) && FSL_FEATURE_TPM_HAS_ERRATA_050050)
+        assert(!(currentPwmMode == kTPM_EdgeAlignedPwm && cnv == 1U &&
+                 (base->SC & TPM_SC_PS_MASK) == kTPM_Prescale_Divide_1));
+#endif
+
+        do
+        {
+            base->CONTROLS[chnlId].CnV = cnv;
+            /*
+             * $Branch Coverage Justification$
+             * (cnv != base->CONTROLS[chnlId].CnV) not covered. $ref tpm_c_ref_1$.
+             */
+        } while (cnv != base->CONTROLS[chnlId].CnV);
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    }
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * brief Update the edge level selection for a channel
+ *
+ * note When the TPM has PWM pause level select feature (FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT = 1), the PWM output
+ *      cannot be turned off by selecting the output level. In this case, must use TPM_DisableChannel API to close
+ * the PWM output.
+ *
+ * param base       TPM peripheral base address
+ * param chnlNumber The channel number
+ * param level      The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
+ *                   See the appropriate SoC reference manual for details about this field.
+ */
+void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level)
+{
+    assert(((uint8_t)chnlNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) &&
+           (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)));
+
+    uint8_t control = TPM_GetChannelContorlBits(base, chnlNumber);
+
+    /* When switching mode, disable channel first */
+    TPM_DisableChannel(base, chnlNumber);
+
+    /* Clear the field and write the new level value */
+    control &= ~(uint8_t)(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+    control |= ((uint8_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Enable channle with new level value */
+    TPM_EnableChannel(base, chnlNumber, control);
+}
+
+/*!
+ * brief Enables capturing an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
+ * the CnV register. The user has to read the CnV register separately to get this value.
+ *
+ * param base        TPM peripheral base address
+ * param chnlNumber  The channel number
+ * param captureMode Specifies which edge to capture
+ */
+void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode)
+{
+    assert(((uint8_t)chnlNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) &&
+           (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)));
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* The TPM's QDCTRL register required to be effective */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base))
+    {
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if (((uint32_t)chnlNumber == 0u) || ((uint32_t)chnlNumber == 1u))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
+    }
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    /* The TPM's COMBINE register required to be effective */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base))
+    {
+        /* Clear the combine bit for chnlNumber */
+        base->COMBINE &= ~((uint32_t)1U << (((uint32_t)chnlNumber / 2U) * TPM_COMBINE_SHIFT));
+    }
+#endif
+    /*Clear CPWMS bit when the input capture mode is selected */
+    base->SC &= ~TPM_SC_CPWMS_MASK;
+    /* When switching mode, disable channel first */
+    TPM_DisableChannel(base, chnlNumber);
+    /* Enable channel with new requested input capture mode */
+    TPM_EnableChannel(base, chnlNumber, (uint8_t)captureMode);
+}
+
+/*!
+ * brief Configures the TPM to generate timed pulses.
+ *
+ * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
+ * output is changed based on what is specified in the compareMode argument.
+ *
+ * param base         TPM peripheral base address
+ * param chnlNumber   The channel number
+ * param compareMode  Action to take on the channel output when the compare condition is met
+ * param compareValue Value to be programmed in the CnV register.
+ */
+void TPM_SetupOutputCompare(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_output_compare_mode_t compareMode,
+                            uint32_t compareValue)
+{
+    assert(((uint8_t)chnlNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) &&
+           (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)));
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* The TPM's QDCTRL register required to be effective */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base))
+    {
+        /* Clear quadrature Decoder mode for channel 0 or 1 */
+        if (((uint32_t)chnlNumber == 0U) || ((uint32_t)chnlNumber == 1U))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
+    }
+#endif
+
+    /*Clear CPWMS bit when the output compare mode is selected */
+    base->SC &= ~TPM_SC_CPWMS_MASK;
+    /* When switching mode, disable channel first  */
+    TPM_DisableChannel(base, chnlNumber);
+    /* Enable channel with new requested compare mode */
+    TPM_EnableChannel(base, chnlNumber, (uint8_t)compareMode);
+
+    /* Setup the compare value */
+    do
+    {
+        base->CONTROLS[chnlNumber].CnV = compareValue;
+        /*
+         * $Branch Coverage Justification$
+         * (compareValue != base->CONTROLS[chnlNumber].CnV) not covered. $ref tpm_c_ref_1$.
+         */
+    } while (compareValue != base->CONTROLS[chnlNumber].CnV);
+}
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+/*!
+ * brief Configures the dual edge capture mode of the TPM.
+ *
+ * This function allows to measure a pulse width of the signal on the input of channel of a
+ * channel pair. The filter function is disabled if the filterVal argument passed is zero.
+ *
+ * param base           TPM peripheral base address
+ * param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
+ * param edgeParam      Sets up the dual edge capture function
+ * param filterValue    Filter value, specify 0 to disable filter.
+ */
+void TPM_SetupDualEdgeCapture(TPM_Type *base,
+                              tpm_chnl_t chnlPairNumber,
+                              const tpm_dual_edge_capture_param_t *edgeParam,
+                              uint32_t filterValue)
+{
+    assert(NULL != edgeParam);
+    assert(((uint8_t)chnlPairNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U) &&
+           (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)));
+    assert(1U == (uint8_t)FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
+
+    uint32_t reg;
+    uint32_t u32flag;
+    uint8_t chnlId = (uint8_t)chnlPairNumber * 2U;
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* The TPM's QDCTRL register required to be effective */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base))
+    {
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if (chnlId == 0u)
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
+    }
+#endif
+
+    /* When switching mode, disable channel first */
+    TPM_DisableChannel(base, (tpm_chnl_t)chnlId);
+    chnlId++;
+    TPM_DisableChannel(base, (tpm_chnl_t)chnlId);
+    chnlId--;
+
+    /* Now, the registers for input mode can be operated. */
+    if (true == edgeParam->enableSwap)
+    {
+        u32flag = TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK;
+        /* Set the combine and swap bits for the channel pair */
+        base->COMBINE |= u32flag << (TPM_COMBINE_SHIFT * (uint32_t)chnlPairNumber);
+
+        /* Input filter setup for channel n+1 input */
+        reg = base->FILTER;
+        reg &= ~((uint32_t)TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlId + 1U)));
+        reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlId + 1U)));
+        base->FILTER = reg;
+    }
+    else
+    {
+        reg = base->COMBINE;
+        /* Clear the swap bit for the channel pair */
+        reg &= ~((uint32_t)TPM_COMBINE_COMSWAP0_MASK << ((uint32_t)chnlPairNumber * TPM_COMBINE_COMSWAP0_SHIFT));
+        u32flag = TPM_COMBINE_COMBINE0_MASK;
+
+        /* Set the combine bit for the channel pair */
+        reg |= u32flag << (TPM_COMBINE_SHIFT * (uint32_t)chnlPairNumber);
+        base->COMBINE = reg;
+
+        /* Input filter setup for channel n input */
+        reg = base->FILTER;
+        reg &= ~((uint32_t)TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlId));
+        reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlId));
+        base->FILTER = reg;
+    }
+
+    /* Setup the edge detection from channel n and n+1*/
+    TPM_EnableChannel(base, (tpm_chnl_t)chnlId, (uint8_t)edgeParam->currChanEdgeMode);
+    chnlId++;
+    TPM_EnableChannel(base, (tpm_chnl_t)chnlId, (uint8_t)edgeParam->nextChanEdgeMode);
+}
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+/*!
+ * brief Configures the parameters and activates the quadrature decode mode.
+ *
+ * param base         TPM peripheral base address
+ * param phaseAParams Phase A configuration parameters
+ * param phaseBParams Phase B configuration parameters
+ * param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void TPM_SetupQuadDecode(TPM_Type *base,
+                         const tpm_phase_params_t *phaseAParams,
+                         const tpm_phase_params_t *phaseBParams,
+                         tpm_quad_decode_mode_t quadMode)
+{
+    assert(NULL != phaseAParams);
+    assert(NULL != phaseBParams);
+    assert(1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base));
+
+    /* Disable channel 0 */
+    TPM_DisableChannel(base, kTPM_Chnl_0);
+
+    uint32_t reg;
+
+    /* Set Phase A filter value */
+    reg = base->FILTER;
+    reg &= ~(TPM_FILTER_CH0FVAL_MASK);
+    reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal);
+    base->FILTER = reg;
+
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    /*
+     * $Branch Coverage Justification$
+     * (1U != FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)) not covered. $ref tpm_c_ref_4$.
+     */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_POL_HAS_EFFECTn(base))
+    {
+        /* Set Phase A polarity */
+        if (kTPM_QuadPhaseInvert == phaseAParams->phasePolarity)
+        {
+            base->POL |= TPM_POL_POL0_MASK;
+        }
+        else
+        {
+            base->POL &= ~TPM_POL_POL0_MASK;
+        }
+    }
+#endif
+
+    /* Disable channel 1 */
+    TPM_DisableChannel(base, kTPM_Chnl_0);
+
+    /* Set Phase B filter value */
+    reg = base->FILTER;
+    reg &= ~(TPM_FILTER_CH1FVAL_MASK);
+    reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal);
+    base->FILTER = reg;
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    /*
+     * $Branch Coverage Justification$
+     * (1U != FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)) not covered. $ref tpm_c_ref_4$.
+     */
+    if (1U == (uint8_t)FSL_FEATURE_TPM_POL_HAS_EFFECTn(base))
+    {
+        /* Set Phase B polarity */
+        if (kTPM_QuadPhaseInvert == phaseBParams->phasePolarity)
+        {
+            base->POL |= TPM_POL_POL1_MASK;
+        }
+        else
+        {
+            base->POL &= ~TPM_POL_POL1_MASK;
+        }
+    }
+#endif
+
+    /* Set Quadrature mode */
+    reg = base->QDCTRL;
+    reg &= ~(TPM_QDCTRL_QUADMODE_MASK);
+    reg |= TPM_QDCTRL_QUADMODE(quadMode);
+    base->QDCTRL = reg;
+
+    /* Enable Quad decode */
+    base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK;
+}
+
+#endif
+
+/*!
+ * brief Enables the selected TPM interrupts.
+ *
+ * param base TPM peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask)
+{
+    uint32_t chnlInterrupts = (mask & 0xFFU);
+    uint8_t chnlNumber      = 0;
+
+    /* Enable the timer overflow interrupt */
+    if ((uint32_t)kTPM_TimeOverflowInterruptEnable == (mask & (uint32_t)kTPM_TimeOverflowInterruptEnable))
+    {
+        base->SC |= TPM_SC_TOIE_MASK;
+    }
+
+    /* Enable the channel interrupts */
+    while (0U != chnlInterrupts)
+    {
+        if (0U != (chnlInterrupts & 0x1u))
+        {
+            base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK;
+        }
+        chnlNumber++;
+        chnlInterrupts = chnlInterrupts >> 1U;
+    }
+}
+
+/*!
+ * brief Disables the selected TPM interrupts.
+ *
+ * param base TPM peripheral base address
+ * param mask The interrupts to disable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask)
+{
+    uint32_t chnlInterrupts = (mask & 0xFFU);
+    uint8_t chnlNumber      = 0;
+
+    /* Disable the timer overflow interrupt */
+    if ((uint32_t)kTPM_TimeOverflowInterruptEnable == (mask & (uint32_t)kTPM_TimeOverflowInterruptEnable))
+    {
+        base->SC &= ~TPM_SC_TOIE_MASK;
+    }
+
+    /* Disable the channel interrupts */
+    while (0U != chnlInterrupts)
+    {
+        if (0U != (chnlInterrupts & 0x1u))
+        {
+            base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK;
+        }
+        chnlNumber++;
+        chnlInterrupts = chnlInterrupts >> 1U;
+    }
+}
+
+/*!
+ * brief Gets the enabled TPM interrupts.
+ *
+ * param base TPM peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::tpm_interrupt_enable_t
+ */
+uint32_t TPM_GetEnabledInterrupts(TPM_Type *base)
+{
+    uint32_t enabledInterrupts = 0;
+    uint32_t u32flag           = 1;
+    int8_t chnlCount           = FSL_FEATURE_TPM_CHANNEL_COUNTn(base);
+
+    /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */
+    assert(chnlCount != -1);
+
+    /* Check if timer overflow interrupt is enabled */
+    if (0U != (base->SC & TPM_SC_TOIE_MASK))
+    {
+        enabledInterrupts |= (uint32_t)kTPM_TimeOverflowInterruptEnable;
+    }
+
+    /* Check if the channel interrupts are enabled */
+    while (chnlCount > 0)
+    {
+        chnlCount--;
+        if (0U != (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK))
+        {
+            enabledInterrupts |= (u32flag << (uint8_t)chnlCount);
+        }
+    }
+
+    return enabledInterrupts;
+}
+
+/*!
+ * brief Register callback.
+ *
+ * If channel or overflow interrupt is enabled by the user, then a callback can be registered
+ * which will be invoked when the interrupt is triggered.
+ *
+ * param base       TPM peripheral base address
+ * param callback   Callback function
+ */
+void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback)
+{
+    uint32_t instance;
+
+    instance = TPM_GetInstance(base);
+
+    /* Create TPM callback instance. */
+    s_tpmCallback[instance] = callback;
+
+    /* Enable IRQ. */
+    (void)EnableIRQ(s_tpmIRQ[instance]);
+}
+
+#if defined(TPM0)
+void TPM0_DriverIRQHandler(void);
+void TPM0_DriverIRQHandler(void)
+{
+    if (NULL != s_tpmCallback[0])
+    {
+        s_tpmCallback[0](TPM0);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(TPM1)
+void TPM1_DriverIRQHandler(void);
+void TPM1_DriverIRQHandler(void)
+{
+    if (NULL != s_tpmCallback[1])
+    {
+        s_tpmCallback[1](TPM1);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.h
new file mode 100644
index 0000000000..b210f9cc56
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_tpm.h
@@ -0,0 +1,949 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_TPM_H_
+#define FSL_TPM_H_
+
+#include "fsl_common.h"
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification tpm_h_ref_1$
+ * Hardware limitations make this code impossible to implement.
+ *
+ */
+
+/*!
+ * @addtogroup tpm
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief TPM driver version 2.3.1. */
+#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*! @} */
+
+/*! @brief Help macro to get the max counter value */
+#define TPM_MAX_COUNTER_VALUE(x) ((1U != (uint8_t)FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x)) ? 0xFFFFU : 0xFFFFFFFFU)
+
+/*!
+ * @brief List of TPM channels.
+ * @note Actual number of available channels is SoC dependent
+ */
+typedef enum _tpm_chnl
+{
+    kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
+    kTPM_Chnl_1,      /*!< TPM channel number 1 */
+    kTPM_Chnl_2,      /*!< TPM channel number 2 */
+    kTPM_Chnl_3,      /*!< TPM channel number 3 */
+    kTPM_Chnl_4,      /*!< TPM channel number 4 */
+    kTPM_Chnl_5,      /*!< TPM channel number 5 */
+    kTPM_Chnl_6,      /*!< TPM channel number 6 */
+    kTPM_Chnl_7       /*!< TPM channel number 7 */
+} tpm_chnl_t;
+
+/*! @brief TPM PWM operation modes */
+typedef enum _tpm_pwm_mode
+{
+    kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
+    kTPM_CenterAlignedPwm,    /*!< Center aligned PWM */
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    kTPM_CombinedPwm /*!< Combined PWM (Edge-aligned, center-aligned, or asymmetrical PWMs can be obtained in combined
+                        mode using different software configurations) */
+#endif
+} tpm_pwm_mode_t;
+
+/*!
+ * @brief TPM PWM output pulse mode: high-true, low-true or no output
+ *
+ * @note When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output
+ *       level. In this case, the channel must be closed to close the PWM output.
+ */
+typedef enum _tpm_pwm_level_select
+{
+#if !(defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT)
+    kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
+    kTPM_LowTrue,          /*!< Low true pulses */
+    kTPM_HighTrue          /*!< High true pulses */
+#else
+    kTPM_HighTrue = 0U, /*!< High true pulses */
+    kTPM_LowTrue        /*!< Low true pulses */
+#endif
+} tpm_pwm_level_select_t;
+
+#if (defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT)
+/*! @brief TPM PWM output when first enabled or paused: set or clear */
+typedef enum _tpm_pwm_pause_level_select
+{
+    kTPM_ClearOnPause = 0U, /*!< Clear Output when counter first enabled or paused. */
+    kTPM_SetOnPause         /*!< Set Output when counter first enabled or paused. */
+} tpm_pwm_pause_level_select_t;
+#endif
+
+/*! @brief List of TPM channel modes and level control bit mask */
+typedef enum _tpm_chnl_control_bit_mask
+{
+    kTPM_ChnlELSnAMask = TPM_CnSC_ELSA_MASK, /*!< Channel ELSA bit mask.*/
+    kTPM_ChnlELSnBMask = TPM_CnSC_ELSB_MASK, /*!< Channel ELSB bit mask.*/
+    kTPM_ChnlMSAMask   = TPM_CnSC_MSA_MASK,  /*!< Channel MSA bit mask.*/
+    kTPM_ChnlMSBMask   = TPM_CnSC_MSB_MASK,  /*!< Channel MSB bit mask.*/
+} tpm_chnl_control_bit_mask_t;
+
+/*! @brief Options to configure a TPM channel's PWM signal */
+typedef struct _tpm_chnl_pwm_signal_param
+{
+    tpm_chnl_t chnlNumber; /*!< TPM channel to configure.
+                                In combined mode (available in some SoC's), this represents the
+                                channel pair number */
+#if (defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT)
+    tpm_pwm_pause_level_select_t pauseLevel; /*!< PWM output level when counter first enabled or paused */
+#endif
+    tpm_pwm_level_select_t level; /*!< PWM output active level select */
+    uint8_t dutyCyclePercent;     /*!< PWM pulse width, value should be between 0 to 100
+                                       0=inactive signal(0% duty cycle)...
+                                       100=always active signal (100% duty cycle)*/
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
+                                        Specifies the delay to the first edge in a PWM period.
+                                        If unsure, leave as 0. Should be specified as percentage
+                                        of the PWM period, (dutyCyclePercent + firstEdgeDelayPercent) value
+                                        should be not greate than 100. */
+    bool enableComplementary;      /*!< Used only in combined PWM mode.
+                                        true: The combined channels output complementary signals;
+                                        false: The combined channels output same signals; */
+#if (defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT)
+    tpm_pwm_pause_level_select_t secPauseLevel; /*!< Used only in combined PWM mode. Define the second channel output
+                                                   level when counter first enabled or paused */
+#endif
+    uint8_t deadTimeValue[2]; /*!< The dead time value for channel n and n+1 in combined complementary PWM mode.
+                               Deadtime insertion is disabled when this value is zero, otherwise deadtime insertion for
+                               channel n/n+1 is configured as (deadTimeValue * 4) clock cycles. deadTimeValue's
+                               available range is 0 ~ 15. */
+#endif
+} tpm_chnl_pwm_signal_param_t;
+
+#if !(defined(FSL_FEATURE_TPM_HAS_NO_CONF) && FSL_FEATURE_TPM_HAS_NO_CONF)
+/*!
+ * @brief Trigger sources available.
+ *
+ * This is used for both internal & external trigger sources (external trigger sources available in certain SoC's)
+ *
+ * @note The actual trigger sources available is SoC-specific.
+ */
+typedef enum _tpm_trigger_select
+{
+    kTPM_Trigger_Select_0 = 0U,
+    kTPM_Trigger_Select_1,
+    kTPM_Trigger_Select_2,
+    kTPM_Trigger_Select_3,
+    kTPM_Trigger_Select_4,
+    kTPM_Trigger_Select_5,
+    kTPM_Trigger_Select_6,
+    kTPM_Trigger_Select_7,
+    kTPM_Trigger_Select_8,
+    kTPM_Trigger_Select_9,
+    kTPM_Trigger_Select_10,
+    kTPM_Trigger_Select_11,
+    kTPM_Trigger_Select_12,
+    kTPM_Trigger_Select_13,
+    kTPM_Trigger_Select_14,
+    kTPM_Trigger_Select_15
+} tpm_trigger_select_t;
+
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+/*!
+ * @brief Trigger source options available
+ *
+ * @note This selection is available only on some SoC's. For SoC's without this selection, the only
+ * trigger source available is internal triger.
+ */
+typedef enum _tpm_trigger_source
+{
+    kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
+    kTPM_TriggerSource_Internal       /*!< Use internal trigger (channel pin input capture) */
+} tpm_trigger_source_t;
+
+/*!
+ * @brief External trigger source polarity
+ *
+ * @note Selects the polarity of the external trigger source.
+ */
+typedef enum _tpm_ext_trigger_polarity
+{
+    kTPM_ExtTrigger_Active_High = 0U, /*!< External trigger input is active high */
+    kTPM_ExtTrigger_Active_Low        /*!< External trigger input is active low */
+} tpm_ext_trigger_polarity_t;
+#endif
+#endif
+
+/*! @brief TPM output compare modes */
+typedef enum _tpm_output_compare_mode
+{
+    kTPM_NoOutputSignal  = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV  */
+    kTPM_ToggleOnMatch   = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
+    kTPM_ClearOnMatch    = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */
+    kTPM_SetOnMatch      = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */
+    kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
+    kTPM_LowPulseOutput  = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT))  /*!< Pulse output low */
+} tpm_output_compare_mode_t;
+
+/*! @brief TPM input capture edge */
+typedef enum _tpm_input_capture_edge
+{
+    kTPM_RisingEdge      = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */
+    kTPM_FallingEdge     = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */
+    kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT)  /*!< Capture on rising or falling edge */
+} tpm_input_capture_edge_t;
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+/*!
+ * @brief TPM dual edge capture parameters
+ *
+ * @note This mode is available only on some SoC's.
+ */
+typedef struct _tpm_dual_edge_capture_param
+{
+    bool enableSwap;                           /*!< true: Use channel n+1 input, channel n input is ignored;
+                                                    false: Use channel n input, channel n+1 input is ignored */
+    tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
+    tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
+} tpm_dual_edge_capture_param_t;
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+/*!
+ * @brief TPM quadrature decode modes
+ *
+ * @note This mode is available only on some SoC's.
+ */
+typedef enum _tpm_quad_decode_mode
+{
+    kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
+    kTPM_QuadCountAndDir       /*!< Count and direction encoding mode */
+} tpm_quad_decode_mode_t;
+
+/*! @brief TPM quadrature phase polarities */
+typedef enum _tpm_phase_polarity
+{
+    kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
+    kTPM_QuadPhaseInvert       /*!< Phase input signal is inverted */
+} tpm_phase_polarity_t;
+
+/*! @brief TPM quadrature decode phase parameters */
+typedef struct _tpm_phase_param
+{
+    uint32_t phaseFilterVal;            /*!< Filter value, filter is disabled when the value is zero */
+    tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
+} tpm_phase_params_t;
+#endif
+
+/*! @brief TPM clock source selection*/
+typedef enum _tpm_clock_source
+{
+    kTPM_SystemClock = 1U, /*!< System clock */
+#if defined(FSL_FEATURE_TPM_HAS_SC_CLKS) && FSL_FEATURE_TPM_HAS_SC_CLKS
+    kTPM_FixedClock, /*!< Fixed frequency clock */
+#endif
+    kTPM_ExternalClock, /*!< External TPM_EXTCLK pin clock */
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+    kTPM_ExternalInputTriggerClock /*!< Selected external input trigger clock */
+#endif
+} tpm_clock_source_t;
+
+/*! @brief TPM prescale value selection for the clock source*/
+typedef enum _tpm_clock_prescale
+{
+    kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
+    kTPM_Prescale_Divide_2,      /*!< Divide by 2 */
+    kTPM_Prescale_Divide_4,      /*!< Divide by 4 */
+    kTPM_Prescale_Divide_8,      /*!< Divide by 8 */
+    kTPM_Prescale_Divide_16,     /*!< Divide by 16 */
+    kTPM_Prescale_Divide_32,     /*!< Divide by 32 */
+    kTPM_Prescale_Divide_64,     /*!< Divide by 64 */
+    kTPM_Prescale_Divide_128     /*!< Divide by 128 */
+} tpm_clock_prescale_t;
+
+/*!
+ * @brief TPM config structure
+ *
+ * This structure holds the configuration settings for the TPM peripheral. To initialize this
+ * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _tpm_config
+{
+    tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */
+#if !(defined(FSL_FEATURE_TPM_HAS_NO_CONF) && FSL_FEATURE_TPM_HAS_NO_CONF)
+    bool useGlobalTimeBase;  /*!< true: The TPM channels use an external global time base (the local counter still use
+                                for generate overflow interrupt and DMA request);
+                                false: All TPM channels use the local counter as their timebase */
+    bool syncGlobalTimeBase; /*!< true: The TPM counter is synchronized to the global time base;
+                                 false: disabled */
+    tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+    tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
+    tpm_ext_trigger_polarity_t
+        extTriggerPolarity; /*!< when using external trigger source, need selects the polarity of it. */
+#endif
+    bool enableDoze;            /*!< true: TPM counter is paused in doze mode;
+                                     false: TPM counter continues in doze mode */
+    bool enableDebugMode;       /*!< true: TPM counter continues in debug mode;
+                                     false: TPM counter is paused in debug mode */
+    bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
+                                     false: TPM counter not reloaded */
+    bool enableStopOnOverflow;  /*!< true: TPM counter stops after overflow;
+                                     false: TPM counter continues running after overflow */
+    bool enableStartOnTrigger;  /*!< true: TPM counter only starts when a trigger is detected;
+                                     false: TPM counter starts immediately */
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+    bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
+                                    false: TPM counter continues running */
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    uint8_t chnlPolarity; /*!< Defines the input/output polarity of the channels in POL register */
+#endif
+#endif
+} tpm_config_t;
+
+/*! @brief List of TPM interrupts */
+typedef enum _tpm_interrupt_enable
+{
+    kTPM_Chnl0InterruptEnable        = (1U << 0), /*!< Channel 0 interrupt.*/
+    kTPM_Chnl1InterruptEnable        = (1U << 1), /*!< Channel 1 interrupt.*/
+    kTPM_Chnl2InterruptEnable        = (1U << 2), /*!< Channel 2 interrupt.*/
+    kTPM_Chnl3InterruptEnable        = (1U << 3), /*!< Channel 3 interrupt.*/
+    kTPM_Chnl4InterruptEnable        = (1U << 4), /*!< Channel 4 interrupt.*/
+    kTPM_Chnl5InterruptEnable        = (1U << 5), /*!< Channel 5 interrupt.*/
+    kTPM_Chnl6InterruptEnable        = (1U << 6), /*!< Channel 6 interrupt.*/
+    kTPM_Chnl7InterruptEnable        = (1U << 7), /*!< Channel 7 interrupt.*/
+    kTPM_TimeOverflowInterruptEnable = (1U << 8)  /*!< Time overflow interrupt.*/
+} tpm_interrupt_enable_t;
+
+/*! @brief List of TPM flags */
+typedef enum _tpm_status_flags
+{
+    kTPM_Chnl0Flag        = (1U << 0), /*!< Channel 0 flag */
+    kTPM_Chnl1Flag        = (1U << 1), /*!< Channel 1 flag */
+    kTPM_Chnl2Flag        = (1U << 2), /*!< Channel 2 flag */
+    kTPM_Chnl3Flag        = (1U << 3), /*!< Channel 3 flag */
+    kTPM_Chnl4Flag        = (1U << 4), /*!< Channel 4 flag */
+    kTPM_Chnl5Flag        = (1U << 5), /*!< Channel 5 flag */
+    kTPM_Chnl6Flag        = (1U << 6), /*!< Channel 6 flag */
+    kTPM_Chnl7Flag        = (1U << 7), /*!< Channel 7 flag */
+    kTPM_TimeOverflowFlag = (1U << 8)  /*!< Time overflow flag */
+} tpm_status_flags_t;
+
+/*!
+ * @brief TPM callback function pointer
+ *
+ * @param base   TPM peripheral base address.
+ */
+typedef void (*tpm_callback_t)(TPM_Type *base);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base TPM peripheral base address
+ * @return The TPM instance
+ */
+uint32_t TPM_GetInstance(TPM_Type *base);
+
+/*!
+ * @brief Ungates the TPM clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the TPM driver.
+ *
+ * @param base   TPM peripheral base address
+ * @param config Pointer to user's TPM config structure.
+ */
+void TPM_Init(TPM_Type *base, const tpm_config_t *config);
+
+/*!
+ * @brief Stops the counter and gates the TPM clock
+ *
+ * @param base TPM peripheral base address
+ */
+void TPM_Deinit(TPM_Type *base);
+
+/*!
+ * @brief  Fill in the TPM config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->prescale = kTPM_Prescale_Divide_1;
+ *     config->useGlobalTimeBase = false;
+ *     config->syncGlobalTimeBase = false;
+ *     config->dozeEnable = false;
+ *     config->dbgMode = false;
+ *     config->enableReloadOnTrigger = false;
+ *     config->enableStopOnOverflow = false;
+ *     config->enableStartOnTrigger = false;
+ *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+ *     config->enablePauseOnTrigger = false;
+ *#endif
+ *     config->triggerSelect = kTPM_Trigger_Select_0;
+ *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+ *     config->triggerSource = kTPM_TriggerSource_External;
+ *     config->extTriggerPolarity = kTPM_ExtTrigger_Active_High;
+ *#endif
+ *#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+ *     config->chnlPolarity = 0U;
+ *#endif
+ * @endcode
+ * @param config Pointer to user's TPM config structure.
+ */
+void TPM_GetDefaultConfig(tpm_config_t *config);
+
+/*!
+ * @brief Calculates the counter clock prescaler.
+ *
+ * This function calculates the values for SC[PS].
+ *
+ * @param base              TPM peripheral base address
+ * @param counterPeriod_Hz  The desired frequency in Hz which corresponding to the time when the counter reaches the mod
+ *                          value
+ * @param srcClock_Hz       TPM counter clock in Hz
+ *
+ * return Calculated clock prescaler value.
+ */
+tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz);
+
+/*! @}*/
+
+/*!
+ * @name Channel mode operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters
+ *
+ * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
+ * function to configure all the TPM channels that will be used to output a PWM signal
+ *
+ * @param base        TPM peripheral base address
+ * @param chnlParams  Array of PWM channel parameters to configure the channel(s)
+ * @param numOfChnls  Number of channels to configure, this should be the size of the array passed in
+ * @param mode        PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
+ * @param pwmFreq_Hz  PWM signal frequency in Hz
+ * @param srcClock_Hz TPM counter clock in Hz
+ *
+ * @return kStatus_Success if the PWM setup was successful,
+ *         kStatus_Error on failure
+ */
+status_t TPM_SetupPwm(TPM_Type *base,
+                      const tpm_chnl_pwm_signal_param_t *chnlParams,
+                      uint8_t numOfChnls,
+                      tpm_pwm_mode_t mode,
+                      uint32_t pwmFreq_Hz,
+                      uint32_t srcClock_Hz);
+
+/*!
+ * @brief Update the duty cycle of an active PWM signal
+ *
+ * @param base              TPM peripheral base address
+ * @param chnlNumber        The channel number. In combined mode, this represents
+ *                          the channel pair number
+ * @param currentPwmMode    The current PWM mode set during PWM setup
+ * @param dutyCyclePercent  New PWM pulse width, value should be between 0 to 100
+ *                          0=inactive signal(0% duty cycle)...
+ *                          100=active signal (100% duty cycle)
+ * @return kStatus_Success if the PWM setup was successful,
+ *         kStatus_Error on failure
+ */
+status_t TPM_UpdatePwmDutycycle(TPM_Type *base,
+                                tpm_chnl_t chnlNumber,
+                                tpm_pwm_mode_t currentPwmMode,
+                                uint8_t dutyCyclePercent);
+
+/*!
+ * @brief Update the edge level selection for a channel
+ *
+ * @note When the TPM has PWM pause level select feature (FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT = 1), the PWM output
+ *      cannot be turned off by selecting the output level. In this case, must use TPM_DisableChannel API to close the
+ *      PWM output.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @param level      The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
+ *                   See the appropriate SoC reference manual for details about this field.
+ */
+void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
+
+/*!
+ * @brief Get the channel control bits value (mode, edge and level bit fileds).
+ *
+ * This function disable the channel by clear all mode and level control bits.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @return The contorl bits value. This is the logical OR of members of the
+ *         enumeration @ref tpm_chnl_control_bit_mask_t.
+ */
+static inline uint8_t TPM_GetChannelContorlBits(TPM_Type *base, tpm_chnl_t chnlNumber)
+{
+    return (uint8_t)(base->CONTROLS[chnlNumber].CnSC &
+                     (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK));
+}
+
+/*!
+ * @brief Dsiable the channel.
+ *
+ * This function disable the channel by clear all mode and level control bits.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ */
+static inline void TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber)
+{
+    do
+    {
+        /* Clear channel MSnB:MSnA and ELSnB:ELSnA to disable its output. */
+        base->CONTROLS[chnlNumber].CnSC &=
+            ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+        /* Wait till mode change to disable channel is acknowledged */
+        /*
+         * $Branch Coverage Justification$
+         * (0U != (base->CONTROLS[chnlNumber].CnSC &
+         *           (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+         * not covered.  $ref tpm_h_ref_1$.
+         */
+
+    } while (0U != (base->CONTROLS[chnlNumber].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)));
+}
+
+/*!
+ * @brief Enable the channel according to mode and level configs.
+ *
+ * This function enable the channel output according to input mode/level config parameters.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @param control     The contorl bits value. This is the logical OR of members of the
+ *                    enumeration @ref tpm_chnl_control_bit_mask_t.
+ */
+static inline void TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control)
+{
+#if defined(FSL_FEATURE_TPM_CnSC_CHF_WRITE_0_CLEAR) && FSL_FEATURE_TPM_CnSC_CHF_WRITE_0_CLEAR
+    control |= TPM_CnSC_CHF_MASK;
+#endif
+
+    do
+    {
+        /* Set channel MSB:MSA and ELSB:ELSA bits. */
+        base->CONTROLS[chnlNumber].CnSC =
+            (base->CONTROLS[chnlNumber].CnSC &
+             ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) |
+            (control & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK));
+        /* Wait till mode change is acknowledged */
+        /*
+         * $Branch Coverage Justification$
+         * ((control & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) !=
+         *    (uint8_t)(base->CONTROLS[chnlNumber].CnSC &
+         *              (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+         * not covered. $ref tpm_h_ref_1$.
+         */
+    } while ((control & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) !=
+             (uint8_t)(base->CONTROLS[chnlNumber].CnSC &
+                       (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)));
+}
+
+/*!
+ * @brief Enables capturing an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
+ * the CnV register. The user has to read the CnV register separately to get this value.
+ *
+ * @param base        TPM peripheral base address
+ * @param chnlNumber  The channel number
+ * @param captureMode Specifies which edge to capture
+ */
+void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
+
+/*!
+ * @brief Configures the TPM to generate timed pulses.
+ *
+ * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
+ * output is changed based on what is specified in the compareMode argument.
+ *
+ * @param base         TPM peripheral base address
+ * @param chnlNumber   The channel number
+ * @param compareMode  Action to take on the channel output when the compare condition is met
+ * @param compareValue Value to be programmed in the CnV register.
+ */
+void TPM_SetupOutputCompare(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_output_compare_mode_t compareMode,
+                            uint32_t compareValue);
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+/*!
+ * @brief Configures the dual edge capture mode of the TPM.
+ *
+ * This function allows to measure a pulse width of the signal on the input of channel of a
+ * channel pair. The filter function is disabled if the filterVal argument passed is zero.
+ *
+ * @param base           TPM peripheral base address
+ * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
+ * @param edgeParam      Sets up the dual edge capture function
+ * @param filterValue    Filter value, specify 0 to disable filter.
+ */
+void TPM_SetupDualEdgeCapture(TPM_Type *base,
+                              tpm_chnl_t chnlPairNumber,
+                              const tpm_dual_edge_capture_param_t *edgeParam,
+                              uint32_t filterValue);
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+/*!
+ * @brief Configures the parameters and activates the quadrature decode mode.
+ *
+ * @param base         TPM peripheral base address
+ * @param phaseAParams Phase A configuration parameters
+ * @param phaseBParams Phase B configuration parameters
+ * @param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void TPM_SetupQuadDecode(TPM_Type *base,
+                         const tpm_phase_params_t *phaseAParams,
+                         const tpm_phase_params_t *phaseBParams,
+                         tpm_quad_decode_mode_t quadMode);
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+/*!
+ * @brief Set the input and output polarity of each of the channels.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @param enable     true: Set the channel polarity to active high;
+ *                   false: Set the channel polarity to active low;
+ */
+static inline void TPM_SetChannelPolarity(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)
+{
+    assert(1U == (uint8_t)FSL_FEATURE_TPM_POL_HAS_EFFECTn(base));
+    if (enable)
+    {
+        base->POL &= ~((uint32_t)TPM_POL_POL0_MASK << (uint8_t)chnlNumber);
+    }
+    else
+    {
+        base->POL |= (uint32_t)TPM_POL_POL0_MASK << (uint8_t)chnlNumber;
+    }
+}
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_TRIG) && FSL_FEATURE_TPM_HAS_TRIG
+/*!
+ * @brief Enable external trigger input to be used by channel.
+ *
+ * In input capture mode, configures the trigger input that is used by the channel to capture the
+ * counter value. In output compare or PWM mode, configures the trigger input used to modulate
+ * the channel output. When modulating the output, the output is forced to the channel initial
+ * value whenever the trigger is not asserted.
+ *
+ * @note No matter how many external trigger sources there are, only input trigger 0 and 1 are used. The even numbered
+ *      channels share the input trigger 0 and the odd numbered channels share the second input trigger 1.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @param enable     true: Configures trigger input 0 or 1 to be used by channel;
+ *                   false: Trigger input has no effect on the channel
+ */
+static inline void TPM_EnableChannelExtTrigger(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)
+{
+    assert(1U == (uint8_t)FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(base));
+    if (enable)
+    {
+        base->TRIG |= (uint32_t)TPM_TRIG_TRIG0_MASK << (uint8_t)chnlNumber;
+    }
+    else
+    {
+        base->TRIG &= ~((uint32_t)TPM_TRIG_TRIG0_MASK << (uint8_t)chnlNumber);
+    }
+}
+#endif
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the selected TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ * @param mask The interrupts to disable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::tpm_interrupt_enable_t
+ */
+uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
+
+/*!
+ * @brief Register callback.
+ *
+ * If channel or overflow interrupt is enabled by the user, then a callback can be registered
+ * which will be invoked when the interrupt is triggered.
+ *
+ * @param base       TPM peripheral base address
+ * @param callback   Callback function
+ */
+void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+/*!
+ * @brief Gets the TPM channel value
+ *
+ * @note  The TPM channel value contain the captured TPM counter value for the input modes or the match value for the
+ *        output modes.
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @return The channle CnV regisyer value.
+ */
+static inline uint32_t TPM_GetChannelValue(TPM_Type *base, tpm_chnl_t chnlNumber)
+{
+    return base->CONTROLS[chnlNumber].CnV;
+}
+
+/*!
+ * @brief Gets the TPM status flags
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::tpm_status_flags_t
+ */
+static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
+{
+    uint32_t statusFlags = 0;
+
+#if defined(FSL_FEATURE_TPM_HAS_NO_STATUS) && FSL_FEATURE_TPM_HAS_NO_STATUS
+    uint8_t chanlNumber = 0;
+
+    /* Check the timer flag */
+    if (0U != (base->SC & TPM_SC_TOF_MASK))
+    {
+        statusFlags |= (uint32_t)kTPM_TimeOverflowFlag;
+    }
+
+    for (chanlNumber = 0; (int8_t)chanlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base); chanlNumber++)
+    {
+        /* Check the channel flag */
+        if (0U != (base->CONTROLS[chanlNumber].CnSC & TPM_CnSC_CHF_MASK))
+        {
+            statusFlags |= (1UL << chanlNumber);
+        }
+    }
+#else
+    statusFlags = base->STATUS;
+#endif
+
+    return statusFlags;
+}
+
+/*!
+ * @brief Clears the TPM status flags
+ *
+ * @param base TPM peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::tpm_status_flags_t
+ */
+static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
+{
+#if defined(FSL_FEATURE_TPM_HAS_NO_STATUS) && FSL_FEATURE_TPM_HAS_NO_STATUS
+    uint32_t chnlStatusFlags = (mask & 0xFFU);
+    uint8_t chnlNumber       = 0;
+
+    /* Clear the timer overflow flag by writing a 0 to the bit while it is set */
+    if (0U != (mask & (uint32_t)kTPM_TimeOverflowFlag))
+    {
+        base->SC &= ~TPM_SC_TOF_MASK;
+    }
+    /* Clear the channel flag */
+    while (0U != chnlStatusFlags)
+    {
+        if (0U != (chnlStatusFlags & 0x1U))
+        {
+            base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHF_MASK;
+        }
+        chnlNumber++;
+        chnlStatusFlags = chnlStatusFlags >> 1U;
+    }
+#else
+    /* Clear the status flags */
+    base->STATUS = mask;
+#endif
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the MOD register.
+ *
+ * @note
+ * 1. This API allows the user to use the TPM module as a timer. Do not mix usage
+ *    of this API with TPM's PWM setup API's.
+ * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base TPM peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)
+{
+    if (1U != (uint8_t)FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(base))
+    {
+        assert(ticks <= 0xFFFFU);
+    }
+    base->MOD = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)
+{
+    return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT);
+}
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the TPM counter.
+ *
+ * @param base        TPM peripheral base address
+ * @param clockSource TPM clock source; once clock source is set the counter will start running
+ */
+static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
+{
+    uint32_t reg = base->SC;
+#if defined(FSL_FEATURE_TPM_HAS_SC_CLKS) && FSL_FEATURE_TPM_HAS_SC_CLKS
+    reg &= ~(TPM_SC_CLKS_MASK);
+    reg |= TPM_SC_CLKS(clockSource);
+#else
+    reg &= ~(TPM_SC_CMOD_MASK);
+    reg |= TPM_SC_CMOD(clockSource);
+#endif
+    base->SC = reg;
+}
+
+/*!
+ * @brief Stops the TPM counter.
+ *
+ * @param base TPM peripheral base address
+ */
+static inline void TPM_StopTimer(TPM_Type *base)
+{
+#if defined(FSL_FEATURE_TPM_HAS_SC_CLKS) && FSL_FEATURE_TPM_HAS_SC_CLKS
+    /* Set clock source to none to disable counter */
+    base->SC &= ~(TPM_SC_CLKS_MASK);
+
+    /* Wait till this reads as zero acknowledging the counter is disabled */
+    while (0U != (base->SC & TPM_SC_CLKS_MASK))
+    {
+    }
+#else
+    /* Set clock source to none to disable counter */
+    base->SC &= ~(TPM_SC_CMOD_MASK);
+
+    /* Wait till this reads as zero acknowledging the counter is disabled */
+    while (0U != (base->SC & TPM_SC_CMOD_MASK))
+    {
+    }
+#endif
+}
+
+/*! @}*/
+
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
+/*!
+ * @brief Performs a software reset on the TPM module.
+ *
+ * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.
+ *
+ * @note TPM software reset is available on certain SoC's only
+ *
+ * @param base TPM peripheral base address
+ */
+static inline void TPM_Reset(TPM_Type *base)
+{
+    base->GLOBAL |= TPM_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
+}
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_TPM_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.c
new file mode 100644
index 0000000000..a98e20bf38
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.c
@@ -0,0 +1,1946 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart"
+#endif
+
+/* UART transfer state. */
+enum
+{
+    kUART_TxIdle,         /* TX idle. */
+    kUART_TxBusy,         /* TX busy. */
+    kUART_RxIdle,         /* RX idle. */
+    kUART_RxBusy,         /* RX busy. */
+    kUART_RxFramingError, /* Rx framing error */
+    kUART_RxParityError   /* Rx parity error */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @param handle UART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UART handle. */
+#if (defined(UART5))
+#define UART_HANDLE_ARRAY_SIZE 6
+#else /* UART5 */
+#if (defined(UART4))
+#define UART_HANDLE_ARRAY_SIZE 5
+#else /* UART4 */
+#if (defined(UART3))
+#define UART_HANDLE_ARRAY_SIZE 4
+#else /* UART3 */
+#if (defined(UART2))
+#define UART_HANDLE_ARRAY_SIZE 3
+#else /* UART2 */
+#if (defined(UART1))
+#define UART_HANDLE_ARRAY_SIZE 2
+#else /* UART1 */
+#if (defined(UART0))
+#define UART_HANDLE_ARRAY_SIZE 1
+#else /* UART0 */
+#error No UART instance.
+#endif /* UART 0 */
+#endif /* UART 1 */
+#endif /* UART 2 */
+#endif /* UART 3 */
+#endif /* UART 4 */
+#endif /* UART 5 */
+void *s_uartHandle[UART_HANDLE_ARRAY_SIZE];
+/* Array of UART peripheral base address. */
+static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
+
+/* Array of UART IRQ number. */
+const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of UART clock name. */
+static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* UART ISR for transactional APIs. */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+uart_isr_t s_uartIsr = (uart_isr_t)DefaultISR;
+#else
+uart_isr_t s_uartIsr;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Get the UART instance from peripheral base address.
+ *
+ * param base UART peripheral base address.
+ * return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base)
+{
+    uint32_t instance;
+    uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < uartArrayCount; instance++)
+    {
+        if (s_uartBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < uartArrayCount);
+
+    return instance;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle UART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    size_t size;
+    uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+    uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+    if (rxRingBufferTail > rxRingBufferHead)
+    {
+        size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+    }
+    else
+    {
+        size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+    }
+
+    return size;
+}
+
+static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    bool full;
+
+    if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+
+    return full;
+}
+
+/*!
+ * brief Initializes a UART instance with a user configuration structure and peripheral clock.
+ *
+ * This function configures the UART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
+ * The example below shows how to use this API to configure UART.
+ * code
+ *  uart_config_t uartConfig;
+ *  uartConfig.baudRate_Bps = 115200U;
+ *  uartConfig.parityMode = kUART_ParityDisabled;
+ *  uartConfig.stopBitCount = kUART_OneStopBit;
+ *  uartConfig.txFifoWatermark = 0;
+ *  uartConfig.rxFifoWatermark = 1;
+ *  UART_Init(UART1, &uartConfig, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param config Pointer to the user-defined configuration structure.
+ * param srcClock_Hz UART clock source frequency in HZ.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Status UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config != NULL);
+    assert(config->baudRate_Bps != 0U);
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    assert((uint8_t)FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
+    assert((uint8_t)FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
+#endif
+
+    uint32_t sbr      = 0U;
+    uint8_t temp      = 0U;
+    uint32_t baudDiff = 0U;
+
+    /* Calculate the baud rate modulo divisor, sbr*/
+    sbr = srcClock_Hz / (config->baudRate_Bps * 16U);
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0U)
+    {
+        sbr = 1U;
+    }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* Determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    uint32_t tempBaud = 0U;
+
+    uint32_t brfa = (2U * srcClock_Hz / (config->baudRate_Bps)) - 32U * sbr;
+
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = srcClock_Hz * 2U / (sbr * 32U + brfa);
+    baudDiff =
+        (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
+
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16U)) - config->baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16U * ((uint32_t)sbr + 1U)))))
+    {
+        baudDiff = config->baudRate_Bps - (srcClock_Hz / (16U * ((uint32_t)sbr + 1U)));
+        sbr++;
+    }
+#endif
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff > ((config->baudRate_Bps / 100U) * 3U))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable uart clock */
+    CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable UART TX RX before setting. */
+    base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK);
+
+    /* Write the sbr value to the BDH and BDL registers*/
+    base->BDH = (base->BDH & ~(uint8_t)UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+    base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* Write the brfa value to the register*/
+    base->C4 = (base->C4 & ~(uint8_t)UART_C4_BRFA_MASK) | ((uint8_t)brfa & UART_C4_BRFA_MASK);
+#endif
+
+    /* Set bit count/parity mode/idle type. */
+    temp = base->C1 &
+           ~((uint8_t)UART_C1_PE_MASK | (uint8_t)UART_C1_PT_MASK | (uint8_t)UART_C1_M_MASK | (uint8_t)UART_C1_ILT_MASK);
+
+    temp |= UART_C1_ILT(config->idleType);
+
+    if (kUART_ParityDisabled != config->parityMode)
+    {
+        temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode);
+    }
+
+    base->C1 = temp;
+
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    /* Set stop bit per char */
+    base->BDH = (base->BDH & ~(uint8_t)UART_BDH_SBNS_MASK) | (uint8_t)UART_BDH_SBNS((uint8_t)config->stopBitCount);
+#endif
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    /* Set tx/rx FIFO watermark
+       Note:
+       Take care of the RX FIFO, RX interrupt request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       RX interrupt because the water mark is 2.
+     */
+    base->TWFIFO = config->txFifoWatermark;
+    base->RWFIFO = config->rxFifoWatermark;
+
+    /* Enable tx/rx FIFO */
+    base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK);
+
+    /* Flush FIFO */
+    base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+    if (config->enableRxRTS)
+    {
+        /* Enable receiver RTS(request-to-send) function. */
+        base->MODEM |= UART_MODEM_RXRTSE_MASK;
+    }
+    if (config->enableTxCTS)
+    {
+        /* Enable transmitter CTS(clear-to-send) function. */
+        base->MODEM |= UART_MODEM_TXCTSE_MASK;
+    }
+#endif
+
+    /* Enable TX/RX base on configure structure. */
+    temp = base->C2;
+
+    if (config->enableTx)
+    {
+        temp |= UART_C2_TE_MASK;
+    }
+
+    if (config->enableRx)
+    {
+        temp |= UART_C2_RE_MASK;
+    }
+
+    base->C2 = temp;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base)
+{
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    /* Wait tx FIFO send out*/
+    while (0U != base->TCFIFO)
+    {
+    }
+#endif
+    /* Wait last char shoft out */
+    while (0U == (base->S1 & UART_S1_TC_MASK))
+    {
+    }
+
+    /* Disable the module. */
+    base->C2 = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable uart clock */
+    CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value. The default
+ * values are as follows.
+ *   uartConfig->baudRate_Bps = 115200U;
+ *   uartConfig->bitCountPerChar = kUART_8BitsPerChar;
+ *   uartConfig->parityMode = kUART_ParityDisabled;
+ *   uartConfig->stopBitCount = kUART_OneStopBit;
+ *   uartConfig->txFifoWatermark = 0;
+ *   uartConfig->rxFifoWatermark = 1;
+ *   uartConfig->idleType = kUART_IdleTypeStartBit;
+ *   uartConfig->enableTx = false;
+ *   uartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config)
+{
+    assert(config != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->baudRate_Bps = 115200U;
+    config->parityMode   = kUART_ParityDisabled;
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    config->stopBitCount = kUART_OneStopBit;
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    config->txFifoWatermark = 0;
+    config->rxFifoWatermark = 1;
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+    config->enableRxRTS = false;
+    config->enableTxCTS = false;
+#endif
+    config->idleType = kUART_IdleTypeStartBit;
+    config->enableTx = false;
+    config->enableRx = false;
+}
+
+/*!
+ * brief Sets the UART instance baud rate.
+ *
+ * This function configures the UART module baud rate. This function is used to update
+ * the UART module baud rate after the UART module is initialized by the UART_Init.
+ * code
+ *  UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param baudRate_Bps UART baudrate to be set.
+ * param srcClock_Hz UART clock source frequency in Hz.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    assert(baudRate_Bps != 0U);
+
+    uint32_t sbr      = 0;
+    uint32_t baudDiff = 0;
+    uint8_t oldCtrl;
+
+    /* Calculate the baud rate modulo divisor, sbr*/
+    sbr = srcClock_Hz / (baudRate_Bps * 16U);
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0U)
+    {
+        sbr = 1U;
+    }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* Determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    uint32_t tempBaud = 0U;
+
+    uint32_t brfa = (2U * srcClock_Hz / (baudRate_Bps)) - 32U * sbr;
+
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = (srcClock_Hz * 2U / ((sbr * 32U + brfa)));
+    baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16U)) - baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16U * (sbr + 1U)))))
+    {
+        baudDiff = baudRate_Bps - (srcClock_Hz / (16U * (sbr + 1U)));
+        sbr++;
+    }
+#endif
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff < ((baudRate_Bps / 100U) * 3U))
+    {
+        /* Store C2 before disable Tx and Rx */
+        oldCtrl = base->C2;
+
+        /* Disable UART TX RX before setting. */
+        base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK);
+
+        /* Write the sbr value to the BDH and BDL registers*/
+        base->BDH = (base->BDH & ~(uint8_t)UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+        base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+        /* Write the brfa value to the register*/
+        base->C4 = (base->C4 & ~(uint8_t)UART_C4_BRFA_MASK) | ((uint8_t)brfa & (uint8_t)UART_C4_BRFA_MASK);
+#endif
+        /* Restore C2. */
+        base->C2 = oldCtrl;
+
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
+}
+
+/*!
+ * brief Enable 9-bit data mode for UART.
+ *
+ * This function set the 9-bit mode for UART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base UART peripheral base address.
+ * param enable true to enable, flase to disable.
+ */
+void UART_Enable9bitMode(UART_Type *base, bool enable)
+{
+    assert(base != NULL);
+
+    uint8_t temp = 0U;
+
+    if (enable)
+    {
+        /* Set UART_C1_M for 9-bit mode, clear UART_C1_PT and UART_C1_PE to disable parity. */
+        temp = base->C1 & ~((uint8_t)UART_C1_PE_MASK | (uint8_t)UART_C1_PT_MASK | (uint8_t)UART_C1_M_MASK);
+        temp |= (uint8_t)UART_C1_M_MASK;
+        base->C1 = temp;
+    }
+    else
+    {
+        /* Clear UART_C1_M. */
+        base->C1 &= ~(uint8_t)UART_C1_M_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_UART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base UART peripheral base address.
+ * param address UART slave address.
+ */
+void UART_SendAddress(UART_Type *base, uint8_t address)
+{
+    assert(base != NULL);
+
+    /* Set address mark. */
+    UART_Set9thTransmitBit(base);
+    /* Send address. */
+    UART_WriteByte(base, address);
+    /* Clear address mark for following data transfer. */
+    UART_Clear9thTransmitBit(base);
+}
+#endif
+
+/*!
+ * brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See ref _uart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
+ * code
+ *     UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
+{
+    mask &= (uint32_t)kUART_AllInterruptsEnable;
+
+    /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
+     */
+    base->BDH |= (uint8_t)mask;
+    base->C2 |= (uint8_t)(mask >> 8);
+    base->C3 |= (uint8_t)(mask >> 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    base->CFIFO |= (uint8_t)(mask >> 24);
+#endif
+}
+
+/*!
+ * brief Disables the UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See ref _uart_interrupt_enable.
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
+ * code
+ *     UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param mask The interrupts to disable. Logical OR of ref _uart_interrupt_enable.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
+{
+    mask &= (uint32_t)kUART_AllInterruptsEnable;
+
+    /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
+     */
+    base->BDH &= ~(uint8_t)mask;
+    base->C2 &= ~(uint8_t)(mask >> 8);
+    base->C3 &= ~(uint8_t)(mask >> 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    base->CFIFO &= ~(uint8_t)(mask >> 24);
+#endif
+}
+
+/*!
+ * brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators ref _uart_interrupt_enable. To check
+ * a specific interrupts enable status, compare the return value with enumerators
+ * in ref _uart_interrupt_enable.
+ * For example, to check whether TX empty interrupt is enabled, do the following.
+ * code
+ *     uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
+ *
+ *     if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * return UART interrupt flags which are logical OR of the enumerators in ref _uart_interrupt_enable.
+ */
+uint32_t UART_GetEnabledInterrupts(UART_Type *base)
+{
+    uint32_t temp;
+
+    temp = (uint32_t)base->BDH;
+    temp |= ((uint32_t)(base->C2) << 8);
+    temp |= ((uint32_t)(base->C3) << 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    temp |= ((uint32_t)(base->CFIFO) << 24);
+#endif
+
+    return temp & (uint32_t)kUART_AllInterruptsEnable;
+}
+
+/*!
+ * brief Gets UART status flags.
+ *
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators ref _uart_flags. To check a specific status,
+ * compare the return value with enumerators in ref _uart_flags.
+ * For example, to check whether the TX is empty, do the following.
+ * code
+ *     if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * return UART status flags which are ORed by the enumerators in the _uart_flags.
+ */
+uint32_t UART_GetStatusFlags(UART_Type *base)
+{
+    uint32_t status_flag;
+
+    status_flag = (uint32_t)base->S1;
+    status_flag |= ((uint32_t)(base->S2) << 8);
+
+#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    status_flag |= ((uint32_t)(base->ED) << 16);
+#endif
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    status_flag |= ((uint32_t)(base->SFIFO) << 24);
+#endif
+
+    return status_flag;
+}
+
+/*!
+ * brief Clears status flags with the provided mask.
+ *
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
+ * can't be cleared by this function.
+ * These flags can only be cleared or set by hardware.
+ *    kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
+ *    kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
+ *    kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
+ * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
+ *
+ * param base UART peripheral base address.
+ * param mask The status flags to be cleared; it is logical OR value of ref _uart_flags.
+ * retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * retval kStatus_Success Status in the mask is cleared.
+ */
+status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask)
+{
+    uint8_t reg = base->S2;
+    status_t status;
+
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+    reg &= ~((uint8_t)UART_S2_RXEDGIF_MASK | (uint8_t)UART_S2_LBKDIF_MASK);
+#else
+    reg &= ~(uint8_t)UART_S2_RXEDGIF_MASK;
+#endif
+
+    base->S2 = reg | (uint8_t)(mask >> 8);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    base->SFIFO = (uint8_t)(mask >> 24);
+#endif
+
+    if ((mask & ((uint32_t)kUART_IdleLineFlag | (uint32_t)kUART_NoiseErrorFlag | (uint32_t)kUART_FramingErrorFlag |
+                 (uint32_t)kUART_ParityErrorFlag | (uint32_t)kUART_RxOverrunFlag)) != 0u)
+    {
+        /* Read base->S1 and base->D to clear the flags. */
+        (void)base->S1;
+        (void)base->D;
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Read base->D may cause receiver underflow when there are no valid data.
+           Clear receiver underflow flag */
+        base->SFIFO = UART_SFIFO_RXUF_MASK;
+        /* Flush FIFO data. Otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+    }
+
+    /* If some flags still pending. */
+    if ((mask & UART_GetStatusFlags(base)) != 0U)
+    {
+        /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag,
+        kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag,
+        kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */
+        status = kStatus_UART_FlagCannotClearManually;
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_UART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)
+{
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+    while (0U != length--)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->S1 & UART_S1_TDRE_MASK)) && (0U != --waitTimes))
+#else
+        while (0U == (base->S1 & UART_S1_TDRE_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            return kStatus_LPUART_Timeout;
+        }
+#endif
+        base->D = *(data++);
+    }
+
+    /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->S1 & UART_S1_TC_MASK)) && (0U != --waitTimes))
+#else
+    while (0U == (base->S1 & UART_S1_TC_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (waitTimes == 0U)
+    {
+        return kStatus_LPUART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(data != NULL);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->D = data[i];
+    }
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the TX register.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * retval kStatus_UART_ParityError A parity error occurred while receiving data.
+ * retval kStatus_UART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data != NULL);
+
+    status_t status = kStatus_Success;
+    uint32_t statusFlag;
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (length-- != 0U)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        while (base->RCFIFO == 0U)
+#else
+        while ((base->S1 & UART_S1_RDRF_MASK) == 0U)
+#endif
+        {
+#if UART_RETRY_TIMES
+            if (0U == --waitTimes)
+            {
+                status = kStatus_LPUART_Timeout;
+                break;
+            }
+#endif
+            statusFlag = UART_GetStatusFlags(base);
+
+            if (0U != (statusFlag & (uint32_t)kUART_RxOverrunFlag))
+            {
+                status = ((kStatus_Success == UART_ClearStatusFlags(base, (uint32_t)kUART_RxOverrunFlag)) ?
+                              (status_t)(kStatus_UART_RxHardwareOverrun) :
+                              (status_t)(kStatus_UART_FlagCannotClearManually));
+                /* If the OR bit is set all the other error flags are prevented from setting,
+                   no need to check other status flags. */
+                break;
+            }
+
+            if (0U != (statusFlag & (uint32_t)kUART_ParityErrorFlag))
+            {
+                status = ((kStatus_Success == UART_ClearStatusFlags(base, (uint32_t)kUART_ParityErrorFlag)) ?
+                              (status_t)(kStatus_UART_ParityError) :
+                              (status_t)(kStatus_UART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kUART_FramingErrorFlag))
+            {
+                status = ((kStatus_Success == UART_ClearStatusFlags(base, (uint32_t)kUART_FramingErrorFlag)) ?
+                              (status_t)(kStatus_UART_FramingError) :
+                              (status_t)(kStatus_UART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kUART_NoiseErrorFlag))
+            {
+                status = ((kStatus_Success == UART_ClearStatusFlags(base, (uint32_t)kUART_NoiseErrorFlag)) ?
+                              (status_t)(kStatus_UART_NoiseError) :
+                              (status_t)(kStatus_UART_FlagCannotClearManually));
+            }
+            if (kStatus_Success != status)
+            {
+                break;
+            }
+        }
+        if (kStatus_Success == status)
+        {
+            *(data++) = base->D;
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data != NULL);
+
+    size_t i;
+
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        data[i] = base->D;
+    }
+}
+
+/*!
+ * brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+                               uart_handle_t *handle,
+                               uart_transfer_callback_t callback,
+                               void *userData)
+{
+    assert(handle != NULL);
+
+    uint32_t instance;
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kUART_RxIdle;
+    handle->txState = (uint8_t)kUART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Get instance from peripheral base address. */
+    instance = UART_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_uartHandle[instance] = handle;
+
+    s_uartIsr = UART_TransferHandleIRQ;
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(s_uartIRQ[instance]);
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize Size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    assert(handle != NULL);
+    assert(ringBuffer != NULL);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer     = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+
+    /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
+    uint32_t irqMask = DisableGlobalIRQ();
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    base->C2 |= (uint8_t)UART_C2_RIE_MASK;
+    base->C3 |= ((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+    /* Enable parity error interrupt when parity mode is enable*/
+    if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+    {
+        base->C3 |= (uint8_t)UART_C3_PEIE_MASK;
+    }
+    EnableGlobalIRQ(irqMask);
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    if (handle->rxState == (uint8_t)kUART_RxIdle)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        base->C2 &= ~(uint8_t)UART_C2_RIE_MASK;
+        base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+        {
+            base->C3 &= ~(uint8_t)UART_C3_PEIE_MASK;
+        }
+        EnableGlobalIRQ(irqMask);
+    }
+
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the ref kStatus_UART_TxIdle as status parameter.
+ *
+ * note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure. See  #uart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->dataSize != 0U);
+    assert(xfer->txData != NULL);
+
+    status_t status;
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kUART_TxBusy == handle->txState)
+    {
+        status = kStatus_UART_TxBusy;
+    }
+    else
+    {
+        handle->txData        = xfer->txData;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = (uint8_t)kUART_TxBusy;
+
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        /* Enable transmitter interrupt. */
+        base->C2 |= (uint8_t)UART_C2_TIE_MASK;
+        EnableGlobalIRQ(irqMask);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
+    uint32_t irqMask = DisableGlobalIRQ();
+    base->C2 &= ~((uint8_t)UART_C2_TIE_MASK | (uint8_t)UART_C2_TCIE_MASK);
+    EnableGlobalIRQ(irqMask);
+
+    handle->txDataSize = 0;
+    handle->txState    = (uint8_t)kUART_TxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes sent out to bus.
+ *
+ * This function gets the number of bytes sent out to bus by using the interrupt method.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument The parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    *count = handle->txDataSizeAll - handle->txDataSize - base->TCFIFO;
+#else
+    if ((base->S1 & (uint8_t)kUART_TxDataRegEmptyFlag) != 0U)
+    {
+        *count = handle->txDataSizeAll - handle->txDataSize;
+    }
+    else
+    {
+        *count = handle->txDataSizeAll - handle->txDataSize - 1U;
+    }
+#endif /* FSL_FEATURE_UART_HAS_FIFO */
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure, see #uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+                                         uart_handle_t *handle,
+                                         uart_transfer_t *xfer,
+                                         size_t *receivedBytes)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->rxData != NULL);
+    assert(xfer->dataSize != 0U);
+
+    uint32_t i;
+    status_t status;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t irqMask;
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if ((uint8_t)kUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_UART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Disable UART RX IRQ, protect ring buffer. */
+            base->C2 &= ~(uint8_t)UART_C2_RIE_MASK;
+            EnableGlobalIRQ(irqMask);
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
+
+            if (bytesToCopy != 0U)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive != 0U)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->rxData + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = xfer->dataSize;
+                handle->rxState       = (uint8_t)kUART_RxBusy;
+            }
+
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Re-enable UART RX IRQ. */
+            base->C2 |= (uint8_t)UART_C2_RIE_MASK;
+            EnableGlobalIRQ(irqMask);
+
+            /* Call user callback since all data are received. */
+            if (0U == bytesToReceive)
+            {
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData        = xfer->rxData + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = (uint8_t)kUART_RxBusy;
+
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Enable RX/Rx overrun/framing error/idle line interrupt. */
+            base->C2 |= ((uint8_t)UART_C2_RIE_MASK | (uint8_t)UART_C2_ILIE_MASK);
+            base->C3 |= ((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+
+            /* Enable parity error interrupt when parity mode is enable*/
+            if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+            {
+                base->C3 |= (uint8_t)UART_C3_PEIE_MASK;
+            }
+            EnableGlobalIRQ(irqMask);
+        }
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes != NULL)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        uint32_t irqMask = DisableGlobalIRQ();
+        /* Disable RX interrupt. */
+        base->C2 &= ~((uint8_t)UART_C2_RIE_MASK | (uint8_t)UART_C2_ILIE_MASK);
+        base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+        {
+            base->C3 &= ~(uint8_t)UART_C3_PEIE_MASK;
+        }
+        EnableGlobalIRQ(irqMask);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+/*!
+ * @brief Enables or disables the UART Tx FIFO.
+ *
+ * This function enables or disables the UART Tx FIFO.
+ *
+ * param base UART peripheral base address.
+ * param enable true to enable, false to disable.
+ * retval kStatus_Success Successfully turn on or turn off Tx FIFO.
+ * retval kStatus_Fail Fail to turn on or turn off Tx FIFO.
+ */
+status_t UART_EnableTxFIFO(UART_Type *base, bool enable)
+{
+    uint8_t sfifo = 0;
+    uint8_t temp  = 0;
+
+    sfifo = base->SFIFO;
+    temp  = base->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK);
+    /* The Tx FIFO must be empty */
+    if ((sfifo & UART_SFIFO_TXEMPT_MASK) == UART_SFIFO_TXEMPT_MASK)
+    {
+        /* Disable UART TX RX before setting */
+        base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK);
+        /* Flush FIFO */
+        base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+
+        if (enable)
+        {
+            base->PFIFO |= (uint8_t)UART_PFIFO_TXFE_MASK;
+        }
+        else
+        {
+            base->PFIFO &= ~(uint8_t)UART_PFIFO_TXFE_MASK;
+        }
+
+        /* Flush FIFO */
+        base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+        base->C2 |= temp;
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+/*!
+ * @brief Enables or disables the UART Rx FIFO.
+ *
+ * This function enables or disables the UART Rx FIFO.
+ *
+ * param base UART peripheral base address.
+ * param enable true to enable, false to disable.
+ * retval kStatus_Success Successfully turn on or turn off Rx FIFO.
+ * retval kStatus_Fail Fail to turn on or turn off Rx FIFO.
+ */
+status_t UART_EnableRxFIFO(UART_Type *base, bool enable)
+{
+    uint8_t sfifo = 0;
+    uint8_t temp  = 0;
+
+    sfifo = base->SFIFO;
+    temp  = base->C2 & ((uint8_t)UART_C2_RE_MASK | (uint8_t)UART_C2_TE_MASK);
+    /* The Rx FIFO must be empty */
+    if ((sfifo & UART_SFIFO_RXEMPT_MASK) == UART_SFIFO_RXEMPT_MASK)
+    {
+        /* Disable UART TX RX before setting */
+        base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK);
+        /* Flush FIFO */
+        base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+
+        if (enable)
+        {
+            base->PFIFO |= (uint8_t)UART_PFIFO_RXFE_MASK;
+        }
+        else
+        {
+            base->PFIFO &= ~(uint8_t)UART_PFIFO_RXFE_MASK;
+        }
+        /* Flush FIFO */
+        base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+        base->C2 |= temp;
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+#endif /* FSL_FEATURE_UART_HAS_FIFO */
+
+/*!
+ * brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param irqHandle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, void *irqHandle)
+{
+    assert(irqHandle != NULL);
+
+    uint8_t count;
+    uint8_t tempCount;
+    uint32_t status = UART_GetStatusFlags(base);
+    uint8_t tmpdata;
+    uint32_t irqMask;
+    uart_handle_t *handle = (uart_handle_t *)irqHandle;
+
+    /* If RX framing error */
+    if (((uint32_t)kUART_FramingErrorFlag & status) != 0U)
+    {
+        /* Read base->D to clear framing error flag, otherwise the RX does not work. */
+        while ((base->S1 & UART_S1_RDRF_MASK) != 0U)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState    = (uint8_t)kUART_RxFramingError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
+        }
+    }
+
+    /* If RX parity error */
+    if (((uint32_t)kUART_ParityErrorFlag & status) != 0U)
+    {
+        /* Read base->D to clear parity error flag, otherwise the RX does not work. */
+        while ((base->S1 & UART_S1_RDRF_MASK) != 0U)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState    = (uint8_t)kUART_RxParityError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
+        }
+    }
+
+    /* If RX overrun. */
+    if (((uint32_t)kUART_RxOverrunFlag & status) != 0U)
+    {
+        /* Read base->D to clear overrun flag, otherwise the RX does not work. */
+        while ((base->S1 & UART_S1_RDRF_MASK) != 0U)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* If IDLE line was detected. */
+    if ((((uint32_t)kUART_IdleLineFlag & status) != 0U) && ((UART_C2_ILIE_MASK & base->C2) != 0U))
+    {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* If still some data in the FIFO, read out these data to user data buffer. */
+        count = base->RCFIFO;
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        while ((count != 0U) && (handle->rxDataSize != 0U))
+        {
+            tempCount = (uint8_t)MIN(handle->rxDataSize, (uint32_t)count);
+
+            /* Using non block API to read the data from the registers. */
+            UART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData += tempCount;
+            handle->rxDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (0U == handle->rxDataSize)
+            {
+                handle->rxState = (uint8_t)kUART_RxIdle;
+
+                /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+                 * read-modify-wrte. */
+                irqMask = DisableGlobalIRQ();
+                /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */
+                base->C2 &= ~(uint8_t)UART_C2_RIE_MASK;
+                base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+                /* Disable parity error interrupt when parity mode is enabled */
+                if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+                {
+                    base->C3 &= ~(uint8_t)UART_C3_PEIE_MASK;
+                }
+                EnableGlobalIRQ(irqMask);
+
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+#endif
+        /* To clear IDLE, read UART status S1 with IDLE set and then read D.*/
+        while ((UART_S1_IDLE_MASK & base->S1) != 0U)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+        /* If rxDataSize is 0, disable idle line interrupt.*/
+        if (0U == (handle->rxDataSize))
+        {
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            base->C2 &= ~(uint8_t)UART_C2_ILIE_MASK;
+            EnableGlobalIRQ(irqMask);
+        }
+        /* If callback is not NULL and rxDataSize is not 0. */
+        if ((handle->callback != NULL) && (handle->rxDataSize != 0U))
+        {
+            handle->callback(base, handle, kStatus_UART_IdleLineDetected, handle->userData);
+        }
+    }
+    /* Receive data register full */
+    if ((((uint32_t)kUART_RxDataRegFullFlag & status) != 0U) && ((UART_C2_RIE_MASK & base->C2) != 0U))
+    {
+/* Get the size that can be stored into buffer for this interrupt. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        count = base->RCFIFO;
+#else
+        count = 1;
+#endif
+
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        while ((count != 0U) && (handle->rxDataSize != 0U))
+        {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+            tempCount = (uint8_t)MIN(handle->rxDataSize, (uint32_t)count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to read the data from the registers. */
+            UART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData += tempCount;
+            handle->rxDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (0U == handle->rxDataSize)
+            {
+                handle->rxState = (uint8_t)kUART_RxIdle;
+
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+
+        /* If use RX ring buffer, receive data to ring buffer. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            while (0U != count--)
+            {
+                /* If RX ring buffer is full, trigger callback to notify over run. */
+                if (UART_TransferIsRxRingBufferFull(handle))
+                {
+                    if (handle->callback != NULL)
+                    {
+                        handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData);
+                    }
+                }
+
+                /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                if (UART_TransferIsRxRingBufferFull(handle))
+                {
+                    /* Increase handle->rxRingBufferTail to make room for new data. */
+                    if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+
+                /* Read data. */
+                tmpdata                                        = base->D;
+                handle->rxRingBuffer[handle->rxRingBufferHead] = tmpdata;
+
+                /* Increase handle->rxRingBufferHead. */
+                if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferHead = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferHead++;
+                }
+            }
+        }
+
+        else if (0U == handle->rxDataSize)
+        {
+            /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+             * read-modify-wrte. */
+            irqMask = DisableGlobalIRQ();
+            /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */
+            base->C2 &= ~(uint8_t)UART_C2_RIE_MASK;
+            base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+            /* Disable parity error interrupt when parity mode is enabled */
+            if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+            {
+                base->C3 &= ~(uint8_t)UART_C3_PEIE_MASK;
+            }
+            EnableGlobalIRQ(irqMask);
+        }
+        else
+        {
+        }
+    }
+
+    /* If framing error or parity error happened, stop the RX interrupt when use no ring buffer */
+    if (((handle->rxState == (uint8_t)kUART_RxFramingError) || (handle->rxState == (uint8_t)kUART_RxParityError)) &&
+        (NULL == handle->rxRingBuffer))
+    {
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        irqMask = DisableGlobalIRQ();
+        /* Enable RX/Rx overrun/framing error/idle line interrupt. */
+        base->C2 |= ((uint8_t)UART_C2_RIE_MASK | (uint8_t)UART_C2_ILIE_MASK);
+        base->C3 |= ((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK);
+
+        /* Enable parity error interrupt when parity mode is enable*/
+        if (((uint8_t)UART_C1_PE_MASK & base->C1) != 0U)
+        {
+            base->C3 |= (uint8_t)UART_C3_PEIE_MASK;
+        }
+        EnableGlobalIRQ(irqMask);
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((((uint32_t)kUART_TxDataRegEmptyFlag & status) != 0U) && ((base->C2 & UART_C2_TIE_MASK) != 0U))
+    {
+/* Get the bytes that available at this moment. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        count = (uint8_t)FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO;
+#else
+        count = 1;
+#endif
+
+        while ((count != 0U) && (handle->txDataSize != 0U))
+        {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+            tempCount = (uint8_t)MIN(handle->txDataSize, (uint32_t)count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to write the data to the registers. */
+            UART_WriteNonBlocking(base, handle->txData, tempCount);
+            handle->txData += tempCount;
+            handle->txDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data are written to data register, TX finished. */
+            if (0U == handle->txDataSize)
+            {
+                /* Disable and re-enable the global interrupt to protect the interrupt enable register during
+                 * read-modify-wrte. */
+                irqMask = DisableGlobalIRQ();
+                /* Disable TX register empty interrupt and enable transmission complete interrupt. */
+                base->C2 = (base->C2 & ~(uint8_t)UART_C2_TIE_MASK) | (uint8_t)UART_C2_TCIE_MASK;
+                EnableGlobalIRQ(irqMask);
+            }
+        }
+    }
+
+    /* Transmission complete and the interrupt is enabled. */
+    if ((0U != ((uint32_t)kUART_TransmissionCompleteFlag & status)) && (0U != (base->C2 & UART_C2_TCIE_MASK)))
+    {
+        /* Set txState to idle only when all data has been sent out to bus. */
+        handle->txState = (uint8_t)kUART_TxIdle;
+
+        /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
+         */
+        irqMask = DisableGlobalIRQ();
+        /* Disable transmission complete interrupt. */
+        base->C2 &= ~(uint8_t)UART_C2_TCIE_MASK;
+        EnableGlobalIRQ(irqMask);
+
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param irqHandle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, void *irqHandle)
+{
+    /* To be implemented by User. */
+}
+
+#if defined(FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1_IRQ2_IRQ3) && FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1_IRQ2_IRQ3
+void UART0_UART1_UART2_UART3_DriverIRQHandler(void);
+void UART0_UART1_UART2_UART3_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 0U; instance < 4U; instance++)
+    {
+        if (s_uartHandle[instance] != NULL)
+        {
+            s_uartIsr(s_uartBases[instance], s_uartHandle[instance]);
+        }
+    }
+}
+#else
+#if defined(FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1
+void UART0_UART1_DriverIRQHandler(void);
+void UART0_UART1_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 0U; instance < 2U; instance++)
+    {
+        if (s_uartHandle[instance] != NULL)
+        {
+            s_uartIsr(s_uartBases[instance], s_uartHandle[instance]);
+        }
+    }
+}
+#else /* FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1 */
+#if defined(UART0)
+#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \
+     ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0)))
+void UART0_DriverIRQHandler(void);
+void UART0_DriverIRQHandler(void)
+{
+    s_uartIsr(UART0, s_uartHandle[0]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART0_RX_TX_DriverIRQHandler(void);
+void UART0_RX_TX_DriverIRQHandler(void)
+{
+    UART0_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
+#endif /* UART0 */
+
+#if defined(UART1)
+void UART1_DriverIRQHandler(void);
+void UART1_DriverIRQHandler(void)
+{
+    s_uartIsr(UART1, s_uartHandle[1]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART1_RX_TX_DriverIRQHandler(void);
+void UART1_RX_TX_DriverIRQHandler(void)
+{
+    UART1_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* UART1 */
+#endif /* FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1 */
+
+#if defined(FSL_FEATURE_UART_HAS_SHARED_IRQ2_IRQ3) && FSL_FEATURE_UART_HAS_SHARED_IRQ2_IRQ3
+void UART2_UART3_DriverIRQHandler(void);
+void UART2_UART3_DriverIRQHandler(void)
+{
+    for (uint32_t instance = 2U; instance < 4U; instance++)
+    {
+        if (s_uartHandle[instance] != NULL)
+        {
+            s_uartIsr(s_uartBases[instance], s_uartHandle[instance]);
+        }
+    }
+}
+#else /* FSL_FEATURE_UART_HAS_SHARED_IRQ2_IRQ3 */
+#if defined(UART2)
+void UART2_DriverIRQHandler(void);
+void UART2_DriverIRQHandler(void)
+{
+    s_uartIsr(UART2, s_uartHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART2_RX_TX_DriverIRQHandler(void);
+void UART2_RX_TX_DriverIRQHandler(void)
+{
+    UART2_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* UART2 */
+
+#if defined(UART3)
+void UART3_DriverIRQHandler(void);
+void UART3_DriverIRQHandler(void)
+{
+    s_uartIsr(UART3, s_uartHandle[3]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART3_RX_TX_DriverIRQHandler(void);
+void UART3_RX_TX_DriverIRQHandler(void)
+{
+    UART3_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif /* UART3 */
+#endif /* FSL_FEATURE_UART_HAS_SHARED_IRQ2_IRQ3 */
+#endif /* FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1_IRQ2_IRQ3 */
+
+#if defined(UART4)
+void UART4_DriverIRQHandler(void);
+void UART4_DriverIRQHandler(void)
+{
+    s_uartIsr(UART4, s_uartHandle[4]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART4_RX_TX_DriverIRQHandler(void);
+void UART4_RX_TX_DriverIRQHandler(void)
+{
+    UART4_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(UART5)
+void UART5_DriverIRQHandler(void);
+void UART5_DriverIRQHandler(void)
+{
+    s_uartIsr(UART5, s_uartHandle[5]);
+    SDK_ISR_EXIT_BARRIER;
+}
+
+void UART5_RX_TX_DriverIRQHandler(void);
+void UART5_RX_TX_DriverIRQHandler(void)
+{
+    UART5_DriverIRQHandler();
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.h
new file mode 100644
index 0000000000..44d5419f6b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart.h
@@ -0,0 +1,979 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_UART_H_
+#define FSL_UART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief UART driver version. */
+#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
+/*! @} */
+
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+#endif
+
+/*! @brief Error codes for the UART driver. */
+enum
+{
+    kStatus_UART_TxBusy              = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */
+    kStatus_UART_RxBusy              = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */
+    kStatus_UART_TxIdle              = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */
+    kStatus_UART_RxIdle              = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */
+    kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large  */
+    kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large  */
+    kStatus_UART_FlagCannotClearManually =
+        MAKE_STATUS(kStatusGroup_UART, 6),                                 /*!< UART flag can't be manually cleared. */
+    kStatus_UART_Error               = MAKE_STATUS(kStatusGroup_UART, 7),  /*!< Error happens on UART. */
+    kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8),  /*!< UART RX software ring buffer overrun. */
+    kStatus_UART_RxHardwareOverrun   = MAKE_STATUS(kStatusGroup_UART, 9),  /*!< UART RX receiver overrun. */
+    kStatus_UART_NoiseError          = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */
+    kStatus_UART_FramingError        = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */
+    kStatus_UART_ParityError         = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */
+    kStatus_UART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */
+    kStatus_UART_IdleLineDetected = MAKE_STATUS(kStatusGroup_UART, 14), /*!< UART IDLE line detected. */
+    kStatus_UART_Timeout          = MAKE_STATUS(kStatusGroup_UART, 15), /*!< UART times out. */
+};
+
+/*! @brief UART parity mode. */
+typedef enum _uart_parity_mode
+{
+    kUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _uart_stop_bit_count
+{
+    kUART_OneStopBit = 0U, /*!< One stop bit */
+    kUART_TwoStopBit = 1U, /*!< Two stop bits */
+} uart_stop_bit_count_t;
+
+/*! @brief UART idle type select. */
+typedef enum _uart_idle_type_select
+{
+    kUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
+    kUART_IdleTypeStopBit  = 1U, /*!< Start counting after a stop bit. */
+} uart_idle_type_select_t;
+
+/*!
+ * @brief UART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the UART interrupt configurations.
+ */
+enum _uart_interrupt_enable
+{
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+    kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */
+#endif
+    kUART_RxActiveEdgeInterruptEnable         = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */
+    kUART_TxDataRegEmptyInterruptEnable       = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */
+    kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */
+    kUART_RxDataRegFullInterruptEnable        = (UART_C2_RIE_MASK << 8),  /*!< Receiver data register full interrupt. */
+    kUART_IdleLineInterruptEnable             = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */
+    kUART_RxOverrunInterruptEnable            = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */
+    kUART_NoiseErrorInterruptEnable           = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */
+    kUART_FramingErrorInterruptEnable         = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */
+    kUART_ParityErrorInterruptEnable          = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    kUART_RxFifoOverflowInterruptEnable  = (UART_CFIFO_RXOFE_MASK << 24), /*!< RX FIFO overflow interrupt. */
+    kUART_TxFifoOverflowInterruptEnable  = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */
+    kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
+#endif
+    kUART_AllInterruptsEnable =
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+        kUART_LinBreakInterruptEnable |
+#endif
+        kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable |
+        kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable |
+        kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable |
+        kUART_ParityErrorInterruptEnable
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        | kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable |
+        kUART_RxFifoUnderflowInterruptEnable
+#endif
+    ,
+};
+
+/*!
+ * @brief UART status flags.
+ *
+ * This provides constants for the UART status flags for use in the UART functions.
+ */
+enum
+{
+    kUART_TxDataRegEmptyFlag       = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */
+    kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK),   /*!< Transmission complete flag. */
+    kUART_RxDataRegFullFlag        = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */
+    kUART_IdleLineFlag             = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */
+    kUART_RxOverrunFlag            = (UART_S1_OR_MASK),   /*!< RX overrun flag. */
+    kUART_NoiseErrorFlag           = (UART_S1_NF_MASK),   /*!< RX takes 3 samples of each received bit.
+                                                               If any of these samples differ, noise flag sets */
+    kUART_FramingErrorFlag = (UART_S1_FE_MASK),           /*!< Frame error flag, sets if logic 0 was detected
+                                                               where stop bit expected */
+    kUART_ParityErrorFlag = (UART_S1_PF_MASK),            /*!< If parity enabled, sets upon parity error detection */
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+    kUART_LinBreakFlag =
+        (UART_S2_LBKDIF_MASK
+         << 8), /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+#endif
+    kUART_RxActiveEdgeFlag =
+        (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,sets when active edge detected */
+    kUART_RxActiveFlag =
+        (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kUART_NoiseErrorInRxDataRegFlag  = (UART_ED_NOISY_MASK << 16),   /*!< Noisy bit, sets if noise detected. */
+    kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Parity bit, sets if parity error detected. */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    kUART_TxFifoEmptyFlag     = (int)(UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */
+    kUART_RxFifoEmptyFlag     = (UART_SFIFO_RXEMPT_MASK << 24),      /*!< RXEMPT bit, sets if RX buffer is empty */
+    kUART_TxFifoOverflowFlag  = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */
+    kUART_RxFifoOverflowFlag  = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */
+    kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */
+#endif
+};
+
+/*! @brief UART configuration structure. */
+typedef struct _uart_config
+{
+    uint32_t baudRate_Bps;         /*!< UART baud rate  */
+    uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+    uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+    bool enableRxRTS; /*!< RX RTS enable */
+    bool enableTxCTS; /*!< TX CTS enable */
+#endif
+    uart_idle_type_select_t idleType; /*!< IDLE type select. */
+    bool enableTx;                    /*!< Enable TX */
+    bool enableRx;                    /*!< Enable RX */
+} uart_config_t;
+
+/*! @brief UART transfer structure. */
+typedef struct _uart_transfer
+{
+    /*
+     * Use separate TX and RX data pointer, because TX data is const data.
+     * The member data is kept for backward compatibility.
+     */
+    union
+    {
+        uint8_t *data;         /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;       /*!< The buffer to receive data. */
+        const uint8_t *txData; /*!< The buffer of data to be sent. */
+    };
+    size_t dataSize; /*!< The byte count to be transfer. */
+} uart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_handle uart_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief UART handle structure. */
+struct _uart_handle
+{
+    const uint8_t *volatile txData; /*!< Address of remaining data to send. */
+    volatile size_t txDataSize;     /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;           /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;       /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize;     /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;           /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    uart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                    /*!< UART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*uart_isr_t)(UART_Type *base, void *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! Pointers to uart handles for each instance. */
+extern void *s_uartHandle[];
+
+/* Array of UART IRQs. */
+extern const IRQn_Type s_uartIRQ[];
+
+/*! Pointer to uart IRQ handler for each instance. */
+extern uart_isr_t s_uartIsr;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Get the UART instance from peripheral base address.
+ *
+ * @param base UART peripheral base address.
+ * @return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with a user configuration structure and peripheral clock.
+ *
+ * This function configures the UART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
+ * The example below shows how to use this API to configure UART.
+ * @code
+ *  uart_config_t uartConfig;
+ *  uartConfig.baudRate_Bps = 115200U;
+ *  uartConfig.parityMode = kUART_ParityDisabled;
+ *  uartConfig.stopBitCount = kUART_OneStopBit;
+ *  uartConfig.txFifoWatermark = 0;
+ *  uartConfig.rxFifoWatermark = 1;
+ *  UART_Init(UART1, &uartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param config Pointer to the user-defined configuration structure.
+ * @param srcClock_Hz UART clock source frequency in HZ.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Status UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value. The default
+ * values are as follows.
+ *   uartConfig->baudRate_Bps = 115200U;
+ *   uartConfig->bitCountPerChar = kUART_8BitsPerChar;
+ *   uartConfig->parityMode = kUART_ParityDisabled;
+ *   uartConfig->stopBitCount = kUART_OneStopBit;
+ *   uartConfig->txFifoWatermark = 0;
+ *   uartConfig->rxFifoWatermark = 1;
+ *   uartConfig->idleType = kUART_IdleTypeStartBit;
+ *   uartConfig->enableTx = false;
+ *   uartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config);
+
+/*!
+ * @brief Sets the UART instance baud rate.
+ *
+ * This function configures the UART module baud rate. This function is used to update
+ * the UART module baud rate after the UART module is initialized by the UART_Init.
+ * @code
+ *  UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param baudRate_Bps UART baudrate to be set.
+ * @param srcClock_Hz UART clock source frequency in Hz.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 9-bit data mode for UART.
+ *
+ * This function set the 9-bit mode for UART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * @param base UART peripheral base address.
+ * @param enable true to enable, flase to disable.
+ */
+void UART_Enable9bitMode(UART_Type *base, bool enable);
+
+#if defined(FSL_FEATURE_UART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+/*!
+ * @brief Set the UART slave address.
+ *
+ * This function configures the address for UART module that works as slave in 9-bit data mode. One or two address
+ * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being
+ * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one
+ * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in
+ * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with
+ * unmatched address.
+ *
+ * @note Any UART instance joined in the multi-slave system can work as slave. The position of the address mark is the
+ * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
+ *
+ * @param base UART peripheral base address.
+ * @param address1 UART slave address 1.
+ * @param address2 UART slave address 2.
+ */
+static inline void UART_SetMatchAddress(UART_Type *base, uint8_t address1, uint8_t address2)
+{
+    /* Configure match address. */
+    base->MA1 = address1;
+    base->MA2 = address2;
+}
+
+/*!
+ * @brief Enable the UART match address feature.
+ *
+ * @param base UART peripheral base address.
+ * @param match1 true to enable match address1, false to disable.
+ * @param match2 true to enable match address2, false to disable.
+ */
+static inline void UART_EnableMatchAddress(UART_Type *base, bool match1, bool match2)
+{
+    /* Configure match address1 enable bit. */
+    if (match1)
+    {
+        base->C4 |= (uint8_t)UART_C4_MAEN1_MASK;
+    }
+    else
+    {
+        base->C4 &= ~(uint8_t)UART_C4_MAEN1_MASK;
+    }
+    /* Configure match address2 enable bit. */
+    if (match2)
+    {
+        base->C4 |= (uint8_t)UART_C4_MAEN2_MASK;
+    }
+    else
+    {
+        base->C4 &= ~(uint8_t)UART_C4_MAEN2_MASK;
+    }
+}
+#endif
+
+/*!
+ * @brief Set UART 9th transmit bit.
+ *
+ * @param base UART peripheral base address.
+ */
+static inline void UART_Set9thTransmitBit(UART_Type *base)
+{
+    base->C3 |= (uint8_t)UART_C3_T8_MASK;
+}
+
+/*!
+ * @brief Clear UART 9th transmit bit.
+ *
+ * @param base UART peripheral base address.
+ */
+static inline void UART_Clear9thTransmitBit(UART_Type *base)
+{
+    base->C3 &= ~(uint8_t)UART_C3_T8_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets UART status flags.
+ *
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators _uart_flags. To check a specific status,
+ * compare the return value with enumerators in _uart_flags.
+ * For example, to check whether the TX is empty, do the following.
+ * @code
+ *     if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @return UART status flags which are ORed by the enumerators in the _uart_flags.
+ */
+uint32_t UART_GetStatusFlags(UART_Type *base);
+
+/*!
+ * @brief Clears status flags with the provided mask.
+ *
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
+ * can't be cleared by this function.
+ * These flags can only be cleared or set by hardware.
+ *    kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
+ *    kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
+ *    kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
+ * @note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
+ *
+ * @param base UART peripheral base address.
+ * @param mask The status flags to be cleared; it is logical OR value of _uart_flags.
+ * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask is cleared.
+ */
+status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
+ * @code
+ *     UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
+ * @code
+ *     UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check
+ * a specific interrupts enable status, compare the return value with enumerators
+ * in @ref _uart_interrupt_enable.
+ * For example, to check whether TX empty interrupt is enabled, do the following.
+ * @code
+ *     uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
+ *
+ *     if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable.
+ */
+uint32_t UART_GetEnabledInterrupts(UART_Type *base);
+
+/*! @} */
+
+#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Gets the UART data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @return UART data register addresses which are used both by the transmitter and the receiver.
+ */
+static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base)
+{
+    return (uint32_t) & (base->D);
+}
+
+/*!
+ * @brief Enables or disables the UART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableTxDMA(UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+        base->C4 |= (uint8_t)UART_C4_TDMAS_MASK;
+#else
+        base->C5 |= (uint8_t)UART_C5_TDMAS_MASK;
+#endif
+        base->C2 |= (uint8_t)UART_C2_TIE_MASK;
+    }
+    else
+    {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+        base->C4 &= ~(uint8_t)UART_C4_TDMAS_MASK;
+#else
+        base->C5 &= ~(uint8_t)UART_C5_TDMAS_MASK;
+#endif
+        base->C2 &= ~(uint8_t)UART_C2_TIE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the UART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableRxDMA(UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+        base->C4 |= (uint8_t)UART_C4_RDMAS_MASK;
+#else
+        base->C5 |= (uint8_t)UART_C5_RDMAS_MASK;
+#endif
+        base->C2 |= (uint8_t)UART_C2_RIE_MASK;
+    }
+    else
+    {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+        base->C4 &= ~(uint8_t)UART_C4_RDMAS_MASK;
+#else
+        base->C5 &= ~(uint8_t)UART_C5_RDMAS_MASK;
+#endif
+        base->C2 &= ~(uint8_t)UART_C2_RIE_MASK;
+    }
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the UART transmitter.
+ *
+ * This function enables or disables the UART transmitter.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableTx(UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C2 |= (uint8_t)UART_C2_TE_MASK;
+    }
+    else
+    {
+        base->C2 &= ~(uint8_t)UART_C2_TE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the UART receiver.
+ *
+ * This function enables or disables the UART receiver.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableRx(UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C2 |= (uint8_t)UART_C2_RE_MASK;
+    }
+    else
+    {
+        base->C2 &= ~(uint8_t)UART_C2_RE_MASK;
+    }
+}
+
+/*!
+ * @brief Writes to the TX register.
+ *
+ * This function writes data to the TX register directly. The upper layer must ensure
+ * that the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void UART_WriteByte(UART_Type *base, uint8_t data)
+{
+    base->D = data;
+}
+
+/*!
+ * @brief Reads the RX register directly.
+ *
+ * This function reads data from the RX register directly. The upper layer must
+ * ensure that the RX register is full or that the TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @return The byte read from UART data register.
+ */
+static inline uint8_t UART_ReadByte(UART_Type *base)
+{
+    return base->D;
+}
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+/*!
+ * @brief Gets the rx FIFO data count.
+ *
+ * @param base UART peripheral base address.
+ * @return rx FIFO data count.
+ */
+static inline uint8_t UART_GetRxFifoCount(UART_Type *base)
+{
+    return (uint8_t)base->RCFIFO;
+}
+
+/*!
+ * @brief Gets the tx FIFO data count.
+ *
+ * @param base UART peripheral base address.
+ * @return tx FIFO data count.
+ */
+static inline uint8_t UART_GetTxFifoCount(UART_Type *base)
+{
+    return (uint8_t)base->TCFIFO;
+}
+#endif /* FSL_FEATURE_UART_HAS_FIFO */
+
+#if defined(FSL_FEATURE_UART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_UART_HAS_ADDRESS_MATCHING
+/*!
+ * @brief Transmit an address frame in 9-bit data mode.
+ *
+ * @param base UART peripheral base address.
+ * @param address UART slave address.
+ */
+void UART_SendAddress(UART_Type *base, uint8_t address);
+#endif
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_UART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the TX register.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * @retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * @retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * @retval kStatus_UART_ParityError A parity error occurred while receiving data.
+ * @retval kStatus_UART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+                               uart_handle_t *handle,
+                               uart_transfer_callback_t callback,
+                               void *userData);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle UART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure. See  #uart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes sent out to bus.
+ *
+ * This function gets the number of bytes sent out to bus by using the interrupt method.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument The parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure, see #uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+                                         uart_handle_t *handle,
+                                         uart_transfer_t *xfer,
+                                         size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+/*!
+ * @brief Enables or disables the UART Tx FIFO.
+ *
+ * This function enables or disables the UART Tx FIFO.
+ *
+ * param base UART peripheral base address.
+ * param enable true to enable, false to disable.
+ * retval kStatus_Success Successfully turn on or turn off Tx FIFO.
+ * retval kStatus_Fail Fail to turn on or turn off Tx FIFO.
+ */
+status_t UART_EnableTxFIFO(UART_Type *base, bool enable);
+
+/*!
+ * @brief Enables or disables the UART Rx FIFO.
+ *
+ * This function enables or disables the UART Rx FIFO.
+ *
+ * param base UART peripheral base address.
+ * param enable true to enable, false to disable.
+ * retval kStatus_Success Successfully turn on or turn off Rx FIFO.
+ * retval kStatus_Fail Fail to turn on or turn off Rx FIFO.
+ */
+status_t UART_EnableRxFIFO(UART_Type *base, bool enable);
+
+/*!
+ * @brief Sets the rx FIFO watermark.
+ *
+ * @param base UART peripheral base address.
+ * @param water Rx FIFO watermark.
+ */
+static inline void UART_SetRxFifoWatermark(UART_Type *base, uint8_t water)
+{
+    assert((uint8_t)FSL_FEATURE_UART_FIFO_SIZEn(base) >= water);
+    base->RWFIFO = water;
+}
+
+/*!
+ * @brief Sets the tx FIFO watermark.
+ *
+ * @param base UART peripheral base address.
+ * @param water Tx FIFO watermark.
+ */
+static inline void UART_SetTxFifoWatermark(UART_Type *base, uint8_t water)
+{
+    assert((uint8_t)FSL_FEATURE_UART_FIFO_SIZEn(base) >= water);
+    base->TWFIFO = water;
+}
+#endif /* FSL_FEATURE_UART_HAS_FIFO */
+
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param irqHandle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, void *irqHandle);
+
+/*!
+ * @brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param irqHandle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, void *irqHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_UART_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.c
new file mode 100644
index 0000000000..2f9ff5ff5d
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart_dma"
+#endif
+
+/* Array of UART handle. */
+#if (defined(UART5))
+#define UART_HANDLE_ARRAY_SIZE 6
+#else /* UART5 */
+#if (defined(UART4))
+#define UART_HANDLE_ARRAY_SIZE 5
+#else /* UART4 */
+#if (defined(UART3))
+#define UART_HANDLE_ARRAY_SIZE 4
+#else /* UART3 */
+#if (defined(UART2))
+#define UART_HANDLE_ARRAY_SIZE 3
+#else /* UART2 */
+#if (defined(UART1))
+#define UART_HANDLE_ARRAY_SIZE 2
+#else /* UART1 */
+#if (defined(UART0))
+#define UART_HANDLE_ARRAY_SIZE 1
+#else /* UART0 */
+#error No UART instance.
+#endif /* UART 0 */
+#endif /* UART 1 */
+#endif /* UART 2 */
+#endif /* UART 3 */
+#endif /* UART 4 */
+#endif /* UART 5 */
+
+/*<! Structure definition for uart_dma_handle_t. The structure is private. */
+typedef struct _uart_dma_private_handle
+{
+    UART_Type *base;
+    uart_dma_handle_t *handle;
+} uart_dma_private_handle_t;
+
+/* UART DMA transfer handle. */
+enum
+{
+    kUART_TxIdle, /* TX idle. */
+    kUART_TxBusy, /* TX busy. */
+    kUART_RxIdle, /* RX idle. */
+    kUART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static uart_dma_private_handle_t s_dmaPrivateHandle[UART_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief UART DMA send finished callback function.
+ *
+ * This function is called when UART DMA send finished. It disables the UART
+ * TX DMA request and sends @ref kStatus_UART_TxIdle to UART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void UART_TransferSendDMACallback(dma_handle_t *handle, void *param);
+
+/*!
+ * @brief UART DMA receive finished callback function.
+ *
+ * This function is called when UART DMA receive finished. It disables the UART
+ * RX DMA request and sends @ref kStatus_UART_RxIdle to UART callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void UART_TransferSendDMACallback(dma_handle_t *handle, void *param)
+{
+    assert(handle != NULL);
+    assert(param != NULL);
+
+    uart_dma_private_handle_t *uartPrivateHandle = (uart_dma_private_handle_t *)param;
+
+    /* Disable UART TX DMA. */
+    UART_EnableTxDMA(uartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    /* Enable tx complete interrupt */
+    UART_EnableInterrupts(uartPrivateHandle->base, (uint32_t)kUART_TransmissionCompleteInterruptEnable);
+}
+
+static void UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
+{
+    assert(handle != NULL);
+    assert(param != NULL);
+
+    uart_dma_private_handle_t *uartPrivateHandle = (uart_dma_private_handle_t *)param;
+
+    /* Disable UART RX DMA. */
+    UART_EnableRxDMA(uartPrivateHandle->base, false);
+
+    /* Disable interrupt. */
+    DMA_DisableInterrupts(handle->base, handle->channel);
+
+    uartPrivateHandle->handle->rxState = (uint8_t)kUART_RxIdle;
+
+    if (uartPrivateHandle->handle->callback != NULL)
+    {
+        uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle,
+                                            uartPrivateHandle->handle->userData);
+    }
+}
+
+/*!
+ * brief Initializes the UART handle which is used in transactional functions and sets the callback.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_dma_handle_t structure.
+ * param callback UART callback, NULL means no callback.
+ * param userData User callback function data.
+ * param rxDmaHandle User requested DMA handle for the RX DMA transfer.
+ * param txDmaHandle User requested DMA handle for the TX DMA transfer.
+ */
+void UART_TransferCreateHandleDMA(UART_Type *base,
+                                  uart_dma_handle_t *handle,
+                                  uart_dma_transfer_callback_t callback,
+                                  void *userData,
+                                  dma_handle_t *txDmaHandle,
+                                  dma_handle_t *rxDmaHandle)
+{
+    assert(handle != NULL);
+
+    uint32_t instance = UART_GetInstance(base);
+
+    (void)memset(handle, 0, sizeof(*handle));
+
+    s_dmaPrivateHandle[instance].base   = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    handle->rxState = (uint8_t)kUART_RxIdle;
+    handle->txState = (uint8_t)kUART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+    /* Note:
+       Take care of the RX FIFO, DMA request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       DMA transfer because the water mark is 2.
+     */
+    if (rxDmaHandle != NULL)
+    {
+        base->RWFIFO = 1U;
+    }
+#endif
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_uartHandle[instance] = handle;
+    /* Save IRQ handler into static ISR function pointer. */
+    s_uartIsr = UART_TransferDMAHandleIRQ;
+    /* Disable internal IRQs and enable global IRQ. */
+    UART_DisableInterrupts(base, (uint32_t)kUART_AllInterruptsEnable);
+    (void)EnableIRQ(s_uartIRQ[instance]);
+
+    /* Configure TX. */
+    if (txDmaHandle != NULL)
+    {
+        DMA_SetCallback(txDmaHandle, UART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle != NULL)
+    {
+        DMA_SetCallback(rxDmaHandle, UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+}
+
+/*!
+ * brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART DMA transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->data != NULL);
+    assert(xfer->dataSize != 0U);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if ((uint8_t)kUART_TxBusy == handle->txState)
+    {
+        status = kStatus_UART_TxBusy;
+    }
+    else
+    {
+        handle->txState       = (uint8_t)kUART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (uint32_t *)UART_GetDataRegisterAddress(base),
+                            sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral);
+
+        /* Submit transfer. */
+        (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+        DMA_StartTransfer(handle->txDmaHandle);
+
+        /* Enable UART TX DMA. */
+        UART_EnableTxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_dma_handle_t structure.
+ * param xfer UART DMA transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_RxBusy Previous transfer on going.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+    assert(xfer != NULL);
+    assert(xfer->data != NULL);
+    assert(xfer->dataSize != 0U);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if ((uint8_t)kUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_UART_RxBusy;
+    }
+    else
+    {
+        handle->rxState       = (uint8_t)kUART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (uint32_t *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
+                            sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt);
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        /* Enable UART RX DMA. */
+        UART_EnableRxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the send data using DMA.
+ *
+ * This function aborts the sent data using DMA.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to uart_dma_handle_t structure.
+ */
+void UART_TransferAbortSendDMA(UART_Type *base, uart_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+
+    /* Disable UART TX DMA. */
+    UART_EnableTxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->txDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->txState = (uint8_t)kUART_TxIdle;
+}
+
+/*!
+ * brief Aborts the received data using DMA.
+ *
+ * This function abort receive data which using DMA.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to uart_dma_handle_t structure.
+ */
+void UART_TransferAbortReceiveDMA(UART_Type *base, uart_dma_handle_t *handle)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+
+    /* Disable UART RX DMA. */
+    UART_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+
+    /* Write DMA->DSR[DONE] to abort transfer and clear status. */
+    DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel,
+                                (uint32_t)kDMA_TransactionsDoneFlag);
+
+    handle->rxState = (uint8_t)kUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes written to UART TX register.
+ *
+ * This function gets the number of bytes written to UART TX
+ * register by DMA.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->txDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle != NULL);
+    assert(handle->rxDmaHandle != NULL);
+    assert(count != NULL);
+
+    if ((uint8_t)kUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+void UART_TransferDMAHandleIRQ(UART_Type *base, void *uartDmaHandle)
+{
+    assert(uartDmaHandle != NULL);
+
+    uart_dma_handle_t *handle = (uart_dma_handle_t *)uartDmaHandle;
+
+    handle->txState = (uint8_t)kUART_TxIdle;
+
+    /* Disable tx complete interrupt */
+    UART_DisableInterrupts(base, (uint32_t)kUART_TransmissionCompleteInterruptEnable);
+
+    if (handle->callback != NULL)
+    {
+        handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
+    }
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.h
new file mode 100644
index 0000000000..4cc0112691
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_dma.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_UART_DMA_H_
+#define FSL_UART_DMA_H_
+
+#include "fsl_uart.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup uart_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief UART DMA driver version. */
+#define FSL_UART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
+
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_dma_handle uart_dma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*uart_dma_transfer_callback_t)(UART_Type *base,
+                                             uart_dma_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+ * @brief UART DMA handle
+ */
+struct _uart_dma_handle
+{
+    UART_Type *base; /*!< UART peripheral base address. */
+
+    uart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< UART callback function parameter.*/
+    size_t rxDataSizeAll;                  /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                  /*!< Size of the data to send out. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle which is used in transactional functions and sets the callback.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_dma_handle_t structure.
+ * @param callback UART callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMA handle for the RX DMA transfer.
+ * @param txDmaHandle User requested DMA handle for the TX DMA transfer.
+ */
+void UART_TransferCreateHandleDMA(UART_Type *base,
+                                  uart_dma_handle_t *handle,
+                                  uart_dma_transfer_callback_t callback,
+                                  void *userData,
+                                  dma_handle_t *txDmaHandle,
+                                  dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART DMA transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_dma_handle_t structure.
+ * @param xfer UART DMA transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the send data using DMA.
+ *
+ * This function aborts the sent data using DMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to uart_dma_handle_t structure.
+ */
+void UART_TransferAbortSendDMA(UART_Type *base, uart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function abort receive data which using DMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to uart_dma_handle_t structure.
+ */
+void UART_TransferAbortReceiveDMA(UART_Type *base, uart_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes written to UART TX register.
+ *
+ * This function gets the number of bytes written to UART TX
+ * register by DMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief UART DMA IRQ handle function.
+ *
+ * This function handles the UART transmit complete IRQ request and invoke user callback.
+ *
+ * @param base UART peripheral base address.
+ * @param uartDmaHandle UART handle pointer.
+ */
+void UART_TransferDMAHandleIRQ(UART_Type *base, void *uartDmaHandle);
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_UART_DMA_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_freertos.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_freertos.h
new file mode 100644
index 0000000000..c46fa02f5f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_uart_freertos.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_UART_RTOS_H__
+#define __FSL_UART_RTOS_H__
+
+#include "fsl_uart.h"
+#include <FreeRTOS.h>
+#include <event_groups.h>
+#include <semphr.h>
+
+/*!
+ * @addtogroup uart_freertos_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UART FreeRTOS driver version. */
+#define FSL_UART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*@}*/
+
+/*! @brief UART configuration structure */
+typedef struct _uart_rtos_config
+{
+    UART_Type *base;                /*!< UART base address */
+    uint32_t srcclk;                /*!< UART source clock in Hz*/
+    uint32_t baudrate;              /*!< Desired communication speed */
+    uart_parity_mode_t parity;      /*!< Parity setting */
+    uart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */
+    uint8_t *buffer;                /*!< Buffer for background reception */
+    uint32_t buffer_size;           /*!< Size of buffer for background reception */
+} uart_rtos_config_t;
+
+/*!
+ * @cond RTOS_PRIVATE
+ * @name UART FreeRTOS handler
+ *
+ * These are the only valid states for txEvent and rxEvent (uart_rtos_handle_t).
+ */
+/*@{*/
+/*! @brief Event flag - transfer complete. */
+#define RTOS_UART_COMPLETE 0x1U
+/*! @brief Event flag - ring buffer overrun. */
+#define RTOS_UART_RING_BUFFER_OVERRUN 0x2U
+/*! @brief Event flag - hardware buffer overrun. */
+#define RTOS_UART_HARDWARE_BUFFER_OVERRUN 0x4U
+/*@}*/
+
+/*! @brief UART FreeRTOS transfer structure. */
+typedef struct _uart_rtos_handle
+{
+    UART_Type *base;               /*!< UART base address */
+    uart_transfer_t txTransfer;    /*!< TX transfer structure */
+    uart_transfer_t rxTransfer;    /*!< RX transfer structure */
+    SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */
+    SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */
+    EventGroupHandle_t rxEvent;    /*!< RX completion event */
+    EventGroupHandle_t txEvent;    /*!< TX completion event */
+    void *t_state;                 /*!< Transactional state of the underlying driver */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */
+    StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */
+    StaticEventGroup_t txEventBuffer;    /*!< Statically allocated memory for txEvent */
+    StaticEventGroup_t rxEventBuffer;    /*!< Statically allocated memory for rxEvent */
+#endif
+} uart_rtos_handle_t;
+/*! \endcond */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name UART RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance for operation in RTOS.
+ *
+ * @param handle The RTOS UART handle, the pointer to an allocated space for RTOS context.
+ * @param t_handle The pointer to the allocated space to store the transactional layer internal state.
+ * @param cfg The pointer to the parameters required to configure the UART after initialization.
+ * @return 0 succeed; otherwise fail.
+ */
+int UART_RTOS_Init(uart_rtos_handle_t *handle, uart_handle_t *t_handle, const uart_rtos_config_t *cfg);
+
+/*!
+ * @brief Deinitializes a UART instance for operation.
+ *
+ * This function deinitializes the UART module, sets all register values to reset value,
+ * and frees the resources.
+ *
+ * @param handle The RTOS UART handle.
+ */
+int UART_RTOS_Deinit(uart_rtos_handle_t *handle);
+
+/*!
+ * @name UART transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Sends data in the background.
+ *
+ * This function sends data. It is a synchronous API.
+ * If the hardware buffer is full, the task is in the blocked state.
+ *
+ * @param handle The RTOS UART handle.
+ * @param buffer The pointer to the buffer to send.
+ * @param length The number of bytes to send.
+ */
+int UART_RTOS_Send(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length);
+
+/*!
+ * @brief Receives data.
+ *
+ * This function receives data from UART. It is a synchronous API. If data is immediately available,
+ * it is returned immediately and the number of bytes received.
+ *
+ * @param handle The RTOS UART handle.
+ * @param buffer The pointer to the buffer to write received data.
+ * @param length The number of bytes to receive.
+ * @param received The pointer to a variable of size_t where the number of received data is filled.
+ */
+int UART_RTOS_Receive(uart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_UART_RTOS_H__ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.c
new file mode 100644
index 0000000000..400e5a6229
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_vref.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.vref"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base VREF peripheral base address
+ *
+ * @return The VREF instance
+ */
+static uint32_t VREF_GetInstance(VREF_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to VREF bases for each instance. */
+static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to VREF clocks for each instance. */
+static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t VREF_GetInstance(VREF_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
+    {
+        if (s_vrefBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_vrefBases));
+
+    return instance;
+}
+
+/*!
+ * brief Enables the clock gate and configures the VREF module according to the configuration structure.
+ *
+ * This function must be called before calling all other VREF driver functions,
+ * read/write registers, and configurations with user-defined settings.
+ * The example below shows how to set up  vref_config_t parameters and
+ * how to call the VREF_Init function by passing in these parameters.
+ * This is an example.
+ * code
+ *   vref_config_t vrefConfig;
+ *   vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig.enableExternalVoltRef = false;
+ *   vrefConfig.enableLowRef = false;
+ *   VREF_Init(VREF, &vrefConfig);
+ * endcode
+ *
+ * param base VREF peripheral address.
+ * param config Pointer to the configuration structure.
+ */
+void VREF_Init(VREF_Type *base, const vref_config_t *config)
+{
+    assert(config != NULL);
+
+    uint8_t reg = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate clock for VREF */
+    CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* Configure VREF to a known state */
+#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
+    /* Set chop oscillator bit */
+    base->TRM |= VREF_TRM_CHOPEN_MASK;
+#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
+/* Get current SC register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFH_SC;
+#else
+    reg      = base->SC;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    /* Clear old buffer mode selection bits */
+    reg &= ~(uint8_t)VREF_SC_MODE_LV_MASK;
+    /* Set buffer Mode selection and Regulator enable bit */
+    reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
+#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
+    /* Set second order curvature compensation enable bit */
+    reg |= VREF_SC_ICOMPEN(1U);
+#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
+    /* Enable VREF module */
+    reg |= VREF_SC_VREFEN(1U);
+/* Update bit-field from value to Status and Control register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    base->VREFH_SC = reg;
+#else
+    base->SC = reg;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFL_TRM;
+    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
+    reg &= (uint8_t)(~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK));
+    /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
+    reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
+    base->VREFL_TRM = reg;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    reg = base->TRM4;
+    /* Clear old select internal voltage reference bit (2.1V) */
+    reg &= ~(uint8_t)VREF_TRM4_VREF2V1_EN_MASK;
+    /* Select internal voltage reference (2.1V) */
+    reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
+    base->TRM4 = reg;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+/* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+/*!
+ * brief Stops and disables the clock for the VREF module.
+ *
+ * This function should be called to shut down the module.
+ * This is an example.
+ * code
+ *   vref_config_t vrefUserConfig;
+ *   VREF_Init(VREF);
+ *   VREF_GetDefaultConfig(&vrefUserConfig);
+ *   ...
+ *   VREF_Deinit(VREF);
+ * endcode
+ *
+ * param base VREF peripheral address.
+ */
+void VREF_Deinit(VREF_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate clock for VREF */
+    CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Initializes the VREF configuration structure.
+ *
+ * This function initializes the VREF configuration structure to default values.
+ * This is an example.
+ * code
+ *   vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig->enableExternalVoltRef = false;
+ *   vrefConfig->enableLowRef = false;
+ * endcode
+ *
+ * param config Pointer to the initialization structure.
+ */
+void VREF_GetDefaultConfig(vref_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+/* Set High power buffer mode in */
+#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
+    config->bufferMode = kVREF_ModeHighPowerBuffer;
+#else
+    config->bufferMode = kVREF_ModeTightRegulationBuffer;
+#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    /* Select internal voltage reference */
+    config->enableExternalVoltRef = false;
+    /* Set VREFL (0.4 V) reference buffer disable */
+    config->enableLowRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    /* Disable internal voltage reference (2.1V) */
+    config->enable2V1VoltRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+}
+
+/*!
+ * brief Sets a TRIM value for the reference voltage.
+ *
+ * This function sets a TRIM value for the reference voltage.
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * param base VREF peripheral address.
+ * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference */
+    reg       = base->TRM;
+    reg       = (uint8_t)((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
+    base->TRM = reg;
+/* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+/*!
+ * brief Sets a TRIM value for the reference voltage (2V1).
+ *
+ * This function sets a TRIM value for the reference voltage (2V1).
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * param base VREF peripheral address.
+ * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference (2V1) */
+    reg        = base->TRM4;
+    reg        = (uint8_t)((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
+    base->TRM4 = reg;
+    /* Wait until internal voltage stable */
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
+    {
+    }
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+/*!
+ * brief Sets the TRIM value for the low voltage reference.
+ *
+ * This function sets the TRIM value for low reference voltage.
+ * Note the following.
+ *      - The TRIM value maximum is 0x05U
+ *      - The values 111b and 110b are not valid/allowed.
+ *
+ * param base VREF peripheral address.
+ * param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)).
+ */
+void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
+{
+    /* The values 111b and 110b are NOT valid/allowed */
+    assert((trimValue != 0x7U) && (trimValue != 0x6U));
+
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in low voltage reference */
+    reg             = base->VREFL_TRM;
+    reg             = ((reg & (uint8_t)(~VREF_VREFL_TRM_VREFL_TRIM_MASK)) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
+    base->VREFL_TRM = reg;
+    /* Wait until internal voltage stable */
+
+    while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
+    {
+    }
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.h
new file mode 100644
index 0000000000..ded4bdb70e
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/drivers/fsl_vref.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_VREF_H_
+#define FSL_VREF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup vref
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */
+/*! @} */
+
+/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+#define VREF_SC_MODE_LV       VREF_VREFH_SC_MODE_LV
+#define VREF_SC_REGEN         VREF_VREFH_SC_REGEN
+#define VREF_SC_VREFEN        VREF_VREFH_SC_VREFEN
+#define VREF_SC_ICOMPEN       VREF_VREFH_SC_ICOMPEN
+#define VREF_SC_REGEN_MASK    VREF_VREFH_SC_REGEN_MASK
+#define VREF_SC_VREFST_MASK   VREF_VREFH_SC_VREFST_MASK
+#define VREF_SC_VREFEN_MASK   VREF_VREFH_SC_VREFEN_MASK
+#define VREF_SC_MODE_LV_MASK  VREF_VREFH_SC_MODE_LV_MASK
+#define VREF_SC_ICOMPEN_MASK  VREF_VREFH_SC_ICOMPEN_MASK
+#define TRM                   VREFH_TRM
+#define VREF_TRM_TRIM         VREF_VREFH_TRM_TRIM
+#define VREF_TRM_CHOPEN_MASK  VREF_VREFH_TRM_CHOPEN_MASK
+#define VREF_TRM_TRIM_MASK    VREF_VREFH_TRM_TRIM_MASK
+#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT
+#define VREF_TRM_TRIM_SHIFT   VREF_VREFH_TRM_TRIM_SHIFT
+#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT
+#define VREF_SC_REGEN_SHIFT   VREF_VREFH_SC_REGEN_SHIFT
+#define VREF_SC_VREFST_SHIFT  VREF_VREFH_SC_VREFST_SHIFT
+#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*!
+ * @brief VREF modes.
+ */
+typedef enum _vref_buffer_mode
+{
+    kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */
+#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
+    kVREF_ModeHighPowerBuffer = 1U, /*!< High-power buffer mode enabled */
+    kVREF_ModeLowPowerBuffer  = 2U  /*!< Low-power buffer mode enabled */
+#else
+    kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */
+#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
+} vref_buffer_mode_t;
+
+/*!
+ * @brief The description structure for the VREF module.
+ */
+typedef struct _vref_config
+{
+    vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    bool enableLowRef;          /*!< Set VREFL (0.4 V) reference buffer enable or disable */
+    bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */
+#endif                          /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    bool enable2V1VoltRef; /*!< Enable Internal Voltage Reference (2.1V) */
+#endif                     /* FSL_FEATURE_VREF_HAS_TRM4 */
+} vref_config_t;
+
+/******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name VREF functional operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the clock gate and configures the VREF module according to the configuration structure.
+ *
+ * This function must be called before calling all other VREF driver functions,
+ * read/write registers, and configurations with user-defined settings.
+ * The example below shows how to set up  vref_config_t parameters and
+ * how to call the VREF_Init function by passing in these parameters.
+ * This is an example.
+ * @code
+ *   vref_config_t vrefConfig;
+ *   vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig.enableExternalVoltRef = false;
+ *   vrefConfig.enableLowRef = false;
+ *   VREF_Init(VREF, &vrefConfig);
+ * @endcode
+ *
+ * @param base VREF peripheral address.
+ * @param config Pointer to the configuration structure.
+ */
+void VREF_Init(VREF_Type *base, const vref_config_t *config);
+
+/*!
+ * @brief Stops and disables the clock for the VREF module.
+ *
+ * This function should be called to shut down the module.
+ * This is an example.
+ * @code
+ *   vref_config_t vrefUserConfig;
+ *   VREF_Init(VREF);
+ *   VREF_GetDefaultConfig(&vrefUserConfig);
+ *   ...
+ *   VREF_Deinit(VREF);
+ * @endcode
+ *
+ * @param base VREF peripheral address.
+ */
+void VREF_Deinit(VREF_Type *base);
+
+/*!
+ * @brief Initializes the VREF configuration structure.
+ *
+ * This function initializes the VREF configuration structure to default values.
+ * This is an example.
+ * @code
+ *   vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig->enableExternalVoltRef = false;
+ *   vrefConfig->enableLowRef = false;
+ * @endcode
+ *
+ * @param config Pointer to the initialization structure.
+ */
+void VREF_GetDefaultConfig(vref_config_t *config);
+
+/*!
+ * @brief Sets a TRIM value for the reference voltage.
+ *
+ * This function sets a TRIM value for the reference voltage.
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage.
+ *
+ * This function gets the TRIM value from the TRM register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrimVal(VREF_Type *base)
+{
+    return (base->TRM & VREF_TRM_TRIM_MASK);
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+/*!
+ * @brief Sets a TRIM value for the reference voltage (2V1).
+ *
+ * This function sets a TRIM value for the reference voltage (2V1).
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage (2V1).
+ *
+ * This function gets the TRIM value from the VREF_TRM4 register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrim2V1Val(VREF_Type *base)
+{
+    return (base->TRM4 & VREF_TRM4_TRIM2V1_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+
+/*!
+ * @brief Sets the TRIM value for the low voltage reference.
+ *
+ * This function sets the TRIM value for low reference voltage.
+ * Note the following.
+ *      - The TRIM value maximum is 0x05U
+ *      - The values 111b and 110b are not valid/allowed.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)).
+ */
+void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage.
+ *
+ * This function gets the TRIM value from the VREFL_TRM register.
+ *
+ * @param base VREF peripheral address.
+ * @return Three-bit value of the trim setting.
+ */
+static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base)
+{
+    return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* FSL_VREF_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/fsl_device_registers.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/fsl_device_registers.h
new file mode 100644
index 0000000000..4b61d468a7
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/fsl_device_registers.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2024 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MCXC444VLH) || defined(CPU_MCXC444VMP))
+
+#define MCXC444_SERIES
+
+/* CMSIS-style register definitions */
+#include "MCXC444.h"
+/* CPU specific feature definitions */
+#include "MCXC444_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/gcc/startup_MCXC444.S b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/gcc/startup_MCXC444.S
new file mode 100644
index 0000000000..99bec9ca66
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/gcc/startup_MCXC444.S
@@ -0,0 +1,377 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_MCXC444.s                                              */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                      */
+/*            MCXC444                                                        */
+/*  @version: 1.0                                                            */
+/*  @date:    2024-3-11                                                      */
+/*  @build:   b240401                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2024 NXP                                                   */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
+    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
+    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
+    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
+    .long   Reserved20_IRQHandler                           /* Reserved interrupt*/
+    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
+    .long   PMC_IRQHandler                                  /* Low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 single interrupt vector for all sources*/
+    .long   SPI1_IRQHandler                                 /* SPI1 single interrupt vector for all sources*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   UART2_FLEXIO_IRQHandler                         /* UART2 or FLEXIO*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   TPM0_IRQHandler                                 /* TPM0 single interrupt vector for all sources*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   RTC_IRQHandler                                  /* RTC alarm*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   I2S0_IRQHandler                                 /* I2S0 interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   Reserved42_IRQHandler                           /* Reserved interrupt*/
+    .long   Reserved43_IRQHandler                           /* Reserved interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
+    .long   LCD_IRQHandler                                  /* LCD interrupt*/
+    .long   PORTA_IRQHandler                                /* PORTA Pin detect*/
+    .long   PORTC_PORTD_IRQHandler                          /* Single interrupt vector for PORTC; PORTD Pin detect*/
+
+    .size   __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3FFE
+
+    .text
+    .thumb
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#endif
+#endif
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__isr_vector
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    subs    r2, r1
+    ble .LC3
+
+    movs    r0, 0
+.LC2:
+    subs    r2, 4
+    str r0, [r1, r2]
+    bgt .LC2
+.LC3:
+#endif
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#ifdef __REDLIB__
+#define __START __main
+#else
+#define __START _start
+#endif
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_IRQHandler
+    .type DMA2_IRQHandler, %function
+DMA2_IRQHandler:
+    ldr   r0,=DMA2_DriverIRQHandler
+    bx    r0
+    .size DMA2_IRQHandler, . - DMA2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_IRQHandler
+    .type DMA3_IRQHandler, %function
+DMA3_IRQHandler:
+    ldr   r0,=DMA3_DriverIRQHandler
+    bx    r0
+    .size DMA3_IRQHandler, . - DMA3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C0_IRQHandler
+    .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    ldr   r0,=I2C0_DriverIRQHandler
+    bx    r0
+    .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C1_IRQHandler
+    .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    ldr   r0,=I2C1_DriverIRQHandler
+    bx    r0
+    .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI0_IRQHandler
+    .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    ldr   r0,=SPI0_DriverIRQHandler
+    bx    r0
+    .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI1_IRQHandler
+    .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    ldr   r0,=SPI1_DriverIRQHandler
+    bx    r0
+    .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART0_IRQHandler
+    .type LPUART0_IRQHandler, %function
+LPUART0_IRQHandler:
+    ldr   r0,=LPUART0_DriverIRQHandler
+    bx    r0
+    .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART1_IRQHandler
+    .type LPUART1_IRQHandler, %function
+LPUART1_IRQHandler:
+    ldr   r0,=LPUART1_DriverIRQHandler
+    bx    r0
+    .size LPUART1_IRQHandler, . - LPUART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART2_FLEXIO_IRQHandler
+    .type UART2_FLEXIO_IRQHandler, %function
+UART2_FLEXIO_IRQHandler:
+    ldr   r0,=UART2_FLEXIO_DriverIRQHandler
+    bx    r0
+    .size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2S0_IRQHandler
+    .type I2S0_IRQHandler, %function
+I2S0_IRQHandler:
+    ldr   r0,=I2S0_DriverIRQHandler
+    bx    r0
+    .size I2S0_IRQHandler, . - I2S0_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+/* Exception Handlers */
+    def_irq_handler    DMA0_DriverIRQHandler
+    def_irq_handler    DMA1_DriverIRQHandler
+    def_irq_handler    DMA2_DriverIRQHandler
+    def_irq_handler    DMA3_DriverIRQHandler
+    def_irq_handler    Reserved20_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    I2C0_DriverIRQHandler
+    def_irq_handler    I2C1_DriverIRQHandler
+    def_irq_handler    SPI0_DriverIRQHandler
+    def_irq_handler    SPI1_DriverIRQHandler
+    def_irq_handler    LPUART0_DriverIRQHandler
+    def_irq_handler    LPUART1_DriverIRQHandler
+    def_irq_handler    UART2_FLEXIO_DriverIRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    I2S0_DriverIRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    Reserved42_IRQHandler
+    def_irq_handler    Reserved43_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    LCD_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTC_PORTD_IRQHandler
+
+    .end
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/iar/startup_MCXC444.s b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/iar/startup_MCXC444.s
new file mode 100644
index 0000000000..40d222e733
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/iar/startup_MCXC444.s
@@ -0,0 +1,304 @@
+; -------------------------------------------------------------------------
+;  @file:    startup_MCXC444.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MCXC444
+;  @version: 1.0
+;  @date:    2024-3-11
+;  @build:   b240401
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2024 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__iar_init$$done:              ; The vector table is not needed
+                      ; until after copy initialization is done
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_IRQHandler                               ;DMA channel 0 transfer complete
+        DCD     DMA1_IRQHandler                               ;DMA channel 1 transfer complete
+        DCD     DMA2_IRQHandler                               ;DMA channel 2 transfer complete
+        DCD     DMA3_IRQHandler                               ;DMA channel 3 transfer complete
+        DCD     Reserved20_IRQHandler                         ;Reserved interrupt
+        DCD     FTFA_IRQHandler                               ;Command complete and read collision
+        DCD     PMC_IRQHandler                                ;Low-voltage detect, low-voltage warning
+        DCD     LLWU_IRQHandler                               ;Low leakage wakeup
+        DCD     I2C0_IRQHandler                               ;I2C0 interrupt
+        DCD     I2C1_IRQHandler                               ;I2C1 interrupt
+        DCD     SPI0_IRQHandler                               ;SPI0 single interrupt vector for all sources
+        DCD     SPI1_IRQHandler                               ;SPI1 single interrupt vector for all sources
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     UART2_FLEXIO_IRQHandler                       ;UART2 or FLEXIO
+        DCD     ADC0_IRQHandler                               ;ADC0 interrupt
+        DCD     CMP0_IRQHandler                               ;CMP0 interrupt
+        DCD     TPM0_IRQHandler                               ;TPM0 single interrupt vector for all sources
+        DCD     TPM1_IRQHandler                               ;TPM1 single interrupt vector for all sources
+        DCD     TPM2_IRQHandler                               ;TPM2 single interrupt vector for all sources
+        DCD     RTC_IRQHandler                                ;RTC alarm
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     PIT_IRQHandler                                ;PIT interrupt
+        DCD     I2S0_IRQHandler                               ;I2S0 interrupt
+        DCD     USB0_IRQHandler                               ;USB0 interrupt
+        DCD     DAC0_IRQHandler                               ;DAC0 interrupt
+        DCD     Reserved42_IRQHandler                         ;Reserved interrupt
+        DCD     Reserved43_IRQHandler                         ;Reserved interrupt
+        DCD     LPTMR0_IRQHandler                             ;LPTMR0 interrupt
+        DCD     LCD_IRQHandler                                ;LCD interrupt
+        DCD     PORTA_IRQHandler                              ;PORTA Pin detect
+        DCD     PORTC_PORTD_IRQHandler                        ;Single interrupt vector for PORTC; PORTD Pin detect
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+        DCD 0xFFFFFFFF
+        DCD 0xFFFFFFFF
+        DCD 0xFFFFFFFF
+        DCD 0xFFFF3FFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =0xE000ED08
+        LDR     R1, =__vector_table
+        STR     R1, [R0]
+        LDR     R2, [R1]
+        MSR     MSP, R2
+        LDR     R0, =SystemInit
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA1_IRQHandler
+        PUBWEAK DMA1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA1_IRQHandler
+        LDR     R0, =DMA1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA2_IRQHandler
+        PUBWEAK DMA2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA2_IRQHandler
+        LDR     R0, =DMA2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA3_IRQHandler
+        PUBWEAK DMA3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA3_IRQHandler
+        LDR     R0, =DMA3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved20_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK I2C0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+I2C0_IRQHandler
+        LDR     R0, =I2C0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK I2C1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+I2C1_IRQHandler
+        LDR     R0, =I2C1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK SPI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPI0_IRQHandler
+        LDR     R0, =SPI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK SPI1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPI1_IRQHandler
+        LDR     R0, =SPI1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LPUART0_IRQHandler
+        LDR     R0, =LPUART0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK LPUART1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LPUART1_IRQHandler
+        LDR     R0, =LPUART1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK UART2_FLEXIO_IRQHandler
+        PUBWEAK UART2_FLEXIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UART2_FLEXIO_IRQHandler
+        LDR     R0, =UART2_FLEXIO_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK PIT_IRQHandler
+        PUBWEAK I2S0_IRQHandler
+        PUBWEAK I2S0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+I2S0_IRQHandler
+        LDR     R0, =I2S0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK Reserved42_IRQHandler
+        PUBWEAK Reserved43_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTC_PORTD_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DriverIRQHandler
+DMA1_DriverIRQHandler
+DMA2_DriverIRQHandler
+DMA3_DriverIRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+PMC_IRQHandler
+LLWU_IRQHandler
+I2C0_DriverIRQHandler
+I2C1_DriverIRQHandler
+SPI0_DriverIRQHandler
+SPI1_DriverIRQHandler
+LPUART0_DriverIRQHandler
+LPUART1_DriverIRQHandler
+UART2_FLEXIO_DriverIRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_DriverIRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+Reserved42_IRQHandler
+Reserved43_IRQHandler
+LPTMR0_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTC_PORTD_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.c b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.c
new file mode 100644
index 0000000000..98dc64d9d3
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.c
@@ -0,0 +1,109 @@
+/*
+** ###################################################################
+**     Processors:          MCXC444VLH
+**                          MCXC444VMP
+**
+**     Compilers:           Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240401
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-11)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXC444
+ * @version 1.0
+ * @date 2024-03-11
+ * @brief Device specific configuration file for MCXC444 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (ACK_ISOLATION)
+  if((PMC->REGSC &  PMC_REGSC_ACKISO_MASK) != 0U) {
+    PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
+  }
+#endif
+
+#if (DISABLE_WDOG)
+  /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
+  SIM->COPC = (uint32_t)0x00U;
+#endif /* (DISABLE_WDOG) */
+
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
+    /* High internal reference clock is selected */
+    MCGOUTClock = CPU_INT_FAST_CLK_HZ;                                  /* Fast internal reference clock selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
+    /* Internal reference clock is selected */
+    Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+    MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider);           /* Slow internal reference clock 8MHz selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
+    /* External reference clock is selected */
+    MCGOUTClock = CPU_XTAL_CLK_HZ;
+  } else {
+    /* Reserved value */
+    return;
+  } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.h b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.h
new file mode 100644
index 0000000000..d7ecec039b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/MCXC444/system_MCXC444.h
@@ -0,0 +1,121 @@
+/*
+** ###################################################################
+**     Processors:          MCXC444VLH
+**                          MCXC444VMP
+**
+**     Compilers:           Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240401
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2024-03-11)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MCXC444
+ * @version 1.0
+ * @date 2024-03-11
+ * @brief Device specific configuration file for MCXC444 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MCXC444_H_
+#define _SYSTEM_MCXC444_H_                       /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+#define ACK_ISOLATION                  1
+
+/* Define clock source values */
+#define CPU_XTAL_CLK_HZ                32768U              /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ            48000000U           /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ             48000000U           /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+#define DEFAULT_SYSTEM_CLOCK           8000000U            /* Default System clock value */
+#define CPU_INT_SLOW_CLK_HZ            8000000U            /* Value of the slow internal oscillator clock frequency in Hz */
+
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_MCXC444_H_ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/MCXC444/SConscript b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/SConscript
new file mode 100644
index 0000000000..793dcde045
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/MCXC444/SConscript
@@ -0,0 +1,48 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+path = [cwd + '/../CMSIS/Core/Include', cwd + '/MCXC444', cwd + '/MCXC444/drivers']
+src = Split('''
+            MCXC444/system_MCXC444.c
+            ''')
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += ['MCXC444/gcc/startup_MCXC444.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += ['MCXC444/arm/startup_MCXC444.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += ['MCXC444/iar/startup_MCXC444.s']
+
+src += ['MCXC444/drivers/fsl_adc16.c']
+src += ['MCXC444/drivers/fsl_clock.c']
+src += ['MCXC444/drivers/fsl_cmp.c']
+src += ['MCXC444/drivers/fsl_common.c']
+src += ['MCXC444/drivers/fsl_common_arm.c']
+src += ['MCXC444/drivers/fsl_cop.c']
+src += ['MCXC444/drivers/fsl_dac.c']
+src += ['MCXC444/drivers/fsl_dma.c']
+src += ['MCXC444/drivers/fsl_ftfx_controller.c']
+src += ['MCXC444/drivers/fsl_ftfx_flexnvm.c']
+src += ['MCXC444/drivers/fsl_gpio.c']
+src += ['MCXC444/drivers/fsl_i2c.c']
+src += ['MCXC444/drivers/fsl_i2c_dma.c']
+src += ['MCXC444/drivers/fsl_lpuart.c']
+src += ['MCXC444/drivers/fsl_lpuart_dma.c']
+src += ['MCXC444/drivers/fsl_pit.c']
+src += ['MCXC444/drivers/fsl_pmc.c']
+src += ['MCXC444/drivers/fsl_rtc.c']
+src += ['MCXC444/drivers/fsl_sai.c']
+src += ['MCXC444/drivers/fsl_sai_dma.c']
+src += ['MCXC444/drivers/fsl_sim.c']
+src += ['MCXC444/drivers/fsl_slcd.c']
+src += ['MCXC444/drivers/fsl_smc.c']
+src += ['MCXC444/drivers/fsl_spi.c']
+src += ['MCXC444/drivers/fsl_tpm.c']
+src += ['MCXC444/drivers/fsl_uart.c']
+src += ['MCXC444/drivers/fsl_uart_dma.c']
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript
new file mode 100644
index 0000000000..aedc385849
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript
@@ -0,0 +1,45 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+src = []
+
+if GetDepend('BSP_USING_PIN'):
+    src += ['drv_pin.c']
+
+if  GetDepend('BSP_USING_UART'):
+    src += ['drv_uart.c']
+
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+
+if  GetDepend('BSP_USING_SPI'):
+    src += ['drv_spi.c']
+
+if  GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+
+if  GetDepend('BSP_USING_SW_I2C'):
+    src += ['drv_soft_i2c.c']
+
+if  GetDepend('BSP_USING_ADC'):
+    src += ['drv_adc.c']
+
+if  GetDepend('BSP_USING_DAC'):
+    src += ['drv_dac.c']
+
+if  GetDepend('BSP_USING_HWTIMER'):
+    src += ['drv_hwtimer.c']
+
+if  GetDepend('BSP_USING_WDT'):
+    src += ['drv_wdt.c']
+
+if  GetDepend('BSP_USING_PWM'):
+    src += ['drv_pwm.c']
+
+
+path =  [cwd,cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.c b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.c
new file mode 100644
index 0000000000..29baf254f2
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-08-25     RT-Thread    the first version for MCXC444.
+ */
+
+#include "drv_pin.h"
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_port.h"
+
+#ifdef RT_USING_PIN
+
+#define GET_GPIO_PORT(x)      ((x) / 32)
+#define GET_GPIO_PIN(x)       ((x) % 32)
+
+static struct rt_pin_ops mcx_pin_ops;
+
+static GPIO_Type *GPIO_TYPE_TBL[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE};
+static PORT_Type *PORT_TYPE_TBL[] = {PORTA, PORTB, PORTC, PORTD, PORTE};
+static void (*pin_irq_hdr_tab[32 * 5])(void *args) = {0};
+static void *pin_irq_arg_tab[32 * 5] = {0};
+
+#define PIN2GPIO(x)     GPIO_TYPE_TBL[GET_GPIO_PORT(x)]
+#define PIN2PORT(x)     PORT_TYPE_TBL[GET_GPIO_PORT(x)]
+
+static void mcx_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+{
+    gpio_pin_config_t gpio_config = {0};
+    PORT_SetPinMux(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_MuxAsGpio);
+
+    switch (mode)
+    {
+        case PIN_MODE_OUTPUT:
+            gpio_config.pinDirection = kGPIO_DigitalOutput;
+            gpio_config.outputLogic = 0;
+            break;
+        case PIN_MODE_INPUT:
+            gpio_config.pinDirection = kGPIO_DigitalInput;
+            //PORT_SetPinPullSelect(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_PullDisable);
+            break;
+        case PIN_MODE_INPUT_PULLUP:
+            gpio_config.pinDirection = kGPIO_DigitalInput;
+            //PORT_SetPinPullSelect(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_PullUp);
+            break;
+        case PIN_MODE_INPUT_PULLDOWN:
+            gpio_config.pinDirection = kGPIO_DigitalInput;
+            //PORT_SetPinPullSelect(PIN2PORT(pin), GET_GPIO_PIN(pin), kPORT_PullDown);
+            break;
+        case PIN_MODE_OUTPUT_OD:
+            gpio_config.pinDirection = kGPIO_DigitalOutput;
+            gpio_config.outputLogic = 1;
+            //PORT_SetPinOpenDrainEnable(PIN2PORT(pin), GET_GPIO_PIN(pin), true);
+            break;
+    }
+
+    GPIO_PinInit(PIN2GPIO(pin), GET_GPIO_PIN(pin), &gpio_config);
+}
+
+static void mcx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+{
+    GPIO_PinWrite(PIN2GPIO(pin), GET_GPIO_PIN(pin), value);
+}
+
+static rt_ssize_t mcx_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    return GPIO_PinRead(PIN2GPIO(pin), GET_GPIO_PIN(pin));
+}
+
+static rt_err_t mcx_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
+{
+    PORT_Type *port = PIN2PORT(pin);
+    uint32_t pin_index = GET_GPIO_PIN(pin);
+    uint32_t port_index = GET_GPIO_PORT(pin);
+    port_interrupt_t port_int = kPORT_InterruptOrDMADisabled;
+
+    switch (mode)
+    {
+        case PIN_IRQ_MODE_RISING:
+            port_int = kPORT_InterruptRisingEdge;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            port_int = kPORT_InterruptFallingEdge;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            port_int = kPORT_InterruptEitherEdge;
+            break;
+        case PIN_IRQ_MODE_HIGH_LEVEL:
+            port_int = kPORT_InterruptLogicOne;
+            break;
+        case PIN_IRQ_MODE_LOW_LEVEL:
+            port_int = kPORT_InterruptLogicZero;
+            break;
+        default:
+            return RT_EINVAL;
+    }
+
+    PORT_SetPinInterruptConfig(port, pin_index, kPORT_InterruptOrDMADisabled);
+
+    pin_irq_hdr_tab[port_index * 32 + pin_index] = hdr;
+    pin_irq_arg_tab[port_index * 32 + pin_index] = args;
+
+    PORT_SetPinInterruptConfig(port, pin_index, port_int);
+
+    return RT_EOK;
+}
+
+
+static rt_err_t mcx_pin_detach_irq(struct rt_device *device, rt_base_t pin)
+{
+    PORT_Type *port = PIN2PORT(pin);
+    uint32_t pin_index = GET_GPIO_PIN(pin);
+
+    PORT_SetPinInterruptConfig(port, pin_index, kPORT_InterruptOrDMADisabled);
+
+    return RT_EOK;
+}
+
+static rt_err_t mcx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
+{
+    PORT_Type *port = PIN2PORT(pin);
+    uint32_t pin_index = GET_GPIO_PIN(pin);
+    IRQn_Type irqn;
+
+    switch ((uint32_t)port)
+    {
+        case PORTA_BASE:
+            irqn = PORTA_IRQn;
+            break;
+        case PORTB_BASE:
+            irqn = NotAvail_IRQn;
+            break;
+        case PORTC_BASE:
+            irqn = PORTC_PORTD_IRQn;
+            break;
+        case PORTD_BASE:
+            irqn = PORTC_PORTD_IRQn;
+            break;
+        case PORTE_BASE:
+            irqn = NotAvail_IRQn;
+            break;
+        default:
+            return RT_ERROR;
+    }
+
+    if (enabled)
+    {
+        PORT_SetPinInterruptConfig(port, pin_index, kPORT_InterruptRisingEdge);
+
+        PORT_ClearPinsInterruptFlags(port, (1U << pin_index));
+
+        NVIC_EnableIRQ(irqn);
+    }
+    else
+    {
+        PORT_SetPinInterruptConfig(port, pin_index, kPORT_InterruptOrDMADisabled);
+
+        NVIC_DisableIRQ(irqn);
+    }
+
+    return RT_EOK;
+}
+
+
+static void mcx_gpio_irq_handler(PORT_Type *port)
+{
+    uint32_t pin_index;
+    uint32_t port_index = ((uint32_t)port - PORTA_BASE) / (PORTB_BASE - PORTA_BASE);
+
+
+    for (pin_index = 0; pin_index < 32; pin_index++)
+    {
+        if (PORT_GetPinsInterruptFlags(port) & (1U << pin_index))
+        {
+            PORT_ClearPinsInterruptFlags(port, 1U << pin_index);
+            if (pin_irq_hdr_tab[port_index * 32 + pin_index])
+            {
+                pin_irq_hdr_tab[port_index * 32 + pin_index](pin_irq_arg_tab[port_index * 32 + pin_index]);
+            }
+        }
+    }
+}
+
+void PORTA_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    mcx_gpio_irq_handler(PORTA);
+    rt_interrupt_leave();
+}
+
+
+void PORTC_PORTD_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    mcx_gpio_irq_handler(PORTC);
+    rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+    int ret = RT_EOK;
+
+    mcx_pin_ops.pin_mode        = mcx_pin_mode;
+    mcx_pin_ops.pin_read        = mcx_pin_read;
+    mcx_pin_ops.pin_write       = mcx_pin_write;
+    mcx_pin_ops.pin_attach_irq  = mcx_pin_attach_irq;
+    mcx_pin_ops.pin_detach_irq  = mcx_pin_detach_irq;
+    mcx_pin_ops.pin_irq_enable  = mcx_pin_irq_enable;
+    mcx_pin_ops.pin_get         = RT_NULL;
+
+    ret = rt_device_pin_register("pin", &mcx_pin_ops, RT_NULL);
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /* RT_USING_PIN */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.h b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.h
new file mode 100644
index 0000000000..93cc4a92f6
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_pin.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-13     Liuguang     the first version.
+ * 2018-03-19     Liuguang     add GPIO interrupt mode support.
+ * 2019-07-15     yandld      The first version for MCXN
+ */
+
+#ifndef __DRV_PIN_H__
+#define __DRV_PIN_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+
+extern int rt_hw_pin_init(void);
+
+#endif /* __DRV_PIN_H__ */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.c b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.c
new file mode 100644
index 0000000000..733e4b8faa
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-08-25     RT-Thread    First version for MCXC444
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_uart.h"
+
+#include "fsl_lpuart.h"
+#include "fsl_port.h"
+#include "fsl_clock.h"
+
+#ifdef RT_USING_SERIAL
+
+/* MCXC444 UART driver */
+struct mcxc444_uart
+{
+    LPUART_Type *uart_base;
+    IRQn_Type irqn;
+    struct rt_serial_device *serial;
+    char *device_name;
+};
+
+static void uart_isr(struct rt_serial_device *serial);
+
+#if defined(BSP_USING_UART0)
+struct rt_serial_device serial0;
+
+void LPUART0_IRQHandler(void)
+{
+    uart_isr(&serial0);
+}
+
+static const struct mcxc444_uart uart0 =
+{
+    LPUART0,
+    LPUART0_IRQn,
+    &serial0,
+    "uart0",
+};
+#endif
+
+static rt_err_t mcxc444_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct mcxc444_uart *uart = (struct mcxc444_uart *)serial->parent.user_data;
+    lpuart_config_t config;
+
+    LPUART_GetDefaultConfig(&config);
+    config.baudRate_Bps = cfg->baud_rate;
+    config.enableTx = true;
+    config.enableRx = true;
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        config.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        config.stopBitCount = kLPUART_OneStopBit;
+        break;
+    case STOP_BITS_2:
+        config.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        config.parityMode = kLPUART_ParityDisabled;
+        break;
+    case PARITY_ODD:
+        config.parityMode = kLPUART_ParityOdd;
+        break;
+    case PARITY_EVEN:
+        config.parityMode = kLPUART_ParityEven;
+        break;
+    default:
+        return RT_ERROR;
+    }
+
+    CLOCK_SetLpuart0Clock(0x1U);
+    LPUART_Init(uart->uart_base, &config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
+
+    return RT_EOK;
+}
+
+static rt_err_t mcxc444_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct mcxc444_uart *uart = (struct mcxc444_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
+        DisableIRQ(uart->irqn);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
+        EnableIRQ(uart->irqn);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int mcxc444_putc(struct rt_serial_device *serial, char ch)
+{
+    struct mcxc444_uart *uart = (struct mcxc444_uart *)serial->parent.user_data;
+
+    LPUART_WriteByte(uart->uart_base, ch);
+    while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
+
+    return 1;
+}
+
+static int mcxc444_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct mcxc444_uart *uart = (struct mcxc444_uart *)serial->parent.user_data;
+
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
+    {
+        ch = LPUART_ReadByte(uart->uart_base);
+        return ch;
+    }
+    else
+    {
+        return -1;
+    }
+}
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct mcxc444_uart *uart = (struct mcxc444_uart *)serial->parent.user_data;
+
+    rt_interrupt_enter();
+
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+
+static const struct rt_uart_ops mcxc444_uart_ops =
+{
+    mcxc444_configure,
+    mcxc444_control,
+    mcxc444_putc,
+    mcxc444_getc,
+};
+
+int rt_hw_uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    serial0.ops = &mcxc444_uart_ops;
+    serial0.config = config;
+
+    rt_hw_serial_register(&serial0, uart0.device_name,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          (void *)&uart0);
+#endif
+
+    return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif /* RT_USING_SERIAL */
diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.h b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.h
new file mode 100644
index 0000000000..406ee70cac
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/drv_uart.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-15     yandld      The first version for MCXN
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+extern int rt_hw_uart_init(void);
+
+
+#endif /* __DRV_UART_H__ */
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/.config b/bsp/nxp/mcx/mcxc/frdm-mcxc444/.config
new file mode 100644
index 0000000000..e8ef6320fa
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/.config
@@ -0,0 +1,1189 @@
+CONFIG_SOC_MCX=y
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
+# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_USING_TINY_FFS is not set
+# end of kservice optimization
+
+#
+# klibc optimization
+#
+# CONFIG_RT_KLIBC_USING_STDLIB is not set
+# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set
+# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set
+# end of klibc optimization
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_ASSERT=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50200
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_SOFT_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_BITOPS is not set
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_MCXC444=y
+
+#
+# On-chip Peripheral Drivers
+#
+# CONFIG_BSP_USING_DMA is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_HWTIMER is not set
+# CONFIG_BSP_USING_PWM is not set
+# end of On-chip Peripheral Drivers
+# end of Hardware Drivers Config
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/Kconfig b/bsp/nxp/mcx/mcxc/frdm-mcxc444/Kconfig
new file mode 100644
index 0000000000..121269ec6f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/Kconfig
@@ -0,0 +1,17 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../../../..
+
+PKGS_DIR := packages
+
+config SOC_MCX
+    bool
+    select ARCH_ARM_CORTEX_M0
+    default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../Libraries/Kconfig"
+rsource "board/Kconfig"
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/README_EN.md b/bsp/nxp/mcx/mcxc/frdm-mcxc444/README_EN.md
new file mode 100644
index 0000000000..c0cb768952
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/README_EN.md
@@ -0,0 +1 @@
+FRDM-MCXC444 support
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConstruct b/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConstruct
new file mode 100644
index 0000000000..ed0bfe11ff
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/SConstruct
@@ -0,0 +1,67 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+if rtconfig.PLATFORM == 'armcc':
+    env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+        CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+        # overwrite cflags, because cflags has '--C99'
+        CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+else:
+    env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+        CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+        CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/Libraries'):
+    libraries_path_prefix = SDK_ROOT + '/Libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/SConscript
new file mode 100644
index 0000000000..f11833c8d8
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src     = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/main.c b/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/main.c
new file mode 100644
index 0000000000..e6cb9146ab
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/applications/main.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-24     Magicoe      first version
+ * 2020-01-10     Kevin/Karl   Add PS demo
+ * 2020-09-21     supperthomas fix the main.c
+ *
+ */
+
+#include <rtdevice.h>
+#include <rtthread.h>
+#include "drv_pin.h"
+
+#define LED_PIN         ((4*32)+31)
+#define BUTTON_PIN      ((2*32)+3)
+
+static void sw_pin_cb(void *args);
+
+int main(void)
+{
+#if defined(__CC_ARM)
+    rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION);
+#elif defined(__clang__)
+    rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION);
+#elif defined(__ICCARM__)
+    rt_kprintf("using iccarm, version: %d\n", __VER__);
+#elif defined(__GNUC__)
+    rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
+#endif
+
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);  /* Set GPIO as Output */
+
+    rt_pin_mode(BUTTON_PIN, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(BUTTON_PIN, PIN_IRQ_MODE_FALLING, sw_pin_cb, RT_NULL);
+    rt_pin_irq_enable(BUTTON_PIN, 1);
+
+    rt_kprintf("MCXC444 HelloWorld\r\n");
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);    /* Set GPIO output 1 */
+        rt_thread_mdelay(500);               /* Delay 500mS */
+        rt_pin_write(LED_PIN, PIN_LOW);     /* Set GPIO output 0 */
+        rt_thread_mdelay(500);               /* Delay 500mS */
+    }
+}
+
+static void sw_pin_cb(void *args)
+{
+    rt_kprintf("sw pressed\r\n");
+}
+
+// end file
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig
new file mode 100644
index 0000000000..f0ea626331
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig
@@ -0,0 +1,93 @@
+menu "Hardware Drivers Config"
+
+config SOC_MCXC444
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_DMA
+        bool "Enable DMA"
+        select RT_USING_DMA
+        default n
+
+    config BSP_USING_PIN
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y
+  
+        endif
+
+    menuconfig BSP_USING_I2C
+        config BSP_USING_I2C
+            bool "Enable I2C"
+            select RT_USING_I2C
+            default y
+
+            if BSP_USING_I2C
+                config BSP_USING_I2C0
+                    bool "Enable Flexcomm0 I2C"
+                    default y
+                config BSP_USING_I2C1
+                    bool "Enable Flexcomm1 I2C"
+                    default y
+            endif
+
+    menuconfig BSP_USING_SPI
+        config BSP_USING_SPI
+            bool "Enable SPI"
+            select RT_USING_SPI
+            select BSP_USING_PIN
+            default y
+
+            if BSP_USING_SPI
+                config BSP_USING_SPI1
+                    bool "Enable Flexcomm1 as SPI"
+                    default n
+
+            endif
+
+        
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default y
+
+    config BSP_USING_WDT
+        bool "Enable WatchDog"
+        select RT_USING_WDT
+        default n
+
+    menuconfig BSP_USING_HWTIMER
+        config BSP_USING_HWTIMER
+            bool "Enable Timer"
+            select RT_USING_HWTIMER
+            default y
+
+    menuconfig BSP_USING_PWM
+        config BSP_USING_PWM
+            bool "Enable PWM"
+            select RT_USING_PWM
+            default y
+
+            if BSP_USING_PWM
+                config BSP_USING_LEDG_PWM
+                    bool "Enable on-board green LED as PWM output (pwm0, channel 3)"
+                    default y
+            endif
+
+endmenu
+
+
+endmenu
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.c b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.c
new file mode 100644
index 0000000000..af7f2a8fbd
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v13.0
+processor: MCXC444
+package_id: MCXC444VLH
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 8 MHz}
+- {id: MCGPCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: HIRC}
+- {id: MCG.CLKS.sel, value: MCG.HIRC}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+sources:
+- {id: MCG.HIRC.outFreq, value: 48 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
+    {
+        .outSrc = kMCGLITE_ClkSrcHirc,            /* MCGOUTCLK source is HIRC */
+        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCGLITE_Lirc8M,                  /* Slow internal reference (LIRC) 8 MHz clock selected */
+        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .hircEnableInNotHircMode = true,          /* HIRC source is enabled */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to HIRC mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 1 MHz}
+- {id: Core_clock.outFreq, value: 2 MHz}
+- {id: Flash_clock.outFreq, value: 1 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 2 MHz}
+- {id: System_clock.outFreq, value: 2 MHz}
+settings:
+- {id: MCGMode, value: LIRC2M}
+- {id: powerMode, value: VLPR}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+sources:
+- {id: MCG.LIRC.outFreq, value: 2 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
+    {
+        .outSrc = kMCGLITE_ClkSrcLirc,            /* MCGOUTCLK source is LIRC */
+        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCGLITE_Lirc2M,                  /* Slow internal reference (LIRC) 2 MHz clock selected */
+        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+        .hircEnableInNotHircMode = false,         /* HIRC source is not enabled */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to LIRC2M mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
+
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.h b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.h
new file mode 100644
index 0000000000..fc45b79105
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/clock_config.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
+ */
+extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              2000000U  /*!< Core clock frequency: 2000000Hz */
+
+/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.c
new file mode 100644
index 0000000000..277fba2303
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+void BOARD_InitPins(void)
+{
+    /* Port A Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+
+    /* PORTA1 (pin 23) is configured as LPUART0_RX */
+    PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
+
+    /* PORTA2 (pin 24) is configured as LPUART0_TX */
+    PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
+
+    SIM->SOPT5 = ((SIM->SOPT5 &
+                   /* Mask bits to zero which are setting */
+                   (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
+
+                  /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+                  | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
+
+                  /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+                  | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
+}
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.h
new file mode 100644
index 0000000000..3f2b68b0f9
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/MCUX_Config/board/pin_mux.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
+#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
+
+
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* _PIN_MUX_H_ */
+
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/SConscript b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/SConscript
new file mode 100644
index 0000000000..36df070e2b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/SConscript
@@ -0,0 +1,18 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+board.c
+MCUX_Config/board/clock_config.c
+MCUX_Config/board/pin_mux.c
+""")
+
+
+CPPPATH = [cwd, cwd + '/MCUX_Config/board']
+CPPDEFINES = ['DEBUG', 'CPU_MCXC444VLH']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.c b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.c
new file mode 100644
index 0000000000..cfcd0f912a
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "board.h"
+#include "pin_mux.h"
+#include "fsl_common.h"
+
+
+void rt_hw_board_init()
+{
+    CLOCK_EnableClock(kCLOCK_PortA);
+    CLOCK_EnableClock(kCLOCK_PortB);
+    CLOCK_EnableClock(kCLOCK_PortC);
+    CLOCK_EnableClock(kCLOCK_PortD);
+    CLOCK_EnableClock(kCLOCK_PortE);
+
+    BOARD_InitBootClocks();
+    BOARD_InitPins();
+
+
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization board with RT-Thread Components */
+    rt_components_board_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_kprintf("sram heap, begin: %p, end: %p\n", HEAP_BEGIN, HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END));
+#endif
+}
+
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.h b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.h
new file mode 100644
index 0000000000..b0cdfb899f
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/board.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <rtthread.h>
+
+#include "clock_config.h"
+#include "fsl_gpio.h"
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
+extern int Image$$ARM_LIB_STACK$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
+#define HEAP_END    ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base)
+#elif defined(__ICCARM__)
+#pragma section="HEAP"
+#define HEAP_BEGIN          (__segment_end("HEAP"))
+extern void __RTT_HEAP_END;
+#define HEAP_END            (&__RTT_HEAP_END)
+#elif defined(__GNUC__)
+extern int __HeapBase;
+extern int __HeapLimit;
+#define HEAP_BEGIN  ((void *)&__HeapBase)
+#define HEAP_END  ((void *)&__HeapLimit)
+#endif
+
+void rt_hw_board_init(void);
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.icf b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.icf
new file mode 100644
index 0000000000..ee1447f940
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.icf
@@ -0,0 +1,78 @@
+/*

+** ###################################################################

+**     Processors:          MCXC444VLH

+**                          MCXC444VMP

+**

+**     Compiler:            IAR ANSI C/C++ Compiler for ARM

+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024

+**     Version:             rev. 1.0, 2024-03-11

+**     Build:               b240401

+**

+**     Abstract:

+**         Linker file for the IAR ANSI C/C++ Compiler for ARM

+**

+**     Copyright 2016 Freescale Semiconductor, Inc.

+**     Copyright 2016-2024 NXP

+**     SPDX-License-Identifier: BSD-3-Clause

+**

+**     http:                 www.nxp.com

+**     mail:                 [email protected]

+**

+** ###################################################################

+*/

+

+define symbol m_interrupts_start       = 0x00000000;

+define symbol m_interrupts_end         = 0x000001FF;

+

+define symbol m_flash_config_start     = 0x00000400;

+define symbol m_flash_config_end       = 0x0000040F;

+

+define symbol m_text_start             = 0x00000410;

+define symbol m_text_end               = 0x0003FFFF;

+

+define symbol m_data_start             = 0x1FFFE000;

+define symbol m_data_end               = 0x20005FFF;

+

+/* Sizes */

+if (isdefinedsymbol(__stack_size__)) {

+  define symbol __size_cstack__        = __stack_size__;

+} else {

+  define symbol __size_cstack__        = 0x0400;

+}

+

+if (isdefinedsymbol(__heap_size__)) {

+  define symbol __size_heap__          = __heap_size__;

+} else {

+  define symbol __size_heap__          = 0x0400;

+}

+

+

+define memory mem with size = 4G;

+define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];

+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]

+                          | mem:[from m_text_start to m_text_end];

+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];

+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];

+

+define block CSTACK    with alignment = 8, size = __size_cstack__   { };

+define block HEAP      with alignment = 8, size = __size_heap__     { };

+define block RW        { readwrite };

+define block ZI        { zi };

+define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };

+define block QACCESS_CODE  { section CodeQuickAccess };

+define block QACCESS_DATA  { section DataQuickAccess };

+

+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };

+do not initialize  { section .noinit };

+

+place at address mem: m_interrupts_start    { readonly section .intvec };

+place in m_flash_config_region              { section FlashConfig };

+place in TEXT_region                        { readonly };

+place in DATA_region                        { block RW };

+place in DATA_region                        { block ZI };

+place in DATA_region                        { last block HEAP };

+place in CSTACK_region                      { block CSTACK };

+place in DATA_region                        { block NCACHE_VAR };

+place in DATA_region                        { block QACCESS_CODE };

+place in DATA_region                        { block QACCESS_DATA };

+

diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.ld b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.ld
new file mode 100644
index 0000000000..8abb7faed5
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.ld
@@ -0,0 +1,217 @@
+/*
+** ###################################################################
+**     Processors:          MCXC444VLH
+**                          MCXC444VMP
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240401
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000200
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0003FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(NonCacheable.init)     /* NonCacheable init section */
+    *(NonCacheable)          /* NonCacheable section */
+    *(CodeQuickAccess)       /* quick access code section */
+    *(DataQuickAccess)       /* quick access data section */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.scf b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.scf
new file mode 100644
index 0000000000..d7cbdba5db
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/linker_scripts/MCXC444_flash.scf
@@ -0,0 +1,75 @@
+#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m0plus -E -x c
+/*
+** ###################################################################
+**     Processors:          MCXC444VLH
+**                          MCXC444VMP
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    MCXC444RM, Rev.1, Mar 2024
+**     Version:             rev. 1.0, 2024-03-11
+**     Build:               b240401
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000200
+
+#define m_flash_config_start           0x00000400
+#define m_flash_config_size            0x00000010
+
+#define m_text_start                   0x00000410
+#define m_text_size                    0x0003FBF0
+
+#define m_data_start                   0x1FFFE000
+#define m_data_size                    0x00008000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0800
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0000
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+  ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+    * (.FlashConfig,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    * (RamFunction)
+    * (NonCacheable.init)
+    * (*NonCacheable)
+    * (CodeQuickAccess)
+    * (DataQuickAccess)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}
+
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvoptx b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvoptx
new file mode 100644
index 0000000000..95b02053c9
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvoptx
@@ -0,0 +1,1310 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread-frdm-mcxc444</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
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+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>81</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\arm\startup_MCXC444.s</PathWithFileName>
+      <FilenameWithoutPath>startup_MCXC444.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>82</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\drivers\fsl_sim.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_sim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>83</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\drivers\fsl_adc16.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_adc16.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>84</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\drivers\fsl_rtc.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_rtc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>8</GroupNumber>
+      <FileNumber>85</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\drivers\fsl_ftfx_controller.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_ftfx_controller.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
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+      <GroupNumber>8</GroupNumber>
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+      <tvExp>0</tvExp>
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+      <PathWithFileName>..\Libraries\MCXC444\MCXC444\drivers\fsl_pmc.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_pmc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
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+      <FileNumber>87</FileNumber>
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+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
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+      <FilenameWithoutPath>fsl_spi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx
new file mode 100644
index 0000000000..8fcd940bfc
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx
@@ -0,0 +1,2714 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-frdm-mcxc444</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MCXC444VLH</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>NXP.MCXC444_DFP.17.0.0</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <Cpu>IRAM(0x1fffe000,0x8000) IROM(0x00000000,0x040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFE000 -FC800 -FN1 -FF0MK_P256_48MHZ_MCXC444 -FS00 -FL040000 -FP0($$Device:MCXC444VLH$devices\MCXC444\arm\MK_P256_48MHZ_MCXC444.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MCXC444VLH$devices\MCXC444\fsl_device_registers.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MCXC444VLH$devices\MCXC444\MCXC444.xml</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>0</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <nBranchProt>0</nBranchProt>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1fffe000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x30060000</StartAddress>
+                <Size>0x8000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x1fffe000</StartAddress>
+                <Size>0x8000</Size>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
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+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
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+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>--target=arm-arm-none-eabi</MiscControls>
+              <Define>DEBUG, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC, CPU_MCXC444VLH, __STDC_LIMIT_MACROS</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\..\..\..\components\drivers\spi;applications;..\..\..\..\..\components\finsh;..\..\..\..\..\components\libc\posix\io\poll;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\posix\io\eventfd;..\Libraries\drivers\config;..\..\..\..\..\components\libc\compilers\common\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\Libraries\CMSIS\Core\Include;..\..\..\..\..\components\libc\posix\ipc;..\..\..\..\..\components\drivers\include;..\Libraries\drivers;..\..\..\..\..\libcpu\arm\common;..\Libraries\MCXC444\MCXC444;..\..\..\..\..\components\drivers\include;..\Libraries\MCXC444\MCXC444\drivers;..\..\..\..\..\libcpu\arm\cortex-m0;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\..\components\drivers\include;.;..\..\..\..\..\include;..\..\..\..\..\components\drivers\include;board\MCUX_Config\board;..\..\..\..\..\components\drivers\include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls>-x assembler-with-cpp</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x02000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\MCXC444_flash.scf</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Compiler</GroupName>
+          <Files>
+            <File>
+              <FileName>syscall_mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>syscalls.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
+            </File>
+            <File>
+              <FileName>cctype.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\common\cctype.c</FilePath>
+            </File>
+            <File>
+              <FileName>cstdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
+            </File>
+            <File>
+              <FileName>cstring.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\common\cstring.c</FilePath>
+            </File>
+            <File>
+              <FileName>ctime.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\common\ctime.c</FilePath>
+            </File>
+            <File>
+              <FileName>cunistd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\components\libc\compilers\common\cunistd.c</FilePath>
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+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_KERNEL_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>scheduler_comm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\src\scheduler_comm.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
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+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_KERNEL_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>scheduler_up.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\src\scheduler_up.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_KERNEL_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\src\thread.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_KERNEL_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\src\timer.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_KERNEL_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libcpu</GroupName>
+          <Files>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>fsl_common.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_common.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_ftfx_flexnvm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_ftfx_flexnvm.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_cmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_cmp.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_lpuart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_lpuart.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_i2c_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_i2c_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_dac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_dac.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_sai_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_sai_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_cop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_cop.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_lpuart_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_lpuart_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_tpm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_tpm.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_smc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_smc.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_MCXC444.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\system_MCXC444.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_pit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_pit.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_slcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_slcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_sai.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_sai.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_uart_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_uart_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_common_arm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_common_arm.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_MCXC444.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\arm\startup_MCXC444.s</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_sim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_sim.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_adc16.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_adc16.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_ftfx_controller.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_ftfx_controller.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_pmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_pmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Libraries\MCXC444\MCXC444\drivers\fsl_spi.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>template</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.h b/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.h
new file mode 100644
index 0000000000..f88b3e0975
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.h
@@ -0,0 +1,340 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+#define SOC_MCX
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+/* end of kservice optimization */
+
+/* klibc optimization */
+
+/* end of klibc optimization */
+#define RT_USING_DEBUG
+#define RT_DEBUGING_ASSERT
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+#define RT_USING_OVERFLOW_CHECK
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50200
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M0
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+/* end of DFS: device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
+#define RT_USING_PWM
+#define RT_USING_RTC
+#define RT_USING_SPI
+#define RT_USING_PIN
+#define RT_USING_HWTIMER
+/* end of Device Drivers */
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
+
+/* Network */
+
+/* end of Network */
+
+/* Memory protection */
+
+/* end of Memory protection */
+
+/* Utilities */
+
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* end of Marvell WiFi */
+
+/* Wiced WiFi */
+
+/* end of Wiced WiFi */
+
+/* CYW43012 WiFi */
+
+/* end of CYW43012 WiFi */
+
+/* BL808 WiFi */
+
+/* end of BL808 WiFi */
+
+/* CYW43439 WiFi */
+
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
+
+/* IoT Cloud */
+
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
+
+/* security packages */
+
+/* end of security packages */
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* XML: Extensible Markup Language */
+
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
+
+/* u8g2: a monochrome graphic library */
+
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
+
+/* tools packages */
+
+/* end of tools packages */
+
+/* system packages */
+
+/* enhanced kernel services */
+
+/* end of enhanced kernel services */
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
+
+/* Kendryte SDK */
+
+/* end of Kendryte SDK */
+/* end of HAL & SDK Drivers */
+
+/* sensors drivers */
+
+/* end of sensors drivers */
+
+/* touch drivers */
+
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
+
+/* AI packages */
+
+/* end of AI packages */
+
+/* Signal Processing and Control Algorithm Packages */
+
+/* end of Signal Processing and Control Algorithm Packages */
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* end of project laboratory */
+
+/* samples: kernel and components samples */
+
+/* end of samples: kernel and components samples */
+
+/* entertainment: terminal games and other interesting software packages */
+
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+/* end of Projects and Demos */
+
+/* Sensors */
+
+/* end of Sensors */
+
+/* Display */
+
+/* end of Display */
+
+/* Timing */
+
+/* end of Timing */
+
+/* Data Processing */
+
+/* end of Data Processing */
+
+/* Data Storage */
+
+/* Communication */
+
+/* end of Communication */
+
+/* Device Control */
+
+/* end of Device Control */
+
+/* Other */
+
+/* end of Other */
+
+/* Signal IO */
+
+/* end of Signal IO */
+
+/* Uncategorized */
+
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
+
+/* Hardware Drivers Config */
+
+#define SOC_MCXC444
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_PIN
+#define BSP_USING_UART
+#define BSP_USING_UART0
+/* end of On-chip Peripheral Drivers */
+/* end of Hardware Drivers Config */
+
+#endif
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.py b/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.py
new file mode 100644
index 0000000000..b86bc760dd
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/rtconfig.py
@@ -0,0 +1,198 @@
+import os
+import sys
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+BOARD_NAME = 'lpcxpresso'
+BSP_LIBRARY_TYPE = 'MCXC444'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armclang'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'C:\Program Files\IAR Systems\Embedded Workbench 9.1'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'arm-none-eabi-'
+    CC  = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS'
+    LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--defsym=__heap_size__=0x10000,--gc-sections,-Map=rtthread.map,--print-memory-usage -Tboard/linker_scripts/MCXC444_flash.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting 
+    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
+    CXXFLAGS += CFLAGS
+
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu ' + CPU + '.fp.sp'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/MCXC444_flash" '
+
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)' 
+
+    CFLAGS += ' --diag_suppress=66,1296,186,6134'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' --c99'
+
+    POST_ACTION = 'fromelf -z $TARGET'
+    # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'armclang':
+    # toolchains
+    CC = 'armclang'
+    CXX = 'armclang'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M0 '
+    CFLAGS = ' --target=arm-arm-none-eabi'
+    CFLAGS += ' -mcpu=' + CPU
+    CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
+    CFLAGS += ' -gdwarf-3 -ffunction-sections '
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
+    LFLAGS += ' --list rt-thread.map '
+    LFLAGS += r' --strict --scatter "board/linker_scripts/MCXC444_flash" '
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
+
+    EXEC_PATH += '/ARM/ARMCLANG/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O1' # armclang recommend
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+        
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' -D__FPU_PRESENT'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=' + CPU
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' -Ol'
+    CFLAGS += ' --use_c++_inline'
+
+    AFLAGS = ''
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu ' + CPU
+    AFLAGS += ' --fpu None'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/MCXC444_flash.icf"'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny'
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
+    
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvoptx b/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvoptx
new file mode 100644
index 0000000000..c8af17628b
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvoptx
@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread-frdm-mcxc444</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00000000 -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFFE000 -FC800 -FN1 -FF0MK_P256_48MHZ_MCXC444.FLM -FS00 -FL040000 -FP0($$Device:MCXC444VLH$devices\MCXC444\arm\MK_P256_48MHZ_MCXC444.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFFE000 -FC800 -FN1 -FF0MK_P256_48MHZ_MCXC444 -FS00 -FL040000 -FP0($$Device:MCXC444VLH$devices\MCXC444\arm\MK_P256_48MHZ_MCXC444.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFFE000 -FC800 -FN1 -FF0MK_P256_48MHZ_MCXC444 -FS00 -FL040000 -FP0($$Device:MCXC444VLH$devices\MCXC444\arm\MK_P256_48MHZ_MCXC444.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvprojx b/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvprojx
new file mode 100644
index 0000000000..23a4a40ec0
--- /dev/null
+++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/template.uvprojx
@@ -0,0 +1,401 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-frdm-mcxc444</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MCXC444VLH</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>NXP.MCXC444_DFP.17.0.0</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <Cpu>IRAM(0x1fffe000,0x8000) IROM(0x00000000,0x040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFE000 -FC800 -FN1 -FF0MK_P256_48MHZ_MCXC444 -FS00 -FL040000 -FP0($$Device:MCXC444VLH$devices\MCXC444\arm\MK_P256_48MHZ_MCXC444.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MCXC444VLH$devices\MCXC444\fsl_device_registers.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MCXC444VLH$devices\MCXC444\MCXC444.xml</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>0</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <nBranchProt>0</nBranchProt>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1fffe000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x30060000</StartAddress>
+                <Size>0x8000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fffe000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>--target=arm-arm-none-eabi</MiscControls>
+              <Define>RT_USING_ARM_LIBC</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls>-x assembler-with-cpp</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x02000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\MCXC444_flash.scf</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>template</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvoptx b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvoptx
index 8c8f6ed470..a3a94b1d9e 100644
--- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvoptx
+++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvoptx
@@ -73,11 +73,11 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
-      <CpuCode>0</CpuCode>
+      <CpuCode>8</CpuCode>
       <DebugOpt>
         <uSim>0</uSim>
         <uTrg>1</uTrg>
@@ -181,4 +181,1312 @@
     </TargetOption>
   </Target>
 
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Compiler</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
+      <FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
+      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\cctype.c</PathWithFileName>
+      <FilenameWithoutPath>cctype.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\cstdlib.c</PathWithFileName>
+      <FilenameWithoutPath>cstdlib.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\cstring.c</PathWithFileName>
+      <FilenameWithoutPath>cstring.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\ctime.c</PathWithFileName>
+      <FilenameWithoutPath>ctime.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\cunistd.c</PathWithFileName>
+      <FilenameWithoutPath>cunistd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\libc\compilers\common\cwchar.c</PathWithFileName>
+      <FilenameWithoutPath>cwchar.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>DeviceDrivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\core\device.c</PathWithFileName>
+      <FilenameWithoutPath>device.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\hwtimer\hwtimer.c</PathWithFileName>
+      <FilenameWithoutPath>hwtimer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\ipc\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\ipc\condvar.c</PathWithFileName>
+      <FilenameWithoutPath>condvar.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\ipc\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\drivers\ipc\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>16</FileNumber>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\utilities\ulog\ulog.c</PathWithFileName>
+      <FilenameWithoutPath>ulog.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>103</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\..\components\utilities\ulog\backend\console_be.c</PathWithFileName>
+      <FilenameWithoutPath>console_be.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
 </ProjectOpt>
diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx
index eb0a4e2380..e1e54cf371 100644
--- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx
+++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx
@@ -1,7 +1,10 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
   <SchemaVersion>2.1</SchemaVersion>
+
   <Header>### uVision Project, (C) Keil Software</Header>
+
   <Targets>
     <Target>
       <TargetName>rtthread-frdm-mcxn947</TargetName>
@@ -16,28 +19,28 @@
           <PackID>NXP.MCXN947_DFP.17.0.0</PackID>
           <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
           <Cpu>IRAM(0x20000000,0x060000) IRAM2(0x20060000,0x8000) IROM(0x03000000,0x040000) IROM2(0x13000000,0x040000) XRAM(0x30060000,0x8000) XRAM2(0x04000000,0x018000) XRAM3(0x14000000,0x018000) XROM(0x00000000,0x100000) XROM2(0x00100000,0x100000) XROM3(0x10000000,0x100000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec />
-          <StartupFile />
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
           <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048 -FS00 -FL0200000 -FF1MCXN9XX_2048_S -FS110000000 -FL1200000 -FF2MCXN9XX_W25Q64 -FS280000000 -FL2800000 -FF3MCXN9XX_W25Q64_S -FS390000000 -FL3800000 -FP0($$Device:MCXN947VDF$arm\MCXN9XX_2048.FLM) -FP1($$Device:MCXN947VDF$arm\MCXN9XX_2048_S.FLM) -FP2($$Device:MCXN947VDF$arm\MCXN9XX_W25Q64.FLM) -FP3($$Device:MCXN947VDF$arm\MCXN9XX_W25Q64_S.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
           <RegisterFile>$$Device:MCXN947VDF$fsl_device_registers.h</RegisterFile>
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile>$$Device:MCXN947VDF$MCXN947_cm33_core0.xml</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath />
-          <DBRegisterFilePath />
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -59,8 +62,8 @@
           <BeforeCompile>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopU1X>0</nStopU1X>
@@ -69,8 +72,8 @@
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopB1X>0</nStopB1X>
@@ -79,15 +82,15 @@
           <AfterMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
+          <SVCSIdString></SVCSIdString>
         </TargetCommonOption>
         <CommonProperty>
           <UseCPPCompiler>0</UseCPPCompiler>
@@ -101,15 +104,15 @@
           <AssembleAssemblyFile>0</AssembleAssemblyFile>
           <PublicsOnly>0</PublicsOnly>
           <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
-          <SimDllName />
-          <SimDllArguments />
-          <SimDlgDll />
-          <SimDlgDllArguments />
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
           <TargetDllName>SARMV8M.DLL</TargetDllName>
           <TargetDllArguments> -MPU</TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
@@ -136,10 +139,10 @@
           <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2V8M.DLL</Flash2>
           <Flash3>"" ()</Flash3>
-          <Flash4 />
-          <pFcarmOut />
-          <pFcarmGrp />
-          <pFcArmRoot />
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
           <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
@@ -172,7 +175,7 @@
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M33"</AdsCpuType>
-            <RvctDeviceName />
+            <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
             <uocRam>0</uocRam>
@@ -307,7 +310,7 @@
                 <Size>0x8000</Size>
               </OCR_RVCT10>
             </OnChipMemories>
-            <RvctStartVector />
+            <RvctStartVector></RvctStartVector>
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
@@ -336,7 +339,7 @@
             <VariousControls>
               <MiscControls>--target=arm-arm-none-eabi</MiscControls>
               <Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, CPU_MCXN947VDF_cm33_core0, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, DEBUG</Define>
-              <Undefine />
+              <Undefine></Undefine>
               <IncludePath>..\..\..\..\..\include;..\..\..\..\..\libcpu\arm\common;..\Libraries\drivers;..\..\..\..\..\libcpu\arm\cortex-m33;..\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\..\components\libc\posix\ipc;..\Libraries\MCXN947\middleware\sdmmc\inc;..\..\..\..\..\components\libc\posix\io\poll;.;..\..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\..\components\drivers\include;..\Libraries\MCXN947\MCXN947\drivers;board\MCUX_Config\board;..\..\..\..\..\components\drivers\include;..\Libraries\MCXN947\middleware\sdmmc\port;..\..\..\..\..\components\libc\compilers\common\include;..\..\..\..\..\components\drivers\include;..\..\..\..\..\components\finsh;..\..\..\..\..\components\utilities\ulog;..\Libraries\MCXN947\MCXN947;board;..\Libraries\CMSIS\Core\Include;..\..\..\..\..\components\libc\posix\io\eventfd;applications;..\..\..\..\..\components\drivers\include;..\Libraries\MCXN947\components\codec;..\Libraries\drivers\config;..\..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\..\components\drivers\include</IncludePath>
             </VariousControls>
           </Cads>
@@ -353,9 +356,9 @@
             <ClangAsOpt>1</ClangAsOpt>
             <VariousControls>
               <MiscControls>-x assembler-with-cpp</MiscControls>
-              <Define />
-              <Undefine />
-              <IncludePath />
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -367,13 +370,13 @@
             <useFile>0</useFile>
             <TextAddressRange>0x00000000</TextAddressRange>
             <DataAddressRange>0x02000000</DataAddressRange>
-            <pXoBase />
+            <pXoBase></pXoBase>
             <ScatterFile>.\board\linker_scripts\MCXN947_cm33_core0_flash.scf</ScatterFile>
-            <IncludeLibs />
-            <IncludeLibsPath />
-            <Misc />
-            <LinkerInputFile />
-            <DisabledWarnings />
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
@@ -396,50 +399,36 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>syscalls.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cctype.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\common\cctype.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstdlib.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstring.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\common\cstring.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ctime.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\common\ctime.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cunistd.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\libc\compilers\common\cunistd.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cwchar.c</FileName>
               <FileType>1</FileType>
@@ -455,222 +444,668 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\drivers\core\device.c</FilePath>
               <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
                 <FileArmAds>
                   <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
                     <VariousControls>
                       <MiscControls> </MiscControls>
                       <Define>__RT_IPC_SOURCE__</Define>
                       <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
+                      <IncludePath></IncludePath>
                     </VariousControls>
                   </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>hwtimer.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\drivers\hwtimer\hwtimer.c</FilePath>
               <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
                 <FileArmAds>
                   <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
                     <VariousControls>
                       <MiscControls> </MiscControls>
                       <Define>__RT_IPC_SOURCE__</Define>
                       <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
+                      <IncludePath></IncludePath>
                     </VariousControls>
                   </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>completion.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\drivers\ipc\completion.c</FilePath>
               <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
                 <FileArmAds>
                   <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
                     <VariousControls>
                       <MiscControls> </MiscControls>
                       <Define>__RT_IPC_SOURCE__</Define>
                       <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
+                      <IncludePath></IncludePath>
                     </VariousControls>
                   </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>condvar.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\drivers\ipc\condvar.c</FilePath>
               <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
                 <FileArmAds>
                   <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
                     <VariousControls>
                       <MiscControls> </MiscControls>
                       <Define>__RT_IPC_SOURCE__</Define>
                       <Undefine> </Undefine>
-                      <IncludePath> </IncludePath>
+                      <IncludePath></IncludePath>
                     </VariousControls>
                   </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
               <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
                 <FileArmAds>
                   <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
                     <VariousControls>
                       <MiscControls> </MiscControls>
                       <Define>__RT_IPC_SOURCE__</Define>
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@@ -1095,337 +2061,241 @@
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