diff options
| author | Kai <[email protected]> | 2026-11-09 11:12:48 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-11-09 11:12:48 +0800 |
| commit | 95e82ec2e44ac646d58d92107844ade49ff5a93c (patch) | |
| tree | a3aceeff0f9c9d65db66eaf8a1ca2b49967b9b5d | |
| parent | 22293ce3329c914a5dbfe56c0703d9d89f4a3f1b (diff) | |
27 files changed, 1080 insertions, 1417 deletions
diff --git a/bsp/wch/risc-v/ch32v103r-evt/.config b/bsp/wch/risc-v/ch32v103r-evt/.config index 3fc8c6c211..d292fe0858 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/.config +++ b/bsp/wch/risc-v/ch32v103r-evt/.config @@ -1426,6 +1426,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V1=y +CONFIG_WCH_QINGKE_V3A=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h index 4b2a1fef21..6ab765ee4c 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h +++ b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h @@ -61,19 +61,19 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -101,10 +101,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -115,12 +115,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 1024 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -153,17 +153,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -195,7 +193,6 @@ /* IoT - internet of things */ - /* Wi-Fi */ /* Marvell WiFi */ @@ -356,7 +353,6 @@ /* Arduino libraries */ - /* Projects and Demos */ /* end of Projects and Demos */ @@ -401,6 +397,7 @@ /* end of RT-Thread online packages */ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V1 +#define WCH_QINGKE_V3A /* Hardware Drivers Config */ diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/.config b/bsp/wch/risc-v/ch32v203c-evt-r0/.config index 70fc119400..0a9e081227 100644 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/.config +++ b/bsp/wch/risc-v/ch32v203c-evt-r0/.config @@ -368,13 +368,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_PKG_USING_CH32V20x_SDK=y CONFIG_PKG_CH32V20x_SDK_PATH="/packages/peripherals/hal-sdk/wch/ch32v20x_sdk" # CONFIG_PKG_USING_CH32V20x_SDK_V202 is not set -CONFIG_PKG_USING_CH32V20x_SDK_LATEST_VERSION=y -CONFIG_PKG_CH32V20x_SDK_VER="latest" +CONFIG_PKG_USING_CH32V20x_SDK_V205=y +# CONFIG_PKG_USING_CH32V20x_SDK_LATEST_VERSION is not set +CONFIG_PKG_CH32V20x_SDK_VER="v2.5" # end of WCH HAL & SDK Drivers CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V2=y CONFIG_SOC_RISCV_SERIES_CH32V20x_D6=y +CONFIG_WCH_QINGKE_V4B=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/README.md b/bsp/wch/risc-v/ch32v203c-evt-r0/README.md index b10e55d567..0841206dca 100644 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/README.md +++ b/bsp/wch/risc-v/ch32v203c-evt-r0/README.md @@ -30,7 +30,7 @@ CH32V203C8T6-EVT-R0 是 WCH 推出的一款基于 RISC-V 内核的开发板，� 1. [下载 WCH 编译工具链](https://github.com/NanjingQinheng/sdk-toolchain-RISC-V-GCC-WCH) 2. 下载 Env 工具 [最新版本](https://github.com/RT-Thread/env-windows/releases) -3. 将 [CH32V20x-SDK-for-RTT](https://github.com/kaidegit/CH32V20x-SDK-for-RTT) clone 到 `packages/CH32V20x-SDK-for-RTT` +3. 在当前 BSP 目录下执行 `pkgs --update`，下载配置中指定的 CH32V20x SDK v2.5 4. 在当前 BSP 目录下执行 `scons --exec-path=工具链的bin目录` 5. 编译完成之后会生成 **rtthread.bin** 文件。默认只打开 GPIO 和 UART1。 diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/SConstruct b/bsp/wch/risc-v/ch32v203c-evt-r0/SConstruct index 316efd6cc5..d39bf6576e 100644 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/SConstruct +++ b/bsp/wch/risc-v/ch32v203c-evt-r0/SConstruct @@ -46,41 +46,6 @@ else: SDK_LIB = libraries_path_prefix Export('SDK_LIB') -def _allow_ch32v20x_d6_in_sdk_package(): - """Official CH32V20x-SDK-for-RTT ships a D8W startup file and Exit()s on D6. - CH32V203C8T6 is D6. Keep the SDK peripherals and use board/startup_ch32v20x_D6.S. - Only that package is edited, and only while Exit() is still present, so a - D8W tree or an already patched file is left untouched. - """ - import re - candidates = [ - os.path.join(SDK_ROOT, 'packages', 'CH32V20x-SDK-for-RTT', 'SConscript'), - os.path.join(libraries_path_prefix, 'ch32v20x_sdk-latest', 'SConscript'), - ] - for sc in candidates: - if not os.path.isfile(sc): - continue - with open(sc, 'r', encoding='utf-8') as f: - text = f.read() - if 'Exit()' not in text or 'SOC_RISCV_SERIES_CH32V20x_D6' not in text: - continue - if not re.search(r'^import os\b', text, re.M): - text = 'import os\n' + text - patched, n = re.subn( - r"if GetDepend\(\['SOC_RISCV_SERIES_CH32V20x_D6'\]\):.*?\n Exit\(\)\n", - "if GetDepend(['SOC_RISCV_SERIES_CH32V20x_D6']):\n" - " CPPDEFINES.append(\"CH32V20x_D6\")\n", - text, - count=1, - flags=re.S, - ) - if n == 0 or patched == text: - continue - with open(sc, 'w', encoding='utf-8', newline='\n') as f: - f.write(patched) - -_allow_ch32v20x_d6_in_sdk_package() - # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/board/SConscript b/bsp/wch/risc-v/ch32v203c-evt-r0/board/SConscript index aa6c728dd3..ea54a3a737 100644 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/board/SConscript +++ b/bsp/wch/risc-v/ch32v203c-evt-r0/board/SConscript @@ -10,7 +10,6 @@ cwd = GetCurrentDir() src = Split(''' board.c software_irq.c -startup_ch32v20x_D6.S ''') path = [cwd] diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/board/startup_ch32v20x_D6.S b/bsp/wch/risc-v/ch32v203c-evt-r0/board/startup_ch32v20x_D6.S deleted file mode 100644 index f7dc334da6..0000000000 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/board/startup_ch32v20x_D6.S +++ /dev/null @@ -1,258 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : startup_ch32v20x_D6.S -* Author : WCH -* Version : V1.0.2 -* Date : 2025/10/21 -* Description : CH32V203C8T6 (D6) vector table from WCH EVT. -* handle_reset jumps to RT-Thread entry, same as -* CH32V20x-SDK-for-RTT D8W rtt-patch (not bare-metal main). -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ - - .section .init,"ax",@progbits - .global _start - .align 1 -_start: - j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 - - .section .vector,"ax",@progbits - .align 1 -_vector_base: - .option norvc; - .word _start - .word 0 - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word Ecall_M_Mode_Handler - .word 0 - .word 0 - .word Ecall_U_Mode_Handler - .word Break_Point_Handler - .word 0 - .word 0 - .word SysTick_Handler - .word 0 - .word SW_handler /* libcpu symbol; SW_Handler would be a different infinite loop */ - .word 0 - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word USBFS_IRQHandler - .word USBFSWakeUp_IRQHandler - .word UART4_IRQHandler - .word DMA1_Channel8_IRQHandler - - .option rvc; - .section .text.vector_handler, "ax", @progbits - .weak NMI_Handler - .weak HardFault_Handler - .weak Ecall_M_Mode_Handler - .weak Ecall_U_Mode_Handler - .weak Break_Point_Handler - .weak SysTick_Handler - .weak SW_handler - .weak WWDG_IRQHandler - .weak PVD_IRQHandler - .weak TAMPER_IRQHandler - .weak RTC_IRQHandler - .weak FLASH_IRQHandler - .weak RCC_IRQHandler - .weak EXTI0_IRQHandler - .weak EXTI1_IRQHandler - .weak EXTI2_IRQHandler - .weak EXTI3_IRQHandler - .weak EXTI4_IRQHandler - .weak DMA1_Channel1_IRQHandler - .weak DMA1_Channel2_IRQHandler - .weak DMA1_Channel3_IRQHandler - .weak DMA1_Channel4_IRQHandler - .weak DMA1_Channel5_IRQHandler - .weak DMA1_Channel6_IRQHandler - .weak DMA1_Channel7_IRQHandler - .weak ADC1_2_IRQHandler - .weak USB_HP_CAN1_TX_IRQHandler - .weak USB_LP_CAN1_RX0_IRQHandler - .weak CAN1_RX1_IRQHandler - .weak CAN1_SCE_IRQHandler - .weak EXTI9_5_IRQHandler - .weak TIM1_BRK_IRQHandler - .weak TIM1_UP_IRQHandler - .weak TIM1_TRG_COM_IRQHandler - .weak TIM1_CC_IRQHandler - .weak TIM2_IRQHandler - .weak TIM3_IRQHandler - .weak TIM4_IRQHandler - .weak I2C1_EV_IRQHandler - .weak I2C1_ER_IRQHandler - .weak I2C2_EV_IRQHandler - .weak I2C2_ER_IRQHandler - .weak SPI1_IRQHandler - .weak SPI2_IRQHandler - .weak USART1_IRQHandler - .weak USART2_IRQHandler - .weak USART3_IRQHandler - .weak EXTI15_10_IRQHandler - .weak RTCAlarm_IRQHandler - .weak USBWakeUp_IRQHandler - .weak USBFS_IRQHandler - .weak USBFSWakeUp_IRQHandler - .weak UART4_IRQHandler - .weak DMA1_Channel8_IRQHandler - -NMI_Handler: -HardFault_Handler: -Ecall_M_Mode_Handler: -Ecall_U_Mode_Handler: -Break_Point_Handler: -SysTick_Handler: -SW_handler: -WWDG_IRQHandler: -PVD_IRQHandler: -TAMPER_IRQHandler: -RTC_IRQHandler: -FLASH_IRQHandler: -RCC_IRQHandler: -EXTI0_IRQHandler: -EXTI1_IRQHandler: -EXTI2_IRQHandler: -EXTI3_IRQHandler: -EXTI4_IRQHandler: -DMA1_Channel1_IRQHandler: -DMA1_Channel2_IRQHandler: -DMA1_Channel3_IRQHandler: -DMA1_Channel4_IRQHandler: -DMA1_Channel5_IRQHandler: -DMA1_Channel6_IRQHandler: -DMA1_Channel7_IRQHandler: -ADC1_2_IRQHandler: -USB_HP_CAN1_TX_IRQHandler: -USB_LP_CAN1_RX0_IRQHandler: -CAN1_RX1_IRQHandler: -CAN1_SCE_IRQHandler: -EXTI9_5_IRQHandler: -TIM1_BRK_IRQHandler: -TIM1_UP_IRQHandler: -TIM1_TRG_COM_IRQHandler: -TIM1_CC_IRQHandler: -TIM2_IRQHandler: -TIM3_IRQHandler: -TIM4_IRQHandler: -I2C1_EV_IRQHandler: -I2C1_ER_IRQHandler: -I2C2_EV_IRQHandler: -I2C2_ER_IRQHandler: -SPI1_IRQHandler: -SPI2_IRQHandler: -USART1_IRQHandler: -USART2_IRQHandler: -USART3_IRQHandler: -EXTI15_10_IRQHandler: -RTCAlarm_IRQHandler: -USBWakeUp_IRQHandler: -USBFS_IRQHandler: -USBFSWakeUp_IRQHandler: -UART4_IRQHandler: -DMA1_Channel8_IRQHandler: -1: - j 1b - - .section .text.handle_reset,"ax",@progbits - .weak handle_reset - .align 1 -handle_reset: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la sp, _eusrstack - - la a0, _data_lma - la a1, _data_vma - la a2, _edata - bgeu a1, a2, 2f -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b -2: - la a0, _sbss - la a1, _ebss - bgeu a0, a1, 2f -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b -2: - li t0, 0x1f - csrw 0xbc0, t0 - - li t0, 0x2 - csrw 0x804, t0 - - li t0, 0x1800 - csrw mstatus, t0 - - la t0, _vector_base - ori t0, t0, 3 - csrw mtvec, t0 - - jal SystemInit - la t0, entry - csrw mepc, t0 - mret diff --git a/bsp/wch/risc-v/ch32v203c-evt-r0/rtconfig.h b/bsp/wch/risc-v/ch32v203c-evt-r0/rtconfig.h index 39dcf31162..4fe0ad79f2 100644 --- a/bsp/wch/risc-v/ch32v203c-evt-r0/rtconfig.h +++ b/bsp/wch/risc-v/ch32v203c-evt-r0/rtconfig.h @@ -61,19 +61,19 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -101,10 +101,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50301 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -115,12 +115,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 1024 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -152,17 +152,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -193,11 +191,12 @@ /* WCH HAL & SDK Drivers */ #define PKG_USING_CH32V20x_SDK -#define PKG_USING_CH32V20x_SDK_LATEST_VERSION +#define PKG_USING_CH32V20x_SDK_V205 /* end of WCH HAL & SDK Drivers */ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V2 #define SOC_RISCV_SERIES_CH32V20x_D6 +#define WCH_QINGKE_V4B /* Hardware Drivers Config */ diff --git a/bsp/wch/risc-v/ch32v208w-r0/.config b/bsp/wch/risc-v/ch32v208w-r0/.config index 01fe52c444..00aa448946 100644 --- a/bsp/wch/risc-v/ch32v208w-r0/.config +++ b/bsp/wch/risc-v/ch32v208w-r0/.config @@ -829,8 +829,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_PKG_USING_CH32V20x_SDK=y CONFIG_PKG_CH32V20x_SDK_PATH="/packages/peripherals/hal-sdk/wch/ch32v20x_sdk" # CONFIG_PKG_USING_CH32V20x_SDK_V202 is not set -CONFIG_PKG_USING_CH32V20x_SDK_LATEST_VERSION=y -CONFIG_PKG_CH32V20x_SDK_VER="latest" +CONFIG_PKG_USING_CH32V20x_SDK_V205=y +# CONFIG_PKG_USING_CH32V20x_SDK_LATEST_VERSION is not set +CONFIG_PKG_CH32V20x_SDK_VER="v2.5" # CONFIG_PKG_USING_CH32V307_SDK is not set # end of WCH HAL & SDK Drivers @@ -1437,6 +1438,7 @@ CONFIG_PKG_CH32V20x_SDK_VER="latest" CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V2=y CONFIG_SOC_RISCV_SERIES_CH32V20x_D8W=y +CONFIG_WCH_QINGKE_V4C=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h index 51e9b0b875..67f0a123fd 100644 --- a/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h +++ b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h @@ -61,19 +61,19 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -101,10 +101,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -115,12 +115,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 2048 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -158,17 +158,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -200,7 +198,6 @@ /* IoT - internet of things */ - /* Wi-Fi */ /* Marvell WiFi */ @@ -297,7 +294,7 @@ /* WCH HAL & SDK Drivers */ #define PKG_USING_CH32V20x_SDK -#define PKG_USING_CH32V20x_SDK_LATEST_VERSION +#define PKG_USING_CH32V20x_SDK_V205 /* end of WCH HAL & SDK Drivers */ /* AT32 HAL & SDK Drivers */ @@ -363,7 +360,6 @@ /* Arduino libraries */ - /* Projects and Demos */ /* end of Projects and Demos */ @@ -409,6 +405,7 @@ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V2 #define SOC_RISCV_SERIES_CH32V20x_D8W +#define WCH_QINGKE_V4C /* Hardware Drivers Config */ diff --git a/bsp/wch/risc-v/ch32v307v-r1/.config b/bsp/wch/risc-v/ch32v307v-r1/.config index e7b3853c5d..5b16292af0 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/.config +++ b/bsp/wch/risc-v/ch32v307v-r1/.config @@ -823,9 +823,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CH32V20x_SDK is not set CONFIG_PKG_USING_CH32V307_SDK=y CONFIG_PKG_CH32V307_SDK_PATH="/packages/peripherals/hal-sdk/wch/ch32v307_sdk" -CONFIG_PKG_USING_CH32V307_SDK_V207=y +# CONFIG_PKG_USING_CH32V307_SDK_V207 is not set +CONFIG_PKG_USING_CH32V307_SDK_V302=y # CONFIG_PKG_USING_CH32V307_SDK_LATEST_VERSION is not set -CONFIG_PKG_CH32V307_SDK_VER="v2.7" +CONFIG_PKG_CH32V307_SDK_VER="v3.2" # end of WCH HAL & SDK Drivers # @@ -1430,6 +1431,9 @@ CONFIG_PKG_CH32V307_SDK_VER="v2.7" CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V3=y +CONFIG_WCH_QINGKE_V4F=y +CONFIG_WCH_HAS_FAST_IRQ=y +CONFIG_WCH_USING_FAST_IRQ=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/board.c b/bsp/wch/risc-v/ch32v307v-r1/board/board.c index 3f949af488..d70fa59061 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/board/board.c +++ b/bsp/wch/risc-v/ch32v307v-r1/board/board.c @@ -9,6 +9,7 @@ */ #include "board.h" +#include <drv_common.h> #include <stdint.h> #include "drv_usart.h" #include "drv_gpio.h" @@ -40,7 +41,7 @@ void rt_hw_board_init() _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); #if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) - rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif /* USART driver initialization is open by default */ #ifdef RT_USING_SERIAL @@ -57,10 +58,9 @@ void rt_hw_board_init() #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - } -void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void SysTick_Handler(void) WCH_IRQ_ATTR; void SysTick_Handler(void) { GET_INT_SP(); @@ -71,5 +71,4 @@ void SysTick_Handler(void) /* leave interrupt */ rt_interrupt_leave(); FREE_INT_SP(); - } diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h index 106f3443d9..7d0ea1fa50 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h +++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h @@ -61,19 +61,19 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -101,10 +101,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -115,12 +115,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 11 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 11 #define FINSH_THREAD_STACK_SIZE 2048 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -153,17 +153,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -195,7 +193,6 @@ /* IoT - internet of things */ - /* Wi-Fi */ /* Marvell WiFi */ @@ -292,7 +289,7 @@ /* WCH HAL & SDK Drivers */ #define PKG_USING_CH32V307_SDK -#define PKG_USING_CH32V307_SDK_V207 +#define PKG_USING_CH32V307_SDK_V302 /* end of WCH HAL & SDK Drivers */ /* AT32 HAL & SDK Drivers */ @@ -358,7 +355,6 @@ /* Arduino libraries */ - /* Projects and Demos */ /* end of Projects and Demos */ @@ -403,6 +399,9 @@ /* end of RT-Thread online packages */ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V3 +#define WCH_QINGKE_V4F +#define WCH_HAS_FAST_IRQ +#define WCH_USING_FAST_IRQ /* Hardware Drivers Config */ @@ -419,7 +418,7 @@ #define BSP_USING_UART1 #define BSP_UART1_RX_BUFSIZE 256 #define BSP_UART1_TX_BUFSIZE 0 -#define LSI_VALUE 40000 +#define LSI_VALUE 40000 /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ diff --git a/bsp/wch/risc-v/ch569w-evt/.config b/bsp/wch/risc-v/ch569w-evt/.config index 399a32397c..fb328c02bf 100644 --- a/bsp/wch/risc-v/ch569w-evt/.config +++ b/bsp/wch/risc-v/ch569w-evt/.config @@ -1423,6 +1423,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_SOC_FAMILY_CH56X=y CONFIG_SOC_SERIES_CH569=y +CONFIG_WCH_QINGKE_V3A=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch569w-evt/rtconfig.h b/bsp/wch/risc-v/ch569w-evt/rtconfig.h index 69d4472795..900bc1048a 100644 --- a/bsp/wch/risc-v/ch569w-evt/rtconfig.h +++ b/bsp/wch/risc-v/ch569w-evt/rtconfig.h @@ -61,12 +61,12 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 200 +#define RT_TICK_PER_SECOND 200 #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -100,10 +100,10 @@ #define RT_USING_DEVICE #define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -114,12 +114,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 1024 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -152,17 +152,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -194,7 +192,6 @@ /* IoT - internet of things */ - /* Wi-Fi */ /* Marvell WiFi */ @@ -355,7 +352,6 @@ /* Arduino libraries */ - /* Projects and Demos */ /* end of Projects and Demos */ @@ -400,6 +396,7 @@ /* end of RT-Thread online packages */ #define SOC_FAMILY_CH56X #define SOC_SERIES_CH569 +#define WCH_QINGKE_V3A /* Hardware Drivers Config */ diff --git a/bsp/wch/risc-v/libraries/Kconfig b/bsp/wch/risc-v/libraries/Kconfig index 16c67cdbbb..e276ddd8ae 100644 --- a/bsp/wch/risc-v/libraries/Kconfig +++ b/bsp/wch/risc-v/libraries/Kconfig @@ -6,6 +6,7 @@ config SOC_RISCV_SERIES_CH32V1 select ARCH_RISCV select SOC_RISCV_FAMILY_CH32 select RT_USING_HW_ATOMIC + select WCH_QINGKE_V3A config SOC_RISCV_SERIES_CH32V2 bool @@ -16,12 +17,15 @@ config SOC_RISCV_SERIES_CH32V2 config SOC_RISCV_SERIES_CH32V20x_D6 bool + select WCH_QINGKE_V4B config SOC_RISCV_SERIES_CH32V20x_D8 bool + select WCH_QINGKE_V4B config SOC_RISCV_SERIES_CH32V20x_D8W bool + select WCH_QINGKE_V4C config SOC_RISCV_SERIES_CH32V3 bool @@ -29,6 +33,7 @@ config SOC_RISCV_SERIES_CH32V3 select SOC_RISCV_FAMILY_CH32 select RT_USING_HW_ATOMIC select PKG_USING_CH32V307_SDK + select WCH_QINGKE_V4F config SOC_FAMILY_CH56X bool @@ -39,3 +44,26 @@ config SOC_SERIES_CH569 bool select SOC_FAMILY_CH56X select RT_USING_HW_ATOMIC + select WCH_QINGKE_V3A + +config WCH_QINGKE_V3A + bool + +config WCH_QINGKE_V4B + bool + +config WCH_QINGKE_V4C + bool + +config WCH_QINGKE_V4F + bool + +config WCH_HAS_FAST_IRQ + bool + # Allow cores with at least three hardware stack levels. + default y if WCH_QINGKE_V4F || WCH_QINGKE_V5F + +config WCH_USING_FAST_IRQ + bool "Enable WCH fast interrupts" + depends on WCH_HAS_FAST_IRQ + default y diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_can.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_can.c index 1847d584c2..3a1829de74 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_can.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_can.c @@ -9,6 +9,7 @@ */ #include <stdint.h> #include <board.h> +#include "drv_common.h" #include <rtdevice.h> #include "drv_can.h" #ifdef BSP_USING_CAN @@ -20,39 +21,39 @@ //兼容老版的can宏定义 #ifndef RT_CAN_MODE_LISTEN -#define RT_CAN_MODE_LISTEN RT_CAN_MODE_LISEN +#define RT_CAN_MODE_LISTEN RT_CAN_MODE_LISEN #endif #ifndef RT_CAN_MODE_LOOPBACKANLISTEN -#define RT_CAN_MODE_LOOPBACKANLISTEN RT_CAN_MODE_LOOPBACKANLISEN +#define RT_CAN_MODE_LOOPBACKANLISTEN RT_CAN_MODE_LOOPBACKANLISEN #endif struct ch32v307x_can_baud_info { rt_uint32_t baud_rate; rt_uint16_t prescaler; - rt_uint8_t tsjw; //CAN synchronisation jump width. - rt_uint8_t tbs1; //CAN time quantum in bit segment 1. - rt_uint8_t tbs2; //CAN time quantum in bit segment 2. - rt_uint8_t notused; + rt_uint8_t tsjw; //CAN synchronisation jump width. + rt_uint8_t tbs1; //CAN time quantum in bit segment 1. + rt_uint8_t tbs2; //CAN time quantum in bit segment 2. + rt_uint8_t notused; }; #define CH32V307X_CAN_BAUD_DEF(xrate, xsjw, xbs1, xbs2, xprescale) \ - { \ - .baud_rate = xrate, \ - .tsjw = xsjw, \ - .tbs1 = xbs1, \ - .tbs2 = xbs2, \ - .prescaler = xprescale \ + { \ + .baud_rate = xrate, \ + .tsjw = xsjw, \ + .tbs1 = xbs1, \ + .tbs2 = xbs2, \ + .prescaler = xprescale \ } /* CH32V307X can device object */ struct ch32v307x_can_obj { - char * name; - CAN_TypeDef * can_base; - CAN_InitTypeDef can_init; - CAN_FilterInitTypeDef can_filter_init; - struct rt_can_device device; /* inherit from can device */ + char *name; + CAN_TypeDef *can_base; + CAN_InitTypeDef can_init; + CAN_FilterInitTypeDef can_filter_init; + struct rt_can_device device; /* inherit from can device */ }; /* @@ -69,31 +70,28 @@ struct ch32v307x_can_obj * sample = 75% at baud > 800K */ #if defined(CH32V30x_D8C) /* APB1 (PCLK1 72MHz) */ -static const struct ch32v307x_can_baud_info can_baud_rate_tab[] = -{ - CH32V307X_CAN_BAUD_DEF( CAN1MBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 4), +static const struct ch32v307x_can_baud_info can_baud_rate_tab[] = { + CH32V307X_CAN_BAUD_DEF(CAN1MBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 4), CH32V307X_CAN_BAUD_DEF(CAN800kBaud, CAN_SJW_1tq, CAN_BS1_12tq, CAN_BS2_2tq, 6), CH32V307X_CAN_BAUD_DEF(CAN500kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 8), CH32V307X_CAN_BAUD_DEF(CAN250kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 16), CH32V307X_CAN_BAUD_DEF(CAN125kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 32), CH32V307X_CAN_BAUD_DEF(CAN100kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 40), - CH32V307X_CAN_BAUD_DEF( CAN50kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 80), - CH32V307X_CAN_BAUD_DEF( CAN20kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 200), - CH32V307X_CAN_BAUD_DEF( CAN10kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 400), + CH32V307X_CAN_BAUD_DEF(CAN50kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 80), + CH32V307X_CAN_BAUD_DEF(CAN20kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 200), + CH32V307X_CAN_BAUD_DEF(CAN10kBaud, CAN_SJW_1tq, CAN_BS1_15tq, CAN_BS2_2tq, 400), }; #endif #ifdef BSP_USING_CAN1 -static struct ch32v307x_can_obj drv_can1 = -{ +static struct ch32v307x_can_obj drv_can1 = { .name = "can1", .can_base = CAN1, }; #endif #ifdef BSP_USING_CAN2 -static struct ch32v307x_can_obj drv_can2 = -{ +static struct ch32v307x_can_obj drv_can2 = { .name = "can2", .can_base = CAN2, }; @@ -102,21 +100,21 @@ static struct ch32v307x_can_obj drv_can2 = #ifdef BSP_USING_CAN rt_weak void ch32v307x_can_gpio_init(CAN_TypeDef *can_base) { - GPIO_InitTypeDef GPIO_InitSturcture={0}; + GPIO_InitTypeDef GPIO_InitSturcture = { 0 }; #ifdef BSP_USING_CAN1 if (CAN1 == can_base) { - RCC_APB2PeriphClockCmd( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE ); - RCC_APB1PeriphClockCmd( RCC_APB1Periph_CAN1, ENABLE ); - GPIO_PinRemapConfig( GPIO_Remap1_CAN1, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); + GPIO_PinRemapConfig(GPIO_Remap1_CAN1, ENABLE); // CAN1 TXD --> PB9 CAN1 RXD --> PB8 GPIO_InitSturcture.GPIO_Pin = GPIO_Pin_9; GPIO_InitSturcture.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitSturcture.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init( GPIOB, &GPIO_InitSturcture); + GPIO_Init(GPIOB, &GPIO_InitSturcture); GPIO_InitSturcture.GPIO_Pin = GPIO_Pin_8; GPIO_InitSturcture.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init( GPIOB, &GPIO_InitSturcture); + GPIO_Init(GPIOB, &GPIO_InitSturcture); /* RCC_APB2PeriphClockCmd( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE ); RCC_APB1PeriphClockCmd( RCC_APB1Periph_CAN1, ENABLE ); @@ -135,16 +133,16 @@ rt_weak void ch32v307x_can_gpio_init(CAN_TypeDef *can_base) #ifdef BSP_USING_CAN2 if (CAN2 == can_base) { - RCC_APB2PeriphClockCmd( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE ); - RCC_APB1PeriphClockCmd( RCC_APB1Periph_CAN2, ENABLE ); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); // CAN2 TXD --> PB13 CAN2 RXD --> PB12 GPIO_InitSturcture.GPIO_Pin = GPIO_Pin_13; GPIO_InitSturcture.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitSturcture.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init( GPIOB, &GPIO_InitSturcture); + GPIO_Init(GPIOB, &GPIO_InitSturcture); GPIO_InitSturcture.GPIO_Pin = GPIO_Pin_12; GPIO_InitSturcture.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init( GPIOB, &GPIO_InitSturcture); + GPIO_Init(GPIOB, &GPIO_InitSturcture); /* RCC_APB2PeriphClockCmd( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE ); RCC_APB1PeriphClockCmd( RCC_APB1Periph_CAN2, ENABLE ); @@ -171,7 +169,9 @@ static uint32_t get_can_baud_index(rt_uint32_t baud) for (index = 0; index < len; index++) { if (can_baud_rate_tab[index].baud_rate == baud) + { return index; + } } return 0; /* default baud is CAN1MBaud */ } @@ -201,11 +201,11 @@ static rt_err_t _can_filter_config(struct ch32v307x_can_obj *drv_can_obj) { if (drv_can_obj->can_base == CAN1) { - CAN_FilterInit( &(drv_can_obj->can_filter_init) ); + CAN_FilterInit(&(drv_can_obj->can_filter_init)); } else if (drv_can_obj->can_base == CAN2) { - CAN_FilterInit( &(drv_can_obj->can_filter_init) ); + CAN_FilterInit(&(drv_can_obj->can_filter_init)); } else { @@ -215,7 +215,6 @@ static rt_err_t _can_filter_config(struct ch32v307x_can_obj *drv_can_obj) return RT_EOK; } - static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg) { struct ch32v307x_can_obj *drv_can_obj; @@ -261,18 +260,18 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg drv_can_obj->can_init.CAN_BS2 = can_baud_rate_tab[baud_index].tbs2; drv_can_obj->can_init.CAN_Prescaler = can_baud_rate_tab[baud_index].prescaler; /* init can */ - if (CAN_Init( drv_can_obj->can_base, &(drv_can_obj->can_init) ) != CAN_InitStatus_Success ) + if (CAN_Init(drv_can_obj->can_base, &(drv_can_obj->can_init)) != CAN_InitStatus_Success) { LOG_E("can init error"); return -RT_ERROR; } - smaple = (can_baud_rate_tab[baud_index].tsjw + can_baud_rate_tab[baud_index].tbs1)*100 * 100 ; + smaple = (can_baud_rate_tab[baud_index].tsjw + can_baud_rate_tab[baud_index].tbs1) * 100 * 100; smaple = smaple / (can_baud_rate_tab[baud_index].tsjw + can_baud_rate_tab[baud_index].tbs1 + can_baud_rate_tab[baud_index].tbs2); LOG_D("can[%08X] init baud:%d sjw:%d tbs1:%d tbs2:%d prescaler:%d sample:%d.%d", - drv_can_obj->can_base, cfg->baud_rate, - can_baud_rate_tab[baud_index].tsjw, can_baud_rate_tab[baud_index].tbs1, can_baud_rate_tab[baud_index].tbs2, - can_baud_rate_tab[baud_index].prescaler , smaple/100, smaple%100); + drv_can_obj->can_base, cfg->baud_rate, + can_baud_rate_tab[baud_index].tsjw, can_baud_rate_tab[baud_index].tbs1, can_baud_rate_tab[baud_index].tbs2, + can_baud_rate_tab[baud_index].prescaler, smaple / 100, smaple % 100); /* default filter config */ _can_filter_config(drv_can_obj); @@ -305,18 +304,18 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) NVIC_DisableIRQ(CAN2_RX0_IRQn); NVIC_DisableIRQ(CAN2_RX1_IRQn); } -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP0 ); -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF0 ); -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV0 ); -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP1 ); -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF1 ); -// CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV1 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP0 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF0 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV0 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP1 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF1 ); + // CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV1 ); CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FMP0, DISABLE); /* FIFO 0 message pending Interrupt*/ - CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF0, DISABLE); /* FIFO 0 full Interrupt*/ + CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF0, DISABLE); /* FIFO 0 full Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FOV0, DISABLE); /* FIFO 0 overrun Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FMP1, DISABLE); /* FIFO 1 message pending Interrupt*/ - CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF1, DISABLE); /* FIFO 1 full Interrupt*/ + CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF1, DISABLE); /* FIFO 1 full Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FOV1, DISABLE); /* FIFO 1 overrun Interrupt*/ } else if (argval == RT_DEVICE_FLAG_INT_TX) @@ -341,11 +340,11 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { NVIC_DisableIRQ(CAN2_SCE_IRQn); } - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_EWG ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_EPV ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_BOF ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_LEC ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_ERR ); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_EWG); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_EPV); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_BOF); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_LEC); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_ERR); CAN_ITConfig(drv_can_obj->can_base, CAN_IT_EWG, DISABLE); /*!< Error warning Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_EPV, DISABLE); /*!< Error passive Interrupt*/ @@ -358,18 +357,18 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) argval = (rt_uint32_t)arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP0 ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF0 ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV0 ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FMP1 ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FF1 ); - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_FOV1 ); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FMP0); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FF0); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FOV0); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FMP1); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FF1); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_FOV1); CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FMP0, ENABLE); /* FIFO 0 message pending Interrupt*/ - CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF0, ENABLE); /* FIFO 0 full Interrupt*/ + CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF0, ENABLE); /* FIFO 0 full Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FOV0, ENABLE); /* FIFO 0 overrun Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FMP1, ENABLE); /* FIFO 1 message pending Interrupt*/ - CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF1, ENABLE); /* FIFO 1 full Interrupt*/ + CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FF1, ENABLE); /* FIFO 1 full Interrupt*/ CAN_ITConfig(drv_can_obj->can_base, CAN_IT_FOV1, ENABLE); /* FIFO 1 overrun Interrupt*/ if (CAN1 == drv_can_obj->can_base) @@ -389,7 +388,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) } else if (argval == RT_DEVICE_FLAG_INT_TX) { - CAN_ClearITPendingBit( drv_can_obj->can_base, CAN_IT_TME ); + CAN_ClearITPendingBit(drv_can_obj->can_base, CAN_IT_TME); CAN_ITConfig(drv_can_obj->can_base, CAN_IT_TME, ENABLE); /*!< Transmit mailbox empty Interrupt*/ if (CAN1 == drv_can_obj->can_base) @@ -451,11 +450,11 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) drv_can_obj->can_filter_init.CAN_FilterNumber = filter_cfg->items[i].hdr_bank; } - if (filter_cfg->items[i].mode == 0x00) //CAN_FILTERMODE_IDMASK + if (filter_cfg->items[i].mode == 0x00) //CAN_FILTERMODE_IDMASK { drv_can_obj->can_filter_init.CAN_FilterMode = CAN_FilterMode_IdMask; } - else if (filter_cfg->items[i].mode == 0x01) //CAN_FILTERMODE_IDLIST + else if (filter_cfg->items[i].mode == 0x01) //CAN_FILTERMODE_IDLIST { drv_can_obj->can_filter_init.CAN_FilterMode = CAN_FilterMode_IdList; } @@ -465,7 +464,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF; id_l = ((filter_cfg->items[i].id << 18) | (filter_cfg->items[i].ide << 2) | - (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + (filter_cfg->items[i].rtr << 1)) & + 0xFFFF; mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF; mask_l = ((filter_cfg->items[i].mask << 21)) & 0xFFFF; } @@ -474,15 +474,16 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF; id_l = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | - (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + (filter_cfg->items[i].rtr << 1)) & + 0xFFFF; mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF; - mask_l = ((filter_cfg->items[i].mask << 3) ) & 0xFFFF; + mask_l = ((filter_cfg->items[i].mask << 3)) & 0xFFFF; } drv_can_obj->can_filter_init.CAN_FilterScale = CAN_FilterScale_32bit; drv_can_obj->can_filter_init.CAN_FilterIdHigh = id_h; - drv_can_obj->can_filter_init.CAN_FilterIdLow = id_l; + drv_can_obj->can_filter_init.CAN_FilterIdLow = id_l; drv_can_obj->can_filter_init.CAN_FilterMaskIdHigh = mask_h; - drv_can_obj->can_filter_init.CAN_FilterMaskIdLow = mask_l; + drv_can_obj->can_filter_init.CAN_FilterMaskIdLow = mask_l; drv_can_obj->can_filter_init.CAN_FilterFIFOAssignment = CAN_Filter_FIFO0; drv_can_obj->can_filter_init.CAN_FilterActivation = ENABLE; @@ -543,10 +544,10 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) case RT_CAN_CMD_GET_STATUS: { rt_uint32_t errval; - errval = drv_can_obj->can_base->ERRSR; //ERRSR - drv_can_obj->device.status.rcverrcnt = errval >> 24; //REC - drv_can_obj->device.status.snderrcnt = (errval >> 16 & 0xFF); //TEC - drv_can_obj->device.status.lasterrtype = errval & 0x70; //LEC + errval = drv_can_obj->can_base->ERRSR; //ERRSR + drv_can_obj->device.status.rcverrcnt = errval >> 24; //REC + drv_can_obj->device.status.snderrcnt = (errval >> 16 & 0xFF); //TEC + drv_can_obj->device.status.lasterrtype = errval & 0x70; //LEC drv_can_obj->device.status.errcode = errval & 0x07; rt_memcpy(arg, &drv_can_obj->device.status, sizeof(drv_can_obj->device.status)); @@ -558,11 +559,11 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) } /* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((rt_uint32_t)0x00000001) +#define TMIDxR_TXRQ ((rt_uint32_t)0x00000001) static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t mailbox_index) { - CanTxMsg CAN_TxMessage = {0}; + CanTxMsg CAN_TxMessage = { 0 }; CanTxMsg *TxMessage = &CAN_TxMessage; /* Select one empty transmit mailbox */ switch (mailbox_index) @@ -617,7 +618,7 @@ static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_ui if (mailbox_index != CAN_TxStatus_NoMailBox) { /* Set Id */ - can_base->sTxMailBox[mailbox_index].TXMIR &= TMIDxR_TXRQ; + can_base->sTxMailBox[mailbox_index].TXMIR &= TMIDxR_TXRQ; if (TxMessage->IDE == CAN_Id_Standard) { can_base->sTxMailBox[mailbox_index].TXMIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); @@ -667,11 +668,11 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t FIFONum) { - CanRxMsg CAN_RxMessage = {0}; + CanRxMsg CAN_RxMessage = { 0 }; CanRxMsg *RxMessage = &CAN_RxMessage; /* Check the Rx FIFO */ - if( CAN_MessagePending( can_base, FIFONum ) == 0) + if (CAN_MessagePending(can_base, FIFONum) == 0) { return -RT_ERROR; } @@ -692,11 +693,11 @@ static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_ui RxMessage->FMI = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDTR >> 8); /* Get the data field */ - pmsg->data[0] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR; + pmsg->data[0] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR; pmsg->data[1] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 8); pmsg->data[2] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 16); pmsg->data[3] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 24); - pmsg->data[4] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR; + pmsg->data[4] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR; pmsg->data[5] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 8); pmsg->data[6] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 16); pmsg->data[7] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 24); @@ -735,7 +736,7 @@ static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_ui pmsg->hdr_index = (RxMessage->FMI >> 1) + 14; } /* Release FIFO */ - CAN_FIFORelease(can_base,FIFONum); + CAN_FIFORelease(can_base, FIFONum); return RT_EOK; } @@ -752,8 +753,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) return _can_recv_rtmsg(drv_can_obj->can_base, ((struct rt_can_msg *)buf), fifo); } -static const struct rt_can_ops _can_ops = -{ +static const struct rt_can_ops _can_ops = { _can_config, _can_control, _can_sendmsg, @@ -767,37 +767,37 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) drv_can_obj = (struct ch32v307x_can_obj *)can->parent.user_data; RT_ASSERT(drv_can_obj != RT_NULL); - CAN_TypeDef * can_base = drv_can_obj->can_base; + CAN_TypeDef *can_base = drv_can_obj->can_base; switch (fifo) { case CAN_FIFO0: - if( ((can_base->RFIFO0 & CAN_RFIFO0_FMP0) ) && ((can_base->INTENR & CAN_IT_FMP0) == CAN_IT_FMP0) ) + if (((can_base->RFIFO0 & CAN_RFIFO0_FMP0)) && ((can_base->INTENR & CAN_IT_FMP0) == CAN_IT_FMP0)) { rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); } - if( ((can_base->RFIFO0 & CAN_RFIFO0_FULL0)) && ((can_base->INTENR & CAN_IT_FF0) == CAN_IT_FF0) ) + if (((can_base->RFIFO0 & CAN_RFIFO0_FULL0)) && ((can_base->INTENR & CAN_IT_FF0) == CAN_IT_FF0)) { - can_base->RFIFO0 |= CAN_RFIFO0_FULL0; //clear + can_base->RFIFO0 |= CAN_RFIFO0_FULL0; //clear } - if( ((can_base->RFIFO0 & CAN_RFIFO0_FOVR0)) && ((can_base->INTENR & CAN_IT_FOV0) == CAN_IT_FOV0) ) + if (((can_base->RFIFO0 & CAN_RFIFO0_FOVR0)) && ((can_base->INTENR & CAN_IT_FOV0) == CAN_IT_FOV0)) { - can_base->RFIFO0 |= CAN_RFIFO0_FOVR0; //clear + can_base->RFIFO0 |= CAN_RFIFO0_FOVR0; //clear rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); } break; case CAN_FIFO1: - if( ((can_base->RFIFO1 & CAN_RFIFO1_FMP1)) && ((can_base->INTENR & CAN_IT_FMP1) == CAN_IT_FMP1) ) + if (((can_base->RFIFO1 & CAN_RFIFO1_FMP1)) && ((can_base->INTENR & CAN_IT_FMP1) == CAN_IT_FMP1)) { rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); } - if( ((can_base->RFIFO1 & CAN_RFIFO1_FULL1)) && ((can_base->INTENR & CAN_IT_FF1) == CAN_IT_FF1) ) + if (((can_base->RFIFO1 & CAN_RFIFO1_FULL1)) && ((can_base->INTENR & CAN_IT_FF1) == CAN_IT_FF1)) { - can_base->RFIFO1 |= CAN_RFIFO1_FULL1; //clear + can_base->RFIFO1 |= CAN_RFIFO1_FULL1; //clear } - if( ((can_base->RFIFO1 & CAN_RFIFO1_FOVR1)) && ((can_base->INTENR & CAN_IT_FOV1) == CAN_IT_FOV1) ) + if (((can_base->RFIFO1 & CAN_RFIFO1_FOVR1)) && ((can_base->INTENR & CAN_IT_FOV1) == CAN_IT_FOV1)) { - can_base->RFIFO1 |= CAN_RFIFO1_FOVR1; //clear + can_base->RFIFO1 |= CAN_RFIFO1_FOVR1; //clear rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); } break; @@ -808,66 +808,63 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /** * @brief This function handles CAN1 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt */ -void USB_HP_CAN1_TX_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USB_HP_CAN1_TX_IRQHandler(void) WCH_IRQ_ATTR; void USB_HP_CAN1_TX_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); struct ch32v307x_can_obj *drv_can_obj = &drv_can1; - CAN_TypeDef * can_base = drv_can_obj->can_base; + CAN_TypeDef *can_base = drv_can_obj->can_base; - if((can_base->INTENR & CAN_IT_TME) == CAN_IT_TME) + if ((can_base->INTENR & CAN_IT_TME) == CAN_IT_TME) { - if( (can_base->TSTATR & CAN_TSTATR_RQCP0) == CAN_TSTATR_RQCP0) + if ((can_base->TSTATR & CAN_TSTATR_RQCP0) == CAN_TSTATR_RQCP0) { //Request Completed Mailbox0 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) + if ((can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) { can_base->TSTATR |= CAN_TSTATR_TXOK0; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x00 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST0) == CAN_TSTATR_ALST0) - || (( can_base->TSTATR & CAN_TSTATR_TERR0) == CAN_TSTATR_TERR0) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST0) == CAN_TSTATR_ALST0) || ((can_base->TSTATR & CAN_TSTATR_TERR0) == CAN_TSTATR_TERR0)) { can_base->TSTATR |= (CAN_TSTATR_ALST0 | CAN_TSTATR_TERR0); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x00 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP0; // set 1 clear } - if( (can_base->TSTATR & CAN_TSTATR_RQCP1) == CAN_TSTATR_RQCP1) + if ((can_base->TSTATR & CAN_TSTATR_RQCP1) == CAN_TSTATR_RQCP1) { //Request Completed Mailbox1 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) + if ((can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) { can_base->TSTATR |= CAN_TSTATR_TXOK1; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x01 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST1) == CAN_TSTATR_ALST1) - || (( can_base->TSTATR & CAN_TSTATR_TERR1) == CAN_TSTATR_TERR1) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST1) == CAN_TSTATR_ALST1) || ((can_base->TSTATR & CAN_TSTATR_TERR1) == CAN_TSTATR_TERR1)) { can_base->TSTATR |= (CAN_TSTATR_ALST1 | CAN_TSTATR_TERR1); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x01 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP1; // set 1 clear } - if( (can_base->TSTATR & CAN_TSTATR_RQCP2) == CAN_TSTATR_RQCP2) + if ((can_base->TSTATR & CAN_TSTATR_RQCP2) == CAN_TSTATR_RQCP2) { //Request Completed Mailbox2 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) + if ((can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) { can_base->TSTATR |= CAN_TSTATR_TXOK2; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x02 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST2) == CAN_TSTATR_ALST2) - || (( can_base->TSTATR & CAN_TSTATR_TERR2) == CAN_TSTATR_TERR2) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST2) == CAN_TSTATR_ALST2) || ((can_base->TSTATR & CAN_TSTATR_TERR2) == CAN_TSTATR_TERR2)) { can_base->TSTATR |= (CAN_TSTATR_ALST2 | CAN_TSTATR_TERR2); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x02 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP2; // set 1 clear } - CAN_ClearITPendingBit( can_base, CAN_IT_TME ); + CAN_ClearITPendingBit(can_base, CAN_IT_TME); } rt_interrupt_leave(); FREE_INT_SP(); @@ -876,7 +873,7 @@ void USB_HP_CAN1_TX_IRQHandler(void) /** * @brief This function handles CAN1 RX0 interrupts. */ -void USB_LP_CAN1_RX0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USB_LP_CAN1_RX0_IRQHandler(void) WCH_IRQ_ATTR; void USB_LP_CAN1_RX0_IRQHandler(void) { GET_INT_SP(); @@ -889,7 +886,7 @@ void USB_LP_CAN1_RX0_IRQHandler(void) /** * @brief This function handles CAN1 RX1 interrupts. */ -void CAN1_RX1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN1_RX1_IRQHandler(void) WCH_IRQ_ATTR; void CAN1_RX1_IRQHandler(void) { GET_INT_SP(); @@ -902,15 +899,15 @@ void CAN1_RX1_IRQHandler(void) /** * @brief This function handles CAN1 SCE interrupts. */ -void CAN1_SCE_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN1_SCE_IRQHandler(void) WCH_IRQ_ATTR; void CAN1_SCE_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); struct ch32v307x_can_obj *drv_can_obj = &drv_can1; - CAN_TypeDef * can_base = drv_can_obj->can_base; - rt_uint32_t errval = can_base->ERRSR; //ERRSR + CAN_TypeDef *can_base = drv_can_obj->can_base; + rt_uint32_t errval = can_base->ERRSR; //ERRSR switch ((errval & 0x70) >> 4) { @@ -922,15 +919,15 @@ void CAN1_SCE_IRQHandler(void) break; case RT_CAN_BUS_ACK_ERR: drv_can_obj->device.status.ackerrcnt++; - if( (can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) + if ((can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x00 << 8); - }else - if( (can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) + } + else if ((can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x01 << 8); - }else - if( (can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) + } + else if ((can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x02 << 8); } @@ -959,66 +956,63 @@ void CAN1_SCE_IRQHandler(void) /** * @brief This function handles CAN2 TX interrupts. */ -void CAN2_TX_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN2_TX_IRQHandler(void) WCH_IRQ_ATTR; void CAN2_TX_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); struct ch32v307x_can_obj *drv_can_obj = &drv_can2; - CAN_TypeDef * can_base = drv_can_obj->can_base; + CAN_TypeDef *can_base = drv_can_obj->can_base; - if((can_base->INTENR & CAN_IT_TME) == CAN_IT_TME) + if ((can_base->INTENR & CAN_IT_TME) == CAN_IT_TME) { - if( (can_base->TSTATR & CAN_TSTATR_RQCP0) == CAN_TSTATR_RQCP0) + if ((can_base->TSTATR & CAN_TSTATR_RQCP0) == CAN_TSTATR_RQCP0) { //Request Completed Mailbox0 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) + if ((can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) { can_base->TSTATR |= CAN_TSTATR_TXOK0; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x00 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST0) == CAN_TSTATR_ALST0) - || (( can_base->TSTATR & CAN_TSTATR_TERR0) == CAN_TSTATR_TERR0) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST0) == CAN_TSTATR_ALST0) || ((can_base->TSTATR & CAN_TSTATR_TERR0) == CAN_TSTATR_TERR0)) { can_base->TSTATR |= (CAN_TSTATR_ALST0 | CAN_TSTATR_TERR0); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x00 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP0; // set 1 clear } - if( (can_base->TSTATR & CAN_TSTATR_RQCP1) == CAN_TSTATR_RQCP1) + if ((can_base->TSTATR & CAN_TSTATR_RQCP1) == CAN_TSTATR_RQCP1) { //Request Completed Mailbox1 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) + if ((can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) { can_base->TSTATR |= CAN_TSTATR_TXOK1; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x01 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST1) == CAN_TSTATR_ALST1) - || (( can_base->TSTATR & CAN_TSTATR_TERR1) == CAN_TSTATR_TERR1) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST1) == CAN_TSTATR_ALST1) || ((can_base->TSTATR & CAN_TSTATR_TERR1) == CAN_TSTATR_TERR1)) { can_base->TSTATR |= (CAN_TSTATR_ALST1 | CAN_TSTATR_TERR1); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x01 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP1; // set 1 clear } - if( (can_base->TSTATR & CAN_TSTATR_RQCP2) == CAN_TSTATR_RQCP2) + if ((can_base->TSTATR & CAN_TSTATR_RQCP2) == CAN_TSTATR_RQCP2) { //Request Completed Mailbox2 - if( ( can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) + if ((can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) { can_base->TSTATR |= CAN_TSTATR_TXOK2; // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_DONE | (0x02 << 8)); } - if( ( ( can_base->TSTATR & CAN_TSTATR_ALST2) == CAN_TSTATR_ALST2) - || (( can_base->TSTATR & CAN_TSTATR_TERR2) == CAN_TSTATR_TERR2) ) + if (((can_base->TSTATR & CAN_TSTATR_ALST2) == CAN_TSTATR_ALST2) || ((can_base->TSTATR & CAN_TSTATR_TERR2) == CAN_TSTATR_TERR2)) { can_base->TSTATR |= (CAN_TSTATR_ALST2 | CAN_TSTATR_TERR2); // set 1 clear rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | (0x02 << 8)); } can_base->TSTATR |= CAN_TSTATR_RQCP2; // set 1 clear } - CAN_ClearITPendingBit( can_base, CAN_IT_TME ); + CAN_ClearITPendingBit(can_base, CAN_IT_TME); } rt_interrupt_leave(); FREE_INT_SP(); @@ -1027,7 +1021,7 @@ void CAN2_TX_IRQHandler(void) /** * @brief This function handles CAN2 RX0 interrupts. */ -void CAN2_RX0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN2_RX0_IRQHandler(void) WCH_IRQ_ATTR; void CAN2_RX0_IRQHandler(void) { GET_INT_SP(); @@ -1040,7 +1034,7 @@ void CAN2_RX0_IRQHandler(void) /** * @brief This function handles CAN2 RX1 interrupts. */ -void CAN2_RX1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN2_RX1_IRQHandler(void) WCH_IRQ_ATTR; void CAN2_RX1_IRQHandler(void) { GET_INT_SP(); @@ -1053,14 +1047,14 @@ void CAN2_RX1_IRQHandler(void) /** * @brief This function handles CAN2 SCE interrupts. */ -void CAN2_SCE_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void CAN2_SCE_IRQHandler(void) WCH_IRQ_ATTR; void CAN2_SCE_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); struct ch32v307x_can_obj *drv_can_obj = &drv_can2; - CAN_TypeDef * can_base = drv_can_obj->can_base; - rt_uint32_t errval = can_base->ERRSR; //ERRSR + CAN_TypeDef *can_base = drv_can_obj->can_base; + rt_uint32_t errval = can_base->ERRSR; //ERRSR switch ((errval & 0x70) >> 4) { @@ -1072,15 +1066,15 @@ void CAN2_SCE_IRQHandler(void) break; case RT_CAN_BUS_ACK_ERR: drv_can_obj->device.status.ackerrcnt++; - if( (can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) + if ((can_base->TSTATR & CAN_TSTATR_TXOK0) == CAN_TSTATR_TXOK0) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x00 << 8); - }else - if( (can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) + } + else if ((can_base->TSTATR & CAN_TSTATR_TXOK1) == CAN_TSTATR_TXOK1) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x01 << 8); - }else - if( (can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) + } + else if ((can_base->TSTATR & CAN_TSTATR_TXOK2) == CAN_TSTATR_TXOK2) { rt_hw_can_isr(&drv_can_obj->device, RT_CAN_EVENT_TX_FAIL | 0x02 << 8); } diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_common.h b/bsp/wch/risc-v/libraries/ch32_drivers/drv_common.h index 1df9af8783..8aeecfc447 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_common.h +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_common.h @@ -11,9 +11,17 @@ #ifndef __DRV_COMMON_H__ #define __DRV_COMMON_H__ +#include <rtthread.h> + +#ifdef WCH_USING_FAST_IRQ +#define WCH_IRQ_ATTR __attribute__((interrupt("WCH-Interrupt-fast"))) +#else +#define WCH_IRQ_ATTR __attribute__((interrupt())) +#endif #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif void rt_hw_us_delay(rt_uint32_t us); diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_eth.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_eth.c index 6aaef7bcc0..de5e276086 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_eth.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_eth.c @@ -9,58 +9,55 @@ */ #include "board.h" +#include "drv_common.h" #include <rtdevice.h> - #ifdef BSP_USING_ETH #include <netif/ethernetif.h> #include "lwipopts.h" #include <drv_eth.h> -#define LOG_TAG "drv.eth" +#define LOG_TAG "drv.eth" #include <drv_log.h> -#define MAX_ADDR_LEN 6 -#define ETH_DMARxDesc_FrameLengthShift 16 - -#define define_O(a,b) \ -GPIO_InitStructure.GPIO_Pin = b;\ -GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\ -GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\ -GPIO_Init(a, &GPIO_InitStructure) +#define MAX_ADDR_LEN 6 +#define ETH_DMARxDesc_FrameLengthShift 16 -#define define_I(a,b) \ -GPIO_InitStructure.GPIO_Pin = b;\ -GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\ -GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\ -GPIO_Init(a, &GPIO_InitStructure) +#define define_O(a, b) \ + GPIO_InitStructure.GPIO_Pin = b; \ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; \ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; \ + GPIO_Init(a, &GPIO_InitStructure) +#define define_I(a, b) \ + GPIO_InitStructure.GPIO_Pin = b; \ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; \ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; \ + GPIO_Init(a, &GPIO_InitStructure) /* globe variable */ -extern ETH_DMADESCTypeDef *DMATxDescToSet; //set tx Desc then send it -extern ETH_DMADESCTypeDef *DMARxDescToGet; //current rx Desc - +extern ETH_DMADESCTypeDef *DMATxDescToSet; //set tx Desc then send it +extern ETH_DMADESCTypeDef *DMARxDescToGet; //current rx Desc /* rt-thread eth */ struct rt_ch32_eth { - /* inherit from ethernet device */ + /* inherit from ethernet device */ struct eth_device parent; #ifndef PHY_USING_INTERRUPT_MODE rt_timer_t poll_link_timer; #endif /* interface address info, hw address */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* ETH_Speed */ - uint32_t ETH_Speed; + uint32_t ETH_Speed; /* ETH_Duplex_Mode */ - uint32_t ETH_Mode; + uint32_t ETH_Mode; }; -static ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; -static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE],Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE]; -struct rt_ch32_eth ch32v30x_eth_device; - +static ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; +static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE]; +struct rt_ch32_eth ch32v30x_eth_device; //#define ETH_RX_DUMP #if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) @@ -75,29 +72,38 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) rt_kprintf("%08X: ", i); for (j = 0; j < 16; j++) + { if (i + j < buflen) + { rt_kprintf("%02X ", buf[i + j]); + } else + { rt_kprintf(" "); + } + } rt_kprintf(" "); for (j = 0; j < 16; j++) + { if (i + j < buflen) + { rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } rt_kprintf("\r\n"); } } #endif - /* received data */ FrameTypeDef ETH_RxPkt_ChainMode(void) { u32 framelength = 0; - FrameTypeDef frame = {0,0,NULL}; + FrameTypeDef frame = { 0, 0, NULL }; /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) + if ((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) { frame.length = ETH_ERROR; if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET) @@ -108,11 +114,11 @@ FrameTypeDef ETH_RxPkt_ChainMode(void) ETH->DMARPDR = 0; } LOG_E("Error:ETH_DMARxDesc_OWN.\r\n"); - /* Return error: OWN bit set */ - return frame; + /* Return error: OWN bit set */ + return frame; } - if( + if ( ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) && ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) && ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET)) @@ -127,22 +133,20 @@ FrameTypeDef ETH_RxPkt_ChainMode(void) { /* Return ERROR */ framelength = ETH_ERROR; - rt_kprintf("Error:recv error frame,status:0x%08x.\r\n",DMARxDescToGet->Status); + rt_kprintf("Error:recv error frame,status:0x%08x.\r\n", DMARxDescToGet->Status); } - DMARxDescToGet->Status|=ETH_DMARxDesc_OWN; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; frame.length = framelength; frame.descriptor = DMARxDescToGet; /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ /* Chained Mode */ /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); /* Return Frame */ return (frame); } - - /******************************************************************************* * Function Name : GETH_pin_init * Description : PHY RGMII interface GPIO initialization. @@ -155,29 +159,28 @@ void GETH_pin_init(void) /* PB12/13 set AF_PP_OUT */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE); - GPIOB->CFGHR&=~(0xff<<16); - GPIOB->CFGHR|= (0xbb<<16); - GPIOB->CFGLR&=~(0xff<<4); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + GPIOB->CFGHR &= ~(0xff << 16); + GPIOB->CFGHR |= (0xbb << 16); + GPIOB->CFGLR &= ~(0xff << 4); - define_O(GPIOA,GPIO_Pin_2); - define_O(GPIOA,GPIO_Pin_3); - define_O(GPIOA,GPIO_Pin_7); - define_O(GPIOC,GPIO_Pin_4); - define_O(GPIOC,GPIO_Pin_5); - define_O(GPIOB,GPIO_Pin_0); + define_O(GPIOA, GPIO_Pin_2); + define_O(GPIOA, GPIO_Pin_3); + define_O(GPIOA, GPIO_Pin_7); + define_O(GPIOC, GPIO_Pin_4); + define_O(GPIOC, GPIO_Pin_5); + define_O(GPIOB, GPIO_Pin_0); - define_I(GPIOC,GPIO_Pin_0); - define_I(GPIOC,GPIO_Pin_1); - define_I(GPIOC,GPIO_Pin_2); - define_I(GPIOC,GPIO_Pin_3); - define_I(GPIOA,GPIO_Pin_0); - define_I(GPIOA,GPIO_Pin_1); + define_I(GPIOC, GPIO_Pin_0); + define_I(GPIOC, GPIO_Pin_1); + define_I(GPIOC, GPIO_Pin_2); + define_I(GPIOC, GPIO_Pin_3); + define_I(GPIOA, GPIO_Pin_0); + define_I(GPIOA, GPIO_Pin_1); - define_I(GPIOB,GPIO_Pin_1);/* 125m in */ + define_I(GPIOB, GPIO_Pin_1); /* 125m in */ } - /******************************************************************************* * Function Name : GETH_pin_init * Description : PHY MII/RMII interface GPIO initialization. @@ -189,43 +192,43 @@ void FETH_pin_init(void) GPIO_InitTypeDef GPIO_InitStructure; #ifdef USE_RMII - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC|RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE); GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII); - define_O(GPIOA,GPIO_Pin_2);/* MDC */ - define_O(GPIOC,GPIO_Pin_1);/* MDIO */ + define_O(GPIOA, GPIO_Pin_2); /* MDC */ + define_O(GPIOC, GPIO_Pin_1); /* MDIO */ - define_O(GPIOB,GPIO_Pin_11);//txen - define_O(GPIOB,GPIO_Pin_12);//txd0 - define_O(GPIOB,GPIO_Pin_13);//txd1 + define_O(GPIOB, GPIO_Pin_11); //txen + define_O(GPIOB, GPIO_Pin_12); //txd0 + define_O(GPIOB, GPIO_Pin_13); //txd1 - define_I(GPIOA,GPIO_Pin_1);/* PA1 REFCLK */ - define_I(GPIOA,GPIO_Pin_7);/* PA7 CRSDV */ - define_I(GPIOC,GPIO_Pin_4);/* RXD0 */ - define_I(GPIOC,GPIO_Pin_5);/* RXD1 */ + define_I(GPIOA, GPIO_Pin_1); /* PA1 REFCLK */ + define_I(GPIOA, GPIO_Pin_7); /* PA7 CRSDV */ + define_I(GPIOC, GPIO_Pin_4); /* RXD0 */ + define_I(GPIOC, GPIO_Pin_5); /* RXD1 */ #else - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); /* tx */ - define_O(GPIOA,GPIO_Pin_2);/* MDC */ - define_O(GPIOC,GPIO_Pin_1);/* MDIO */ + define_O(GPIOA, GPIO_Pin_2); /* MDC */ + define_O(GPIOC, GPIO_Pin_1); /* MDIO */ - define_I(GPIOC,GPIO_Pin_3);//txclk - define_O(GPIOB,GPIO_Pin_11);//txen - define_O(GPIOB,GPIO_Pin_12);//txd0 - define_O(GPIOB,GPIO_Pin_13);//txd1 - define_O(GPIOC,GPIO_Pin_2); //txd2 - define_O(GPIOB,GPIO_Pin_8);//txd3 + define_I(GPIOC, GPIO_Pin_3); //txclk + define_O(GPIOB, GPIO_Pin_11); //txen + define_O(GPIOB, GPIO_Pin_12); //txd0 + define_O(GPIOB, GPIO_Pin_13); //txd1 + define_O(GPIOC, GPIO_Pin_2); //txd2 + define_O(GPIOB, GPIO_Pin_8); //txd3 /* tx */ - define_I(GPIOA,GPIO_Pin_1);/* PA1 RXC */ - define_I(GPIOA,GPIO_Pin_7);/* PA7 RXDV */ - define_I(GPIOC,GPIO_Pin_4);/* RXD0 */ - define_I(GPIOC,GPIO_Pin_5);/* RXD1 */ - define_I(GPIOB,GPIO_Pin_0);/* RXD2 */ - define_I(GPIOB,GPIO_Pin_1);/* RXD3 */ - define_I(GPIOB,GPIO_Pin_10);/* RXER */ + define_I(GPIOA, GPIO_Pin_1); /* PA1 RXC */ + define_I(GPIOA, GPIO_Pin_7); /* PA7 RXDV */ + define_I(GPIOC, GPIO_Pin_4); /* RXD0 */ + define_I(GPIOC, GPIO_Pin_5); /* RXD1 */ + define_I(GPIOB, GPIO_Pin_0); /* RXD2 */ + define_I(GPIOB, GPIO_Pin_1); /* RXD3 */ + define_I(GPIOB, GPIO_Pin_10); /* RXER */ - define_O(GPIOA,GPIO_Pin_0);/* PA0 */ - define_O(GPIOA,GPIO_Pin_3);/* PA3 */ + define_O(GPIOA, GPIO_Pin_0); /* PA0 */ + define_O(GPIOA, GPIO_Pin_3); /* PA3 */ #endif } @@ -236,11 +239,11 @@ void FETH_pin_init(void) * PHYAddress:PHY address. * Return : Initialization status. *******************************************************************************/ -uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +uint32_t ETH_Init(ETH_InitTypeDef *ETH_InitStruct, uint16_t PHYAddress) { uint32_t tmpreg = 0; uint16_t RegValue = 0; - uint32_t tickstart=0; + uint32_t tickstart = 0; /* config phy */ tmpreg = ETH->MACMIIAR; tmpreg &= MACMIIAR_CR_MASK; @@ -249,192 +252,192 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) ETH->MACMIIAR = (uint32_t)tmpreg; /* reset phy */ ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset); - tickstart= rt_tick_get_millisecond(); - do{ - asm("nop"); /* waiting for finish */ - }while((rt_tick_get_millisecond()-tickstart)<1000); - + tickstart = rt_tick_get_millisecond(); + do + { + asm("nop"); /* waiting for finish */ + } while ((rt_tick_get_millisecond() - tickstart) < 1000); - tickstart= rt_tick_get_millisecond(); + tickstart = rt_tick_get_millisecond(); RegValue = 0; - while( (RegValue&(PHY_Reset)) ) + while ((RegValue & (PHY_Reset))) { RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); - if((rt_tick_get_millisecond()-tickstart)>10000) + if ((rt_tick_get_millisecond() - tickstart) > 10000) { LOG_E("Error:Wait phy reset timeout!\r\n"); - while(1); + while (1); } } /* waiting for link up */ - tickstart= rt_tick_get_millisecond(); + tickstart = rt_tick_get_millisecond(); RegValue = 0; - while((RegValue&(PHY_Linked_Status)) == 0) + while ((RegValue & (PHY_Linked_Status)) == 0) { - RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BSR); - if((rt_tick_get_millisecond()-tickstart)>10000) - { - LOG_E("Error:Wait phy linking timeout!\r\n"); - while(1); - } + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BSR); + if ((rt_tick_get_millisecond() - tickstart) > 10000) + { + LOG_E("Error:Wait phy linking timeout!\r\n"); + while (1); + } } /* waiting for auto-negotiation */ - tickstart= rt_tick_get_millisecond(); + tickstart = rt_tick_get_millisecond(); RegValue = 0; - while((RegValue&PHY_AutoNego_Complete) == 0) + while ((RegValue & PHY_AutoNego_Complete) == 0) { RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BSR); - if((rt_tick_get_millisecond()-tickstart)>10000) + if ((rt_tick_get_millisecond() - tickstart) > 10000) { LOG_E("Error:Wait phy auto-negotiation complete timeout!\r\n"); - while(1); + while (1); } } #ifdef USE10BASE_T RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BMCR); - LOG_D("PHY_BMCR:%d,value:%04x.\n",PHY_BMCR,RegValue); - if((RegValue & (1<<8)) != (uint32_t)RESET) + LOG_D("PHY_BMCR:%d,value:%04x.\n", PHY_BMCR, RegValue); + if ((RegValue & (1 << 8)) != (uint32_t)RESET) { - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - ch32v30x_eth_device.ETH_Mode=ETH_Mode_FullDuplex; - LOG_D("Full-Duplex.\n"); + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + LOG_D("Full-Duplex.\n"); } else { - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - ch32v30x_eth_device.ETH_Mode=ETH_Mode_HalfDuplex; - LOG_D("Half-Duplex.\n"); + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; + LOG_D("Half-Duplex.\n"); } - if(RegValue & (1<<13)) + if (RegValue & (1 << 13)) { - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - ch32v30x_eth_device.ETH_Speed=ETH_Speed_100M; - /* send link up. */ - eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); - LOG_D("Link speed:100M.\n"); + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_100M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:100M.\n"); } else { - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ch32v30x_eth_device.ETH_Speed=ETH_Speed_10M; - /* send link up. */ - eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); - LOG_D("Link speed:10M.\n"); + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_10M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:10M.\n"); } #endif #ifdef USE_FAST_MAC /* 100M MAC,RMII */ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_BMCR); - LOG_D("PHY_BMCR:%d,value:%04x.\n",PHY_BMCR,RegValue); - if((RegValue & (1<<8)) != (uint32_t)RESET) + LOG_D("PHY_BMCR:%d,value:%04x.\n", PHY_BMCR, RegValue); + if ((RegValue & (1 << 8)) != (uint32_t)RESET) { - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; - LOG_D("Full-Duplex.\n"); + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + LOG_D("Full-Duplex.\n"); } else { - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; - LOG_D("Half-Duplex.\n"); + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; + LOG_D("Half-Duplex.\n"); } - if(RegValue & (1<<13)) + if (RegValue & (1 << 13)) { - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - ch32v30x_eth_device.ETH_Speed=ETH_Speed_100M; - /* send link up. */ - eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); - LOG_D("Link speed:100M.\n"); + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_100M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:100M.\n"); } else { - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ch32v30x_eth_device.ETH_Speed=ETH_Speed_10M; - /* send link up. */ - eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); - LOG_D("Link speed:10M.\n"); + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_10M; + /* send link up. */ + eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); + LOG_D("Link speed:10M.\n"); } #endif #ifdef USE_GIGA_MAC /* GMAC,RGMI */ - ETH_WritePHYRegister(PHYAddress, 31,0x0a43 ); + ETH_WritePHYRegister(PHYAddress, 31, 0x0a43); RegValue = ETH_ReadPHYRegister(PHYAddress, 26); - if( RegValue & 0x0008 ) + if (RegValue & 0x0008) { - ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; ch32v30x_eth_device.ETH_Mode = ETH_Mode_FullDuplex; LOG_D("full duplex.\n"); } else { - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; ch32v30x_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; LOG_D("half duplex!\n"); } - if(( RegValue & 0x0030 ) == 0x0000) + if ((RegValue & 0x0030) == 0x0000) { - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ch32v30x_eth_device.ETH_Speed= ETH_Speed_10M; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_10M; eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); LOG_D("Link speed:10Mbps.\n"); } - else if(( RegValue & 0x0030 ) == 0x0010) + else if ((RegValue & 0x0030) == 0x0010) { - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - ch32v30x_eth_device.ETH_Speed= ETH_Speed_100M; + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_100M; eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); LOG_D("Link speed:100Mbps.\n"); } - else if(( RegValue & 0x0030 ) == 0x0020) + else if ((RegValue & 0x0030) == 0x0020) { - ETH_InitStruct->ETH_Speed = ETH_Speed_1000M; - ch32v30x_eth_device.ETH_Speed= ETH_Speed_1000M; + ETH_InitStruct->ETH_Speed = ETH_Speed_1000M; + ch32v30x_eth_device.ETH_Speed = ETH_Speed_1000M; eth_device_linkchange(&ch32v30x_eth_device.parent, RT_TRUE); LOG_D("Link speed:1000Mbps.\n"); } #endif - tickstart= rt_tick_get_millisecond(); - do{ + tickstart = rt_tick_get_millisecond(); + do + { asm("nop"); - }while((rt_tick_get_millisecond()-tickstart)<1000); - + } while ((rt_tick_get_millisecond() - tickstart) < 1000); /* MAC config */ /* if use RGMII,should config RGMII clock delay register */ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | - ETH_InitStruct->ETH_Jabber | - ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | - ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | - ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); ETH->MACCR = (uint32_t)tmpreg; #ifdef USE10BASE_T /* enable internal pull up resistance,50Ω */ - ETH->MACCR|=ETH_Internal_Pull_Up_Res_Enable; + ETH->MACCR |= ETH_Internal_Pull_Up_Res_Enable; #endif ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | - ETH_InitStruct->ETH_SourceAddrFilter | - ETH_InitStruct->ETH_PassControlFrames | - ETH_InitStruct->ETH_BroadcastFramesReception | - ETH_InitStruct->ETH_DestinationAddrFilter | - ETH_InitStruct->ETH_PromiscuousMode | - ETH_InitStruct->ETH_MulticastFramesFilter | - ETH_InitStruct->ETH_UnicastFramesFilter); + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); /* Write to ETHERNET MACHTHR */ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; /* Write to ETHERNET MACHTLR */ @@ -445,38 +448,38 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | - ETH_InitStruct->ETH_UnicastPauseFrameDetect | - ETH_InitStruct->ETH_ReceiveFlowControl | - ETH_InitStruct->ETH_TransmitFlowControl); + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); ETH->MACFCR = (uint32_t)tmpreg; ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | - ETH_InitStruct->ETH_VLANTagIdentifier); + ETH_InitStruct->ETH_VLANTagIdentifier); tmpreg = ETH->DMAOMR; /* Clear xx bits */ tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | - ETH_InitStruct->ETH_FlushReceivedFrame | - ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | - ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); ETH->DMAOMR = (uint32_t)tmpreg; ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | - ETH_InitStruct->ETH_FixedBurst | - ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - ETH_InitStruct->ETH_TxDMABurstLength | - (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | - ETH_InitStruct->ETH_DMAArbitration | - ETH_DMABMR_USP); + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); return ETH_SUCCESS; } @@ -484,17 +487,17 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* eth initialization function */ static rt_err_t rt_ch32_eth_init(rt_device_t dev) { - ETH_InitTypeDef ETH_InitStructure={0}; + ETH_InitTypeDef ETH_InitStructure = { 0 }; RCC_PLL3Cmd(DISABLE); RCC_PREDIV2Config(RCC_PREDIV2_Div2); RCC_PLL3Config(RCC_PLL3Mul_15); RCC_PLL3Cmd(ENABLE); - while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); + while (RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); LOG_D("PLL3 Init Finish\r\n"); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC|RCC_AHBPeriph_ETH_MAC_Tx|RCC_AHBPeriph_ETH_MAC_Rx,ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx, ENABLE); #ifdef USE10BASE_T /* Enable internal 10BASE-T PHY*/ - EXTEN->EXTEN_CTR |=EXTEN_ETH_10M_EN; + EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; #endif #ifdef USE_GIGA_MAC /* Enable 1G MAC*/ @@ -515,13 +518,13 @@ static rt_err_t rt_ch32_eth_init(rt_device_t dev) /* Software reset */ ETH_SoftwareReset(); /* Wait for software reset */ - while(ETH->DMABMR & ETH_DMABMR_SR); + while (ETH->DMABMR & ETH_DMABMR_SR); LOG_D("ETH RST Finish\r\n"); ETH_StructInit(Ð_InitStructure); ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; ETH_InitStructure.ETH_Speed = ETH_Speed_1000M; - ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ; + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; @@ -551,16 +554,13 @@ static rt_err_t rt_ch32_eth_init(rt_device_t dev) /* Configure Ethernet */ ETH_Init(Ð_InitStructure, PHY_ADDRESS); /* Enable the Ethernet Rx Interrupt */ - ETH_DMAITConfig(ETH_DMA_IT_NIS - | ETH_DMA_IT_R - | ETH_DMA_IT_T - ,ENABLE); - NVIC_SetPriority(ETH_IRQn,1<<4); + ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE); + NVIC_SetPriority(ETH_IRQn, 1 << 4); NVIC_EnableIRQ(ETH_IRQn); ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); #ifdef USE_GIGA_MAC - RGMII_TXC_Delay(0,2); + RGMII_TXC_Delay(0, 2); #endif ETH_Start(); return RT_EOK; @@ -592,18 +592,23 @@ static rt_ssize_t rt_ch32_eth_write(rt_device_t dev, rt_off_t pos, const void *b return 0; } - static rt_err_t rt_ch32_eth_control(rt_device_t dev, int cmd, void *args) { switch (cmd) { case NIOCTL_GADDR: /* get mac address */ - if (args) rt_memcpy(args, ch32v30x_eth_device.dev_addr, 6); - else return -RT_ERROR; + if (args) + { + rt_memcpy(args, ch32v30x_eth_device.dev_addr, 6); + } + else + { + return -RT_ERROR; + } break; - default : + default: break; } @@ -616,7 +621,7 @@ rt_err_t rt_ch32_eth_tx(rt_device_t dev, struct pbuf *p) struct pbuf *q; uint8_t *buffer = (uint8_t *)(DMATxDescToSet->Buffer1Addr); uint8_t *pdata; - uint32_t framelength = 0,len=0; + uint32_t framelength = 0, len = 0; /* copy frame from pbufs to driver buffers */ for (q = p; q != NULL; q = q->next) { @@ -631,7 +636,7 @@ rt_err_t rt_ch32_eth_tx(rt_device_t dev, struct pbuf *p) pdata = q->payload; len = q->len; framelength += len; - rt_memcpy(buffer,pdata,len); + rt_memcpy(buffer, pdata, len); buffer += len; } @@ -644,7 +649,7 @@ rt_err_t rt_ch32_eth_tx(rt_device_t dev, struct pbuf *p) DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; ret = ERR_OK; - Tx_error: +Tx_error: /* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { @@ -654,11 +659,10 @@ rt_err_t rt_ch32_eth_tx(rt_device_t dev, struct pbuf *p) ETH->DMATPDR = 0; } - DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); return ret; } - volatile FrameTypeDef frame; struct pbuf *rt_ch32_eth_rx(rt_device_t dev) { @@ -668,13 +672,13 @@ struct pbuf *rt_ch32_eth_rx(rt_device_t dev) uint8_t *buffer; uint8_t *pdata; - if(!frame.length) + if (!frame.length) { return NULL; } - len=frame.length; - frame.length=0; - buffer=(uint8_t *)frame.buffer; + len = frame.length; + frame.length = 0; + buffer = (uint8_t *)frame.buffer; if (len > 0) { /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */ @@ -688,35 +692,37 @@ struct pbuf *rt_ch32_eth_rx(rt_device_t dev) for (q = p; q != NULL; q = q->next) { pdata = q->payload; - rt_memcpy(pdata,buffer,q->len); + rt_memcpy(pdata, buffer, q->len); pdata += (q->len); buffer += (q->len); } - } + } else { LOG_E("p=null\r\n"); } return p; - } +} /* interrupt service routine */ -void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void ETH_IRQHandler(void) WCH_IRQ_ATTR; void ETH_IRQHandler(void) { GET_INT_SP(); /* enter interrupt */ rt_err_t result; rt_interrupt_enter(); - if(ETH->DMASRÐ_DMA_IT_R) + if (ETH->DMASR & ETH_DMA_IT_R) { ETH_DMAClearITPendingBit(ETH_DMA_IT_R); frame = ETH_RxPkt_ChainMode(); result = eth_device_ready(&(ch32v30x_eth_device.parent)); if (result != RT_EOK) + { rt_kprintf("RxCpltCallback err = %d\r\n", result); + } } - if(ETH->DMASRÐ_DMA_IT_T) + if (ETH->DMASR & ETH_DMA_IT_T) { ETH_DMAClearITPendingBit(ETH_DMA_IT_T); } @@ -726,7 +732,6 @@ void ETH_IRQHandler(void) FREE_INT_SP(); } - /* Register the EMAC device */ static int rt_hw_ch32_eth_init(void) { @@ -740,16 +745,16 @@ static int rt_hw_ch32_eth_init(void) ch32v30x_eth_device.dev_addr[4] = 0x2; ch32v30x_eth_device.dev_addr[5] = 0x3; - ch32v30x_eth_device.parent.parent.init = rt_ch32_eth_init; - ch32v30x_eth_device.parent.parent.open = rt_ch32_eth_open; - ch32v30x_eth_device.parent.parent.close = rt_ch32_eth_close; - ch32v30x_eth_device.parent.parent.read = rt_ch32_eth_read; - ch32v30x_eth_device.parent.parent.write = rt_ch32_eth_write; - ch32v30x_eth_device.parent.parent.control = rt_ch32_eth_control; - ch32v30x_eth_device.parent.parent.user_data = RT_NULL; + ch32v30x_eth_device.parent.parent.init = rt_ch32_eth_init; + ch32v30x_eth_device.parent.parent.open = rt_ch32_eth_open; + ch32v30x_eth_device.parent.parent.close = rt_ch32_eth_close; + ch32v30x_eth_device.parent.parent.read = rt_ch32_eth_read; + ch32v30x_eth_device.parent.parent.write = rt_ch32_eth_write; + ch32v30x_eth_device.parent.parent.control = rt_ch32_eth_control; + ch32v30x_eth_device.parent.parent.user_data = RT_NULL; - ch32v30x_eth_device.parent.eth_rx = rt_ch32_eth_rx; - ch32v30x_eth_device.parent.eth_tx = rt_ch32_eth_tx; + ch32v30x_eth_device.parent.eth_rx = rt_ch32_eth_rx; + ch32v30x_eth_device.parent.eth_tx = rt_ch32_eth_tx; /* register eth device */ state = eth_device_init(&(ch32v30x_eth_device.parent), "e0"); diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_gpio.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_gpio.c index 00a1ead30f..dbe4ee2254 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_gpio.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_gpio.c @@ -9,15 +9,16 @@ */ #include <board.h> +#include "drv_common.h" #include "drv_gpio.h" #ifdef BSP_USING_GPIO #define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) -#define PIN_PORT(pin) ((rt_uint8_t)(((pin) >> 4) & 0xFu)) -#define PIN_NO(pin) ((rt_uint8_t)((pin) & 0xFu)) +#define PIN_PORT(pin) ((rt_uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((rt_uint8_t)((pin) & 0xFu)) #define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) -#define PIN_STPIN(pin) ((rt_uint16_t)(1u << PIN_NO(pin))) +#define PIN_STPIN(pin) ((rt_uint16_t)(1u << PIN_NO(pin))) #if defined(GPIOZ) #define __CH32_PORT_MAX 12u @@ -50,44 +51,42 @@ #define PIN_STPORT_MAX __CH32_PORT_MAX -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_Pin_0, EXTI0_IRQn}, - {GPIO_Pin_1, EXTI1_IRQn}, - {GPIO_Pin_2, EXTI2_IRQn}, - {GPIO_Pin_3, EXTI3_IRQn}, - {GPIO_Pin_4, EXTI4_IRQn}, - {GPIO_Pin_5, EXTI9_5_IRQn}, - {GPIO_Pin_6, EXTI9_5_IRQn}, - {GPIO_Pin_7, EXTI9_5_IRQn}, - {GPIO_Pin_8, EXTI9_5_IRQn}, - {GPIO_Pin_9, EXTI9_5_IRQn}, - {GPIO_Pin_10, EXTI15_10_IRQn}, - {GPIO_Pin_11, EXTI15_10_IRQn}, - {GPIO_Pin_12, EXTI15_10_IRQn}, - {GPIO_Pin_13, EXTI15_10_IRQn}, - {GPIO_Pin_14, EXTI15_10_IRQn}, - {GPIO_Pin_15, EXTI15_10_IRQn}, +static const struct pin_irq_map pin_irq_map[] = { + { GPIO_Pin_0, EXTI0_IRQn }, + { GPIO_Pin_1, EXTI1_IRQn }, + { GPIO_Pin_2, EXTI2_IRQn }, + { GPIO_Pin_3, EXTI3_IRQn }, + { GPIO_Pin_4, EXTI4_IRQn }, + { GPIO_Pin_5, EXTI9_5_IRQn }, + { GPIO_Pin_6, EXTI9_5_IRQn }, + { GPIO_Pin_7, EXTI9_5_IRQn }, + { GPIO_Pin_8, EXTI9_5_IRQn }, + { GPIO_Pin_9, EXTI9_5_IRQn }, + { GPIO_Pin_10, EXTI15_10_IRQn }, + { GPIO_Pin_11, EXTI15_10_IRQn }, + { GPIO_Pin_12, EXTI15_10_IRQn }, + { GPIO_Pin_13, EXTI15_10_IRQn }, + { GPIO_Pin_14, EXTI15_10_IRQn }, + { GPIO_Pin_15, EXTI15_10_IRQn }, }; -static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, }; static rt_uint32_t pin_irq_enable_mask = 0; @@ -230,7 +229,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) }; static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) + rt_uint8_t mode, void (*hdr)(void *args), void *args) { rt_base_t level; rt_int32_t irqindex = -1; @@ -301,14 +300,14 @@ static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_base_t pin) } static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint8_t enabled) + rt_uint8_t enabled) { const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t irqindex = -1; - rt_uint8_t gpio_port_souce=0; - GPIO_InitTypeDef GPIO_InitStruct={0}; - EXTI_InitTypeDef EXTI_InitStructure={0}; + rt_uint8_t gpio_port_souce = 0; + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + EXTI_InitTypeDef EXTI_InitStructure = { 0 }; if (PIN_PORT(pin) >= PIN_STPORT_MAX) { @@ -334,12 +333,12 @@ static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, irqmap = &pin_irq_map[irqindex]; /* Configure GPIO_InitStructure */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); GPIO_InitStruct.GPIO_Pin = PIN_STPIN(pin); GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - EXTI_InitStructure.EXTI_Line=PIN_STPIN(pin); + EXTI_InitStructure.EXTI_Line = PIN_STPIN(pin); EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_LineCmd = ENABLE; @@ -360,13 +359,13 @@ static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, } GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct); - gpio_port_souce=PIN_PORT(pin); + gpio_port_souce = PIN_PORT(pin); - GPIO_EXTILineConfig(gpio_port_souce,(rt_uint8_t)irqindex); + GPIO_EXTILineConfig(gpio_port_souce, (rt_uint8_t)irqindex); EXTI_Init(&EXTI_InitStructure); - NVIC_SetPriority(irqmap->irqno,5<<4); - NVIC_EnableIRQ( irqmap->irqno ); + NVIC_SetPriority(irqmap->irqno, 5 << 4); + NVIC_EnableIRQ(irqmap->irqno); pin_irq_enable_mask |= irqmap->pinbit; rt_hw_interrupt_enable(level); @@ -383,16 +382,16 @@ static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, pin_irq_enable_mask &= ~irqmap->pinbit; - if (( irqmap->pinbit>=GPIO_Pin_5 )&&( irqmap->pinbit<=GPIO_Pin_9 )) + if ((irqmap->pinbit >= GPIO_Pin_5) && (irqmap->pinbit <= GPIO_Pin_9)) { - if(!(pin_irq_enable_mask&(GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7|GPIO_Pin_8|GPIO_Pin_9))) + if (!(pin_irq_enable_mask & (GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9))) { NVIC_DisableIRQ(irqmap->irqno); } } - else if (( irqmap->pinbit>=GPIO_Pin_10 )&&( irqmap->pinbit<=GPIO_Pin_15 )) + else if ((irqmap->pinbit >= GPIO_Pin_10) && (irqmap->pinbit <= GPIO_Pin_15)) { - if(!(pin_irq_enable_mask&(GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15))) + if (!(pin_irq_enable_mask & (GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15))) { NVIC_DisableIRQ(irqmap->irqno); } @@ -411,8 +410,7 @@ static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_EOK; } -static const struct rt_pin_ops _ch32_pin_ops = -{ +static const struct rt_pin_ops _ch32_pin_ops = { ch32_pin_mode, ch32_pin_write, ch32_pin_read, @@ -435,28 +433,19 @@ void HAL_GPIO_EXTI_Callback(rt_uint16_t GPIO_Pin) pin_irq_hdr(bit2bitno(GPIO_Pin)); } -#if defined (SOC_RISCV_SERIES_CH32V2) -void EXTI0_IRQHandler(void) __attribute__((interrupt())); -void EXTI1_IRQHandler(void) __attribute__((interrupt())); -void EXTI2_IRQHandler(void) __attribute__((interrupt())); -void EXTI3_IRQHandler(void) __attribute__((interrupt())); -void EXTI4_IRQHandler(void) __attribute__((interrupt())); -void EXTI9_5_IRQHandler(void) __attribute__((interrupt())); -#else -void EXTI0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void EXTI1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void EXTI2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void EXTI3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void EXTI4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void EXTI9_5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void EXTI0_IRQHandler(void) WCH_IRQ_ATTR; +void EXTI1_IRQHandler(void) WCH_IRQ_ATTR; +void EXTI2_IRQHandler(void) WCH_IRQ_ATTR; +void EXTI3_IRQHandler(void) WCH_IRQ_ATTR; +void EXTI4_IRQHandler(void) WCH_IRQ_ATTR; +void EXTI9_5_IRQHandler(void) WCH_IRQ_ATTR; void EXTI0_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_Line0)!=RESET) + if (EXTI_GetITStatus(EXTI_Line0) != RESET) { HAL_GPIO_EXTI_Callback(GPIO_Pin_0); EXTI_ClearITPendingBit(EXTI_Line0); @@ -470,7 +459,7 @@ void EXTI1_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_Line1)!=RESET) + if (EXTI_GetITStatus(EXTI_Line1) != RESET) { HAL_GPIO_EXTI_Callback(GPIO_Pin_1); EXTI_ClearITPendingBit(EXTI_Line1); @@ -483,7 +472,7 @@ void EXTI2_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_Line2)!=RESET) + if (EXTI_GetITStatus(EXTI_Line2) != RESET) { HAL_GPIO_EXTI_Callback(GPIO_Pin_2); EXTI_ClearITPendingBit(EXTI_Line2); @@ -496,7 +485,7 @@ void EXTI3_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_Line3)!=RESET) + if (EXTI_GetITStatus(EXTI_Line3) != RESET) { HAL_GPIO_EXTI_Callback(GPIO_Pin_3); EXTI_ClearITPendingBit(EXTI_Line3); @@ -509,7 +498,7 @@ void EXTI4_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if(EXTI_GetITStatus(EXTI_Line4)!=RESET) + if (EXTI_GetITStatus(EXTI_Line4) != RESET) { HAL_GPIO_EXTI_Callback(GPIO_Pin_4); EXTI_ClearITPendingBit(EXTI_Line4); @@ -522,18 +511,18 @@ void EXTI9_5_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - if( (EXTI_GetITStatus(EXTI_Line5)!=RESET)|| \ - (EXTI_GetITStatus(EXTI_Line6)!=RESET)|| \ - (EXTI_GetITStatus(EXTI_Line7)!=RESET)|| \ - (EXTI_GetITStatus(EXTI_Line8)!=RESET)|| \ - (EXTI_GetITStatus(EXTI_Line9)!=RESET) ) + if ((EXTI_GetITStatus(EXTI_Line5) != RESET) || + (EXTI_GetITStatus(EXTI_Line6) != RESET) || + (EXTI_GetITStatus(EXTI_Line7) != RESET) || + (EXTI_GetITStatus(EXTI_Line8) != RESET) || + (EXTI_GetITStatus(EXTI_Line9) != RESET)) { - HAL_GPIO_EXTI_Callback(GPIO_Pin_5); - HAL_GPIO_EXTI_Callback(GPIO_Pin_6); - HAL_GPIO_EXTI_Callback(GPIO_Pin_7); - HAL_GPIO_EXTI_Callback(GPIO_Pin_8); - HAL_GPIO_EXTI_Callback(GPIO_Pin_9); - EXTI_ClearITPendingBit(EXTI_Line5|EXTI_Line6|EXTI_Line7|EXTI_Line8|EXTI_Line9); + HAL_GPIO_EXTI_Callback(GPIO_Pin_5); + HAL_GPIO_EXTI_Callback(GPIO_Pin_6); + HAL_GPIO_EXTI_Callback(GPIO_Pin_7); + HAL_GPIO_EXTI_Callback(GPIO_Pin_8); + HAL_GPIO_EXTI_Callback(GPIO_Pin_9); + EXTI_ClearITPendingBit(EXTI_Line5 | EXTI_Line6 | EXTI_Line7 | EXTI_Line8 | EXTI_Line9); } rt_interrupt_leave(); FREE_INT_SP(); @@ -542,29 +531,29 @@ void EXTI9_5_IRQHandler(void) int rt_hw_pin_init(void) { #if defined(RCC_APB2Periph_GPIOA) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); #if defined(RCC_APB2Periph_GPIOB) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); #if defined(RCC_APB2Periph_GPIOC) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); #if defined(RCC_APB2Periph_GPIOD) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); #if defined(RCC_APB2Periph_GPIOE) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); #if defined(RCC_APB2Periph_GPIOF) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE); #if defined(RCC_APB2Periph_GPIOG) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE); #if defined(RCC_APB2Periph_GPIOH) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOH , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOH, ENABLE); #if defined(RCC_APB2Periph_GPIOI) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOI , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOI, ENABLE); #if defined(RCC_APB2Periph_GPIOJ) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOJ , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOJ, ENABLE); #if defined(RCC_APB2Periph_GPIOK) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOK , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOK, ENABLE); #if defined(RCC_APB2Periph_GPIOZ) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOZ , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOZ, ENABLE); #endif /* defined(RCC_APB2Periph_GPIOZ) */ #endif /* defined(RCC_APB2Periph_GPIOK) */ #endif /* defined(RCC_APB2Periph_GPIOJ) */ diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_timer.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_timer.c index f58196620b..6727c1e2cd 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_timer.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_timer.c @@ -12,12 +12,13 @@ #include <rtdevice.h> #ifdef BSP_USING_CLOCK_TIMER -#define DBG_TAG "TIM" -#define DBG_LVL DBG_LOG +#define DBG_TAG "TIM" +#define DBG_LVL DBG_LOG #include <rtdbg.h> #include "drv_timer.h" #include "board.h" +#include "drv_common.h" #ifdef RT_USING_CLOCK_TIME @@ -55,8 +56,7 @@ enum #endif }; -static struct ch32_clock_timer ch32_clock_timer_obj[] = -{ +static struct ch32_clock_timer ch32_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, #endif @@ -107,7 +107,7 @@ void ch32_get_pclk_doubler(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_double *pclk1_doubler = 1; *pclk2_doubler = 1; - if((RCC->CFGR0 & RCC_PPRE1) == RCC_PPRE1_DIV1) + if ((RCC->CFGR0 & RCC_PPRE1) == RCC_PPRE1_DIV1) { *pclk1_doubler = 1; } @@ -116,7 +116,7 @@ void ch32_get_pclk_doubler(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_double *pclk1_doubler = 2; } - if((RCC->CFGR0 & RCC_PPRE2) == RCC_PPRE2_DIV1) + if ((RCC->CFGR0 & RCC_PPRE2) == RCC_PPRE2_DIV1) { *pclk2_doubler = 1; } @@ -139,19 +139,19 @@ static void ch32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32 RCC_GetClocksFreq(&RCC_ClockStruct); ch32_get_pclk_doubler(&pclk1_doubler, &pclk2_doubler); - if(state) + if (state) { tim = (TIM_HandleTypeDef *)timer->parent.user_data; tim_device = (struct ch32_clock_timer *)timer; -#if defined (SOC_RISCV_SERIES_CH32V2) - if(tim->instance == TIM1) +#if defined(SOC_RISCV_SERIES_CH32V2) + if (tim->instance == TIM1) #elif defined(SOC_RISCV_SERIES_CH32V3) - if(tim->instance == TIM1 || tim->instance == TIM8 || - tim->instance == TIM9 || tim->instance == TIM10) + if (tim->instance == TIM1 || tim->instance == TIM8 || + tim->instance == TIM9 || tim->instance == TIM10) #else #error " unsupported CH32 series! " - if(RT_NULL) + if (RT_NULL) #endif { RCC_APB2PeriphClockCmd(tim->rcc, ENABLE); @@ -167,17 +167,17 @@ static void ch32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32 tim->init.TIM_Period = 10000 - 1; tim->init.TIM_RepetitionCounter = 0; - if(timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { tim->init.TIM_CounterMode = TIM_CounterMode_Up; } else { - tim->init.TIM_CounterMode = TIM_CounterMode_Down; + tim->init.TIM_CounterMode = TIM_CounterMode_Down; } -#if defined (SOC_RISCV_SERIES_CH32V3) +#if defined(SOC_RISCV_SERIES_CH32V3) /* TIM6 and TIM7 only support counter up mode */ - if(tim->instance == TIM6 || tim->instance == TIM7) + if (tim->instance == TIM6 || tim->instance == TIM7) { tim->init.TIM_CounterMode = TIM_CounterMode_Up; } @@ -273,14 +273,14 @@ static rt_err_t ch32_clock_timer_control(struct rt_clock_timer_device *timer, rt ch32_get_pclk_doubler(&pclk1_doubler, &pclk2_doubler); RCC_GetClocksFreq(&RCC_ClockStruct); -#if defined (SOC_RISCV_SERIES_CH32V2) - if(tim->instance == TIM1) +#if defined(SOC_RISCV_SERIES_CH32V2) + if (tim->instance == TIM1) #elif defined(SOC_RISCV_SERIES_CH32V3) - if(tim->instance == TIM1 || tim->instance == TIM8 || - tim->instance == TIM9 || tim->instance == TIM10) + if (tim->instance == TIM1 || tim->instance == TIM8 || + tim->instance == TIM9 || tim->instance == TIM10) #else #error " unsupported CH32 series! " - if(RT_NULL) + if (RT_NULL) #endif { val = RCC_ClockStruct.PCLK2_Frequency * pclk2_doubler / freq; @@ -336,8 +336,7 @@ static rt_err_t ch32_clock_timer_control(struct rt_clock_timer_device *timer, rt } static const struct rt_clock_timer_info ch32_clock_timer_info = TIM_DEV_INFO_CONFIG; -static const struct rt_clock_timer_ops ch32_clock_timer_ops = -{ +static const struct rt_clock_timer_ops ch32_clock_timer_ops = { ch32_clock_timer_init, ch32_clock_timer_start, ch32_clock_timer_stop, @@ -351,7 +350,7 @@ static void ch32_clock_timer_isr(struct rt_clock_timer_device *device) struct ch32_clock_timer *clock_timer = RT_NULL; clock_timer = rt_container_of(device, struct ch32_clock_timer, device); - if(TIM_GetITStatus(clock_timer->handle.instance, TIM_IT_Update) != RESET) + if (TIM_GetITStatus(clock_timer->handle.instance, TIM_IT_Update) != RESET) { rt_clock_timer_isr(device); TIM_ClearITPendingBit(clock_timer->handle.instance, TIM_IT_Update); @@ -359,7 +358,7 @@ static void ch32_clock_timer_isr(struct rt_clock_timer_device *device) } #ifdef BSP_USING_TIM1 -void TIM1_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM1_UP_IRQHandler(void) WCH_IRQ_ATTR; void TIM1_UP_IRQHandler(void) { GET_INT_SP(); @@ -371,7 +370,7 @@ void TIM1_UP_IRQHandler(void) #endif /* BSP_USING_TIM1 */ #ifdef BSP_USING_TIM2 -void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM2_IRQHandler(void) WCH_IRQ_ATTR; void TIM2_IRQHandler(void) { GET_INT_SP(); @@ -383,7 +382,7 @@ void TIM2_IRQHandler(void) #endif /* BSP_USING_TIM2 */ #ifdef BSP_USING_TIM3 -void TIM3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM3_IRQHandler(void) WCH_IRQ_ATTR; void TIM3_IRQHandler(void) { GET_INT_SP(); @@ -395,7 +394,7 @@ void TIM3_IRQHandler(void) #endif /* BSP_USING_TIM3 */ #ifdef BSP_USING_TIM4 -void TIM4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM4_IRQHandler(void) WCH_IRQ_ATTR; void TIM4_IRQHandler(void) { GET_INT_SP(); @@ -407,7 +406,7 @@ void TIM4_IRQHandler(void) #endif /* BSP_USING_TIM4 */ #ifdef BSP_USING_TIM5 -void TIM5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM5_IRQHandler(void) WCH_IRQ_ATTR; void TIM5_IRQHandler(void) { GET_INT_SP(); @@ -419,7 +418,7 @@ void TIM5_IRQHandler(void) #endif /* BSP_USING_TIM5 */ #ifdef BSP_USING_TIM6 -void TIM6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM6_IRQHandler(void) WCH_IRQ_ATTR; void TIM6_IRQHandler(void) { GET_INT_SP(); @@ -431,7 +430,7 @@ void TIM6_IRQHandler(void) #endif /* BSP_USING_TIM6 */ #ifdef BSP_USING_TIM7 -void TIM7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM7_IRQHandler(void) WCH_IRQ_ATTR; void TIM7_IRQHandler(void) { GET_INT_SP(); @@ -443,7 +442,7 @@ void TIM7_IRQHandler(void) #endif /* BSP_USING_TIM7 */ #ifdef BSP_USING_TIM8 -void TIM8_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM8_UP_IRQHandler(void) WCH_IRQ_ATTR; void TIM8_UP_IRQHandler(void) { GET_INT_SP(); @@ -455,7 +454,7 @@ void TIM8_UP_IRQHandler(void) #endif /* BSP_USING_TIM8 */ #ifdef BSP_USING_TIM9 -void TIM9_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM9_UP_IRQHandler(void) WCH_IRQ_ATTR; void TIM9_UP_IRQHandler(void) { GET_INT_SP(); @@ -467,7 +466,7 @@ void TIM9_UP_IRQHandler(void) #endif /* BSP_USING_TIM9 */ #ifdef BSP_USING_TIM10 -void TIM10_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM10_UP_IRQHandler(void) WCH_IRQ_ATTR; void TIM10_UP_IRQHandler(void) { GET_INT_SP(); @@ -486,9 +485,9 @@ static int rt_hw_timer_init(void) for (i = 0; i < sizeof(ch32_clock_timer_obj) / sizeof(ch32_clock_timer_obj[0]); i++) { ch32_clock_timer_obj[i].device.info = &ch32_clock_timer_info; - ch32_clock_timer_obj[i].device.ops = &ch32_clock_timer_ops; + ch32_clock_timer_obj[i].device.ops = &ch32_clock_timer_ops; result = rt_clock_timer_register(&ch32_clock_timer_obj[i].device, - ch32_clock_timer_obj[i].name, (void *)&ch32_clock_timer_obj[i].handle); + ch32_clock_timer_obj[i].name, (void *)&ch32_clock_timer_obj[i].handle); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart.c index 9daa586c35..db6ede9d70 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart.c @@ -9,19 +9,20 @@ */ #include "board.h" +#include "drv_common.h" #include <rtdevice.h> #include <drv_usart.h> #ifdef RT_USING_SERIAL //#define DRV_DEBUG -#define LOG_TAG "drv.uart" +#define LOG_TAG "drv.uart" #include <drv_log.h> #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \ !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) - #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif enum @@ -54,14 +55,17 @@ enum /* If you want to use other serial ports, please follow UART1 to complete other serial ports. For clock configuration, */ -static struct ch32_uart_hw_config uart_hw_config[] = -{ +static struct ch32_uart_hw_config uart_hw_config[] = { #ifdef BSP_USING_UART1 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB2Periph_USART1, RCC_APB2Periph_GPIOA, + RCC_APB2Periph_USART1, + RCC_APB2Periph_GPIOA, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOA, GPIO_Pin_9, /* Tx */GPIOA, GPIO_Pin_10, /* Rx */ + GPIOA, + GPIO_Pin_9, + /* Tx */ GPIOA, + GPIO_Pin_10, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -70,9 +74,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART2 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_USART2, RCC_APB2Periph_GPIOA, + RCC_APB1Periph_USART2, + RCC_APB2Periph_GPIOA, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOA, GPIO_Pin_2, /* Tx */GPIOA, GPIO_Pin_3, /* Rx */ + GPIOA, + GPIO_Pin_2, + /* Tx */ GPIOA, + GPIO_Pin_3, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -81,9 +89,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART3 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_USART3, RCC_APB2Periph_GPIOB, + RCC_APB1Periph_USART3, + RCC_APB2Periph_GPIOB, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOB, GPIO_Pin_10, /* Tx */GPIOB, GPIO_Pin_11, /* Rx */ + GPIOB, + GPIO_Pin_10, + /* Tx */ GPIOB, + GPIO_Pin_11, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -92,9 +104,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART4 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_UART4, RCC_APB2Periph_GPIOC, + RCC_APB1Periph_UART4, + RCC_APB2Periph_GPIOC, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOC, GPIO_Pin_10, /* Tx */GPIOC, GPIO_Pin_11, /* Rx */ + GPIOC, + GPIO_Pin_10, + /* Tx */ GPIOC, + GPIO_Pin_11, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -103,9 +119,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART5 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_UART5, RCC_APB2Periph_GPIOC|RCC_APB2Periph_GPIOD, + RCC_APB1Periph_UART5, + RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOC, GPIO_Pin_12, /* Tx */GPIOD, GPIO_Pin_2, /* Rx */ + GPIOC, + GPIO_Pin_12, + /* Tx */ GPIOD, + GPIO_Pin_2, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -114,9 +134,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART6 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_UART6, RCC_APB2Periph_GPIOC, + RCC_APB1Periph_UART6, + RCC_APB2Periph_GPIOC, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOC, GPIO_Pin_0, /* Tx */GPIOC, GPIO_Pin_1, /* Rx */ + GPIOC, + GPIO_Pin_0, + /* Tx */ GPIOC, + GPIO_Pin_1, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -125,9 +149,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART7 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_UART7, RCC_APB2Periph_GPIOC, + RCC_APB1Periph_UART7, + RCC_APB2Periph_GPIOC, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOC, GPIO_Pin_2, /* Tx */GPIOC, GPIO_Pin_3, /* Rx */ + GPIOC, + GPIO_Pin_2, + /* Tx */ GPIOC, + GPIO_Pin_3, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -136,9 +164,13 @@ static struct ch32_uart_hw_config uart_hw_config[] = #ifdef BSP_USING_UART8 { /* clock configuration, please refer to ch32v30x_rcc.h */ - RCC_APB1Periph_UART8, RCC_APB2Periph_GPIOC, + RCC_APB1Periph_UART8, + RCC_APB2Periph_GPIOC, /* GPIO configuration : TX_Port,TX_Pin, RX_Port,RX_Pin */ - GPIOC, GPIO_Pin_4, /* Tx */GPIOC, GPIO_Pin_5, /* Rx */ + GPIOC, + GPIO_Pin_4, + /* Tx */ GPIOC, + GPIO_Pin_5, /* Rx */ /* Whether to enable port remapping, you can refer to ch32v30x_gpio.h file, for example, USART1 needs to be turned on, you can use GPIO_Remap_USART1 */ GPIO_Remap_NONE, @@ -146,8 +178,7 @@ static struct ch32_uart_hw_config uart_hw_config[] = #endif }; -static struct ch32_uart_config uart_config[] = -{ +static struct ch32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 { "uart1", @@ -206,21 +237,21 @@ static struct ch32_uart_config uart_config[] = #endif }; -static struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = { 0 }; static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct ch32_uart *uart; - GPIO_InitTypeDef GPIO_InitStructure={0}; + GPIO_InitTypeDef GPIO_InitStructure = { 0 }; RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct ch32_uart *) serial->parent.user_data; + uart = (struct ch32_uart *)serial->parent.user_data; - uart->Init.USART_BaudRate = cfg->baud_rate; - uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - uart->Init.USART_Mode = USART_Mode_Rx|USART_Mode_Tx; + uart->Init.USART_BaudRate = cfg->baud_rate; + uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + uart->Init.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; switch (cfg->data_bits) { @@ -238,34 +269,34 @@ static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_co switch (cfg->stop_bits) { case STOP_BITS_1: - uart->Init.USART_StopBits = USART_StopBits_1; + uart->Init.USART_StopBits = USART_StopBits_1; break; case STOP_BITS_2: - uart->Init.USART_StopBits = USART_StopBits_2; + uart->Init.USART_StopBits = USART_StopBits_2; break; default: - uart->Init.USART_StopBits = USART_StopBits_1; + uart->Init.USART_StopBits = USART_StopBits_1; break; } switch (cfg->parity) { case PARITY_NONE: - uart->Init.USART_Parity = USART_Parity_No; + uart->Init.USART_Parity = USART_Parity_No; break; case PARITY_ODD: - uart->Init.USART_Parity = USART_Parity_Odd; + uart->Init.USART_Parity = USART_Parity_Odd; break; case PARITY_EVEN: - uart->Init.USART_Parity = USART_Parity_Even; + uart->Init.USART_Parity = USART_Parity_Even; break; default: - uart->Init.USART_Parity = USART_Parity_No; + uart->Init.USART_Parity = USART_Parity_No; break; } /* UART hardware configuration, including clock and GPIO, etc. */ RCC_APB2PeriphClockCmd(uart->hw_config->gpio_periph_clock, ENABLE); - if(uart->config->Instance == USART1) + if (uart->config->Instance == USART1) { RCC_APB2PeriphClockCmd(uart->hw_config->uart_periph_clock, ENABLE); } @@ -274,7 +305,7 @@ static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_co RCC_APB1PeriphClockCmd(uart->hw_config->uart_periph_clock, ENABLE); } - if(uart->hw_config->remap != GPIO_Remap_NONE) + if (uart->hw_config->remap != GPIO_Remap_NONE) { RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); GPIO_PinRemapConfig(uart->hw_config->remap, ENABLE); @@ -288,7 +319,7 @@ static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_co GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(uart->hw_config->rx_gpio_port, &GPIO_InitStructure); - USART_Init(uart->config->Instance,&uart->Init); + USART_Init(uart->config->Instance, &uart->Init); USART_Cmd(uart->config->Instance, ENABLE); return RT_EOK; @@ -306,14 +337,14 @@ static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg /* disable rx irq */ NVIC_DisableIRQ(uart->config->irq_type); /* disable interrupt */ - USART_ITConfig(uart->config->Instance,USART_IT_RXNE,DISABLE); + USART_ITConfig(uart->config->Instance, USART_IT_RXNE, DISABLE); break; /* enable interrupt */ case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->config->irq_type); /* enable interrupt */ - USART_ITConfig(uart->config->Instance, USART_IT_RXNE,ENABLE); + USART_ITConfig(uart->config->Instance, USART_IT_RXNE, ENABLE); break; } return RT_EOK; @@ -350,7 +381,7 @@ static rt_ssize_t ch32dma_transmit(struct rt_serial_device *serial, rt_uint8_t * static void uart_isr(struct rt_serial_device *serial) { - struct ch32_uart *uart = (struct ch32_uart *) serial->parent.user_data; + struct ch32_uart *uart = (struct ch32_uart *)serial->parent.user_data; RT_ASSERT(uart != RT_NULL); if (USART_GetITStatus(uart->config->Instance, USART_IT_RXNE) != RESET) { @@ -359,8 +390,7 @@ static void uart_isr(struct rt_serial_device *serial) } } -static const struct rt_uart_ops ch32_uart_ops = -{ +static const struct rt_uart_ops ch32_uart_ops = { ch32_configure, ch32_control, ch32_putc, @@ -369,11 +399,7 @@ static const struct rt_uart_ops ch32_uart_ops = }; #ifdef BSP_USING_UART1 -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART1_IRQHandler(void) __attribute__((interrupt())); -#else -void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART1_IRQHandler(void) WCH_IRQ_ATTR; void USART1_IRQHandler(void) { GET_INT_SP(); @@ -385,11 +411,7 @@ void USART1_IRQHandler(void) #endif #ifdef BSP_USING_UART2 -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART2_IRQHandler(void) __attribute__((interrupt())); -#else -void USART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART2_IRQHandler(void) WCH_IRQ_ATTR; void USART2_IRQHandler(void) { GET_INT_SP(); @@ -401,11 +423,7 @@ void USART2_IRQHandler(void) #endif #ifdef BSP_USING_UART3 -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART3_IRQHandler(void) __attribute__((interrupt())); -#else -void USART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART3_IRQHandler(void) WCH_IRQ_ATTR; void USART3_IRQHandler(void) { GET_INT_SP(); @@ -417,11 +435,7 @@ void USART3_IRQHandler(void) #endif #ifdef BSP_USING_UART4 -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART4_IRQHandler(void) __attribute__((interrupt())); -#else -void UART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART4_IRQHandler(void) WCH_IRQ_ATTR; void UART4_IRQHandler(void) { GET_INT_SP(); @@ -433,11 +447,7 @@ void UART4_IRQHandler(void) #endif #ifdef BSP_USING_UART5 -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART5_IRQHandler(void) __attribute__((interrupt())); -#else -void UART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART5_IRQHandler(void) WCH_IRQ_ATTR; void UART5_IRQHandler(void) { GET_INT_SP(); @@ -449,11 +459,7 @@ void UART5_IRQHandler(void) #endif #ifdef BSP_USING_UART6 -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART6_IRQHandler(void) __attribute__((interrupt())); -#else -void UART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART6_IRQHandler(void) WCH_IRQ_ATTR; void UART6_IRQHandler(void) { GET_INT_SP(); @@ -465,11 +471,7 @@ void UART6_IRQHandler(void) #endif #ifdef BSP_USING_UART7 -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART7_IRQHandler(void) __attribute__((interrupt())); -#else -void UART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART7_IRQHandler(void) WCH_IRQ_ATTR; void UART7_IRQHandler(void) { GET_INT_SP(); @@ -481,11 +483,7 @@ void UART7_IRQHandler(void) #endif #ifdef BSP_USING_UART8 -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART8_IRQHandler(void) __attribute__((interrupt())); -#else -void UART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART8_IRQHandler(void) WCH_IRQ_ATTR; void UART8_IRQHandler(void) { GET_INT_SP(); @@ -505,27 +503,25 @@ int rt_hw_usart_init(void) for (int i = 0; i < obj_num; i++) { /* init UART object */ - uart_obj[i].config = &uart_config[i]; - uart_obj[i].hw_config = &uart_hw_config[i]; - uart_obj[i].serial.ops = &ch32_uart_ops; + uart_obj[i].config = &uart_config[i]; + uart_obj[i].hw_config = &uart_hw_config[i]; + uart_obj[i].serial.ops = &ch32_uart_ops; uart_obj[i].serial.config = config; /* Hardware initialization is required, otherwise it will not be registered into the device framework */ - if(uart_obj[i].hw_config->gpio_periph_clock == 0) + if (uart_obj[i].hw_config->gpio_periph_clock == 0) { LOG_E("You did not perform hardware initialization for %s", uart_obj[i].config->name); continue; } - if(uart_obj[i].hw_config->uart_periph_clock == 0) + if (uart_obj[i].hw_config->uart_periph_clock == 0) { LOG_E("You did not perform hardware initialization for %s", uart_obj[i].config->name); continue; } /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, - RT_DEVICE_FLAG_RDWR - | RT_DEVICE_FLAG_INT_RX - , &uart_obj[i]); + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart_obj[i]); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart_v2.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart_v2.c index f9e45964b3..038d43d0d4 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart_v2.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usart_v2.c @@ -11,6 +11,7 @@ #include <rtthread.h> #include <rtdevice.h> #include "board.h" +#include "drv_common.h" #include "drv_usart_v2.h" #ifdef RT_USING_SERIAL_V2 #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) @@ -47,62 +48,60 @@ enum #endif }; - - struct DMA_HandleTypeDef { - DMA_Channel_TypeDef *Instance; /* DMA registers base address */ + DMA_Channel_TypeDef *Instance; /* DMA registers base address */ struct UART_HandleTypeDef *Parent; - DMA_InitTypeDef Init; /* DMA initialization parameters */ - rt_uint32_t dma_rcc; - IRQn_Type dma_irq; - void (*DMA_ITC_Callback)(struct UART_HandleTypeDef *huart) ;/* DMA transfer complete callback */ - void (*DMA_IE_Callback)(void); /* DMA error complete callback */ + DMA_InitTypeDef Init; /* DMA initialization parameters */ + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + void (*DMA_ITC_Callback)(struct UART_HandleTypeDef *huart); /* DMA transfer complete callback */ + void (*DMA_IE_Callback)(void); /* DMA error complete callback */ }; struct UART_HandleTypeDef { - USART_TypeDef *Instance; /*!< UART registers base address */ - USART_InitTypeDef Init; /*!< UART communication parameters */ - struct DMA_HandleTypeDef *HDMA_Tx; /*!< UART Tx DMA handle parameters */ - struct DMA_HandleTypeDef *HDMA_Rx; /*!< UART Rx DMA handle parameters */ + USART_TypeDef *Instance; /*!< UART registers base address */ + USART_InitTypeDef Init; /*!< UART communication parameters */ + struct DMA_HandleTypeDef *HDMA_Tx; /*!< UART Tx DMA handle parameters */ + struct DMA_HandleTypeDef *HDMA_Rx; /*!< UART Rx DMA handle parameters */ }; struct ch32_uart_config { - const char *name; + const char *name; USART_TypeDef *Instance; - rt_uint32_t rcc; - IRQn_Type irq_type; - GPIO_TypeDef *tx_port; - uint16_t tx_pin; - GPIO_TypeDef *rx_port; - uint16_t rx_pin; + rt_uint32_t rcc; + IRQn_Type irq_type; + GPIO_TypeDef *tx_port; + uint16_t tx_pin; + GPIO_TypeDef *rx_port; + uint16_t rx_pin; }; struct ch32_uart { struct UART_HandleTypeDef handle; - struct ch32_uart_config *config; + struct ch32_uart_config *config; #ifdef RT_SERIAL_USING_DMA struct { struct DMA_HandleTypeDef handle; - rt_size_t remaining_cnt; + rt_size_t remaining_cnt; } dma_rx; struct { struct DMA_HandleTypeDef handle; } dma_tx; #endif - rt_uint16_t uart_dma_flag; + rt_uint16_t uart_dma_flag; struct rt_serial_device serial; }; /********************************************************************************************************************************** */ /******************************* funtion ****************************************************************************************** */ -static void ch32_uart_get_config(void); +static void ch32_uart_get_config(void); static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg); -static void NVIC_Set(IRQn_Type irq, FunctionalState state); +static void NVIC_Set(IRQn_Type irq, FunctionalState state); #ifdef RT_SERIAL_USING_DMA static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag); static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); @@ -110,34 +109,29 @@ void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart); static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma); #endif -static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin); +static void GPIOInit(GPIO_TypeDef *GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin); /********************************************************************************************************************************** */ /******************************** value ******************************************************************************************* */ -static struct ch32_uart_config uart_config[] = -{ +static struct ch32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 - { - .name = "uart1", - .Instance = USART1, - .rcc = RCC_APB2Periph_USART1, - .irq_type = USART1_IRQn, - .tx_port = GPIOA, - .tx_pin = GPIO_Pin_9, - .rx_port = GPIOA, - .rx_pin = GPIO_Pin_10 - }, + { .name = "uart1", + .Instance = USART1, + .rcc = RCC_APB2Periph_USART1, + .irq_type = USART1_IRQn, + .tx_port = GPIOA, + .tx_pin = GPIO_Pin_9, + .rx_port = GPIOA, + .rx_pin = GPIO_Pin_10 }, #endif #ifdef BSP_USING_UART2 - { - .name = "uart2", - .Instance = USART2, - .rcc = RCC_APB1Periph_USART2, - .irq_type = USART2_IRQn, - .tx_port = GPIOA, - .tx_pin = GPIO_Pin_2, - .rx_port = GPIOA, - .rx_pin = GPIO_Pin_3 - }, + { .name = "uart2", + .Instance = USART2, + .rcc = RCC_APB1Periph_USART2, + .irq_type = USART2_IRQn, + .tx_port = GPIOA, + .tx_pin = GPIO_Pin_2, + .rx_port = GPIOA, + .rx_pin = GPIO_Pin_3 }, #endif #ifdef BSP_USING_UART3 { @@ -145,10 +139,10 @@ static struct ch32_uart_config uart_config[] = .Instance = USART3, .rcc = RCC_APB1Periph_USART3, .irq_type = USART3_IRQn, - .tx_port = GPIOB, - .tx_pin = GPIO_Pin_10, - .rx_port = GPIOB, - .rx_pin = GPIO_Pin_11, + .tx_port = GPIOB, + .tx_pin = GPIO_Pin_10, + .rx_port = GPIOB, + .rx_pin = GPIO_Pin_11, }, #endif #ifdef BSP_USING_UART4 @@ -157,10 +151,10 @@ static struct ch32_uart_config uart_config[] = .Instance = UART4, .rcc = RCC_APB1Periph_UART4, .irq_type = UART4_IRQn, - .tx_port = GPIOC, - .tx_pin = GPIO_Pin_10, - .rx_port = GPIOC, - .rx_pin = GPIO_Pin_11, + .tx_port = GPIOC, + .tx_pin = GPIO_Pin_10, + .rx_port = GPIOC, + .rx_pin = GPIO_Pin_11, }, #endif #ifdef BSP_USING_UART5 @@ -169,10 +163,10 @@ static struct ch32_uart_config uart_config[] = .Instance = UART5, .rcc = RCC_APB1Periph_UART5, .irq_type = UART5_IRQn, - .tx_port = GPIOC, - .tx_pin = GPIO_Pin_12, - .rx_port = GPIOD, - .rx_pin = GPIO_Pin_2, + .tx_port = GPIOC, + .tx_pin = GPIO_Pin_12, + .rx_port = GPIOD, + .rx_pin = GPIO_Pin_2, }, #endif #ifdef BSP_USING_UART6 @@ -181,10 +175,10 @@ static struct ch32_uart_config uart_config[] = .Instance = UART6, .rcc = RCC_APB1Periph_UART6, .irq_type = UART6_IRQn, - .tx_port = GPIOC, - .tx_pin = GPIO_Pin_0, - .rx_port = GPIOC, - .rx_pin = GPIO_Pin_1, + .tx_port = GPIOC, + .tx_pin = GPIO_Pin_0, + .rx_port = GPIOC, + .rx_pin = GPIO_Pin_1, }, #endif @@ -194,10 +188,10 @@ static struct ch32_uart_config uart_config[] = .Instance = UART7, .rcc = RCC_APB1Periph_UART7, .irq_type = UART7_IRQn, - .tx_port = GPIOC, - .tx_pin = GPIO_Pin_2, - .rx_port = GPIOC, - .rx_pin = GPIO_Pin_3, + .tx_port = GPIOC, + .tx_pin = GPIO_Pin_2, + .rx_port = GPIOC, + .rx_pin = GPIO_Pin_3, }, #endif #ifdef BSP_USING_UART8 @@ -206,17 +200,17 @@ static struct ch32_uart_config uart_config[] = .Instance = UART8, .rcc = RCC_APB1Periph_UART8, .irq_type = UART8_IRQn, - .tx_port = GPIOC, - .tx_pin = GPIO_Pin_4, - .rx_port = GPIOC, - .rx_pin = GPIO_Pin_5, + .tx_port = GPIOC, + .tx_pin = GPIO_Pin_4, + .rx_port = GPIOC, + .rx_pin = GPIO_Pin_5, }, #endif }; static struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(struct ch32_uart_config)]; /********************************************************************************************************************************** */ -static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin) +static void GPIOInit(GPIO_TypeDef *GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin) { GPIO_InitTypeDef GPIO_InitStructure; /* Enable the GPIO Clock */ @@ -241,15 +235,15 @@ static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeD RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); } /* Configure the GPIO pin */ - GPIO_InitStructure.GPIO_Pin = Pin; - GPIO_InitStructure.GPIO_Mode = mode; + GPIO_InitStructure.GPIO_Pin = Pin; + GPIO_InitStructure.GPIO_Mode = mode; GPIO_InitStructure.GPIO_Speed = speed; GPIO_Init(GPIOx, &GPIO_InitStructure); } static void ch32_uart_init(struct ch32_uart_config *uart) { - if (uart->Instance==USART1) + if (uart->Instance == USART1) { RCC_APB2PeriphClockCmd(uart->rcc, ENABLE); } @@ -361,23 +355,31 @@ static void NVIC_Set(IRQn_Type irq, FunctionalState state) static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct ch32_uart *uart; - rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ch32_uart, serial); if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) { if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + } else + { ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } } else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) { if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + } else + { ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } } switch (cmd) @@ -393,7 +395,6 @@ static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg if (ctrl_arg & RT_DEVICE_FLAG_INT_TX) { USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE); - } #ifdef RT_SERIAL_USING_DMA if (ctrl_arg & RT_DEVICE_FLAG_DMA_RX) @@ -401,7 +402,6 @@ static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg NVIC_Set(uart->dma_rx.handle.dma_irq, DISABLE); USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, DISABLE); DMA_DeInit(uart->dma_rx.handle.Instance); - } else if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) { @@ -418,17 +418,17 @@ static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) { ch32_uart_dma_config(serial, ctrl_arg); - } else + { ch32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg); + } break; #endif case RT_DEVICE_CTRL_SET_INT: NVIC_Set(uart->config->irq_type, ENABLE); if (ctrl_arg & RT_DEVICE_FLAG_INT_RX) { - USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, ENABLE); USART_ClearITPendingBit(uart->config->Instance, USART_IT_RXNE); USART_ClearFlag(uart->handle.Instance, USART_FLAG_RXNE); @@ -443,9 +443,13 @@ static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CHECK_OPTMODE: if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) + { return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + } else + { return RT_SERIAL_TX_BLOCKING_BUFFER; + } case RT_DEVICE_CTRL_CLOSE: #ifdef RT_SERIAL_USING_DMA DMA_Cmd(uart->dma_tx.handle.Instance, DISABLE); @@ -470,9 +474,9 @@ static int ch32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ch32_uart, serial); - while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET); + while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET); uart->config->Instance->DATAR = c; -/* Transmit Data */ + /* Transmit Data */ return 1; } @@ -488,9 +492,9 @@ static int ch32_getc(struct rt_serial_device *serial) } static rt_ssize_t ch32_transmit(struct rt_serial_device *serial, - rt_uint8_t *buf, - rt_size_t size, - rt_uint32_t tx_flag) + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) { struct ch32_uart *uart; @@ -513,7 +517,6 @@ static rt_ssize_t ch32_transmit(struct rt_serial_device *serial, return size; } - /** * Uart common interrupt process. This need add to uart ISR. * @@ -541,7 +544,7 @@ static void uart_isr(struct rt_serial_device *serial) { USART_SendData(uart->handle.Instance, put_char); } - USART_ClearITPendingBit(uart->config->Instance, USART_IT_TXE); + USART_ClearITPendingBit(uart->config->Instance, USART_IT_TXE); } else if (USART_GetITStatus(uart->handle.Instance, USART_IT_TC) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TC)) { @@ -551,25 +554,17 @@ static void uart_isr(struct rt_serial_device *serial) } #ifdef RT_SERIAL_USING_DMA - else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_IDLE) != RESET) - && (USART_GetITStatus(uart->handle.Instance, USART_IT_IDLE) != RESET)) + else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_IDLE) != RESET) && (USART_GetITStatus(uart->handle.Instance, USART_IT_IDLE) != RESET)) { /* clean IDLEF flag */ dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); USART_ReceiveData(uart->handle.Instance); } #endif - } - - #if defined(BSP_USING_UART1) -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART1_IRQHandler(void) __attribute__((interrupt())); -#else -void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART1_IRQHandler(void) WCH_IRQ_ATTR; void USART1_IRQHandler(void) { GET_INT_SP(); @@ -583,11 +578,7 @@ void USART1_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel5_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel5_IRQHandler(void) { GET_INT_SP(); @@ -603,11 +594,7 @@ void DMA1_Channel5_IRQHandler(void) #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel4_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel4_IRQHandler(void) { GET_INT_SP(); @@ -624,11 +611,7 @@ void DMA1_Channel4_IRQHandler(void) #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART2_IRQHandler(void) __attribute__((interrupt())); -#else -void USART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART2_IRQHandler(void) WCH_IRQ_ATTR; void USART2_IRQHandler(void) { GET_INT_SP(); @@ -642,11 +625,7 @@ void USART2_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel6_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel6_IRQHandler(void) { GET_INT_SP(); @@ -661,11 +640,7 @@ void DMA1_Channel6_IRQHandler(void) } #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel7_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel7_IRQHandler(void) { GET_INT_SP(); @@ -682,11 +657,7 @@ void DMA1_Channel7_IRQHandler(void) #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#if defined (SOC_RISCV_SERIES_CH32V2) -void USART3_IRQHandler(void) __attribute__((interrupt())); -#else -void USART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void USART3_IRQHandler(void) WCH_IRQ_ATTR; void USART3_IRQHandler(void) { GET_INT_SP(); @@ -700,11 +671,7 @@ void USART3_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel3_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel3_IRQHandler(void) { GET_INT_SP(); @@ -719,11 +686,7 @@ void DMA1_Channel3_IRQHandler(void) } #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA1_Channel2_IRQHandler(void) WCH_IRQ_ATTR; void DMA1_Channel2_IRQHandler(void) { GET_INT_SP(); @@ -740,11 +703,7 @@ void DMA1_Channel2_IRQHandler(void) #endif /* BSP_USING_UART3*/ #if defined(BSP_USING_UART4) -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART4_IRQHandler(void) __attribute__((interrupt())); -#else -void UART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART4_IRQHandler(void) WCH_IRQ_ATTR; void UART4_IRQHandler(void) { GET_INT_SP(); @@ -758,11 +717,7 @@ void UART4_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel3_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel3_IRQHandler(void) { GET_INT_SP(); @@ -778,11 +733,7 @@ void DMA2_Channel3_IRQHandler(void) #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel5_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel5_IRQHandler(void) { GET_INT_SP(); @@ -799,11 +750,7 @@ void DMA2_Channel5_IRQHandler(void) #endif /* BSP_USING_UART4*/ #if defined(BSP_USING_UART5) -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART5_IRQHandler(void) __attribute__((interrupt())); -#else -void UART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART5_IRQHandler(void) WCH_IRQ_ATTR; void UART5_IRQHandler(void) { GET_INT_SP(); @@ -817,11 +764,7 @@ void UART5_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel2_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel2_IRQHandler(void) { GET_INT_SP(); @@ -836,11 +779,7 @@ void DMA2_Channel2_IRQHandler(void) } #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel4_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel4_IRQHandler(void) { GET_INT_SP(); @@ -857,11 +796,7 @@ void DMA2_Channel4_IRQHandler(void) #endif /* BSP_USING_UART5*/ #if defined(BSP_USING_UART6) -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART6_IRQHandler(void) __attribute__((interrupt())); -#else -void UART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART6_IRQHandler(void) WCH_IRQ_ATTR; void UART6_IRQHandler(void) { GET_INT_SP(); @@ -875,11 +810,7 @@ void UART6_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel7_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel7_IRQHandler(void) { GET_INT_SP(); @@ -894,11 +825,7 @@ void DMA2_Channel7_IRQHandler(void) } #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel6_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel6_IRQHandler(void) { GET_INT_SP(); @@ -915,11 +842,7 @@ void DMA2_Channel6_IRQHandler(void) #endif /* BSP_USING_UART6*/ #if defined(BSP_USING_UART7) -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART7_IRQHandler(void) __attribute__((interrupt())); -#else -void UART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART7_IRQHandler(void) WCH_IRQ_ATTR; void UART7_IRQHandler(void) { GET_INT_SP(); @@ -933,11 +856,7 @@ void UART7_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel9_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel9_IRQHandler(void) { GET_INT_SP(); @@ -952,11 +871,7 @@ void DMA2_Channel9_IRQHandler(void) } #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel8_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel8_IRQHandler(void) { GET_INT_SP(); @@ -973,11 +888,7 @@ void DMA2_Channel8_IRQHandler(void) #endif /* BSP_USING_UART7*/ #if defined(BSP_USING_UART8) -#if defined (SOC_RISCV_SERIES_CH32V2) -void UART8_IRQHandler(void) __attribute__((interrupt())); -#else -void UART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void UART8_IRQHandler(void) WCH_IRQ_ATTR; void UART8_IRQHandler(void) { GET_INT_SP(); @@ -991,11 +902,7 @@ void UART8_IRQHandler(void) FREE_INT_SP(); } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel11_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel11_IRQHandler(void) { GET_INT_SP(); @@ -1010,11 +917,7 @@ void DMA2_Channel11_IRQHandler(void) } #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */ #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) -#if defined (SOC_RISCV_SERIES_CH32V2) -void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt())); -#else -void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -#endif +void DMA2_Channel10_IRQHandler(void) WCH_IRQ_ATTR; void DMA2_Channel10_IRQHandler(void) { GET_INT_SP(); @@ -1034,216 +937,216 @@ static void ch32_uart_get_config(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART1 - uart_obj[UART1_INDEX].serial.config = config; + uart_obj[UART1_INDEX].serial.config = config; uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE; uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE; - uart_obj[UART1_INDEX].handle.Instance = USART1; - uart_obj[UART1_INDEX].uart_dma_flag = 0; + uart_obj[UART1_INDEX].handle.Instance = USART1; + uart_obj[UART1_INDEX].uart_dma_flag = 0; #ifdef BSP_UART1_RX_USING_DMA - uart_obj[UART1_INDEX].handle.HDMA_Rx = &uart_obj[UART1_INDEX].dma_rx.handle; + uart_obj[UART1_INDEX].handle.HDMA_Rx = &uart_obj[UART1_INDEX].dma_rx.handle; uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE; - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART1_INDEX].dma_rx.handle.Parent = &uart_obj[UART1_INDEX].handle; - uart_obj[UART1_INDEX].dma_rx.handle.Instance = DMA1_Channel5; - uart_obj[UART1_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART1_INDEX].dma_rx.handle.dma_irq = DMA1_Channel5_IRQn; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART1_INDEX].dma_rx.handle.Parent = &uart_obj[UART1_INDEX].handle; + uart_obj[UART1_INDEX].dma_rx.handle.Instance = DMA1_Channel5; + uart_obj[UART1_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART1_INDEX].dma_rx.handle.dma_irq = DMA1_Channel5_IRQn; #endif #ifdef BSP_UART1_TX_USING_DMA - uart_obj[UART1_INDEX].handle.HDMA_Tx = &uart_obj[UART1_INDEX].dma_tx.handle; - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART1_INDEX].dma_tx.handle.Parent = &uart_obj[UART1_INDEX].handle; - uart_obj[UART1_INDEX].dma_tx.handle.Instance = DMA1_Channel4; - uart_obj[UART1_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART1_INDEX].dma_tx.handle.dma_irq = DMA1_Channel4_IRQn; + uart_obj[UART1_INDEX].handle.HDMA_Tx = &uart_obj[UART1_INDEX].dma_tx.handle; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART1_INDEX].dma_tx.handle.Parent = &uart_obj[UART1_INDEX].handle; + uart_obj[UART1_INDEX].dma_tx.handle.Instance = DMA1_Channel4; + uart_obj[UART1_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART1_INDEX].dma_tx.handle.dma_irq = DMA1_Channel4_IRQn; #endif #endif #ifdef BSP_USING_UART2 - uart_obj[UART2_INDEX].serial.config = config; + uart_obj[UART2_INDEX].serial.config = config; uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE; uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE; - uart_obj[UART2_INDEX].handle.Instance = USART2; - uart_obj[UART2_INDEX].uart_dma_flag = 0; + uart_obj[UART2_INDEX].handle.Instance = USART2; + uart_obj[UART2_INDEX].uart_dma_flag = 0; #ifdef BSP_UART2_RX_USING_DMA - uart_obj[UART2_INDEX].handle.HDMA_Rx = &uart_obj[UART2_INDEX].dma_rx.handle; + uart_obj[UART2_INDEX].handle.HDMA_Rx = &uart_obj[UART2_INDEX].dma_rx.handle; uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE; - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART2_INDEX].dma_rx.handle.Parent = &uart_obj[UART2_INDEX].handle; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART2_INDEX].dma_rx.handle.Parent = &uart_obj[UART2_INDEX].handle; uart_obj[UART2_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART2_INDEX].dma_rx.handle.Instance = DMA1_Channel6; - uart_obj[UART2_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART2_INDEX].dma_rx.handle.dma_irq = DMA1_Channel6_IRQn; + uart_obj[UART2_INDEX].dma_rx.handle.Instance = DMA1_Channel6; + uart_obj[UART2_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART2_INDEX].dma_rx.handle.dma_irq = DMA1_Channel6_IRQn; #endif #ifdef BSP_UART2_TX_USING_DMA - uart_obj[UART2_INDEX].handle.HDMA_Tx = &uart_obj[UART2_INDEX].dma_tx.handle; - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART2_INDEX].dma_tx.handle.Parent = &uart_obj[UART2_INDEX].handle; + uart_obj[UART2_INDEX].handle.HDMA_Tx = &uart_obj[UART2_INDEX].dma_tx.handle; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART2_INDEX].dma_tx.handle.Parent = &uart_obj[UART2_INDEX].handle; uart_obj[UART2_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART2_INDEX].dma_tx.handle.Instance = DMA1_Channel7; - uart_obj[UART2_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART2_INDEX].dma_tx.handle.dma_irq = DMA1_Channel7_IRQn; + uart_obj[UART2_INDEX].dma_tx.handle.Instance = DMA1_Channel7; + uart_obj[UART2_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART2_INDEX].dma_tx.handle.dma_irq = DMA1_Channel7_IRQn; #endif #endif #ifdef BSP_USING_UART3 - uart_obj[UART3_INDEX].serial.config = config; + uart_obj[UART3_INDEX].serial.config = config; uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE; uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE; - uart_obj[UART3_INDEX].handle.Instance = USART3; - uart_obj[UART3_INDEX].uart_dma_flag = 0; + uart_obj[UART3_INDEX].handle.Instance = USART3; + uart_obj[UART3_INDEX].uart_dma_flag = 0; #ifdef BSP_UART3_RX_USING_DMA - uart_obj[UART3_INDEX].handle.HDMA_Rx = &uart_obj[UART3_INDEX].dma_rx.handle; + uart_obj[UART3_INDEX].handle.HDMA_Rx = &uart_obj[UART3_INDEX].dma_rx.handle; uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE; - uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART3_INDEX].dma_rx.handle.Parent = &uart_obj[UART3_INDEX].handle; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART3_INDEX].dma_rx.handle.Parent = &uart_obj[UART3_INDEX].handle; uart_obj[UART3_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART3_INDEX].dma_rx.handle.Instance = DMA1_Channel3; - uart_obj[UART3_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn; + uart_obj[UART3_INDEX].dma_rx.handle.Instance = DMA1_Channel3; + uart_obj[UART3_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn; #endif #ifdef BSP_UART3_TX_USING_DMA - uart_obj[UART3_INDEX].handle.HDMA_Tx = &uart_obj[UART3_INDEX].dma_tx.handle; - uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART3_INDEX].dma_tx.handle.Parent = &uart_obj[UART3_INDEX].handle; - uart_obj[UART3_INDEX].dma_tx.handle.Instance = DMA1_Channel2; + uart_obj[UART3_INDEX].handle.HDMA_Tx = &uart_obj[UART3_INDEX].dma_tx.handle; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART3_INDEX].dma_tx.handle.Parent = &uart_obj[UART3_INDEX].handle; + uart_obj[UART3_INDEX].dma_tx.handle.Instance = DMA1_Channel2; uart_obj[UART3_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART3_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; - uart_obj[UART3_INDEX].dma_tx.handle.dma_irq = DMA1_Channel2_IRQn; + uart_obj[UART3_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1; + uart_obj[UART3_INDEX].dma_tx.handle.dma_irq = DMA1_Channel2_IRQn; #endif #endif #ifdef BSP_USING_UART4 - uart_obj[UART4_INDEX].serial.config = config; + uart_obj[UART4_INDEX].serial.config = config; uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE; uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE; - uart_obj[UART4_INDEX].handle.Instance = UART4; - uart_obj[UART4_INDEX].uart_dma_flag = 0; + uart_obj[UART4_INDEX].handle.Instance = UART4; + uart_obj[UART4_INDEX].uart_dma_flag = 0; #ifdef BSP_UART4_RX_USING_DMA - uart_obj[UART4_INDEX].handle.HDMA_Rx = &uart_obj[UART4_INDEX].dma_rx.handle; + uart_obj[UART4_INDEX].handle.HDMA_Rx = &uart_obj[UART4_INDEX].dma_rx.handle; uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE; - uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART4_INDEX].dma_rx.handle.Parent = &uart_obj[UART4_INDEX].handle; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART4_INDEX].dma_rx.handle.Parent = &uart_obj[UART4_INDEX].handle; uart_obj[UART4_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART4_INDEX].dma_rx.handle.Instance = DMA2_Channel3; - uart_obj[UART4_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART4_INDEX].dma_rx.handle.dma_irq = DMA2_Channel3_IRQn; + uart_obj[UART4_INDEX].dma_rx.handle.Instance = DMA2_Channel3; + uart_obj[UART4_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART4_INDEX].dma_rx.handle.dma_irq = DMA2_Channel3_IRQn; #endif #ifdef BSP_UART4_TX_USING_DMA - uart_obj[UART4_INDEX].handle.HDMA_Tx = &uart_obj[UART4_INDEX].dma_tx.handle; - uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART4_INDEX].dma_tx.handle.Parent = &uart_obj[UART4_INDEX].handle; + uart_obj[UART4_INDEX].handle.HDMA_Tx = &uart_obj[UART4_INDEX].dma_tx.handle; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART4_INDEX].dma_tx.handle.Parent = &uart_obj[UART4_INDEX].handle; uart_obj[UART4_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART4_INDEX].dma_tx.handle.Instance = DMA2_Channel5; - uart_obj[UART4_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART4_INDEX].dma_tx.handle.dma_irq = DMA2_Channel5_IRQn; + uart_obj[UART4_INDEX].dma_tx.handle.Instance = DMA2_Channel5; + uart_obj[UART4_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART4_INDEX].dma_tx.handle.dma_irq = DMA2_Channel5_IRQn; #endif #endif #ifdef BSP_USING_UART5 - uart_obj[UART5_INDEX].serial.config = config; + uart_obj[UART5_INDEX].serial.config = config; uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE; uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE; - uart_obj[UART5_INDEX].handle.Instance = UART5; - uart_obj[UART5_INDEX].uart_dma_flag = 0; + uart_obj[UART5_INDEX].handle.Instance = UART5; + uart_obj[UART5_INDEX].uart_dma_flag = 0; #ifdef BSP_UART5_RX_USING_DMA - uart_obj[UART5_INDEX].handle.HDMA_Rx = &uart_obj[UART5_INDEX].dma_rx.handle; + uart_obj[UART5_INDEX].handle.HDMA_Rx = &uart_obj[UART5_INDEX].dma_rx.handle; uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE; - uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART5_INDEX].dma_rx.handle.Parent = &uart_obj[UART5_INDEX].handle; + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART5_INDEX].dma_rx.handle.Parent = &uart_obj[UART5_INDEX].handle; uart_obj[UART5_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART5_INDEX].dma_rx.handle.Instance = DMA2_Channel2; - uart_obj[UART5_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART5_INDEX].dma_rx.handle.dma_irq = DMA2_Channel2_IRQn; + uart_obj[UART5_INDEX].dma_rx.handle.Instance = DMA2_Channel2; + uart_obj[UART5_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART5_INDEX].dma_rx.handle.dma_irq = DMA2_Channel2_IRQn; #endif #ifdef BSP_UART5_TX_USING_DMA - uart_obj[UART5_INDEX].handle.HDMA_Tx = &uart_obj[UART5_INDEX].dma_tx.handle; - uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART5_INDEX].dma_tx.handle.Parent = &uart_obj[UART5_INDEX].handle; + uart_obj[UART5_INDEX].handle.HDMA_Tx = &uart_obj[UART5_INDEX].dma_tx.handle; + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART5_INDEX].dma_tx.handle.Parent = &uart_obj[UART5_INDEX].handle; uart_obj[UART5_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART5_INDEX].dma_tx.handle.Instance = DMA2_Channel4; - uart_obj[UART5_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART5_INDEX].dma_tx.handle.dma_irq = DMA2_Channel4_IRQn; + uart_obj[UART5_INDEX].dma_tx.handle.Instance = DMA2_Channel4; + uart_obj[UART5_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART5_INDEX].dma_tx.handle.dma_irq = DMA2_Channel4_IRQn; #endif #endif #ifdef BSP_USING_UART6 - uart_obj[UART6_INDEX].serial.config = config; + uart_obj[UART6_INDEX].serial.config = config; uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE; uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE; - uart_obj[UART6_INDEX].handle.Instance = UART6; - uart_obj[UART6_INDEX].uart_dma_flag = 0; + uart_obj[UART6_INDEX].handle.Instance = UART6; + uart_obj[UART6_INDEX].uart_dma_flag = 0; #ifdef BSP_UART6_RX_USING_DMA - uart_obj[UART6_INDEX].handle.HDMA_Rx = &uart_obj[UART6_INDEX].dma_rx.handle; + uart_obj[UART6_INDEX].handle.HDMA_Rx = &uart_obj[UART6_INDEX].dma_rx.handle; uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE; - uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART6_INDEX].dma_rx.handle.Parent = &uart_obj[UART6_INDEX].handle; + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART6_INDEX].dma_rx.handle.Parent = &uart_obj[UART6_INDEX].handle; uart_obj[UART6_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART6_INDEX].dma_rx.handle.Instance = DMA2_Channel7; - uart_obj[UART6_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART6_INDEX].dma_rx.handle.dma_irq = DMA2_Channel7_IRQn; + uart_obj[UART6_INDEX].dma_rx.handle.Instance = DMA2_Channel7; + uart_obj[UART6_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART6_INDEX].dma_rx.handle.dma_irq = DMA2_Channel7_IRQn; #endif #ifdef BSP_UART6_TX_USING_DMA - uart_obj[UART6_INDEX].handle.HDMA_Tx = &uart_obj[UART6_INDEX].dma_tx.handle; - uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART6_INDEX].dma_tx.handle.Parent = &uart_obj[UART6_INDEX].handle; + uart_obj[UART6_INDEX].handle.HDMA_Tx = &uart_obj[UART6_INDEX].dma_tx.handle; + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART6_INDEX].dma_tx.handle.Parent = &uart_obj[UART6_INDEX].handle; uart_obj[UART6_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART6_INDEX].dma_tx.handle.Instance = DMA2_Channel6; - uart_obj[UART6_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART6_INDEX].dma_tx.handle.dma_irq = DMA2_Channel6_IRQn; + uart_obj[UART6_INDEX].dma_tx.handle.Instance = DMA2_Channel6; + uart_obj[UART6_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART6_INDEX].dma_tx.handle.dma_irq = DMA2_Channel6_IRQn; #endif #endif #ifdef BSP_USING_UART7 - uart_obj[UART7_INDEX].serial.config = config; + uart_obj[UART7_INDEX].serial.config = config; uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE; uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE; - uart_obj[UART7_INDEX].handle.Instance = UART7; - uart_obj[UART7_INDEX].uart_dma_flag = 0; + uart_obj[UART7_INDEX].handle.Instance = UART7; + uart_obj[UART7_INDEX].uart_dma_flag = 0; #ifdef BSP_UART7_RX_USING_DMA - uart_obj[UART7_INDEX].handle.HDMA_Rx = &uart_obj[UART7_INDEX].dma_rx.handle; + uart_obj[UART7_INDEX].handle.HDMA_Rx = &uart_obj[UART7_INDEX].dma_rx.handle; uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE; - uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART7_INDEX].dma_rx.handle.Parent = &uart_obj[UART7_INDEX].handle; + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART7_INDEX].dma_rx.handle.Parent = &uart_obj[UART7_INDEX].handle; uart_obj[UART7_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART7_INDEX].dma_rx.handle.Instance = DMA2_Channel9; - uart_obj[UART7_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART7_INDEX].dma_rx.handle.dma_irq = DMA2_Channel9_IRQn; + uart_obj[UART7_INDEX].dma_rx.handle.Instance = DMA2_Channel9; + uart_obj[UART7_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART7_INDEX].dma_rx.handle.dma_irq = DMA2_Channel9_IRQn; #endif #ifdef BSP_UART7_TX_USING_DMA - uart_obj[UART7_INDEX].handle.HDMA_Tx = &uart_obj[UART7_INDEX].dma_tx.handle; - uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART7_INDEX].dma_tx.handle.Parent = &uart_obj[UART7_INDEX].handle; + uart_obj[UART7_INDEX].handle.HDMA_Tx = &uart_obj[UART7_INDEX].dma_tx.handle; + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART7_INDEX].dma_tx.handle.Parent = &uart_obj[UART7_INDEX].handle; uart_obj[UART7_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART7_INDEX].dma_tx.handle.Instance = DMA2_Channel8; - uart_obj[UART7_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART7_INDEX].dma_tx.handle.dma_irq = DMA2_Channel8_IRQn; + uart_obj[UART7_INDEX].dma_tx.handle.Instance = DMA2_Channel8; + uart_obj[UART7_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART7_INDEX].dma_tx.handle.dma_irq = DMA2_Channel8_IRQn; #endif #endif #ifdef BSP_USING_UART8 - uart_obj[UART8_INDEX].serial.config = config; - uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE; - uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE; - uart_obj[UART8_INDEX].handle.Instance = UART8; - uart_obj[UART8_INDEX].uart_dma_flag = 0; + uart_obj[UART8_INDEX].serial.config = config; + uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE; + uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE; + uart_obj[UART8_INDEX].handle.Instance = UART8; + uart_obj[UART8_INDEX].uart_dma_flag = 0; #ifdef BSP_UART8_RX_USING_DMA - uart_obj[UART8_INDEX].handle.HDMA_Rx = &uart_obj[UART8_INDEX].dma_rx.handle; + uart_obj[UART8_INDEX].handle.HDMA_Rx = &uart_obj[UART8_INDEX].dma_rx.handle; uart_obj[UART8_INDEX].serial.config.dma_ping_bufsz = BSP_UART8_DMA_PING_BUFSIZE; - uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - uart_obj[UART8_INDEX].dma_rx.handle.Parent = &uart_obj[UART8_INDEX].handle; + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART8_INDEX].dma_rx.handle.Parent = &uart_obj[UART8_INDEX].handle; uart_obj[UART8_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback; - uart_obj[UART8_INDEX].dma_rx.handle.Instance = DMA2_Channel10; - uart_obj[UART8_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART8_INDEX].dma_rx.handle.dma_irq = DMA2_Channel10_IRQn; + uart_obj[UART8_INDEX].dma_rx.handle.Instance = DMA2_Channel10; + uart_obj[UART8_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART8_INDEX].dma_rx.handle.dma_irq = DMA2_Channel10_IRQn; #endif #ifdef BSP_UART8_TX_USING_DMA - uart_obj[UART8_INDEX].handle.HDMA_Tx = &uart_obj[UART8_INDEX].dma_tx.handle; - uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - uart_obj[UART8_INDEX].dma_tx.handle.Parent = &uart_obj[UART8_INDEX].handle; + uart_obj[UART8_INDEX].handle.HDMA_Tx = &uart_obj[UART8_INDEX].dma_tx.handle; + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART8_INDEX].dma_tx.handle.Parent = &uart_obj[UART8_INDEX].handle; uart_obj[UART8_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback; - uart_obj[UART8_INDEX].dma_tx.handle.Instance = DMA2_Channel11; - uart_obj[UART8_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; - uart_obj[UART8_INDEX].dma_tx.handle.dma_irq = DMA2_Channel11_IRQn; + uart_obj[UART8_INDEX].dma_tx.handle.Instance = DMA2_Channel11; + uart_obj[UART8_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2; + uart_obj[UART8_INDEX].dma_tx.handle.dma_irq = DMA2_Channel11_IRQn; #endif #endif } @@ -1252,7 +1155,7 @@ static void ch32_uart_get_config(void) static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) { struct DMA_HandleTypeDef *DMA_Handle; - struct ch32_uart *uart; + struct ch32_uart *uart; RT_ASSERT(serial != RT_NULL); RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); @@ -1268,29 +1171,29 @@ static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t fla RCC_AHBPeriphClockCmd(DMA_Handle->dma_rcc, ENABLE); DMA_DeInit(DMA_Handle->Instance); - DMA_Handle->Init.DMA_PeripheralBaseAddr = (unsigned int)uart->config->Instance + 0x4; - DMA_Handle->Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_Handle->Init.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_Handle->Init.DMA_PeripheralBaseAddr = (unsigned int)uart->config->Instance + 0x4; + DMA_Handle->Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_Handle->Init.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_Handle->Init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_Handle->Init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_Handle->Init.DMA_M2M = DMA_M2M_Disable; + DMA_Handle->Init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_Handle->Init.DMA_M2M = DMA_M2M_Disable; if (RT_DEVICE_FLAG_DMA_RX == flag) { rt_uint8_t *ptr = NULL; rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr); - DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)ptr; - DMA_Handle->Init.DMA_BufferSize = serial->config.dma_ping_bufsz; + DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)ptr; + DMA_Handle->Init.DMA_BufferSize = serial->config.dma_ping_bufsz; DMA_Handle->Init.DMA_Mode = DMA_Mode_Circular; - DMA_Handle->Init.DMA_Priority = DMA_Priority_VeryHigh; + DMA_Handle->Init.DMA_Priority = DMA_Priority_VeryHigh; } else if (RT_DEVICE_FLAG_DMA_TX == flag) { - DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralDST; - DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)1; - DMA_Handle->Init.DMA_BufferSize = 1; + DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)1; + DMA_Handle->Init.DMA_BufferSize = 1; DMA_Handle->Init.DMA_Mode = DMA_Mode_Normal; - DMA_Handle->Init.DMA_Priority = DMA_Priority_High; + DMA_Handle->Init.DMA_Priority = DMA_Priority_High; } DMA_Init(DMA_Handle->Instance, &DMA_Handle->Init); NVIC_Set(DMA_Handle->dma_irq, ENABLE); @@ -1329,7 +1232,7 @@ static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma) { dmax = DMA2; } - unsigned int flag_it = dmax->INTFR; + unsigned int flag_it = dmax->INTFR; unsigned int channel_offset = ((unsigned int)hdma->Instance - (unsigned int)dmax - 8) / 20; /* Transfer Complete Interrupt management ***********************************/ if ((flag_it & 2u << (4 * channel_offset))) @@ -1342,27 +1245,23 @@ static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma) { hdma->DMA_ITC_Callback(&uart->handle); } - } - if(flag_it & (8u << (4 * channel_offset))) + if (flag_it & (8u << (4 * channel_offset))) { rt_kprintf("DMA error: %d\n", flag_it & (8u << (4 * channel_offset))); dmax->INTFCR |= 8u << (4 * channel_offset); } - - - } static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) { struct ch32_uart *uart; - rt_base_t level; - rt_size_t recv_len, counter; + rt_base_t level; + rt_size_t recv_len, counter; RT_ASSERT(serial != RT_NULL); - uart = rt_container_of(serial, struct ch32_uart, serial); + uart = rt_container_of(serial, struct ch32_uart, serial); recv_len = 0; counter = uart->dma_rx.handle.Instance->CNTR; @@ -1370,16 +1269,24 @@ static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) { case UART_RX_DMA_IT_IDLE_FLAG: if (counter <= uart->dma_rx.remaining_cnt) + { recv_len = uart->dma_rx.remaining_cnt - counter; + } else + { recv_len = serial->config.dma_ping_bufsz + uart->dma_rx.remaining_cnt - counter; + } break; case UART_RX_DMA_IT_HT_FLAG: if (counter < uart->dma_rx.remaining_cnt) + { recv_len = uart->dma_rx.remaining_cnt - counter; + } else + { recv_len = 0; + } break; case UART_RX_DMA_IT_TC_FLAG: recv_len = uart->dma_rx.remaining_cnt; @@ -1396,8 +1303,6 @@ static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } - - } void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart) @@ -1417,18 +1322,17 @@ void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart) } #endif /* RT_SERIAL_USING_DMA */ -static const struct rt_uart_ops ch32_uart_ops = -{ +static const struct rt_uart_ops ch32_uart_ops = { .configure = ch32_configure, - .control = ch32_control, - .putc = ch32_putc, - .getc = ch32_getc, - .transmit = ch32_transmit + .control = ch32_control, + .putc = ch32_putc, + .getc = ch32_getc, + .transmit = ch32_transmit }; int rt_hw_usart_init(void) { - rt_err_t result = 0; + rt_err_t result = 0; rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ch32_uart); ch32_uart_get_config(); diff --git a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usbh.c b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usbh.c index 15005305c7..c380799dd1 100644 --- a/bsp/wch/risc-v/libraries/ch32_drivers/drv_usbh.c +++ b/bsp/wch/risc-v/libraries/ch32_drivers/drv_usbh.c @@ -9,6 +9,7 @@ */ #include "board.h" +#include "drv_common.h" #include "drv_usbh.h" #ifdef BSP_USING_USBH @@ -20,8 +21,8 @@ static struct uhcd uhcd; static struct rt_completion urb_completion; -__attribute__((aligned(4))) int8_t usb_rx_buf[ MAX_PACKET_SIZE ]; -__attribute__((aligned(4))) int8_t usb_tx_buf[ MAX_PACKET_SIZE ]; +__attribute__((aligned(4))) int8_t usb_rx_buf[MAX_PACKET_SIZE]; +__attribute__((aligned(4))) int8_t usb_tx_buf[MAX_PACKET_SIZE]; USBOTGH_FS_TypeDef *USBFSH = USBOTG_H_FS; @@ -44,15 +45,16 @@ rt_err_t usbh_reset_port(rt_uint8_t port) rt_thread_mdelay(20); //Set speed - if ((USBFSH->HOST_CTRL & USBFS_UH_PORT_EN) == 0) { //Set speed only when port is closed - if(USBFSH->MIS_ST & USBFS_UMS_DM_LEVEL) //RB_UMS_DM_LEVEL: 1/Low 0/Full - { //Low speed + if ((USBFSH->HOST_CTRL & USBFS_UH_PORT_EN) == 0) + { //Set speed only when port is closed + if (USBFSH->MIS_ST & USBFS_UMS_DM_LEVEL) //RB_UMS_DM_LEVEL: 1/Low 0/Full + { //Low speed USBFSH->BASE_CTRL |= USBFS_UC_LOW_SPEED; USBFSH->HOST_CTRL |= USBFS_UH_LOW_SPEED; USBFSH->HOST_SETUP |= USBFS_UH_PRE_PID_EN; } else - { //Full speed + { //Full speed USBFSH->BASE_CTRL &= ~USBFS_UC_LOW_SPEED; USBFSH->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; USBFSH->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN; @@ -66,9 +68,13 @@ rt_err_t usbh_reset_port(rt_uint8_t port) //Enable interrupt USBFSH->INT_EN |= USBFS_UIE_DETECT; - if(USBFSH->INT_FG & USBFS_UIF_DETECT) - if(USBFSH->MIS_ST & USBFS_UMS_DEV_ATTACH) + if (USBFSH->INT_FG & USBFS_UIF_DETECT) + { + if (USBFSH->MIS_ST & USBFS_UMS_DEV_ATTACH) + { USBFSH->INT_FG = USBFS_UIF_DETECT; + } + } return RT_EOK; } @@ -80,7 +86,7 @@ int usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int USBFSH->DEV_ADDR = (USBFS_UDA_GP_BIT & USBFSH->DEV_ADDR) | (pipe->pipe_index & USBFS_USB_ADDR_MASK); - if(pipe->ep.bEndpointAddress & USB_DIR_IN) + if (pipe->ep.bEndpointAddress & USB_DIR_IN) { usb_pid = USB_PID_IN; USBFSH->HOST_TX_LEN = 0x00; @@ -92,14 +98,20 @@ int usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int USBFSH->HOST_TX_LEN = nbytes; } - switch(usb_pid) + switch (usb_pid) { case USB_PID_IN: - if (nbytes == 0) *tog = USB_PID_DATA1; + if (nbytes == 0) + { + *tog = USB_PID_DATA1; + } USBFSH->HOST_RX_CTRL = (*tog == USB_PID_DATA1) ? USBFS_UH_R_TOG : 0x00; break; case USB_PID_OUT: - if (nbytes == 0) *tog = USB_PID_DATA1; + if (nbytes == 0) + { + *tog = USB_PID_DATA1; + } USBFSH->HOST_TX_CTRL = (*tog == USB_PID_DATA1) ? USBFS_UH_T_TOG : 0x00; break; case USB_PID_SETUP: @@ -111,24 +123,32 @@ int usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int rt_uint16_t try = 3; if ((pipe->ep.bmAttributes & USB_EP_ATTR_TYPE_MASK) == USB_EP_ATTR_CONTROL) + { try = 1000; + } - while(try--) + while (try--) { USBFSH->HOST_EP_PID = (usb_pid << 4) | (pipe->ep.bEndpointAddress & 0x0F); if (rt_completion_wait(&urb_completion, timeouts) != RT_EOK) + { continue; + } if (USBFSH->INT_ST & USBHS_UIS_TOG_OK) + { *tog = (*tog == USB_PID_DATA0) ? USB_PID_DATA1 : USB_PID_DATA0; + } - switch(USBFSH->INT_ST & USBHS_UIS_H_RES_MASK) + switch (USBFSH->INT_ST & USBHS_UIS_H_RES_MASK) { case USB_PID_DATA0: case USB_PID_DATA1: pipe->status = UPIPE_STATUS_OK; if (pipe->callback != RT_NULL) + { pipe->callback(pipe); + } if (usb_pid == USB_PID_IN) { rt_memcpy(buffer, usb_rx_buf, USBFSH->RX_LEN); @@ -139,18 +159,24 @@ int usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int case USB_PID_ACK: pipe->status = UPIPE_STATUS_OK; if (pipe->callback != RT_NULL) + { pipe->callback(pipe); + } return nbytes; case USB_PID_NAK: if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) + { rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); + } rt_thread_mdelay(1); continue; case USB_PID_STALL: pipe->status = UPIPE_STATUS_STALL; if (pipe->callback != RT_NULL) + { pipe->callback(pipe); + } return 0; default: @@ -160,7 +186,9 @@ int usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int pipe->status = UPIPE_STATUS_ERROR; if (pipe->callback != RT_NULL) + { pipe->callback(pipe); + } return -RT_ERROR; } @@ -184,7 +212,7 @@ rt_err_t hcd_init(rt_device_t dev) //Force reset handler clear FIFO & interrupt flags USBFSH->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; rt_thread_mdelay(20); - USBFSH->BASE_CTRL = 0; //Set SIE to 0 manually + USBFSH->BASE_CTRL = 0; //Set SIE to 0 manually USBFSH->BASE_CTRL = USBFS_UC_HOST_MODE; USBFSH->HOST_CTRL = 0; @@ -201,13 +229,19 @@ rt_err_t hcd_init(rt_device_t dev) USBFSH->INT_FG = 0xFF; USBFSH->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; - if( SystemCoreClock == 144000000 ) - RCC_OTGFSCLKConfig( RCC_OTGFSCLKSource_PLLCLK_Div3 ); - else if( SystemCoreClock == 96000000 ) - RCC_OTGFSCLKConfig( RCC_OTGFSCLKSource_PLLCLK_Div2 ); - else if( SystemCoreClock == 48000000 ) - RCC_OTGFSCLKConfig( RCC_OTGFSCLKSource_PLLCLK_Div1 ); - RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE ); + if (SystemCoreClock == 144000000) + { + RCC_OTGFSCLKConfig(RCC_OTGFSCLKSource_PLLCLK_Div3); + } + else if (SystemCoreClock == 96000000) + { + RCC_OTGFSCLKConfig(RCC_OTGFSCLKSource_PLLCLK_Div2); + } + else if (SystemCoreClock == 48000000) + { + RCC_OTGFSCLKConfig(RCC_OTGFSCLKSource_PLLCLK_Div1); + } + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); NVIC_EnableIRQ(OTG_FS_IRQn); @@ -216,16 +250,15 @@ rt_err_t hcd_init(rt_device_t dev) return RT_EOK; } -static struct uhcd_ops uhcd_ops = -{ +static struct uhcd_ops uhcd_ops = { .reset_port = usbh_reset_port, .pipe_xfer = usbh_pipe_xfer, .open_pipe = usbh_open_pipe, .close_pipe = usbh_close_pipe, }; -void OTG_HS_IRQHandler() __attribute__((interrupt("WCH-Interrupt-fast"))); -void OTG_HS_IRQHandler() +void OTG_HS_IRQHandler(void) WCH_IRQ_ATTR; +void OTG_HS_IRQHandler(void) { rt_interrupt_enter(); @@ -233,7 +266,7 @@ void OTG_HS_IRQHandler() { USBFSH->HOST_EP_PID = 0x00; USBFSH->INT_FG = USBFS_UIF_TRANSFER; - rt_completion_done(&urb_completion); //本应在此处理的中断在传输函数里进行枚举 + rt_completion_done(&urb_completion); //本应在此处理的中断在传输函数里进行枚举 rt_kprintf("USB: Transfer finished\n"); } else if (USBFSH->INT_FG & USBFS_UIF_DETECT) @@ -283,4 +316,4 @@ int rt_hw_usbh_init() return RT_EOK; } -#endif //BSP_USING_USBH
\ No newline at end of file +#endif //BSP_USING_USBH diff --git a/bsp/wch/risc-v/yd-ch32v307vct6/.config b/bsp/wch/risc-v/yd-ch32v307vct6/.config index 1687b84ce8..d7fa031ce7 100644 --- a/bsp/wch/risc-v/yd-ch32v307vct6/.config +++ b/bsp/wch/risc-v/yd-ch32v307vct6/.config @@ -823,9 +823,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CH32V20x_SDK is not set CONFIG_PKG_USING_CH32V307_SDK=y CONFIG_PKG_CH32V307_SDK_PATH="/packages/peripherals/hal-sdk/wch/ch32v307_sdk" -CONFIG_PKG_USING_CH32V307_SDK_V207=y +# CONFIG_PKG_USING_CH32V307_SDK_V207 is not set +CONFIG_PKG_USING_CH32V307_SDK_V302=y # CONFIG_PKG_USING_CH32V307_SDK_LATEST_VERSION is not set -CONFIG_PKG_CH32V307_SDK_VER="v2.7" +CONFIG_PKG_CH32V307_SDK_VER="v3.2" # end of WCH HAL & SDK Drivers # @@ -1430,6 +1431,9 @@ CONFIG_PKG_CH32V307_SDK_VER="v2.7" CONFIG_SOC_RISCV_FAMILY_CH32=y CONFIG_SOC_RISCV_SERIES_CH32V3=y +CONFIG_WCH_QINGKE_V4F=y +CONFIG_WCH_HAS_FAST_IRQ=y +CONFIG_WCH_USING_FAST_IRQ=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/yd-ch32v307vct6/board/board.c b/bsp/wch/risc-v/yd-ch32v307vct6/board/board.c index 5753d3b24f..333e72c561 100644 --- a/bsp/wch/risc-v/yd-ch32v307vct6/board/board.c +++ b/bsp/wch/risc-v/yd-ch32v307vct6/board/board.c @@ -9,6 +9,7 @@ */ #include "board.h" +#include <drv_common.h> #include <stdint.h> #include "drv_usart.h" #include <rthw.h> @@ -39,7 +40,7 @@ void rt_hw_board_init() _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); #if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) - rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif /* USART driver initialization is open by default */ @@ -59,7 +60,7 @@ void rt_hw_board_init() #endif } -void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void SysTick_Handler(void) WCH_IRQ_ATTR; void SysTick_Handler(void) { GET_INT_SP(); @@ -70,5 +71,4 @@ void SysTick_Handler(void) /* leave interrupt */ rt_interrupt_leave(); FREE_INT_SP(); - } diff --git a/bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.h b/bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.h index a567f70101..54c1b8678f 100644 --- a/bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.h +++ b/bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.h @@ -61,12 +61,12 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR @@ -74,7 +74,7 @@ #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -102,10 +102,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -116,12 +116,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 1024 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -154,17 +154,15 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ - /* Interprocess Communication (IPC) */ - /* Socket is in the 'Network' category */ /* end of Interprocess Communication (IPC) */ @@ -196,7 +194,6 @@ /* IoT - internet of things */ - /* Wi-Fi */ /* Marvell WiFi */ @@ -293,7 +290,7 @@ /* WCH HAL & SDK Drivers */ #define PKG_USING_CH32V307_SDK -#define PKG_USING_CH32V307_SDK_V207 +#define PKG_USING_CH32V307_SDK_V302 /* end of WCH HAL & SDK Drivers */ /* AT32 HAL & SDK Drivers */ @@ -359,7 +356,6 @@ /* Arduino libraries */ - /* Projects and Demos */ /* end of Projects and Demos */ @@ -404,6 +400,9 @@ /* end of RT-Thread online packages */ #define SOC_RISCV_FAMILY_CH32 #define SOC_RISCV_SERIES_CH32V3 +#define WCH_QINGKE_V4F +#define WCH_HAS_FAST_IRQ +#define WCH_USING_FAST_IRQ /* Hardware Drivers Config */ |