diff options
| author | seteiro <[email protected]> | 2026-11-10 02:36:22 +0900 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2026-11-13 16:42:26 +0800 |
| commit | 9d36c767f5ea74eb4be61370399703fe8ac6a6f4 (patch) | |
| tree | 185e4a46d63f80e873d1e4855153d7f28c019b00 | |
| parent | 6c955645ec82372469f20746ead53e2ce3b5eda5 (diff) | |
[bsp][esp32-c3] fix chip revision fields for v1.x chips
ESP32-C3 revision 1.x chips (such as v1.1) fail to flash and boot because
the old header fields set min_rev=3 and full revision fields were invalid/0,
causing esptool and the 2nd-stage bootloader to reject the chip.
- In SConstruct elf2image(): set min_rev=0, min_rev_full=3, max_rev_full=199
to match ESP-IDF revision range specifications.
- In builtin_imgs/bootloader.bin: update header chip revision fields to
min_rev=0, min_rev_full=3, max_rev_full=199 and recalculate trailing SHA-256
digest (header workaround, host environment lacks CMake for IDF rebuild).
| -rw-r--r-- | bsp/ESP/ESP32_C3/SConstruct | 4 | ||||
| -rw-r--r-- | bsp/ESP/ESP32_C3/builtin_imgs/bootloader.bin | bin | 20064 -> 20064 bytes |
2 files changed, 3 insertions, 1 deletions
diff --git a/bsp/ESP/ESP32_C3/SConstruct b/bsp/ESP/ESP32_C3/SConstruct index 4b507b7b6a..b6dd1af4c9 100644 --- a/bsp/ESP/ESP32_C3/SConstruct +++ b/bsp/ESP/ESP32_C3/SConstruct @@ -9,7 +9,9 @@ def elf2image(target, source, env): print("Creating esp32c3 image...") image = CHIP_DEFS["esp32c3"].BOOTLOADER_IMAGE() - image.min_rev = 3 + image.min_rev = 0 + image.min_rev_full = 3 + image.max_rev_full = 199 image.entrypoint = e.entrypoint image.flash_mode = 2 # flash_mode: dio diff --git a/bsp/ESP/ESP32_C3/builtin_imgs/bootloader.bin b/bsp/ESP/ESP32_C3/builtin_imgs/bootloader.bin Binary files differindex cce9cb2086..c1259b0d40 100644 --- a/bsp/ESP/ESP32_C3/builtin_imgs/bootloader.bin +++ b/bsp/ESP/ESP32_C3/builtin_imgs/bootloader.bin |