diff options
| author | Onlyou_tzZ <[email protected]> | 2026-08-20 17:32:18 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-08-20 17:32:18 +0800 |
| commit | 9fce24b62b0b1dffc63e6f506d73e66a12944144 (patch) | |
| tree | 5deabcd567e59b6c645a63a808bb9613358624c1 | |
| parent | 8234a3614e289945cf425e3fcca3979f99a17422 (diff) | |
[bsp][n32] add H47X/H49X/H7XX driver support- #11711 #11711
60 files changed, 5643 insertions, 1999 deletions
diff --git a/bsp/README.md b/bsp/README.md index 7390ccb833..39703eddc3 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -332,8 +332,8 @@ This document is based on the RT-Thread mainline repository and categorizes the | [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | | [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | | [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | - | - | - | ✅ | - | - | - | +| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | - | - | - | ✅ | - | - | - | #### 🟡 NRF5x diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/can_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/can_config.h new file mode 100644 index 0000000000..8d5d61ef26 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/can_config.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include <rtthread.h> +#include "n32h47x_48x_fdcan.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct n32_fdcan_config +{ + const char *name; + FDCAN_Module *Instance; + uint32_t std_filter_size; + uint32_t ext_filter_size; + uint32_t rx_fifo0_size; + uint32_t rx_fifo0_data_bytes; + uint32_t rx_fifo1_size; + uint32_t rx_fifo1_data_bytes; + uint32_t rx_buffer_size; + uint32_t rx_buffer_data_bytes; + uint32_t tx_event_size; + uint32_t tx_buffer_size; + uint32_t tx_buffer_data_bytes; + uint32_t tx_fifo_queue_size; + uint32_t tx_fifo_queue_mode; + uint32_t tdc_offset; + uint32_t tdc_filter; + rt_bool_t tdc_enabled; +}; + +#define FDCAN_RESOURCE_CONFIG(number) \ + .std_filter_size = BSP_FDCAN##number##_STD_FILTER_SIZE, \ + .ext_filter_size = BSP_FDCAN##number##_EXT_FILTER_SIZE, \ + .rx_fifo0_size = BSP_FDCAN##number##_RX_FIFO0_SIZE, \ + .rx_fifo0_data_bytes = BSP_FDCAN##number##_RX_FIFO0_DATA_BYTES, \ + .rx_fifo1_size = BSP_FDCAN##number##_RX_FIFO1_SIZE, \ + .rx_fifo1_data_bytes = BSP_FDCAN##number##_RX_FIFO1_DATA_BYTES, \ + .rx_buffer_size = BSP_FDCAN##number##_RX_BUFFER_SIZE, \ + .rx_buffer_data_bytes = BSP_FDCAN##number##_RX_BUFFER_DATA_BYTES, \ + .tx_event_size = BSP_FDCAN##number##_TX_EVENT_FIFO_SIZE, \ + .tx_buffer_size = BSP_FDCAN##number##_TX_BUFFER_SIZE, \ + .tx_buffer_data_bytes = BSP_FDCAN##number##_TX_BUFFER_DATA_BYTES, \ + .tx_fifo_queue_size = BSP_FDCAN##number##_TX_FIFO_QUEUE_SIZE + +#define FDCAN_INSTANCE_CONFIG(number) \ + { \ + .name = "fdcan" #number, \ + .Instance = FDCAN##number, \ + FDCAN_RESOURCE_CONFIG(number), \ + FDCAN##number##_MODE_CONFIG, \ + FDCAN##number##_TDC_CONFIG, \ + } + +#define FDCAN_TX_FIFO_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_FIFO_MODE +#define FDCAN_TX_QUEUE_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_QUEUE_MODE +#define FDCAN_TDC_DISABLED_CONFIG(number) \ + .tdc_enabled = RT_FALSE, .tdc_offset = 0, .tdc_filter = 0 +#define FDCAN_TDC_ENABLED_CONFIG(number) \ + .tdc_enabled = RT_TRUE, \ + .tdc_offset = BSP_FDCAN##number##_TDC_OFFSET, \ + .tdc_filter = BSP_FDCAN##number##_TDC_FILTER + +#if defined(BSP_USING_FDCAN1) +#if defined(BSP_FDCAN1_TX_QUEUE_MODE) +#define FDCAN1_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(1) +#else +#define FDCAN1_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(1) +#endif +#if defined(BSP_FDCAN1_USING_TDC) +#define FDCAN1_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(1) +#else +#define FDCAN1_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(1) +#endif +#define FDCAN1_CONFIG FDCAN_INSTANCE_CONFIG(1) +#endif + +#if defined(BSP_USING_FDCAN2) +#if defined(BSP_FDCAN2_TX_QUEUE_MODE) +#define FDCAN2_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(2) +#else +#define FDCAN2_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(2) +#endif +#if defined(BSP_FDCAN2_USING_TDC) +#define FDCAN2_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(2) +#else +#define FDCAN2_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(2) +#endif +#define FDCAN2_CONFIG FDCAN_INSTANCE_CONFIG(2) +#endif + +#if defined(BSP_USING_FDCAN3) +#if defined(BSP_FDCAN3_TX_QUEUE_MODE) +#define FDCAN3_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(3) +#else +#define FDCAN3_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(3) +#endif +#if defined(BSP_FDCAN3_USING_TDC) +#define FDCAN3_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(3) +#else +#define FDCAN3_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(3) +#endif +#define FDCAN3_CONFIG FDCAN_INSTANCE_CONFIG(3) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/uart_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/uart_config.h index fb9a2b3115..6f7f1454a8 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/uart_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/uart_config.h @@ -21,10 +21,10 @@ extern "C" { #ifndef UART1_CONFIG #define UART1_CONFIG \ { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .periph = RCC_APB2_PERIPH_USART1, \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + .periph = RCC_APB2_PERIPH_USART1, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART1_CONFIG */ @@ -34,8 +34,8 @@ extern "C" { #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ { \ - .DMAy = UART1_RX_DMA, \ - .DMAChx = UART1_RX_DMA_CHType, \ + .DMAy = UART1_RX_DMA, \ + .DMAChx = UART1_RX_DMA_CHType, \ .dma_irq = UART1_RX_DMA_IRQ, \ .dma_rcc = UART1_RX_DMA_RCC, \ .request = UART1_RX_DMA_REQUEST, \ @@ -51,8 +51,8 @@ extern "C" { #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ { \ - .DMAy = UART1_TX_DMA, \ - .DMAChx = UART1_TX_DMA_CHType, \ + .DMAy = UART1_TX_DMA, \ + .DMAChx = UART1_TX_DMA_CHType, \ .dma_irq = UART1_TX_DMA_IRQ, \ .dma_rcc = UART1_TX_DMA_RCC, \ .request = UART1_TX_DMA_REQUEST, \ @@ -68,10 +68,10 @@ extern "C" { #ifndef UART2_CONFIG #define UART2_CONFIG \ { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .periph = RCC_APB1_PERIPH_USART2, \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + .periph = RCC_APB1_PERIPH_USART2, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART2_CONFIG */ @@ -81,8 +81,8 @@ extern "C" { #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ { \ - .DMAy = UART2_RX_DMA, \ - .DMAChx = UART2_RX_DMA_CHType, \ + .DMAy = UART2_RX_DMA, \ + .DMAChx = UART2_RX_DMA_CHType, \ .dma_irq = UART2_RX_DMA_IRQ, \ .dma_rcc = UART2_RX_DMA_RCC, \ .request = UART2_RX_DMA_REQUEST, \ @@ -98,8 +98,8 @@ extern "C" { #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ { \ - .DMAy = UART2_TX_DMA, \ - .DMAChx = UART2_TX_DMA_CHType, \ + .DMAy = UART2_TX_DMA, \ + .DMAChx = UART2_TX_DMA_CHType, \ .dma_irq = UART2_TX_DMA_IRQ, \ .dma_rcc = UART2_TX_DMA_RCC, \ .request = UART2_TX_DMA_REQUEST, \ @@ -115,10 +115,10 @@ extern "C" { #ifndef UART3_CONFIG #define UART3_CONFIG \ { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .periph = RCC_APB1_PERIPH_USART3, \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .periph = RCC_APB1_PERIPH_USART3, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART3_CONFIG */ @@ -128,8 +128,8 @@ extern "C" { #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ { \ - .DMAy = UART3_RX_DMA, \ - .DMAChx = UART3_RX_DMA_CHType, \ + .DMAy = UART3_RX_DMA, \ + .DMAChx = UART3_RX_DMA_CHType, \ .dma_irq = UART3_RX_DMA_IRQ, \ .dma_rcc = UART3_RX_DMA_RCC, \ .request = UART3_RX_DMA_REQUEST, \ @@ -145,8 +145,8 @@ extern "C" { #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ { \ - .DMAy = UART3_TX_DMA, \ - .DMAChx = UART3_TX_DMA_CHType, \ + .DMAy = UART3_TX_DMA, \ + .DMAChx = UART3_TX_DMA_CHType, \ .dma_irq = UART3_TX_DMA_IRQ, \ .dma_rcc = UART3_TX_DMA_RCC, \ .request = UART3_TX_DMA_REQUEST, \ @@ -162,10 +162,10 @@ extern "C" { #ifndef UART4_CONFIG #define UART4_CONFIG \ { \ - .name = "uart4", \ - .Instance = USART4, \ - .irq_type = USART4_IRQn, \ - .periph = RCC_APB2_PERIPH_USART4, \ + .name = "uart4", \ + .Instance = USART4, \ + .irq_type = USART4_IRQn, \ + .periph = RCC_APB2_PERIPH_USART4, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART4_CONFIG */ @@ -175,8 +175,8 @@ extern "C" { #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ { \ - .DMAy = UART4_RX_DMA, \ - .DMAChx = UART4_RX_DMA_CHType, \ + .DMAy = UART4_RX_DMA, \ + .DMAChx = UART4_RX_DMA_CHType, \ .dma_irq = UART4_RX_DMA_IRQ, \ .dma_rcc = UART4_RX_DMA_RCC, \ .request = UART4_RX_DMA_REQUEST, \ @@ -192,8 +192,8 @@ extern "C" { #ifndef UART4_DMA_TX_CONFIG #define UART4_DMA_TX_CONFIG \ { \ - .DMAy = UART4_TX_DMA, \ - .DMAChx = UART4_TX_DMA_CHType, \ + .DMAy = UART4_TX_DMA, \ + .DMAChx = UART4_TX_DMA_CHType, \ .dma_irq = UART4_TX_DMA_IRQ, \ .dma_rcc = UART4_TX_DMA_RCC, \ .request = UART4_TX_DMA_REQUEST, \ @@ -209,10 +209,10 @@ extern "C" { #ifndef UART5_CONFIG #define UART5_CONFIG \ { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .periph = RCC_APB1_PERIPH_UART5, \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + .periph = RCC_APB1_PERIPH_UART5, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART5_CONFIG */ @@ -222,8 +222,8 @@ extern "C" { #ifndef UART5_DMA_RX_CONFIG #define UART5_DMA_RX_CONFIG \ { \ - .DMAy = UART5_RX_DMA, \ - .DMAChx = UART5_RX_DMA_CHType, \ + .DMAy = UART5_RX_DMA, \ + .DMAChx = UART5_RX_DMA_CHType, \ .dma_irq = UART5_RX_DMA_IRQ, \ .dma_rcc = UART5_RX_DMA_RCC, \ .request = UART5_RX_DMA_REQUEST, \ @@ -239,8 +239,8 @@ extern "C" { #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ { \ - .DMAy = UART5_TX_DMA, \ - .DMAChx = UART5_TX_DMA_CHType, \ + .DMAy = UART5_TX_DMA, \ + .DMAChx = UART5_TX_DMA_CHType, \ .dma_irq = UART5_TX_DMA_IRQ, \ .dma_rcc = UART5_TX_DMA_RCC, \ .request = UART5_TX_DMA_REQUEST, \ @@ -256,10 +256,10 @@ extern "C" { #ifndef UART6_CONFIG #define UART6_CONFIG \ { \ - .name = "uart6", \ - .Instance = UART6, \ - .irq_type = UART6_IRQn, \ - .periph = RCC_APB2_PERIPH_UART6, \ + .name = "uart6", \ + .Instance = UART6, \ + .irq_type = UART6_IRQn, \ + .periph = RCC_APB2_PERIPH_UART6, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART6_CONFIG */ @@ -269,8 +269,8 @@ extern "C" { #ifndef UART6_DMA_RX_CONFIG #define UART6_DMA_RX_CONFIG \ { \ - .DMAy = UART6_RX_DMA, \ - .DMAChx = UART6_RX_DMA_CHType, \ + .DMAy = UART6_RX_DMA, \ + .DMAChx = UART6_RX_DMA_CHType, \ .dma_irq = UART6_RX_DMA_IRQ, \ .dma_rcc = UART6_RX_DMA_RCC, \ .request = UART6_RX_DMA_REQUEST, \ @@ -286,8 +286,8 @@ extern "C" { #ifndef UART6_DMA_TX_CONFIG #define UART6_DMA_TX_CONFIG \ { \ - .DMAy = UART6_TX_DMA, \ - .DMAChx = UART6_TX_DMA_CHType, \ + .DMAy = UART6_TX_DMA, \ + .DMAChx = UART6_TX_DMA_CHType, \ .dma_irq = UART6_TX_DMA_IRQ, \ .dma_rcc = UART6_TX_DMA_RCC, \ .request = UART6_TX_DMA_REQUEST, \ @@ -303,10 +303,10 @@ extern "C" { #ifndef UART7_CONFIG #define UART7_CONFIG \ { \ - .name = "uart7", \ - .Instance = UART7, \ - .irq_type = UART7_IRQn, \ - .periph = RCC_APB2_PERIPH_UART7, \ + .name = "uart7", \ + .Instance = UART7, \ + .irq_type = UART7_IRQn, \ + .periph = RCC_APB2_PERIPH_UART7, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART7_CONFIG */ @@ -316,8 +316,8 @@ extern "C" { #ifndef UART7_DMA_RX_CONFIG #define UART7_DMA_RX_CONFIG \ { \ - .DMAy = UART7_RX_DMA, \ - .DMAChx = UART7_RX_DMA_CHType, \ + .DMAy = UART7_RX_DMA, \ + .DMAChx = UART7_RX_DMA_CHType, \ .dma_irq = UART7_RX_DMA_IRQ, \ .dma_rcc = UART7_RX_DMA_RCC, \ .request = UART7_RX_DMA_REQUEST, \ @@ -333,8 +333,8 @@ extern "C" { #ifndef UART7_DMA_TX_CONFIG #define UART7_DMA_TX_CONFIG \ { \ - .DMAy = UART7_TX_DMA, \ - .DMAChx = UART7_TX_DMA_CHType, \ + .DMAy = UART7_TX_DMA, \ + .DMAChx = UART7_TX_DMA_CHType, \ .dma_irq = UART7_TX_DMA_IRQ, \ .dma_rcc = UART7_TX_DMA_RCC, \ .request = UART7_TX_DMA_REQUEST, \ @@ -350,10 +350,10 @@ extern "C" { #ifndef UART8_CONFIG #define UART8_CONFIG \ { \ - .name = "uart8", \ - .Instance = UART8, \ - .irq_type = UART8_IRQn, \ - .periph = RCC_APB1_PERIPH_UART8, \ + .name = "uart8", \ + .Instance = UART8, \ + .irq_type = UART8_IRQn, \ + .periph = RCC_APB1_PERIPH_UART8, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART8_CONFIG */ @@ -363,8 +363,8 @@ extern "C" { #ifndef UART8_DMA_RX_CONFIG #define UART8_DMA_RX_CONFIG \ { \ - .DMAy = UART8_RX_DMA, \ - .DMAChx = UART8_RX_DMA_CHType, \ + .DMAy = UART8_RX_DMA, \ + .DMAChx = UART8_RX_DMA_CHType, \ .dma_irq = UART8_RX_DMA_IRQ, \ .dma_rcc = UART8_RX_DMA_RCC, \ .request = UART8_RX_DMA_REQUEST, \ @@ -380,8 +380,8 @@ extern "C" { #ifndef UART8_DMA_TX_CONFIG #define UART8_DMA_TX_CONFIG \ { \ - .DMAy = UART8_TX_DMA, \ - .DMAChx = UART8_TX_DMA_CHType, \ + .DMAy = UART8_TX_DMA, \ + .DMAChx = UART8_TX_DMA_CHType, \ .dma_irq = UART8_TX_DMA_IRQ, \ .dma_rcc = UART8_TX_DMA_RCC, \ .request = UART8_TX_DMA_REQUEST, \ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/can_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/can_config.h new file mode 100644 index 0000000000..679e8571b3 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/can_config.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include <rtthread.h> +#include "n32h49x_fdcan.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct n32_fdcan_config +{ + const char *name; + FDCAN_Module *Instance; + uint32_t std_filter_size; + uint32_t ext_filter_size; + uint32_t rx_fifo0_size; + uint32_t rx_fifo0_data_bytes; + uint32_t rx_fifo1_size; + uint32_t rx_fifo1_data_bytes; + uint32_t rx_buffer_size; + uint32_t rx_buffer_data_bytes; + uint32_t tx_event_size; + uint32_t tx_buffer_size; + uint32_t tx_buffer_data_bytes; + uint32_t tx_fifo_queue_size; + uint32_t tx_fifo_queue_mode; + uint32_t tdc_offset; + uint32_t tdc_filter; + rt_bool_t tdc_enabled; +}; + +#define FDCAN_RESOURCE_CONFIG(number) \ + .std_filter_size = BSP_FDCAN##number##_STD_FILTER_SIZE, \ + .ext_filter_size = BSP_FDCAN##number##_EXT_FILTER_SIZE, \ + .rx_fifo0_size = BSP_FDCAN##number##_RX_FIFO0_SIZE, \ + .rx_fifo0_data_bytes = BSP_FDCAN##number##_RX_FIFO0_DATA_BYTES, \ + .rx_fifo1_size = BSP_FDCAN##number##_RX_FIFO1_SIZE, \ + .rx_fifo1_data_bytes = BSP_FDCAN##number##_RX_FIFO1_DATA_BYTES, \ + .rx_buffer_size = BSP_FDCAN##number##_RX_BUFFER_SIZE, \ + .rx_buffer_data_bytes = BSP_FDCAN##number##_RX_BUFFER_DATA_BYTES, \ + .tx_event_size = BSP_FDCAN##number##_TX_EVENT_FIFO_SIZE, \ + .tx_buffer_size = BSP_FDCAN##number##_TX_BUFFER_SIZE, \ + .tx_buffer_data_bytes = BSP_FDCAN##number##_TX_BUFFER_DATA_BYTES, \ + .tx_fifo_queue_size = BSP_FDCAN##number##_TX_FIFO_QUEUE_SIZE + +#define FDCAN_INSTANCE_CONFIG(number) \ + { \ + .name = "fdcan" #number, \ + .Instance = FDCAN##number, \ + FDCAN_RESOURCE_CONFIG(number), \ + FDCAN##number##_MODE_CONFIG, \ + FDCAN##number##_TDC_CONFIG, \ + } + +#define FDCAN_TX_FIFO_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_FIFO_MODE +#define FDCAN_TX_QUEUE_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_QUEUE_MODE +#define FDCAN_TDC_DISABLED_CONFIG(number) \ + .tdc_enabled = RT_FALSE, .tdc_offset = 0, .tdc_filter = 0 +#define FDCAN_TDC_ENABLED_CONFIG(number) \ + .tdc_enabled = RT_TRUE, \ + .tdc_offset = BSP_FDCAN##number##_TDC_OFFSET, \ + .tdc_filter = BSP_FDCAN##number##_TDC_FILTER + +#if defined(BSP_USING_FDCAN1) +#if defined(BSP_FDCAN1_TX_QUEUE_MODE) +#define FDCAN1_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(1) +#else +#define FDCAN1_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(1) +#endif +#if defined(BSP_FDCAN1_USING_TDC) +#define FDCAN1_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(1) +#else +#define FDCAN1_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(1) +#endif +#define FDCAN1_CONFIG FDCAN_INSTANCE_CONFIG(1) +#endif + +#if defined(BSP_USING_FDCAN2) +#if defined(BSP_FDCAN2_TX_QUEUE_MODE) +#define FDCAN2_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(2) +#else +#define FDCAN2_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(2) +#endif +#if defined(BSP_FDCAN2_USING_TDC) +#define FDCAN2_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(2) +#else +#define FDCAN2_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(2) +#endif +#define FDCAN2_CONFIG FDCAN_INSTANCE_CONFIG(2) +#endif + +#if defined(BSP_USING_FDCAN3) +#if defined(BSP_FDCAN3_TX_QUEUE_MODE) +#define FDCAN3_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(3) +#else +#define FDCAN3_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(3) +#endif +#if defined(BSP_FDCAN3_USING_TDC) +#define FDCAN3_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(3) +#else +#define FDCAN3_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(3) +#endif +#define FDCAN3_CONFIG FDCAN_INSTANCE_CONFIG(3) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h index c9c28c815c..045d1ad44f 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h @@ -19,13 +19,13 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .periph = RCC_APB2_PERIPHEN_USART1, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + .periph = RCC_APB2_PERIPHEN_USART1, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ @@ -34,8 +34,8 @@ extern "C" { #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ { \ - .DMAy = UART1_RX_DMA, \ - .DMAChx = UART1_RX_DMA_CHType, \ + .DMAy = UART1_RX_DMA, \ + .DMAChx = UART1_RX_DMA_CHType, \ .dma_irq = UART1_RX_DMA_IRQ, \ .dma_rcc = UART1_RX_DMA_RCC, \ .request = UART1_RX_DMA_REQUEST, \ @@ -51,8 +51,8 @@ extern "C" { #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ { \ - .DMAy = UART1_TX_DMA, \ - .DMAChx = UART1_TX_DMA_CHType, \ + .DMAy = UART1_TX_DMA, \ + .DMAChx = UART1_TX_DMA_CHType, \ .dma_irq = UART1_TX_DMA_IRQ, \ .dma_rcc = UART1_TX_DMA_RCC, \ .request = UART1_TX_DMA_REQUEST, \ @@ -66,13 +66,13 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .periph = RCC_APB1_PERIPHEN_USART2, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + .periph = RCC_APB1_PERIPHEN_USART2, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ @@ -81,8 +81,8 @@ extern "C" { #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ { \ - .DMAy = UART2_RX_DMA, \ - .DMAChx = UART2_RX_DMA_CHType, \ + .DMAy = UART2_RX_DMA, \ + .DMAChx = UART2_RX_DMA_CHType, \ .dma_irq = UART2_RX_DMA_IRQ, \ .dma_rcc = UART2_RX_DMA_RCC, \ .request = UART2_RX_DMA_REQUEST, \ @@ -98,8 +98,8 @@ extern "C" { #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ { \ - .DMAy = UART2_TX_DMA, \ - .DMAChx = UART2_TX_DMA_CHType, \ + .DMAy = UART2_TX_DMA, \ + .DMAChx = UART2_TX_DMA_CHType, \ .dma_irq = UART2_TX_DMA_IRQ, \ .dma_rcc = UART2_TX_DMA_RCC, \ .request = UART2_TX_DMA_REQUEST, \ @@ -113,13 +113,13 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .periph = RCC_APB1_PERIPHEN_USART3, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .periph = RCC_APB1_PERIPHEN_USART3, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART3_CONFIG */ #endif /* BSP_USING_UART3 */ @@ -128,8 +128,8 @@ extern "C" { #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ { \ - .DMAy = UART3_RX_DMA, \ - .DMAChx = UART3_RX_DMA_CHType, \ + .DMAy = UART3_RX_DMA, \ + .DMAChx = UART3_RX_DMA_CHType, \ .dma_irq = UART3_RX_DMA_IRQ, \ .dma_rcc = UART3_RX_DMA_RCC, \ .request = UART3_RX_DMA_REQUEST, \ @@ -145,8 +145,8 @@ extern "C" { #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ { \ - .DMAy = UART3_TX_DMA, \ - .DMAChx = UART3_TX_DMA_CHType, \ + .DMAy = UART3_TX_DMA, \ + .DMAChx = UART3_TX_DMA_CHType, \ .dma_irq = UART3_TX_DMA_IRQ, \ .dma_rcc = UART3_TX_DMA_RCC, \ .request = UART3_TX_DMA_REQUEST, \ @@ -160,13 +160,13 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = USART4, \ - .irq_type = USART4_IRQn, \ - .periph = RCC_APB2_PERIPHEN_USART4, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = USART4, \ + .irq_type = USART4_IRQn, \ + .periph = RCC_APB2_PERIPHEN_USART4, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART4_CONFIG */ #endif /* BSP_USING_UART4 */ @@ -175,8 +175,8 @@ extern "C" { #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ { \ - .DMAy = UART4_RX_DMA, \ - .DMAChx = UART4_RX_DMA_CHType, \ + .DMAy = UART4_RX_DMA, \ + .DMAChx = UART4_RX_DMA_CHType, \ .dma_irq = UART4_RX_DMA_IRQ, \ .dma_rcc = UART4_RX_DMA_RCC, \ .request = UART4_RX_DMA_REQUEST, \ @@ -192,8 +192,8 @@ extern "C" { #ifndef UART4_DMA_TX_CONFIG #define UART4_DMA_TX_CONFIG \ { \ - .DMAy = UART4_TX_DMA, \ - .DMAChx = UART4_TX_DMA_CHType, \ + .DMAy = UART4_TX_DMA, \ + .DMAChx = UART4_TX_DMA_CHType, \ .dma_irq = UART4_TX_DMA_IRQ, \ .dma_rcc = UART4_TX_DMA_RCC, \ .request = UART4_TX_DMA_REQUEST, \ @@ -209,10 +209,10 @@ extern "C" { #ifndef UART5_CONFIG #define UART5_CONFIG \ { \ - .name = "uart5", \ - .Instance = UART5, \ - .irq_type = UART5_IRQn, \ - .periph = RCC_APB1_PERIPHEN_UART5, \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + .periph = RCC_APB1_PERIPHEN_UART5, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART5_CONFIG */ @@ -222,8 +222,8 @@ extern "C" { #ifndef UART5_DMA_RX_CONFIG #define UART5_DMA_RX_CONFIG \ { \ - .DMAy = UART5_RX_DMA, \ - .DMAChx = UART5_RX_DMA_CHType, \ + .DMAy = UART5_RX_DMA, \ + .DMAChx = UART5_RX_DMA_CHType, \ .dma_irq = UART5_RX_DMA_IRQ, \ .dma_rcc = UART5_RX_DMA_RCC, \ .request = UART5_RX_DMA_REQUEST, \ @@ -239,8 +239,8 @@ extern "C" { #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ { \ - .DMAy = UART5_TX_DMA, \ - .DMAChx = UART5_TX_DMA_CHType, \ + .DMAy = UART5_TX_DMA, \ + .DMAChx = UART5_TX_DMA_CHType, \ .dma_irq = UART5_TX_DMA_IRQ, \ .dma_rcc = UART5_TX_DMA_RCC, \ .request = UART5_TX_DMA_REQUEST, \ @@ -256,10 +256,10 @@ extern "C" { #ifndef UART6_CONFIG #define UART6_CONFIG \ { \ - .name = "uart6", \ - .Instance = UART6, \ - .irq_type = UART6_IRQn, \ - .periph = RCC_APB2_PERIPHEN_UART6, \ + .name = "uart6", \ + .Instance = UART6, \ + .irq_type = UART6_IRQn, \ + .periph = RCC_APB2_PERIPHEN_UART6, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART6_CONFIG */ @@ -269,8 +269,8 @@ extern "C" { #ifndef UART6_DMA_RX_CONFIG #define UART6_DMA_RX_CONFIG \ { \ - .DMAy = UART6_RX_DMA, \ - .DMAChx = UART6_RX_DMA_CHType, \ + .DMAy = UART6_RX_DMA, \ + .DMAChx = UART6_RX_DMA_CHType, \ .dma_irq = UART6_RX_DMA_IRQ, \ .dma_rcc = UART6_RX_DMA_RCC, \ .request = UART6_RX_DMA_REQUEST, \ @@ -286,8 +286,8 @@ extern "C" { #ifndef UART6_DMA_TX_CONFIG #define UART6_DMA_TX_CONFIG \ { \ - .DMAy = UART6_TX_DMA, \ - .DMAChx = UART6_TX_DMA_CHType, \ + .DMAy = UART6_TX_DMA, \ + .DMAChx = UART6_TX_DMA_CHType, \ .dma_irq = UART6_TX_DMA_IRQ, \ .dma_rcc = UART6_TX_DMA_RCC, \ .request = UART6_TX_DMA_REQUEST, \ @@ -303,10 +303,10 @@ extern "C" { #ifndef UART7_CONFIG #define UART7_CONFIG \ { \ - .name = "uart7", \ - .Instance = UART7, \ - .irq_type = UART7_IRQn, \ - .periph = RCC_APB2_PERIPHEN_UART7, \ + .name = "uart7", \ + .Instance = UART7, \ + .irq_type = UART7_IRQn, \ + .periph = RCC_APB2_PERIPHEN_UART7, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART7_CONFIG */ @@ -316,8 +316,8 @@ extern "C" { #ifndef UART7_DMA_RX_CONFIG #define UART7_DMA_RX_CONFIG \ { \ - .DMAy = UART7_RX_DMA, \ - .DMAChx = UART7_RX_DMA_CHType, \ + .DMAy = UART7_RX_DMA, \ + .DMAChx = UART7_RX_DMA_CHType, \ .dma_irq = UART7_RX_DMA_IRQ, \ .dma_rcc = UART7_RX_DMA_RCC, \ .request = UART7_RX_DMA_REQUEST, \ @@ -333,8 +333,8 @@ extern "C" { #ifndef UART7_DMA_TX_CONFIG #define UART7_DMA_TX_CONFIG \ { \ - .DMAy = UART7_TX_DMA, \ - .DMAChx = UART7_TX_DMA_CHType, \ + .DMAy = UART7_TX_DMA, \ + .DMAChx = UART7_TX_DMA_CHType, \ .dma_irq = UART7_TX_DMA_IRQ, \ .dma_rcc = UART7_TX_DMA_RCC, \ .request = UART7_TX_DMA_REQUEST, \ @@ -350,10 +350,10 @@ extern "C" { #ifndef UART8_CONFIG #define UART8_CONFIG \ { \ - .name = "uart8", \ - .Instance = UART8, \ - .irq_type = UART8_IRQn, \ - .periph = RCC_APB1_PERIPHEN_UART8, \ + .name = "uart8", \ + .Instance = UART8, \ + .irq_type = UART8_IRQn, \ + .periph = RCC_APB1_PERIPHEN_UART8, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk, \ } #endif /* UART8_CONFIG */ @@ -363,8 +363,8 @@ extern "C" { #ifndef UART8_DMA_RX_CONFIG #define UART8_DMA_RX_CONFIG \ { \ - .DMAy = UART8_RX_DMA, \ - .DMAChx = UART8_RX_DMA_CHType, \ + .DMAy = UART8_RX_DMA, \ + .DMAChx = UART8_RX_DMA_CHType, \ .dma_irq = UART8_RX_DMA_IRQ, \ .dma_rcc = UART8_RX_DMA_RCC, \ .request = UART8_RX_DMA_REQUEST, \ @@ -380,8 +380,8 @@ extern "C" { #ifndef UART8_DMA_TX_CONFIG #define UART8_DMA_TX_CONFIG \ { \ - .DMAy = UART8_TX_DMA, \ - .DMAChx = UART8_TX_DMA_CHType, \ + .DMAy = UART8_TX_DMA, \ + .DMAChx = UART8_TX_DMA_CHType, \ .dma_irq = UART8_TX_DMA_IRQ, \ .dma_rcc = UART8_TX_DMA_RCC, \ .request = UART8_TX_DMA_REQUEST, \ @@ -395,13 +395,13 @@ extern "C" { #if defined(BSP_USING_UART9) #ifndef UART9_CONFIG -#define UART9_CONFIG \ - { \ - .name = "uart9", \ - .Instance = USART9, \ - .irq_type = USART9_IRQn, \ - .periph = RCC_APB2_PERIPHEN_USART9, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = USART9, \ + .irq_type = USART9_IRQn, \ + .periph = RCC_APB2_PERIPHEN_USART9, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART9_CONFIG */ #endif /* BSP_USING_UART9 */ @@ -410,8 +410,8 @@ extern "C" { #ifndef UART9_DMA_RX_CONFIG #define UART9_DMA_RX_CONFIG \ { \ - .DMAy = UART9_RX_DMA, \ - .DMAChx = UART9_RX_DMA_CHType, \ + .DMAy = UART9_RX_DMA, \ + .DMAChx = UART9_RX_DMA_CHType, \ .dma_irq = UART9_RX_DMA_IRQ, \ .dma_rcc = UART9_RX_DMA_RCC, \ .request = UART9_RX_DMA_REQUEST, \ @@ -427,8 +427,8 @@ extern "C" { #ifndef UART9_DMA_TX_CONFIG #define UART9_DMA_TX_CONFIG \ { \ - .DMAy = UART9_TX_DMA, \ - .DMAChx = UART9_TX_DMA_CHType, \ + .DMAy = UART9_TX_DMA, \ + .DMAChx = UART9_TX_DMA_CHType, \ .dma_irq = UART9_TX_DMA_IRQ, \ .dma_rcc = UART9_TX_DMA_RCC, \ .request = UART9_TX_DMA_REQUEST, \ @@ -442,13 +442,13 @@ extern "C" { #if defined(BSP_USING_UART10) #ifndef UART10_CONFIG -#define UART10_CONFIG \ - { \ - .name = "uart10", \ - .Instance = URT10, \ - .irq_type = UART10_IRQn, \ - .periph = RCC_APB2_PERIPHEN_UART10, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = URT10, \ + .irq_type = UART10_IRQn, \ + .periph = RCC_APB2_PERIPHEN_UART10, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk, \ } #endif /* UART10_CONFIG */ #endif /* BSP_USING_UART10 */ @@ -457,8 +457,8 @@ extern "C" { #ifndef UART10_DMA_RX_CONFIG #define UART10_DMA_RX_CONFIG \ { \ - .DMAy = UART10_RX_DMA, \ - .DMAChx = UART10_RX_DMA_CHType, \ + .DMAy = UART10_RX_DMA, \ + .DMAChx = UART10_RX_DMA_CHType, \ .dma_irq = UART10_RX_DMA_IRQ, \ .dma_rcc = UART10_RX_DMA_RCC, \ .request = UART10_RX_DMA_REQUEST, \ @@ -474,8 +474,8 @@ extern "C" { #ifndef UART10_DMA_TX_CONFIG #define UART10_DMA_TX_CONFIG \ { \ - .DMAy = UART10_TX_DMA, \ - .DMAChx = UART10_TX_DMA_CHType, \ + .DMAy = UART10_TX_DMA, \ + .DMAChx = UART10_TX_DMA_CHType, \ .dma_irq = UART10_TX_DMA_IRQ, \ .dma_rcc = UART10_TX_DMA_RCC, \ .request = UART10_TX_DMA_REQUEST, \ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h index d3f23b6587..e0167c57cd 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h @@ -19,72 +19,72 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_CONFIG -#define ADC1_CONFIG \ - { \ - .ADCx = ADC1, \ - .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \ - .EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \ - .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ - .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ - .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ - .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ - .Init.MultiChEn = DISABLE, \ - .Init.ContinueConvEn = DISABLE, \ - .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ - .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ - .Init.DatAlign = ADC_DAT_ALIGN_R, \ - .Init.ChsNumber = 1U, \ - .Init.Resolution = ADC_DATA_RES_12BIT, \ - .Rank = 1U, \ - .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ +#define ADC1_CONFIG \ + { \ + .ADCx = ADC1, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ } #endif /* ADC1_CONFIG */ #endif /* BSP_USING_ADC1 */ #ifdef BSP_USING_ADC2 #ifndef ADC2_CONFIG -#define ADC2_CONFIG \ - { \ - .ADCx = ADC2, \ - .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \ - .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ - .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ - .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ - .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ - .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ - .Init.MultiChEn = DISABLE, \ - .Init.ContinueConvEn = DISABLE, \ - .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ - .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ - .Init.DatAlign = ADC_DAT_ALIGN_R, \ - .Init.ChsNumber = 1U, \ - .Init.Resolution = ADC_DATA_RES_12BIT, \ - .Rank = 1U, \ - .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ +#define ADC2_CONFIG \ + { \ + .ADCx = ADC2, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ } #endif /* ADC2_CONFIG */ #endif /* BSP_USING_ADC2 */ #ifdef BSP_USING_ADC3 #ifndef ADC3_CONFIG -#define ADC3_CONFIG \ - { \ - .ADCx = ADC3, \ - .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \ - .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ - .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ - .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ - .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ - .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ - .Init.MultiChEn = DISABLE, \ - .Init.ContinueConvEn = DISABLE, \ - .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ - .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ - .Init.DatAlign = ADC_DAT_ALIGN_R, \ - .Init.ChsNumber = 1U, \ - .Init.Resolution = ADC_DATA_RES_12BIT, \ - .Rank = 1U, \ - .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ +#define ADC3_CONFIG \ + { \ + .ADCx = ADC3, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ } #endif /* ADC3_CONFIG */ #endif /* BSP_USING_ADC3 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h index 71bce0b5dc..fa6a155f80 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h @@ -2,10 +2,6 @@ * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2026-06-22 lin.qi first version */ #ifndef __CAN_CONFIG_H__ @@ -18,106 +14,173 @@ extern "C" { #endif -/** - *\*\name n32_fdcan_config. - *\*\brief FDCAN instance configuration structure. - *\*\note Clock and GPIO initialization are handled by CubeMX-generated code - *\*\ in n32h7xx_cfg.c (from Cube.ntfx). NVIC interrupt vector numbers - *\*\ are hardcoded in drv_fdcan.c per instance. - */ struct n32_fdcan_config { - const char *name; /**< device name */ - FDCAN_Module *Instance; /**< FDCAN peripheral base address */ + const char *name; + FDCAN_Module *Instance; + uint32_t std_filter_size; + uint32_t ext_filter_size; + uint32_t rx_fifo0_size; + uint32_t rx_fifo0_data_bytes; + uint32_t rx_fifo1_size; + uint32_t rx_fifo1_data_bytes; + uint32_t rx_buffer_size; + uint32_t rx_buffer_data_bytes; + uint32_t tx_event_size; + uint32_t tx_buffer_size; + uint32_t tx_buffer_data_bytes; + uint32_t tx_fifo_queue_size; + uint32_t tx_fifo_queue_mode; + uint32_t tdc_offset; + uint32_t tdc_filter; + rt_bool_t tdc_enabled; }; -/* - * Hardware connection pairs on N32H760ZIL7-STB: - * FDCAN1 <-> FDCAN2 - * FDCAN3 <-> FDCAN4 - * FDCAN5 <-> FDCAN6 - * FDCAN7 <-> FDCAN8 - */ +#define FDCAN_RESOURCE_CONFIG(number) \ + .std_filter_size = BSP_FDCAN##number##_STD_FILTER_SIZE, \ + .ext_filter_size = BSP_FDCAN##number##_EXT_FILTER_SIZE, \ + .rx_fifo0_size = BSP_FDCAN##number##_RX_FIFO0_SIZE, \ + .rx_fifo0_data_bytes = BSP_FDCAN##number##_RX_FIFO0_DATA_BYTES, \ + .rx_fifo1_size = BSP_FDCAN##number##_RX_FIFO1_SIZE, \ + .rx_fifo1_data_bytes = BSP_FDCAN##number##_RX_FIFO1_DATA_BYTES, \ + .rx_buffer_size = BSP_FDCAN##number##_RX_BUFFER_SIZE, \ + .rx_buffer_data_bytes = BSP_FDCAN##number##_RX_BUFFER_DATA_BYTES, \ + .tx_event_size = BSP_FDCAN##number##_TX_EVENT_FIFO_SIZE, \ + .tx_buffer_size = BSP_FDCAN##number##_TX_BUFFER_SIZE, \ + .tx_buffer_data_bytes = BSP_FDCAN##number##_TX_BUFFER_DATA_BYTES, \ + .tx_fifo_queue_size = BSP_FDCAN##number##_TX_FIFO_QUEUE_SIZE -#if defined(BSP_USING_FDCAN1) -#ifndef FDCAN1_CONFIG -#define FDCAN1_CONFIG \ - { \ - .name = "fdcan1", \ - .Instance = FDCAN1, \ +#define FDCAN_INSTANCE_CONFIG(number) \ + { \ + .name = "fdcan" #number, \ + .Instance = FDCAN##number, \ + FDCAN_RESOURCE_CONFIG(number), \ + FDCAN##number##_MODE_CONFIG, \ + FDCAN##number##_TDC_CONFIG, \ } + +#define FDCAN_TX_FIFO_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_FIFO_MODE +#define FDCAN_TX_QUEUE_CONFIG(number) \ + .tx_fifo_queue_mode = FDCAN_TX_QUEUE_MODE +#define FDCAN_TDC_DISABLED_CONFIG(number) \ + .tdc_enabled = RT_FALSE, .tdc_offset = 0, .tdc_filter = 0 +#define FDCAN_TDC_ENABLED_CONFIG(number) \ + .tdc_enabled = RT_TRUE, \ + .tdc_offset = BSP_FDCAN##number##_TDC_OFFSET, \ + .tdc_filter = BSP_FDCAN##number##_TDC_FILTER + +#if defined(BSP_USING_FDCAN1) +#if defined(BSP_FDCAN1_TX_QUEUE_MODE) +#define FDCAN1_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(1) +#else +#define FDCAN1_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(1) +#endif +#if defined(BSP_FDCAN1_USING_TDC) +#define FDCAN1_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(1) +#else +#define FDCAN1_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(1) +#endif +#define FDCAN1_CONFIG FDCAN_INSTANCE_CONFIG(1) #endif -#endif /* BSP_USING_FDCAN1 */ #if defined(BSP_USING_FDCAN2) -#ifndef FDCAN2_CONFIG -#define FDCAN2_CONFIG \ - { \ - .name = "fdcan2", \ - .Instance = FDCAN2, \ - } +#if defined(BSP_FDCAN2_TX_QUEUE_MODE) +#define FDCAN2_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(2) +#else +#define FDCAN2_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(2) +#endif +#if defined(BSP_FDCAN2_USING_TDC) +#define FDCAN2_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(2) +#else +#define FDCAN2_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(2) +#endif +#define FDCAN2_CONFIG FDCAN_INSTANCE_CONFIG(2) #endif -#endif /* BSP_USING_FDCAN2 */ #if defined(BSP_USING_FDCAN3) -#ifndef FDCAN3_CONFIG -#define FDCAN3_CONFIG \ - { \ - .name = "fdcan3", \ - .Instance = FDCAN3, \ - } +#if defined(BSP_FDCAN3_TX_QUEUE_MODE) +#define FDCAN3_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(3) +#else +#define FDCAN3_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(3) +#endif +#if defined(BSP_FDCAN3_USING_TDC) +#define FDCAN3_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(3) +#else +#define FDCAN3_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(3) +#endif +#define FDCAN3_CONFIG FDCAN_INSTANCE_CONFIG(3) #endif -#endif /* BSP_USING_FDCAN3 */ #if defined(BSP_USING_FDCAN4) -#ifndef FDCAN4_CONFIG -#define FDCAN4_CONFIG \ - { \ - .name = "fdcan4", \ - .Instance = FDCAN4, \ - } +#if defined(BSP_FDCAN4_TX_QUEUE_MODE) +#define FDCAN4_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(4) +#else +#define FDCAN4_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(4) +#endif +#if defined(BSP_FDCAN4_USING_TDC) +#define FDCAN4_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(4) +#else +#define FDCAN4_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(4) +#endif +#define FDCAN4_CONFIG FDCAN_INSTANCE_CONFIG(4) #endif -#endif /* BSP_USING_FDCAN4 */ #if defined(BSP_USING_FDCAN5) -#ifndef FDCAN5_CONFIG -#define FDCAN5_CONFIG \ - { \ - .name = "fdcan5", \ - .Instance = FDCAN5, \ - } +#if defined(BSP_FDCAN5_TX_QUEUE_MODE) +#define FDCAN5_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(5) +#else +#define FDCAN5_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(5) +#endif +#if defined(BSP_FDCAN5_USING_TDC) +#define FDCAN5_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(5) +#else +#define FDCAN5_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(5) +#endif +#define FDCAN5_CONFIG FDCAN_INSTANCE_CONFIG(5) #endif -#endif /* BSP_USING_FDCAN5 */ #if defined(BSP_USING_FDCAN6) -#ifndef FDCAN6_CONFIG -#define FDCAN6_CONFIG \ - { \ - .name = "fdcan6", \ - .Instance = FDCAN6, \ - } +#if defined(BSP_FDCAN6_TX_QUEUE_MODE) +#define FDCAN6_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(6) +#else +#define FDCAN6_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(6) +#endif +#if defined(BSP_FDCAN6_USING_TDC) +#define FDCAN6_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(6) +#else +#define FDCAN6_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(6) +#endif +#define FDCAN6_CONFIG FDCAN_INSTANCE_CONFIG(6) #endif -#endif /* BSP_USING_FDCAN6 */ #if defined(BSP_USING_FDCAN7) -#ifndef FDCAN7_CONFIG -#define FDCAN7_CONFIG \ - { \ - .name = "fdcan7", \ - .Instance = FDCAN7, \ - } +#if defined(BSP_FDCAN7_TX_QUEUE_MODE) +#define FDCAN7_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(7) +#else +#define FDCAN7_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(7) +#endif +#if defined(BSP_FDCAN7_USING_TDC) +#define FDCAN7_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(7) +#else +#define FDCAN7_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(7) +#endif +#define FDCAN7_CONFIG FDCAN_INSTANCE_CONFIG(7) #endif -#endif /* BSP_USING_FDCAN7 */ #if defined(BSP_USING_FDCAN8) -#ifndef FDCAN8_CONFIG -#define FDCAN8_CONFIG \ - { \ - .name = "fdcan8", \ - .Instance = FDCAN8, \ - } +#if defined(BSP_FDCAN8_TX_QUEUE_MODE) +#define FDCAN8_MODE_CONFIG FDCAN_TX_QUEUE_CONFIG(8) +#else +#define FDCAN8_MODE_CONFIG FDCAN_TX_FIFO_CONFIG(8) +#endif +#if defined(BSP_FDCAN8_USING_TDC) +#define FDCAN8_TDC_CONFIG FDCAN_TDC_ENABLED_CONFIG(8) +#else +#define FDCAN8_TDC_CONFIG FDCAN_TDC_DISABLED_CONFIG(8) +#endif +#define FDCAN8_CONFIG FDCAN_INSTANCE_CONFIG(8) #endif -#endif /* BSP_USING_FDCAN8 */ #ifdef __cplusplus } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h index b1256573d8..67fd7458dc 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h @@ -19,46 +19,46 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_CONFIG -#define DAC1_CONFIG \ - { \ - .DACx = DAC1, \ - .DAC_Module = DAC12, \ - .periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \ - .DAC_clk_pres = 150, \ - .Init.DAC_Trigger = DAC_Trigger_Software, \ - .Init.DAC_Trigger2 = DAC_Trigger2_Software, \ - .Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \ - .Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \ - .Init.DAC_OutputBuffer = DISABLE, \ - .Init.DAC_TriggerEnable = ENABLE, \ - .Init.DAC_ConnectOnChipPeripheral = DISABLE, \ - .Init.DAC_ConnectExternalPin = ENABLE, \ - .Init.DAC_DMADoubleDataMode = DISABLE, \ - .Init.DAC_SignedFormat = DISABLE, \ +#define DAC1_CONFIG \ + { \ + .DACx = DAC1, \ + .DAC_Module = DAC12, \ + .periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \ + .DAC_clk_pres = 150, \ + .Init.DAC_Trigger = DAC_Trigger_Software, \ + .Init.DAC_Trigger2 = DAC_Trigger2_Software, \ + .Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \ + .Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \ + .Init.DAC_OutputBuffer = DISABLE, \ + .Init.DAC_TriggerEnable = ENABLE, \ + .Init.DAC_ConnectOnChipPeripheral = DISABLE, \ + .Init.DAC_ConnectExternalPin = ENABLE, \ + .Init.DAC_DMADoubleDataMode = DISABLE, \ + .Init.DAC_SignedFormat = DISABLE, \ } #endif /* DAC1_CONFIG */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_CONFIG -#define DAC2_CONFIG \ - { \ - .DACx = DAC2, \ - .DAC_Module = DAC12, \ - .periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \ - .DAC_clk_pres = 150, \ - .Init.DAC_Trigger = DAC_Trigger_Software, \ - .Init.DAC_Trigger2 = DAC_Trigger2_Software, \ - .Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \ - .Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \ - .Init.DAC_OutputBuffer = DISABLE, \ - .Init.DAC_TriggerEnable = ENABLE, \ - .Init.DAC_ConnectOnChipPeripheral = DISABLE, \ - .Init.DAC_ConnectExternalPin = ENABLE, \ - .Init.DAC_DMADoubleDataMode = DISABLE, \ - .Init.DAC_SignedFormat = DISABLE, \ +#define DAC2_CONFIG \ + { \ + .DACx = DAC2, \ + .DAC_Module = DAC12, \ + .periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \ + .DAC_clk_pres = 150, \ + .Init.DAC_Trigger = DAC_Trigger_Software, \ + .Init.DAC_Trigger2 = DAC_Trigger2_Software, \ + .Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \ + .Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \ + .Init.DAC_OutputBuffer = DISABLE, \ + .Init.DAC_TriggerEnable = ENABLE, \ + .Init.DAC_ConnectOnChipPeripheral = DISABLE, \ + .Init.DAC_ConnectExternalPin = ENABLE, \ + .Init.DAC_DMADoubleDataMode = DISABLE, \ + .Init.DAC_SignedFormat = DISABLE, \ } #endif /* DAC2_CONFIG */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h index 08de65cc08..ac32f682f3 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h @@ -21,16 +21,16 @@ extern "C" { #ifndef I2C1_BUS_CONFIG #define I2C1_BUS_CONFIG \ { \ - .name = "hwi2c1", \ - .Instance = I2C1, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C1_EV_IRQn, \ - .erirq_type = I2C1_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB1_PERIPHEN_M7_I2C1, \ + .name = "hwi2c1", \ + .Instance = I2C1, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C1, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ .I2CKerClkSource = RCC_ConfigI2C1KerClkSource, \ } @@ -40,11 +40,11 @@ extern "C" { #ifndef I2C1_RX_DMA_CONFIG #define I2C1_RX_DMA_CONFIG \ { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .dma_irq = I2C1_RX_DMA_IRQ, \ - .HsInterface = I2C1_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C1_RX_DMA_DMA_RCC, \ - .dma_channel = I2C1_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .HsInterface = I2C1_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C1_RX_DMA_DMA_RCC, \ + .dma_channel = I2C1_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C1_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C1_RX_DMA_DMAMUX_REQUEST, \ } @@ -54,11 +54,11 @@ extern "C" { #ifndef I2C1_TX_DMA_CONFIG #define I2C1_TX_DMA_CONFIG \ { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .dma_irq = I2C1_TX_DMA_IRQ, \ - .HsInterface = I2C1_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C1_TX_DMA_DMA_RCC, \ - .dma_channel = I2C1_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .HsInterface = I2C1_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C1_TX_DMA_DMA_RCC, \ + .dma_channel = I2C1_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C1_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C1_TX_DMA_DMAMUX_REQUEST, \ } @@ -69,16 +69,16 @@ extern "C" { #ifndef I2C2_BUS_CONFIG #define I2C2_BUS_CONFIG \ { \ - .name = "hwi2c2", \ - .Instance = I2C2, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C2_EV_IRQn, \ - .erirq_type = I2C2_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB1_PERIPHEN_M7_I2C2, \ + .name = "hwi2c2", \ + .Instance = I2C2, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C2, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ .I2CKerClkSource = RCC_ConfigI2C2KerClkSource, \ } @@ -88,11 +88,11 @@ extern "C" { #ifndef I2C2_RX_DMA_CONFIG #define I2C2_RX_DMA_CONFIG \ { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .dma_irq = I2C2_RX_DMA_IRQ, \ - .HsInterface = I2C2_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C2_RX_DMA_DMA_RCC, \ - .dma_channel = I2C2_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .HsInterface = I2C2_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C2_RX_DMA_DMA_RCC, \ + .dma_channel = I2C2_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C2_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C2_RX_DMA_DMAMUX_REQUEST, \ } @@ -102,11 +102,11 @@ extern "C" { #ifndef I2C2_TX_DMA_CONFIG #define I2C2_TX_DMA_CONFIG \ { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .dma_irq = I2C2_TX_DMA_IRQ, \ - .HsInterface = I2C2_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C2_TX_DMA_DMA_RCC, \ - .dma_channel = I2C2_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .HsInterface = I2C2_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C2_TX_DMA_DMA_RCC, \ + .dma_channel = I2C2_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C2_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C2_TX_DMA_DMAMUX_REQUEST, \ } @@ -117,16 +117,16 @@ extern "C" { #ifndef I2C3_BUS_CONFIG #define I2C3_BUS_CONFIG \ { \ - .name = "hwi2c3", \ - .Instance = I2C3, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C3_EV_IRQn, \ - .erirq_type = I2C3_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB1_PERIPHEN_M7_I2C3, \ + .name = "hwi2c3", \ + .Instance = I2C3, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C3, \ .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ .I2CKerClkSource = RCC_ConfigI2C3KerClkSource, \ } @@ -136,11 +136,11 @@ extern "C" { #ifndef I2C3_RX_DMA_CONFIG #define I2C3_RX_DMA_CONFIG \ { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .dma_irq = I2C3_RX_DMA_IRQ, \ - .HsInterface = I2C3_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C3_RX_DMA_DMA_RCC, \ - .dma_channel = I2C3_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .HsInterface = I2C3_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C3_RX_DMA_DMA_RCC, \ + .dma_channel = I2C3_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C3_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C3_RX_DMA_DMAMUX_REQUEST, \ } @@ -150,11 +150,11 @@ extern "C" { #ifndef I2C3_TX_DMA_CONFIG #define I2C3_TX_DMA_CONFIG \ { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .dma_irq = I2C3_TX_DMA_IRQ, \ - .HsInterface = I2C3_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C3_TX_DMA_DMA_RCC, \ - .dma_channel = I2C3_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .HsInterface = I2C3_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C3_TX_DMA_DMA_RCC, \ + .dma_channel = I2C3_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C3_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C3_TX_DMA_DMAMUX_REQUEST, \ } @@ -165,16 +165,16 @@ extern "C" { #ifndef I2C4_BUS_CONFIG #define I2C4_BUS_CONFIG \ { \ - .name = "hwi2c4", \ - .Instance = I2C4, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C4_EV_IRQn, \ - .erirq_type = I2C4_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB2_PERIPHEN_M7_I2C4, \ + .name = "hwi2c4", \ + .Instance = I2C4, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C4, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C4KerClkSource, \ } @@ -184,11 +184,11 @@ extern "C" { #ifndef I2C4_RX_DMA_CONFIG #define I2C4_RX_DMA_CONFIG \ { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .dma_irq = I2C4_RX_DMA_IRQ, \ - .HsInterface = I2C4_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C4_RX_DMA_DMA_RCC, \ - .dma_channel = I2C4_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .HsInterface = I2C4_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C4_RX_DMA_DMA_RCC, \ + .dma_channel = I2C4_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C4_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C4_RX_DMA_DMAMUX_REQUEST, \ } @@ -198,11 +198,11 @@ extern "C" { #ifndef I2C4_TX_DMA_CONFIG #define I2C4_TX_DMA_CONFIG \ { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .dma_irq = I2C4_TX_DMA_IRQ, \ - .HsInterface = I2C4_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C4_TX_DMA_DMA_RCC, \ - .dma_channel = I2C4_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .HsInterface = I2C4_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C4_TX_DMA_DMA_RCC, \ + .dma_channel = I2C4_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C4_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C4_TX_DMA_DMAMUX_REQUEST, \ } @@ -213,16 +213,16 @@ extern "C" { #ifndef I2C5_BUS_CONFIG #define I2C5_BUS_CONFIG \ { \ - .name = "hwi2c5", \ - .Instance = I2C5, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C5_EV_IRQn, \ - .erirq_type = I2C5_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB2_PERIPHEN_M7_I2C5, \ + .name = "hwi2c5", \ + .Instance = I2C5, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C5_EV_IRQn, \ + .erirq_type = I2C5_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C5, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C5KerClkSource, \ } @@ -232,11 +232,11 @@ extern "C" { #ifndef I2C5_RX_DMA_CONFIG #define I2C5_RX_DMA_CONFIG \ { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .dma_irq = I2C5_RX_DMA_IRQ, \ - .HsInterface = I2C5_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C5_RX_DMA_DMA_RCC, \ - .dma_channel = I2C5_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .dma_irq = I2C5_RX_DMA_IRQ, \ + .HsInterface = I2C5_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C5_RX_DMA_DMA_RCC, \ + .dma_channel = I2C5_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C5_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C5_RX_DMA_DMAMUX_REQUEST, \ } @@ -246,11 +246,11 @@ extern "C" { #ifndef I2C5_TX_DMA_CONFIG #define I2C5_TX_DMA_CONFIG \ { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .dma_irq = I2C5_TX_DMA_IRQ, \ - .HsInterface = I2C5_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C5_TX_DMA_DMA_RCC, \ - .dma_channel = I2C5_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .dma_irq = I2C5_TX_DMA_IRQ, \ + .HsInterface = I2C5_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C5_TX_DMA_DMA_RCC, \ + .dma_channel = I2C5_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C5_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C5_TX_DMA_DMAMUX_REQUEST, \ } @@ -261,16 +261,16 @@ extern "C" { #ifndef I2C6_BUS_CONFIG #define I2C6_BUS_CONFIG \ { \ - .name = "hwi2c6", \ - .Instance = I2C6, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C6_EV_IRQn, \ - .erirq_type = I2C6_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB2_PERIPHEN_M7_I2C6, \ + .name = "hwi2c6", \ + .Instance = I2C6, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C6_EV_IRQn, \ + .erirq_type = I2C6_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C6, \ .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C6KerClkSource, \ } @@ -280,11 +280,11 @@ extern "C" { #ifndef I2C6_RX_DMA_CONFIG #define I2C6_RX_DMA_CONFIG \ { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .dma_irq = I2C6_RX_DMA_IRQ, \ - .HsInterface = I2C6_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C6_RX_DMA_DMA_RCC, \ - .dma_channel = I2C6_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .dma_irq = I2C6_RX_DMA_IRQ, \ + .HsInterface = I2C6_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C6_RX_DMA_DMA_RCC, \ + .dma_channel = I2C6_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C6_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C6_RX_DMA_DMAMUX_REQUEST, \ } @@ -294,11 +294,11 @@ extern "C" { #ifndef I2C6_TX_DMA_CONFIG #define I2C6_TX_DMA_CONFIG \ { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .dma_irq = I2C6_TX_DMA_IRQ, \ - .HsInterface = I2C6_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C6_TX_DMA_DMA_RCC, \ - .dma_channel = I2C6_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .dma_irq = I2C6_TX_DMA_IRQ, \ + .HsInterface = I2C6_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C6_TX_DMA_DMA_RCC, \ + .dma_channel = I2C6_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C6_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C6_TX_DMA_DMAMUX_REQUEST, \ } @@ -309,16 +309,16 @@ extern "C" { #ifndef I2C7_BUS_CONFIG #define I2C7_BUS_CONFIG \ { \ - .name = "hwi2c7", \ - .Instance = I2C7, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C7_EV_IRQn, \ - .erirq_type = I2C7_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB5_PERIPHEN_M7_I2C7, \ + .name = "hwi2c7", \ + .Instance = I2C7, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C7_EV_IRQn, \ + .erirq_type = I2C7_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C7, \ .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C7KerClkSource, \ } @@ -328,11 +328,11 @@ extern "C" { #ifndef I2C7_RX_DMA_CONFIG #define I2C7_RX_DMA_CONFIG \ { \ - .Instance = I2C7_RX_DMA_INSTANCE, \ - .dma_irq = I2C7_RX_DMA_IRQ, \ - .HsInterface = I2C7_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C7_RX_DMA_DMA_RCC, \ - .dma_channel = I2C7_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C7_RX_DMA_INSTANCE, \ + .dma_irq = I2C7_RX_DMA_IRQ, \ + .HsInterface = I2C7_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C7_RX_DMA_DMA_RCC, \ + .dma_channel = I2C7_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C7_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C7_RX_DMA_DMAMUX_REQUEST, \ } @@ -342,11 +342,11 @@ extern "C" { #ifndef I2C7_TX_DMA_CONFIG #define I2C7_TX_DMA_CONFIG \ { \ - .Instance = I2C7_TX_DMA_INSTANCE, \ - .dma_irq = I2C7_TX_DMA_IRQ, \ - .HsInterface = I2C7_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C7_TX_DMA_DMA_RCC, \ - .dma_channel = I2C7_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C7_TX_DMA_INSTANCE, \ + .dma_irq = I2C7_TX_DMA_IRQ, \ + .HsInterface = I2C7_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C7_TX_DMA_DMA_RCC, \ + .dma_channel = I2C7_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C7_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C7_TX_DMA_DMAMUX_REQUEST, \ } @@ -357,16 +357,16 @@ extern "C" { #ifndef I2C8_BUS_CONFIG #define I2C8_BUS_CONFIG \ { \ - .name = "hwi2c8", \ - .Instance = I2C8, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C8_EV_IRQn, \ - .erirq_type = I2C8_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB5_PERIPHEN_M7_I2C8, \ + .name = "hwi2c8", \ + .Instance = I2C8, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C8_EV_IRQn, \ + .erirq_type = I2C8_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C8, \ .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C8KerClkSource, \ } @@ -376,11 +376,11 @@ extern "C" { #ifndef I2C8_RX_DMA_CONFIG #define I2C8_RX_DMA_CONFIG \ { \ - .Instance = I2C8_RX_DMA_INSTANCE, \ - .dma_irq = I2C8_RX_DMA_IRQ, \ - .HsInterface = I2C8_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C8_RX_DMA_DMA_RCC, \ - .dma_channel = I2C8_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C8_RX_DMA_INSTANCE, \ + .dma_irq = I2C8_RX_DMA_IRQ, \ + .HsInterface = I2C8_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C8_RX_DMA_DMA_RCC, \ + .dma_channel = I2C8_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C8_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C8_RX_DMA_DMAMUX_REQUEST, \ } @@ -390,11 +390,11 @@ extern "C" { #ifndef I2C8_TX_DMA_CONFIG #define I2C8_TX_DMA_CONFIG \ { \ - .Instance = I2C8_TX_DMA_INSTANCE, \ - .dma_irq = I2C8_TX_DMA_IRQ, \ - .HsInterface = I2C8_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C8_TX_DMA_DMA_RCC, \ - .dma_channel = I2C8_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C8_TX_DMA_INSTANCE, \ + .dma_irq = I2C8_TX_DMA_IRQ, \ + .HsInterface = I2C8_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C8_TX_DMA_DMA_RCC, \ + .dma_channel = I2C8_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C8_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C8_TX_DMA_DMAMUX_REQUEST, \ } @@ -405,16 +405,16 @@ extern "C" { #ifndef I2C9_BUS_CONFIG #define I2C9_BUS_CONFIG \ { \ - .name = "hwi2c9", \ - .Instance = I2C9, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C9_EV_IRQn, \ - .erirq_type = I2C9_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB5_PERIPHEN_M7_I2C9, \ + .name = "hwi2c9", \ + .Instance = I2C9, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C9_EV_IRQn, \ + .erirq_type = I2C9_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C9, \ .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C9KerClkSource, \ } @@ -424,11 +424,11 @@ extern "C" { #ifndef I2C9_RX_DMA_CONFIG #define I2C9_RX_DMA_CONFIG \ { \ - .Instance = I2C9_RX_DMA_INSTANCE, \ - .dma_irq = I2C9_RX_DMA_IRQ, \ - .HsInterface = I2C9_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C9_RX_DMA_DMA_RCC, \ - .dma_channel = I2C9_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C9_RX_DMA_INSTANCE, \ + .dma_irq = I2C9_RX_DMA_IRQ, \ + .HsInterface = I2C9_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C9_RX_DMA_DMA_RCC, \ + .dma_channel = I2C9_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C9_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C9_RX_DMA_DMAMUX_REQUEST, \ } @@ -438,11 +438,11 @@ extern "C" { #ifndef I2C9_TX_DMA_CONFIG #define I2C9_TX_DMA_CONFIG \ { \ - .Instance = I2C9_TX_DMA_INSTANCE, \ - .dma_irq = I2C9_TX_DMA_IRQ, \ - .HsInterface = I2C9_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C9_TX_DMA_DMA_RCC, \ - .dma_channel = I2C9_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C9_TX_DMA_INSTANCE, \ + .dma_irq = I2C9_TX_DMA_IRQ, \ + .HsInterface = I2C9_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C9_TX_DMA_DMA_RCC, \ + .dma_channel = I2C9_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C9_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C9_TX_DMA_DMAMUX_REQUEST, \ } @@ -453,16 +453,16 @@ extern "C" { #ifndef I2C10_BUS_CONFIG #define I2C10_BUS_CONFIG \ { \ - .name = "hwi2c10", \ - .Instance = I2C10, \ - .timing = 0x50012526, \ - .timeout = 0x1000, \ - .evirq_type = I2C10_EV_IRQn, \ - .erirq_type = I2C10_ER_IRQn, \ - .scl_af_width = 0, \ - .sda_af_width = 0, \ - .df_width = 0, \ - .periph = RCC_APB5_PERIPHEN_M7_I2C10, \ + .name = "hwi2c10", \ + .Instance = I2C10, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C10_EV_IRQn, \ + .erirq_type = I2C10_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C10, \ .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ .I2CKerClkSource = RCC_ConfigI2C10KerClkSource, \ } @@ -472,11 +472,11 @@ extern "C" { #ifndef I2C10_RX_DMA_CONFIG #define I2C10_RX_DMA_CONFIG \ { \ - .Instance = I2C10_RX_DMA_INSTANCE, \ - .dma_irq = I2C10_RX_DMA_IRQ, \ - .HsInterface = I2C10_RX_DMA_HANDSHAK, \ - .dma_rcc = I2C10_RX_DMA_DMA_RCC, \ - .dma_channel = I2C10_RX_DMA_DMA_CHANNEL, \ + .Instance = I2C10_RX_DMA_INSTANCE, \ + .dma_irq = I2C10_RX_DMA_IRQ, \ + .HsInterface = I2C10_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C10_RX_DMA_DMA_RCC, \ + .dma_channel = I2C10_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C10_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C10_RX_DMA_DMAMUX_REQUEST, \ } @@ -486,11 +486,11 @@ extern "C" { #ifndef I2C10_TX_DMA_CONFIG #define I2C10_TX_DMA_CONFIG \ { \ - .Instance = I2C10_TX_DMA_INSTANCE, \ - .dma_irq = I2C10_TX_DMA_IRQ, \ - .HsInterface = I2C10_TX_DMA_HANDSHAK, \ - .dma_rcc = I2C10_TX_DMA_DMA_RCC, \ - .dma_channel = I2C10_TX_DMA_DMA_CHANNEL, \ + .Instance = I2C10_TX_DMA_INSTANCE, \ + .dma_irq = I2C10_TX_DMA_IRQ, \ + .HsInterface = I2C10_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C10_TX_DMA_DMA_RCC, \ + .dma_channel = I2C10_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = I2C10_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = I2C10_TX_DMA_DMAMUX_REQUEST, \ } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h index eceb6d5193..ebea68d41c 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h @@ -22,7 +22,7 @@ extern "C" { { \ .maxfreq = 1000000, \ .minfreq = 3000, \ - .maxcnt = 0xFFFF, \ + .maxcnt = 0xFFFF, \ .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* LPTIM_DEV_INFO_CONFIG */ @@ -31,9 +31,9 @@ extern "C" { #ifndef LPTIM1_CONFIG #define LPTIM1_CONFIG \ { \ - .timer = LPTIM1, \ + .timer = LPTIM1, \ .tim_irqn = LPTIM1_WKUP_IRQn, \ - .name = "lptim1", \ + .name = "lptim1", \ } #endif /* LPTIM1_CONFIG */ #endif /* BSP_USING_LPTIM1 */ @@ -42,9 +42,9 @@ extern "C" { #ifndef LPTIM2_CONFIG #define LPTIM2_CONFIG \ { \ - .timer = LPTIM2, \ + .timer = LPTIM2, \ .tim_irqn = LPTIM2_WKUP_IRQn, \ - .name = "lptim2", \ + .name = "lptim2", \ } #endif /* LPTIM2_CONFIG */ #endif /* BSP_USING_LPTIM2 */ @@ -53,9 +53,9 @@ extern "C" { #ifndef LPTIM3_CONFIG #define LPTIM3_CONFIG \ { \ - .timer = LPTIM3, \ + .timer = LPTIM3, \ .tim_irqn = LPTIM3_WKUP_IRQn, \ - .name = "lptim3", \ + .name = "lptim3", \ } #endif /* LPTIM3_CONFIG */ #endif /* BSP_USING_LPTIM3 */ @@ -64,9 +64,9 @@ extern "C" { #ifndef LPTIM4_CONFIG #define LPTIM4_CONFIG \ { \ - .timer = LPTIM4, \ + .timer = LPTIM4, \ .tim_irqn = LPTIM4_WKUP_IRQn, \ - .name = "lptim4", \ + .name = "lptim4", \ } #endif /* LPTIM4_CONFIG */ #endif /* BSP_USING_LPTIM4 */ @@ -75,9 +75,9 @@ extern "C" { #ifndef LPTIM5_CONFIG #define LPTIM5_CONFIG \ { \ - .timer = LPTIM5, \ + .timer = LPTIM5, \ .tim_irqn = LPTIM5_WKUP_IRQn, \ - .name = "lptim5", \ + .name = "lptim5", \ } #endif /* LPTIM5_CONFIG */ #endif /* BSP_USING_LPTIM5 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h index 824d95efd5..e2adbe7336 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h @@ -21,9 +21,9 @@ extern "C" { #ifndef PULSE_ENCODER1_CONFIG #define PULSE_ENCODER1_CONFIG \ { \ - .timer = ATIM1, \ + .timer = ATIM1, \ .tim_irqn = ATIM1_UP_IRQn, \ - .name = "pulse1", \ + .name = "pulse1", \ } #endif /* PULSE_ENCODER1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER1 */ @@ -32,9 +32,9 @@ extern "C" { #ifndef PULSE_ENCODER2_CONFIG #define PULSE_ENCODER2_CONFIG \ { \ - .timer = ATIM2, \ + .timer = ATIM2, \ .tim_irqn = ATIM2_UP_IRQn, \ - .name = "pulse2", \ + .name = "pulse2", \ } #endif /* PULSE_ENCODER2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER2 */ @@ -43,9 +43,9 @@ extern "C" { #ifndef PULSE_ENCODER3_CONFIG #define PULSE_ENCODER3_CONFIG \ { \ - .timer = ATIM3, \ + .timer = ATIM3, \ .tim_irqn = ATIM3_UP_IRQn, \ - .name = "pulse3", \ + .name = "pulse3", \ } #endif /* PULSE_ENCODER3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER3 */ @@ -54,9 +54,9 @@ extern "C" { #ifndef PULSE_ENCODER4_CONFIG #define PULSE_ENCODER4_CONFIG \ { \ - .timer = ATIM4, \ + .timer = ATIM4, \ .tim_irqn = ATIM4_UP_IRQn, \ - .name = "pulse4", \ + .name = "pulse4", \ } #endif /* PULSE_ENCODER4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER4 */ @@ -65,9 +65,9 @@ extern "C" { #ifndef PULSE_ENCODER5_CONFIG #define PULSE_ENCODER5_CONFIG \ { \ - .timer = GTIMA1, \ + .timer = GTIMA1, \ .tim_irqn = GTIMA1_IRQn, \ - .name = "pulse5", \ + .name = "pulse5", \ } #endif /* PULSE_ENCODER5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER5 */ @@ -76,9 +76,9 @@ extern "C" { #ifndef PULSE_ENCODER6_CONFIG #define PULSE_ENCODER6_CONFIG \ { \ - .timer = GTIMA2, \ + .timer = GTIMA2, \ .tim_irqn = GTIMA2_IRQn, \ - .name = "pulse6", \ + .name = "pulse6", \ } #endif /* PULSE_ENCODER6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER6 */ @@ -87,9 +87,9 @@ extern "C" { #ifndef PULSE_ENCODER7_CONFIG #define PULSE_ENCODER7_CONFIG \ { \ - .timer = GTIMA3, \ + .timer = GTIMA3, \ .tim_irqn = GTIMA3_IRQn, \ - .name = "pulse7", \ + .name = "pulse7", \ } #endif /* PULSE_ENCODER7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER7 */ @@ -98,9 +98,9 @@ extern "C" { #ifndef PULSE_ENCODER8_CONFIG #define PULSE_ENCODER8_CONFIG \ { \ - .timer = GTIMA4, \ + .timer = GTIMA4, \ .tim_irqn = GTIMA4_IRQn, \ - .name = "pulse8", \ + .name = "pulse8", \ } #endif /* PULSE_ENCODER8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER8 */ @@ -109,9 +109,9 @@ extern "C" { #ifndef PULSE_ENCODER9_CONFIG #define PULSE_ENCODER9_CONFIG \ { \ - .timer = GTIMA5, \ + .timer = GTIMA5, \ .tim_irqn = GTIMA5_IRQn, \ - .name = "pulse9", \ + .name = "pulse9", \ } #endif /* PULSE_ENCODER9_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER9 */ @@ -120,9 +120,9 @@ extern "C" { #ifndef PULSE_ENCODER10_CONFIG #define PULSE_ENCODER10_CONFIG \ { \ - .timer = GTIMA6, \ + .timer = GTIMA6, \ .tim_irqn = GTIMA6_IRQn, \ - .name = "pulse10", \ + .name = "pulse10", \ } #endif /* PULSE_ENCODER10_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER10 */ @@ -131,9 +131,9 @@ extern "C" { #ifndef PULSE_ENCODER11_CONFIG #define PULSE_ENCODER11_CONFIG \ { \ - .timer = GTIMA7, \ + .timer = GTIMA7, \ .tim_irqn = GTIMA7_IRQn, \ - .name = "pulse11", \ + .name = "pulse11", \ } #endif /* PULSE_ENCODER11_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER11 */ @@ -142,9 +142,9 @@ extern "C" { #ifndef PULSE_ENCODER12_CONFIG #define PULSE_ENCODER12_CONFIG \ { \ - .timer = GTIMB1, \ + .timer = GTIMB1, \ .tim_irqn = GTIMB1_IRQn, \ - .name = "pulse12", \ + .name = "pulse12", \ } #endif /* PULSE_ENCODER12_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER12 */ @@ -153,9 +153,9 @@ extern "C" { #ifndef PULSE_ENCODER13_CONFIG #define PULSE_ENCODER13_CONFIG \ { \ - .timer = GTIMB2, \ + .timer = GTIMB2, \ .tim_irqn = GTIMB2_IRQn, \ - .name = "pulse13", \ + .name = "pulse13", \ } #endif /* PULSE_ENCODER13_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER13 */ @@ -164,9 +164,9 @@ extern "C" { #ifndef PULSE_ENCODER14_CONFIG #define PULSE_ENCODER14_CONFIG \ { \ - .timer = GTIMB3, \ + .timer = GTIMB3, \ .tim_irqn = GTIMB3_IRQn, \ - .name = "pulse14", \ + .name = "pulse14", \ } #endif /* PULSE_ENCODER14_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER14 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pwm_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pwm_config.h index 0888968436..b137d42af7 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pwm_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pwm_config.h @@ -19,154 +19,154 @@ extern "C" { #ifdef BSP_USING_PWM1 #ifndef PWM1_CONFIG -#define PWM1_CONFIG \ - { \ - .timer = ATIM1, \ - .name = "pwm1", \ - .channel = 0 \ +#define PWM1_CONFIG \ + { \ + .timer = ATIM1, \ + .name = "pwm1", \ + .channel = 0 \ } #endif /* PWM1_CONFIG */ #endif /* BSP_USING_PWM1 */ #ifdef BSP_USING_PWM2 #ifndef PWM2_CONFIG -#define PWM2_CONFIG \ - { \ - .timer = ATIM2, \ - .name = "pwm2", \ - .channel = 0 \ +#define PWM2_CONFIG \ + { \ + .timer = ATIM2, \ + .name = "pwm2", \ + .channel = 0 \ } #endif /* PWM2_CONFIG */ #endif /* BSP_USING_PWM2 */ #ifdef BSP_USING_PWM3 #ifndef PWM3_CONFIG -#define PWM3_CONFIG \ - { \ - .timer = ATIM3, \ - .name = "pwm3", \ - .channel = 0 \ +#define PWM3_CONFIG \ + { \ + .timer = ATIM3, \ + .name = "pwm3", \ + .channel = 0 \ } #endif /* PWM3_CONFIG */ #endif /* BSP_USING_PWM3 */ #ifdef BSP_USING_PWM4 #ifndef PWM4_CONFIG -#define PWM4_CONFIG \ - { \ - .timer = ATIM4, \ - .name = "pwm4", \ - .channel = 0 \ +#define PWM4_CONFIG \ + { \ + .timer = ATIM4, \ + .name = "pwm4", \ + .channel = 0 \ } #endif /* PWM4_CONFIG */ #endif /* BSP_USING_PWM4 */ #ifdef BSP_USING_PWM5 #ifndef PWM5_CONFIG -#define PWM5_CONFIG \ - { \ - .timer = GTIMA1, \ - .name = "pwm5", \ - .channel = 0 \ +#define PWM5_CONFIG \ + { \ + .timer = GTIMA1, \ + .name = "pwm5", \ + .channel = 0 \ } #endif /* PWM5_CONFIG */ #endif /* BSP_USING_PWM5 */ #ifdef BSP_USING_PWM6 #ifndef PWM6_CONFIG -#define PWM6_CONFIG \ - { \ - .timer = GTIMA2, \ - .name = "pwm6", \ - .channel = 0 \ +#define PWM6_CONFIG \ + { \ + .timer = GTIMA2, \ + .name = "pwm6", \ + .channel = 0 \ } #endif /* PWM6_CONFIG */ #endif /* BSP_USING_PWM6 */ #ifdef BSP_USING_PWM7 #ifndef PWM7_CONFIG -#define PWM7_CONFIG \ - { \ - .timer = GTIMA3, \ - .name = "pwm7", \ - .channel = 0 \ +#define PWM7_CONFIG \ + { \ + .timer = GTIMA3, \ + .name = "pwm7", \ + .channel = 0 \ } #endif /* PWM7_CONFIG */ #endif /* BSP_USING_PWM7 */ #ifdef BSP_USING_PWM8 #ifndef PWM8_CONFIG -#define PWM8_CONFIG \ - { \ - .timer = GTIMA4, \ - .name = "pwm8", \ - .channel = 0 \ +#define PWM8_CONFIG \ + { \ + .timer = GTIMA4, \ + .name = "pwm8", \ + .channel = 0 \ } #endif /* PWM8_CONFIG */ #endif /* BSP_USING_PWM8 */ #ifdef BSP_USING_PWM9 #ifndef PWM9_CONFIG -#define PWM9_CONFIG \ - { \ - .timer = GTIMA5, \ - .name = "pwm9", \ - .channel = 0 \ +#define PWM9_CONFIG \ + { \ + .timer = GTIMA5, \ + .name = "pwm9", \ + .channel = 0 \ } #endif /* PWM9_CONFIG */ #endif /* BSP_USING_PWM9 */ #ifdef BSP_USING_PWM10 #ifndef PWM10_CONFIG -#define PWM10_CONFIG \ - { \ - .timer = GTIMA6, \ - .name = "pwm10", \ - .channel = 0 \ +#define PWM10_CONFIG \ + { \ + .timer = GTIMA6, \ + .name = "pwm10", \ + .channel = 0 \ } #endif /* PWM10_CONFIG */ #endif /* BSP_USING_PWM10 */ #ifdef BSP_USING_PWM11 #ifndef PWM11_CONFIG -#define PWM11_CONFIG \ - { \ - .timer = GTIMA7, \ - .name = "pwm11", \ - .channel = 0 \ +#define PWM11_CONFIG \ + { \ + .timer = GTIMA7, \ + .name = "pwm11", \ + .channel = 0 \ } #endif /* PWM11_CONFIG */ #endif /* BSP_USING_PWM11 */ #ifdef BSP_USING_PWM12 #ifndef PWM12_CONFIG -#define PWM12_CONFIG \ - { \ - .timer = GTIMB1, \ - .name = "pwm12", \ - .channel = 0 \ +#define PWM12_CONFIG \ + { \ + .timer = GTIMB1, \ + .name = "pwm12", \ + .channel = 0 \ } #endif /* PWM12_CONFIG */ #endif /* BSP_USING_PWM12 */ #ifdef BSP_USING_PWM13 #ifndef PWM13_CONFIG -#define PWM13_CONFIG \ - { \ - .timer = GTIMB2, \ - .name = "pwm13", \ - .channel = 0 \ +#define PWM13_CONFIG \ + { \ + .timer = GTIMB2, \ + .name = "pwm13", \ + .channel = 0 \ } #endif /* PWM13_CONFIG */ #endif /* BSP_USING_PWM13 */ #ifdef BSP_USING_PWM14 #ifndef PWM14_CONFIG -#define PWM14_CONFIG \ - { \ - .timer = GTIMB3, \ - .name = "pwm14", \ - .channel = 0 \ +#define PWM14_CONFIG \ + { \ + .timer = GTIMB3, \ + .name = "pwm14", \ + .channel = 0 \ } #endif /* PWM14_CONFIG */ #endif /* BSP_USING_PWM14 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/spi_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/spi_config.h index fc00c218d7..edbd7c8940 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/spi_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/spi_config.h @@ -21,7 +21,7 @@ extern "C" { #ifndef SPI1_BUS_CONFIG #define SPI1_BUS_CONFIG \ { \ - .SPIx = SPI1, \ + .SPIx = SPI1, \ .bus_name = "spi1", \ .irq_type = SPI1_IRQn, \ } @@ -31,11 +31,11 @@ extern "C" { #ifndef SPI1_TX_DMA_CONFIG #define SPI1_TX_DMA_CONFIG \ { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .dma_irq = SPI1_TX_DMA_IRQ, \ - .HsInterface = SPI1_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI1_TX_DMA_DMA_RCC, \ - .dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + .HsInterface = SPI1_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI1_TX_DMA_DMA_RCC, \ + .dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \ } @@ -45,11 +45,11 @@ extern "C" { #ifndef SPI1_RX_DMA_CONFIG #define SPI1_RX_DMA_CONFIG \ { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .dma_irq = SPI1_RX_DMA_IRQ, \ - .HsInterface = SPI1_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI1_RX_DMA_DMA_RCC, \ - .dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + .HsInterface = SPI1_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI1_RX_DMA_DMA_RCC, \ + .dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \ } @@ -60,7 +60,7 @@ extern "C" { #ifndef SPI2_BUS_CONFIG #define SPI2_BUS_CONFIG \ { \ - .SPIx = SPI2, \ + .SPIx = SPI2, \ .bus_name = "spi2", \ .irq_type = SPI2_IRQn, \ } @@ -70,11 +70,11 @@ extern "C" { #ifndef SPI2_TX_DMA_CONFIG #define SPI2_TX_DMA_CONFIG \ { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .dma_irq = SPI2_TX_DMA_IRQ, \ - .HsInterface = SPI2_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI2_TX_DMA_DMA_RCC, \ - .dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + .HsInterface = SPI2_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI2_TX_DMA_DMA_RCC, \ + .dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \ } @@ -84,11 +84,11 @@ extern "C" { #ifndef SPI2_RX_DMA_CONFIG #define SPI2_RX_DMA_CONFIG \ { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .dma_irq = SPI2_RX_DMA_IRQ, \ - .HsInterface = SPI2_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI2_RX_DMA_DMA_RCC, \ - .dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + .HsInterface = SPI2_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI2_RX_DMA_DMA_RCC, \ + .dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \ } @@ -99,7 +99,7 @@ extern "C" { #ifndef SPI3_BUS_CONFIG #define SPI3_BUS_CONFIG \ { \ - .SPIx = SPI3, \ + .SPIx = SPI3, \ .bus_name = "spi3", \ .irq_type = SPI3_IRQn, \ } @@ -109,11 +109,11 @@ extern "C" { #ifndef SPI3_TX_DMA_CONFIG #define SPI3_TX_DMA_CONFIG \ { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .dma_irq = SPI3_TX_DMA_IRQ, \ - .HsInterface = SPI3_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI3_TX_DMA_DMA_RCC, \ - .dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + .HsInterface = SPI3_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI3_TX_DMA_DMA_RCC, \ + .dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \ } @@ -123,11 +123,11 @@ extern "C" { #ifndef SPI3_RX_DMA_CONFIG #define SPI3_RX_DMA_CONFIG \ { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .dma_irq = SPI3_RX_DMA_IRQ, \ - .HsInterface = SPI3_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI3_RX_DMA_DMA_RCC, \ - .dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + .HsInterface = SPI3_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI3_RX_DMA_DMA_RCC, \ + .dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \ } @@ -138,7 +138,7 @@ extern "C" { #ifndef SPI4_BUS_CONFIG #define SPI4_BUS_CONFIG \ { \ - .SPIx = SPI4, \ + .SPIx = SPI4, \ .bus_name = "spi4", \ .irq_type = SPI4_IRQn, \ } @@ -148,11 +148,11 @@ extern "C" { #ifndef SPI4_TX_DMA_CONFIG #define SPI4_TX_DMA_CONFIG \ { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .dma_irq = SPI4_TX_DMA_IRQ, \ - .HsInterface = SPI4_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI4_TX_DMA_DMA_RCC, \ - .dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + .HsInterface = SPI4_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI4_TX_DMA_DMA_RCC, \ + .dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \ } @@ -162,11 +162,11 @@ extern "C" { #ifndef SPI4_RX_DMA_CONFIG #define SPI4_RX_DMA_CONFIG \ { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .dma_irq = SPI4_RX_DMA_IRQ, \ - .HsInterface = SPI4_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI4_RX_DMA_DMA_RCC, \ - .dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + .HsInterface = SPI4_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI4_RX_DMA_DMA_RCC, \ + .dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \ } @@ -177,7 +177,7 @@ extern "C" { #ifndef SPI5_BUS_CONFIG #define SPI5_BUS_CONFIG \ { \ - .SPIx = SPI5, \ + .SPIx = SPI5, \ .bus_name = "spi5", \ .irq_type = SPI5_IRQn, \ } @@ -187,11 +187,11 @@ extern "C" { #ifndef SPI5_TX_DMA_CONFIG #define SPI5_TX_DMA_CONFIG \ { \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .dma_irq = SPI5_TX_DMA_IRQ, \ - .HsInterface = SPI5_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI5_TX_DMA_DMA_RCC, \ - .dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + .HsInterface = SPI5_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI5_TX_DMA_DMA_RCC, \ + .dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \ } @@ -201,11 +201,11 @@ extern "C" { #ifndef SPI5_RX_DMA_CONFIG #define SPI5_RX_DMA_CONFIG \ { \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .dma_irq = SPI5_RX_DMA_IRQ, \ - .HsInterface = SPI5_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI5_RX_DMA_DMA_RCC, \ - .dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + .HsInterface = SPI5_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI5_RX_DMA_DMA_RCC, \ + .dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \ } @@ -216,7 +216,7 @@ extern "C" { #ifndef SPI6_BUS_CONFIG #define SPI6_BUS_CONFIG \ { \ - .SPIx = SPI6, \ + .SPIx = SPI6, \ .bus_name = "spi6", \ .irq_type = SPI6_IRQn, \ } @@ -226,11 +226,11 @@ extern "C" { #ifndef SPI6_TX_DMA_CONFIG #define SPI6_TX_DMA_CONFIG \ { \ - .Instance = SPI6_TX_DMA_INSTANCE, \ - .dma_irq = SPI6_TX_DMA_IRQ, \ - .HsInterface = SPI6_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI6_TX_DMA_DMA_RCC, \ - .dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .dma_irq = SPI6_TX_DMA_IRQ, \ + .HsInterface = SPI6_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI6_TX_DMA_DMA_RCC, \ + .dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \ } @@ -240,11 +240,11 @@ extern "C" { #ifndef SPI6_RX_DMA_CONFIG #define SPI6_RX_DMA_CONFIG \ { \ - .Instance = SPI6_RX_DMA_INSTANCE, \ - .dma_irq = SPI6_RX_DMA_IRQ, \ - .HsInterface = SPI6_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI6_RX_DMA_DMA_RCC, \ - .dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .dma_irq = SPI6_RX_DMA_IRQ, \ + .HsInterface = SPI6_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI6_RX_DMA_DMA_RCC, \ + .dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \ } @@ -255,7 +255,7 @@ extern "C" { #ifndef SPI7_BUS_CONFIG #define SPI7_BUS_CONFIG \ { \ - .SPIx = SPI7, \ + .SPIx = SPI7, \ .bus_name = "spi7", \ .irq_type = SPI7_IRQn, \ } @@ -265,11 +265,11 @@ extern "C" { #ifndef SPI7_TX_DMA_CONFIG #define SPI7_TX_DMA_CONFIG \ { \ - .Instance = SPI7_TX_DMA_INSTANCE, \ - .dma_irq = SPI7_TX_DMA_IRQ, \ - .HsInterface = SPI7_TX_DMA_HANDSHAK, \ - .dma_rcc = SPI7_TX_DMA_DMA_RCC, \ - .dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \ + .Instance = SPI7_TX_DMA_INSTANCE, \ + .dma_irq = SPI7_TX_DMA_IRQ, \ + .HsInterface = SPI7_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI7_TX_DMA_DMA_RCC, \ + .dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \ } @@ -279,11 +279,11 @@ extern "C" { #ifndef SPI7_RX_DMA_CONFIG #define SPI7_RX_DMA_CONFIG \ { \ - .Instance = SPI7_RX_DMA_INSTANCE, \ - .dma_irq = SPI7_RX_DMA_IRQ, \ - .HsInterface = SPI7_RX_DMA_HANDSHAK, \ - .dma_rcc = SPI7_RX_DMA_DMA_RCC, \ - .dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \ + .Instance = SPI7_RX_DMA_INSTANCE, \ + .dma_irq = SPI7_RX_DMA_IRQ, \ + .HsInterface = SPI7_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI7_RX_DMA_DMA_RCC, \ + .dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \ } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/tim_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/tim_config.h index 153b1c4f11..d24baed1f0 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/tim_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/tim_config.h @@ -22,7 +22,7 @@ extern "C" { { \ .maxfreq = 1000000, \ .minfreq = 3000, \ - .maxcnt = 0xFFFF, \ + .maxcnt = 0xFFFF, \ .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ @@ -31,9 +31,9 @@ extern "C" { #ifndef ATIM1_CONFIG #define ATIM1_CONFIG \ { \ - .timer = ATIM1, \ + .timer = ATIM1, \ .tim_irqn = ATIM1_UP_IRQn, \ - .name = "timer1", \ + .name = "timer1", \ } #endif /* ATIM1_CONFIG */ #endif /* BSP_USING_ATIM1 */ @@ -42,9 +42,9 @@ extern "C" { #ifndef ATIM2_CONFIG #define ATIM2_CONFIG \ { \ - .timer = ATIM2, \ + .timer = ATIM2, \ .tim_irqn = ATIM2_UP_IRQn, \ - .name = "timer2", \ + .name = "timer2", \ } #endif /* ATIM2_CONFIG */ #endif /* BSP_USING_ATIM2 */ @@ -53,9 +53,9 @@ extern "C" { #ifndef ATIM3_CONFIG #define ATIM3_CONFIG \ { \ - .timer = ATIM3, \ + .timer = ATIM3, \ .tim_irqn = ATIM3_UP_IRQn, \ - .name = "timer3", \ + .name = "timer3", \ } #endif /* ATIM3_CONFIG */ #endif /* BSP_USING_ATIM3 */ @@ -64,9 +64,9 @@ extern "C" { #ifndef ATIM4_CONFIG #define ATIM4_CONFIG \ { \ - .timer = ATIM4, \ + .timer = ATIM4, \ .tim_irqn = ATIM4_UP_IRQn, \ - .name = "timer4", \ + .name = "timer4", \ } #endif /* ATIM4_CONFIG */ #endif /* BSP_USING_ATIM4 */ @@ -75,9 +75,9 @@ extern "C" { #ifndef GTIMA1_CONFIG #define GTIMA1_CONFIG \ { \ - .timer = GTIMA1, \ + .timer = GTIMA1, \ .tim_irqn = GTIMA1_IRQn, \ - .name = "timer5", \ + .name = "timer5", \ } #endif /* GTIMA1_CONFIG */ #endif /* BSP_USING_GTIMA1 */ @@ -86,9 +86,9 @@ extern "C" { #ifndef GTIMA2_CONFIG #define GTIMA2_CONFIG \ { \ - .timer = GTIMA2, \ + .timer = GTIMA2, \ .tim_irqn = GTIMA2_IRQn, \ - .name = "timer6", \ + .name = "timer6", \ } #endif /* GTIMA2_CONFIG */ #endif /* BSP_USING_GTIMA2 */ @@ -97,9 +97,9 @@ extern "C" { #ifndef GTIMA3_CONFIG #define GTIMA3_CONFIG \ { \ - .timer = GTIMA3, \ + .timer = GTIMA3, \ .tim_irqn = GTIMA3_IRQn, \ - .name = "timer7", \ + .name = "timer7", \ } #endif /* GTIMA3_CONFIG */ #endif /* BSP_USING_GTIMA3 */ @@ -108,9 +108,9 @@ extern "C" { #ifndef GTIMA4_CONFIG #define GTIMA4_CONFIG \ { \ - .timer = GTIMA4, \ + .timer = GTIMA4, \ .tim_irqn = GTIMA4_IRQn, \ - .name = "timer8", \ + .name = "timer8", \ } #endif /* GTIMA4_CONFIG */ #endif /* BSP_USING_GTIMA4 */ @@ -119,9 +119,9 @@ extern "C" { #ifndef GTIMA5_CONFIG #define GTIMA5_CONFIG \ { \ - .timer = GTIMA5, \ + .timer = GTIMA5, \ .tim_irqn = GTIMA5_IRQn, \ - .name = "timer9", \ + .name = "timer9", \ } #endif /* GTIMA5_CONFIG */ #endif /* BSP_USING_GTIMA5 */ @@ -130,9 +130,9 @@ extern "C" { #ifndef GTIMA6_CONFIG #define GTIMA6_CONFIG \ { \ - .timer = GTIMA6, \ + .timer = GTIMA6, \ .tim_irqn = GTIMA6_IRQn, \ - .name = "timer10", \ + .name = "timer10", \ } #endif /* GTIMA6_CONFIG */ #endif /* BSP_USING_GTIMA6 */ @@ -141,9 +141,9 @@ extern "C" { #ifndef GTIMA7_CONFIG #define GTIMA7_CONFIG \ { \ - .timer = GTIMA7, \ + .timer = GTIMA7, \ .tim_irqn = GTIMA7_IRQn, \ - .name = "timer11", \ + .name = "timer11", \ } #endif /* GTIMA7_CONFIG */ #endif /* BSP_USING_GTIMA7 */ @@ -152,9 +152,9 @@ extern "C" { #ifndef GTIMB1_CONFIG #define GTIMB1_CONFIG \ { \ - .timer = GTIMB1, \ + .timer = GTIMB1, \ .tim_irqn = GTIMB1_IRQn, \ - .name = "timer12", \ + .name = "timer12", \ } #endif /* GTIMB1_CONFIG */ #endif /* BSP_USING_GTIMB1 */ @@ -163,9 +163,9 @@ extern "C" { #ifndef GTIMB2_CONFIG #define GTIMB2_CONFIG \ { \ - .timer = GTIMB2, \ + .timer = GTIMB2, \ .tim_irqn = GTIMB2_IRQn, \ - .name = "timer13", \ + .name = "timer13", \ } #endif /* GTIMB2_CONFIG */ #endif /* BSP_USING_GTIMB2 */ @@ -174,9 +174,9 @@ extern "C" { #ifndef GTIMB3_CONFIG #define GTIMB3_CONFIG \ { \ - .timer = GTIMB3, \ + .timer = GTIMB3, \ .tim_irqn = GTIMB3_IRQn, \ - .name = "timer14", \ + .name = "timer14", \ } #endif /* GTIMB3_CONFIG */ #endif /* BSP_USING_GTIMB3 */ @@ -185,9 +185,9 @@ extern "C" { #ifndef BTIM1_CONFIG #define BTIM1_CONFIG \ { \ - .timer = BTIM1, \ + .timer = BTIM1, \ .tim_irqn = BTIM1_IRQn, \ - .name = "timer15", \ + .name = "timer15", \ } #endif /* BTIM1_CONFIG */ #endif /* BSP_USING_BTIM1 */ @@ -196,9 +196,9 @@ extern "C" { #ifndef BTIM2_CONFIG #define BTIM2_CONFIG \ { \ - .timer = BTIM2, \ + .timer = BTIM2, \ .tim_irqn = BTIM2_IRQn, \ - .name = "timer16", \ + .name = "timer16", \ } #endif /* BTIM2_CONFIG */ #endif /* BSP_USING_BTIM2 */ @@ -207,9 +207,9 @@ extern "C" { #ifndef BTIM3_CONFIG #define BTIM3_CONFIG \ { \ - .timer = BTIM3, \ + .timer = BTIM3, \ .tim_irqn = BTIM3_IRQn, \ - .name = "timer17", \ + .name = "timer17", \ } #endif /* BTIM3_CONFIG */ #endif /* BSP_USING_BTIM3 */ @@ -218,9 +218,9 @@ extern "C" { #ifndef BTIM4_CONFIG #define BTIM4_CONFIG \ { \ - .timer = BTIM4, \ + .timer = BTIM4, \ .tim_irqn = BTIM4_IRQn, \ - .name = "timer18", \ + .name = "timer18", \ } #endif /* BTIM4_CONFIG */ #endif /* BSP_USING_BTIM4 */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h index 0446664921..9787ce26dc 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h @@ -19,13 +19,13 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = USART1, \ - .irq_type = USART1_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_USART1, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART1, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ @@ -34,11 +34,11 @@ extern "C" { #ifndef UART1_DMA_RX_CONFIG #define UART1_DMA_RX_CONFIG \ { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - .HsInterface = UART1_RX_DMA_HANDSHAK, \ - .dma_rcc = UART1_RX_DMA_DMA_RCC, \ - .dma_channel = UART1_RX_DMA_DMA_CHANNEL, \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + .HsInterface = UART1_RX_DMA_HANDSHAK, \ + .dma_rcc = UART1_RX_DMA_DMA_RCC, \ + .dma_channel = UART1_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART1_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART1_RX_DMA_DMAMUX_REQUEST, \ } @@ -52,11 +52,11 @@ extern "C" { #ifndef UART1_DMA_TX_CONFIG #define UART1_DMA_TX_CONFIG \ { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .dma_irq = UART1_TX_DMA_IRQ, \ - .HsInterface = UART1_TX_DMA_HANDSHAK, \ - .dma_rcc = UART1_TX_DMA_DMA_RCC, \ - .dma_channel = UART1_TX_DMA_DMA_CHANNEL, \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + .HsInterface = UART1_TX_DMA_HANDSHAK, \ + .dma_rcc = UART1_TX_DMA_DMA_RCC, \ + .dma_channel = UART1_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART1_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART1_TX_DMA_DMAMUX_REQUEST, \ } @@ -68,13 +68,13 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = USART2, \ - .irq_type = USART2_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_USART2, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART2, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ @@ -83,11 +83,11 @@ extern "C" { #ifndef UART2_DMA_RX_CONFIG #define UART2_DMA_RX_CONFIG \ { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - .HsInterface = UART2_RX_DMA_HANDSHAK, \ - .dma_rcc = UART2_RX_DMA_DMA_RCC, \ - .dma_channel = UART2_RX_DMA_DMA_CHANNEL, \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + .HsInterface = UART2_RX_DMA_HANDSHAK, \ + .dma_rcc = UART2_RX_DMA_DMA_RCC, \ + .dma_channel = UART2_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART2_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART2_RX_DMA_DMAMUX_REQUEST, \ } @@ -101,11 +101,11 @@ extern "C" { #ifndef UART2_DMA_TX_CONFIG #define UART2_DMA_TX_CONFIG \ { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .dma_irq = UART2_TX_DMA_IRQ, \ - .HsInterface = UART2_TX_DMA_HANDSHAK, \ - .dma_rcc = UART2_TX_DMA_DMA_RCC, \ - .dma_channel = UART2_TX_DMA_DMA_CHANNEL, \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + .HsInterface = UART2_TX_DMA_HANDSHAK, \ + .dma_rcc = UART2_TX_DMA_DMA_RCC, \ + .dma_channel = UART2_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART2_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART2_TX_DMA_DMAMUX_REQUEST, \ } @@ -117,13 +117,13 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = USART3, \ - .irq_type = USART3_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_USART3, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART3, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART3_CONFIG */ #endif /* BSP_USING_UART3 */ @@ -132,11 +132,11 @@ extern "C" { #ifndef UART3_DMA_RX_CONFIG #define UART3_DMA_RX_CONFIG \ { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .dma_irq = UART3_RX_DMA_IRQ, \ - .HsInterface = UART3_RX_DMA_HANDSHAK, \ - .dma_rcc = UART3_RX_DMA_DMA_RCC, \ - .dma_channel = UART3_RX_DMA_DMA_CHANNEL, \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + .HsInterface = UART3_RX_DMA_HANDSHAK, \ + .dma_rcc = UART3_RX_DMA_DMA_RCC, \ + .dma_channel = UART3_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART3_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART3_RX_DMA_DMAMUX_REQUEST, \ } @@ -150,11 +150,11 @@ extern "C" { #ifndef UART3_DMA_TX_CONFIG #define UART3_DMA_TX_CONFIG \ { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .dma_irq = UART3_TX_DMA_IRQ, \ - .HsInterface = UART3_TX_DMA_HANDSHAK, \ - .dma_rcc = UART3_TX_DMA_DMA_RCC, \ - .dma_channel = UART3_TX_DMA_DMA_CHANNEL, \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + .HsInterface = UART3_TX_DMA_HANDSHAK, \ + .dma_rcc = UART3_TX_DMA_DMA_RCC, \ + .dma_channel = UART3_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART3_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART3_TX_DMA_DMAMUX_REQUEST, \ } @@ -166,13 +166,13 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = USART4, \ - .irq_type = USART4_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_USART4, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = USART4, \ + .irq_type = USART4_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART4, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART4_CONFIG */ #endif /* BSP_USING_UART4 */ @@ -181,11 +181,11 @@ extern "C" { #ifndef UART4_DMA_RX_CONFIG #define UART4_DMA_RX_CONFIG \ { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .dma_irq = UART4_RX_DMA_IRQ, \ - .HsInterface = UART4_RX_DMA_HANDSHAK, \ - .dma_rcc = UART4_RX_DMA_DMA_RCC, \ - .dma_channel = UART4_RX_DMA_DMA_CHANNEL, \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + .HsInterface = UART4_RX_DMA_HANDSHAK, \ + .dma_rcc = UART4_RX_DMA_DMA_RCC, \ + .dma_channel = UART4_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART4_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART4_RX_DMA_DMAMUX_REQUEST, \ } @@ -199,11 +199,11 @@ extern "C" { #ifndef UART4_DMA_TX_CONFIG #define UART4_DMA_TX_CONFIG \ { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .dma_irq = UART4_TX_DMA_IRQ, \ - .HsInterface = UART4_TX_DMA_HANDSHAK, \ - .dma_rcc = UART4_TX_DMA_DMA_RCC, \ - .dma_channel = UART4_TX_DMA_DMA_CHANNEL, \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + .HsInterface = UART4_TX_DMA_HANDSHAK, \ + .dma_rcc = UART4_TX_DMA_DMA_RCC, \ + .dma_channel = UART4_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART4_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART4_TX_DMA_DMAMUX_REQUEST, \ } @@ -215,13 +215,13 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = USART5, \ - .irq_type = USART5_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_USART5, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = USART5, \ + .irq_type = USART5_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART5, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART5_CONFIG */ #endif /* BSP_USING_UART5 */ @@ -230,11 +230,11 @@ extern "C" { #ifndef UART5_DMA_RX_CONFIG #define UART5_DMA_RX_CONFIG \ { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .dma_irq = UART5_RX_DMA_IRQ, \ - .HsInterface = UART5_RX_DMA_HANDSHAK, \ - .dma_rcc = UART5_RX_DMA_DMA_RCC, \ - .dma_channel = UART5_RX_DMA_DMA_CHANNEL, \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .dma_irq = UART5_RX_DMA_IRQ, \ + .HsInterface = UART5_RX_DMA_HANDSHAK, \ + .dma_rcc = UART5_RX_DMA_DMA_RCC, \ + .dma_channel = UART5_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART5_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART5_RX_DMA_DMAMUX_REQUEST, \ } @@ -248,11 +248,11 @@ extern "C" { #ifndef UART5_DMA_TX_CONFIG #define UART5_DMA_TX_CONFIG \ { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .dma_irq = UART5_TX_DMA_IRQ, \ - .HsInterface = UART5_TX_DMA_HANDSHAK, \ - .dma_rcc = UART5_TX_DMA_DMA_RCC, \ - .dma_channel = UART5_TX_DMA_DMA_CHANNEL, \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .dma_irq = UART5_TX_DMA_IRQ, \ + .HsInterface = UART5_TX_DMA_HANDSHAK, \ + .dma_rcc = UART5_TX_DMA_DMA_RCC, \ + .dma_channel = UART5_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART5_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART5_TX_DMA_DMAMUX_REQUEST, \ } @@ -264,13 +264,13 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = USART6, \ - .irq_type = USART6_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_USART6, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = USART6, \ + .irq_type = USART6_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART6, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART6_CONFIG */ #endif /* BSP_USING_UART6 */ @@ -279,11 +279,11 @@ extern "C" { #ifndef UART6_DMA_RX_CONFIG #define UART6_DMA_RX_CONFIG \ { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .dma_irq = UART6_RX_DMA_IRQ, \ - .HsInterface = UART6_RX_DMA_HANDSHAK, \ - .dma_rcc = UART6_RX_DMA_DMA_RCC, \ - .dma_channel = UART6_RX_DMA_DMA_CHANNEL, \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .dma_irq = UART6_RX_DMA_IRQ, \ + .HsInterface = UART6_RX_DMA_HANDSHAK, \ + .dma_rcc = UART6_RX_DMA_DMA_RCC, \ + .dma_channel = UART6_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART6_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART6_RX_DMA_DMAMUX_REQUEST, \ } @@ -297,11 +297,11 @@ extern "C" { #ifndef UART6_DMA_TX_CONFIG #define UART6_DMA_TX_CONFIG \ { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .dma_irq = UART6_TX_DMA_IRQ, \ - .HsInterface = UART6_TX_DMA_HANDSHAK, \ - .dma_rcc = UART6_TX_DMA_DMA_RCC, \ - .dma_channel = UART6_TX_DMA_DMA_CHANNEL, \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .dma_irq = UART6_TX_DMA_IRQ, \ + .HsInterface = UART6_TX_DMA_HANDSHAK, \ + .dma_rcc = UART6_TX_DMA_DMA_RCC, \ + .dma_channel = UART6_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART6_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART6_TX_DMA_DMAMUX_REQUEST, \ } @@ -313,13 +313,13 @@ extern "C" { #if defined(BSP_USING_UART7) #ifndef UART7_CONFIG -#define UART7_CONFIG \ - { \ - .name = "uart7", \ - .Instance = USART7, \ - .irq_type = USART7_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_USART7, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = USART7, \ + .irq_type = USART7_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART7, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART7_CONFIG */ #endif /* BSP_USING_UART7 */ @@ -328,11 +328,11 @@ extern "C" { #ifndef UART7_DMA_RX_CONFIG #define UART7_DMA_RX_CONFIG \ { \ - .Instance = UART7_RX_DMA_INSTANCE, \ - .dma_irq = UART7_RX_DMA_IRQ, \ - .HsInterface = UART7_RX_DMA_HANDSHAK, \ - .dma_rcc = UART7_RX_DMA_DMA_RCC, \ - .dma_channel = UART7_RX_DMA_DMA_CHANNEL, \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .dma_irq = UART7_RX_DMA_IRQ, \ + .HsInterface = UART7_RX_DMA_HANDSHAK, \ + .dma_rcc = UART7_RX_DMA_DMA_RCC, \ + .dma_channel = UART7_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART7_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART7_RX_DMA_DMAMUX_REQUEST, \ } @@ -346,11 +346,11 @@ extern "C" { #ifndef UART7_DMA_TX_CONFIG #define UART7_DMA_TX_CONFIG \ { \ - .Instance = UART7_TX_DMA_INSTANCE, \ - .dma_irq = UART7_TX_DMA_IRQ, \ - .HsInterface = UART7_TX_DMA_HANDSHAK, \ - .dma_rcc = UART7_TX_DMA_DMA_RCC, \ - .dma_channel = UART7_TX_DMA_DMA_CHANNEL, \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .dma_irq = UART7_TX_DMA_IRQ, \ + .HsInterface = UART7_TX_DMA_HANDSHAK, \ + .dma_rcc = UART7_TX_DMA_DMA_RCC, \ + .dma_channel = UART7_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART7_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART7_TX_DMA_DMAMUX_REQUEST, \ } @@ -362,13 +362,13 @@ extern "C" { #if defined(BSP_USING_UART8) #ifndef UART8_CONFIG -#define UART8_CONFIG \ - { \ - .name = "uart8", \ - .Instance = USART8, \ - .irq_type = USART8_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_USART8, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = USART8, \ + .irq_type = USART8_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART8, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART8_CONFIG */ #endif /* BSP_USING_UART8 */ @@ -377,11 +377,11 @@ extern "C" { #ifndef UART8_DMA_RX_CONFIG #define UART8_DMA_RX_CONFIG \ { \ - .Instance = UART8_RX_DMA_INSTANCE, \ - .dma_irq = UART8_RX_DMA_IRQ, \ - .HsInterface = UART8_RX_DMA_HANDSHAK, \ - .dma_rcc = UART8_RX_DMA_DMA_RCC, \ - .dma_channel = UART8_RX_DMA_DMA_CHANNEL, \ + .Instance = UART8_RX_DMA_INSTANCE, \ + .dma_irq = UART8_RX_DMA_IRQ, \ + .HsInterface = UART8_RX_DMA_HANDSHAK, \ + .dma_rcc = UART8_RX_DMA_DMA_RCC, \ + .dma_channel = UART8_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART8_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART8_RX_DMA_DMAMUX_REQUEST, \ } @@ -395,11 +395,11 @@ extern "C" { #ifndef UART8_DMA_TX_CONFIG #define UART8_DMA_TX_CONFIG \ { \ - .Instance = UART8_TX_DMA_INSTANCE, \ - .dma_irq = UART8_TX_DMA_IRQ, \ - .HsInterface = UART8_TX_DMA_HANDSHAK, \ - .dma_rcc = UART8_TX_DMA_DMA_RCC, \ - .dma_channel = UART8_TX_DMA_DMA_CHANNEL, \ + .Instance = UART8_TX_DMA_INSTANCE, \ + .dma_irq = UART8_TX_DMA_IRQ, \ + .HsInterface = UART8_TX_DMA_HANDSHAK, \ + .dma_rcc = UART8_TX_DMA_DMA_RCC, \ + .dma_channel = UART8_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART8_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART8_TX_DMA_DMAMUX_REQUEST, \ } @@ -411,13 +411,13 @@ extern "C" { #if defined(BSP_USING_UART9) #ifndef UART9_CONFIG -#define UART9_CONFIG \ - { \ - .name = "uart9", \ - .Instance = UART9, \ - .irq_type = UART9_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_UART9, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = UART9, \ + .irq_type = UART9_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART9, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART9_CONFIG */ #endif /* BSP_USING_UART9 */ @@ -426,11 +426,11 @@ extern "C" { #ifndef UART9_DMA_RX_CONFIG #define UART9_DMA_RX_CONFIG \ { \ - .Instance = UART9_RX_DMA_INSTANCE, \ - .dma_irq = UART9_RX_DMA_IRQ, \ - .HsInterface = UART9_RX_DMA_HANDSHAK, \ - .dma_rcc = UART9_RX_DMA_DMA_RCC, \ - .dma_channel = UART9_RX_DMA_DMA_CHANNEL, \ + .Instance = UART9_RX_DMA_INSTANCE, \ + .dma_irq = UART9_RX_DMA_IRQ, \ + .HsInterface = UART9_RX_DMA_HANDSHAK, \ + .dma_rcc = UART9_RX_DMA_DMA_RCC, \ + .dma_channel = UART9_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART9_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART9_RX_DMA_DMAMUX_REQUEST, \ } @@ -444,11 +444,11 @@ extern "C" { #ifndef UART9_DMA_TX_CONFIG #define UART9_DMA_TX_CONFIG \ { \ - .Instance = UART9_TX_DMA_INSTANCE, \ - .dma_irq = UART9_TX_DMA_IRQ, \ - .HsInterface = UART9_TX_DMA_HANDSHAK, \ - .dma_rcc = UART9_TX_DMA_DMA_RCC, \ - .dma_channel = UART9_TX_DMA_DMA_CHANNEL, \ + .Instance = UART9_TX_DMA_INSTANCE, \ + .dma_irq = UART9_TX_DMA_IRQ, \ + .HsInterface = UART9_TX_DMA_HANDSHAK, \ + .dma_rcc = UART9_TX_DMA_DMA_RCC, \ + .dma_channel = UART9_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART9_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART9_TX_DMA_DMAMUX_REQUEST, \ } @@ -460,13 +460,13 @@ extern "C" { #if defined(BSP_USING_UART10) #ifndef UART10_CONFIG -#define UART10_CONFIG \ - { \ - .name = "uart10", \ - .Instance = UART10, \ - .irq_type = UART10_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_UART10, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = UART10, \ + .irq_type = UART10_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART10, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART10_CONFIG */ #endif /* BSP_USING_UART10 */ @@ -475,11 +475,11 @@ extern "C" { #ifndef UART10_DMA_RX_CONFIG #define UART10_DMA_RX_CONFIG \ { \ - .Instance = UART10_RX_DMA_INSTANCE, \ - .dma_irq = UART10_RX_DMA_IRQ, \ - .HsInterface = UART10_RX_DMA_HANDSHAK, \ - .dma_rcc = UART10_RX_DMA_DMA_RCC, \ - .dma_channel = UART10_RX_DMA_DMA_CHANNEL, \ + .Instance = UART10_RX_DMA_INSTANCE, \ + .dma_irq = UART10_RX_DMA_IRQ, \ + .HsInterface = UART10_RX_DMA_HANDSHAK, \ + .dma_rcc = UART10_RX_DMA_DMA_RCC, \ + .dma_channel = UART10_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART10_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART10_RX_DMA_DMAMUX_REQUEST, \ } @@ -493,11 +493,11 @@ extern "C" { #ifndef UART10_DMA_TX_CONFIG #define UART10_DMA_TX_CONFIG \ { \ - .Instance = UART10_TX_DMA_INSTANCE, \ - .dma_irq = UART10_TX_DMA_IRQ, \ - .HsInterface = UART10_TX_DMA_HANDSHAK, \ - .dma_rcc = UART10_TX_DMA_DMA_RCC, \ - .dma_channel = UART10_TX_DMA_DMA_CHANNEL, \ + .Instance = UART10_TX_DMA_INSTANCE, \ + .dma_irq = UART10_TX_DMA_IRQ, \ + .HsInterface = UART10_TX_DMA_HANDSHAK, \ + .dma_rcc = UART10_TX_DMA_DMA_RCC, \ + .dma_channel = UART10_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART10_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART10_TX_DMA_DMAMUX_REQUEST, \ } @@ -509,13 +509,13 @@ extern "C" { #if defined(BSP_USING_UART11) #ifndef UART11_CONFIG -#define UART11_CONFIG \ - { \ - .name = "uart11", \ - .Instance = UART11, \ - .irq_type = UART11_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_UART11, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART11_CONFIG \ + { \ + .name = "uart11", \ + .Instance = UART11, \ + .irq_type = UART11_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART11, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART11_CONFIG */ #endif /* BSP_USING_UART11 */ @@ -524,11 +524,11 @@ extern "C" { #ifndef UART11_DMA_RX_CONFIG #define UART11_DMA_RX_CONFIG \ { \ - .Instance = UART11_RX_DMA_INSTANCE, \ - .dma_irq = UART11_RX_DMA_IRQ, \ - .HsInterface = UART11_RX_DMA_HANDSHAK, \ - .dma_rcc = UART11_RX_DMA_DMA_RCC, \ - .dma_channel = UART11_RX_DMA_DMA_CHANNEL, \ + .Instance = UART11_RX_DMA_INSTANCE, \ + .dma_irq = UART11_RX_DMA_IRQ, \ + .HsInterface = UART11_RX_DMA_HANDSHAK, \ + .dma_rcc = UART11_RX_DMA_DMA_RCC, \ + .dma_channel = UART11_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART11_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART11_RX_DMA_DMAMUX_REQUEST, \ } @@ -542,11 +542,11 @@ extern "C" { #ifndef UART11_DMA_TX_CONFIG #define UART11_DMA_TX_CONFIG \ { \ - .Instance = UART11_TX_DMA_INSTANCE, \ - .dma_irq = UART11_TX_DMA_IRQ, \ - .HsInterface = UART11_TX_DMA_HANDSHAK, \ - .dma_rcc = UART11_TX_DMA_DMA_RCC, \ - .dma_channel = UART11_TX_DMA_DMA_CHANNEL, \ + .Instance = UART11_TX_DMA_INSTANCE, \ + .dma_irq = UART11_TX_DMA_IRQ, \ + .HsInterface = UART11_TX_DMA_HANDSHAK, \ + .dma_rcc = UART11_TX_DMA_DMA_RCC, \ + .dma_channel = UART11_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART11_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART11_TX_DMA_DMAMUX_REQUEST, \ } @@ -558,13 +558,13 @@ extern "C" { #if defined(BSP_USING_UART12) #ifndef UART12_CONFIG -#define UART12_CONFIG \ - { \ - .name = "uart12", \ - .Instance = UART12, \ - .irq_type = UART12_IRQn, \ - .periph = RCC_APB1_PERIPHEN_M7_UART12, \ - .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ +#define UART12_CONFIG \ + { \ + .name = "uart12", \ + .Instance = UART12, \ + .irq_type = UART12_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART12, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ } #endif /* UART12_CONFIG */ #endif /* BSP_USING_UART12 */ @@ -573,11 +573,11 @@ extern "C" { #ifndef UART12_DMA_RX_CONFIG #define UART12_DMA_RX_CONFIG \ { \ - .Instance = UART12_RX_DMA_INSTANCE, \ - .dma_irq = UART12_RX_DMA_IRQ, \ - .HsInterface = UART12_RX_DMA_HANDSHAK, \ - .dma_rcc = UART12_RX_DMA_DMA_RCC, \ - .dma_channel = UART12_RX_DMA_DMA_CHANNEL, \ + .Instance = UART12_RX_DMA_INSTANCE, \ + .dma_irq = UART12_RX_DMA_IRQ, \ + .HsInterface = UART12_RX_DMA_HANDSHAK, \ + .dma_rcc = UART12_RX_DMA_DMA_RCC, \ + .dma_channel = UART12_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART12_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART12_RX_DMA_DMAMUX_REQUEST, \ } @@ -591,11 +591,11 @@ extern "C" { #ifndef UART12_DMA_TX_CONFIG #define UART12_DMA_TX_CONFIG \ { \ - .Instance = UART12_TX_DMA_INSTANCE, \ - .dma_irq = UART12_TX_DMA_IRQ, \ - .HsInterface = UART12_TX_DMA_HANDSHAK, \ - .dma_rcc = UART12_TX_DMA_DMA_RCC, \ - .dma_channel = UART12_TX_DMA_DMA_CHANNEL, \ + .Instance = UART12_TX_DMA_INSTANCE, \ + .dma_irq = UART12_TX_DMA_IRQ, \ + .HsInterface = UART12_TX_DMA_HANDSHAK, \ + .dma_rcc = UART12_TX_DMA_DMA_RCC, \ + .dma_channel = UART12_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART12_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART12_TX_DMA_DMAMUX_REQUEST, \ } @@ -607,13 +607,13 @@ extern "C" { #if defined(BSP_USING_UART13) #ifndef UART13_CONFIG -#define UART13_CONFIG \ - { \ - .name = "uart13", \ - .Instance = UART13, \ - .irq_type = UART13_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_UART13, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART13_CONFIG \ + { \ + .name = "uart13", \ + .Instance = UART13, \ + .irq_type = UART13_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART13, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART13_CONFIG */ #endif /* BSP_USING_UART13 */ @@ -622,11 +622,11 @@ extern "C" { #ifndef UART13_DMA_RX_CONFIG #define UART13_DMA_RX_CONFIG \ { \ - .Instance = UART13_RX_DMA_INSTANCE, \ - .dma_irq = UART13_RX_DMA_IRQ, \ - .HsInterface = UART13_RX_DMA_HANDSHAK, \ - .dma_rcc = UART13_RX_DMA_DMA_RCC, \ - .dma_channel = UART13_RX_DMA_DMA_CHANNEL, \ + .Instance = UART13_RX_DMA_INSTANCE, \ + .dma_irq = UART13_RX_DMA_IRQ, \ + .HsInterface = UART13_RX_DMA_HANDSHAK, \ + .dma_rcc = UART13_RX_DMA_DMA_RCC, \ + .dma_channel = UART13_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART13_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART13_RX_DMA_DMAMUX_REQUEST, \ } @@ -640,11 +640,11 @@ extern "C" { #ifndef UART13_DMA_TX_CONFIG #define UART13_DMA_TX_CONFIG \ { \ - .Instance = UART13_TX_DMA_INSTANCE, \ - .dma_irq = UART13_TX_DMA_IRQ, \ - .HsInterface = UART13_TX_DMA_HANDSHAK, \ - .dma_rcc = UART13_TX_DMA_DMA_RCC, \ - .dma_channel = UART13_TX_DMA_DMA_CHANNEL, \ + .Instance = UART13_TX_DMA_INSTANCE, \ + .dma_irq = UART13_TX_DMA_IRQ, \ + .HsInterface = UART13_TX_DMA_HANDSHAK, \ + .dma_rcc = UART13_TX_DMA_DMA_RCC, \ + .dma_channel = UART13_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART13_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART13_TX_DMA_DMAMUX_REQUEST, \ } @@ -656,13 +656,13 @@ extern "C" { #if defined(BSP_USING_UART14) #ifndef UART14_CONFIG -#define UART14_CONFIG \ - { \ - .name = "uart14", \ - .Instance = UART14, \ - .irq_type = UART14_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_UART14, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART14_CONFIG \ + { \ + .name = "uart14", \ + .Instance = UART14, \ + .irq_type = UART14_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART14, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART14_CONFIG */ #endif /* BSP_USING_UART14 */ @@ -671,11 +671,11 @@ extern "C" { #ifndef UART14_DMA_RX_CONFIG #define UART14_DMA_RX_CONFIG \ { \ - .Instance = UART14_RX_DMA_INSTANCE, \ - .dma_irq = UART14_RX_DMA_IRQ, \ - .HsInterface = UART14_RX_DMA_HANDSHAK, \ - .dma_rcc = UART14_RX_DMA_DMA_RCC, \ - .dma_channel = UART14_RX_DMA_DMA_CHANNEL, \ + .Instance = UART14_RX_DMA_INSTANCE, \ + .dma_irq = UART14_RX_DMA_IRQ, \ + .HsInterface = UART14_RX_DMA_HANDSHAK, \ + .dma_rcc = UART14_RX_DMA_DMA_RCC, \ + .dma_channel = UART14_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART14_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART14_RX_DMA_DMAMUX_REQUEST, \ } @@ -689,11 +689,11 @@ extern "C" { #ifndef UART14_DMA_TX_CONFIG #define UART14_DMA_TX_CONFIG \ { \ - .Instance = UART14_TX_DMA_INSTANCE, \ - .dma_irq = UART14_TX_DMA_IRQ, \ - .HsInterface = UART14_TX_DMA_HANDSHAK, \ - .dma_rcc = UART14_TX_DMA_DMA_RCC, \ - .dma_channel = UART14_TX_DMA_DMA_CHANNEL, \ + .Instance = UART14_TX_DMA_INSTANCE, \ + .dma_irq = UART14_TX_DMA_IRQ, \ + .HsInterface = UART14_TX_DMA_HANDSHAK, \ + .dma_rcc = UART14_TX_DMA_DMA_RCC, \ + .dma_channel = UART14_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART14_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART14_TX_DMA_DMAMUX_REQUEST, \ } @@ -705,13 +705,13 @@ extern "C" { #if defined(BSP_USING_UART15) #ifndef UART15_CONFIG -#define UART15_CONFIG \ - { \ - .name = "uart15", \ - .Instance = UART15, \ - .irq_type = UART15_IRQn, \ - .periph = RCC_APB2_PERIPHEN_M7_UART15, \ - .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ +#define UART15_CONFIG \ + { \ + .name = "uart15", \ + .Instance = UART15, \ + .irq_type = UART15_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART15, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ } #endif /* UART15_CONFIG */ #endif /* BSP_USING_UART15 */ @@ -720,11 +720,11 @@ extern "C" { #ifndef UART15_DMA_RX_CONFIG #define UART15_DMA_RX_CONFIG \ { \ - .Instance = UART15_RX_DMA_INSTANCE, \ - .dma_irq = UART15_RX_DMA_IRQ, \ - .HsInterface = UART15_RX_DMA_HANDSHAK, \ - .dma_rcc = UART15_RX_DMA_DMA_RCC, \ - .dma_channel = UART15_RX_DMA_DMA_CHANNEL, \ + .Instance = UART15_RX_DMA_INSTANCE, \ + .dma_irq = UART15_RX_DMA_IRQ, \ + .HsInterface = UART15_RX_DMA_HANDSHAK, \ + .dma_rcc = UART15_RX_DMA_DMA_RCC, \ + .dma_channel = UART15_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART15_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART15_RX_DMA_DMAMUX_REQUEST, \ } @@ -738,11 +738,11 @@ extern "C" { #ifndef UART15_DMA_TX_CONFIG #define UART15_DMA_TX_CONFIG \ { \ - .Instance = UART15_TX_DMA_INSTANCE, \ - .dma_irq = UART15_TX_DMA_IRQ, \ - .HsInterface = UART15_TX_DMA_HANDSHAK, \ - .dma_rcc = UART15_TX_DMA_DMA_RCC, \ - .dma_channel = UART15_TX_DMA_DMA_CHANNEL, \ + .Instance = UART15_TX_DMA_INSTANCE, \ + .dma_irq = UART15_TX_DMA_IRQ, \ + .HsInterface = UART15_TX_DMA_HANDSHAK, \ + .dma_rcc = UART15_TX_DMA_DMA_RCC, \ + .dma_channel = UART15_TX_DMA_DMA_CHANNEL, \ .dmamux_channel = UART15_TX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = UART15_TX_DMA_DMAMUX_REQUEST, \ } @@ -754,13 +754,13 @@ extern "C" { #if defined(BSP_USING_LPUART1) #ifndef LPUART1_CONFIG -#define LPUART1_CONFIG \ - { \ - .name = "lpuart1", \ - .Instance = LPUART1, \ - .irq_type = LPUART1_IRQn, \ - .periph = RCC_RD_PERIPHEN_M7_LPUART1, \ - .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ +#define LPUART1_CONFIG \ + { \ + .name = "lpuart1", \ + .Instance = LPUART1, \ + .irq_type = LPUART1_IRQn, \ + .periph = RCC_RD_PERIPHEN_M7_LPUART1, \ + .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ } #endif /* LPUART1_CONFIG */ #endif /* BSP_USING_LPUART1 */ @@ -768,11 +768,11 @@ extern "C" { #ifndef LPUART1_DMA_RX_CONFIG #define LPUART1_DMA_RX_CONFIG \ { \ - .Instance = LPUART1_RX_DMA_INSTANCE, \ - .dma_irq = LPUART1_RX_DMA_IRQ, \ - .HsInterface = LPUART1_RX_DMA_HANDSHAK, \ - .dma_rcc = LPUART1_RX_DMA_DMA_RCC, \ - .dma_channel = LPUART1_RX_DMA_DMA_CHANNEL, \ + .Instance = LPUART1_RX_DMA_INSTANCE, \ + .dma_irq = LPUART1_RX_DMA_IRQ, \ + .HsInterface = LPUART1_RX_DMA_HANDSHAK, \ + .dma_rcc = LPUART1_RX_DMA_DMA_RCC, \ + .dma_channel = LPUART1_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = LPUART1_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = LPUART1_RX_DMA_DMAMUX_REQUEST, \ } @@ -781,13 +781,13 @@ extern "C" { #if defined(BSP_USING_LPUART2) #ifndef LPUART2_CONFIG -#define LPUART2_CONFIG \ - { \ - .name = "lpuart2", \ - .Instance = LPUART2, \ - .irq_type = LPUART2_IRQn, \ - .periph = RCC_RD_PERIPHEN_M7_LPUART2, \ - .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ +#define LPUART2_CONFIG \ + { \ + .name = "lpuart2", \ + .Instance = LPUART2, \ + .irq_type = LPUART2_IRQn, \ + .periph = RCC_RD_PERIPHEN_M7_LPUART2, \ + .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ } #endif /* LPUART2_CONFIG */ #endif /* BSP_USING_LPUART2 */ @@ -795,11 +795,11 @@ extern "C" { #ifndef LPUART2_DMA_RX_CONFIG #define LPUART2_DMA_RX_CONFIG \ { \ - .Instance = LPUART2_RX_DMA_INSTANCE, \ - .dma_irq = LPUART2_RX_DMA_IRQ, \ - .HsInterface = LPUART2_RX_DMA_HANDSHAK, \ - .dma_rcc = LPUART2_RX_DMA_DMA_RCC, \ - .dma_channel = LPUART2_RX_DMA_DMA_CHANNEL, \ + .Instance = LPUART2_RX_DMA_INSTANCE, \ + .dma_irq = LPUART2_RX_DMA_IRQ, \ + .HsInterface = LPUART2_RX_DMA_HANDSHAK, \ + .dma_rcc = LPUART2_RX_DMA_DMA_RCC, \ + .dma_channel = LPUART2_RX_DMA_DMA_CHANNEL, \ .dmamux_channel = LPUART2_RX_DMA_DMAMUX_CHANNEL, \ .dmamux_request = LPUART2_RX_DMA_DMAMUX_REQUEST, \ } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c index cd04672c07..6e31a8dc82 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c @@ -15,7 +15,7 @@ #include "drv_config.h" //#define DRV_DEBUG -#define LOG_TAG "drv.adc" +#define LOG_TAG "drv.adc" #include <drv_log.h> @@ -35,8 +35,7 @@ typedef struct ADC_InitType Init; } ADC_InitInfo_t; -static ADC_InitInfo_t adc_config[] = -{ +static ADC_InitInfo_t adc_config[] = { #ifdef BSP_USING_ADC1 ADC1_CONFIG, #endif @@ -65,34 +64,34 @@ static rt_err_t n32_adc_get_channel(rt_int8_t rt_channel, uint32_t *n32_channel) { switch (rt_channel) { - case 0: + case 0: *n32_channel = ADC_CH_0; break; - case 1: + case 1: *n32_channel = ADC_CH_1; break; - case 2: + case 2: *n32_channel = ADC_CH_2; break; - case 3: + case 3: *n32_channel = ADC_CH_3; break; - case 4: + case 4: *n32_channel = ADC_CH_4; break; - case 5: + case 5: *n32_channel = ADC_CH_5; break; - case 6: + case 6: *n32_channel = ADC_CH_6; break; - case 7: + case 7: *n32_channel = ADC_CH_7; break; - case 8: + case 8: *n32_channel = ADC_CH_8; break; - case 9: + case 9: *n32_channel = ADC_CH_9; break; case 10: @@ -262,7 +261,7 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, static rt_err_t n32_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { - uint16_t Convert_Value; + uint16_t Convert_Value = 0; ADC_InitInfo_t *n32_adc_info; RT_ASSERT(device != RT_NULL); @@ -284,7 +283,9 @@ static rt_err_t n32_adc_get_value(struct rt_adc_device *device, rt_int8_t channe Convert_Value = ADC_GetDat(n32_adc_info->ADCx); if (channel == RT_ADC_INTERN_CH_VBAT) + { Convert_Value *= 4U; + } #endif *value = Convert_Value; @@ -323,14 +324,13 @@ static rt_uint8_t n32_adc_get_resolution(struct rt_adc_device *device) } -static rt_int16_t n32_adc_get_vref (struct rt_adc_device *device) +static rt_int16_t n32_adc_get_vref(struct rt_adc_device *device) { return 3300; } -static const struct rt_adc_ops n32_adc_ops = -{ +static const struct rt_adc_ops n32_adc_ops = { .enabled = n32_adc_enabled, .convert = n32_adc_get_value, .get_resolution = n32_adc_get_resolution, @@ -342,7 +342,7 @@ static int n32_adc_init(void) { int result = RT_EOK; /* save adc name */ - char name_buf[5] = {'a', 'd', 'c', '0', 0}; + char name_buf[5] = { 'a', 'd', 'c', '0', 0 }; int i = 0; for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++) diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h index 8bd9acdbc9..42e6334d2c 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h @@ -34,9 +34,11 @@ extern "C" { #elif defined(SOC_SERIES_N32H49x) #include "h49x/dma_config.h" #include "h49x/uart_config.h" +#include "h49x/can_config.h" #elif defined(SOC_SERIES_N32H47x_48x) #include "h47x_48x/dma_config.h" #include "h47x_48x/uart_config.h" +#include "h47x_48x/can_config.h" #endif /* defined(SOC_SERIES_N32H7xx) */ #ifdef __cplusplus diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h index 1f69f62a0b..bfcfddd364 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h @@ -34,12 +34,12 @@ struct dma_config #elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) struct dma_config { - DMA_Module *DMAy; + DMA_Module *DMAy; DMA_ChannelType *DMAChx; - IRQn_Type dma_irq; - rt_uint32_t dma_rcc; - rt_uint32_t request; - rt_uint32_t channel; + IRQn_Type dma_irq; + rt_uint32_t dma_rcc; + rt_uint32_t request; + rt_uint32_t channel; }; #endif diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c index 6f787a2497..45c42ce1fc 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2026-06-22 ox-horse first version - N32H7xx FDCAN driver + * 2026-08-05 ox-horse add N32H47x/48x support + * 2026-08-06 ox-horse add N32H49x support */ #include "drv_fdcan.h" @@ -21,30 +23,31 @@ #define LOG_TAG "drv.fdcan" #include <drv_log.h> -/* FDCAN kernel clock: 40MHz (APB1/APB2 peripheral clock) */ -#define FDCAN_KERNEL_CLK (40000000U) +#define FDCAN_IS_VALID_DATA_BYTES(value) \ + (((value) == 8) || ((value) == 12) || \ + ((value) == 16) || ((value) == 20) || \ + ((value) == 24) || ((value) == 32) || \ + ((value) == 48) || ((value) == 64)) -/* FDCAN Message RAM base addresses */ -#define FDCAN_MSG_RAM_BASE1 ((uint32_t)0x30050000U) /* SRAM5 BANK1: FDCAN1~4 */ -#define FDCAN_MSG_RAM_BASE2 ((uint32_t)0x30054000U) /* SRAM5 BANK2: FDCAN5~8 */ - -/* Message RAM offset per FDCAN instance within a bank (in words) */ +/* FDCAN Message RAM configuration */ +#if defined(SOC_SERIES_N32H7xx) +#define FDCAN_MSG_RAM_BASE1 ((uint32_t)0x30050000U) /* SRAM5 BANK1: FDCAN1~4 */ +#define FDCAN_MSG_RAM_BASE2 ((uint32_t)0x30054000U) /* SRAM5 BANK2: FDCAN5~8 */ #define FDCAN_MSG_RAM_OFFSET_PER_INSTANCE ((uint32_t)0x400U) +#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) +/* FDCAN1/2/3 share one configurable continuous Message RAM array. */ +#ifndef BSP_FDCAN_MSG_RAM_WORDS +#define BSP_FDCAN_MSG_RAM_WORDS (768U) +#endif +#if (BSP_FDCAN_MSG_RAM_WORDS < 1) || (BSP_FDCAN_MSG_RAM_WORDS > 4480) +#error "BSP_FDCAN_MSG_RAM_WORDS must be between 1 and 4480" +#endif +static uint32_t _fdcan_msg_ram[BSP_FDCAN_MSG_RAM_WORDS]; +#else +#error "Unsupported N32 FDCAN series" +#endif -/* Number of dedicated TX Buffers for blocking send */ -#define FDCAN_TX_BUF_NUM (3U) - -/* Number of RX FIFO0 elements */ -#define FDCAN_RX_FIFO0_SIZE (8U) - -/* Default RX FIFO0 watermark (50%) */ -#define FDCAN_RX_FIFO0_WATERMARK (4U) - -/*============================================================================== - * Baud rate configuration tables (40MHz FDCAN kernel clock) - * Matching STM32 H7 FDCAN timing values. - * Formula: BaudRate = FDCAN_KERNEL_CLK / (Prescaler * (Tseg1 + Tseg2 + 1)) - *============================================================================*/ +/* BaudRate = kernel clock / (Prescaler * (Tseg1 + Tseg2 + 1)). */ /** *\*\name _fdcan_arb_timing_table. @@ -72,61 +75,172 @@ static const struct n32_fdcan_data_timing _fdcan_data_timing_table[] = { { CAN1MBaud * 8, 1, 1, 3, 1 }, /* 8Mbps : 40M / (1 * (3+1+1)) = 8M */ { CAN1MBaud * 5, 1, 2, 5, 2 }, /* 5Mbps : 40M / (1 * (5+2+1)) = 5M */ { CAN1MBaud * 4, 1, 2, 7, 2 }, /* 4Mbps : 40M / (1 * (7+2+1)) = 4M */ - { CAN1MBaud * 2, 1, 4, 15, 4 }, /* 2Mbps : 40M / (4 * (3+1+1)) = 2M */ + { CAN1MBaud * 2, 1, 4, 15, 4 }, /* 2Mbps : 40M / (1 * (15+4+1)) = 2M */ { CAN1MBaud, 1, 8, 31, 8 }, /* 1Mbps : 40M / (1 * (31+8+1)) = 1M */ { CAN800kBaud, 2, 5, 19, 5 }, /* 800kbps : 40M / (2 * (19+5+1)) = 800k */ - { CAN500kBaud, 4, 4, 15, 4 }, /* 400kbps : 40M / (4 * (15+4+1)) = 500k */ + { CAN500kBaud, 4, 4, 15, 4 }, /* 500kbps : 40M / (4 * (15+4+1)) = 500k */ +}; + +struct n32_fdcan_resource_config +{ + uint32_t std_filter_size; + uint32_t ext_filter_size; + uint32_t rx_fifo0_size; + uint32_t rx_fifo0_data_bytes; + uint32_t rx_fifo1_size; + uint32_t rx_fifo1_data_bytes; + uint32_t rx_buffer_size; + uint32_t rx_buffer_data_bytes; + uint32_t tx_event_size; + uint32_t tx_buffer_size; + uint32_t tx_buffer_data_bytes; + uint32_t tx_fifo_queue_size; + uint32_t tx_fifo_queue_mode; + uint32_t tdc_offset; + uint32_t tdc_filter; + rt_bool_t tdc_enabled; }; +static void _fdcan_get_resource_config(FDCAN_Module *FDCANx, + const struct n32_fdcan_config *config, + struct n32_fdcan_resource_config *resource) +{ + RT_ASSERT(config != RT_NULL); + RT_ASSERT(config->Instance == FDCANx); + + resource->std_filter_size = config->std_filter_size; + resource->ext_filter_size = config->ext_filter_size; + resource->rx_fifo0_size = config->rx_fifo0_size; + resource->rx_fifo0_data_bytes = config->rx_fifo0_data_bytes; + resource->rx_fifo1_size = config->rx_fifo1_size; + resource->rx_fifo1_data_bytes = config->rx_fifo1_data_bytes; + resource->rx_buffer_size = config->rx_buffer_size; + resource->rx_buffer_data_bytes = config->rx_buffer_data_bytes; + resource->tx_event_size = config->tx_event_size; + resource->tx_buffer_size = config->tx_buffer_size; + resource->tx_buffer_data_bytes = config->tx_buffer_data_bytes; + resource->tx_fifo_queue_size = config->tx_fifo_queue_size; + resource->tx_fifo_queue_mode = config->tx_fifo_queue_mode; + resource->tdc_offset = config->tdc_offset; + resource->tdc_filter = config->tdc_filter; + resource->tdc_enabled = config->tdc_enabled; +} + +static uint32_t _fdcan_data_size_from_bytes(uint32_t bytes) +{ + switch (bytes) + { + case 8: + return FDCAN_DATA_BYTES_8; + case 12: + return FDCAN_DATA_BYTES_12; + case 16: + return FDCAN_DATA_BYTES_16; + case 20: + return FDCAN_DATA_BYTES_20; + case 24: + return FDCAN_DATA_BYTES_24; + case 32: + return FDCAN_DATA_BYTES_32; + case 48: + return FDCAN_DATA_BYTES_48; + case 64: + return FDCAN_DATA_BYTES_64; + default: + return 0; + } +} + +static rt_err_t _fdcan_validate_resource_config( + const struct n32_fdcan_resource_config *resource) +{ + if (resource->std_filter_size > 128 || resource->ext_filter_size > 64 || + resource->rx_fifo0_size < 1 || resource->rx_fifo0_size > 64 || + resource->rx_fifo1_size > 64 || resource->rx_buffer_size > 64 || + resource->tx_event_size > 32 || resource->tx_buffer_size < 1 || + resource->tx_buffer_size > 32 || resource->tx_fifo_queue_size > 31 || + resource->tx_buffer_size + resource->tx_fifo_queue_size > 32 || + resource->tdc_offset > 127 || resource->tdc_filter > 127 || + !FDCAN_IS_VALID_DATA_BYTES(resource->rx_fifo0_data_bytes) || + !FDCAN_IS_VALID_DATA_BYTES(resource->rx_fifo1_data_bytes) || + !FDCAN_IS_VALID_DATA_BYTES(resource->rx_buffer_data_bytes) || + !FDCAN_IS_VALID_DATA_BYTES(resource->tx_buffer_data_bytes)) + { + return -RT_EINVAL; + } + return RT_EOK; +} + +static uint32_t _fdcan_get_tx_buffer_mask(uint32_t count) +{ + return (count >= 32U) ? 0xFFFFFFFFU : ((1UL << count) - 1UL); +} + /*============================================================================== * FDCAN instance objects *============================================================================*/ #ifdef BSP_USING_FDCAN1 +static const struct n32_fdcan_config _fdcan1_config = FDCAN1_CONFIG; static struct n32_fdcan _drv_fdcan1 = { .name = "fdcan1", + .config = &_fdcan1_config, }; #endif #ifdef BSP_USING_FDCAN2 +static const struct n32_fdcan_config _fdcan2_config = FDCAN2_CONFIG; static struct n32_fdcan _drv_fdcan2 = { .name = "fdcan2", + .config = &_fdcan2_config, }; #endif #ifdef BSP_USING_FDCAN3 +static const struct n32_fdcan_config _fdcan3_config = FDCAN3_CONFIG; static struct n32_fdcan _drv_fdcan3 = { .name = "fdcan3", + .config = &_fdcan3_config, }; #endif -#ifdef BSP_USING_FDCAN4 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN4) +static const struct n32_fdcan_config _fdcan4_config = FDCAN4_CONFIG; static struct n32_fdcan _drv_fdcan4 = { .name = "fdcan4", + .config = &_fdcan4_config, }; #endif -#ifdef BSP_USING_FDCAN5 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN5) +static const struct n32_fdcan_config _fdcan5_config = FDCAN5_CONFIG; static struct n32_fdcan _drv_fdcan5 = { .name = "fdcan5", + .config = &_fdcan5_config, }; #endif -#ifdef BSP_USING_FDCAN6 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN6) +static const struct n32_fdcan_config _fdcan6_config = FDCAN6_CONFIG; static struct n32_fdcan _drv_fdcan6 = { .name = "fdcan6", + .config = &_fdcan6_config, }; #endif -#ifdef BSP_USING_FDCAN7 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN7) +static const struct n32_fdcan_config _fdcan7_config = FDCAN7_CONFIG; static struct n32_fdcan _drv_fdcan7 = { .name = "fdcan7", + .config = &_fdcan7_config, }; #endif -#ifdef BSP_USING_FDCAN8 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN8) +static const struct n32_fdcan_config _fdcan8_config = FDCAN8_CONFIG; static struct n32_fdcan _drv_fdcan8 = { .name = "fdcan8", + .config = &_fdcan8_config, }; #endif @@ -266,6 +380,7 @@ static uint32_t _get_data_baud_index(uint32_t baud_rate) * Instance index calculation *============================================================================*/ +#if defined(SOC_SERIES_N32H7xx) /** *\*\name _fdcan_get_index. *\*\fun Get the index of the specified FDCAN instance. @@ -312,6 +427,71 @@ static uint8_t _fdcan_get_index(FDCAN_Module *FDCANx) } return 7; /* FDCAN8 */ } +#endif + +static uint32_t _fdcan_get_required_ram_words(const FDCAN_InitType *init) +{ + return init->StdFilterSize + + init->ExtFilterSize * FDCAN_EXT_FILTER_WORDS + + init->RxFifo0Size * init->RxFifo0DataSize + + init->RxFifo1Size * init->RxFifo1DataSize + + init->RxBufferSize * init->RxBufferDataSize + + init->TxEventSize * FDCAN_TX_EVENT_FIFO_WORDS + + (init->TxBufferSize + init->TxFifoQueueSize) * init->TxBufferDataSize; +} + +#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) +static uint32_t _fdcan_get_resource_ram_words( + const struct n32_fdcan_resource_config *resource) +{ + return resource->std_filter_size + + resource->ext_filter_size * FDCAN_EXT_FILTER_WORDS + + resource->rx_fifo0_size * _fdcan_data_size_from_bytes(resource->rx_fifo0_data_bytes) + + resource->rx_fifo1_size * _fdcan_data_size_from_bytes(resource->rx_fifo1_data_bytes) + + resource->rx_buffer_size * _fdcan_data_size_from_bytes(resource->rx_buffer_data_bytes) + + resource->tx_event_size * FDCAN_TX_EVENT_FIFO_WORDS + + (resource->tx_buffer_size + resource->tx_fifo_queue_size) * + _fdcan_data_size_from_bytes(resource->tx_buffer_data_bytes); +} + +static uint32_t _fdcan_get_msg_ram_offset(FDCAN_Module *FDCANx) +{ + struct n32_fdcan_resource_config resource; + uint32_t offset = 0; + +#ifdef BSP_USING_FDCAN1 + if (FDCANx == FDCAN1) + { + return offset; + } + _fdcan_get_resource_config(FDCAN1, _drv_fdcan1.config, &resource); + if (_fdcan_validate_resource_config(&resource) != RT_EOK) + { + return 0xFFFFFFFFU; + } + offset += _fdcan_get_resource_ram_words(&resource); +#endif +#ifdef BSP_USING_FDCAN2 + if (FDCANx == FDCAN2) + { + return offset; + } + _fdcan_get_resource_config(FDCAN2, _drv_fdcan2.config, &resource); + if (_fdcan_validate_resource_config(&resource) != RT_EOK) + { + return 0xFFFFFFFFU; + } + offset += _fdcan_get_resource_ram_words(&resource); +#endif +#ifdef BSP_USING_FDCAN3 + if (FDCANx == FDCAN3) + { + return offset; + } +#endif + return 0xFFFFFFFFU; +} +#endif /** *\*\name _fdcan_get_int0_irqn. @@ -334,6 +514,7 @@ static IRQn_Type _fdcan_get_int0_irqn(FDCAN_Module *FDCANx) { return FDCAN3_INT0_IRQn; } +#if defined(SOC_SERIES_N32H7xx) if (FDCANx == FDCAN4) { return FDCAN4_INT0_IRQn; @@ -351,6 +532,9 @@ static IRQn_Type _fdcan_get_int0_irqn(FDCAN_Module *FDCANx) return FDCAN7_INT0_IRQn; } return FDCAN8_INT0_IRQn; +#else + return FDCAN1_INT0_IRQn; +#endif } /** @@ -374,6 +558,7 @@ static IRQn_Type _fdcan_get_int1_irqn(FDCAN_Module *FDCANx) { return FDCAN3_INT1_IRQn; } +#if defined(SOC_SERIES_N32H7xx) if (FDCANx == FDCAN4) { return FDCAN4_INT1_IRQn; @@ -391,6 +576,9 @@ static IRQn_Type _fdcan_get_int1_irqn(FDCAN_Module *FDCANx) return FDCAN7_INT1_IRQn; } return FDCAN8_INT1_IRQn; +#else + return FDCAN1_INT1_IRQn; +#endif } /*============================================================================== @@ -409,6 +597,7 @@ static IRQn_Type _fdcan_get_int1_irqn(FDCAN_Module *FDCANx) static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure *cfg) { struct n32_fdcan *p_drv; + struct n32_fdcan_resource_config resource; ErrorStatus status; RT_ASSERT(can != RT_NULL); @@ -417,8 +606,19 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure p_drv = (struct n32_fdcan *)can->parent.user_data; RT_ASSERT(p_drv != RT_NULL); + _fdcan_get_resource_config(p_drv->fdcan_x, p_drv->config, &resource); + if (_fdcan_validate_resource_config(&resource) != RT_EOK) + { + LOG_E("%s: invalid Message RAM resource configuration", p_drv->name); + return -RT_EINVAL; + } + /* Fill FDCAN init parameters */ - p_drv->init_struct.FrameFormat = FDCAN_FRAME_FD_BRS; +#ifdef RT_CAN_USING_CANFD + p_drv->init_struct.FrameFormat = cfg->enable_canfd ? FDCAN_FRAME_FD_BRS : FDCAN_FRAME_CLASSIC; +#else + p_drv->init_struct.FrameFormat = FDCAN_FRAME_CLASSIC; +#endif p_drv->init_struct.Mode = FDCAN_MODE_NORMAL; p_drv->init_struct.AutoRetransmission = ENABLE; p_drv->init_struct.TransmitPause = DISABLE; @@ -483,47 +683,82 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure } #endif - /* Configure Message RAM: FDCAN1~4 use BANK1, FDCAN5~8 use BANK2 */ - uint32_t instance_idx = _fdcan_get_index(p_drv->fdcan_x); - if (instance_idx < 4) - { - p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE1; - p_drv->init_struct.MsgRamOffset = instance_idx * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; - } - else - { - p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE2; - p_drv->init_struct.MsgRamOffset = (instance_idx - 4) * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; - } - /* Filter configuration */ - p_drv->init_struct.StdFilterSize = 2; /* 2 standard ID filters */ - p_drv->init_struct.ExtFilterSize = 2; /* 2 extended ID filters */ + p_drv->init_struct.StdFilterSize = resource.std_filter_size; + p_drv->init_struct.ExtFilterSize = resource.ext_filter_size; /* RX FIFO0 configuration */ - p_drv->init_struct.RxFifo0Size = FDCAN_RX_FIFO0_SIZE; - p_drv->init_struct.RxFifo0DataSize = FDCAN_DATA_BYTES_64; + p_drv->init_struct.RxFifo0Size = resource.rx_fifo0_size; + p_drv->init_struct.RxFifo0DataSize = _fdcan_data_size_from_bytes(resource.rx_fifo0_data_bytes); - /* RX FIFO1 configuration (not used) */ - p_drv->init_struct.RxFifo1Size = 0; - p_drv->init_struct.RxFifo1DataSize = FDCAN_DATA_BYTES_64; + /* RX FIFO1 configuration */ + p_drv->init_struct.RxFifo1Size = resource.rx_fifo1_size; + p_drv->init_struct.RxFifo1DataSize = _fdcan_data_size_from_bytes(resource.rx_fifo1_data_bytes); - /* RX Buffer configuration (not used) */ - p_drv->init_struct.RxBufferSize = 0; - p_drv->init_struct.RxBufferDataSize = FDCAN_DATA_BYTES_64; + /* Dedicated RX Buffer configuration */ + p_drv->init_struct.RxBufferSize = resource.rx_buffer_size; + p_drv->init_struct.RxBufferDataSize = _fdcan_data_size_from_bytes(resource.rx_buffer_data_bytes); - /* TX Event FIFO configuration (not used) */ - p_drv->init_struct.TxEventSize = 0; + /* TX Event FIFO configuration */ + p_drv->init_struct.TxEventSize = resource.tx_event_size; - /* TX Buffer configuration: dedicated Tx Buffer mode */ - p_drv->init_struct.TxBufferSize = FDCAN_TX_BUF_NUM; - p_drv->init_struct.TxBufferDataSize = FDCAN_DATA_BYTES_64; - p_drv->init_struct.TxFifoQueueMode = FDCAN_TX_FIFO_MODE; - p_drv->init_struct.TxFifoQueueSize = 0; /* not using Tx FIFO, use Dedicated Tx Buffer */ + /* TX Buffer/FIFO/Queue configuration */ + p_drv->init_struct.TxBufferSize = resource.tx_buffer_size; + p_drv->init_struct.TxBufferDataSize = _fdcan_data_size_from_bytes(resource.tx_buffer_data_bytes); + p_drv->init_struct.TxFifoQueueMode = resource.tx_fifo_queue_mode; + p_drv->init_struct.TxFifoQueueSize = resource.tx_fifo_queue_size; /* Message RAM info pointer */ p_drv->init_struct.pMsgInfo = &p_drv->msg_ram; + /* Configure and validate the series-specific shared Message RAM. */ +#if defined(SOC_SERIES_N32H7xx) + { + uint32_t instance_idx = _fdcan_get_index(p_drv->fdcan_x); + uint32_t required_words = _fdcan_get_required_ram_words(&p_drv->init_struct); + + if (required_words > FDCAN_MSG_RAM_OFFSET_PER_INSTANCE) + { + LOG_E("%s: Message RAM needs %u words, slot has %u words", + p_drv->name, required_words, FDCAN_MSG_RAM_OFFSET_PER_INSTANCE); + return -RT_ENOMEM; + } + + if (instance_idx < 4) + { + p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE1; + p_drv->init_struct.MsgRamOffset = instance_idx * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; + } + else + { + p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE2; + p_drv->init_struct.MsgRamOffset = (instance_idx - 4) * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; + } + } +#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) + { + uint32_t offset = _fdcan_get_msg_ram_offset(p_drv->fdcan_x); + uint32_t required_words = _fdcan_get_required_ram_words(&p_drv->init_struct); + + if (offset == 0xFFFFFFFFU) + { + LOG_E("%s: invalid FDCAN instance", p_drv->name); + return -RT_ERROR; + } + + if (offset + required_words > BSP_FDCAN_MSG_RAM_WORDS) + { + LOG_E("%s: Message RAM range [%u, %u) exceeds %u words", + p_drv->name, offset, offset + required_words, + BSP_FDCAN_MSG_RAM_WORDS); + return -RT_ENOMEM; + } + + p_drv->init_struct.MsgRamStrAddr = (uint32_t)_fdcan_msg_ram; + p_drv->init_struct.MsgRamOffset = offset; + } +#endif + /* Stop FDCAN before re-initializing (needed for mode/baud changes) */ FDCAN_Stop(p_drv->fdcan_x); @@ -532,7 +767,7 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure * on every reconfigure. FDCAN_AbortTxRequest() is asynchronous - poll * TXBRP until it actually clears before continuing. */ { - rt_uint32_t cancel_mask = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; + rt_uint32_t cancel_mask = _fdcan_get_tx_buffer_mask(resource.tx_buffer_size); volatile uint32_t timeout = 1000000; FDCAN_AbortTxRequest(p_drv->fdcan_x, cancel_mask); while ((p_drv->fdcan_x->TXBRP & cancel_mask) && --timeout) @@ -549,11 +784,13 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure return -RT_ERROR; } -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) /* Configure and enable Transmitter Delay Compensation (TDC) */ - if (cfg->enable_canfd) + if (cfg->enable_canfd && resource.tdc_enabled) { - FDCAN_ConfigTxDelayCompensation(p_drv->fdcan_x, 0x0C, 0x00); + FDCAN_ConfigTxDelayCompensation(p_drv->fdcan_x, + resource.tdc_offset, + resource.tdc_filter); FDCAN_EnableTxDelayCompensation(p_drv->fdcan_x); } #endif @@ -565,14 +802,18 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure FDCAN_FILTER_STD_REMOTE, FDCAN_FILTER_EXT_REMOTE); - /* Apply default filter */ - FDCAN_ConfigFilter(p_drv->fdcan_x, &p_drv->filter_cfg); + /* Apply default filter when at least one standard filter is allocated. */ + if (p_drv->init_struct.StdFilterSize > 0) + { + FDCAN_ConfigFilter(p_drv->fdcan_x, &p_drv->filter_cfg); + } /* Configure RX FIFO0 as Overwrite mode */ FDCAN_ConfigRxFifoMode(p_drv->fdcan_x, FDCAN_RX_FIFO0, FDCAN_RX_FIFO_OVERWRITE); /* Configure RX FIFO0 watermark */ - FDCAN_ConfigFifoWatermark(p_drv->fdcan_x, FDCAN_RX_FIFO0, FDCAN_RX_FIFO0_WATERMARK); + FDCAN_ConfigFifoWatermark(p_drv->fdcan_x, FDCAN_RX_FIFO0, + (resource.rx_fifo0_size > 1U) ? (resource.rx_fifo0_size / 2U) : 1U); /* Enable RX FIFO0 New Message interrupt (INT0) */ FDCAN_ConfigIntLine(p_drv->fdcan_x, FDCAN_INT_RX_FIFO0_NEW_MESSAGE, FDCAN_INTERRUPT_LINE0); @@ -592,6 +833,10 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure /* Start FDCAN */ FDCAN_Start(p_drv->fdcan_x); + /* RT_DEVICE_CTRL_CONFIG bypasses the CAN framework's field-by-field + * setters, so keep the device's configuration snapshot synchronized. */ + p_drv->device.config = *cfg; + LOG_I("%s: configured, baud=%d, mode=%d", p_drv->name, cfg->baud_rate, cfg->mode); return RT_EOK; @@ -720,7 +965,7 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) FDCAN_INTERRUPT_LINE1); /* Activate TX Complete interrupt for each dedicated TX Buffer */ FDCAN_ActivateInt(p_drv->fdcan_x, FDCAN_INT_TX_COMPLETE, - FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2); + _fdcan_get_tx_buffer_mask(p_drv->init_struct.TxBufferSize)); NVIC_SetPriority(_fdcan_get_int1_irqn(p_drv->fdcan_x), 2); NVIC_EnableIRQ(_fdcan_get_int1_irqn(p_drv->fdcan_x)); } @@ -745,10 +990,20 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) break; case RT_CAN_CMD_SET_FILTER: +#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) + /* Filter changes follow the same Stop/Init/Start re-init rule. */ + if (_fdcan_configure(&p_drv->device, &p_drv->device.config) != RT_EOK) + { + return -RT_ERROR; + } +#endif if (RT_NULL == arg) { /* Restore default filter */ - FDCAN_ConfigFilter(p_drv->fdcan_x, &p_drv->filter_cfg); + if (p_drv->init_struct.StdFilterSize > 0) + { + FDCAN_ConfigFilter(p_drv->fdcan_x, &p_drv->filter_cfg); + } } else { @@ -768,6 +1023,12 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) } if (argval != p_drv->device.config.mode) { +#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) + struct can_configure new_config = p_drv->device.config; + + new_config.mode = argval; + return _fdcan_configure(&p_drv->device, &new_config); +#else /* Direct CCCR register modification for mode change * (avoids full FDCAN_Stop+Init re-init which can fail) */ FDCAN_Module *fdcan = p_drv->fdcan_x; @@ -776,7 +1037,7 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) * (see _fdcan_configure() for the same pattern); the abort is * asynchronous, so poll TXBRP until it actually clears. */ { - rt_uint32_t cm = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; + rt_uint32_t cm = _fdcan_get_tx_buffer_mask(p_drv->init_struct.TxBufferSize); volatile uint32_t to = 1000000; FDCAN_AbortTxRequest(fdcan, cm); while ((fdcan->TXBRP & cm) && --to) @@ -819,6 +1080,7 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) while (fdcan->CCCR & FDCAN_CCCR_INIT); p_drv->device.config.mode = argval; LOG_I("%s: mode changed to %d", p_drv->name, argval); +#endif } break; @@ -830,8 +1092,10 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) } if (argval != p_drv->device.config.baud_rate) { - p_drv->device.config.baud_rate = argval; - return _fdcan_configure(&p_drv->device, &p_drv->device.config); + struct can_configure new_config = p_drv->device.config; + + new_config.baud_rate = argval; + return _fdcan_configure(&p_drv->device, &new_config); } break; @@ -867,8 +1131,10 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) } if (argval != p_drv->device.config.baud_rate_fd) { - p_drv->device.config.baud_rate_fd = argval; - return _fdcan_configure(&p_drv->device, &p_drv->device.config); + struct can_configure new_config = p_drv->device.config; + + new_config.baud_rate_fd = argval; + return _fdcan_configure(&p_drv->device, &new_config); } #endif } @@ -893,7 +1159,7 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) *\*\param buf : *\*\ Pointer to the CAN message to be sent *\*\param box_no : - *\*\ TX Buffer index (0 ~ FDCAN_TX_BUF_NUM-1) + *\*\ TX Buffer index (0 ~ configured TxBufferSize-1) *\*\return RT_EOK on success, or negative error code on failure */ static rt_ssize_t _fdcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_no) @@ -1093,7 +1359,7 @@ static rt_ssize_t _fdcan_sendmsg_nonblocking(struct rt_can_device *can, const vo RT_ASSERT(p_drv != RT_NULL); /* Scan dedicated TX Buffers for a free one */ - for (rt_uint32_t i = 0; i < FDCAN_TX_BUF_NUM; i++) + for (rt_uint32_t i = 0; i < p_drv->init_struct.TxBufferSize; i++) { if (FDCAN_CheckTxBufRequest(p_drv->fdcan_x, FDCAN_TX_BUFFER0 << i) == RESET) { @@ -1205,7 +1471,7 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) rt_uint32_t buffer_idx = 0; rt_bool_t found = RT_FALSE; - for (rt_uint32_t i = 0; i < FDCAN_TX_BUF_NUM; i++) + for (rt_uint32_t i = 0; i < p_drv->init_struct.TxBufferSize; i++) { rt_uint32_t bit = FDCAN_TX_BUFFER0 << i; if ((p_drv->tx_pending_mask & bit) && !(fdcan->TXBRP & bit)) @@ -1222,7 +1488,7 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) * dropping the event. */ if (!found) { - for (rt_uint32_t i = 0; i < FDCAN_TX_BUF_NUM; i++) + for (rt_uint32_t i = 0; i < p_drv->init_struct.TxBufferSize; i++) { rt_uint32_t bit = FDCAN_TX_BUFFER0 << i; if (p_drv->tx_pending_mask & bit) @@ -1258,7 +1524,7 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) /* PSR.BO == 1 means this IR.BO edge is a Bus-Off *entry*; == 0 * would mean leaving Bus-Off (recovery is kicked off separately * by the ARB_PROTOCOL_ERROR branch below). */ - for (rt_uint32_t i = 0; i < FDCAN_TX_BUF_NUM; i++) + for (rt_uint32_t i = 0; i < p_drv->init_struct.TxBufferSize; i++) { rt_uint32_t bit = FDCAN_TX_BUFFER0 << i; if (p_drv->tx_pending_mask & bit) @@ -1368,7 +1634,7 @@ void FDCAN3_INT1_IRQHandler(void) } #endif /* BSP_USING_FDCAN3 */ -#ifdef BSP_USING_FDCAN4 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN4) void FDCAN4_INT0_IRQHandler(void) { rt_interrupt_enter(); @@ -1384,7 +1650,7 @@ void FDCAN4_INT1_IRQHandler(void) } #endif /* BSP_USING_FDCAN4 */ -#ifdef BSP_USING_FDCAN5 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN5) void FDCAN5_INT0_IRQHandler(void) { rt_interrupt_enter(); @@ -1400,7 +1666,7 @@ void FDCAN5_INT1_IRQHandler(void) } #endif /* BSP_USING_FDCAN5 */ -#ifdef BSP_USING_FDCAN6 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN6) void FDCAN6_INT0_IRQHandler(void) { rt_interrupt_enter(); @@ -1416,7 +1682,7 @@ void FDCAN6_INT1_IRQHandler(void) } #endif /* BSP_USING_FDCAN6 */ -#ifdef BSP_USING_FDCAN7 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN7) void FDCAN7_INT0_IRQHandler(void) { rt_interrupt_enter(); @@ -1432,7 +1698,7 @@ void FDCAN7_INT1_IRQHandler(void) } #endif /* BSP_USING_FDCAN7 */ -#ifdef BSP_USING_FDCAN8 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN8) void FDCAN8_INT0_IRQHandler(void) { rt_interrupt_enter(); @@ -1464,12 +1730,13 @@ void FDCAN8_INT1_IRQHandler(void) static int rt_hw_fdcan_init(void) { struct can_configure config; + struct n32_fdcan_resource_config resource; FDCAN_FilterType default_filter; /* Default CAN configuration */ config.baud_rate = CAN1MBaud; config.msgboxsz = RT_CANMSG_BOX_SZ; - config.sndboxnumber = FDCAN_TX_BUF_NUM; + config.sndboxnumber = 1; config.mode = RT_CAN_MODE_NORMAL; config.privmode = RT_CAN_MODE_NOPRIV; config.ticks = 50; @@ -1490,7 +1757,23 @@ static int rt_hw_fdcan_init(void) default_filter.FilterID2 = 0x000; default_filter.RxBufferIndex = 0; +#if defined(SOC_SERIES_N32H47x_48x) + /* RCC_Configuration() selects the kernel clock; enable APB gating here. */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_FDCAN1 | + RCC_APB1_PERIPH_FDCAN2 | + RCC_APB1_PERIPH_FDCAN3, + ENABLE); +#elif defined(SOC_SERIES_N32H49x) + /* RCC_Configuration() selects the kernel clock; enable APB gating here. */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_FDCAN1 | + RCC_APB1_PERIPHEN_FDCAN2 | + RCC_APB1_PERIPHEN_FDCAN3, + ENABLE); +#endif + #ifdef BSP_USING_FDCAN1 + _fdcan_get_resource_config(FDCAN1, _drv_fdcan1.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan1.fdcan_x = FDCAN1; _drv_fdcan1.filter_cfg = default_filter; _drv_fdcan1.device.config = config; @@ -1499,6 +1782,8 @@ static int rt_hw_fdcan_init(void) #endif #ifdef BSP_USING_FDCAN2 + _fdcan_get_resource_config(FDCAN2, _drv_fdcan2.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan2.fdcan_x = FDCAN2; _drv_fdcan2.filter_cfg = default_filter; _drv_fdcan2.device.config = config; @@ -1507,6 +1792,8 @@ static int rt_hw_fdcan_init(void) #endif #ifdef BSP_USING_FDCAN3 + _fdcan_get_resource_config(FDCAN3, _drv_fdcan3.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan3.fdcan_x = FDCAN3; _drv_fdcan3.filter_cfg = default_filter; _drv_fdcan3.device.config = config; @@ -1514,7 +1801,9 @@ static int rt_hw_fdcan_init(void) LOG_I("FDCAN3 registered"); #endif -#ifdef BSP_USING_FDCAN4 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN4) + _fdcan_get_resource_config(FDCAN4, _drv_fdcan4.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan4.fdcan_x = FDCAN4; _drv_fdcan4.filter_cfg = default_filter; _drv_fdcan4.device.config = config; @@ -1522,7 +1811,9 @@ static int rt_hw_fdcan_init(void) LOG_I("FDCAN4 registered"); #endif -#ifdef BSP_USING_FDCAN5 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN5) + _fdcan_get_resource_config(FDCAN5, _drv_fdcan5.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan5.fdcan_x = FDCAN5; _drv_fdcan5.filter_cfg = default_filter; _drv_fdcan5.device.config = config; @@ -1530,7 +1821,9 @@ static int rt_hw_fdcan_init(void) LOG_I("FDCAN5 registered"); #endif -#ifdef BSP_USING_FDCAN6 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN6) + _fdcan_get_resource_config(FDCAN6, _drv_fdcan6.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan6.fdcan_x = FDCAN6; _drv_fdcan6.filter_cfg = default_filter; _drv_fdcan6.device.config = config; @@ -1538,7 +1831,9 @@ static int rt_hw_fdcan_init(void) LOG_I("FDCAN6 registered"); #endif -#ifdef BSP_USING_FDCAN7 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN7) + _fdcan_get_resource_config(FDCAN7, _drv_fdcan7.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan7.fdcan_x = FDCAN7; _drv_fdcan7.filter_cfg = default_filter; _drv_fdcan7.device.config = config; @@ -1546,7 +1841,9 @@ static int rt_hw_fdcan_init(void) LOG_I("FDCAN7 registered"); #endif -#ifdef BSP_USING_FDCAN8 +#if defined(SOC_SERIES_N32H7xx) && defined(BSP_USING_FDCAN8) + _fdcan_get_resource_config(FDCAN8, _drv_fdcan8.config, &resource); + config.sndboxnumber = resource.tx_buffer_size; _drv_fdcan8.fdcan_x = FDCAN8; _drv_fdcan8.filter_cfg = default_filter; _drv_fdcan8.device.config = config; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h index 4b7e676825..4e49c31d27 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h @@ -6,14 +6,16 @@ * Change Logs: * Date Author Notes * 2026-06-22 ox-horse first version - N32H7xx FDCAN driver + * 2026-08-05 ox-horse add N32H47x/48x support + * 2026-08-06 ox-horse add N32H49x support */ #ifndef __DRV_FDCAN_H__ #define __DRV_FDCAN_H__ +#include <board.h> #include <rtdevice.h> #include <rtthread.h> -#include <board.h> #ifdef __cplusplus extern "C" { @@ -27,9 +29,9 @@ struct n32_fdcan_arb_timing { uint32_t baud_rate; /**< baud rate in bps */ uint16_t prescaler; /**< prescaler (1~512) */ - uint8_t sjw; /**< synchronization jump width (1~128) */ + uint8_t sjw; /**< synchronization jump width (1~128) */ uint16_t tseg1; /**< time segment 1 (2~256) */ - uint8_t tseg2; /**< time segment 2 (2~128) */ + uint8_t tseg2; /**< time segment 2 (2~128) */ }; /** @@ -40,27 +42,30 @@ struct n32_fdcan_data_timing { uint32_t baud_rate; /**< data phase baud rate in bps */ uint16_t prescaler; /**< data phase prescaler (1~32) */ - uint8_t sjw; /**< data phase synchronization jump width (1~16) */ + uint8_t sjw; /**< data phase synchronization jump width (1~16) */ uint16_t tseg1; /**< data phase time segment 1 (1~32) */ - uint8_t tseg2; /**< data phase time segment 2 (1~16) */ + uint8_t tseg2; /**< data phase time segment 2 (1~16) */ }; +struct n32_fdcan_config; + /** *\*\name n32_fdcan. *\*\brief N32 FDCAN device structure. *\*\note GPIO pin initialization is handled by CubeMX-generated code - *\*\ in n32h7xx_cfg.c. This driver only handles peripheral configuration. + *\*\ in Cube-generated board code. This driver only handles peripheral configuration. */ struct n32_fdcan { - const char *name; /**< device name */ - FDCAN_Module *fdcan_x; /**< FDCAN peripheral base address (FDCAN1~FDCAN8) */ - FDCAN_InitType init_struct; /**< FDCAN init parameters */ - FDCAN_MsgRamType msg_ram; /**< Message RAM block config */ - FDCAN_FilterType filter_cfg; /**< default filter configuration */ - FDCAN_TxHeaderType tx_header; /**< TX header cache */ - FDCAN_RxHeaderType rx_header; /**< RX header cache */ - rt_uint32_t tx_pending_mask; /**< software mask of TX buffers with a pending request + const char *name; /**< device name */ + const struct n32_fdcan_config *config; /**< instance resource configuration */ + FDCAN_Module *fdcan_x; /**< FDCAN peripheral base address */ + FDCAN_InitType init_struct; /**< FDCAN init parameters */ + FDCAN_MsgRamType msg_ram; /**< Message RAM block config */ + FDCAN_FilterType filter_cfg; /**< default filter configuration */ + FDCAN_TxHeaderType tx_header; /**< TX header cache */ + FDCAN_RxHeaderType rx_header; /**< RX header cache */ + rt_uint32_t tx_pending_mask; /**< software mask of TX buffers with a pending request (FDCAN_TX_BUFFER0<<i). Cleared when the ISR detects TXBRP has gone to zero for that buffer, i.e. the hardware finished/cancelled the transmission. */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.c new file mode 100644 index 0000000000..7828cfbf49 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-06 li.mengmeng implement for N32H47x/48x + */ + +#include <rtconfig.h> +#include <rtthread.h> + +#ifdef BSP_USING_ON_CHIP_FLASH + +#include <board.h> +#include "drv_flash_h47x_48x.h" +#include "n32h47x_48x_flash.h" +#include "n32h47x_48x_rcc.h" + +#ifdef RT_USING_FAL +#include <fal.h> +#endif + +#define LOG_TAG "drv.flash" +#include <drv_log.h> + +#define N32_FLASH_PAGE_SIZE ((rt_uint32_t)0x2000U) +#define N32_FLASH_PROGRAM_SIZE ((rt_uint32_t)0x0008U) + +static struct rt_mutex _flash_mutex; + +static rt_bool_t n32_flash_range_is_valid(rt_uint32_t addr, size_t size) +{ + if ((size == 0U) || (addr < N32_FLASH_START_ADRESS) || + (addr >= N32_FLASH_END_ADDRESS)) + { + return RT_FALSE; + } + + if (size > (size_t)(N32_FLASH_END_ADDRESS - addr)) + { + return RT_FALSE; + } + + return RT_TRUE; +} + +static rt_err_t n32_flash_prepare(void) +{ + RCC_EnableHsi(ENABLE); + if (RCC_WaitHsiStable() != SUCCESS) + { + LOG_E("HSI is not ready"); + return -RT_ERROR; + } + + FLASH_Unlock(); + if (Flash_GetLockStatus() != RESET) + { + LOG_E("unlock failed"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int n32_flash_lock_take(void) +{ + if (rt_mutex_take(&_flash_mutex, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_EBUSY; + } + + return RT_EOK; +} + +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) +{ + int result; + + if ((buf == RT_NULL) || !n32_flash_range_is_valid(addr, size)) + { + LOG_E("invalid read: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + rt_memcpy(buf, (const void *)addr, size); + rt_mutex_release(&_flash_mutex); + + return (int)size; +} + +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) +{ + FLASH_STS status; + rt_uint32_t data[2]; + rt_uint32_t write_addr; + size_t offset; + size_t i; + int result; + + if ((buf == RT_NULL) || !n32_flash_range_is_valid(addr, size) || + ((addr & (N32_FLASH_PROGRAM_SIZE - 1U)) != 0U) || + ((size & (N32_FLASH_PROGRAM_SIZE - 1U)) != 0U)) + { + LOG_E("invalid write: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + for (i = 0; i < size; i++) + { + if (*(const rt_uint8_t *)(addr + i) != 0xFFU) + { + LOG_E("write target is not erased: addr=0x%08x", addr + (rt_uint32_t)i); + result = -RT_ERROR; + goto __exit; + } + } + + result = n32_flash_prepare(); + if (result != RT_EOK) + { + goto __exit; + } + + for (offset = 0; offset < size; offset += N32_FLASH_PROGRAM_SIZE) + { + write_addr = addr + (rt_uint32_t)offset; + rt_memcpy(data, buf + offset, sizeof(data)); + + status = FLASH_ProgramdoubleWord(write_addr, data[0], data[1]); + if (status != FLASH_EOP) + { + LOG_E("program failed: addr=0x%08x, status=%d", write_addr, status); + result = -RT_ERROR; + goto __lock_exit; + } + + if (rt_memcmp((const void *)write_addr, buf + offset, + N32_FLASH_PROGRAM_SIZE) != 0) + { + LOG_E("verify failed: addr=0x%08x", write_addr); + result = -RT_ERROR; + goto __lock_exit; + } + } + + result = (int)size; + +__lock_exit: + FLASH_Lock(); +__exit: + rt_mutex_release(&_flash_mutex); + return result; +} + +int n32_flash_erase(rt_uint32_t addr, size_t size) +{ + FLASH_STS status; + rt_uint32_t erase_addr; + rt_uint32_t end_addr; + int result; + + if (!n32_flash_range_is_valid(addr, size)) + { + LOG_E("invalid erase: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + result = n32_flash_prepare(); + if (result != RT_EOK) + { + goto __exit; + } + + erase_addr = addr & ~(N32_FLASH_PAGE_SIZE - 1U); + end_addr = addr + (rt_uint32_t)size; + + while (erase_addr < end_addr) + { + status = FLASH_EraseOnePage(erase_addr); + if (status != FLASH_EOP) + { + LOG_E("erase failed: addr=0x%08x, status=%d", erase_addr, status); + result = -RT_ERROR; + goto __lock_exit; + } + + erase_addr += N32_FLASH_PAGE_SIZE; + } + + result = (int)size; + +__lock_exit: + FLASH_Lock(); +__exit: + rt_mutex_release(&_flash_mutex); + return result; +} + +static int n32_flash_init(void) +{ + return rt_mutex_init(&_flash_mutex, "flash", RT_IPC_FLAG_PRIO); +} +INIT_DEVICE_EXPORT(n32_flash_init); + +#ifdef RT_USING_FAL + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); +static int fal_flash_erase(long offset, size_t size); + +const struct fal_flash_dev n32_onchip_flash = { + "onchip_flash", + N32_FLASH_START_ADRESS, + N32_FLASH_SIZE, + N32_FLASH_PAGE_SIZE, + { RT_NULL, fal_flash_read, fal_flash_write, fal_flash_erase } +}; + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) +{ + return n32_flash_read(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return n32_flash_write(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_erase(long offset, size_t size) +{ + return n32_flash_erase(n32_onchip_flash.addr + offset, size); +} + +#endif /* RT_USING_FAL */ + +#endif /* BSP_USING_ON_CHIP_FLASH */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.h new file mode 100644 index 0000000000..d6c85fc612 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h47x_48x.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-06 li.mengmeng implement for N32H47x/48x + */ + +#ifndef __DRV_FLASH_H47X_48X_H__ +#define __DRV_FLASH_H47X_48X_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size); +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size); +int n32_flash_erase(rt_uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H47X_48X_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.c new file mode 100644 index 0000000000..b899e606de --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-07 li.mengmeng implement for N32H49x dual-bank mode + */ + +#include <rtconfig.h> +#include <rtthread.h> + +#ifdef BSP_USING_ON_CHIP_FLASH + +#include <board.h> +#include "drv_flash_h49x.h" +#include "n32h49x_flash.h" +#include "n32h49x_rcc.h" + +#ifdef RT_USING_FAL +#include <fal.h> +#endif + +#define LOG_TAG "drv.flash" +#include <drv_log.h> + +#define N32_FLASH_PAGE_SIZE ((rt_uint32_t)0x2000U) +#define N32_FLASH_PROGRAM_SIZE ((rt_uint32_t)0x0008U) + +static struct rt_mutex _flash_mutex; + +static rt_bool_t n32_flash_range_is_valid(rt_uint32_t addr, size_t size) +{ + if ((size == 0U) || (addr < N32_FLASH_START_ADRESS) || + (addr >= N32_FLASH_END_ADDRESS)) + { + return RT_FALSE; + } + + if (size > (size_t)(N32_FLASH_END_ADDRESS - addr)) + { + return RT_FALSE; + } + + return RT_TRUE; +} + +static rt_bool_t n32_flash_dual_bank_is_active(void) +{ + return FLASH_GetFlagSTS(FLASH_FLAG_BANKMODE) == SET ? RT_TRUE : RT_FALSE; +} + +static rt_bool_t n32_flash_dcache_suspend(void) +{ + rt_bool_t enabled; + + enabled = (FLASH->AC & FLASH_AC_DCAHEN) != 0U ? RT_TRUE : RT_FALSE; + if (enabled) + { + FLASH_DCacheCmd(FLASH_DCache_DIS); + FLASH_DCacheRST(); + } + + return enabled; +} + +static void n32_flash_dcache_restore(rt_bool_t enabled) +{ + if (enabled) + { + FLASH_DCacheRST(); + FLASH_DCacheCmd(FLASH_DCache_EN); + } +} + +static rt_err_t n32_flash_prepare(void) +{ + RCC_EnableHsi(ENABLE); + if (RCC_WaitHsiStable() != SUCCESS) + { + LOG_E("HSI is not ready"); + return -RT_ERROR; + } + + FLASH_Unlock(); + if (Flash_GetLockStatus() != RESET) + { + LOG_E("unlock failed"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int n32_flash_lock_take(void) +{ + if (rt_mutex_take(&_flash_mutex, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_EBUSY; + } + + return RT_EOK; +} + +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) +{ + rt_bool_t dcache_enabled; + int result; + + if ((buf == RT_NULL) || !n32_flash_range_is_valid(addr, size)) + { + LOG_E("invalid read: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + dcache_enabled = n32_flash_dcache_suspend(); + rt_memcpy(buf, (const void *)addr, size); + n32_flash_dcache_restore(dcache_enabled); + rt_mutex_release(&_flash_mutex); + + return (int)size; +} + +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) +{ + FLASH_STS status; + rt_uint32_t data[2]; + rt_uint32_t write_addr; + rt_bool_t dcache_enabled; + size_t offset; + size_t i; + int result; + + if ((buf == RT_NULL) || !n32_flash_range_is_valid(addr, size) || + ((addr & (N32_FLASH_PROGRAM_SIZE - 1U)) != 0U) || + ((size & (N32_FLASH_PROGRAM_SIZE - 1U)) != 0U)) + { + LOG_E("invalid write: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + if (!n32_flash_dual_bank_is_active()) + { + LOG_E("write rejected: Flash is not in dual-bank mode"); + return -RT_ERROR; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + dcache_enabled = n32_flash_dcache_suspend(); + + for (i = 0; i < size; i++) + { + if (*(const rt_uint8_t *)(addr + i) != 0xFFU) + { + LOG_E("write target is not erased: addr=0x%08x", addr + (rt_uint32_t)i); + result = -RT_ERROR; + goto __exit; + } + } + + result = n32_flash_prepare(); + if (result != RT_EOK) + { + goto __exit; + } + + for (offset = 0; offset < size; offset += N32_FLASH_PROGRAM_SIZE) + { + write_addr = addr + (rt_uint32_t)offset; + rt_memcpy(data, buf + offset, sizeof(data)); + + status = FLASH_ProgramdoubleWord(write_addr, data[0], data[1]); + if (status != FLASH_EOP) + { + LOG_E("program failed: addr=0x%08x, status=%d", write_addr, status); + result = -RT_ERROR; + goto __lock_exit; + } + + if (rt_memcmp((const void *)write_addr, buf + offset, + N32_FLASH_PROGRAM_SIZE) != 0) + { + LOG_E("verify failed: addr=0x%08x", write_addr); + result = -RT_ERROR; + goto __lock_exit; + } + } + + result = (int)size; + +__lock_exit: + FLASH_Lock(); +__exit: + n32_flash_dcache_restore(dcache_enabled); + rt_mutex_release(&_flash_mutex); + return result; +} + +int n32_flash_erase(rt_uint32_t addr, size_t size) +{ + FLASH_STS status; + rt_uint32_t erase_addr; + rt_uint32_t end_addr; + rt_bool_t dcache_enabled; + int result; + + if (!n32_flash_range_is_valid(addr, size)) + { + LOG_E("invalid erase: addr=0x%08x, size=%u", addr, (unsigned int)size); + return -RT_EINVAL; + } + + if (!n32_flash_dual_bank_is_active()) + { + LOG_E("erase rejected: Flash is not in dual-bank mode"); + return -RT_ERROR; + } + + result = n32_flash_lock_take(); + if (result != RT_EOK) + { + return result; + } + + dcache_enabled = n32_flash_dcache_suspend(); + result = n32_flash_prepare(); + if (result != RT_EOK) + { + goto __exit; + } + + erase_addr = addr & ~(N32_FLASH_PAGE_SIZE - 1U); + end_addr = addr + (rt_uint32_t)size; + + while (erase_addr < end_addr) + { + status = FLASH_EraseOnePage(erase_addr); + if (status != FLASH_EOP) + { + LOG_E("erase failed: addr=0x%08x, status=%d", erase_addr, status); + result = -RT_ERROR; + goto __lock_exit; + } + + erase_addr += N32_FLASH_PAGE_SIZE; + } + + result = (int)size; + +__lock_exit: + FLASH_Lock(); +__exit: + n32_flash_dcache_restore(dcache_enabled); + rt_mutex_release(&_flash_mutex); + return result; +} + +static int n32_flash_init(void) +{ + rt_err_t result; + + result = rt_mutex_init(&_flash_mutex, "flash", RT_IPC_FLAG_PRIO); + if ((result == RT_EOK) && !n32_flash_dual_bank_is_active()) + { + LOG_E("single-bank mode detected; erase/write are disabled"); + } + + return result; +} +INIT_DEVICE_EXPORT(n32_flash_init); + +#ifdef RT_USING_FAL + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); +static int fal_flash_erase(long offset, size_t size); + +const struct fal_flash_dev n32_onchip_flash = { + "onchip_flash", + N32_FLASH_START_ADRESS, + N32_FLASH_SIZE, + N32_FLASH_PAGE_SIZE, + { RT_NULL, fal_flash_read, fal_flash_write, fal_flash_erase } +}; + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) +{ + return n32_flash_read(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return n32_flash_write(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_erase(long offset, size_t size) +{ + return n32_flash_erase(n32_onchip_flash.addr + offset, size); +} + +#endif /* RT_USING_FAL */ + +#endif /* BSP_USING_ON_CHIP_FLASH */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.h new file mode 100644 index 0000000000..daee2ee408 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h49x.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-07 li.mengmeng implement for N32H49x + */ + +#ifndef __DRV_FLASH_H49X_H__ +#define __DRV_FLASH_H49X_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size); +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size); +int n32_flash_erase(rt_uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H49X_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h index 2b9d4f9abf..db0ff4852b 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h @@ -18,10 +18,10 @@ extern "C" { #endif -#define __N32_PORT(port) GPIO##port##_BASE +#define __N32_PORT(port) GPIO##port##_BASE -#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__N32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) +#define GET_PIN(PORTx, PIN) (rt_base_t)((16 * (((rt_base_t)__N32_PORT(PORTx) - (rt_base_t)GPIOA_BASE) / (0x0400UL))) + PIN) struct pin_irq_map diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c index 0b27136700..3fa639d58d 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c @@ -19,26 +19,26 @@ defined(BSP_USING_HARD_I2C6) || defined(BSP_USING_HARD_I2C7) || defined(BSP_USING_HARD_I2C8) || defined(BSP_USING_HARD_I2C9) || defined(BSP_USING_HARD_I2C10) -#define I2C_CTRL2_NBYTES_POS (16U) -#define MAX_NBYTE_SIZE (255U) +#define I2C_CTRL2_NBYTES_POS (16U) +#define MAX_NBYTE_SIZE (255U) -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_START_READ (I2C_CTRL2_START | I2C_CTRL2_RWN) -#define I2C_START_WRITE (I2C_CTRL2_START) +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_START_READ (I2C_CTRL2_START | I2C_CTRL2_RWN) +#define I2C_START_WRITE (I2C_CTRL2_START) -#define I2C_RELOAD_MODE (CTRL2_REFILL_ENABLE) -#define I2C_AUTOEND_MODE (CTRL2_AUTO_STOP) -#define I2C_SOFTEND_MODE (0x00000000U) +#define I2C_RELOAD_MODE (CTRL2_REFILL_ENABLE) +#define I2C_AUTOEND_MODE (CTRL2_AUTO_STOP) +#define I2C_SOFTEND_MODE (0x00000000U) -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ -#define I2C_CTRL2_CLEAR (I2C_CTRL2_SADR | I2C_CTRL2_RWN | I2C_CTRL2_START | I2C_CTRL2_STOP | I2C_CTRL2_BYTECNT | I2C_CTRL2_REFILL | I2C_CTRL2_AUTOSTOP) +#define I2C_CTRL2_CLEAR (I2C_CTRL2_SADR | I2C_CTRL2_RWN | I2C_CTRL2_START | I2C_CTRL2_STOP | I2C_CTRL2_BYTECNT | I2C_CTRL2_REFILL | I2C_CTRL2_AUTOSTOP) //#define DRV_DEBUG #define LOG_TAG "drv.i2c.hw" @@ -82,8 +82,7 @@ enum #endif /* BSP_USING_HARD_I2C10 */ }; -static struct n32_i2c_config i2c_config[] = -{ +static struct n32_i2c_config i2c_config[] = { #ifdef BSP_USING_HARD_I2C1 I2C1_BUS_CONFIG, #endif /* BSP_USING_HARD_I2C1 */ @@ -116,7 +115,7 @@ static struct n32_i2c_config i2c_config[] = #endif /* BSP_USING_HARD_I2C10 */ }; -static struct n32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; +static struct n32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = { 0 }; static rt_ssize_t n32_iic_transfer_by_dma(struct n32_i2c_config *config, uint8_t *pData, uint16_t Size, rt_bool_t is_rx) { @@ -186,12 +185,12 @@ static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) /* DMA channel struct configuration */ DMA_ChannelStructInit(&DMA_ChInitStr); - DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; - DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; - DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; - DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; /* Read by DMA */ if (is_rx) @@ -202,13 +201,13 @@ static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) RCC_EnableAHB1PeriphClk3(dma_config->dma_rcc, ENABLE); /* DMA channel struct configuration */ - DMA_ChInitStr.SrcAddr = (uint32_t)&config->Instance->RDR; - DMA_ChInitStr.DstAddr = (uint32_t)RT_NULL; - DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; - DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; - DMA_ChInitStr.SrcHsInterface = dma_config->HsInterface; + DMA_ChInitStr.SrcAddr = (uint32_t)&config->Instance->RDR; + DMA_ChInitStr.DstAddr = (uint32_t)RT_NULL; + DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + DMA_ChInitStr.SrcHsInterface = dma_config->HsInterface; } /* Write by DMA */ else @@ -219,13 +218,13 @@ static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) RCC_EnableAHB1PeriphClk3(dma_config->dma_rcc, ENABLE); /* DMA channel struct configuration */ - DMA_ChInitStr.SrcAddr = (uint32_t) RT_NULL; - DMA_ChInitStr.DstAddr = (uint32_t)&config->Instance->WDR; - DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; - DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; - DMA_ChInitStr.DstHsInterface = dma_config->HsInterface; + DMA_ChInitStr.SrcAddr = (uint32_t)RT_NULL; + DMA_ChInitStr.DstAddr = (uint32_t)&config->Instance->WDR; + DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + DMA_ChInitStr.DstHsInterface = dma_config->HsInterface; } /* DMA controller must be enabled before initializing the channel */ @@ -236,11 +235,10 @@ static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) { return -RT_ERROR; } -#endif - /* enable dma irq */ NVIC_SetPriority(dma_config->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_EnableIRQ(dma_config->dma_irq); +#endif return RT_EOK; } @@ -248,7 +246,7 @@ static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv) { rt_err_t ret; - uint32_t BusTim_Reg; + uint32_t BusTim_Reg = 0; I2C_InitType I2C_InitStructure; RT_ASSERT(i2c_drv != RT_NULL); @@ -284,14 +282,14 @@ static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv) I2C_DeInit(cfg->Instance); I2C_InitStruct(&I2C_InitStructure); - I2C_InitStructure.Timing = ((BusTim_Reg != 0) ? BusTim_Reg : cfg->timing); - I2C_InitStructure.OwnAddress1 = 0x0; - I2C_InitStructure.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2C_InitStructure.DualAddressMode = I2C_DUALADDRESS_DISABLE; - I2C_InitStructure.OwnAddress2 = 0x0; + I2C_InitStructure.Timing = ((BusTim_Reg != 0) ? BusTim_Reg : cfg->timing); + I2C_InitStructure.OwnAddress1 = 0x0; + I2C_InitStructure.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + I2C_InitStructure.DualAddressMode = I2C_DUALADDRESS_DISABLE; + I2C_InitStructure.OwnAddress2 = 0x0; I2C_InitStructure.OwnAddress2Masks = I2C_ADDRESS2MASK_NONE; - I2C_InitStructure.GeneralCallMode = I2C_GENERALCALL_DISABLE; - I2C_InitStructure.NoStretchMode = I2C_NOSTRCH_DISABLE; + I2C_InitStructure.GeneralCallMode = I2C_GENERALCALL_DISABLE; + I2C_InitStructure.NoStretchMode = I2C_NOSTRCH_DISABLE; I2C_Init(cfg->Instance, &I2C_InitStructure); I2C_Enable(cfg->Instance, ENABLE); @@ -569,7 +567,7 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) { -#define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ #define TRANS_TIMEOUT_PERSEC 8 /* per ms will trans nums bytes */ rt_int32_t i, ret; @@ -621,8 +619,8 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, if (msg->flags & RT_I2C_RD) { LOG_D("xfer rec msgs[%d] i2c mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" - : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" - : "nuknown mode"); + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = n32_i2c_master_seq_receive_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); @@ -640,14 +638,13 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, { LOG_D("receive time out"); goto out; - } } else { LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" - : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" - : "nuknown mode"); + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = n32_i2c_master_seq_send_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); @@ -675,23 +672,27 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; if (msg->flags & RT_I2C_NO_STOP) + { mode = I2C_LAST_FRAME_NO_STOP; + } else + { mode = I2C_LAST_FRAME; + } LOG_D("xfer last msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); if (msg->flags & RT_I2C_RD) { LOG_D("xfer rec msgs[%d] hal mode=%s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" - : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" - : "nuknown mode"); + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = n32_i2c_master_seq_receive_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); } else { - uint32_t itflags = READ_REG(i2c_obj->config->Instance->STSINT); + uint32_t itflags = READ_REG(i2c_obj->config->Instance->STSINT); ret = n32_i2c_master_seq_receive_it(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); } if (ret != RT_EOK) @@ -708,8 +709,8 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, else { LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" - : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" - : "nuknown mode"); + : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" + : "nuknown mode"); if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = n32_i2c_master_seq_send_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); @@ -727,7 +728,6 @@ static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, { LOG_D("transmit time out"); goto out; - } } LOG_D("xfer end %d mags\r\n", num); @@ -738,8 +738,7 @@ out: } -static const struct rt_i2c_bus_device_ops n32_i2c_ops = -{ +static const struct rt_i2c_bus_device_ops n32_i2c_ops = { .master_xfer = n32_i2c_master_xfer, RT_NULL, RT_NULL @@ -914,7 +913,7 @@ static void i2c_it_error_handler(struct n32_i2c *drv_i2c, uint32_t itflags) } if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) || - ((((itflags & I2C_STSINT_BSER) == I2C_STSINT_BSER) ? SET : RESET) != RESET)) + ((((itflags & I2C_STSINT_BSER) == I2C_STSINT_BSER) ? SET : RESET) != RESET)) { /* Send stop signal to prevent bus lock-up */ LOG_D("I2C NACK Error or BUS Error now stoped"); @@ -1009,7 +1008,7 @@ static void i2c_master_ev_isr_handler_it(struct n32_i2c *drv_i2c) uint16_t devaddress; uint32_t setmask; /* Get current IT Flags and IT sources value */ - volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); /* It takes more than 100 microseconds to clear the TC flag after starting, so wait for the TC flag to clear */ @@ -1026,7 +1025,7 @@ static void i2c_master_ev_isr_handler_it(struct n32_i2c *drv_i2c) } if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) { /* Clear Not Acknowledge received flag */ drv_i2c->config->Instance->INTCLR = I2C_INTCLR_NAKCLR; @@ -1122,7 +1121,7 @@ static void i2c_master_ev_isr_handler_it(struct n32_i2c *drv_i2c) } if (((((itflags & I2C_STSINT_STOPF) == I2C_STSINT_STOPF) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_STOPIE) == I2C_CTRL1_STOPIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_STOPIE) == I2C_CTRL1_STOPIE) ? SET : RESET) != RESET)) { i2c_it_master_complete(drv_i2c, itflags); } @@ -1134,11 +1133,11 @@ static void i2c_master_ev_isr_handler_dma(struct n32_i2c *drv_i2c) uint32_t setmask; uint32_t xfermode; /* Get current IT Flags and IT sources value */ - volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) { /* Clear Not Acknowledge received flag */ drv_i2c->config->Instance->INTCLR = I2C_INTCLR_NAKCLR; @@ -1233,12 +1232,12 @@ static void i2c_master_ev_isr_handler_dma(struct n32_i2c *drv_i2c) static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) { uint32_t tmperror = 0; - volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); /* I2C Bus error interrupt occurred */ if (((((itflags & I2C_STSINT_BSER) == I2C_STSINT_BSER) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) { tmperror |= I2C_STSINT_BSER; @@ -1247,7 +1246,7 @@ static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) /* I2C Over-Run/Under-Run interrupt occurred */ if (((((itflags & I2C_STSINT_OVF) == I2C_STSINT_OVF) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) { tmperror |= I2C_STSINT_OVF; @@ -1256,7 +1255,7 @@ static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) /* I2C Arbitration Loss error interrupt occurred */ if (((((itflags & I2C_STSINT_ABLO) == I2C_STSINT_ABLO) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) { tmperror |= I2C_STSINT_ABLO; @@ -1265,7 +1264,7 @@ static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) /* I2C PEC error interrupt occurred */ if (((((itflags & I2C_STSINT_CRCERR) == I2C_STSINT_CRCERR) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) { tmperror |= I2C_STSINT_CRCERR; @@ -1274,7 +1273,7 @@ static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) /* I2C PEC error interrupt occurred */ if (((((itflags & I2C_STSINT_TMOUT) == I2C_STSINT_TMOUT) ? SET : RESET) != RESET) && - ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) { tmperror |= I2C_STSINT_TMOUT; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h index 2b4a96f569..28c83ec6de 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h @@ -21,34 +21,33 @@ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#define I2C_USING_TX_DMA_FLAG (1U) -#define I2C_USING_RX_DMA_FLAG (1U << 1) +#define I2C_USING_TX_DMA_FLAG (1U) +#define I2C_USING_RX_DMA_FLAG (1U << 1) typedef enum { - I2C_RESET = 0x00U, - I2C_READY = 0x01U, + I2C_RESET = 0x00U, + I2C_READY = 0x01U, I2C_BUSY_TX = 0x02U, I2C_BUSY_RX = 0x03U, } I2C_StateTypeDef; struct n32_i2c_config { - const char *name; - I2C_Module *Instance; - rt_uint32_t timing; - rt_uint32_t timeout; - IRQn_Type evirq_type; - IRQn_Type erirq_type; + const char *name; + I2C_Module *Instance; + rt_uint32_t timing; + rt_uint32_t timeout; + IRQn_Type evirq_type; + IRQn_Type erirq_type; - rt_uint32_t scl_af_width; /* SCL Analog Filter Width */ - rt_uint32_t sda_af_width; /* SDA Analog Filter Width */ - rt_uint32_t df_width; /* Digital Filter Width */ + rt_uint32_t scl_af_width; /* SCL Analog Filter Width */ + rt_uint32_t sda_af_width; /* SDA Analog Filter Width */ + rt_uint32_t df_width; /* Digital Filter Width */ uint32_t periph; void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); @@ -71,16 +70,15 @@ struct n32_i2c { struct hard_i2c_transfer transfer; - struct n32_i2c_config *config; - struct rt_i2c_bus_device i2c_bus; - rt_uint8_t i2c_dma_flag; + struct n32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; + rt_uint8_t i2c_dma_flag; struct rt_completion completion; void (*i2c_isr_callback)(struct n32_i2c *drv_i2c); }; - #ifdef __cplusplus } #endif diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h index 8391d92c64..751cc2b895 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h @@ -17,9 +17,9 @@ typedef enum { DRV_HW_LPTIMER_CTRL_GET_TICK_MAX = 0x20, /* get the maximum tick value */ - DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency */ - DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value */ - DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value */ + DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency */ + DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value */ + DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value */ } drv_hw_lptimer_ctrl_t; #endif /* __DRV_LPTIM_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c index 0d5b769c61..a4339f0079 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c @@ -16,11 +16,11 @@ #ifdef BSP_USING_ONCHIP_RTC #ifndef RTC_BKP_REG1 - #define RTC_BKP_REG1 1U +#define RTC_BKP_REG1 1U #endif //#define DRV_DEBUG -#define LOG_TAG "drv.rtc" +#define LOG_TAG "drv.rtc" #include <drv_log.h> @@ -28,14 +28,14 @@ struct rtc_device_object { - rt_rtc_dev_t rtc_dev; + rt_rtc_dev_t rtc_dev; #ifdef RT_USING_ALARM - struct rt_rtc_wkalarm wkalarm; + struct rt_rtc_wkalarm wkalarm; #endif }; #ifdef RT_USING_ALARM -static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev); +static rt_err_t rtc_alarm_time_set(struct rtc_device_object *p_dev); static int rt_rtc_alarm_init(void); static RTC_AlarmType Alarm_InitStruct = { 0 }; static EXTI_InitType EXTI_InitStructure = { 0 }; @@ -59,25 +59,25 @@ static rt_err_t n32_rtc_get_timeval(struct timeval *tv) { uint32_t SubSeconds; uint32_t Div_Sync; - RTC_TimeType RTC_TimeStruct = {0}; - RTC_DateType RTC_DateStruct = {0}; - struct tm tm_new = {0}; + RTC_TimeType RTC_TimeStruct = { 0 }; + RTC_DateType RTC_DateStruct = { 0 }; + struct tm tm_new = { 0 }; RTC_GetTime(RTC_FORMAT_BIN, &RTC_TimeStruct); RTC_GetDate(RTC_FORMAT_BIN, &RTC_DateStruct); - tm_new.tm_sec = RTC_TimeStruct.Seconds; - tm_new.tm_min = RTC_TimeStruct.Minutes; + tm_new.tm_sec = RTC_TimeStruct.Seconds; + tm_new.tm_min = RTC_TimeStruct.Minutes; tm_new.tm_hour = RTC_TimeStruct.Hours; tm_new.tm_mday = RTC_DateStruct.Date; - tm_new.tm_mon = RTC_DateStruct.Month - 1; + tm_new.tm_mon = RTC_DateStruct.Month - 1; tm_new.tm_year = RTC_DateStruct.Year + 100; tv->tv_sec = timegm(&tm_new); SubSeconds = (uint32_t)(RTC->SUBS); - Div_Sync = (uint32_t)((RTC->PRE) & 0x00007FFFU); + Div_Sync = (uint32_t)((RTC->PRE) & 0x00007FFFU); tv->tv_usec = ((Div_Sync * 1.0) - (SubSeconds * 1.0)) / ((Div_Sync + 1U) * 1.0) * 1000.0 * 1000.0; return RT_EOK; @@ -86,9 +86,9 @@ static rt_err_t n32_rtc_get_timeval(struct timeval *tv) static rt_err_t set_rtc_time_stamp(time_t time_stamp) { - RTC_TimeType RTC_TimeStruct = {0}; - RTC_DateType RTC_DateStruct = {0}; - struct tm tm = {0}; + RTC_TimeType RTC_TimeStruct = { 0 }; + RTC_DateType RTC_DateStruct = { 0 }; + struct tm tm = { 0 }; gmtime_r(&time_stamp, &tm); if (tm.tm_year < 100) @@ -96,12 +96,12 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return -RT_ERROR; } - RTC_TimeStruct.Seconds = tm.tm_sec ; - RTC_TimeStruct.Minutes = tm.tm_min ; - RTC_TimeStruct.Hours = tm.tm_hour; - RTC_DateStruct.Date = tm.tm_mday; - RTC_DateStruct.Month = tm.tm_mon + 1 ; - RTC_DateStruct.Year = tm.tm_year - 100; + RTC_TimeStruct.Seconds = tm.tm_sec; + RTC_TimeStruct.Minutes = tm.tm_min; + RTC_TimeStruct.Hours = tm.tm_hour; + RTC_DateStruct.Date = tm.tm_mday; + RTC_DateStruct.Month = tm.tm_mon + 1; + RTC_DateStruct.Year = tm.tm_year - 100; RTC_DateStruct.WeekDay = tm.tm_wday + 1; if (RTC_ConfigTime(RTC_FORMAT_BIN, &RTC_TimeStruct) == ERROR) @@ -122,8 +122,8 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) static rt_err_t rt_rtc_config(void) { - uint32_t SynchPrediv, AsynchPrediv; - RTC_InitType RTC_InitStructure = { 0 }; + uint32_t SynchPrediv = 0, AsynchPrediv = 0; + RTC_InitType RTC_InitStructure = { 0 }; #if defined(SOC_SERIES_N32H7xx) /* Enable the PWR clock */ @@ -133,24 +133,43 @@ static rt_err_t rt_rtc_config(void) /* Disable RTC clock */ RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLK, DISABLE); +#elif defined(SOC_SERIES_N32H47x_48x) + /* Enable the PWR clock */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR | RCC_APB1_PERIPH_BKP, ENABLE); +#elif defined(SOC_SERIES_N32H49x) + /* Enable the PWR clock */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_PWR | RCC_APB1_PERIPHEN_BKP, ENABLE); +#endif + +#if defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x) + /* Allow access to RTC */ + PWR_BackupAccessEnable(ENABLE); + + /* Disable RTC clock */ + RCC_EnableRtcClk(DISABLE); #endif #if defined(BSP_RTC_USING_LSI) -#if defined(SOC_SERIES_N32H7xx) /* Enable the LSI OSC */ RCC_EnableLsi(ENABLE); if (RCC_WaitLsiStable() == ERROR) { return -RT_ERROR; } + +#if defined(SOC_SERIES_N32H7xx) RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI, RCC_RTCCLK_HSEDIV63); -#endif - SynchPrediv = 0xF9; + + SynchPrediv = 0xF9; AsynchPrediv = 0x7F; +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI); + + SynchPrediv = 0xFB; + AsynchPrediv = 0x7F; +#endif #elif defined(BSP_RTC_USING_LSE) -#if defined(SOC_SERIES_N32H7xx) /* Enable the LSI */ - RCC_EnableLsi(ENABLE); RCC_ConfigLse(RCC_LSE_ENABLE); /****Waite LSE Ready *****/ @@ -159,44 +178,69 @@ static rt_err_t rt_rtc_config(void) return -RT_ERROR; } +#if defined(SOC_SERIES_N32H7xx) RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE, RCC_RTCCLK_HSEDIV_MASK); +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE); #endif - SynchPrediv = 0xFF; + SynchPrediv = 0xFF; AsynchPrediv = 0x7F; #else -#if defined(SOC_SERIES_N32H7xx) /* Enable HSE */ - RCC_EnableLsi(ENABLE); RCC_ConfigHse(RCC_HSE_ENABLE); if (RCC_WaitHseStable() == ERROR) { return -RT_ERROR; } + +#if defined(SOC_SERIES_N32H7xx) RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSEDIV, RCC_RTCCLK_HSEDIV50); -#endif - SynchPrediv = 0x1387; + + SynchPrediv = 0x1387; AsynchPrediv = 0x63; +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128); + + SynchPrediv = 0x3E7; + AsynchPrediv = 0x7C; +#endif #endif #if defined(SOC_SERIES_N32H7xx) /* Enable the RTC Clock */ RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLK, ENABLE); RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLKLP, ENABLE); +#endif RCC_EnableRtcClk(ENABLE); - if (RTC_WaitForSynchro() == ERROR) + /* Wait for RTC register synchronization */ + rt_uint32_t sync_try; + rt_bool_t synced = RT_FALSE; + + for (sync_try = 0; sync_try < 3; sync_try++) { + if (RTC_WaitForSynchro() == SUCCESS) + { + synced = RT_TRUE; + break; + } + + LOG_W("RTC sync not ready (try %d/3)", sync_try + 1); + } + + if (!synced) + { + LOG_E("RTC sync timeout, RTC may be unusable."); return -RT_ERROR; } -#endif if (RTC_BKUP_Read(RTC_BKP_REG1) != BKUP_REG_DATA) { LOG_I("RTC hasn't been configured, please use <date> command to config."); RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; - RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; - RTC_InitStructure.RTC_HourFormat = RTC_24HOUR_FORMAT; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_24HOUR_FORMAT; if (RTC_Init(&RTC_InitStructure) == ERROR) { @@ -225,7 +269,7 @@ static rt_err_t n32_rtc_get_secs(time_t *sec) struct timeval tv; n32_rtc_get_timeval(&tv); - *(time_t *) sec = tv.tv_sec; + *(time_t *)sec = tv.tv_sec; LOG_D("RTC: get rtc_time %d", *sec); return RT_EOK; @@ -268,12 +312,12 @@ static rt_err_t n32_rtc_set_alarm(struct rt_rtc_wkalarm *alarm) LOG_D("RT_DEVICE_CTRL_RTC_SET_ALARM"); if (alarm != RT_NULL) { - rtc_device.wkalarm.enable = alarm->enable; + rtc_device.wkalarm.enable = alarm->enable; rtc_device.wkalarm.tm_hour = alarm->tm_hour; - rtc_device.wkalarm.tm_min = alarm->tm_min; - rtc_device.wkalarm.tm_sec = alarm->tm_sec; + rtc_device.wkalarm.tm_min = alarm->tm_min; + rtc_device.wkalarm.tm_sec = alarm->tm_sec; rtc_device.wkalarm.tm_mday = alarm->tm_mday; - rtc_device.wkalarm.tm_mon = alarm->tm_mon; + rtc_device.wkalarm.tm_mon = alarm->tm_mon; rtc_device.wkalarm.tm_year = alarm->tm_year; rtc_alarm_time_set(&rtc_device); } @@ -292,8 +336,7 @@ static rt_err_t n32_rtc_set_alarm(struct rt_rtc_wkalarm *alarm) } -static const struct rt_rtc_ops n32_rtc_ops = -{ +static const struct rt_rtc_ops n32_rtc_ops = { n32_rtc_init, n32_rtc_get_secs, n32_rtc_set_secs, @@ -304,7 +347,6 @@ static const struct rt_rtc_ops n32_rtc_ops = }; - #ifdef RT_USING_ALARM void rt_rtc_alarm_enable(void) { @@ -324,23 +366,26 @@ void rt_rtc_alarm_enable(void) Alarm_InitStruct.AlarmTime.Minutes, Alarm_InitStruct.AlarmTime.Seconds); - RTC_ClrIntPendingBit(RTC_INT_ALRA); EXTI_ClrITPendBit(EXTI_LINE17); EXTI_InitStruct(&EXTI_InitStructure); -#if defined(SOC_SERIES_N32H7xx) - EXTI_InitStructure.EXTI_Line = EXTI_LINE17; -#endif - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Line = EXTI_LINE17; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_InitPeripheral(&EXTI_InitStructure); NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + +#if defined(SOC_SERIES_N32H7xx) NVIC_SetPriority(RTC_ALARM_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x02, 0)); NVIC_EnableIRQ(RTC_ALARM_IRQn); +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) + NVIC_SetPriority(RTCAlarm_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x02, 0)); + NVIC_EnableIRQ(RTCAlarm_IRQn); +#endif } void rt_rtc_alarm_disable(void) @@ -348,15 +393,18 @@ void rt_rtc_alarm_disable(void) /* Disable the AlarmX */ RTC_EnableAlarm(RTC_A_ALARM, DISABLE); + /* Disable EXTI Line */ EXTI_InitStructure.EXTI_LineCmd = DISABLE; -#if defined(SOC_SERIES_N32H7xx) - EXTI_InitStructure.EXTI_Line = EXTI_LINE17; + EXTI_InitStructure.EXTI_Line = EXTI_LINE17; EXTI_InitPeripheral(&EXTI_InitStructure); EXTI_ClrITPendBit(EXTI_LINE17); -#endif +#if defined(SOC_SERIES_N32H7xx) NVIC_DisableIRQ(RTC_ALARM_IRQn); +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) + NVIC_DisableIRQ(RTCAlarm_IRQn); +#endif } static int rt_rtc_alarm_init(void) @@ -364,21 +412,21 @@ static int rt_rtc_alarm_init(void) return RT_EOK; } -static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev) +static rt_err_t rtc_alarm_time_set(struct rtc_device_object *p_dev) { if (p_dev->wkalarm.enable) { /* Disable the AlarmX */ RTC_EnableAlarm(RTC_A_ALARM, DISABLE); - Alarm_InitStruct.AlarmTime.Hours = p_dev->wkalarm.tm_hour; + Alarm_InitStruct.AlarmTime.Hours = p_dev->wkalarm.tm_hour; Alarm_InitStruct.AlarmTime.Minutes = p_dev->wkalarm.tm_min; Alarm_InitStruct.AlarmTime.Seconds = p_dev->wkalarm.tm_sec; - Alarm_InitStruct.DateWeekValue = p_dev->wkalarm.tm_mday; + Alarm_InitStruct.DateWeekValue = p_dev->wkalarm.tm_mday; - Alarm_InitStruct.AlarmTime.H12 = RTC_AM_H12; - Alarm_InitStruct.DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; - Alarm_InitStruct.AlarmMask = RTC_ALARMMASK_NONE; + Alarm_InitStruct.AlarmTime.H12 = RTC_AM_H12; + Alarm_InitStruct.DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + Alarm_InitStruct.AlarmMask = RTC_ALARMMASK_NONE; LOG_D("alarm set:%d:%d:%d", Alarm_InitStruct.AlarmTime.Hours, Alarm_InitStruct.AlarmTime.Minutes, @@ -389,14 +437,16 @@ static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev) return RT_EOK; } - +#if defined(SOC_SERIES_N32H7xx) void RTC_ALARM_IRQHandler(void) +#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) +void RTCAlarm_IRQHandler(void) +#endif { rt_interrupt_enter(); -#if defined(SOC_SERIES_N32H7xx) + /* Clear EXTI Line Pend Bit */ EXTI_ClrITPendBit(EXTI_LINE17); -#endif if (RTC_GetITStatus(RTC_INT_ALRA) != RESET) { diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.c new file mode 100644 index 0000000000..20dd26ddb9 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.c @@ -0,0 +1,909 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-07-10 Claude N32 SDMMC driver with rt_mmcsd_host_ops, + * SDMMC1/SDMMC2 dual-instance support. + * + * Low-level SDHOST ops (request/set_iocfg/get_card_status/enable_sdio_irq). + * Data transfer: configurable CPU FIFO polling or SDMA. + * INTSTS.CMDC unreliable → poll CMDINHC. + */ + +#include "drv_sdmmc.h" +#include "n32h7xx_rcc.h" +#include "n32h7xx_pwr.h" +#include "n32h7xx_gpio.h" +#include <drivers/dev_mmcsd_core.h> +#include <drivers/dev_sdio.h> + +#define DRV_DBG_TAG "drv.sdmmc" +#define DRV_DBG_LVL DBG_INFO +#include <rtdbg.h> + +#ifdef RT_USING_SDIO + +#define N32_SDIO_CMD_TIMEOUT_MS 100U +#define N32_SDIO_DATA_TIMEOUT_MS 2000U +#define N32_SDIO_BUSY_TIMEOUT_MS 1000U + +/* ═══════════════════════════════════════════════════════════════════════ + * Instance selection — matches STM32 convention: BSP_USING_SDIOx + * ═══════════════════════════════════════════════════════════════════ */ + +#if defined(BSP_USING_SDIO1) && defined(BSP_USING_SDIO2) +#error "Only one SDIO instance supported per configuration" +#endif + +#if defined(BSP_USING_SDIO1) + +static struct n32_sdio_config sdio_cfg = { + .sdhost = SDHOST1, + .sdmmc = SDMMC1, + .irqn = SDMMC1_IRQn, + .clkfb_val = SDMMC1_CLKFB, + .pwrctrl_val = HSC1_SDMMC1_PWRCTRL, + .lpclk_en = RCC_AXI_PERIPHEN_M7_SDMMC1LP, + .periphrst_val = (RCC_AXI_PERIPHRST_SDMMC1 | RCC_AXI_PERIPHRST_SDHOST1), + .name = "sd0", +}; +#define SDMMC_ISR SDMMC1_IRQHandler +#define SDMMC_ENABLE_CLK_FN RCC_EnableAXIPeriphClk1 +#define SDMMC_ENABLE_RST_FN RCC_EnableAXIPeriphReset1 + +#elif defined(BSP_USING_SDIO2) + +static struct n32_sdio_config sdio_cfg = { + .sdhost = SDHOST2, + .sdmmc = SDMMC2, + .irqn = SDMMC2_IRQn, + .clkfb_val = SDMMC2_CLKFB, + .pwrctrl_val = HSC2_SDMMC2_PWRCTRL, + .lpclk_en = RCC_AHB1_PERIPHEN_M7_SDMMC2LP, + .periphrst_val = (RCC_AHB1_PERIPHRST_SDMMC2 | RCC_AHB1_PERIPHRST_SDHOST2), + .name = "sd0", +}; +#define SDMMC_ISR SDMMC2_IRQHandler +#define SDMMC_ENABLE_CLK_FN RCC_EnableAHB1PeriphClk1 +#define SDMMC_ENABLE_RST_FN RCC_EnableAHB1PeriphReset1 + +#else +#error "Define BSP_USING_SDIO1 or BSP_USING_SDIO2" +#endif + +/* ═══════════════════════════════════════════════════════════════════════ + * Helpers + * ═══════════════════════════════════════════════════════════════════════ */ + +/* RT-Thread → N32 response type mapping. + * RT-Thread uses bits [0:3] of flags, N32 uses CARD_ResponseType enum. */ +static SDMMC_CardRspType _map_resp_type(struct rt_mmcsd_cmd *cmd) +{ + switch (resp_type(cmd)) + { + case RESP_NONE: + return CARD_ResponseTypeNone; + case RESP_R1: + return CARD_ResponseTypeR1; + case RESP_R1B: + return CARD_ResponseTypeR1b; + case RESP_R2: + return CARD_ResponseTypeR2; + case RESP_R3: + return CARD_ResponseTypeR3; + case RESP_R4: + return CARD_ResponseTypeR4; + case RESP_R6: + return CARD_ResponseTypeR6; + case RESP_R7: + return CARD_ResponseTypeR7; + case RESP_R5: + return CARD_ResponseTypeR5; + default: + return CARD_ResponseTypeR1; + } +} + +/* ── R2 response normalisation ─────────────────────────────────────── + * N32 SDHOST stores R2 byte-shifted; shift 8 bits left to match + * the SDHCI layout expected by mmcsd_decode_cid / mmcsd_decode_csd. */ +static void _fixup_r2_resp(SDHOST_Module *sdhost, rt_uint32_t resp[4]) +{ + rt_uint32_t r0 = sdhost->CMDRSP0; + rt_uint32_t r1 = sdhost->CMDRSP1; + rt_uint32_t r2 = sdhost->CMDRSP2; + rt_uint32_t r3 = sdhost->CMDRSP3; + + /* N32 numbers R2 words from least to most significant, while + * RT-Thread expects resp[0] to hold bits 127:96. */ + resp[0] = (r3 << 8U) | (r2 >> 24U); + resp[1] = (r2 << 8U) | (r1 >> 24U); + resp[2] = (r1 << 8U) | (r0 >> 24U); + resp[3] = r0 << 8U; +} + +static rt_bool_t _wait_present_clear(SDHOST_Module *sdhost, + rt_uint32_t mask, + rt_uint32_t timeout_ms) +{ + rt_tick_t start = rt_tick_get(); + rt_tick_t timeout = rt_tick_from_millisecond((rt_int32_t)timeout_ms); + + while (sdhost->PRESTS & mask) + { + if ((rt_tick_get() - start) >= timeout) + { + return RT_FALSE; + } + } + + return RT_TRUE; +} + +static rt_bool_t _wait_data_status(SDHOST_Module *sdhost, + rt_uint32_t ready_mask, + rt_uint32_t timeout_ms, + rt_uint32_t *status) +{ + rt_tick_t start = rt_tick_get(); + rt_tick_t timeout = rt_tick_from_millisecond((rt_int32_t)timeout_ms); + + do + { + *status = sdhost->INTSTS; + if (*status & (ready_mask | SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + return RT_TRUE; + } + } while ((rt_tick_get() - start) < timeout); + + return RT_FALSE; +} + +#ifdef BSP_USING_SDIO_SDMA +static rt_bool_t _dcache_is_enabled(void) +{ +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + return (SCB->CCR & SCB_CCR_DC_Msk) != 0U ? RT_TRUE : RT_FALSE; +#else + return RT_FALSE; +#endif +} + +static void _config_sdma_boundary(SDHOST_Module *sdhost, + const void *buffer, + rt_uint32_t length) +{ + rt_uint32_t address = (rt_uint32_t)buffer; + SDHOST_SDMA_Buffer_Size size; + + if (length + (address % 0x1000U) <= 0x1000U) + { + size = SDHOST_SDMABUFFERSIZE_4KB; + } + else if (length + (address % 0x2000U) <= 0x2000U) + { + size = SDHOST_SDMABUFFERSIZE_8KB; + } + else if (length + (address % 0x4000U) <= 0x4000U) + { + size = SDHOST_SDMABUFFERSIZE_16KB; + } + else if (length + (address % 0x8000U) <= 0x8000U) + { + size = SDHOST_SDMABUFFERSIZE_32KB; + } + else if (length + (address % 0x10000U) <= 0x10000U) + { + size = SDHOST_SDMABUFFERSIZE_64KB; + } + else if (length + (address % 0x20000U) <= 0x20000U) + { + size = SDHOST_SDMABUFFERSIZE_128KB; + } + else if (length + (address % 0x40000U) <= 0x40000U) + { + size = SDHOST_SDMABUFFERSIZE_256KB; + } + else + { + size = SDHOST_SDMABUFFERSIZE_512KB; + } + + SDMMC_ConfigSDMABufferSize(sdhost, size); +} +#endif + +/* ═══════════════════════════════════════════════════════════════════════ + * Hardware setup (called once at host creation) + * ═══════════════════════════════════════════════════════════════════════ */ + +static int _hw_setup(struct n32_sdio *sdio) +{ + const struct n32_sdio_config *c = &sdio->cfg; + int i; + + /* 1. Power enable */ + PWR_MoudlePowerEnable(c->pwrctrl_val, ENABLE); + + /* 2. LP clock enable */ + SDMMC_ENABLE_CLK_FN(c->lpclk_en, ENABLE); + + /* 3. Peripheral reset (de-assert) */ + SDMMC_ENABLE_RST_FN(c->periphrst_val); + + /* 4. Clock-feedback select */ + AFIO_SDMMCClkSel(c->clkfb_val, ENABLE); + + /* 6. SDMMC wrapper configuration */ + { + SDMMC_WrapperType w; + SDMMC_StructWrapperInit(&w); + w.MaxBlockLen = SDMMC_MAXBLOCKLEN_512B; + w.SDBaseCLKFreq = 25; + w.TimeOutUnit = SDMMC_TIMEOUTCLKUNIT_KHZ; + w.TuningCNT = 0x20; + w.WKUPSignalMode = SDMMC_ASYNCWKUP; + w.SPIBlockMode = SDMMC_SPIBLOCKMODEUNSUPPORT; + w.SPIMode = SDMMC_SPIMODEUNSUPPORT; + w.DDR50 = SDMMC_DDR50SUPPORT; + w.SDR104 = SDMMC_SDR104SUPPORT; + w.SDR50 = SDMMC_SDR50SUPPORT; + w.SlotType = SDMMC_SDTYPE; + w.AsyncInt = SDMMC_ASYNCINTSUPPORT; + w.Suspend_Resume = SDMMC_SUSRESUNSUPPORT; + w.SDMA = SDMMC_SDMASUPPORT; + w.HS = SDMMC_HSSUPPORT; + w.ADMA2 = SDMMC_ADMA2SUPPORT; + w.Embedded_8bit = SDMMC_EMBEDDEDUNSUPPORT; + w.UseTuningSDR50 = SDMMC_SDR50TUNING; + w.DSSDCLKFreq = 0x04; + w.INITSDCLKFreq = 0x00; + w.SDR12SDCLKFreq = 0x04; + w.HSSDCLKFreq = 0x02; + w.SDR50SDCLKFreq = 0x01; + w.SDR25SDCLKFreq = 0x02; + w.SDR104SDCLKFreq = 0x00; + w.DDR50SDCLKFreq = 0x02; + SDMMC_WrapperConfig(c->sdmmc, &w); + } + + /* 7. Card detect — poll with timeout */ + SDMMC_ConfigCardDetectSignal(c->sdhost, + SDMMC_CARDDETECT_TEST, + SDMMC_CARDTESTLEVEL_HIGH); + + for (i = 0; + SDMMC_GetPresentFlagStatus(c->sdhost, SDHOST_CardInsertedFlag) != SET && i < 1000; + i++) + { + rt_thread_mdelay(1); + } + if (i >= 1000) + { + LOG_E("%s: no card detected", c->name); + return -RT_ERROR; + } + LOG_D("%s: card detected", c->name); + + /* 8. Power on + init clock (400 kHz identification) */ + SDMMC_EnablePower(c->sdhost, ENABLE); + { + uint32_t ps; + if (((SD_XIN_CLK % 400000U) != 0) || ((SD_XIN_CLK / 400000U) % 2 != 0)) + { + ps = SD_XIN_CLK / 400000U / 2 + 1; + } + else + { + ps = SD_XIN_CLK / 400000U / 2; + } + SDMMC_SetSdClock(c->sdhost, DISABLE, ps); + } + + /* Status bits must be enabled even when signal interrupts are disabled. */ + SDMMC_EnableFlagStatus(c->sdhost, SDHOST_AllInterruptFlags, ENABLE); + + LOG_I("%s: hw init done, data path %s", c->name, +#ifdef BSP_USING_SDIO_SDMA + "SDMA"); +#else + "PIO"); +#endif + return RT_EOK; +} + +/* ═══════════════════════════════════════════════════════════════════════ + * rt_mmcsd_host_ops + * ═══════════════════════════════════════════════════════════════════════ */ + +/* ── request() ─────────────────────────────────────────────────────── */ + +static void n32_sdio_request(struct rt_mmcsd_host *host, + struct rt_mmcsd_req *req) +{ + struct n32_sdio *sdio = host->private_data; + SDHOST_Module *sdh = sdio->cfg.sdhost; + struct rt_mmcsd_cmd *cmd = req->cmd; + struct rt_mmcsd_data *data; + SDMMC_CMD sc; + SDHOST_TMODE_struct tm; +#ifdef BSP_USING_SDIO_SDMA + rt_uint32_t total_bytes; +#endif + + RT_ASSERT(cmd != RT_NULL); + + /* ── N32 SDHOST quirks ───────────────────────────────────────── + * CMD5: memory cards return bogus R4 → skip init_sdio() path. */ + if (cmd->cmd_code == SD_IO_SEND_OP_COND) + { + cmd->err = -RT_ERROR; + mmcsd_req_complete(host); + return; + } + + data = cmd->data; + cmd->err = RT_EOK; + if (data != RT_NULL) + { + data->err = RT_EOK; + } + + rt_memset(&sc, 0, sizeof(sc)); + SDMMC_TModeStructInit(&tm); + + /* Do not let status from the previous transaction poison this request. */ + SDMMC_ClrFlag(sdh, SDHOST_CommandFlag | SDHOST_DataFlag | + SDHOST_DmaErrorFlag | SDHOST_DmaCompleteFlag); + + /* ── Populate N32 command descriptor ─────────────────────── */ + sc.index = cmd->cmd_code; + sc.argument = cmd->arg; + sc.type = CARD_CommandTypeNormal; + sc.responseType = _map_resp_type(cmd); + sc.flags = 0; + sc.responseErrorFlags = 0; + + /* ── Data transfer setup ─────────────────────────────────── */ + if (data != RT_NULL) + { + sc.flags |= SDHOST_DataPresentFlag; + +#ifdef BSP_USING_SDIO_SDMA + tm.DMAE = SDHOST_TMODE_DMAENABLE; +#else + tm.DMAE = SDHOST_TMODE_DMADISABLE; +#endif + tm.DATDIR = (data->flags & DATA_DIR_READ) + ? SDHOST_TMODE_DATDIR_READ + : SDHOST_TMODE_DATDIR_WRITE; + tm.BCNTE = (data->blks > 1) + ? SDHOST_TMODE_BLOCKCNTENABLE + : SDHOST_TMODE_BLOCKCNTDISABLE; + tm.BLKSEL = (data->blks > 1) + ? SDHOST_TMODE_MULTIBLK + : SDHOST_TMODE_SINGLEBLK; + /* Auto CMD12 disabled — driver sends CMD12 manually in _out */ + tm.ACMDE = SDHOST_TMODE_NOACMDEN; + + sdh->BLKCFG = (sdh->BLKCFG & ~(SDHOST_BLKCFG_CNT | SDHOST_BLKCFG_SIZE)) | ((data->blks << SDHOST_BLOCK_COUNT_OFFSET) & SDHOST_BLKCFG_CNT) | (data->blksize & SDHOST_BLKCFG_SIZE); + +#ifdef BSP_USING_SDIO_SDMA + total_bytes = data->blks * data->blksize; + + if ((((rt_uint32_t)data->buf) & 3U) != 0U) + { + data->err = -RT_EINVAL; + goto _out; + } + + _config_sdma_boundary(sdh, data->buf, total_bytes); + + /* ── SDMA: cache maintenance ──────────────────────────── */ +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if (_dcache_is_enabled() && (data->flags & DATA_DIR_READ)) + { + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)data->buf, + (int32_t)total_bytes); + } + else if (_dcache_is_enabled()) + { + SCB_CleanDCache_by_Addr((uint32_t *)data->buf, + (int32_t)total_bytes); + } +#endif + /* ── SDMA: system address + DMA mode ──────────────────── */ + sdh->DSADD = (uint32_t)(data->buf); + sdh->CTRL1 &= ~SDHOST_CTRL1_DMASEL; /* SDMA mode (DMASEL=0) */ +#endif + } + + /* ── Fire command ─────────────────────────────────────────── */ + SDMMC_SendCommand(sdh, &sc, &tm); + + /* ── Wait command completion (poll CMDINHC — INTSTS.CMDC unreliable) ── */ + if (!_wait_present_clear(sdh, SDHOST_CommandInhibitFlag, + N32_SDIO_CMD_TIMEOUT_MS)) + { + cmd->err = -RT_ETIMEOUT; + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_CMDLINE); + goto _out; + } + + /* ── Check hardware errors ────────────────────────────────── */ + { + uint32_t ints = sdh->INTSTS; + if (ints & SDHOST_CommandErrorFlag) + { + sdh->INTSTS = (ints & SDHOST_CommandErrorFlag); + cmd->err = (ints & SDHOST_CommandTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_CMDLINE); + goto _out; + } + } + + /* ── Read response ────────────────────────────────────────── */ + if (sc.responseType == CARD_ResponseTypeR2) + { + _fixup_r2_resp(sdh, cmd->resp); + } + else if (sc.responseType != CARD_ResponseTypeNone) + { + cmd->resp[0] = sdh->CMDRSP0; + } + SDMMC_ClrFlag(sdh, SDHOST_CommandFlag); + + if (data == RT_NULL && sc.responseType == CARD_ResponseTypeR1b && + !_wait_present_clear(sdh, SDHOST_DataLineActiveFlag, + N32_SDIO_BUSY_TIMEOUT_MS)) + { + cmd->err = -RT_ETIMEOUT; + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_DATALINE); + goto _out; + } + + /* ── Data transfer ───────────────────────────────────────── */ + if (data != RT_NULL) + { +#ifdef BSP_USING_SDIO_SDMA + /* ── SDMA path ────────────────────────────────────────── */ + volatile uint32_t to; + uint32_t ints; + uint32_t sdma_addr; + + /* Poll for TC or error (HAL-style loop with DSADD re-write) */ + to = 0x800000U; + while (1) + { + ints = sdh->INTSTS; + + if (ints & SDHOST_DmaCompleteFlag) + { + sdh->INTSTS = SDHOST_DmaCompleteFlag; + sdma_addr = sdh->DSADD; + sdh->DSADD = sdma_addr; + } + + if (ints & (SDHOST_DataCompleteFlag | SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + break; + } + + if (--to == 0) + { + data->err = -RT_ETIMEOUT; + goto _data_error; + } + } + + if (ints & (SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + LOG_E("sdma cmd=%u failed: intsts=0x%08x prests=0x%08x dsadd=0x%08x", + cmd->cmd_code, ints, sdh->PRESTS, sdh->DSADD); + sdh->INTSTS = (ints & (SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)); + data->err = (ints & SDHOST_DataTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + goto _data_error; + } + + sdh->INTSTS = SDHOST_DataCompleteFlag | SDHOST_DmaCompleteFlag; + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if (_dcache_is_enabled() && (data->flags & DATA_DIR_READ)) + { + SCB_InvalidateDCache_by_Addr((uint32_t *)data->buf, + (int32_t)total_bytes); + } +#endif +#else + /* ── CPU FIFO path ────────────────────────────────────── */ + rt_uint32_t block; + rt_uint32_t i; + rt_uint32_t words_per_block; + uint32_t ints; + + if ((data->blksize & 3U) != 0U) + { + data->err = -RT_EINVAL; + goto _data_error; + } + words_per_block = data->blksize / 4U; + + if (data->flags & DATA_DIR_READ) + { + rt_uint32_t *dst = (rt_uint32_t *)data->buf; + for (block = 0; block < data->blks; block++) + { + if (!_wait_data_status(sdh, SDHOST_BufferReadReadyFlag, + N32_SDIO_DATA_TIMEOUT_MS, &ints)) + { + data->err = -RT_ETIMEOUT; + goto _data_error; + } + if (ints & (SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + data->err = (ints & SDHOST_DataTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + goto _data_error; + } + + /* One BUFRRDY event makes one complete block available. */ + SDMMC_ClrFlag(sdh, SDHOST_BufferReadReadyFlag); + for (i = 0; i < words_per_block; i++) + { + *dst++ = SDMMC_ReadData(sdh); + } + } + } + else + { + const rt_uint32_t *src = (const rt_uint32_t *)data->buf; + for (block = 0; block < data->blks; block++) + { + if (!_wait_data_status(sdh, SDHOST_BufferWriteReadyFlag, + N32_SDIO_DATA_TIMEOUT_MS, &ints)) + { + data->err = -RT_ETIMEOUT; + goto _data_error; + } + if (ints & (SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + data->err = (ints & SDHOST_DataTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + goto _data_error; + } + + /* One BUFWRDY event accepts one complete block. */ + SDMMC_ClrFlag(sdh, SDHOST_BufferWriteReadyFlag); + for (i = 0; i < words_per_block; i++) + { + SDMMC_WriteData(sdh, *src++); + } + } + } + + if (!_wait_data_status(sdh, SDHOST_DataCompleteFlag, + N32_SDIO_DATA_TIMEOUT_MS, &ints)) + { + data->err = -RT_ETIMEOUT; + goto _data_error; + } + if (ints & (SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag)) + { + data->err = (ints & SDHOST_DataTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + goto _data_error; + } + SDMMC_ClrFlag(sdh, SDHOST_DataFlag | SDHOST_DmaCompleteFlag); +#endif + + /* Multi-block transfers are terminated by CMD12 below. */ + if (req->stop == RT_NULL && + !_wait_present_clear(sdh, SDHOST_DataLineActiveFlag, + N32_SDIO_BUSY_TIMEOUT_MS)) + { + data->err = -RT_ETIMEOUT; + goto _data_error; + } + } + + goto _out; + +_data_error: +#ifdef BSP_USING_SDIO_SDMA + LOG_E("sdma cmd=%u data error=%d: intsts=0x%08x prests=0x%08x dsadd=0x%08x", + cmd->cmd_code, data != RT_NULL ? data->err : 0, + sdh->INTSTS, sdh->PRESTS, sdh->DSADD); +#endif + SDMMC_ClrFlag(sdh, SDHOST_DataFlag | SDHOST_DmaErrorFlag | + SDHOST_DmaCompleteFlag); + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_DATALINE); + +_out: + /* ── Stop command (CMD12) if multi-block ─────────────────── */ + if (req->stop != RT_NULL) + { + SDMMC_CMD sc_s; + SDHOST_TMODE_struct tm_s; + + rt_memset(&sc_s, 0, sizeof(sc_s)); + SDMMC_TModeStructInit(&tm_s); + + sc_s.index = req->stop->cmd_code; + sc_s.argument = req->stop->arg; + sc_s.type = CARD_CommandTypeAbort; + sc_s.responseType = _map_resp_type(req->stop); + sc_s.flags = 0; + sc_s.responseErrorFlags = 0; + + SDMMC_ClrFlag(sdh, SDHOST_CommandFlag); + SDMMC_SendCommand(sdh, &sc_s, &tm_s); + if (!_wait_present_clear(sdh, SDHOST_CommandInhibitFlag, + N32_SDIO_CMD_TIMEOUT_MS)) + { + req->stop->err = -RT_ETIMEOUT; + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_CMDLINE); + } + else + { + uint32_t ints = sdh->INTSTS; + if (ints & SDHOST_CommandErrorFlag) + { + req->stop->err = (ints & SDHOST_CommandTimeoutFlag) + ? -RT_ETIMEOUT + : -RT_ERROR; + } + else + { + if (sc_s.responseType == CARD_ResponseTypeR2) + { + _fixup_r2_resp(sdh, req->stop->resp); + } + else if (sc_s.responseType != CARD_ResponseTypeNone) + { + req->stop->resp[0] = sdh->CMDRSP0; + } + req->stop->err = RT_EOK; + + if (!_wait_present_clear(sdh, SDHOST_DataLineActiveFlag, + N32_SDIO_BUSY_TIMEOUT_MS)) + { + req->stop->err = -RT_ETIMEOUT; + SDMMC_SoftWareReset(sdh, SDHOST_SOFTWARE_DATALINE); + } + } + SDMMC_ClrFlag(sdh, SDHOST_CommandFlag); + } + } + + mmcsd_req_complete(host); +} + +/* ── set_iocfg() ───────────────────────────────────────────────────── */ + +static void n32_sdio_set_iocfg(struct rt_mmcsd_host *host, + struct rt_mmcsd_io_cfg *io_cfg) +{ + struct n32_sdio *sdio = host->private_data; + SDHOST_Module *sdh = sdio->cfg.sdhost; + rt_uint32_t clk = io_cfg->clock; + rt_uint32_t ps; + + /* ── Power mode ─────────────────────────────────────────── */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + SDMMC_EnablePower(sdh, DISABLE); + return; + case MMCSD_POWER_UP: + /* clock stopped during power-up transition */ + SDMMC_EnablePower(sdh, ENABLE); + SDMMC_SetSdClock(sdh, DISABLE, 0); + return; + case MMCSD_POWER_ON: + break; /* proceed to clock + bus width config */ + default: + return; + } + + /* ── Sanity checks ───────────────────────────────────────── */ + if (clk == 0U) + { + LOG_W("%s: zero clock requested, keeping current", sdio->cfg.name); + return; + } + + if (clk > host->freq_max) + { + clk = host->freq_max; + } + + if (clk > (SD_XIN_CLK / 2U)) + { + LOG_W("%s: clk %u > max %u, clamping", + sdio->cfg.name, clk, SD_XIN_CLK / 2U); + clk = SD_XIN_CLK / 2U; + } + + /* SDCLK = SD_XIN_CLK / (2 * prescaler) */ + ps = (SD_XIN_CLK + (2U * clk) - 1U) / (2U * clk); + if (ps < 1U) + { + ps = 1U; + } + + LOG_D("%s: set clk req=%u real=%u ps=%lu bus=%s", + sdio->cfg.name, + clk / 1000U, + (SD_XIN_CLK / (2U * ps)) / 1000U, + ps, + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4-bit" : io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8-bit" + : "1-bit"); + + /* ── Apply clock ─────────────────────────────────────────── */ + SDMMC_SetSdClock(sdh, DISABLE, ps); + + /* ── Bus width ───────────────────────────────────────────── */ + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + SDMMC_ConfigBusWidth(sdh, SDHOST_DataBusWidth4Bit); + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + SDMMC_ConfigBusWidth(sdh, SDHOST_DataBusWidth8Bit); + } + else + { + SDMMC_ConfigBusWidth(sdh, SDHOST_DataBusWidth1Bit); + } +} + +/* ── get_card_status() ─────────────────────────────────────────────── */ + +static rt_int32_t n32_sdio_get_card_status(struct rt_mmcsd_host *host) +{ + struct n32_sdio *sdio = host->private_data; + + if (SDMMC_GetPresentFlagStatus(sdio->cfg.sdhost, + SDHOST_CardInsertedFlag) == SET) + { + return 1; /* card present */ + } + return 0; +} + +/* ── enable_sdio_irq() ─────────────────────────────────────────────── */ + +static void n32_sdio_enable_sdio_irq(struct rt_mmcsd_host *host, + rt_int32_t enable) +{ + struct n32_sdio *sdio = host->private_data; + SDHOST_Module *sdh = sdio->cfg.sdhost; + + if (enable) + { + LOG_D("%s: enable sdio irq", sdio->cfg.name); + SDMMC_ClrFlag(sdh, SDHOST_CardInterruptFlag); + SDMMC_EnableFlagStatus(sdh, SDHOST_CardInterruptFlag, ENABLE); + SDMMC_ConfigInt(sdh, SDHOST_CardInterruptFlag, ENABLE); + NVIC_SetPriority(sdio->cfg.irqn, 1); + NVIC_EnableIRQ(sdio->cfg.irqn); + } + else + { + LOG_D("%s: disable sdio irq", sdio->cfg.name); + NVIC_DisableIRQ(sdio->cfg.irqn); + SDMMC_ConfigInt(sdh, SDHOST_CardInterruptFlag, DISABLE); + SDMMC_EnableFlagStatus(sdh, SDHOST_CardInterruptFlag, DISABLE); + } +} + +/* ═══════════════════════════════════════════════════════════════════════ + * Host ops table + * ═══════════════════════════════════════════════════════════════════════ */ + +static const struct rt_mmcsd_host_ops n32_sdio_ops = { + .request = n32_sdio_request, + .set_iocfg = n32_sdio_set_iocfg, + .get_card_status = n32_sdio_get_card_status, + .enable_sdio_irq = n32_sdio_enable_sdio_irq, + /* tuning / card_busy / signal_voltage_switch → deferred to future */ +}; + +/* ═══════════════════════════════════════════════════════════════════════ + * ISR — forwards to RT-Thread SDIO framework + * ═══════════════════════════════════════════════════════════════════════ */ + +static struct n32_sdio *sdio_inst = RT_NULL; /* singleton for ISR */ + +void SDMMC_ISR(void) +{ + rt_interrupt_enter(); + + if (sdio_inst != RT_NULL && sdio_inst->host != RT_NULL) + { + uint32_t pending = sdio_inst->cfg.sdhost->INTSTS & SDHOST_CardInterruptFlag; + + /* Card interrupt (SDIO I/O) → wake up sdio_irq thread */ + if (pending & SDHOST_INTSTS_CINT) + { + SDMMC_ClrFlag(sdio_inst->cfg.sdhost, SDHOST_CardInterruptFlag); + sdio_irq_wakeup(sdio_inst->host); + } + } + + rt_interrupt_leave(); +} + +/* ═══════════════════════════════════════════════════════════════════════ + * Initialisation + * ═══════════════════════════════════════════════════════════════════════ */ + +int n32_hw_sdio_init(void) +{ + struct n32_sdio *sdio; + struct rt_mmcsd_host *host; + int ret; + + sdio = (struct n32_sdio *)rt_malloc(sizeof(*sdio)); + if (sdio == RT_NULL) + { + LOG_E("malloc n32_sdio failed"); + return -RT_ENOMEM; + } + rt_memset(sdio, 0, sizeof(*sdio)); + sdio->cfg = sdio_cfg; /* copy per-instance config */ + + /* ── Hardware init ──────────────────────────────────────── */ + ret = _hw_setup(sdio); + if (ret != RT_EOK) + { + rt_free(sdio); + return ret; + } + + /* ── Allocate & configure mmcsd host ─────────────────────── */ + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("mmcsd_alloc_host failed"); + rt_free(sdio); + return -RT_ENOMEM; + } + + host->name[0] = 's'; + host->name[1] = 'd'; + host->name[2] = '0'; + host->name[3] = '\0'; + host->ops = &n32_sdio_ops; + host->freq_min = SD_INIT_FREQ; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0x00FFFF80U; /* 1.65V – 3.6V (same as STM32) */ + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 256; + + host->private_data = sdio; + sdio->host = host; + sdio_inst = sdio; /* for ISR */ + + mmcsd_change(host); + + LOG_I("n32 sdio host registered as sd0"); + return RT_EOK; +} +INIT_DEVICE_EXPORT(n32_hw_sdio_init); + +#endif /* RT_USING_SDIO */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.h new file mode 100644 index 0000000000..1b3f93a893 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdmmc.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-07-10 Claude N32 SDMMC driver with rt_mmcsd_host_ops + */ + +#ifndef __DRV_SDMMC_H__ +#define __DRV_SDMMC_H__ + +#include <rtthread.h> +#include "n32h7xx_sdmmc.h" /* BEFORE mmcsd_cmd.h — avoids SWITCH macro clash */ +#include <drivers/mmcsd_host.h> +#include <drivers/mmcsd_cmd.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* ── SDMMC clock frequencies ─────────────────────────────────────────── */ +#define SD_XIN_CLK 100000000U /* SDMMC module base clock (Hz) */ +#define SD_INIT_FREQ 400000U /* Identification mode: 400 kHz */ +#define SD_NORMAL_SPEED_FREQ 25000000U /* Default speed: 25 MHz */ +#define SD_HIGH_SPEED_FREQ 50000000U /* High speed: 50 MHz */ + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ SD_HIGH_SPEED_FREQ +#endif + +/* ── Data buffer ─────────────────────────────────────────────────────── */ +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE 4096 +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN 32 +#endif + +/* ── N32 per-instance descriptor ─────────────────────────────────────── */ +struct n32_sdio_config +{ + SDHOST_Module *sdhost; /* SDHOST register base */ + SDMMC_Module *sdmmc; /* SDMMC wrapper register base */ + IRQn_Type irqn; /* IRQ number */ + uint32_t clkfb_val; /* AFIO clock feedback select */ + uint32_t pwrctrl_val; /* PWR power control bit */ + uint32_t lpclk_en; /* RCC LP clock enable bit */ + uint32_t periphrst_val; /* RCC peripheral reset mask */ + const char *name; /* device name ("sd0") */ +}; + +struct n32_sdio +{ + struct n32_sdio_config cfg; + struct rt_mmcsd_host *host; +}; + +/* ── Public API ──────────────────────────────────────────────────────── */ +int n32_hw_sdio_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SDMMC_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c index 62a747423b..5188b2639a 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c @@ -22,7 +22,7 @@ #include <string.h> //#define DRV_DEBUG -#define LOG_TAG "drv.spi" +#define LOG_TAG "drv.spi" #include <drv_log.h> enum @@ -51,8 +51,7 @@ enum }; -static struct n32_spi_config spi_config[] = -{ +static struct n32_spi_config spi_config[] = { #ifdef BSP_USING_SPI1 SPI1_BUS_CONFIG, #endif @@ -103,10 +102,12 @@ static rt_err_t SPI_DMA_TransmitReceive(struct n32_spi *spi_drv, uint8_t *pTxDat DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + } - spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; - spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pRxData; + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pRxData; spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = Size; DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); @@ -135,10 +136,12 @@ static rt_err_t SPI_DMA_TransmitReceive(struct n32_spi *spi_drv, uint8_t *pTxDat DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + } - spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; - spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pTxData; + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pTxData; spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = Size; DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); @@ -172,7 +175,9 @@ static rt_err_t SPI_DMA_TransmitReceive(struct n32_spi *spi_drv, uint8_t *pTxDat /* Check if the SPI is already enabled */ if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } return RT_EOK; } @@ -182,7 +187,7 @@ static rt_err_t SPI_DMA_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16 RT_ASSERT(spi_drv != RT_NULL); if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) { /* Disable the sFLASH_SPI */ SPI_Enable(spi_drv->config->SPIx, DISABLE); @@ -199,10 +204,12 @@ static rt_err_t SPI_DMA_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16 DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + } - spi_drv->dma.RX_DMA_ChInitStr.IntEn = 0U; - spi_drv->dma.RX_DMA_ChInitStr.DstAddr = NULL; + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 0U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = NULL; spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = 0U; DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); @@ -220,10 +227,12 @@ static rt_err_t SPI_DMA_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16 DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + } - spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; - spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pData; + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pData; spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = Size; DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); @@ -250,7 +259,9 @@ static rt_err_t SPI_DMA_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16 /* Check if the SPI is already enabled */ if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } return RT_EOK; } @@ -265,7 +276,7 @@ static rt_err_t SPI_DMA_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_ } if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) { /* Disable the sFLASH_SPI */ SPI_Enable(spi_drv->config->SPIx, DISABLE); @@ -282,10 +293,12 @@ static rt_err_t SPI_DMA_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_ DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + } - spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; - spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pData; + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pData; spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = Size; DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); @@ -313,10 +326,12 @@ static rt_err_t SPI_DMA_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_ DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + { DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + } - spi_drv->dma.TX_DMA_ChInitStr.IntEn = 0U; - spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = NULL; + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 0U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = NULL; spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); @@ -340,7 +355,9 @@ static rt_err_t SPI_DMA_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_ /* Check if the SPI is already enabled */ if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } return RT_EOK; } @@ -360,7 +377,9 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, } if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) { @@ -379,7 +398,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Loop while DAT register in not emplty */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout befor send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -397,7 +416,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait for DATA send has complete */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout after send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -408,7 +427,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait for SPI bus idle */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking BUSY flag timeout in full-duplex mode."); return -RT_ETIMEOUT; @@ -419,7 +438,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait to receive a byte */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking RNE flag timeout after send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -450,7 +469,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Loop while DAT register in not emplty */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout befor send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -468,7 +487,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait for DATA send has complete */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout after send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -479,7 +498,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait for SPI bus idle */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking BUSY flag timeout in full-duplex mode."); return -RT_ETIMEOUT; @@ -490,7 +509,7 @@ static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, /* Wait to receive a byte */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking RNE flag timeout after send data in full-duplex mode."); return -RT_ETIMEOUT; @@ -529,7 +548,7 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S RT_ASSERT(spi_drv != RT_NULL); if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) { /* Disable the sFLASH_SPI */ SPI_Enable(spi_drv->config->SPIx, DISABLE); @@ -541,7 +560,9 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S } if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) @@ -559,7 +580,7 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S /* Loop while DAT register in not emplty */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout."); return -RT_ETIMEOUT; @@ -589,7 +610,7 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S /* Loop while DAT register in not emplty */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Checking TE flag timeout."); return -RT_ETIMEOUT; @@ -606,14 +627,13 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S } else { - } tickstart = rt_tick_get(); /* Wait for DATA send has complete */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("After sending the data, check the TE flag for timeout."); return -RT_ETIMEOUT; @@ -624,7 +644,7 @@ static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t S /* Wait for SPI bus idle */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("After sending the data, check the BUSY flag for timeout."); return -RT_ETIMEOUT; @@ -658,7 +678,7 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz reg_tmp = spi_drv->config->SPIx->STS; (void)reg_tmp; - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("Before receiving data, check the OVER and RNE flags for timeout."); return -RT_ETIMEOUT; @@ -671,7 +691,7 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz } if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) { /* Disable the sFLASH_SPI */ SPI_Enable(spi_drv->config->SPIx, DISABLE); @@ -683,7 +703,9 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz } if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + { SPI_Enable(spi_drv->config->SPIx, ENABLE); + } if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) { @@ -693,7 +715,7 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz /* Wait to receive a byte */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("During receiving data, check the RNE flags for timeout."); return -RT_ETIMEOUT; @@ -715,7 +737,7 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz /* Wait to receive a byte */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("During receiving data, check the RNE flags for timeout."); return -RT_ETIMEOUT; @@ -731,12 +753,11 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz } else { - } if ((spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_RONLY || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX) && - spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX) && + spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) { /* Disable the sFLASH_SPI */ SPI_Enable(spi_drv->config->SPIx, DISABLE); @@ -746,9 +767,10 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz /* Wait to receive a byte */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) { - spi_drv->config->SPIx->DAT; + volatile rt_uint32_t dummy = spi_drv->config->SPIx->DAT; + (void)dummy; - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("After receiving data, check the RNE flags for timeout."); return -RT_ETIMEOUT; @@ -759,7 +781,7 @@ static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Siz /* Wait for SPI bus idle */ while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) { - if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) { LOG_E("After receiving data, check the BUSY flags for timeout."); return -RT_ETIMEOUT; @@ -806,11 +828,11 @@ static rt_err_t n32_spi_init(struct n32_spi *spi_drv, struct rt_spi_configuratio if (cfg->data_width == 8) { - spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_8BITS; + spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_8BITS; } else if (cfg->data_width == 16) { - spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_16BITS; + spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_16BITS; } else { @@ -819,24 +841,24 @@ static rt_err_t n32_spi_init(struct n32_spi *spi_drv, struct rt_spi_configuratio if (cfg->mode & RT_SPI_CPHA) { - spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; } else { - spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; } if (cfg->mode & RT_SPI_CPOL) { - spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; + spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; } else { - spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; + spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; } - spi_drv->SPI_InitStructure.NSS = SPI_NSS_SOFT; - spi_drv->SPI_InitStructure.CRCPoly = 7; + spi_drv->SPI_InitStructure.NSS = SPI_NSS_SOFT; + spi_drv->SPI_InitStructure.CRCPoly = 7; uint32_t SPI_CLOCK = 0UL; @@ -865,45 +887,45 @@ static rt_err_t n32_spi_init(struct n32_spi *spi_drv, struct rt_spi_configuratio if (cfg->max_hz >= SPI_CLOCK / 2) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_2; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_2; } else if (cfg->max_hz >= SPI_CLOCK / 4) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_4; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_4; } else if (cfg->max_hz >= SPI_CLOCK / 8) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_8; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_8; } else if (cfg->max_hz >= SPI_CLOCK / 16) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_16; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_16; } else if (cfg->max_hz >= SPI_CLOCK / 32) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_32; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_32; } else if (cfg->max_hz >= SPI_CLOCK / 64) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_64; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_64; } else if (cfg->max_hz >= SPI_CLOCK / 128) { - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_128; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_128; } else { /* min prescaler 256 */ - spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256; + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256; } if (cfg->mode & RT_SPI_MSB) { - spi_drv->SPI_InitStructure.FirstBit = SPI_FB_MSB; + spi_drv->SPI_InitStructure.FirstBit = SPI_FB_MSB; } else { - spi_drv->SPI_InitStructure.FirstBit = SPI_FB_LSB; + spi_drv->SPI_InitStructure.FirstBit = SPI_FB_LSB; } /* Initializes the SPIx peripheral */ @@ -972,7 +994,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device, RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); - struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); + struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); spi_drv->cfg = configuration; return n32_spi_init(spi_drv, configuration); @@ -981,7 +1003,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device, static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { -#define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ rt_err_t state = RT_EOK; uint32_t tickstart; @@ -994,7 +1016,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(message != RT_NULL); - struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); + struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) { @@ -1063,8 +1085,10 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m rt_memcpy(dma_aligned_buffer, send_buf, send_length); p_txrx_buffer = dma_aligned_buffer; } - if ((SCB->CCR &(uint32_t)SCB_CCR_DC_Msk) != 0U) - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); + if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) != 0U) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); + } #else if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4) && send_buf != RT_NULL) /* aligned with 4 bytes? */ { @@ -1085,7 +1109,8 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) != RESET) { /*clear RX buff*/ - spi_drv->config->SPIx->DAT; + volatile rt_uint32_t dummy = spi_drv->config->SPIx->DAT; + (void)dummy; if ((rt_tick_get() - tickstart) > 1000U) { @@ -1100,7 +1125,8 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) { /*clear RX buff*/ - spi_drv->config->SPIx->DAT; + volatile rt_uint32_t dummy = spi_drv->config->SPIx->DAT; + (void)dummy; SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); if ((rt_tick_get() - tickstart) > 1000U) @@ -1215,8 +1241,10 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m if (recv_buf != RT_NULL) { #if defined(SOC_SERIES_N32H7xx) - if ((SCB->CCR &(uint32_t)SCB_CCR_DC_Msk) != 0U) - rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length); + if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) != 0U) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length); + } #endif /* SOC_SERIES_N32H7xx */ rt_memcpy(recv_buf, p_txrx_buffer, send_length); } @@ -1231,9 +1259,13 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) { if (device->config.mode & RT_SPI_CS_HIGH) + { rt_pin_write(device->cs_pin, PIN_LOW); + } else + { rt_pin_write(device->cs_pin, PIN_HIGH); + } } if (state != RT_EOK) @@ -1243,14 +1275,12 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m return message->length; } -static const struct rt_spi_ops n32_spi_ops = -{ +static const struct rt_spi_ops n32_spi_ops = { .configure = spi_configure, .xfer = spixfer, }; - static int rt_hw_spi_bus_init(void) { rt_err_t result; @@ -1272,29 +1302,29 @@ static int rt_hw_spi_bus_init(void) /* Receive DMA Config */ DMA_ChannelStructInit(&spi_bus_obj[i].dma.RX_DMA_ChInitStr); - spi_bus_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddr = NULL; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = 0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = NULL; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddr = NULL; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = 0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = NULL; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterInterval = 0x0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; - spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = spi_bus_obj[i].config->dma_rx->HsInterface; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = spi_bus_obj[i].config->dma_rx->HsInterface; /* DMA controller must be enabled before initializing the channel */ DMA_ControllerCmd(spi_bus_obj[i].config->dma_rx->Instance, ENABLE); @@ -1326,29 +1356,29 @@ static int rt_hw_spi_bus_init(void) /* SPI_MASTER_Tx_DMA_Channel DMA1 Channel1 configuration ---------------------------------------------*/ DMA_ChannelStructInit(&spi_bus_obj[i].dma.TX_DMA_ChInitStr); - spi_bus_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = NULL; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = NULL; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = NULL; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = NULL; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterInterval = 0x0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; - spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = spi_bus_obj[i].config->dma_tx->HsInterface; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = spi_bus_obj[i].config->dma_tx->HsInterface; /* DMA controller must be enabled before initializing the channel */ DMA_ControllerCmd(spi_bus_obj[i].config->dma_tx->Instance, ENABLE); @@ -1412,12 +1442,12 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, } -#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI1_TX_USING_DMA) || \ - defined(BSP_SPI2_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || \ - defined(BSP_SPI3_RX_USING_DMA) || defined(BSP_SPI3_TX_USING_DMA) || \ - defined(BSP_SPI4_RX_USING_DMA) || defined(BSP_SPI4_TX_USING_DMA) || \ - defined(BSP_SPI5_RX_USING_DMA) || defined(BSP_SPI5_TX_USING_DMA) || \ - defined(BSP_SPI6_RX_USING_DMA) || defined(BSP_SPI6_TX_USING_DMA) || \ +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI1_TX_USING_DMA) || \ + defined(BSP_SPI2_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || \ + defined(BSP_SPI3_RX_USING_DMA) || defined(BSP_SPI3_TX_USING_DMA) || \ + defined(BSP_SPI4_RX_USING_DMA) || defined(BSP_SPI4_TX_USING_DMA) || \ + defined(BSP_SPI5_RX_USING_DMA) || defined(BSP_SPI5_TX_USING_DMA) || \ + defined(BSP_SPI6_RX_USING_DMA) || defined(BSP_SPI6_TX_USING_DMA) || \ defined(BSP_SPI7_RX_USING_DMA) || defined(BSP_SPI7_TX_USING_DMA) static void spi_isr(struct n32_spi *spi_drv) { @@ -1446,12 +1476,12 @@ static void spi_isr(struct n32_spi *spi_drv) } } -#if defined(BSP_SPI1_RX_USING_DMA) || \ - defined(BSP_SPI2_RX_USING_DMA) || \ - defined(BSP_SPI3_RX_USING_DMA) || \ - defined(BSP_SPI4_RX_USING_DMA) || \ - defined(BSP_SPI5_RX_USING_DMA) || \ - defined(BSP_SPI6_RX_USING_DMA) || \ +#if defined(BSP_SPI1_RX_USING_DMA) || \ + defined(BSP_SPI2_RX_USING_DMA) || \ + defined(BSP_SPI3_RX_USING_DMA) || \ + defined(BSP_SPI4_RX_USING_DMA) || \ + defined(BSP_SPI5_RX_USING_DMA) || \ + defined(BSP_SPI6_RX_USING_DMA) || \ defined(BSP_SPI7_RX_USING_DMA) static void spi_rx_dma_isr(struct n32_spi *spi_drv) { @@ -1484,7 +1514,7 @@ static void spi_rx_dma_isr(struct n32_spi *spi_drv) else if (spi_drv->Direct == SPI_Rx) { if (spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER && (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || - spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_RONLY)) + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_RONLY)) { SPI_Enable(spi_drv->config->SPIx, DISABLE); } @@ -1617,7 +1647,6 @@ void SPI2_TX_DMA_IRQHandler(void) #endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) */ - #if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA) void SPI3_IRQHandler(void) { @@ -1656,7 +1685,6 @@ void SPI3_TX_DMA_IRQHandler(void) #endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) */ - #if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA) void SPI4_IRQHandler(void) { @@ -1695,8 +1723,6 @@ void SPI4_TX_DMA_IRQHandler(void) #endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) */ - - #if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA) void SPI5_IRQHandler(void) { @@ -1735,8 +1761,6 @@ void SPI5_TX_DMA_IRQHandler(void) #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) */ - - #if defined(BSP_SPI6_TX_USING_DMA) || defined(BSP_SPI6_RX_USING_DMA) void SPI6_IRQHandler(void) { @@ -1775,7 +1799,6 @@ void SPI6_TX_DMA_IRQHandler(void) #endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) */ - #if defined(BSP_SPI7_TX_USING_DMA) || defined(BSP_SPI7_RX_USING_DMA) void SPI7_IRQHandler(void) { diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h index d34d610bed..073831568b 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h @@ -44,8 +44,8 @@ struct n32_spi_device }; -#define SPI_USING_RX_DMA_FLAG (1<<0) -#define SPI_USING_TX_DMA_FLAG (1<<1) +#define SPI_USING_RX_DMA_FLAG (1 << 0) +#define SPI_USING_TX_DMA_FLAG (1 << 1) typedef enum { diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c index 02ba9b7e5c..62cd26d2b5 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c @@ -12,15 +12,15 @@ #include <board.h> #ifdef RT_USING_PIN - #include <drv_gpio.h> +#include <drv_gpio.h> #endif #ifdef RT_USING_SERIAL - #ifdef RT_USING_SERIAL_V2 - #include <drv_usart_v2.h> - #else - #include <drv_usart.h> - #endif /* RT_USING_SERIAL */ +#ifdef RT_USING_SERIAL_V2 +#include <drv_usart_v2.h> +#else +#include <drv_usart.h> +#endif /* RT_USING_SERIAL */ #endif /* RT_USING_SERIAL_V2 */ #define DBG_TAG "drv_common" @@ -63,7 +63,9 @@ void rt_hw_systick_init(void) _systick_ms = 1000u / RT_TICK_PER_SECOND; if (_systick_ms == 0) + { _systick_ms = 1; + } } void System_Tick_Increase(void) @@ -74,7 +76,9 @@ void System_Tick_Increase(void) uint32_t System_Tick_Get(void) { if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + { System_Tick_Increase(); + } return uwTick; } @@ -89,7 +93,9 @@ void SysTick_Handler(void) rt_interrupt_enter(); if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + { System_Tick_Increase(); + } rt_tick_increase(); diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h index 9c98335468..b92eb7261d 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h @@ -15,7 +15,7 @@ #include <board.h> #include <rtthread.h> #ifdef RT_USING_DEVICE - #include <rtdevice.h> +#include <rtdevice.h> #endif /* RT_USING_DEVICE */ #ifdef __cplusplus diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c index dedb6fd5e3..3e0e97f3da 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c @@ -204,13 +204,13 @@ void rt_hw_console_init(void) USART_DeInit(USARTx); USART_StructInit(&USART_InitStructure); - USART_InitStructure.BaudRate = 115200; - USART_InitStructure.WordLength = USART_WL_8B; - USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.OverSampling = USART_16OVER; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; USART_Init(USARTx, &USART_InitStructure); USART_Enable(USARTx, ENABLE); } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h index 7970318d27..0db697df88 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h @@ -16,8 +16,8 @@ extern "C" { #endif -#define PIN_LOW 0x00 -#define PIN_HIGH 0x01 +#define PIN_LOW 0x00 +#define PIN_HIGH 0x01 #define PIN_MODE_OUTPUT 0x00 #define PIN_MODE_INPUT 0x01 @@ -25,7 +25,7 @@ extern "C" { #define PIN_MODE_INPUT_PULLDOWN 0x03 #define PIN_MODE_OUTPUT_OD 0x04 -#define GET_PIN(PORTx,PIN) (rt_uint64_t)((((rt_uint64_t)GPIO_PIN_##PIN) << 32) | (rt_uint64_t)(rt_ubase_t)GPIO##PORTx) +#define GET_PIN(PORTx, PIN) (rt_uint64_t)((((rt_uint64_t)GPIO_PIN_##PIN) << 32) | (rt_uint64_t)(rt_ubase_t)GPIO##PORTx) void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode); void rt_pin_write(rt_uint64_t pin, rt_uint8_t value); diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/.config b/bsp/n32/n32hxxx/n32h487zgl7-evb/.config index b7be3cf1cf..4d4870d535 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/.config +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/.config @@ -1499,6 +1499,9 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_TX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_FDCAN is not set # end of On-chip Peripheral Drivers # diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx Binary files differindex cac1fa8b02..468240de0e 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/inc/n32h47x_48x_cfg.h b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/inc/n32h47x_48x_cfg.h index 0500cab396..5bed7aa8f8 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/inc/n32h47x_48x_cfg.h +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/inc/n32h47x_48x_cfg.h @@ -15,7 +15,7 @@ extern "C" { /* NTFx CODE START Extern*/ extern void SysTick_Delayms(uint32_t Delayms); -extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); +extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ); extern bool RCC_Configuration(void); extern bool GPIO_Configuration(void); extern bool NVIC_Configuration(void); diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c index 7bd530175b..607700155c 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c @@ -10,44 +10,44 @@ __IO uint32_t mwTick; void SysTick_Delayms(uint32_t Delayms) { uint32_t tickstart = mwTick; - uint32_t wait = Delayms; + uint32_t wait=Delayms; /* Add 1 to guarantee minimum wait */ if (wait < 0xFFFFFFFFU) { - wait += 1; + wait +=1; } while ((mwTick - tickstart) < wait) { } } -/** -*@name DMA_SetPerMemAddr. -*@brief Set peripher address and memory address of DMA -*@param DMAChx (The input parameters must be the following values): -* - DMA1_CH1 -* - DMA1_CH2 -* - DMA1_CH3 -* - DMA1_CH4 -* - DMA1_CH5 -* - DMA1_CH6 -* - DMA1_CH7 -* - DMA1_CH8 -* - DMA2_CH1 -* - DMA2_CH2 -* - DMA2_CH3 -* - DMA2_CH4 -* - DMA2_CH5 -* - DMA2_CH6 -* - DMA2_CH7 -* - DMA2_CH8 -*@param periphAddr peripher address -*@param memAddr memory address -*@param bufSize buff size -*@return status -*/ -void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize) -{ - /* DMAy Channelx TXNUM Configuration */ + /** + *@name DMA_SetPerMemAddr. + *@brief Set peripher address and memory address of DMA + *@param DMAChx (The input parameters must be the following values): + * - DMA1_CH1 + * - DMA1_CH2 + * - DMA1_CH3 + * - DMA1_CH4 + * - DMA1_CH5 + * - DMA1_CH6 + * - DMA1_CH7 + * - DMA1_CH8 + * - DMA2_CH1 + * - DMA2_CH2 + * - DMA2_CH3 + * - DMA2_CH4 + * - DMA2_CH5 + * - DMA2_CH6 + * - DMA2_CH7 + * - DMA2_CH8 + *@param periphAddr peripher address + *@param memAddr memory address + *@param bufSize buff size + *@return status + */ + void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ) + { + /* DMAy Channelx TXNUM Configuration */ /* Write to DMAy Channelx TXNUM */ DMAChx->TXNUM = bufSize; @@ -58,22 +58,22 @@ void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t me /* DMAy Channelx MADDR Configuration */ /* Write to DMAy Channelx MADDR */ DMAChx->MADDR = memAddr; -} -/** -*@name RCC_InitSHRTPLL. -*@brief Initialze the SHRTPLL clock source and multiplication factor. -*@param SHRTPLL_source(SHRTPLL entry clock source): -* - RCC_SHRTPLL_SRC_HSI HSI oscillator clock selected as SHRTPLL clock entry -* - RCC_SHRTPLL_SRC_HSE HSE oscillator clock selected as SHRTPLL clock entry -*@param CLKF(SHRTPLL Multiple coefficient) -*@param CLKR(SHRTPLL division coefficient) -*@param BWTRIM(Bandwidth adjustment) -*@return none: -*note SHRTPLL = SHRTPLL_source*(CLKF[25:0]/16384)/(CLKR[5:0] +1)/4 -*/ + } + /** + *@name RCC_InitSHRTPLL. + *@brief Initialze the SHRTPLL clock source and multiplication factor. + *@param SHRTPLL_source(SHRTPLL entry clock source): + * - RCC_SHRTPLL_SRC_HSI HSI oscillator clock selected as SHRTPLL clock entry + * - RCC_SHRTPLL_SRC_HSE HSE oscillator clock selected as SHRTPLL clock entry + *@param CLKF(SHRTPLL Multiple coefficient) + *@param CLKR(SHRTPLL division coefficient) + *@param BWTRIM(Bandwidth adjustment) + *@return none: + *note SHRTPLL = SHRTPLL_source*(CLKF[25:0]/16384)/(CLKR[5:0] +1)/4 + */ void RCC_InitSHRTPLL(uint32_t SHRTPLL_source, uint32_t CLKF, uint32_t CLKR, uint32_t BWTRIM) { - uint32_t temp_value1, temp_value2, temp_value3; + uint32_t temp_value1,temp_value2,temp_value3; /* Enable SHRTPLL module power */ @@ -86,8 +86,8 @@ void RCC_InitSHRTPLL(uint32_t SHRTPLL_source, uint32_t CLKF, uint32_t CLKR, uint /* Configure the work mode to normal */ RCC->SHRTPLLCTRL1 &= (~RCC_SHRTPLLMODE_PD); /* Enable Saturation and fraction accumulation function */ - RCC->SHRTPLLCTRL1 |= (RCC_SHRTPLL_SATEN | RCC_SHRTPLL_FRACEN); - + RCC->SHRTPLLCTRL1 |= (RCC_SHRTPLL_SATEN|RCC_SHRTPLL_FRACEN); + /* get the SHRTPLL value */ temp_value1 = RCC->SHRTPLLCTRL1; temp_value2 = RCC->SHRTPLLCTRL2; @@ -103,15 +103,15 @@ void RCC_InitSHRTPLL(uint32_t SHRTPLL_source, uint32_t CLKF, uint32_t CLKR, uint /* Set CLKF[25:0] bits */ temp_value1 |= (uint32_t)CLKF; /* Set CLKR[5:0] bits */ - temp_value2 |= ((uint32_t)CLKR << 26); + temp_value2 |= ((uint32_t)CLKR<<26); /* Set BWTRIM[11:0] bits */ - temp_value3 |= ((uint32_t)BWTRIM << 12); + temp_value3 |= ((uint32_t)BWTRIM<<12); /* Store the new value */ RCC->SHRTPLLCTRL1 = temp_value1; RCC->SHRTPLLCTRL2 = temp_value2; RCC->SHRTPLLCTRL3 = temp_value3; - + /* Reset SHRTPLL */ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPHRST_SHRTPLL); @@ -128,13 +128,13 @@ bool RCC_Configuration(void) { ErrorStatus ClockStatus; RCC_DeInit(); - + RCC_EnableHsi(ENABLE); /* Wait till HSI is ready */ ClockStatus = RCC_WaitHsiStable(); if (ClockStatus != SUCCESS) return false; - - RCC_ConfigPll(RCC_PLL_SRC_HSI, RCC_PLL_PRE_2, RCC_PLL_MUL_60, RCC_PLLOUT_DIV_1); + + RCC_ConfigPll(RCC_PLL_SRC_HSI,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1); /* Enable PLL */ RCC_EnablePll(ENABLE); /* Wait till PLL is ready */ @@ -142,27 +142,27 @@ bool RCC_Configuration(void) RCC_ConfigHclk(RCC_SYSCLK_DIV1); RCC_ConfigPclk2(RCC_HCLK_DIV2); RCC_ConfigPclk1(RCC_HCLK_DIV2); - + /* Disable Prefetch Buffer */ FLASH_PrefetchBufSet(FLASH_PrefetchBuf_DIS); FLASH_iCacheCmd(FLASH_iCache_EN); /* Flash wait state */ FLASH_SetLatency(FLASH_LATENCY_5); - + /*config RNG clock*/ RCC_ConfigTrng1mClk(RCC_TRNG1MCLK_SRC_HSI, RCC_TRNG1MCLK_DIV8); RCC_EnableTrng1mClk(ENABLE); RCC_ConfigRngcClk(RCC_RNGCCLK_SYSCLK_DIV1); /*config TRACE clock*/ RCC_ConfigTraceClk(RCC_TRACECLK_DIV1); - + /* Select PLL as system clock source */ RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL); /* Wait till PLL is used as system clock source */ while (RCC_GetSysclkSrc() != RCC_CFG_SCLKSTS_PLL) ; /* Configure the SysTick to have interrupt in 1ms time basis*/ SysTick_Config(240000); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -175,12 +175,16 @@ bool GPIO_Configuration(void) { GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); - + /* Enable the GPIO clock*/ RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOH, ENABLE); - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); - - + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO,ENABLE); + + + + /*********Initialize USART1 GPIO function *********/ + /********PA9->USART1.TX********/ + /********PA10->USART1.RX********/ /*Initialize AF_PP GPIO */ GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; @@ -188,18 +192,19 @@ bool GPIO_Configuration(void) GPIO_InitStructure.GPIO_Current = GPIO_DS_2mA; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; GPIO_InitStructure.Pin = GPIO_PIN_9; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + /*Initialize input GPIO */ GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; GPIO_InitStructure.Pin = GPIO_PIN_10; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - - GPIO_ConfigPinRemap(0, 0, GPIO_RMP_SWJ_SWD); - - /* NTFx CODE END */ + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + + GPIO_ConfigPinRemap(0,0,GPIO_RMP_SWJ_SWD); + + +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -216,8 +221,8 @@ bool NVIC_Configuration(void) - Lower values gives higher priority */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); - NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(4, 0, 0)); - /* NTFx CODE END */ + NVIC_SetPriority(SysTick_IRQn,NVIC_EncodePriority(4,0,0)); +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -228,7 +233,7 @@ bool NVIC_Configuration(void) */ bool DMA_Configuration(void) { - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -242,24 +247,24 @@ bool USART_Configuration(void) USART_InitType USART_InitStructure; USART_StructInit(&USART_InitStructure); /* Enable USART1 clock */ - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE); - - + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1,ENABLE); + + /*********initialize the USART1************/ USART_DeInit(USART1); USART_InitStructure.BaudRate = 115200; USART_InitStructure.WordLength = USART_WL_8B; USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; - USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - USART_InitStructure.OverSampling = USART_16OVER ; + USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER ; /* Configure USART1 */ USART_Init(USART1, &USART_InitStructure); - - + + /* Enable the USART1 */ USART_Enable(USART1, ENABLE); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig index 011a2a9ce6..c0b5821609 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig @@ -60,6 +60,329 @@ menu "On-chip Peripheral Drivers" endif + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice BSP_RTC_LS_SEL + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + menuconfig BSP_USING_FDCAN + bool "Enable FDCAN (CAN FD)" + default n + select RT_USING_CAN + select RT_CAN_USING_CANFD + select RT_CAN_USING_HDR + if BSP_USING_FDCAN + config BSP_FDCAN_MSG_RAM_WORDS + int "Shared Message RAM size (32-bit words)" + range 1 4480 + default 768 + help + One continuous Message RAM array shared by FDCAN1/2/3. + Enabled instances are packed in instance order using + each instance's configured resource requirement. + + config BSP_USING_FDCAN1 + bool "Enable FDCAN1" + default n + if BSP_USING_FDCAN1 + menu "FDCAN1 resource configuration" + config BSP_FDCAN1_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN1_USING_TDC + config BSP_FDCAN1_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN1_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN1_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN1_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN1_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN1_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN1_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN1_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN1_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + + config BSP_USING_FDCAN2 + bool "Enable FDCAN2" + default n + if BSP_USING_FDCAN2 + menu "FDCAN2 resource configuration" + config BSP_FDCAN2_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN2_USING_TDC + config BSP_FDCAN2_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN2_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN2_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN2_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN2_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN2_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN2_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN2_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN2_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + + config BSP_USING_FDCAN3 + bool "Enable FDCAN3" + default n + if BSP_USING_FDCAN3 + menu "FDCAN3 resource configuration" + config BSP_FDCAN3_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN3_USING_TDC + config BSP_FDCAN3_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN3_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN3_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN3_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN3_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN3_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN3_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN3_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN3_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + endif + source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig" endmenu diff --git a/bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvprojx b/bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvprojx index c5230dbddc..e2aa9ad64c 100644 --- a/bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvprojx +++ b/bsp/n32/n32hxxx/n32h487zgl7-evb/project.uvprojx @@ -337,9 +337,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>N32H488, __CLK_TCK=RT_TICK_PER_SECOND, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, CORE_CM4, __RTTHREAD__, RT_USING_ARMLIBC, RT_USING_LIBC</Define> + <Define>__RTTHREAD__, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, CORE_CM4, RT_USING_ARMLIBC, N32H488, RT_USING_LIBC</Define> <Undefine></Undefine> - <IncludePath>..\libraries\N32_Drivers\drivers;..\..\..\..\components\libc\posix\io\poll;packages\n32h47x_48x_cmsis_driver-latest\device;..\..\..\..\components\finsh;applications;board;.;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\libcpu\arm\common;packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc;board\Cube_Config\USER\inc;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\libc\posix\io\epoll;..\libraries\N32_Drivers\drivers\config;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\libraries\N32_Drivers;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\net\utest;board\ports;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include</IncludePath> + <IncludePath>board;packages\n32h47x_48x_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\eventfd;packages\CMSIS-Core-latest\Include;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;board\ports;..\..\..\..\components\libc\posix\io\poll;packages\n32h47x_48x_std_driver-latest\n32h47x_48x_std_periph_driver\inc;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\net\utest;..\libraries\N32_Drivers\drivers;..\..\..\..\components\drivers\smp_call;applications;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\posix\ipc;board\Cube_Config\USER\inc;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\libraries\N32_Drivers\drivers\config;..\libraries\N32_Drivers;.;..\..\..\..\components\libc\compilers\common\extension</IncludePath> </VariousControls> </Cads> <Aads> diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/.config b/bsp/n32/n32hxxx/n32h497zgl7-evb/.config index c82965c6e3..2d3a0eda5f 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/.config +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/.config @@ -1499,6 +1499,9 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_TX_USING_DMA is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_FDCAN is not set # end of On-chip Peripheral Drivers # diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx Binary files differindex c52178ba3c..e5a1e567ef 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/inc/n32h49x_cfg.h b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/inc/n32h49x_cfg.h index 9145508446..b846e4e837 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/inc/n32h49x_cfg.h +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/inc/n32h49x_cfg.h @@ -22,7 +22,7 @@ extern "C" { /* NTFx CODE START Extern*/ extern void SysTick_Delayms(uint32_t Delayms); -extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); +extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ); extern bool RCC_Configuration(void); extern bool GPIO_Configuration(void); extern bool NVIC_Configuration(void); diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c index 4c50a8abc3..f7d06beb45 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c @@ -10,44 +10,44 @@ __IO uint32_t mwTick; void SysTick_Delayms(uint32_t Delayms) { uint32_t tickstart = mwTick; - uint32_t wait = Delayms; + uint32_t wait=Delayms; /* Add 1 to guarantee minimum wait */ if (wait < 0xFFFFFFFFU) { - wait += 1; + wait +=1; } while ((mwTick - tickstart) < wait) { } } -/** -*@name DMA_SetPerMemAddr. -*@brief Set peripher address and memory address of DMA -*@param DMAChx (The input parameters must be the following values): -* - DMA1_CH1 -* - DMA1_CH2 -* - DMA1_CH3 -* - DMA1_CH4 -* - DMA1_CH5 -* - DMA1_CH6 -* - DMA1_CH7 -* - DMA1_CH8 -* - DMA2_CH1 -* - DMA2_CH2 -* - DMA2_CH3 -* - DMA2_CH4 -* - DMA2_CH5 -* - DMA2_CH6 -* - DMA2_CH7 -* - DMA2_CH8 -*@param periphAddr peripher address -*@param memAddr memory address -*@param bufSize buff size -*@return status -*/ -void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize) -{ - /* DMAy Channelx TXNUM Configuration */ + /** + *@name DMA_SetPerMemAddr. + *@brief Set peripher address and memory address of DMA + *@param DMAChx (The input parameters must be the following values): + * - DMA1_CH1 + * - DMA1_CH2 + * - DMA1_CH3 + * - DMA1_CH4 + * - DMA1_CH5 + * - DMA1_CH6 + * - DMA1_CH7 + * - DMA1_CH8 + * - DMA2_CH1 + * - DMA2_CH2 + * - DMA2_CH3 + * - DMA2_CH4 + * - DMA2_CH5 + * - DMA2_CH6 + * - DMA2_CH7 + * - DMA2_CH8 + *@param periphAddr peripher address + *@param memAddr memory address + *@param bufSize buff size + *@return status + */ + void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ) + { + /* DMAy Channelx TXNUM Configuration */ /* Write to DMAy Channelx TXNUM */ DMAChx->TXNUM = bufSize; @@ -58,7 +58,7 @@ void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t me /* DMAy Channelx MADDR Configuration */ /* Write to DMAy Channelx MADDR */ DMAChx->MADDR = memAddr; -} + } /* NTFx CODE END */ /* NTFx CODE START */ @@ -71,13 +71,13 @@ bool RCC_Configuration(void) { ErrorStatus ClockStatus; RCC_DeInit(); - + RCC_EnableHsi(ENABLE); /* Wait till HSI is ready */ ClockStatus = RCC_WaitHsiStable(); if (ClockStatus != SUCCESS) return false; - - RCC_ConfigPll(RCC_PLL_SRC_HSI, RCC_PLL_PRE_2, RCC_PLL_MUL_60, RCC_PLLOUT_DIV_1); + + RCC_ConfigPll(RCC_PLL_SRC_HSI,RCC_PLL_PRE_2,RCC_PLL_MUL_60,RCC_PLLOUT_DIV_1); /* Enable PLL */ RCC_EnablePll(ENABLE); /* Wait till PLL is ready */ @@ -86,24 +86,24 @@ bool RCC_Configuration(void) RCC_ConfigPclk2(RCC_HCLK_DIV2); RCC_ConfigPclk1(RCC_HCLK_DIV2); RCC_ConfigPeriphClk(RCC_PERIPH_HCLK_DIV1); - + /* Enable Prefetch Buffer */ FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN); /* Flash wait state */ FLASH_SetLatency(FLASH_LATENCY_4); - + /*config RNG clock*/ RCC_ConfigTrng1mClk(RCC_TRNG1MCLK_SRC_HSI, RCC_TRNG1MCLK_DIV8); RCC_EnableTrng1mClk(ENABLE); RCC_ConfigRngcClk(RCC_RNGCCLK_SYSCLK_DIV1); - + /* Select PLL as system clock source */ RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL); /* Wait till PLL is used as system clock source */ while (RCC_GetSysclkSrc() != RCC_CFG_SCLKSTS_PLL) ; /* Configure the SysTick to have interrupt in 1ms time basis*/ SysTick_Config(240000); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -116,13 +116,13 @@ bool GPIO_Configuration(void) { GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); - + /* Enable the GPIO clock*/ RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH | RCC_AHB_PERIPHEN_GPIOA, ENABLE); - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE); - - - + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO,ENABLE); + + + /*********Initialize USART1 GPIO function *********/ /********PA9->USART1.TX********/ /********PA10->USART1.RX********/ @@ -133,19 +133,19 @@ bool GPIO_Configuration(void) GPIO_InitStructure.GPIO_Current = GPIO_DS_2mA; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; GPIO_InitStructure.Pin = GPIO_PIN_9; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + /*Initialize input GPIO */ GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; GPIO_InitStructure.Pin = GPIO_PIN_10; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - - GPIO_ConfigPinRemap(0, 0, GPIO_RMP_SWJ_SWD); - - - /* NTFx CODE END */ + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + + GPIO_ConfigPinRemap(0,0,GPIO_RMP_SWJ_SWD); + + +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -162,8 +162,8 @@ bool NVIC_Configuration(void) - Lower values gives higher priority */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); - NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(4, 15, 0)); - /* NTFx CODE END */ + NVIC_SetPriority(SysTick_IRQn,NVIC_EncodePriority(4,15,0)); +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -174,7 +174,7 @@ bool NVIC_Configuration(void) */ bool DMA_Configuration(void) { - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } /* NTFx CODE START */ @@ -188,24 +188,24 @@ bool USART_Configuration(void) USART_InitType USART_InitStructure; USART_StructInit(&USART_InitStructure); /* Enable USART1 clock */ - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1, ENABLE); - - + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1,ENABLE); + + /*********initialize the USART1************/ USART_DeInit(USART1); USART_InitStructure.BaudRate = 115200; USART_InitStructure.WordLength = USART_WL_8B; USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; - USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - USART_InitStructure.OverSampling = USART_16OVER ; + USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER ; /* Configure USART1 */ USART_Init(USART1, &USART_InitStructure); - - + + /* Enable the USART1 */ USART_Enable(USART1, ENABLE); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig index 011a2a9ce6..5d70700412 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig @@ -60,6 +60,329 @@ menu "On-chip Peripheral Drivers" endif + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice BSP_RTC_LS_SEL + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + menuconfig BSP_USING_FDCAN + bool "Enable FDCAN (CAN FD)" + default n + select RT_USING_CAN + select RT_CAN_USING_CANFD + select RT_CAN_USING_HDR + if BSP_USING_FDCAN + config BSP_FDCAN_MSG_RAM_WORDS + int "Shared Message RAM size (32-bit words)" + range 1 4480 + default 768 + help + One continuous Message RAM array shared by FDCAN1/2/3. + Enabled instances are packed in instance order using + each instance's configured resource requirement. + + config BSP_USING_FDCAN1 + bool "Enable FDCAN1" + default n + if BSP_USING_FDCAN1 + menu "FDCAN1 resource configuration" + config BSP_FDCAN1_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN1_USING_TDC + config BSP_FDCAN1_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN1_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN1_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN1_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN1_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN1_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN1_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN1_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN1_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + + config BSP_USING_FDCAN2 + bool "Enable FDCAN2" + default n + if BSP_USING_FDCAN2 + menu "FDCAN2 resource configuration" + config BSP_FDCAN2_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN2_USING_TDC + config BSP_FDCAN2_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN2_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN2_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN2_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN2_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN2_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN2_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN2_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN2_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + + config BSP_USING_FDCAN3 + bool "Enable FDCAN3" + default n + if BSP_USING_FDCAN3 + menu "FDCAN3 resource configuration" + config BSP_FDCAN3_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN3_USING_TDC + config BSP_FDCAN3_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN3_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN3_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN3_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN3_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN3_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN3_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN3_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN3_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + endif + source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig" endmenu diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvoptx b/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvoptx index 32182abdec..a3c52beefe 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvoptx @@ -176,7 +176,7 @@ <Group> <GroupName>Applications</GroupName> - <tvExp>1</tvExp> + <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> <RteFlg>0</RteFlg> diff --git a/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvprojx b/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvprojx index cb3c0c32af..6af6d28bb0 100644 --- a/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvprojx +++ b/bsp/n32/n32hxxx/n32h497zgl7-evb/project.uvprojx @@ -337,9 +337,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>RT_USING_ARMLIBC, __RTTHREAD__, RT_USING_LIBC, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, N32H49x, CORE_CM4, __CLK_TCK=RT_TICK_PER_SECOND</Define> + <Define>N32H49x, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __STDC_LIMIT_MACROS, CORE_CM4, __RTTHREAD__, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER</Define> <Undefine></Undefine> - <IncludePath>..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;..\libraries\N32_Drivers\drivers\config;applications;board\Cube_Config\USER\inc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;packages\CMSIS-Core-latest\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\eventfd;..\libraries\N32_Drivers\drivers;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;.;packages\n32h49x_cmsis_driver-latest\device;board;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\cortex-m4;packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc;board\ports;..\..\..\..\components\net\utest;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\drivers\phy;..\libraries\N32_Drivers;..\..\..\..\include;..\..\..\..\components\finsh;..\..\..\..\components\libc\posix\ipc</IncludePath> + <IncludePath>..\libraries\N32_Drivers\drivers\config;..\..\..\..\libcpu\arm\cortex-m4;packages\CMSIS-Core-latest\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\finsh;board\Cube_Config\USER\inc;..\..\..\..\components\libc\posix\ipc;..\libraries\N32_Drivers;..\..\..\..\libcpu\arm\common;..\..\..\..\components\net\utest;..\libraries\N32_Drivers\drivers;board\ports;packages\n32h49x_std_driver-latest\n32h49x_std_periph_driver\inc;..\..\..\..\components\drivers\include;.;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;board;packages\n32h49x_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;applications</IncludePath> </VariousControls> </Cads> <Aads> diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.config b/bsp/n32/n32hxxx/n32h760zil7-stb/.config index e495a65abe..d13e20053d 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/.config +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.config @@ -224,7 +224,22 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system # -# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set # end of DFS: device virtual file system # CONFIG_RT_USING_FAL is not set @@ -1507,7 +1522,9 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_QSPI is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_FDCAN is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_CLOCK_TIMER is not set diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx Binary files differindex 506b1fb808..f79a41c17e 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h index 8015ca89bd..419e3c6114 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h @@ -29,7 +29,7 @@ extern "C" { /* NTFx CODE START Extern*/ extern void SysTick_Delayms(uint32_t Delayms); -extern void DMA_SetPerMemAddr(DMA_ChannelType *DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); +extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ); extern bool RCC_Configuration(void); extern bool NVIC_Configuration(void); extern bool DMA_Configuration(void); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c index 82162ec4a7..b248af7d7e 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c @@ -9,76 +9,76 @@ __IO uint32_t mwTick; void SysTick_Delayms(uint32_t Delayms) { uint32_t tickstart = mwTick; - uint32_t wait = Delayms; + uint32_t wait=Delayms; /* Add 1 to guarantee minimum wait */ if (wait < 0xFFFFFFFFU) { - wait += 1; + wait +=1; } while ((mwTick - tickstart) < wait) { } } -/** -*@name DMA_SetSrcDstAddr. -*@brief Set peripher address and memory address of DMA -*param DMAy (The input parameters must be the following values): -* - DMA1 -* - DMA2 -* - DMA3 -*param ChNum (The input parameters must be the following values): -* - DMA_CHANNEL_0 -* - DMA_CHANNEL_1 -* - DMA_CHANNEL_2 -* - DMA_CHANNEL_3 -* - DMA_CHANNEL_4 -* - DMA_CHANNEL_5 -* - DMA_CHANNEL_6 -* - DMA_CHANNEL_7 -*@param SrcAddr Source address -*@param DstAddr Destination address -*@return status -*/ -void DMA_SetSrcDstAddr(DMA_Module * const DMAy, DMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) -{ + /** + *@name DMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of DMA + *param DMAy (The input parameters must be the following values): + * - DMA1 + * - DMA2 + * - DMA3 + *param ChNum (The input parameters must be the following values): + * - DMA_CHANNEL_0 + * - DMA_CHANNEL_1 + * - DMA_CHANNEL_2 + * - DMA_CHANNEL_3 + * - DMA_CHANNEL_4 + * - DMA_CHANNEL_5 + * - DMA_CHANNEL_6 + * - DMA_CHANNEL_7 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ + void DMA_SetSrcDstAddr(DMA_Module *const DMAy,DMA_ChNumType ChNum, uint32_t SrcAddr,uint32_t DstAddr ) + { /* Sets channel n source address register */ WRITE_REG(DMAy->CH[ChNum].SA, SrcAddr); /* Sets channel n destination address register */ WRITE_REG(DMAy->CH[ChNum].DA, DstAddr); -} -/** -*@name MDMA_SetSrcDstAddr. -*@brief Set peripher address and memory address of MDMA -*param MDMAy (The input parameters must be the following values): -* - MDMA -*param ChNum (The input parameters must be the following values): -* - MDMA_CHANNEL_0 -* - MDMA_CHANNEL_1 -* - MDMA_CHANNEL_2 -* - MDMA_CHANNEL_3 -* - MDMA_CHANNEL_4 -* - MDMA_CHANNEL_5 -* - MDMA_CHANNEL_6 -* - MDMA_CHANNEL_7 -* - MDMA_CHANNEL_8 -* - MDMA_CHANNEL_9 -* - MDMA_CHANNEL_10 -* - MDMA_CHANNEL_11 -* - MDMA_CHANNEL_12 -* - MDMA_CHANNEL_13 -* - MDMA_CHANNEL_14 -* - MDMA_CHANNEL_15 -*@param SrcAddr Source address -*@param DstAddr Destination address -*@return status -*/ -void MDMA_SetSrcDstAddr(MDMA_Module * const MDMAy, MDMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) -{ + } + /** + *@name MDMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of MDMA + *param MDMAy (The input parameters must be the following values): + * - MDMA + *param ChNum (The input parameters must be the following values): + * - MDMA_CHANNEL_0 + * - MDMA_CHANNEL_1 + * - MDMA_CHANNEL_2 + * - MDMA_CHANNEL_3 + * - MDMA_CHANNEL_4 + * - MDMA_CHANNEL_5 + * - MDMA_CHANNEL_6 + * - MDMA_CHANNEL_7 + * - MDMA_CHANNEL_8 + * - MDMA_CHANNEL_9 + * - MDMA_CHANNEL_10 + * - MDMA_CHANNEL_11 + * - MDMA_CHANNEL_12 + * - MDMA_CHANNEL_13 + * - MDMA_CHANNEL_14 + * - MDMA_CHANNEL_15 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ + void MDMA_SetSrcDstAddr(MDMA_Module *const MDMAy,MDMA_ChNumType ChNum, uint32_t SrcAddr,uint32_t DstAddr ) + { /* Sets channel n source address register */ WRITE_REG(MDMAy->CH[ChNum].SA, SrcAddr); /* Sets channel n destination address register */ WRITE_REG(MDMAy->CH[ChNum].DA, DstAddr); -} + } /* NTFx CODE END */ /* NTFx CODE START */ @@ -90,20 +90,17 @@ void MDMA_SetSrcDstAddr(MDMA_Module * const MDMAy, MDMA_ChNumType ChNum, uint32_ bool RCC_Configuration(void) { ErrorStatus ClockStatus; - + RCC_ConfigHSIclkDivider(RCC_HSICLK_DIV1); RCC_EnableHsi(ENABLE); /* Wait till HSI is ready */ ClockStatus = RCC_WaitHsiStable(); - if (ClockStatus != SUCCESS) - { - return false; - } + if (ClockStatus != SUCCESS) return false; RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); /*Configures the Periph clock source as HSI*/ RCC_ConfigPeriphClk(RCC_PERIPHCLK_SRC_HSI); - + /* Configure APB1 clock is AHB1/2 = 150.000M */ /* Configure APB2 clock is AHB2/2 = 150.000M */ /* Configure APB5 clock is AHB5/2 = 150.000M */ @@ -111,7 +108,7 @@ bool RCC_Configuration(void) RCC_ConfigAPBclkDivider(RCC_APB1CLK_DIV2, RCC_APB2CLK_DIV2, RCC_APB5CLK_DIV2, RCC_APB6CLK_DIV2); /*Configures the PLL1 clock source and multiplication factor,Fin=64M,Fout=600M*/ //RCC_ConfigPll1(RCC_PLL_SRC_HSI,64000000,600000000,ENABLE); - RCC_ConfigPll1_NoCalculate(RCC_PLL_SRC_HSI, 0, 153600, 3, ENABLE); + RCC_ConfigPll1_NoCalculate(RCC_PLL_SRC_HSI,0,153600,3,ENABLE); /*Configure PLL1 divider value to Pll1A*/ RCC_ConfigPLL1ADivider(RCC_PLLA_DIV1); /*Configure PLL1 divider value to Pll1B*/ @@ -127,18 +124,18 @@ bool RCC_Configuration(void) /* configure sys_clk source is PLL1A */ RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); /* Check if sys_clk source is PLL1A */ - while (RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A); - + while(RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A); + /*Config the USART1/2 PCLK divider from ahb1*/ RCC_ConfigUSARTPClk(RCC_USARTPCLK_AHB1_DIV1); - + /*Config the TRNG clock*/ - RCC_ConfigTRNGClk(RCC_TRNGCLK_SRC_SYSBUSDIV, RCC_TRNGCLK_SYSBUSDIV2); - - + RCC_ConfigTRNGClk(RCC_TRNGCLK_SRC_SYSBUSDIV,RCC_TRNGCLK_SYSBUSDIV2); + + /*Enables the APB1 peripheral clock 3 .*/ - RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE); - /* NTFx CODE END */ + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1 ,ENABLE); +/* NTFx CODE END */ return true; } @@ -150,7 +147,8 @@ bool RCC_Configuration(void) */ bool NVIC_Configuration(void) { - /* NTFx CODE END */ + +/* NTFx CODE END */ return true; } @@ -162,7 +160,8 @@ bool NVIC_Configuration(void) */ bool DMA_Configuration(void) { - /* NTFx CODE END */ + +/* NTFx CODE END */ return true; } @@ -174,30 +173,35 @@ bool DMA_Configuration(void) */ bool GPIO_Configuration(void) { + GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); /* Enable the GPIO clock*/ - RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA | RCC_AHB5_PERIPHEN_M7_GPIOC | RCC_AHB5_PERIPHEN_M7_GPIOH | RCC_AHB5_PERIPHEN_M4_GPIOA | RCC_AHB5_PERIPHEN_M4_GPIOC | RCC_AHB5_PERIPHEN_M4_GPIOH, ENABLE); - RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO | RCC_AHB5_PERIPHEN_M4_AFIO, ENABLE); - - + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA | RCC_AHB5_PERIPHEN_M7_GPIOC | RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE); + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO,ENABLE); + + + + /*********Initialize USART1 GPIO function *********/ + /********PA10->USART1.RX********/ + /********PA9->USART1.TX********/ /*Initialize input GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; - GPIO_InitStructure.Pin = GPIO_PIN_10; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - + GPIO_InitStructure.Pin = GPIO_PIN_10; + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + /*Initialize AF_PP GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW; - GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; + GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; GPIO_InitStructure.GPIO_Alternate = GPIO_AF7; - GPIO_InitStructure.Pin = GPIO_PIN_9; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - - /* NTFx CODE END */ + GPIO_InitStructure.Pin = GPIO_PIN_9; + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + +/* NTFx CODE END */ return true; } @@ -211,24 +215,24 @@ bool USART_Configuration(void) { USART_InitType USART_InitStructure; USART_StructInit(&USART_InitStructure); - - + + /*********initialize the USART1************/ USART_DeInit(USART1); - USART_InitStructure.BaudRate = 115200; - USART_InitStructure.WordLength = USART_WL_8B; - USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; - USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - USART_InitStructure.OverSampling = USART_16OVER; + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER ; /* Configure USART1 */ USART_Init(USART1, &USART_InitStructure); - - + + /* Enable the USART1 */ USART_Enable(USART1, ENABLE); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig index 1f1614fdd4..9e5790c972 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig @@ -403,6 +403,28 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n + + menuconfig BSP_USING_SDIO + bool "Enable SD/MMC" + select RT_USING_SDIO + select RT_USING_BLK + default n + if BSP_USING_SDIO + choice BSP_SDIO_SEL + prompt "Select SDIO Instance" + default BSP_USING_SDIO1 + + config BSP_USING_SDIO1 + bool "SDIO1 (SDMMC1, AXI bus)" + + config BSP_USING_SDIO2 + bool "SDIO2 (SDMMC2, AHB1 bus)" + endchoice + + config BSP_USING_SDIO_SDMA + bool "Enable SDMA data transfer" + default n + endif menuconfig BSP_USING_FDCAN bool "Enable FDCAN (CAN FD)" @@ -414,27 +436,762 @@ menu "On-chip Peripheral Drivers" config BSP_USING_FDCAN1 bool "Enable FDCAN1" default n + if BSP_USING_FDCAN1 + menu "FDCAN1 resource configuration" + config BSP_FDCAN1_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN1_USING_TDC + config BSP_FDCAN1_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN1_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN1_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN1_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN1_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN1_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN1_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN1_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN1_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN1_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN1_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN2 bool "Enable FDCAN2" default n + if BSP_USING_FDCAN2 + menu "FDCAN2 resource configuration" + config BSP_FDCAN2_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN2_USING_TDC + config BSP_FDCAN2_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN2_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN2_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN2_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN2_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN2_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN2_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN2_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN2_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN2_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN2_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN3 bool "Enable FDCAN3" default n + if BSP_USING_FDCAN3 + menu "FDCAN3 resource configuration" + config BSP_FDCAN3_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN3_USING_TDC + config BSP_FDCAN3_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN3_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN3_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN3_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN3_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN3_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN3_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN3_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN3_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN3_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN3_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN4 bool "Enable FDCAN4" default n + if BSP_USING_FDCAN4 + menu "FDCAN4 resource configuration" + config BSP_FDCAN4_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN4_USING_TDC + config BSP_FDCAN4_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN4_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN4_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN4_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN4_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN4_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN4_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN4_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN4_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN4_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN4_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN4_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN4_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN4_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN4_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN5 bool "Enable FDCAN5" default n + if BSP_USING_FDCAN5 + menu "FDCAN5 resource configuration" + config BSP_FDCAN5_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN5_USING_TDC + config BSP_FDCAN5_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN5_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN5_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN5_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN5_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN5_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN5_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN5_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN5_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN5_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN5_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN5_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN5_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN5_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN5_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN6 bool "Enable FDCAN6" default n + if BSP_USING_FDCAN6 + menu "FDCAN6 resource configuration" + config BSP_FDCAN6_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN6_USING_TDC + config BSP_FDCAN6_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN6_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN6_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN6_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN6_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN6_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN6_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN6_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN6_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN6_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN6_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN6_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN6_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN6_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN6_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN7 bool "Enable FDCAN7" default n + if BSP_USING_FDCAN7 + menu "FDCAN7 resource configuration" + config BSP_FDCAN7_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN7_USING_TDC + config BSP_FDCAN7_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN7_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN7_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN7_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN7_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN7_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN7_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN7_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN7_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN7_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN7_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN7_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN7_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN7_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN7_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif + config BSP_USING_FDCAN8 bool "Enable FDCAN8" default n + if BSP_USING_FDCAN8 + menu "FDCAN8 resource configuration" + config BSP_FDCAN8_USING_TDC + bool "Enable transmitter delay compensation" + default n + + if BSP_FDCAN8_USING_TDC + config BSP_FDCAN8_TDC_OFFSET + int "TDC offset" + range 0 127 + default 0 + + config BSP_FDCAN8_TDC_FILTER + int "TDC filter window" + range 0 127 + default 0 + endif + + config BSP_FDCAN8_STD_FILTER_SIZE + int "Standard ID filter elements" + range 0 128 + default 2 + + config BSP_FDCAN8_EXT_FILTER_SIZE + int "Extended ID filter elements" + range 0 64 + default 2 + + config BSP_FDCAN8_RX_FIFO0_SIZE + int "RX FIFO0 elements" + range 1 64 + default 8 + + config BSP_FDCAN8_RX_FIFO0_DATA_BYTES + int "RX FIFO0 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN8_RX_FIFO1_SIZE + int "RX FIFO1 elements" + range 0 64 + default 0 + + config BSP_FDCAN8_RX_FIFO1_DATA_BYTES + int "RX FIFO1 data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN8_RX_BUFFER_SIZE + int "Dedicated RX buffer elements" + range 0 64 + default 0 + + config BSP_FDCAN8_RX_BUFFER_DATA_BYTES + int "Dedicated RX buffer data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN8_TX_EVENT_FIFO_SIZE + int "TX event FIFO elements" + range 0 32 + default 0 + + config BSP_FDCAN8_TX_BUFFER_SIZE + int "Dedicated TX buffer elements" + range 1 32 + default 3 + + config BSP_FDCAN8_TX_BUFFER_DATA_BYTES + int "TX buffer/FIFO data bytes per element" + range 8 64 + default 64 + help + Valid values: 8, 12, 16, 20, 24, 32, 48 or 64. + + config BSP_FDCAN8_TX_QUEUE_MODE + bool "Use TX Queue mode (otherwise FIFO mode)" + default n + + config BSP_FDCAN8_TX_FIFO_QUEUE_SIZE + int "TX FIFO/Queue elements" + range 0 31 + default 0 + endmenu + endif endif menuconfig BSP_USING_DAC diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c index d5709fcc27..032b69058e 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c @@ -31,16 +31,16 @@ void MPU_Config(void) */ MPU_Disable(); - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.Size = MPU_REGION_SIZE_256MB; + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Size = MPU_REGION_SIZE_256MB; MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; - MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER0; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; MPU_InitStruct.SubRegionDisable = 0x00; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; #ifdef BSP_USING_NAND_BANK1 MPU_InitStruct.BaseAddress = ((uint32_t)0xA0000000); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h index b5d9eabd87..216a69cea1 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h @@ -28,12 +28,12 @@ extern "C" { #endif -#define N32_FLASH_START_ADRESS ((uint32_t)0x15000000) -#define N32_FLASH_SIZE ((2 *1024 * 1024) - (128 * 1024)) -#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE)) +#define N32_FLASH_START_ADRESS ((uint32_t)0x15000000) +#define N32_FLASH_SIZE ((2 * 1024 * 1024) - (128 * 1024)) +#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE)) -#define N32_SRAM_SIZE (128) -#define N32_SRAM_END (0x24000000 + N32_SRAM_SIZE * 1024) +#define N32_SRAM_SIZE (128) +#define N32_SRAM_END (0x24000000 + N32_SRAM_SIZE * 1024) #if defined(__ARMCC_VERSION) extern int Image$$RW_AXI_SRAM$$ZI$$Limit; @@ -43,7 +43,7 @@ extern int _app_estack; #define HEAP_BEGIN (&_app_estack) #endif -#define HEAP_END N32_SRAM_END +#define HEAP_END N32_SRAM_END void System_Initialize(void); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sd_host.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sd_host.h new file mode 100644 index 0000000000..f3d023e05d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sd_host.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-08-11 ox-horse first version + */ + +#ifndef __SD_HOST_H__ +#define __SD_HOST_H__ + +#include "board.h" + +/* SD card product name length united as bytes. */ +#define SD_PRODUCT_NAME_BYTES (5U) + +/* SD card CID register */ +typedef struct +{ + uint8_t manufacturerID; /* Manufacturer ID [127:120] */ + uint16_t applicationID; /* OEM/Application ID [119:104] */ + uint8_t productName[SD_PRODUCT_NAME_BYTES]; /* Product name [103:64] */ + uint8_t productVersion; /* Product revision [63:56] */ + uint32_t productSerialNumber; /* Product serial number [55:24] */ + uint16_t manufacturerData; /* Manufacturing date [19:8] */ +} sd_cid; + +/* SD card CSD register */ +typedef struct +{ + uint8_t csdStructure; /* CSD structure [127:126] */ + uint8_t dataReadAccessTime1; /* Data read access-time-1 [119:112] */ + uint8_t dataReadAccessTime2; /* Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /* Maximum data transfer rate [103:96] */ + uint16_t cardCommandClass; /* Card command classes [95:84] */ + uint8_t readBlockLength; /* Maximum read data block length [83:80] */ + uint16_t flags; /* Flags in _sd_csd_flag */ + uint32_t deviceSize; /* Device size [73:62] */ + /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ + uint8_t readCurrentVddMin; /* Maximum read current at VDD min [61:59] */ + uint8_t readCurrentVddMax; /* Maximum read current at VDD max [58:56] */ + uint8_t writeCurrentVddMin; /* Maximum write current at VDD min [55:53] */ + uint8_t writeCurrentVddMax; /* Maximum write current at VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /* Device size multiplier [49:47] */ + + uint8_t eraseSectorSize; /* Erase sector size [45:39] */ + uint8_t writeProtectGroupSize; /* Write protect group size [38:32] */ + uint8_t writeSpeedFactor; /* Write speed factor [28:26] */ + uint8_t writeBlockLength; /* Maximum write data block length [25:22] */ + uint8_t fileFormat; /* File format [11:10] */ +} sd_csd_t; + +/* SD card SCR register */ +typedef struct _sd_scr +{ + uint8_t scrStructure; /* SCR Structure [63:60] */ + uint8_t sdSpecification; /* SD memory card specification version [59:56] */ + uint16_t flags; /* SCR flags in _sd_scr_flag */ + uint8_t sdSecurity; /* Security specification supported [54:52] */ + uint8_t sdBusWidths; /* Data bus widths supported [51:48] */ + uint8_t commandSupport; /* Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ + uint32_t reservedForManufacturer; /* reserved for manufacturer usage [31:0] */ +} sd_scr_t; + +/* Record information of card */ +typedef struct +{ + uint32_t flags; /* sd card Flags */ + uint32_t busy; /* busy status */ + uint32_t ocr; /* Raw OCR content,, only 24bit avalible for SDIO card */ + sd_cid cid; /* CID */ + uint32_t rca; /* Relative address of the card */ + sd_csd_t csd; /* CSD */ + uint32_t blockCount; /* Card total block number */ + uint32_t blockSize; /* Card block size */ + sd_scr_t scr; /* SCR */ + uint32_t version; /* Card version */ +// sd_status_t stat; /* sd 512 bit status */ +} sd_card_info; + + +/* card bus width */ +typedef enum +{ + SDMMC_BusWidth1Bit = 0U, /* card bus 1 width */ + SDMMC_BusWidth4Bit = 1U, /* card bus 4 width */ + SDMMC_BusWidth8Bit = 2U, /* card bus 8 width */ +} sd_bus_width_t; + +/* dma mode */ +typedef enum +{ + SDMMC_NODMA = 0U, /* no use dma */ + SDMMC_SDMA = 1U, /* use sdma */ + SDMMC_ADMA = 2U, /* use adma */ +} sd_dma_t; + +/* card operation voltage */ +typedef enum +{ + SD_OperationVoltageNone = 0U, /* indicate current voltage setting is not setting by suser*/ + SD_OperationVoltage330V = 1U, /* card operation voltage around 3.3v */ + SD_OperationVoltage300V = 2U, /* card operation voltage around 3.0v */ + SD_OperationVoltage180V = 3U, /* card operation voltage around 1.8v */ +} sd_operation_voltage_t; + +/* SD card communication method and speed */ +typedef struct +{ + uint32_t busClock_Hz; /* SD bus clock frequency united in Hz */ + sd_bus_width_t busWidth; /* set DATA bus width */ + SD_ModeConfig mode; /* work mode */ + sd_dma_t dma; /* dma mode */ + sd_operation_voltage_t operationVoltageflag; /* card current operation voltage */ +} sd_card_workmode; + +/* SD card state + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct +{ + SDHOST_Module *SDHOSTx; /* Host device */ + SDMMC_Module *SDMMCx; /* SDMMC */ + SDMMC_CMD command; + sd_card_info sd_card_information; + sd_card_workmode card_workmode; + SDHOST_TMODE_struct tMode; +} sd_card_t; + +#ifdef __cplusplus +} +#endif + +#endif /* __SD_HOST_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx index 8646d492b6..bb17432120 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx @@ -526,42 +526,6 @@ <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <bDave2>0</bDave2> - <PathWithFileName>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c</PathWithFileName> - <FilenameWithoutPath>dfs_elm.c</FilenameWithoutPath> - <RteFlg>0</RteFlg> - <bShared>0</bShared> - </File> - <File> - <GroupNumber>5</GroupNumber> - <FileNumber>27</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <bDave2>0</bDave2> - <PathWithFileName>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c</PathWithFileName> - <FilenameWithoutPath>ff.c</FilenameWithoutPath> - <RteFlg>0</RteFlg> - <bShared>0</bShared> - </File> - <File> - <GroupNumber>5</GroupNumber> - <FileNumber>28</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <bDave2>0</bDave2> - <PathWithFileName>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c</PathWithFileName> - <FilenameWithoutPath>ffunicode.c</FilenameWithoutPath> - <RteFlg>0</RteFlg> - <bShared>0</bShared> - </File> - <File> - <GroupNumber>5</GroupNumber> - <FileNumber>29</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <tvExpOptDlg>0</tvExpOptDlg> - <bDave2>0</bDave2> <PathWithFileName>..\..\..\..\components\dfs\dfs_v1\src\dfs.c</PathWithFileName> <FilenameWithoutPath>dfs.c</FilenameWithoutPath> <RteFlg>0</RteFlg> @@ -569,7 +533,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>30</FileNumber> + <FileNumber>27</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -581,7 +545,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>31</FileNumber> + <FileNumber>28</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -593,7 +557,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>32</FileNumber> + <FileNumber>29</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -613,7 +577,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>6</GroupNumber> - <FileNumber>33</FileNumber> + <FileNumber>30</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -625,7 +589,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>34</FileNumber> + <FileNumber>31</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -637,7 +601,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>35</FileNumber> + <FileNumber>32</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -649,7 +613,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>36</FileNumber> + <FileNumber>33</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -661,7 +625,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>37</FileNumber> + <FileNumber>34</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -681,7 +645,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>7</GroupNumber> - <FileNumber>38</FileNumber> + <FileNumber>35</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -693,7 +657,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>39</FileNumber> + <FileNumber>36</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -705,7 +669,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>40</FileNumber> + <FileNumber>37</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -717,7 +681,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>41</FileNumber> + <FileNumber>38</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -729,7 +693,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>42</FileNumber> + <FileNumber>39</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -741,7 +705,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>43</FileNumber> + <FileNumber>40</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -753,7 +717,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>44</FileNumber> + <FileNumber>41</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -765,7 +729,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>45</FileNumber> + <FileNumber>42</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -777,7 +741,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>46</FileNumber> + <FileNumber>43</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -789,7 +753,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>47</FileNumber> + <FileNumber>44</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -801,7 +765,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>48</FileNumber> + <FileNumber>45</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -813,7 +777,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>49</FileNumber> + <FileNumber>46</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -825,7 +789,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>50</FileNumber> + <FileNumber>47</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -837,7 +801,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>51</FileNumber> + <FileNumber>48</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -849,7 +813,7 @@ </File> <File> <GroupNumber>7</GroupNumber> - <FileNumber>52</FileNumber> + <FileNumber>49</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -869,7 +833,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>8</GroupNumber> - <FileNumber>53</FileNumber> + <FileNumber>50</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -881,7 +845,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>54</FileNumber> + <FileNumber>51</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -893,7 +857,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>55</FileNumber> + <FileNumber>52</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -905,7 +869,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>56</FileNumber> + <FileNumber>53</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -917,7 +881,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>57</FileNumber> + <FileNumber>54</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -929,7 +893,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>58</FileNumber> + <FileNumber>55</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -941,7 +905,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>59</FileNumber> + <FileNumber>56</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -953,7 +917,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>60</FileNumber> + <FileNumber>57</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -965,7 +929,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>61</FileNumber> + <FileNumber>58</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -977,7 +941,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>62</FileNumber> + <FileNumber>59</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -989,7 +953,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>63</FileNumber> + <FileNumber>60</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1001,7 +965,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>64</FileNumber> + <FileNumber>61</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1013,7 +977,7 @@ </File> <File> <GroupNumber>8</GroupNumber> - <FileNumber>65</FileNumber> + <FileNumber>62</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1033,7 +997,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>9</GroupNumber> - <FileNumber>66</FileNumber> + <FileNumber>63</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1045,7 +1009,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>67</FileNumber> + <FileNumber>64</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1057,7 +1021,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>68</FileNumber> + <FileNumber>65</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1069,7 +1033,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>69</FileNumber> + <FileNumber>66</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1081,7 +1045,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>70</FileNumber> + <FileNumber>67</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1093,7 +1057,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>71</FileNumber> + <FileNumber>68</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1105,7 +1069,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>72</FileNumber> + <FileNumber>69</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1117,7 +1081,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>73</FileNumber> + <FileNumber>70</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1129,7 +1093,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>74</FileNumber> + <FileNumber>71</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1141,7 +1105,7 @@ </File> <File> <GroupNumber>9</GroupNumber> - <FileNumber>75</FileNumber> + <FileNumber>72</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1161,7 +1125,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>10</GroupNumber> - <FileNumber>76</FileNumber> + <FileNumber>73</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1173,7 +1137,7 @@ </File> <File> <GroupNumber>10</GroupNumber> - <FileNumber>77</FileNumber> + <FileNumber>74</FileNumber> <FileType>2</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1185,7 +1149,7 @@ </File> <File> <GroupNumber>10</GroupNumber> - <FileNumber>78</FileNumber> + <FileNumber>75</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx index d0e5eb56e7..91f2256883 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx @@ -337,9 +337,9 @@ <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> - <Define>N32H76x, RT_USING_LIBC, __ICACHE_PRESENT=1, __CLK_TCK=RT_TICK_PER_SECOND, __DCACHE_PRESENT=1, CORE_CM7, USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, USING_TCM, __RTTHREAD__</Define> + <Define>N32H76x, __DCACHE_PRESENT=1, USING_TCM, __ICACHE_PRESENT=1, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, __RTTHREAD__, CORE_CM7, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, RT_USING_LIBC</Define> <Undefine></Undefine> - <IncludePath>..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\include;board;..\..\..\..\components\libc\posix\ipc;..\libraries\N32_Drivers\drivers\config;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;applications;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\net\utest;board\Cube_Config\USER\inc;..\..\..\..\libcpu\arm\cortex-m7;..\..\..\..\components\drivers\include;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\common;..\libraries\N32_Drivers;..\..\..\..\components\finsh;..\libraries\N32_Drivers\drivers;..\..\..\..\components\libc\compilers\common\extension;.</IncludePath> + <IncludePath>..\libraries\N32_Drivers\drivers\config;..\..\..\..\components\libc\compilers\common\extension;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\drivers\include;.;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;applications;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;..\libraries\N32_Drivers;packages\CMSIS-Core-latest\Include;..\..\..\..\libcpu\arm\cortex-m7;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\posix\io\eventfd;board;board\Cube_Config\USER\inc;..\libraries\N32_Drivers\drivers;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\common;..\..\..\..\components\net\utest;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;board\ports;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc</IncludePath> </VariousControls> </Cads> <Aads> @@ -1192,174 +1192,6 @@ </FileOption> </File> <File> - <FileName>dfs_elm.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c</FilePath> - <FileOption> - <CommonProperty> - <UseCPPCompiler>2</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <FileArmAds> - <Cads> - <interw>2</interw> - <Optim>0</Optim> - <oTime>2</oTime> - <SplitLS>2</SplitLS> - <OneElfS>2</OneElfS> - <Strict>2</Strict> - <EnumInt>2</EnumInt> - <PlainCh>2</PlainCh> - <Ropi>2</Ropi> - <Rwpi>2</Rwpi> - <wLevel>0</wLevel> - <uThumb>2</uThumb> - <uSurpInc>2</uSurpInc> - <uC99>2</uC99> - <uGnu>2</uGnu> - <useXO>2</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>2</vShortEn> - <vShortWch>2</vShortWch> - <v6Lto>2</v6Lto> - <v6WtE>2</v6WtE> - <v6Rtti>2</v6Rtti> - <VariousControls> - <MiscControls> --c99</MiscControls> - <Define> </Define> - <Undefine> </Undefine> - <IncludePath></IncludePath> - </VariousControls> - </Cads> - </FileArmAds> - </FileOption> - </File> - <File> - <FileName>ff.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c</FilePath> - <FileOption> - <CommonProperty> - <UseCPPCompiler>2</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <FileArmAds> - <Cads> - <interw>2</interw> - <Optim>0</Optim> - <oTime>2</oTime> - <SplitLS>2</SplitLS> - <OneElfS>2</OneElfS> - <Strict>2</Strict> - <EnumInt>2</EnumInt> - <PlainCh>2</PlainCh> - <Ropi>2</Ropi> - <Rwpi>2</Rwpi> - <wLevel>0</wLevel> - <uThumb>2</uThumb> - <uSurpInc>2</uSurpInc> - <uC99>2</uC99> - <uGnu>2</uGnu> - <useXO>2</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>2</vShortEn> - <vShortWch>2</vShortWch> - <v6Lto>2</v6Lto> - <v6WtE>2</v6WtE> - <v6Rtti>2</v6Rtti> - <VariousControls> - <MiscControls> --c99</MiscControls> - <Define> </Define> - <Undefine> </Undefine> - <IncludePath></IncludePath> - </VariousControls> - </Cads> - </FileArmAds> - </FileOption> - </File> - <File> - <FileName>ffunicode.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c</FilePath> - <FileOption> - <CommonProperty> - <UseCPPCompiler>2</UseCPPCompiler> - <RVCTCodeConst>0</RVCTCodeConst> - <RVCTZI>0</RVCTZI> - <RVCTOtherData>0</RVCTOtherData> - <ModuleSelection>0</ModuleSelection> - <IncludeInBuild>1</IncludeInBuild> - <AlwaysBuild>0</AlwaysBuild> - <GenerateAssemblyFile>0</GenerateAssemblyFile> - <AssembleAssemblyFile>0</AssembleAssemblyFile> - <PublicsOnly>0</PublicsOnly> - <StopOnExitCode>3</StopOnExitCode> - <CustomArgument></CustomArgument> - <IncludeLibraryModules></IncludeLibraryModules> - <ComprImg>1</ComprImg> - </CommonProperty> - <FileArmAds> - <Cads> - <interw>2</interw> - <Optim>0</Optim> - <oTime>2</oTime> - <SplitLS>2</SplitLS> - <OneElfS>2</OneElfS> - <Strict>2</Strict> - <EnumInt>2</EnumInt> - <PlainCh>2</PlainCh> - <Ropi>2</Ropi> - <Rwpi>2</Rwpi> - <wLevel>0</wLevel> - <uThumb>2</uThumb> - <uSurpInc>2</uSurpInc> - <uC99>2</uC99> - <uGnu>2</uGnu> - <useXO>2</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>2</vShortEn> - <vShortWch>2</vShortWch> - <v6Lto>2</v6Lto> - <v6WtE>2</v6WtE> - <v6Rtti>2</v6Rtti> - <VariousControls> - <MiscControls> --c99</MiscControls> - <Define> </Define> - <Undefine> </Undefine> - <IncludePath></IncludePath> - </VariousControls> - </Cads> - </FileArmAds> - </FileOption> - </File> - <File> <FileName>dfs.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\dfs\dfs_v1\src\dfs.c</FilePath> @@ -2615,13 +2447,4 @@ <files/> </RTE> - <LayerInfo> - <Layers> - <Layer> - <LayName>project</LayName> - <LayPrjMark>1</LayPrjMark> - </Layer> - </Layers> - </LayerInfo> - </Project> |