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authorZYH <[email protected]>2018-08-12 20:56:30 +0800
committerGitHub <[email protected]>2018-08-12 20:56:30 +0800
commitb571cd8899ff37341f184dbded101d6ef434d8c1 (patch)
treeb00f33d33629c75c6723ee332ac60dcddda96d42
parent68edd04cbbd996cb80d935f40e4f90d3742bfbc6 (diff)
parent250de62d5c5ababe7c3ae2a752b0f53734fab0ad (diff)
Merge pull request #1714 from xeonxu/fix_pwm
[STM32 BSP]Fix PWM channel calculate argorithm.
-rw-r--r--bsp/stm32f4xx-HAL/drivers/drv_pwm.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c
index c5be0e1267..f046090c96 100644
--- a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c
+++ b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c
@@ -38,18 +38,21 @@ static struct rt_pwm_ops drv_ops =
static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
- rt_uint32_t channel = 0x04 * configuration->channel;
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
if(!enable)
{
HAL_TIM_PWM_Stop(htim, channel);
}
- HAL_TIM_PWM_Start(htim, channel);
+ else
+ {
+ HAL_TIM_PWM_Start(htim, channel);
+ }
return RT_EOK;
}
static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration)
{
- rt_uint32_t channel = 0x04 * configuration->channel;
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
rt_uint32_t tim_clock;
#if (RT_HSE_HCLK > 100000000UL)//100M
if(htim->Instance == TIM1 && htim->Instance == TIM8)
@@ -81,7 +84,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio
{
rt_uint32_t period, pulse;
rt_uint32_t tim_clock, psc;
- rt_uint32_t channel = 0x04 * configuration->channel;
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
#if (RT_HSE_HCLK > 100000000UL)//100M
if(htim->Instance == TIM1 && htim->Instance == TIM8)
{