diff options
| author | Onlyou_tzZ <[email protected]> | 2026-08-12 15:37:21 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-08-12 15:37:21 +0800 |
| commit | b71a16830a58f8d0dd4067cc98efe7ebb3f47fa0 (patch) | |
| tree | 02bcd9ccddbad0b2f844574b5b4552eac07908c9 | |
| parent | 46fdeefb3239f8f4a22a373fc6fd362499389c9e (diff) | |
[bsp/n32]上传Nsing LCDC和SDRAM的驱动#11682
30 files changed, 5542 insertions, 811 deletions
diff --git a/bsp/README.md b/bsp/README.md index 233ecea93c..9fd1e080c2 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -317,23 +317,23 @@ This document is based on the RT-Thread mainline repository and categorizes the #### 🟡 N32 -| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH | -|----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----| -| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH | SDRAM | LCDC | QSPI | +|----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----|-----|---------|-------|------|-----|--------------|-------|------|-----| +| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | - | +| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | #### 🟡 NRF5x diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c index a931003a05..16f4b9bb55 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c @@ -24,15 +24,15 @@ typedef struct { - DACX DACx; + DACX DACx; DAC_Module *DAC_Module; - uint32_t periph_clk; - void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); - uint32_t DAC_clk_pres; + uint32_t periph_clk; + void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); + uint32_t DAC_clk_pres; GPIO_Module *GPIOx; - uint16_t GPIO_Pin; - uint32_t GPIO_RCC; + uint16_t GPIO_Pin; + uint32_t GPIO_RCC; DAC_InitType Init; } DAC_InitInfo_t; @@ -52,7 +52,7 @@ static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])]; struct n32_dac { - DAC_InitInfo_t DAC_Info; + DAC_InitInfo_t DAC_Info; struct rt_dac_device n32_dac_device; }; @@ -92,7 +92,7 @@ static rt_uint8_t n32_dac_get_resolution(struct rt_dac_device *device) static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) { - rt_uint16_t set_value; + rt_uint16_t set_value; DAC_InitInfo_t *n32_dac_info; RT_ASSERT(device != RT_NULL); @@ -116,17 +116,17 @@ static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t chan } static const struct rt_dac_ops n32_dac_ops = { - .disabled = n32_dac_disabled, - .enabled = n32_dac_enabled, - .convert = n32_set_dac_value, + .disabled = n32_dac_disabled, + .enabled = n32_dac_enabled, + .convert = n32_set_dac_value, .get_resolution = n32_dac_get_resolution, }; static int n32_dac_init(void) { - int result = RT_EOK; + int result = RT_EOK; char name_buf[5] = { 'd', 'a', 'c', '0', 0 }; - int i = 0; + int i = 0; for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++) { @@ -135,9 +135,13 @@ static int n32_dac_init(void) /* Set device name */ name_buf[3] = '0'; if (n32_dac_obj[i].DAC_Info.DACx == DAC1) + { name_buf[3] = '1'; + } else if (n32_dac_obj[i].DAC_Info.DACx == DAC2) + { name_buf[3] = '2'; + } /* Enable DAC peripheral clock */ n32_dac_obj[i].DAC_Info.EnablePeriphClk(n32_dac_obj[i].DAC_Info.periph_clk, ENABLE); diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c index 68773a2aca..071538a173 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c @@ -42,13 +42,13 @@ struct rt_n32_eth rt_uint8_t phy_addr; }; -static ETH_DMADescType *DMARxDscrTab, *DMATxDscrTab; -static rt_uint8_t *Rx_Buff, *Tx_Buff; -static ETH_InfoType sEthInfo; -static ETH_InitType sETH_InitParam; -static struct rt_n32_eth n32_eth_device; +static ETH_DMADescType *DMARxDscrTab, *DMATxDscrTab; +static rt_uint8_t *Rx_Buff, *Tx_Buff; +static ETH_InfoType sEthInfo; +static ETH_InitType sETH_InitParam; +static struct rt_n32_eth n32_eth_device; static struct rt_semaphore tx_sem; -static volatile rt_bool_t tx_is_waiting = RT_FALSE; +static volatile rt_bool_t tx_is_waiting = RT_FALSE; /* ======================= Debug Helper ======================= */ @@ -57,22 +57,32 @@ static volatile rt_bool_t tx_is_waiting = RT_FALSE; static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) { unsigned char *buf = (unsigned char *)ptr; - int i, j; + int i, j; for (i = 0; i < buflen; i += 16) { rt_kprintf("%08X: ", i); for (j = 0; j < 16; j++) + { if (i + j < buflen) + { rt_kprintf("%02X ", buf[i + j]); + } else + { rt_kprintf(" "); + } + } rt_kprintf(" "); for (j = 0; j < 16; j++) + { if (i + j < buflen) + { rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } rt_kprintf("\n"); } } @@ -87,7 +97,7 @@ extern void phy_reset(void); static rt_err_t rt_n32_eth_init(rt_device_t dev) { struct rt_n32_eth *eth = (struct rt_n32_eth *)dev; - EthFuncStatusType status; + EthFuncStatusType status; /* Enable or disable PWR Clock */ RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_PWR, ENABLE); @@ -102,21 +112,21 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev) memset(&sEthInfo, 0, sizeof(ETH_InfoType)); /* Set ETH operation-related information via sEthInfo */ - sEthInfo.MDCClockMode = ETH_MDCCLK_NORMAL; + sEthInfo.MDCClockMode = ETH_MDCCLK_NORMAL; sEthInfo.MediaInterface = ETH_MEDIA_INTERFACE; - sEthInfo.pMACAddr = (rt_uint8_t *)ð->dev_addr[0]; - sEthInfo.pRxDesc = DMARxDscrTab; - sEthInfo.pTxDesc = DMATxDscrTab; - sEthInfo.RxBuffLen = ETH_MAX_PACKET_SIZE; + sEthInfo.pMACAddr = (rt_uint8_t *)ð->dev_addr[0]; + sEthInfo.pRxDesc = DMARxDscrTab; + sEthInfo.pTxDesc = DMATxDscrTab; + sEthInfo.RxBuffLen = ETH_MAX_PACKET_SIZE; /* PHY register information */ - sEthInfo.PHYInfo.bcRegAddr = PHY_BASIC_CONTROL_REG; - sEthInfo.PHYInfo.bsRegAddr = PHY_BASIC_STATUS_REG; - sEthInfo.PHYInfo.phyReset = PHY_RESET_MASK; - sEthInfo.PHYInfo.phyAutoNeg = PHY_AUTO_NEGOTIATION_MASK; + sEthInfo.PHYInfo.bcRegAddr = PHY_BASIC_CONTROL_REG; + sEthInfo.PHYInfo.bsRegAddr = PHY_BASIC_STATUS_REG; + sEthInfo.PHYInfo.phyReset = PHY_RESET_MASK; + sEthInfo.PHYInfo.phyAutoNeg = PHY_AUTO_NEGOTIATION_MASK; sEthInfo.PHYInfo.phyAutoNegOK = PHY_AUTONEGO_COMPLETE_MASK; - sEthInfo.PHYInfo.phyLinkOK = PHY_LINKED_STATUS_MASK; - sEthInfo.PHYInfo.phyAddr = eth->phy_addr; + sEthInfo.PHYInfo.phyLinkOK = PHY_LINKED_STATUS_MASK; + sEthInfo.PHYInfo.phyAddr = eth->phy_addr; /* DeInitializes the ETH peripheral */ ETH_DeInit(ETH); @@ -126,13 +136,13 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev) /* Modify ETH initialization parameters (only override StructInit defaults) */ /* MAC Configuration */ - sETH_InitParam.AutoPadCRCStrip = ((uint32_t)ENABLE << 20); - sETH_InitParam.CRCStripTypePacket = ((uint32_t)ENABLE << 21); - sETH_InitParam.ProgramWatchdog = ((uint32_t)ENABLE << 8); + sETH_InitParam.AutoPadCRCStrip = ((uint32_t)ENABLE << 20); + sETH_InitParam.CRCStripTypePacket = ((uint32_t)ENABLE << 21); + sETH_InitParam.ProgramWatchdog = ((uint32_t)ENABLE << 8); sETH_InitParam.GiantPacketSizeLimit = (0x618U); /* Duplex and Speed (updated after PHY auto-negotiation) */ - sETH_InitParam.Duplex = (EthDuplexType)eth->ETH_Mode; + sETH_InitParam.Duplex = (EthDuplexType)eth->ETH_Mode; sETH_InitParam.SpeedSelect = (EthSpeedType)eth->ETH_Speed; /* MTL Configuration */ @@ -145,7 +155,7 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev) #endif /* DMA System Bus Mode Configuration */ - sETH_InitParam.BurstMode = ETH_BURST_MODE_FIXED; + sETH_InitParam.BurstMode = ETH_BURST_MODE_FIXED; sETH_InitParam.AddrAlignedBeats = ((uint32_t)ENABLE << 12); /* DMA Channel Configuration */ @@ -183,7 +193,7 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev) * Buf1Addr is the CPU-side backup for use in SMEMCPY during tx. */ for (rt_size_t i = 0; i < ETH_TX_DESC_NUMBER; i++) { - sEthInfo.pTxDesc[i].DESC0 = (uint32_t)&Tx_Buff[i * ETH_MAX_PACKET_SIZE]; + sEthInfo.pTxDesc[i].DESC0 = (uint32_t)&Tx_Buff[i * ETH_MAX_PACKET_SIZE]; sEthInfo.pTxDesc[i].Buf1Addr = (uint32_t)&Tx_Buff[i * ETH_MAX_PACKET_SIZE]; } @@ -197,9 +207,9 @@ static rt_err_t rt_n32_eth_init(rt_device_t dev) for (rt_size_t i = 0; i < ETH_RX_DESC_NUMBER; i++) { // ETH_RxDescAssignMemory(&sEthInfo, i, (uint8_t *)&Rx_Buff[i * ETH_MAX_PACKET_SIZE], NULL); - sEthInfo.pRxDesc[i].DESC0 = (uint32_t)&Rx_Buff[i * ETH_MAX_PACKET_SIZE]; - sEthInfo.pRxDesc[i].Buf1Addr = (uint32_t)&Rx_Buff[i * ETH_MAX_PACKET_SIZE]; - sEthInfo.pRxDesc[i].DESC3 |= ETH_DMARXND3RF_BUF1V | ETH_DMARXND3RF_OWN; + sEthInfo.pRxDesc[i].DESC0 = (uint32_t)&Rx_Buff[i * ETH_MAX_PACKET_SIZE]; + sEthInfo.pRxDesc[i].Buf1Addr = (uint32_t)&Rx_Buff[i * ETH_MAX_PACKET_SIZE]; + sEthInfo.pRxDesc[i].DESC3 |= ETH_DMARXND3RF_BUF1V | ETH_DMARXND3RF_OWN; } /* ETH interrupt Init */ @@ -267,16 +277,16 @@ static rt_err_t rt_n32_eth_control(rt_device_t dev, int cmd, void *args) rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) { - struct pbuf *q; - rt_uint32_t framelen = 0; - rt_uint32_t offset = 0; - rt_uint32_t remaining = 0; - rt_uint32_t copysize = 0; - uint8_t *src; - uint8_t *buffer; - rt_uint32_t node_idx = 0; - rt_uint32_t desc_idx; - ETH_BufferType TxBufNodes[ETH_TX_DESC_NUMBER]; + struct pbuf *q; + rt_uint32_t framelen = 0; + rt_uint32_t offset = 0; + rt_uint32_t remaining = 0; + rt_uint32_t copysize = 0; + uint8_t *src; + uint8_t *buffer; + rt_uint32_t node_idx = 0; + rt_uint32_t desc_idx; + ETH_BufferType TxBufNodes[ETH_TX_DESC_NUMBER]; ETH_TxPacketType TxPacket; /* Wait for descriptor to become available (interrupt-driven, no busy-poll) */ @@ -285,7 +295,7 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) rt_err_t sem_ret; tx_is_waiting = RT_TRUE; - sem_ret = rt_sem_take(&tx_sem, RT_TICK_PER_SECOND); + sem_ret = rt_sem_take(&tx_sem, RT_TICK_PER_SECOND); tx_is_waiting = RT_FALSE; if (sem_ret != RT_EOK) @@ -303,16 +313,16 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) } /* First buffer from current descriptor */ - buffer = (uint8_t *)(sEthInfo.pTxDesc->Buf1Addr); - TxBufNodes[0].pBuf = buffer; - TxBufNodes[0].Len = 0; + buffer = (uint8_t *)(sEthInfo.pTxDesc->Buf1Addr); + TxBufNodes[0].pBuf = buffer; + TxBufNodes[0].Len = 0; TxBufNodes[0].pNext = NULL; /* Copy pbuf chain into TX buffer pool, splitting at ETH_MAX_PACKET_SIZE boundaries */ for (q = p; q != NULL; q = q->next) { remaining = q->len; - src = (uint8_t *)q->payload; + src = (uint8_t *)q->payload; while (remaining > 0) { @@ -333,7 +343,7 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) /* Get next buffer from contiguous pool (wrap around descriptor ring) */ desc_idx = (sEthInfo.TxDescList.CurTxDesc + node_idx) % ETH_TX_DESC_NUMBER; - buffer = &Tx_Buff[desc_idx * ETH_MAX_PACKET_SIZE]; + buffer = &Tx_Buff[desc_idx * ETH_MAX_PACKET_SIZE]; /* Check this descriptor is available */ if ((sEthInfo.pTxDesc[desc_idx].DESC3 & ETH_DMATXND3RF_OWN) != (uint32_t)RESET) @@ -342,10 +352,10 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) return ERR_USE; } - TxBufNodes[node_idx].pBuf = buffer; - TxBufNodes[node_idx].Len = 0; + TxBufNodes[node_idx].pBuf = buffer; + TxBufNodes[node_idx].Len = 0; TxBufNodes[node_idx].pNext = NULL; - offset = 0; + offset = 0; } copysize = remaining; @@ -355,9 +365,9 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) } SMEMCPY(buffer + offset, src, copysize); - src += copysize; - offset += copysize; - framelen += copysize; + src += copysize; + offset += copysize; + framelen += copysize; remaining -= copysize; } } @@ -373,13 +383,13 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) /* Build TX packet: linked list of buffer segments */ memset(&TxPacket, 0, sizeof(ETH_TxPacketType)); - TxPacket.pTxBuffer = &TxBufNodes[0]; - TxPacket.Length = framelen; + TxPacket.pTxBuffer = &TxBufNodes[0]; + TxPacket.Length = framelen; TxPacket.Attributes = ETH_TX_PACKETS_FEATURES_CRCPAD; TxPacket.CRCPadCtrl = ETH_CRC_PAD_INSERT; #ifdef RT_LWIP_USING_HW_CHECKSUM - TxPacket.Attributes |= ETH_TX_PACKETS_FEATURES_CSUM; - TxPacket.ChecksumCtrl = ETH_CHECKSUM_INSERT_IPHDR_PAYLOAD_PHDR_CALC; + TxPacket.Attributes |= ETH_TX_PACKETS_FEATURES_CSUM; + TxPacket.ChecksumCtrl = ETH_CHECKSUM_INSERT_IPHDR_PAYLOAD_PHDR_CALC; #endif /* Transmit via SDK: handles descriptor setup, multi-descriptor FD/LD, @@ -407,15 +417,15 @@ rt_err_t rt_n32_eth_tx(rt_device_t dev, struct pbuf *p) struct pbuf *rt_n32_eth_rx(rt_device_t dev) { - struct pbuf *p = NULL; - struct pbuf *q; - rt_uint16_t len; - rt_uint32_t src_offset; - rt_uint32_t dst_offset; - rt_uint32_t remaining; - rt_uint32_t copysize; + struct pbuf *p = NULL; + struct pbuf *q; + rt_uint16_t len; + rt_uint32_t src_offset; + rt_uint32_t dst_offset; + rt_uint32_t remaining; + rt_uint32_t copysize; ETH_BufferType *src_node; - ETH_BufferType RxBufNodes[ETH_RX_DESC_NUMBER]; + ETH_BufferType RxBufNodes[ETH_RX_DESC_NUMBER]; /* Check if a complete frame has been received. * SDK internally scans descriptors, validates FD/LD, updates @@ -467,12 +477,12 @@ struct pbuf *rt_n32_eth_rx(rt_device_t dev) * src_offset — bytes already consumed from current src_node * remaining — bytes still needed to fill current pbuf segment * dst_offset — bytes already written into current pbuf segment */ - src_node = RxBufNodes; + src_node = RxBufNodes; src_offset = 0; for (q = p; q != NULL; q = q->next) { - remaining = q->len; + remaining = q->len; dst_offset = 0; while (remaining > 0 && src_node != NULL) @@ -480,7 +490,7 @@ struct pbuf *rt_n32_eth_rx(rt_device_t dev) /* Switch to next source node when current one is exhausted */ if (src_offset >= src_node->Len) { - src_node = src_node->pNext; + src_node = src_node->pNext; src_offset = 0; continue; } @@ -498,7 +508,7 @@ struct pbuf *rt_n32_eth_rx(rt_device_t dev) copysize); src_offset += copysize; dst_offset += copysize; - remaining -= copysize; + remaining -= copysize; } } @@ -587,10 +597,10 @@ void ETH_GLOBAL_IRQHANDLER(void) static void phy_linkchange(void) { - static rt_uint8_t phy_speed = 0; - rt_uint8_t phy_speed_new = 0; - rt_uint32_t status; - rt_uint8_t phy_addr = n32_eth_device.phy_addr; + static rt_uint8_t phy_speed = 0; + rt_uint8_t phy_speed_new = 0; + rt_uint32_t status; + rt_uint8_t phy_addr = n32_eth_device.phy_addr; /* Read PHY Basic Status Register */ ETH_ReadPHYRegister(ETH, phy_addr, PHY_BASIC_STATUS_REG, &status); @@ -760,7 +770,7 @@ static void eth_phy_isr(void *args) static void phy_monitor_thread_entry(void *parameter) { rt_uint8_t detected_count = 0; - rt_uint8_t phy_addr = 0xFF; + rt_uint8_t phy_addr = 0xFF; /* PHY auto-detection: scan addresses 0-31 for a valid PHY */ while (phy_addr == 0xFF) @@ -910,12 +920,12 @@ static int rt_hw_n32_eth_init(void) rt_sem_init(&tx_sem, "tx_sem", 0, RT_IPC_FLAG_FIFO); /* Register device operations */ - n32_eth_device.parent.parent.init = rt_n32_eth_init; - n32_eth_device.parent.parent.open = rt_n32_eth_open; - n32_eth_device.parent.parent.close = rt_n32_eth_close; - n32_eth_device.parent.parent.read = rt_n32_eth_read; - n32_eth_device.parent.parent.write = rt_n32_eth_write; - n32_eth_device.parent.parent.control = rt_n32_eth_control; + n32_eth_device.parent.parent.init = rt_n32_eth_init; + n32_eth_device.parent.parent.open = rt_n32_eth_open; + n32_eth_device.parent.parent.close = rt_n32_eth_close; + n32_eth_device.parent.parent.read = rt_n32_eth_read; + n32_eth_device.parent.parent.write = rt_n32_eth_write; + n32_eth_device.parent.parent.control = rt_n32_eth_control; n32_eth_device.parent.parent.user_data = RT_NULL; n32_eth_device.parent.eth_rx = rt_n32_eth_rx; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c index 823284ebc4..6f787a2497 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c @@ -152,7 +152,9 @@ static uint8_t _dlc_to_length(uint32_t dlc) dlc >>= FDCAN_ELEMENT_DLC_OFFSET; if (dlc > 15) + { return 8; + } return dlc_table[dlc]; } @@ -179,21 +181,37 @@ static uint32_t _length_to_dlc(uint8_t len) uint32_t dlc; if (len <= 8) + { dlc = len; + } else if (len <= 12) + { dlc = 9; + } else if (len <= 16) + { dlc = 10; + } else if (len <= 20) + { dlc = 11; + } else if (len <= 24) + { dlc = 12; + } else if (len <= 32) + { dlc = 13; + } else if (len <= 48) + { dlc = 14; + } else + { dlc = 15; + } return dlc << FDCAN_ELEMENT_DLC_OFFSET; } @@ -216,7 +234,9 @@ static uint32_t _get_arb_baud_index(uint32_t baud_rate) for (uint32_t i = 0; i < len; i++) { if (_fdcan_arb_timing_table[i].baud_rate == baud_rate) + { return i; + } } return (uint32_t)-1; } @@ -235,7 +255,9 @@ static uint32_t _get_data_baud_index(uint32_t baud_rate) for (uint32_t i = 0; i < len; i++) { if (_fdcan_data_timing_table[i].baud_rate == baud_rate) + { return i; + } } return (uint32_t)-1; } @@ -261,19 +283,33 @@ static uint32_t _get_data_baud_index(uint32_t baud_rate) static uint8_t _fdcan_get_index(FDCAN_Module *FDCANx) { if (FDCANx == FDCAN1) + { return 0; + } if (FDCANx == FDCAN2) + { return 1; + } if (FDCANx == FDCAN3) + { return 2; + } if (FDCANx == FDCAN4) + { return 3; + } if (FDCANx == FDCAN5) + { return 4; + } if (FDCANx == FDCAN6) + { return 5; + } if (FDCANx == FDCAN7) + { return 6; + } return 7; /* FDCAN8 */ } @@ -287,19 +323,33 @@ static uint8_t _fdcan_get_index(FDCAN_Module *FDCANx) static IRQn_Type _fdcan_get_int0_irqn(FDCAN_Module *FDCANx) { if (FDCANx == FDCAN1) + { return FDCAN1_INT0_IRQn; + } if (FDCANx == FDCAN2) + { return FDCAN2_INT0_IRQn; + } if (FDCANx == FDCAN3) + { return FDCAN3_INT0_IRQn; + } if (FDCANx == FDCAN4) + { return FDCAN4_INT0_IRQn; + } if (FDCANx == FDCAN5) + { return FDCAN5_INT0_IRQn; + } if (FDCANx == FDCAN6) + { return FDCAN6_INT0_IRQn; + } if (FDCANx == FDCAN7) + { return FDCAN7_INT0_IRQn; + } return FDCAN8_INT0_IRQn; } @@ -313,19 +363,33 @@ static IRQn_Type _fdcan_get_int0_irqn(FDCAN_Module *FDCANx) static IRQn_Type _fdcan_get_int1_irqn(FDCAN_Module *FDCANx) { if (FDCANx == FDCAN1) + { return FDCAN1_INT1_IRQn; + } if (FDCANx == FDCAN2) + { return FDCAN2_INT1_IRQn; + } if (FDCANx == FDCAN3) + { return FDCAN3_INT1_IRQn; + } if (FDCANx == FDCAN4) + { return FDCAN4_INT1_IRQn; + } if (FDCANx == FDCAN5) + { return FDCAN5_INT1_IRQn; + } if (FDCANx == FDCAN6) + { return FDCAN6_INT1_IRQn; + } if (FDCANx == FDCAN7) + { return FDCAN7_INT1_IRQn; + } return FDCAN8_INT1_IRQn; } @@ -345,7 +409,7 @@ static IRQn_Type _fdcan_get_int1_irqn(FDCAN_Module *FDCANx) static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure *cfg) { struct n32_fdcan *p_drv; - ErrorStatus status; + ErrorStatus status; RT_ASSERT(can != RT_NULL); RT_ASSERT(cfg != RT_NULL); @@ -354,11 +418,11 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure RT_ASSERT(p_drv != RT_NULL); /* Fill FDCAN init parameters */ - p_drv->init_struct.FrameFormat = FDCAN_FRAME_FD_BRS; - p_drv->init_struct.Mode = FDCAN_MODE_NORMAL; + p_drv->init_struct.FrameFormat = FDCAN_FRAME_FD_BRS; + p_drv->init_struct.Mode = FDCAN_MODE_NORMAL; p_drv->init_struct.AutoRetransmission = ENABLE; - p_drv->init_struct.TransmitPause = DISABLE; - p_drv->init_struct.ProtocolException = ENABLE; + p_drv->init_struct.TransmitPause = DISABLE; + p_drv->init_struct.ProtocolException = ENABLE; /* Configure operation mode */ switch (cfg->mode) @@ -388,10 +452,10 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure return -RT_ERROR; } - p_drv->init_struct.Prescaler = _fdcan_arb_timing_table[arb_idx].prescaler; + p_drv->init_struct.Prescaler = _fdcan_arb_timing_table[arb_idx].prescaler; p_drv->init_struct.SyncJumpWidth = _fdcan_arb_timing_table[arb_idx].sjw; - p_drv->init_struct.TimeSeg1 = _fdcan_arb_timing_table[arb_idx].tseg1; - p_drv->init_struct.TimeSeg2 = _fdcan_arb_timing_table[arb_idx].tseg2; + p_drv->init_struct.TimeSeg1 = _fdcan_arb_timing_table[arb_idx].tseg1; + p_drv->init_struct.TimeSeg2 = _fdcan_arb_timing_table[arb_idx].tseg2; #ifdef RT_CAN_USING_CANFD /* Configure CAN FD data segment baud rate */ @@ -404,18 +468,18 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure return -RT_ERROR; } - p_drv->init_struct.DataPrescaler = _fdcan_data_timing_table[data_idx].prescaler; + p_drv->init_struct.DataPrescaler = _fdcan_data_timing_table[data_idx].prescaler; p_drv->init_struct.DataSyncJumpWidth = _fdcan_data_timing_table[data_idx].sjw; - p_drv->init_struct.DataTimeSeg1 = _fdcan_data_timing_table[data_idx].tseg1; - p_drv->init_struct.DataTimeSeg2 = _fdcan_data_timing_table[data_idx].tseg2; + p_drv->init_struct.DataTimeSeg1 = _fdcan_data_timing_table[data_idx].tseg1; + p_drv->init_struct.DataTimeSeg2 = _fdcan_data_timing_table[data_idx].tseg2; } else { /* When CAN FD is not enabled, data phase parameters match arbitration */ - p_drv->init_struct.DataPrescaler = p_drv->init_struct.Prescaler; + p_drv->init_struct.DataPrescaler = p_drv->init_struct.Prescaler; p_drv->init_struct.DataSyncJumpWidth = p_drv->init_struct.SyncJumpWidth; - p_drv->init_struct.DataTimeSeg1 = p_drv->init_struct.TimeSeg1; - p_drv->init_struct.DataTimeSeg2 = p_drv->init_struct.TimeSeg2; + p_drv->init_struct.DataTimeSeg1 = p_drv->init_struct.TimeSeg1; + p_drv->init_struct.DataTimeSeg2 = p_drv->init_struct.TimeSeg2; } #endif @@ -424,12 +488,12 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure if (instance_idx < 4) { p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE1; - p_drv->init_struct.MsgRamOffset = instance_idx * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; + p_drv->init_struct.MsgRamOffset = instance_idx * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; } else { p_drv->init_struct.MsgRamStrAddr = FDCAN_MSG_RAM_BASE2; - p_drv->init_struct.MsgRamOffset = (instance_idx - 4) * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; + p_drv->init_struct.MsgRamOffset = (instance_idx - 4) * FDCAN_MSG_RAM_OFFSET_PER_INSTANCE; } /* Filter configuration */ @@ -437,25 +501,25 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure p_drv->init_struct.ExtFilterSize = 2; /* 2 extended ID filters */ /* RX FIFO0 configuration */ - p_drv->init_struct.RxFifo0Size = FDCAN_RX_FIFO0_SIZE; + p_drv->init_struct.RxFifo0Size = FDCAN_RX_FIFO0_SIZE; p_drv->init_struct.RxFifo0DataSize = FDCAN_DATA_BYTES_64; /* RX FIFO1 configuration (not used) */ - p_drv->init_struct.RxFifo1Size = 0; + p_drv->init_struct.RxFifo1Size = 0; p_drv->init_struct.RxFifo1DataSize = FDCAN_DATA_BYTES_64; /* RX Buffer configuration (not used) */ - p_drv->init_struct.RxBufferSize = 0; + p_drv->init_struct.RxBufferSize = 0; p_drv->init_struct.RxBufferDataSize = FDCAN_DATA_BYTES_64; /* TX Event FIFO configuration (not used) */ p_drv->init_struct.TxEventSize = 0; /* TX Buffer configuration: dedicated Tx Buffer mode */ - p_drv->init_struct.TxBufferSize = FDCAN_TX_BUF_NUM; + p_drv->init_struct.TxBufferSize = FDCAN_TX_BUF_NUM; p_drv->init_struct.TxBufferDataSize = FDCAN_DATA_BYTES_64; - p_drv->init_struct.TxFifoQueueMode = FDCAN_TX_FIFO_MODE; - p_drv->init_struct.TxFifoQueueSize = 0; /* not using Tx FIFO, use Dedicated Tx Buffer */ + p_drv->init_struct.TxFifoQueueMode = FDCAN_TX_FIFO_MODE; + p_drv->init_struct.TxFifoQueueSize = 0; /* not using Tx FIFO, use Dedicated Tx Buffer */ /* Message RAM info pointer */ p_drv->init_struct.pMsgInfo = &p_drv->msg_ram; @@ -468,8 +532,8 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure * on every reconfigure. FDCAN_AbortTxRequest() is asynchronous - poll * TXBRP until it actually clears before continuing. */ { - rt_uint32_t cancel_mask = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; - volatile uint32_t timeout = 1000000; + rt_uint32_t cancel_mask = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; + volatile uint32_t timeout = 1000000; FDCAN_AbortTxRequest(p_drv->fdcan_x, cancel_mask); while ((p_drv->fdcan_x->TXBRP & cancel_mask) && --timeout) { @@ -515,15 +579,15 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure FDCAN_EnableInt(p_drv->fdcan_x, FDCAN_INT_RX_FIFO0_NEW_MESSAGE); /* Initialize TX Header cache */ - p_drv->tx_header.ID = 0x000000; - p_drv->tx_header.IdType = FDCAN_EXTENDED_ID; - p_drv->tx_header.TxFrameType = FDCAN_DATA_FRAME; - p_drv->tx_header.DataLength = FDCAN_DLC_BYTES_8; - p_drv->tx_header.ErrorState = FDCAN_ESI_ACTIVE; + p_drv->tx_header.ID = 0x000000; + p_drv->tx_header.IdType = FDCAN_EXTENDED_ID; + p_drv->tx_header.TxFrameType = FDCAN_DATA_FRAME; + p_drv->tx_header.DataLength = FDCAN_DLC_BYTES_8; + p_drv->tx_header.ErrorState = FDCAN_ESI_ACTIVE; p_drv->tx_header.BitRateSwitch = FDCAN_BRS_OFF; - p_drv->tx_header.FDFormat = FDCAN_CLASSIC_CAN; - p_drv->tx_header.TxEventFifo = FDCAN_NO_TX_EVENTS; - p_drv->tx_header.MsgMarker = 0; + p_drv->tx_header.FDFormat = FDCAN_CLASSIC_CAN; + p_drv->tx_header.TxEventFifo = FDCAN_NO_TX_EVENTS; + p_drv->tx_header.MsgMarker = 0; /* Start FDCAN */ FDCAN_Start(p_drv->fdcan_x); @@ -546,7 +610,7 @@ static rt_err_t _fdcan_configure(struct rt_can_device *can, struct can_configure *\*\ Pointer to RT-Thread filter configuration *\*\return RT_EOK on success, or negative error code on failure */ -static rt_err_t _fdcan_filter_config(struct n32_fdcan *p_drv, +static rt_err_t _fdcan_filter_config(struct n32_fdcan *p_drv, struct rt_can_filter_config *filter_cfg) { RT_ASSERT(p_drv != RT_NULL); @@ -557,12 +621,12 @@ static rt_err_t _fdcan_filter_config(struct n32_fdcan *p_drv, /* Set ID type */ if (filter_cfg->items[i].ide == RT_CAN_EXTID) { - p_drv->filter_cfg.IdType = FDCAN_EXTENDED_ID; + p_drv->filter_cfg.IdType = FDCAN_EXTENDED_ID; p_drv->filter_cfg.FilterIndex = filter_cfg->items[i].hdr_bank; } else { - p_drv->filter_cfg.IdType = FDCAN_STANDARD_ID; + p_drv->filter_cfg.IdType = FDCAN_STANDARD_ID; p_drv->filter_cfg.FilterIndex = filter_cfg->items[i].hdr_bank; } @@ -600,8 +664,8 @@ static rt_err_t _fdcan_filter_config(struct n32_fdcan *p_drv, */ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) { - rt_uint32_t argval; - struct n32_fdcan *p_drv; + rt_uint32_t argval; + struct n32_fdcan *p_drv; struct rt_can_filter_config *filter_cfg; RT_ASSERT(can != RT_NULL); @@ -712,7 +776,7 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) * (see _fdcan_configure() for the same pattern); the abort is * asynchronous, so poll TXBRP until it actually clears. */ { - rt_uint32_t cm = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; + rt_uint32_t cm = FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2; volatile uint32_t to = 1000000; FDCAN_AbortTxRequest(fdcan, cm); while ((fdcan->TXBRP & cm) && --to) @@ -725,26 +789,34 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) * effect (Bosch M_CAN: writes to CCE are ignored while INIT=0). * INIT must therefore be requested and confirmed first. */ fdcan->CCCR |= FDCAN_CCCR_INIT; - while ((fdcan->CCCR & FDCAN_CCCR_INIT) == 0) - ; + while ((fdcan->CCCR & FDCAN_CCCR_INIT) == 0); fdcan->CCCR |= FDCAN_CCCR_CCE; /* Clear previous mode bits */ fdcan->CCCR &= ~(FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM); if (argval == RT_CAN_MODE_LOOPBACK) + { fdcan->CCCR |= FDCAN_CCCR_TEST | FDCAN_CCCR_MON; + } else if (argval == RT_CAN_MODE_LISTEN) + { fdcan->CCCR |= FDCAN_CCCR_MON; + } else if (argval == RT_CAN_MODE_LOOPBACKANLISTEN) + { fdcan->CCCR |= FDCAN_CCCR_TEST; + } /* TEST.LBCK must follow CCCR.TEST: it is the bit that actually * routes TX back into RX for both internal and external loopback */ if (argval == RT_CAN_MODE_LOOPBACK || argval == RT_CAN_MODE_LOOPBACKANLISTEN) + { fdcan->TEST |= FDCAN_TEST_LBCK; + } else + { fdcan->TEST &= ~FDCAN_TEST_LBCK; + } fdcan->CCCR &= ~FDCAN_CCCR_INIT; - while (fdcan->CCCR & FDCAN_CCCR_INIT) - ; + while (fdcan->CCCR & FDCAN_CCCR_INIT); p_drv->device.config.mode = argval; LOG_I("%s: mode changed to %d", p_drv->name, argval); } @@ -777,8 +849,8 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) rt_uint32_t ecr_val = p_drv->fdcan_x->ECR; rt_uint32_t psr_val = p_drv->fdcan_x->PSR; - p_drv->device.status.rcverrcnt = (ecr_val >> 8) & 0x000000FF; - p_drv->device.status.snderrcnt = (ecr_val) & 0x000000FF; + p_drv->device.status.rcverrcnt = (ecr_val >> 8) & 0x000000FF; + p_drv->device.status.snderrcnt = (ecr_val) & 0x000000FF; p_drv->device.status.lasterrtype = psr_val & 0x00000007; rt_memcpy(arg, &p_drv->device.status, sizeof(p_drv->device.status)); @@ -826,9 +898,9 @@ static rt_err_t _fdcan_control(struct rt_can_device *can, int cmd, void *arg) */ static rt_ssize_t _fdcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_no) { - struct n32_fdcan *p_drv; + struct n32_fdcan *p_drv; struct rt_can_msg *p_msg; - ErrorStatus status; + ErrorStatus status; RT_ASSERT(can != RT_NULL); RT_ASSERT(buf != RT_NULL); @@ -888,8 +960,8 @@ static rt_ssize_t _fdcan_sendmsg(struct rt_can_device *can, const void *buf, rt_ /* FDCAN_TX_BUFFER0 is the single-bit mask for buffer 0; shift it to get * the mask for an arbitrary buffer index. */ rt_uint32_t buf_bit = FDCAN_TX_BUFFER0 << box_no; - status = FDCAN_AddMsgToTxBuffer(p_drv->fdcan_x, &p_drv->tx_header, - p_msg->data, buf_bit); + status = FDCAN_AddMsgToTxBuffer(p_drv->fdcan_x, &p_drv->tx_header, + p_msg->data, buf_bit); if (status != SUCCESS) { LOG_W("%s: FDCAN_AddMsgToTxBuffer failed, buf=%d", p_drv->name, box_no); @@ -921,8 +993,8 @@ static rt_ssize_t _fdcan_sendmsg(struct rt_can_device *can, const void *buf, rt_ static rt_ssize_t _fdcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) { struct rt_can_msg *p_msg; - struct n32_fdcan *p_drv; - ErrorStatus status; + struct n32_fdcan *p_drv; + ErrorStatus status; RT_ASSERT(can != RT_NULL); RT_ASSERT(buf != RT_NULL); @@ -987,7 +1059,7 @@ static rt_ssize_t _fdcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32 #ifdef RT_CAN_USING_CANFD /* Extract CAN FD flags */ p_msg->fd_frame = (p_drv->rx_header.FDFormat == FDCAN_FD_CAN) ? 1 : 0; - p_msg->brs = (p_drv->rx_header.BitRateSwitch == FDCAN_BRS_ON) ? 1 : 0; + p_msg->brs = (p_drv->rx_header.BitRateSwitch == FDCAN_BRS_ON) ? 1 : 0; #endif return sizeof(struct rt_can_msg); @@ -1009,10 +1081,10 @@ static rt_ssize_t _fdcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32 */ static rt_ssize_t _fdcan_sendmsg_nonblocking(struct rt_can_device *can, const void *buf) { - struct n32_fdcan *p_drv; + struct n32_fdcan *p_drv; struct rt_can_msg *p_msg; - ErrorStatus status; - int32_t free_buf = -1; + ErrorStatus status; + int32_t free_buf = -1; RT_ASSERT(can != RT_NULL); RT_ASSERT(buf != RT_NULL); @@ -1038,20 +1110,20 @@ static rt_ssize_t _fdcan_sendmsg_nonblocking(struct rt_can_device *can, const vo p_msg = (struct rt_can_msg *)buf; /* Set TX Header */ - p_drv->tx_header.IdType = (p_msg->ide == RT_CAN_EXTID) ? FDCAN_EXTENDED_ID : FDCAN_STANDARD_ID; + p_drv->tx_header.IdType = (p_msg->ide == RT_CAN_EXTID) ? FDCAN_EXTENDED_ID : FDCAN_STANDARD_ID; p_drv->tx_header.TxFrameType = (p_msg->rtr == RT_CAN_DTR) ? FDCAN_DATA_FRAME : FDCAN_REMOTE_FRAME; - p_drv->tx_header.ID = p_msg->id; - p_drv->tx_header.DataLength = _length_to_dlc(p_msg->len); + p_drv->tx_header.ID = p_msg->id; + p_drv->tx_header.DataLength = _length_to_dlc(p_msg->len); #ifdef RT_CAN_USING_CANFD - p_drv->tx_header.FDFormat = (p_msg->fd_frame == 1) ? FDCAN_FD_CAN : FDCAN_CLASSIC_CAN; + p_drv->tx_header.FDFormat = (p_msg->fd_frame == 1) ? FDCAN_FD_CAN : FDCAN_CLASSIC_CAN; p_drv->tx_header.BitRateSwitch = (p_msg->brs == 1) ? FDCAN_BRS_ON : FDCAN_BRS_OFF; #endif /* Write message to the free dedicated TX Buffer */ rt_uint32_t buf_bit = FDCAN_TX_BUFFER0 << free_buf; - status = FDCAN_AddMsgToTxBuffer(p_drv->fdcan_x, &p_drv->tx_header, - p_msg->data, buf_bit); + status = FDCAN_AddMsgToTxBuffer(p_drv->fdcan_x, &p_drv->tx_header, + p_msg->data, buf_bit); if (status != SUCCESS) { return -RT_EBUSY; @@ -1069,10 +1141,10 @@ static rt_ssize_t _fdcan_sendmsg_nonblocking(struct rt_can_device *can, const vo *============================================================================*/ static const struct rt_can_ops _fdcan_ops = { - .configure = _fdcan_configure, - .control = _fdcan_control, - .sendmsg = _fdcan_sendmsg, - .recvmsg = _fdcan_recvmsg, + .configure = _fdcan_configure, + .control = _fdcan_control, + .sendmsg = _fdcan_sendmsg, + .recvmsg = _fdcan_recvmsg, .sendmsg_nonblocking = _fdcan_sendmsg_nonblocking, }; @@ -1115,8 +1187,8 @@ static void _fdcan_int0_isr(struct n32_fdcan *p_drv) static void _fdcan_int1_isr(struct n32_fdcan *p_drv) { FDCAN_Module *fdcan = p_drv->fdcan_x; - rt_uint32_t ecr_val; - rt_uint32_t psr_val; + rt_uint32_t ecr_val; + rt_uint32_t psr_val; /* Check TX Complete flag */ if (FDCAN_GetFlag(fdcan, FDCAN_FLAG_TX_COMPLETE) == SET) @@ -1131,7 +1203,7 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) * our software pending mask and look for buffers whose TXBRP * was just cleared by the hardware (pending → !pending). */ rt_uint32_t buffer_idx = 0; - rt_bool_t found = RT_FALSE; + rt_bool_t found = RT_FALSE; for (rt_uint32_t i = 0; i < FDCAN_TX_BUF_NUM; i++) { @@ -1139,8 +1211,8 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) if ((p_drv->tx_pending_mask & bit) && !(fdcan->TXBRP & bit)) { p_drv->tx_pending_mask &= ~bit; - buffer_idx = i; - found = RT_TRUE; + buffer_idx = i; + found = RT_TRUE; break; } } @@ -1156,15 +1228,17 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) if (p_drv->tx_pending_mask & bit) { p_drv->tx_pending_mask &= ~bit; - buffer_idx = i; - found = RT_TRUE; + buffer_idx = i; + found = RT_TRUE; break; } } } if (found) + { rt_hw_can_isr(&p_drv->device, RT_CAN_EVENT_TX_DONE | (buffer_idx << 8)); + } } /* IR.EW/EP/PEA are bus protocol *status* change notifications, not @@ -1211,9 +1285,9 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) if (fdcan->CCCR & FDCAN_CCCR_INIT) { /* Bus-Off state: set CCE, clear INIT to trigger recovery sequence */ - fdcan->CCCR |= FDCAN_CCCR_CCE; - fdcan->CCCR &= ~FDCAN_CCCR_INIT; - p_drv->device.status.errcode = 0xFF; + fdcan->CCCR |= FDCAN_CCCR_CCE; + fdcan->CCCR &= ~FDCAN_CCCR_INIT; + p_drv->device.status.errcode = 0xFF; } else { @@ -1221,8 +1295,8 @@ static void _fdcan_int1_isr(struct n32_fdcan *p_drv) ecr_val = fdcan->ECR; psr_val = fdcan->PSR; - p_drv->device.status.rcverrcnt = (ecr_val >> 8) & 0x000000FF; - p_drv->device.status.snderrcnt = (ecr_val) & 0x000000FF; + p_drv->device.status.rcverrcnt = (ecr_val >> 8) & 0x000000FF; + p_drv->device.status.snderrcnt = (ecr_val) & 0x000000FF; p_drv->device.status.lasterrtype = psr_val & 0x00000007; } } @@ -1390,15 +1464,15 @@ void FDCAN8_INT1_IRQHandler(void) static int rt_hw_fdcan_init(void) { struct can_configure config; - FDCAN_FilterType default_filter; + FDCAN_FilterType default_filter; /* Default CAN configuration */ - config.baud_rate = CAN1MBaud; - config.msgboxsz = RT_CANMSG_BOX_SZ; + config.baud_rate = CAN1MBaud; + config.msgboxsz = RT_CANMSG_BOX_SZ; config.sndboxnumber = FDCAN_TX_BUF_NUM; - config.mode = RT_CAN_MODE_NORMAL; - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; + config.mode = RT_CAN_MODE_NORMAL; + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; #ifdef RT_CAN_USING_HDR config.maxhdr = 14; #endif @@ -1408,73 +1482,73 @@ static int rt_hw_fdcan_init(void) #endif /* Default filter: accept all standard frames into RX FIFO0 */ - default_filter.IdType = FDCAN_STANDARD_ID; - default_filter.FilterIndex = 0; - default_filter.FilterType = FDCAN_FILTER_MASK; - default_filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; - default_filter.FilterID1 = 0x000; - default_filter.FilterID2 = 0x000; + default_filter.IdType = FDCAN_STANDARD_ID; + default_filter.FilterIndex = 0; + default_filter.FilterType = FDCAN_FILTER_MASK; + default_filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + default_filter.FilterID1 = 0x000; + default_filter.FilterID2 = 0x000; default_filter.RxBufferIndex = 0; #ifdef BSP_USING_FDCAN1 - _drv_fdcan1.fdcan_x = FDCAN1; - _drv_fdcan1.filter_cfg = default_filter; + _drv_fdcan1.fdcan_x = FDCAN1; + _drv_fdcan1.filter_cfg = default_filter; _drv_fdcan1.device.config = config; rt_hw_can_register(&_drv_fdcan1.device, _drv_fdcan1.name, &_fdcan_ops, &_drv_fdcan1); LOG_I("FDCAN1 registered"); #endif #ifdef BSP_USING_FDCAN2 - _drv_fdcan2.fdcan_x = FDCAN2; - _drv_fdcan2.filter_cfg = default_filter; + _drv_fdcan2.fdcan_x = FDCAN2; + _drv_fdcan2.filter_cfg = default_filter; _drv_fdcan2.device.config = config; rt_hw_can_register(&_drv_fdcan2.device, _drv_fdcan2.name, &_fdcan_ops, &_drv_fdcan2); LOG_I("FDCAN2 registered"); #endif #ifdef BSP_USING_FDCAN3 - _drv_fdcan3.fdcan_x = FDCAN3; - _drv_fdcan3.filter_cfg = default_filter; + _drv_fdcan3.fdcan_x = FDCAN3; + _drv_fdcan3.filter_cfg = default_filter; _drv_fdcan3.device.config = config; rt_hw_can_register(&_drv_fdcan3.device, _drv_fdcan3.name, &_fdcan_ops, &_drv_fdcan3); LOG_I("FDCAN3 registered"); #endif #ifdef BSP_USING_FDCAN4 - _drv_fdcan4.fdcan_x = FDCAN4; - _drv_fdcan4.filter_cfg = default_filter; + _drv_fdcan4.fdcan_x = FDCAN4; + _drv_fdcan4.filter_cfg = default_filter; _drv_fdcan4.device.config = config; rt_hw_can_register(&_drv_fdcan4.device, _drv_fdcan4.name, &_fdcan_ops, &_drv_fdcan4); LOG_I("FDCAN4 registered"); #endif #ifdef BSP_USING_FDCAN5 - _drv_fdcan5.fdcan_x = FDCAN5; - _drv_fdcan5.filter_cfg = default_filter; + _drv_fdcan5.fdcan_x = FDCAN5; + _drv_fdcan5.filter_cfg = default_filter; _drv_fdcan5.device.config = config; rt_hw_can_register(&_drv_fdcan5.device, _drv_fdcan5.name, &_fdcan_ops, &_drv_fdcan5); LOG_I("FDCAN5 registered"); #endif #ifdef BSP_USING_FDCAN6 - _drv_fdcan6.fdcan_x = FDCAN6; - _drv_fdcan6.filter_cfg = default_filter; + _drv_fdcan6.fdcan_x = FDCAN6; + _drv_fdcan6.filter_cfg = default_filter; _drv_fdcan6.device.config = config; rt_hw_can_register(&_drv_fdcan6.device, _drv_fdcan6.name, &_fdcan_ops, &_drv_fdcan6); LOG_I("FDCAN6 registered"); #endif #ifdef BSP_USING_FDCAN7 - _drv_fdcan7.fdcan_x = FDCAN7; - _drv_fdcan7.filter_cfg = default_filter; + _drv_fdcan7.fdcan_x = FDCAN7; + _drv_fdcan7.filter_cfg = default_filter; _drv_fdcan7.device.config = config; rt_hw_can_register(&_drv_fdcan7.device, _drv_fdcan7.name, &_fdcan_ops, &_drv_fdcan7); LOG_I("FDCAN7 registered"); #endif #ifdef BSP_USING_FDCAN8 - _drv_fdcan8.fdcan_x = FDCAN8; - _drv_fdcan8.filter_cfg = default_filter; + _drv_fdcan8.fdcan_x = FDCAN8; + _drv_fdcan8.filter_cfg = default_filter; _drv_fdcan8.device.config = config; rt_hw_can_register(&_drv_fdcan8.device, _drv_fdcan8.name, &_fdcan_ops, &_drv_fdcan8); LOG_I("FDCAN8 registered"); diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c index 543ec8d375..355352795e 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c @@ -79,7 +79,7 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) */ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_EOK; rt_uint32_t end_addr = addr + size; if ((end_addr) > N32_FLASH_END_ADDRESS) @@ -118,7 +118,7 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) */ int n32_flash_erase(rt_uint32_t addr, size_t size) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_EOK; rt_uint32_t end_addr = addr + size; rt_uint32_t erase_addr; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c index 049d489a1d..f63d680db4 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c @@ -17,10 +17,10 @@ #define PIN_PORT(pin) ((uint8_t)(((pin) >> 4U) & 0xFU)) #define PIN_NO(pin) ((uint8_t)((pin) & 0xFU)) -#define PIN_STPORT(pin) ((GPIO_Module *)(GPIOA_BASE + (0x400U * PIN_PORT(pin)))) -#define PIN_STPIN(pin) ((uint16_t)(1U << PIN_NO(pin))) +#define PIN_STPORT(pin) ((GPIO_Module *)(GPIOA_BASE + (0x400U * PIN_PORT(pin)))) +#define PIN_STPIN(pin) ((uint16_t)(1U << PIN_NO(pin))) -#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) +#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) static uint32_t pin_irq_enable_mask = 0; @@ -29,9 +29,9 @@ static uint32_t pin_irq_enable_mask = 0; #define __N32_PORT_MAX 8u #endif #elif defined(GPIOJ) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOI) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOH) #if defined(SOC_SERIES_N32H7xx) #define __N32_PORT_MAX 16u @@ -41,64 +41,62 @@ static uint32_t pin_irq_enable_mask = 0; #define __N32_PORT_MAX 7u #endif #elif defined(GPIOG) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOF) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOE) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOD) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOC) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOB) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #elif defined(GPIOA) - #define __N32_PORT_MAX 16u +#define __N32_PORT_MAX 16u #else - #define __N32_PORT_MAX 0u - #error Unsupported N32 GPIO peripheral. +#define __N32_PORT_MAX 0u +#error Unsupported N32 GPIO peripheral. #endif #define PIN_STPORT_MAX __N32_PORT_MAX -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI_LINE0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI_LINE1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI_LINE2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI_LINE3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI_LINE4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI_LINE5, EXTI9_5_IRQn}, - {GPIO_PIN_6, EXTI_LINE6, EXTI9_5_IRQn}, - {GPIO_PIN_7, EXTI_LINE7, EXTI9_5_IRQn}, - {GPIO_PIN_8, EXTI_LINE8, EXTI9_5_IRQn}, - {GPIO_PIN_9, EXTI_LINE9, EXTI9_5_IRQn}, - {GPIO_PIN_10, EXTI_LINE10, EXTI15_10_IRQn}, - {GPIO_PIN_11, EXTI_LINE11, EXTI15_10_IRQn}, - {GPIO_PIN_12, EXTI_LINE12, EXTI15_10_IRQn}, - {GPIO_PIN_13, EXTI_LINE13, EXTI15_10_IRQn}, - {GPIO_PIN_14, EXTI_LINE14, EXTI15_10_IRQn}, - {GPIO_PIN_15, EXTI_LINE15, EXTI15_10_IRQn}, +static const struct pin_irq_map pin_irq_map[] = { + { GPIO_PIN_0, EXTI_LINE0, EXTI0_IRQn }, + { GPIO_PIN_1, EXTI_LINE1, EXTI1_IRQn }, + { GPIO_PIN_2, EXTI_LINE2, EXTI2_IRQn }, + { GPIO_PIN_3, EXTI_LINE3, EXTI3_IRQn }, + { GPIO_PIN_4, EXTI_LINE4, EXTI4_IRQn }, + { GPIO_PIN_5, EXTI_LINE5, EXTI9_5_IRQn }, + { GPIO_PIN_6, EXTI_LINE6, EXTI9_5_IRQn }, + { GPIO_PIN_7, EXTI_LINE7, EXTI9_5_IRQn }, + { GPIO_PIN_8, EXTI_LINE8, EXTI9_5_IRQn }, + { GPIO_PIN_9, EXTI_LINE9, EXTI9_5_IRQn }, + { GPIO_PIN_10, EXTI_LINE10, EXTI15_10_IRQn }, + { GPIO_PIN_11, EXTI_LINE11, EXTI15_10_IRQn }, + { GPIO_PIN_12, EXTI_LINE12, EXTI15_10_IRQn }, + { GPIO_PIN_13, EXTI_LINE13, EXTI15_10_IRQn }, + { GPIO_PIN_14, EXTI_LINE14, EXTI15_10_IRQn }, + { GPIO_PIN_15, EXTI_LINE15, EXTI15_10_IRQn }, }; -static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, }; /* e.g. PA.0 */ @@ -283,9 +281,9 @@ static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_base_t pin, level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) { rt_hw_interrupt_enable(level); return RT_EOK; @@ -458,8 +456,7 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_EOK; } -static const struct rt_pin_ops _n32_pin_ops = -{ +static const struct rt_pin_ops _n32_pin_ops = { n32_pin_mode, n32_pin_write, n32_pin_read, diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c new file mode 100644 index 0000000000..f8faaba0b5 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2006-2025 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-07-08 ox-horse first version + */ + +#include <board.h> + +#ifdef BSP_USING_LCD +#include <rtdevice.h> +#include <string.h> +#include "n32h7xx_lcdc.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.lcd" +#include <drv_log.h> + +#define LCD_BUF_SIZE (BSP_LCD_WIDTH_PIXEL * BSP_LCD_HEIGHT_PIXEL * BSP_BITS_PER_PIXEL / 8U) +#define LCD_DEVICE(dev) (struct drv_lcd_device *)(dev) + +struct drv_lcd_device +{ + struct rt_device parent; + + struct rt_device_graphic_info lcd_info; + + struct rt_semaphore lcd_lock; +}; + +struct drv_lcd_device _lcd; + +static rt_err_t drv_lcd_init(struct rt_device *device) +{ + struct drv_lcd_device *lcd = LCD_DEVICE(device); + /* nothing, right now */ + (void)lcd; + return RT_EOK; +} + +static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args) +{ + struct drv_lcd_device *lcd = LCD_DEVICE(device); + + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + if (rt_sem_take(&_lcd.lcd_lock, RT_TICK_PER_SECOND / 20) != RT_EOK) + { + LOG_E("lcd frame update timeout"); + return -RT_ETIMEOUT; + } + LCDC_ReloadConfig(LCDC_VBRELOAD); + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = lcd->lcd_info.pixel_format; + info->bits_per_pixel = lcd->lcd_info.bits_per_pixel; + info->width = lcd->lcd_info.width; + info->height = lcd->lcd_info.height; + info->framebuffer = lcd->lcd_info.framebuffer; + } + break; + + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + +/** + * LCDC event interrupt handler. Handles: + * - Line interrupt (LI): fired at configured scan line position + * - FIFO underrun interrupt (FU): FIFO empty during active data phase + * - Register reload interrupt (RR): fired after vertical blanking reload, used for frame sync + */ +void LCD_EV_IRQHandler(void) +{ + rt_interrupt_enter(); + + /* Line interrupt: triggered at configured scan line position */ + if (LCDC_GetFlagStatus(LCDC_FLAG_L)) + { + LCDC_ClearFlag(LCDC_FLAG_L); + } + + /* FIFO underrun: FIFO empty during active data phase */ + if (LCDC_GetFlagStatus(LCDC_FLAG_FU)) + { + LCDC_ClearFlag(LCDC_FLAG_FU); + LOG_E("LCDC FIFO underrun"); + } + + /* Register reload complete: release semaphore for frame sync */ + if (LCDC_GetFlagStatus(LCDC_FLAG_RR)) + { + LCDC_ClearFlag(LCDC_FLAG_RR); + rt_sem_release(&_lcd.lcd_lock); + } + + rt_interrupt_leave(); +} + +/** + * LCDC error interrupt handler. Handles: + * - BUS error interrupt (BE): AHB bus error during transfer + */ +void LCD_ER_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (LCDC_GetFlagStatus(LCDC_FLAG_BE)) + { + LCDC_ClearFlag(LCDC_FLAG_BE); + LOG_E("LCDC AHB bus error"); + } + + rt_interrupt_leave(); +} + +/** + * Configure LCDC power domain, peripheral clocks and pixel clock. + * This function provides a default configuration for N32H7xx HMI boards. + * Override this function at the board level if different clock settings are needed. + */ +rt_weak void n32_lcd_clock_config(void) +{ + /* Enable LCDC power domain */ + PWR_MoudlePowerEnable(GRAPHIC_LCDC_PWRCTRL, ENABLE); + + /* Enable LCDC AXI peripheral clocks (LCDC core, low-power, APB, APB low-power) */ + RCC_EnableAXIPeriphClk2(RCC_AXI_PERIPHEN_M7_LCDC | RCC_AXI_PERIPHEN_M7_LCDCLP | + RCC_AXI_PERIPHEN_M7_LCDCAPB | RCC_AXI_PERIPHEN_M7_LCDCAPBLP, + ENABLE); + + /* Configure pixel clock source: AXI divided by 8 (600MHz / 8 = 75MHz) */ + RCC_ConfigLCDCPixelClk(RCC_LCDCPIXELCLK_SRC_AXIDIV, RCC_LCDCPIXELCLK_AXIDIV8); +} + +static rt_err_t n32_lcd_init(struct drv_lcd_device *lcd) +{ + LCDC_InitType LCDC_InitStruct; + LCDC_Layer_InitType LCDC_Layer_InitStruct; + + /* Configure LCDC power and clocks */ + n32_lcd_clock_config(); + + /* Initialize structs with default values */ + LCDC_StructInit(&LCDC_InitStruct); + LCDC_LayerStructInit(&LCDC_Layer_InitStruct); + + /* Polarity configuration */ + LCDC_InitStruct.LCDC_HSPolarity = LCDC_HSPOLARITY_LOW; + LCDC_InitStruct.LCDC_VSPolarity = LCDC_VSPOLARITY_LOW; + LCDC_InitStruct.LCDC_DEPolarity = LCDC_DEPOLARITY_LOW; + LCDC_InitStruct.LCDC_PCPolarity = LCDC_PCPOLARITY_IPC; + + /* Timing configuration */ + /* Horizontal synchronization width = HSW - 1 */ + LCDC_InitStruct.LCDC_HorizontalSync = BSP_LCD_HSYNC_WIDTH_PIXEL - 1; + /* Vertical synchronization height = VSW - 1 */ + LCDC_InitStruct.LCDC_VerticalSync = BSP_LCD_VSYNC_HEIGHT_PIXEL - 1; + /* Accumulated horizontal back porch = HSW + HBP - 1 */ + LCDC_InitStruct.LCDC_AccumulatedHBP = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL - 1; + /* Accumulated vertical back porch = VSW + VBP - 1 */ + LCDC_InitStruct.LCDC_AccumulatedVBP = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL - 1; + /* Accumulated active width = HSW + HBP + Active Width - 1 */ + LCDC_InitStruct.LCDC_AccumulatedActiveW = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL + lcd->lcd_info.width - 1; + /* Accumulated active height = VSW + VBP + Active Height - 1 */ + LCDC_InitStruct.LCDC_AccumulatedActiveH = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL + lcd->lcd_info.height - 1; + /* Total height = VSW + VBP + Active Height + VFP - 1 */ + LCDC_InitStruct.LCDC_TotalHeight = LCDC_InitStruct.LCDC_AccumulatedActiveH + BSP_LCD_VFP_PIXEL; + /* Total width = HSW + HBP + Active Width + HFP - 1 */ + LCDC_InitStruct.LCDC_TotalWidth = LCDC_InitStruct.LCDC_AccumulatedActiveW + BSP_LCD_HFP_PIXEL; + + /* Configure R,G,B component values for LCD background color: black */ + LCDC_InitStruct.LCDC_BackgroundRedValue = 0; + LCDC_InitStruct.LCDC_BackgroundGreenValue = 0; + LCDC_InitStruct.LCDC_BackgroundBlueValue = 0; + + /* Initialize LCDC global registers */ + LCDC_Init(&LCDC_InitStruct); + + /* Layer 1 Configuration */ + + /* Windowing configuration */ + LCDC_Layer_InitStruct.LCDC_HorizontalStart = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL; + LCDC_Layer_InitStruct.LCDC_HorizontalStop = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL + lcd->lcd_info.width - 1; + LCDC_Layer_InitStruct.LCDC_VerticalStart = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL; + LCDC_Layer_InitStruct.LCDC_VerticalStop = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL + lcd->lcd_info.height - 1; + + /* Pixel Format configuration */ + if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_RGB565; + } + else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_ARGB8888; + } + else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB888) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_RGB888; + } + else + { + LOG_E("unsupported pixel format"); + return -RT_ERROR; + } + + /* Start Address configuration: point LCDC directly at framebuffer (zero-copy) */ + LCDC_Layer_InitStruct.LCDC_CFBStartAdress = (uint32_t)lcd->lcd_info.framebuffer; + + /* Alpha constant (255 = totally opaque) */ + LCDC_Layer_InitStruct.LCDC_ConstantAlpha = 255; + + /* Default Color configuration */ + LCDC_Layer_InitStruct.LCDC_DefaultAlpha = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorRed = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorGreen = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorBlue = 0xFF; + + /* Configure blending factors: Constant Alpha blending */ + LCDC_Layer_InitStruct.LCDC_BlendingFactor1 = LCDC_BLENDING_FACTOR1_CA; + LCDC_Layer_InitStruct.LCDC_BlendingFactor2 = LCDC_BLENDING_FACTOR2_CA; + + /* Configure the line length, pitch and number of lines */ + LCDC_Layer_InitStruct.LCDC_CFBLineLength = (lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8)) + 7; + LCDC_Layer_InitStruct.LCDC_CFBPitch = lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8); + LCDC_Layer_InitStruct.LCDC_CFBLineNumber = lcd->lcd_info.height; + + /* Initialize LCDC Layer 1 */ + LCDC_LayerInit(LCDC_Layer1, &LCDC_Layer_InitStruct); + + /* Reload layer config immediately */ + LCDC_LayerReloadConfig(LCDC_Layer1, LCDC_LAYER_IMRELOAD); + + /* Enable Layer 1 */ + LCDC_LayerEnable(LCDC_Layer1, ENABLE); + + /* Reload layer config again after enable */ + LCDC_LayerReloadConfig(LCDC_Layer1, LCDC_LAYER_IMRELOAD); + + /* Enable LCDC */ + LCDC_Enable(ENABLE); + + /* Configure line interrupt to trigger at last active line (reserved for TE sync) */ + LCDC_LINTPConfig(LCDC_InitStruct.LCDC_AccumulatedActiveH); + + /* Enable LCDC event interrupts: RR (frame sync), LI (line interrupt), FU (FIFO underrun) */ + LCDC_ConfigInt(LCDC_INT_RRIEN | LCDC_INT_LIEN | LCDC_INT_FUIEN, ENABLE); + + /* Enable LCDC error interrupts: BE (AHB bus error) */ + LCDC_ConfigInt(LCDC_INT_BEIEN, ENABLE); + + /* Configure NVIC for LCDC event and error interrupts */ + NVIC_SetPriority(LCD_EV_IRQn, 1); + NVIC_EnableIRQ(LCD_EV_IRQn); + NVIC_SetPriority(LCD_ER_IRQn, 1); + NVIC_EnableIRQ(LCD_ER_IRQn); + + LOG_D("LCDC init success"); + return RT_EOK; +} + +#if defined(BSP_LCD_BACKLIGHT_USING_PWM) +void turn_on_lcd_backlight(void) +{ + struct rt_device_pwm *pwm_dev; + + /* turn on the LCD backlight */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(BSP_LCD_PWM_DEV_NAME); + /* pwm frequency: 100K = 10000ns */ + rt_pwm_set(pwm_dev, BSP_LCD_PWM_DEV_CHANNEL, 10000, 10000); + rt_pwm_enable(pwm_dev, BSP_LCD_PWM_DEV_CHANNEL); +} +#elif defined(BSP_LCD_BACKLIGHT_USING_GPIO) +void turn_on_lcd_backlight(void) +{ + rt_pin_mode(BSP_LCD_BACKLIGHT_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(BSP_LCD_DISPLAY_PIN, PIN_MODE_OUTPUT); + + rt_pin_write(BSP_LCD_DISPLAY_PIN, PIN_HIGH); + rt_pin_write(BSP_LCD_BACKLIGHT_PIN, PIN_HIGH); +} +#else +void turn_on_lcd_backlight(void) +{ +} +#endif + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops lcd_ops = { + drv_lcd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + drv_lcd_control +}; +#endif + +int drv_lcd_hw_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device = &_lcd.parent; + + /* memset _lcd to zero */ + memset(&_lcd, 0x00, sizeof(_lcd)); + + /* init lcd_lock semaphore, initial value 1 so the first frame update can proceed */ + result = rt_sem_init(&_lcd.lcd_lock, "lcd_lock", 1, RT_IPC_FLAG_FIFO); + if (result != RT_EOK) + { + LOG_E("init semaphore failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* config LCD dev info */ + _lcd.lcd_info.height = BSP_LCD_HEIGHT_PIXEL; + _lcd.lcd_info.width = BSP_LCD_WIDTH_PIXEL; + _lcd.lcd_info.bits_per_pixel = BSP_BITS_PER_PIXEL; + +#if defined(BSP_LCD_PIXEL_FORMAT_RGB565) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; +#elif defined(BSP_LCD_PIXEL_FORMAT_ARGB8888) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888; +#elif defined(BSP_LCD_PIXEL_FORMAT_RGB888) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; +#endif + + /* malloc single framebuffer (zero-copy, LCDC points directly to this buffer) */ + _lcd.lcd_info.framebuffer = rt_malloc_align(LCD_BUF_SIZE, 64); + if (_lcd.lcd_info.framebuffer == RT_NULL) + { + LOG_E("init frame buffer failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* memset buff to 0xFF (white) */ + memset(_lcd.lcd_info.framebuffer, 0xFF, LCD_BUF_SIZE); + + device->type = RT_Device_Class_Graphic; +#ifdef RT_USING_DEVICE_OPS + device->ops = &lcd_ops; +#else + device->init = drv_lcd_init; + device->control = drv_lcd_control; +#endif + + /* register lcd device */ + rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR); + + /* init N32 LCDC */ + if (n32_lcd_init(&_lcd) != RT_EOK) + { + LOG_E("lcd hardware init failed"); + result = -RT_ERROR; + goto __exit; + } + else + { + turn_on_lcd_backlight(); + } + +__exit: + if (result != RT_EOK) + { + rt_sem_detach(&_lcd.lcd_lock); + + if (_lcd.lcd_info.framebuffer) + { + rt_free_align(_lcd.lcd_info.framebuffer); + } + } + return result; +} +INIT_DEVICE_EXPORT(drv_lcd_hw_init); + + +#endif /* BSP_USING_LCD */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c index 6777f0be2f..3964a3996a 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c @@ -44,9 +44,9 @@ enum struct n32_hw_lptimer { rt_clock_timer_t time_device; - LPTIM_Module *timer; - IRQn_Type tim_irqn; - char *name; + LPTIM_Module *timer; + IRQn_Type tim_irqn; + char *name; }; static struct n32_hw_lptimer n32_hw_lptimer_obj[] = { @@ -143,17 +143,29 @@ static void n32_lptim_enable_clock(LPTIM_Module *timer) static uint32_t n32_lptim_get_exti_line(LPTIM_Module *timer) { if (timer == LPTIM1) + { return EXTI_LINE66; + } else if (timer == LPTIM2) + { return EXTI_LINE67; + } else if (timer == LPTIM3) + { return EXTI_LINE68; + } else if (timer == LPTIM4) + { return EXTI_LINE69; + } else if (timer == LPTIM5) + { return EXTI_LINE86; + } else + { return 0; + } } /** @@ -163,13 +175,15 @@ static void n32_lptim_exti_config(LPTIM_Module *timer) { uint32_t exti_line = n32_lptim_get_exti_line(timer); if (exti_line == 0) + { return; + } EXTI_InitType EXTI_InitStructure; EXTI_InitStruct(&EXTI_InitStructure); - EXTI_InitStructure.EXTI_Line = exti_line; + EXTI_InitStructure.EXTI_Line = exti_line; EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitPeripheral(&EXTI_InitStructure); } @@ -199,7 +213,7 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) if (state) { struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device); - LPTIM_Module *lptim = tim_device->timer; + LPTIM_Module *lptim = tim_device->timer; if (tim_device == RT_NULL) { @@ -216,8 +230,7 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) RCC_EnableLsi(ENABLE); /* Wait for LSI ready */ - while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET) - ; + while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET); /* Select LSI as LPTIM clock source */ n32_lptim_clock_source_config(lptim); @@ -229,7 +242,7 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) LPTIM_InitType lptim_init; LPTIM_StructInit(&lptim_init); lptim_init.ClockSource = LPTIM_CLK_SOURCE_INTERNAL; - lptim_init.Prescaler = LPTIM_PRESCALER_DIV32; + lptim_init.Prescaler = LPTIM_PRESCALER_DIV32; if (LPTIM_Init(lptim, &lptim_init) != SUCCESS) { @@ -262,7 +275,7 @@ static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_tim } struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device); - LPTIM_Module *lptim = tim_device->timer; + LPTIM_Module *lptim = tim_device->timer; if (tim_device == RT_NULL) { @@ -310,7 +323,7 @@ static void timer_stop(rt_clock_timer_t *timer) } struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device); - LPTIM_Module *lptim = tim_device->timer; + LPTIM_Module *lptim = tim_device->timer; if (tim_device == RT_NULL) { @@ -355,7 +368,7 @@ static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) } struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device); - LPTIM_Module *lptim = tim_device->timer; + LPTIM_Module *lptim = tim_device->timer; if (tim_device == RT_NULL) { @@ -474,11 +487,11 @@ void LPTIM5_WKUP_IRQHandler(void) #endif static const struct rt_clock_timer_ops _ops = { - .init = timer_init, - .start = timer_start, - .stop = timer_stop, + .init = timer_init, + .start = timer_start, + .stop = timer_stop, .count_get = timer_counter_get, - .control = timer_ctrl, + .control = timer_ctrl, }; /** @@ -486,13 +499,13 @@ static const struct rt_clock_timer_ops _ops = { */ static int n32_hw_lptim_init(void) { - int i = 0; + int i = 0; int result = RT_EOK; for (i = 0; i < sizeof(n32_hw_lptimer_obj) / sizeof(n32_hw_lptimer_obj[0]); i++) { n32_hw_lptimer_obj[i].time_device.info = &_info; - n32_hw_lptimer_obj[i].time_device.ops = &_ops; + n32_hw_lptimer_obj[i].time_device.ops = &_ops; if (rt_clock_timer_register(&n32_hw_lptimer_obj[i].time_device, n32_hw_lptimer_obj[i].name, &n32_hw_lptimer_obj[i].timer) == RT_EOK) { diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c index 60f74043c1..4f611b727c 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c @@ -160,7 +160,7 @@ static rt_err_t rt_nand_init(void) { uint32_t reset_cmd; - reset_cmd = NAND_BANK_ADDR | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_RESET << 3); + reset_cmd = NAND_BANK_ADDR | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_RESET << 3); *((__IO uint16_t *)reset_cmd) = 0x0000; } #endif @@ -207,15 +207,15 @@ static rt_err_t nand_check_status(uint32_t bank_addr) { uint32_t timeout = 0x100000; uint32_t cmd, stat_addr; - uint8_t status; + uint8_t status; - cmd = bank_addr | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_STATUS << 3); + cmd = bank_addr | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_STATUS << 3); stat_addr = bank_addr | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE; do { *((__IO uint8_t *)cmd) = 0x00; - status = *(__IO uint8_t *)(stat_addr); + status = *(__IO uint8_t *)(stat_addr); if (status & NAND_STATUS_ERROR) { @@ -246,11 +246,11 @@ static rt_err_t nand_check_status(uint32_t bank_addr) */ static rt_err_t _read_id(struct rt_mtd_nand_device *device) { - uint32_t cmd_addr, data_addr; - uint8_t id_bytes[5]; + uint32_t cmd_addr, data_addr; + uint8_t id_bytes[5]; rt_uint32_t id; - cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(1) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_READ_ID << 3); + cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(1) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_READ_ID << 3); data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE; *((__IO uint8_t *)cmd_addr) = 0x00; @@ -265,7 +265,7 @@ static rt_err_t _read_id(struct rt_mtd_nand_device *device) id_bytes[0], id_bytes[1], id_bytes[2], id_bytes[3], id_bytes[4]); /* Pack bytes 1-4 into 32-bit return value (byte 0 = Maker ID, discarded) */ - id = (rt_uint32_t)id_bytes[1] << 24; + id = (rt_uint32_t)id_bytes[1] << 24; id |= (rt_uint32_t)id_bytes[2] << 16; id |= (rt_uint32_t)id_bytes[3] << 8; id |= (rt_uint32_t)id_bytes[4]; @@ -275,7 +275,7 @@ static rt_err_t _read_id(struct rt_mtd_nand_device *device) /* read one page (data + spare) */ static rt_err_t _read_page(struct rt_mtd_nand_device *device, - rt_off_t page, + rt_off_t page, rt_uint8_t *data, rt_uint32_t data_len, rt_uint8_t *spare, rt_uint32_t spare_len) { @@ -313,13 +313,13 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, if (data && data_len) { uint32_t *p32; - uint32_t word_cnt; + uint32_t word_cnt; data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE; /* 32-bit aligned bulk */ word_cnt = data_len / 4; - p32 = (uint32_t *)data; + p32 = (uint32_t *)data; for (i = 0; i < word_cnt; i++) { p32[i] = *((__IO uint32_t *)data_addr); @@ -344,7 +344,7 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, /* write one page (data + spare) */ static rt_err_t _write_page(struct rt_mtd_nand_device *device, - rt_off_t page, + rt_off_t page, const rt_uint8_t *data, rt_uint32_t data_len, const rt_uint8_t *spare, rt_uint32_t spare_len) { @@ -371,9 +371,9 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, uint32_t word_cnt, remain_start; addr_no_end = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE; - addr_end = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE; + addr_end = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE; - word_cnt = data_len / 4; + word_cnt = data_len / 4; remain_start = word_cnt * 4; /* @@ -413,7 +413,7 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, } else { - data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE; + data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE; *((__IO uint8_t *)data_addr) = 0x00; } @@ -553,7 +553,7 @@ int rt_hw_nand_init(void) } _nand_dev.page_size = BSP_NAND_PAGE_SIZE; - _nand_dev.oob_size = BSP_NAND_OOB_SIZE; + _nand_dev.oob_size = BSP_NAND_OOB_SIZE; /* * oob_free: bytes in the spare area available for the upper layer. * @@ -566,14 +566,14 @@ int rt_hw_nand_init(void) * The remaining oob_free bytes are available for bad block markers, * wear-leveling metadata, and filesystem bookkeeping. */ - _nand_dev.oob_free = OOB_FREE(BSP_NAND_PAGE_SIZE, BSP_NAND_OOB_SIZE); + _nand_dev.oob_free = OOB_FREE(BSP_NAND_PAGE_SIZE, BSP_NAND_OOB_SIZE); _nand_dev.pages_per_block = BSP_NAND_PAGES_PER_BLOCK; - _nand_dev.plane_num = BSP_NAND_PLANE_NUM; - _nand_dev.block_start = 0; - _nand_dev.block_end = BSP_NAND_BLOCK_COUNT; - _nand_dev.block_total = _nand_dev.block_end - _nand_dev.block_start; - _nand_dev.ops = &_nand_ops; - _nand_dev.priv = RT_NULL; + _nand_dev.plane_num = BSP_NAND_PLANE_NUM; + _nand_dev.block_start = 0; + _nand_dev.block_end = BSP_NAND_BLOCK_COUNT; + _nand_dev.block_total = _nand_dev.block_end - _nand_dev.block_start; + _nand_dev.ops = &_nand_ops; + _nand_dev.priv = RT_NULL; result = rt_mtd_nand_register_device("nand0", &_nand_dev); if (result != RT_EOK) diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pulse_encoder.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pulse_encoder.c index 59363178a3..15fc535da4 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pulse_encoder.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pulse_encoder.c @@ -88,10 +88,10 @@ enum struct n32_pulse_encoder_device { struct rt_pulse_encoder_device pulse_encoder; - TIM_Module *timer; - IRQn_Type tim_irqn; - rt_int32_t over_under_flowcount; - char *name; + TIM_Module *timer; + IRQn_Type tim_irqn; + rt_int32_t over_under_flowcount; + char *name; }; static struct n32_pulse_encoder_device n32_pulse_encoder_obj[] = { @@ -145,7 +145,7 @@ static struct n32_pulse_encoder_device n32_pulse_encoder_obj[] = { static rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder) { struct n32_pulse_encoder_device *n32_device; - TIM_TimeBaseInitType TIM_TimeBaseStructure; + TIM_TimeBaseInitType TIM_TimeBaseStructure; n32_device = (struct n32_pulse_encoder_device *)pulse_encoder; @@ -154,10 +154,10 @@ static rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder /* Configure time base for encoder mode */ TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.Prescaler = 0; + TIM_TimeBaseStructure.Prescaler = 0; TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP; - TIM_TimeBaseStructure.Period = AUTO_RELOAD_VALUE; - TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.Period = AUTO_RELOAD_VALUE; + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; TIM_InitTimeBase(n32_device->timer, &TIM_TimeBaseStructure); /* Limit update interrupt source to counter overflow/underflow only (URS equivalent) */ @@ -219,11 +219,11 @@ static rt_err_t pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_ */ static rt_err_t pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) { - rt_err_t result; + rt_err_t result; struct n32_pulse_encoder_device *n32_device; n32_device = (struct n32_pulse_encoder_device *)pulse_encoder; - result = RT_EOK; + result = RT_EOK; switch (cmd) { @@ -437,10 +437,10 @@ void GTIMB3_IRQHandler(void) /* ---- Device Registration ---- */ static const struct rt_pulse_encoder_ops _ops = { - .init = pulse_encoder_init, - .get_count = pulse_encoder_get_count, + .init = pulse_encoder_init, + .get_count = pulse_encoder_get_count, .clear_count = pulse_encoder_clear_count, - .control = pulse_encoder_control, + .control = pulse_encoder_control, }; static int n32_pulse_encoder_init(void) @@ -452,7 +452,7 @@ static int n32_pulse_encoder_init(void) for (i = 0; i < sizeof(n32_pulse_encoder_obj) / sizeof(n32_pulse_encoder_obj[0]); i++) { n32_pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER; - n32_pulse_encoder_obj[i].pulse_encoder.ops = &_ops; + n32_pulse_encoder_obj[i].pulse_encoder.ops = &_ops; if (rt_device_pulse_encoder_register(&n32_pulse_encoder_obj[i].pulse_encoder, n32_pulse_encoder_obj[i].name, RT_NULL) != RT_EOK) diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pwm.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pwm.c index 0a3b31ee1d..7f6db24ebd 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pwm.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pwm.c @@ -82,9 +82,9 @@ enum struct n32_pwm { struct rt_device_pwm pwm_device; - TIM_Module *timer; - rt_uint8_t channel; /* bitmask: bit0=CH1, bit1=CH2, bit2=CH3, bit3=CH4 */ - char *name; + TIM_Module *timer; + rt_uint8_t channel; /* bitmask: bit0=CH1, bit1=CH2, bit2=CH3, bit3=CH4 */ + char *name; }; static struct n32_pwm n32_pwm_obj[] = { @@ -147,7 +147,7 @@ static struct n32_pwm n32_pwm_obj[] = { static rt_uint64_t tim_clock_get(TIM_Module *timer) { - rt_uint32_t tim_div; + rt_uint32_t tim_div; RCC_ClocksTypeDef RCC_Clocks; n32_tim_ahbx_div_get(timer, &tim_div); @@ -202,7 +202,7 @@ static rt_err_t drv_pwm_get(struct n32_pwm *pwm, struct rt_pwm_configuration *co tim_clock /= 1000000UL; period = TIM_GetAutoReload(pwm->timer) + 1; - psc = TIM_GetPrescaler(pwm->timer) + 1; + psc = TIM_GetPrescaler(pwm->timer) + 1; /* period (ns) = (ARR+1) * (PSC+1) * 1000 / tim_clock_MHz */ configuration->period = period * psc * 1000UL / tim_clock; @@ -238,13 +238,13 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm, struct rt_pwm_configuration *co rt_uint32_t tim_ch = 0x04 * (configuration->channel - 1); tim_clock = tim_clock_get(pwm->timer); - temp = tim_clock; + temp = tim_clock; /* Convert to MHz */ tim_clock /= 1000000UL; /* Calculate period and prescaler from requested period (ns) */ period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL; - psc = period / MAX_PERIOD + 1; + psc = period / MAX_PERIOD + 1; period = period / psc; /* Set prescaler */ @@ -297,11 +297,11 @@ static rt_err_t drv_pwm_set_period(struct n32_pwm *pwm, struct rt_pwm_configurat rt_uint32_t period; rt_uint64_t tim_clock, psc; - tim_clock = tim_clock_get(pwm->timer); + tim_clock = tim_clock_get(pwm->timer); tim_clock /= 1000000UL; period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL; - psc = period / MAX_PERIOD + 1; + psc = period / MAX_PERIOD + 1; period = period / psc; TIM_ConfigPrescaler(pwm->timer, (uint32_t)(psc - 1), TIM_PSC_RELOAD_MODE_UPDATE); @@ -320,11 +320,11 @@ static rt_err_t drv_pwm_set_pulse(struct n32_pwm *pwm, struct rt_pwm_configurati rt_uint32_t period, pulse; rt_uint64_t tim_clock; - tim_clock = tim_clock_get(pwm->timer); + tim_clock = tim_clock_get(pwm->timer); tim_clock /= 1000000UL; period = (TIM_GetAutoReload(pwm->timer) + 1) * (TIM_GetPrescaler(pwm->timer) + 1) * 1000UL / tim_clock; - pulse = (rt_uint64_t)configuration->pulse * (TIM_GetAutoReload(pwm->timer) + 1) / period; + pulse = (rt_uint64_t)configuration->pulse * (TIM_GetAutoReload(pwm->timer) + 1) / period; if (pulse < MIN_PULSE) { @@ -359,7 +359,7 @@ static rt_err_t drv_pwm_set_pulse(struct n32_pwm *pwm, struct rt_pwm_configurati static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - struct n32_pwm *pwm = (struct n32_pwm *)device->parent.user_data; + struct n32_pwm *pwm = (struct n32_pwm *)device->parent.user_data; switch (cmd) { @@ -388,13 +388,13 @@ static void drv_pwm_channel_init(TIM_Module *timer, rt_uint32_t channel_idx, rt_ OCInitType TIM_OCInitStructure; TIM_InitOcStruct(&TIM_OCInitStructure); - TIM_OCInitStructure.OCMode = oc_mode; - TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE; + TIM_OCInitStructure.OCMode = oc_mode; + TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE; TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_DISABLE; - TIM_OCInitStructure.Pulse = 0; - TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH; - TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_HIGH; - TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStructure.Pulse = 0; + TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_HIGH; + TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_RESET; TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET; switch (channel_idx) @@ -425,9 +425,9 @@ static void drv_pwm_channel_init(TIM_Module *timer, rt_uint32_t channel_idx, rt_ */ static rt_err_t n32_hw_pwm_init(struct n32_pwm *device) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_EOK; TIM_TimeBaseInitType TIM_TimeBaseStructure; - rt_uint32_t i; + rt_uint32_t i; RT_ASSERT(device != RT_NULL); @@ -436,11 +436,11 @@ static rt_err_t n32_hw_pwm_init(struct n32_pwm *device) /* Configure time base: default 1kHz, PWM mode */ TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.Period = 1000 - 1; - TIM_TimeBaseStructure.Prescaler = 0; - TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.Period = 1000 - 1; + TIM_TimeBaseStructure.Prescaler = 0; + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP; - TIM_TimeBaseStructure.RepetCnt = 0; + TIM_TimeBaseStructure.RepetCnt = 0; TIM_InitTimeBase(device->timer, &TIM_TimeBaseStructure); /* Configure PWM output channels */ @@ -646,7 +646,7 @@ static void n32_pwm_get_channel(void) static int n32_pwm_init(void) { - int i = 0; + int i = 0; int result = RT_EOK; n32_pwm_get_channel(); diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.c new file mode 100644 index 0000000000..84d17a85b1 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.c @@ -0,0 +1,887 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include "board.h" + + +#if defined(BSP_USING_QSPI2) + +#include "drv_qspi.h" +#include "n32h7xx_xspi_v2.h" +#include "drv_config.h" +#include <string.h> + +#define LOG_TAG "drv.qspi" +#include <drv_log.h> + +#define XSPI_TIMEOUT_TICKS (1000U) +#define DMA_TRANS_MIN_LEN (10U) + +#define XSPI_XIP_BASE_ADDR 0x90000000 + +static struct rt_spi_bus _xspi_bus; +static struct n32_xspi _n32_xspi; + + +static rt_err_t xspi_wait_flag(XSPI_Module *xspi, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = rt_tick_get(); + + while (XSPI_GetFlagStatus(xspi, flag) == RESET) + { + if (((rt_tick_get() - tickstart) >= timeout) && (timeout != 0xFFFFFFFFU)) + { + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static void XSPI_Wait_Tx_Compelete(void) +{ + while (XSPI_GetFlagStatus(xSPI2, XSPI_TXFE_FLAG) != SET) + { + } + + while (XSPI_GetFlagStatus(xSPI2, XSPI_BUSY_FLAG) != RESET) + { + } +} + + +static rt_err_t xspi_wait_flag_clear(XSPI_Module *xspi, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = rt_tick_get(); + + while (XSPI_GetFlagStatus(xspi, flag) != RESET) + { + if (((rt_tick_get() - tickstart) >= timeout) && (timeout != 0xFFFFFFFFU)) + { + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static rt_err_t xspi_wait_busy(XSPI_Module *xspi, uint32_t timeout) +{ + return xspi_wait_flag_clear(xspi, XSPI_BUSY_FLAG, timeout); +} + +/* ---- multi-line helpers ---- */ + +static uint32_t xspi_get_transfer_type(uint8_t instr_lines, uint8_t addr_lines) +{ + if (instr_lines == 1 && addr_lines == 1) + { + return XSPI_INST_ADDR_SINGLE_LINE; + } + + if (addr_lines > 1 && instr_lines == 1) + { + return XSPI_INST_SINGLE_LINE_ADDR_MULTI_LINE; + } + + if (instr_lines > 1 && addr_lines > 1) + { + return XSPI_INST_ADDR_MULTI_LINE; + } + + return XSPI_INST_ADDR_SINGLE_LINE; +} + +static uint32_t xspi_get_frame_format(uint8_t lines) +{ + switch (lines) + { + case 2: + return XSPI_DUAL_LINE_MODE; + + case 4: + return XSPI_QUAD_LINE_MODE; + + case 8: + return XSPI_OCTAL_LINE_MODE; + + default: + + return XSPI_STANDARD_MODE; + } +} +static void xspi_config_enhanced_for_msg(struct n32_xspi *xspi_config, + struct rt_qspi_message *qspi_msg, + uint32_t transfer_mode, rt_uint8_t ddr_enabled) +{ + xspi_config->EnhInitStructure.SCPH = xspi_config->InitStructure.SCPH; + xspi_config->EnhInitStructure.SCPOL = xspi_config->InitStructure.SCPOL; + + xspi_config->EnhInitStructure.DataFrameSize = xspi_config->InitStructure.DataFrameSize; + xspi_config->EnhInitStructure.Baudr = xspi_config->InitStructure.Baudr; + + xspi_config->EnhInitStructure.RxdSamplingEdge = xspi_config->InitStructure.RxdSamplingEdge; + xspi_config->EnhInitStructure.RxdSampleDelay = xspi_config->InitStructure.RxdSampleDelay; + + + if (qspi_msg->instruction.qspi_lines == 1) + { + xspi_config->EnhInitStructure.InstructLen = XSPI_INST_LEN_8BIT; + } + else if (qspi_msg->instruction.qspi_lines == 2) + { + xspi_config->EnhInitStructure.InstructLen = XSPI_INST_LEN_16BIT; + } + else + { + xspi_config->EnhInitStructure.InstructLen = XSPI_NO_INST_PHASE; + } + + if (qspi_msg->address.size == 8) + { + xspi_config->EnhInitStructure.AddrLen = XSPI_ADDR_LEN_8BIT; + } + else if (qspi_msg->address.size == 16) + { + xspi_config->EnhInitStructure.AddrLen = XSPI_ADDR_LEN_16BIT; + } + else if (qspi_msg->address.size == 24) + { + xspi_config->EnhInitStructure.AddrLen = XSPI_ADDR_LEN_24BIT; + } + else if (qspi_msg->address.size == 32) + { + xspi_config->EnhInitStructure.AddrLen = XSPI_ADDR_LEN_32BIT; + } + else + { + xspi_config->EnhInitStructure.AddrLen = XSPI_NO_ADDR_PHASE; + } + + xspi_config->EnhInitStructure.TransferMode = transfer_mode; + + xspi_config->EnhInitStructure.WaitCycles = qspi_msg->dummy_cycles; + + xspi_config->EnhInitStructure.FrameFormat = xspi_get_frame_format(qspi_msg->qspi_data_lines); + + xspi_config->EnhInitStructure.TransferType = xspi_get_transfer_type(qspi_msg->instruction.qspi_lines, qspi_msg->address.qspi_lines); + + xspi_config->EnhInitStructure.ClockStrech = xspi_config->InitStructure.EnhSlave_ClockStrech; + + xspi_config->EnhInitStructure.DDREable = ddr_enabled; + + XSPI_Slave_Select(_n32_xspi.xSPIx, xspi_config->slave_sel); +} + + +static rt_err_t xspi_qspi_transmit(struct n32_xspi *xspi_drv, struct rt_qspi_message *qspi_msg, + uint32_t timeout) +{ + XSPI_Module *xspi = xspi_drv->xSPIx; + + uint8_t *buf = (uint8_t *)qspi_msg->parent.send_buf; + uint32_t len = qspi_msg->parent.length, i = 0; + rt_uint8_t ddr = xspi_drv->qspi_cfg ? xspi_drv->qspi_cfg->ddr_mode : 0; + rt_err_t ret = RT_EOK; + XSPI_Enable(xspi, DISABLE); + + xspi_config_enhanced_for_msg(xspi_drv, qspi_msg, XSPI_TX_ONLY_MODE, ddr); + + xspi_drv->EnhInitStructure.ClockStrech = XSPI_CLOCK_STRETCH_ENABLE; + + XSPI_InitEnhanced(xspi, &xspi_drv->EnhInitStructure); + + XSPI_SetNumberOfDataFrame(xspi, len); + + XSPI_Enable(xspi, ENABLE); + + if (len >= 16) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL15); + } + else if (len == 0) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL0); + } + else + { + XSPI_SetTXStartFIFOThreshold(xspi, (len - 1)); + } + + XSPI_SendData(xspi, qspi_msg->instruction.content); + XSPI_SendData(xspi, qspi_msg->address.content); + + while (i < len) + { + if (XSPI_GetFlagStatus(xspi, XSPI_TXFNF_FLAG) == SET) + { + XSPI_SendData(xspi, buf[i++]); + } + } + + ret = xspi_wait_busy(xspi, timeout); + + XSPI_Enable(xspi, DISABLE); + + return ret; +} + +static rt_err_t xspi_qspi_receive(struct n32_xspi *xspi_drv, struct rt_qspi_message *qspi_msg, + uint32_t timeout) +{ + XSPI_Module *xspi = xspi_drv->xSPIx; + uint8_t *buf = (uint8_t *)qspi_msg->parent.recv_buf; + uint32_t len = qspi_msg->parent.length; + + rt_uint8_t ddr = xspi_drv->qspi_cfg ? xspi_drv->qspi_cfg->ddr_mode : 0; + rt_err_t ret = RT_EOK; + + xspi_config_enhanced_for_msg(xspi_drv, qspi_msg, XSPI_RX_ONLY_MODE, ddr); + + xspi_drv->EnhInitStructure.ClockStrech = XSPI_CLOCK_STRETCH_ENABLE; + + XSPI_Enable(xspi, DISABLE); + + XSPI_InitEnhanced(xspi, &xspi_drv->EnhInitStructure); + XSPI_SetNumberOfDataFrame(xspi, len); + XSPI_ClearRxFIFO(xspi); + XSPI_Enable(xspi, ENABLE); + + XSPI_SetRXFIFOFullThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL1); + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL1); + + XSPI_SendData(xspi, qspi_msg->instruction.content); + + XSPI_SendData(xspi, qspi_msg->address.content); + + for (uint32_t i = 0; i < len; i++) + { + if (xspi_wait_flag(xspi, XSPI_RXFNE_FLAG, timeout) != RT_EOK) + { + ret = -RT_ETIMEOUT; + goto exit; + } + + buf[i] = XSPI_ReceiveData(xspi); + } + + + while (XSPI_GetFlagStatus(xspi, XSPI_BUSY_FLAG) != RESET) + { + } + + XSPI_ClearRxFIFO(xspi); + +exit: + + XSPI_Enable(xspi, DISABLE); + + return ret; +} + + +/* ---- standard SPI (base mode) ---- */ + +static rt_err_t xspi_spi_transmit(struct n32_xspi *xspi_drv, struct rt_qspi_message *qspi_msg, uint32_t timeout) +{ + uint16_t i = 0, rindex = 0; + + uint8_t *send_buf = (uint8_t *)qspi_msg->parent.send_buf; + uint8_t *recv_buf = (uint8_t *)qspi_msg->parent.recv_buf; + + XSPI_Module *xspi = xspi_drv->xSPIx; + + xspi_drv->InitStructure.FrameFormat = XSPI_STANDARD_MODE; + + XSPI_Slave_Select(_n32_xspi.xSPIx, xspi_drv->slave_sel); + + XSPI_Enable(xspi, DISABLE); + + XSPI_InitBase(xspi, &xspi_drv->InitStructure); + + XSPI_SetNumberOfDataFrame(xspi, qspi_msg->parent.length); + + XSPI_Wait_Tx_Compelete(); + + XSPI_Enable(xspi, ENABLE); + + if (qspi_msg->parent.length > 16) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL15); + } + else if (qspi_msg->parent.length == 0) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL0); + } + else + { + XSPI_SetTXStartFIFOThreshold(xspi, (qspi_msg->parent.length - 1)); + } + + if (qspi_msg->parent.length <= 16) + { + while (i < qspi_msg->parent.length) + { + if (XSPI_GetFlagStatus(xspi, XSPI_TXFNF_FLAG) != RESET) + { + uint8_t tx = send_buf ? send_buf[i++] : 0xFF; + + XSPI_SendData(xspi, tx); + } + } + + XSPI_Wait_Tx_Compelete(); + + if (recv_buf) + { + while (XSPI_GetFlagStatus(xspi, XSPI_RXFNE_FLAG) == SET) + { + if (rindex < qspi_msg->parent.length) + { + recv_buf[rindex++] = XSPI_ReceiveData(xspi); + } + else + { + XSPI_ReceiveData(xspi); + } + } + } + } + else if (qspi_msg->parent.length > 16) + { + for (i = 0; i < qspi_msg->parent.length; i++) + { + uint8_t tx = send_buf ? send_buf[i] : 0xFF; + + if (xspi_wait_flag(xspi, XSPI_TXFNF_FLAG, timeout) != RT_EOK) + { + return -RT_ETIMEOUT; + } + + XSPI_SendData(xspi, tx); + + if (recv_buf) + { + if (xspi_wait_flag(xspi, XSPI_RXFNE_FLAG, timeout) != RT_EOK) + { + return -RT_ETIMEOUT; + } + + recv_buf[i] = (uint8_t)XSPI_ReceiveData(xspi); + } + } + } + + XSPI_Enable(xspi, DISABLE); + + return RT_EOK; +} + + +static rt_err_t xspi_spi_send(struct n32_xspi *xspi_drv, struct rt_qspi_message *qspi_msg, uint32_t timeout) +{ + uint16_t number = 0; + + uint8_t *buf = (uint8_t *)qspi_msg->parent.send_buf; + + XSPI_Module *xspi = xspi_drv->xSPIx; + + if (qspi_msg->instruction.content == 0) + { + return RT_ERROR; + } + + XSPI_Enable(xspi, DISABLE); + + xspi_drv->InitStructure.FrameFormat = XSPI_STANDARD_MODE; + + XSPI_Slave_Select(_n32_xspi.xSPIx, xspi_drv->slave_sel); + + + XSPI_InitBase(xspi, &xspi_drv->InitStructure); + + XSPI_SetNumberOfDataFrame(xspi, qspi_msg->parent.length); + + XSPI_Enable(xspi, ENABLE); + + XSPI_Wait_Tx_Compelete(); + + XSPI_ClearRxFIFO(xspi); + + if (qspi_msg->parent.length > 16) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL15); + } + else if (qspi_msg->parent.length == 0) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL0); + } + else + { + XSPI_SetTXStartFIFOThreshold(xspi, (qspi_msg->parent.length)); + } + + XSPI_SendData(xspi, qspi_msg->instruction.content); + + XSPI_SendData(xspi, (qspi_msg->address.content & 0xff0000) >> 16); + XSPI_SendData(xspi, (qspi_msg->address.content & 0xff00) >> 8); + XSPI_SendData(xspi, qspi_msg->address.content & 0xff); + + + while (number < qspi_msg->parent.length) + { + if (XSPI_GetFlagStatus(xspi, XSPI_TXFNF_FLAG) != RESET) + { + XSPI_SendData(xspi, buf[number++]); + } + } + + XSPI_Wait_Tx_Compelete(); + + XSPI_Enable(xspi, DISABLE); + + return RT_EOK; +} + + +static rt_err_t xspi_spi_receive(struct n32_xspi *xspi_drv, struct rt_qspi_message *qspi_msg, uint32_t timeout) +{ + uint16_t i = 0, j = 0; + uint8_t *buf = (uint8_t *)qspi_msg->parent.recv_buf; + + uint8_t s_data[5] = { 0 }; + + if (qspi_msg->instruction.content == 0) + { + return RT_ERROR; + } + + XSPI_Module *xspi = xspi_drv->xSPIx; + + xspi_drv->InitStructure.FrameFormat = XSPI_STANDARD_MODE; + + XSPI_Enable(xspi, DISABLE); + + XSPI_InitBase(xspi, &xspi_drv->InitStructure); + + XSPI_Slave_Select(_n32_xspi.xSPIx, xspi_drv->slave_sel); + + XSPI_SetNumberOfDataFrame(xspi, qspi_msg->parent.length); + + s_data[0] = qspi_msg->instruction.content; + s_data[1] = (qspi_msg->address.content & 0xff0000) >> 16; + s_data[2] = (qspi_msg->address.content & 0xff00) >> 8; + s_data[3] = (qspi_msg->address.content & 0xff); + + XSPI_Enable(xspi, ENABLE); + + if (qspi_msg->parent.length > 16) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL15); + } + else if (qspi_msg->parent.length == 0) + { + XSPI_SetTXStartFIFOThreshold(xspi, XSPI_FIFO_THRESHOLD_LEVEL0); + } + else + { + XSPI_SetTXStartFIFOThreshold(xspi, (qspi_msg->parent.length - 1)); + } + + while (i < qspi_msg->parent.length + 4) /*Tx Fifo not full*/ + { + while ((xspi->STS & XSPI_TXFNF_FLAG) != XSPI_TXFNF_FLAG); /*wait tx FIFO not full flag set*/ + + if (i < 4) + { + xspi->DAT0 = s_data[i]; /*write data register*/ + } + else + { + xspi->DAT0 = 0xFF; + } + + if ((xspi->STS & XSPI_RXFNE_FLAG)) /*Rx Fifo not empty set*/ + { + if (j < 4) + { + buf[0] = xspi->DAT0; + } + else if (j >= 4) + { + *(buf++) = xspi->DAT0; /*read data register*/ + } + + j++; + } + + i++; + } + + do + { + if ((xspi->STS & XSPI_RXFNE_FLAG)) /*Rx Fifo not empty set*/ + { + *(buf++) = xspi->DAT0; /*read data register*/ + } + + } while ((xspi->STS & XSPI_BUSY_FLAG) == SET); + + XSPI_Enable(xspi, DISABLE); + + return RT_EOK; +} + +/* ---- rt_spi_ops ---- */ + +static rt_err_t xspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + struct n32_xspi *xspi_drv = device->bus->parent.user_data; + struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *)device; + + xspi_drv->qspi_cfg = &qspi_dev->config; + xspi_drv->cfg = configuration; + +#if defined(SOC_SERIES_N32H7xx) + /* set scpol/scph value */ + switch (xspi_drv->qspi_cfg->parent.mode & 0x03) + { + case RT_SPI_MODE_0: + { + xspi_drv->InitStructure.SCPH = XSPI_SCPH_FIRST_EDGE; + xspi_drv->InitStructure.SCPOL = XSPI_SCPOL_LOW_LEVEL; + break; + } + + case RT_SPI_MODE_1: + { + xspi_drv->InitStructure.SCPH = XSPI_SCPH_SECOND_EDGE; + xspi_drv->InitStructure.SCPOL = XSPI_SCPOL_LOW_LEVEL; + break; + } + + case RT_SPI_MODE_2: + { + xspi_drv->InitStructure.SCPH = XSPI_SCPH_FIRST_EDGE; + xspi_drv->InitStructure.SCPOL = XSPI_SCPOL_HIGH_LEVEL; + break; + } + + case RT_SPI_MODE_3: + { + xspi_drv->InitStructure.SCPH = XSPI_SCPH_SECOND_EDGE; + xspi_drv->InitStructure.SCPOL = XSPI_SCPOL_HIGH_LEVEL; + break; + } + + default: + { + xspi_drv->InitStructure.SCPH = XSPI_SCPH_FIRST_EDGE; + xspi_drv->InitStructure.SCPOL = XSPI_SCPOL_LOW_LEVEL; + break; + } + } + + /* dl_width = 1/2/4 */ + if (xspi_drv->qspi_cfg->qspi_dl_width == 1) + { + xspi_drv->InitStructure.FrameFormat = XSPI_STANDARD_MODE; + } + else if (xspi_drv->qspi_cfg->qspi_dl_width == 2) + { + xspi_drv->InitStructure.FrameFormat = XSPI_DUAL_LINE_MODE; + } + else if (xspi_drv->qspi_cfg->qspi_dl_width == 4) + { + xspi_drv->InitStructure.FrameFormat = XSPI_QUAD_LINE_MODE; + } + + if (xspi_drv->qspi_cfg->parent.data_width == 8) + { + xspi_drv->InitStructure.DataFrameSize = XSPI_FRAME_SIZE_8_BIT; + } + else if (xspi_drv->qspi_cfg->parent.data_width == 16) + { + xspi_drv->InitStructure.DataFrameSize = XSPI_FRAME_SIZE_16_BIT; + } + else if (xspi_drv->qspi_cfg->parent.data_width == 24) + { + xspi_drv->InitStructure.DataFrameSize = XSPI_FRAME_SIZE_24_BIT; + } + else if (xspi_drv->qspi_cfg->parent.data_width == 32) + { + xspi_drv->InitStructure.DataFrameSize = XSPI_FRAME_SIZE_32_BIT; + } + + +#endif + + return RT_EOK; +} + +static rt_ssize_t xspixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + RT_ASSERT(device != RT_NULL && device->bus != RT_NULL && message != RT_NULL); + rt_err_t state = RT_EOK; + struct n32_xspi *xspi_drv = device->bus->parent.user_data; + struct rt_qspi_message *qmsg = (struct rt_qspi_message *)message; + + if (device->bus->mode & RT_SPI_BUS_MODE_QSPI) + { + if (qmsg->qspi_data_lines == 1) + { + if (message->send_buf && (qmsg->address.qspi_lines == 1)) + { + state = xspi_spi_send(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + else if (message->recv_buf && (qmsg->address.qspi_lines == 1)) + { + state = xspi_spi_receive(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + else if ((message->send_buf != NULL) || (message->recv_buf != NULL)) + { + state = xspi_spi_transmit(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + } + else if (qmsg->qspi_data_lines == 4) + { + if (message->send_buf) + { + state = xspi_qspi_transmit(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + else if (message->recv_buf) + { + state = xspi_qspi_receive(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + } + } + else + { + state = xspi_spi_transmit(xspi_drv, qmsg, XSPI_TIMEOUT_TICKS); + } + + if (state != RT_EOK) + { + LOG_E("xspi transfer error: %d", state); + return -RT_ERROR; + } + + return message->length; +} + +static const struct rt_spi_ops n32_xspi_ops = { + .configure = xspi_configure, + .xfer = xspixfer, +}; + + +/* XSPI XIP */ +static rt_err_t xspi_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_spi_device *spi_dev = (struct rt_spi_device *)dev; + struct n32_xspi *xspi_drv = spi_dev->bus->parent.user_data; + + + switch (cmd) + { + case XSPI_CTRL_ENTER_XIP: + { + static const struct xspi_xip_config _xip_default = { + .XipInstructLen = XSPI_INST_LEN_8BIT, + .XipInstrctEnable = XSPI_XIP_INSTRUCT_ENABLE, + .XipDFSHC = XSPI_XIP_DFSHC_ENABLE, + .XipPrefetch = XSPI_XIP_PREFETCH_DISABLE, + .XipModeBit = XSPI_XIP_MODE_BIT_ENABLE, + .XipModeBitLen = XSPI_XIP_MODE_BIT_LEN_8_BIT, + .XipModeBit_Data = 0x00, + .XipContinousTransfer = XSPI_XIP_INSTRUCT_DISABLE, + .XipWatchDogTimeout = 100U, + .XipIncrOpcode = 0x00, + .XipWrapOpcode = 0x00, + }; + + const struct xspi_xip_config *cfg = args ? args : &_xip_default; + + XSPI_Module *xspi = xspi_drv->xSPIx; + + XSPI_Enable(xspi, DISABLE); + XSPI_XIPInitType XSPI_XIPInit; + + XSPI_InitXIPStruct(&XSPI_XIPInit); + + XSPI_XIPInit.SCPH = xspi_drv->InitStructure.SCPH; + XSPI_XIPInit.SCPOL = xspi_drv->InitStructure.SCPOL; + XSPI_XIPInit.DataFrameSize = xspi_drv->InitStructure.DataFrameSize; + XSPI_XIPInit.Baudr = xspi_drv->InitStructure.Baudr; + XSPI_XIPInit.XipFrameFormat = xspi_drv->InitStructure.FrameFormat; + + XSPI_XIPInit.XipTransferType = xspi_drv->EnhInitStructure.TransferType; + XSPI_XIPInit.XipAddrLen = xspi_drv->EnhInitStructure.AddrLen; + XSPI_XIPInit.XipWaitCycles = xspi_drv->EnhInitStructure.WaitCycles; + XSPI_XIPInit.XipDDREable = xspi_drv->EnhInitStructure.DDREable; + + XSPI_XIPInit.TransferMode = XSPI_RX_ONLY_MODE; + + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipInstructLen = cfg->XipInstructLen; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipInstrctEnable = cfg->XipInstrctEnable; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipDFSHC = cfg->XipDFSHC; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipPrefetch = cfg->XipPrefetch; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipModeBit = cfg->XipModeBit; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.XipModeBitLen = cfg->XipModeBitLen; + + XSPI_XIPInit.XIP_Info.Read_XIPInitType.ContinueTransfer.XipContinueTransfer = cfg->XipContinousTransfer; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.ContinueTransfer.XipWatchDogTimeout = cfg->XipWatchDogTimeout; + + XSPI_XIPInit.XIP_Info.Read_XIPInitType.Info.Rxds_InitType.RxdSamplingEdge = xspi_drv->InitStructure.RxdSamplingEdge; + XSPI_XIPInit.XIP_Info.Read_XIPInitType.Info.Rxds_InitType.RxdSampleDelay = xspi_drv->InitStructure.RxdSampleDelay; + + xspi_drv->xip_enabled = 1; + + xspi_drv->Direct = XSPI_Idle; + + XSPI_InitXIP(xspi, &XSPI_XIPInit); + + XSPI_XIP_Slave_Select(xspi, xspi_drv->slave_sel); + + XSPI_SetXIPModeBit(xspi, cfg->XipModeBit_Data); + + XSPI_SetXIPReadIncrOpcode(xspi, cfg->XipIncrOpcode); + XSPI_SetXIPReadWrapOpcode(xspi, cfg->XipWrapOpcode); + + XSPI_Enable(xspi, ENABLE); + + + return RT_EOK; + } + + + case XSPI_CTRL_EXIT_XIP: + { + XSPI_Enable(xspi_drv->xSPIx, DISABLE); + + xspi_drv->xip_enabled = 0; + xspi_drv->Direct = XSPI_Idle; + LOG_D("%s XIP exit via ioctl", xspi_drv->bus_name); + return RT_EOK; + } + + case XSPI_CTRL_GET_XIP_ADDR: + { + if (args) + { + *(void **)args = (void *)XSPI_XIP_BASE_ADDR; + } + + return RT_EOK; + } + + + default: + + return -RT_EINVAL; + } +} + +/* ---- bus register + device attach ---- */ +static int n32_xspi_register_bus(struct n32_xspi *xspi_drv, const char *name) +{ + RT_ASSERT(xspi_drv != RT_NULL && name != RT_NULL); + _xspi_bus.parent.user_data = xspi_drv; + + int ret = rt_qspi_bus_register(&_xspi_bus, name, &n32_xspi_ops); + + return ret; +} + +rt_err_t rt_hw_xspi_device_attach(const char *bus_name, const char *device_name, + rt_uint8_t data_line_width, + void (*enter_qspi_mode)(struct rt_qspi_device *), + void (*exit_qspi_mode)(struct rt_qspi_device *), + struct n32_xspi_config *cfg) +{ + RT_ASSERT(bus_name != RT_NULL && device_name != RT_NULL); + + struct rt_qspi_device *qspi_device; + rt_err_t result; + + if (cfg != RT_NULL) + { + _n32_xspi.InitStructure.Role = cfg->role; + _n32_xspi.InitStructure.NssToggle = cfg->nss_toggle; + + _n32_xspi.InitStructure.DataFrameSize = cfg->data_frame_size; + _n32_xspi.InitStructure.SCPH = cfg->scph; + _n32_xspi.InitStructure.SCPOL = cfg->scpol; + _n32_xspi.InitStructure.TransferMode = cfg->transfer_mode; + _n32_xspi.InitStructure.Baudr = cfg->baudr; + _n32_xspi.InitStructure.FrameFormat = cfg->frame_format; + _n32_xspi.InitStructure.RxdSamplingEdge = cfg->rxd_sampling_edge; + _n32_xspi.InitStructure.RxdSampleDelay = cfg->rxd_sample_delay; + _n32_xspi.slave_sel = cfg->slave_sel; + + _n32_xspi.InitStructure.EnhSlave_ClockStrech = cfg->Enhance_clock_strech; + + if (data_line_width != 1) + { + _n32_xspi.EnhInitStructure.TransferType = cfg->Enhance_TransferType; + _n32_xspi.EnhInitStructure.AddrLen = cfg->Enhance_AddrLen; + _n32_xspi.EnhInitStructure.InstructLen = cfg->Enhance_InstructLen; + _n32_xspi.EnhInitStructure.WaitCycles = cfg->Enhance_WaitCycles; + _n32_xspi.EnhInitStructure.DDREable = cfg->Enhance_DDR; + } + } + + qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device)); + if (qspi_device == RT_NULL) + { + return -RT_ENOMEM; + } + + qspi_device->enter_qspi_mode = enter_qspi_mode; + qspi_device->exit_qspi_mode = exit_qspi_mode; + + qspi_device->config.qspi_dl_width = data_line_width; + + result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, + bus_name, RT_NULL); + + if (result != RT_EOK) + { + rt_free(qspi_device); + return result; + } + + qspi_device->parent.parent.control = xspi_control; + + return result; +} + + +/* ---- board-level init ---- */ + +static int rt_hw_xspi_bus_init(void) +{ +#if defined(SOC_SERIES_N32H7xx) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_PWR, ENABLE); + + RCC_EnableAXIPeriphReset4(RCC_AXI_PERIPHRST_XSPI2); + RCC_EnableAXIPeriphClk4(RCC_AXI_PERIPHEN_M7_XSPI2, ENABLE); + +#endif + + _n32_xspi.xSPIx = xSPI2; + _n32_xspi.bus_name = "qspi2"; + + + rt_completion_init(&_n32_xspi.cpt); + return n32_xspi_register_bus(&_n32_xspi, "qspi2"); +} + +INIT_BOARD_EXPORT(rt_hw_xspi_bus_init); + +#endif diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.h new file mode 100644 index 0000000000..113e614137 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_qspi.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_XSPI_H__ +#define __DRV_XSPI_H__ + +#include <rtthread.h> +#include <rtdevice.h> +#include <ipc/completion.h> +#include "drv_common.h" + +#include "n32h7xx_xspi_v2.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct mdma_config +{ + MDMA_ChNumType mdma_channel; + IRQn_Type dma_irq; + uint32_t dmamux_channel; + uint32_t dmamux_request; + uint32_t hs_interface; +}; + +#define XSPI_USING_RX_DMA_FLAG (1 << 0) +#define XSPI_USING_TX_DMA_FLAG (1 << 1) + +typedef enum +{ + XSPI_Tx_Rx = 0U, + XSPI_Tx, + XSPI_Rx, + XSPI_Idle, + +} XSPI_Work_Direct_t; + +struct n32_xspi +{ + XSPI_Module *xSPIx; + char *bus_name; + XSPI_InitType InitStructure; + XSPI_EnhancedInitType EnhInitStructure; + XSPI_XIPInitType XIPInitStructure; + + struct rt_qspi_configuration *qspi_cfg; + struct rt_spi_configuration *cfg; + XSPI_Work_Direct_t Direct; + rt_uint8_t xspi_dma_flag; + + struct + { + rt_bool_t DMA_Tx_Init; + MDMA_ChInitType TX_DMA_ChInitStr; + rt_bool_t DMA_Rx_Init; + MDMA_ChInitType RX_DMA_ChInitStr; + } dma; + + rt_uint8_t slave_sel; + rt_uint8_t xip_enabled; + + struct rt_completion cpt; +}; + +struct n32_xspi_config +{ + uint32_t scph; + uint32_t scpol; + uint32_t role; + uint32_t frame_format; + uint32_t data_frame_size; + uint32_t transfer_mode; + uint32_t baudr; + uint32_t rxd_sampling_edge; + uint32_t rxd_sample_delay; + uint32_t nss_toggle; + + uint8_t slave_sel; + + uint32_t Enhance_clock_strech; + uint32_t Enhance_TransferType; + uint32_t Enhance_AddrLen; + uint32_t Enhance_InstructLen; + uint32_t Enhance_WaitCycles; + uint32_t Enhance_DDR; +}; + +struct xspi_xip_config +{ + uint32_t XipInstructLen; + uint32_t XipInstrctEnable; + uint32_t XipDFSHC; + uint32_t XipPrefetch; + + uint32_t XipModeBit; + uint32_t XipModeBitLen; + uint16_t XipModeBit_Data; + + uint32_t XipContinousTransfer; + uint32_t XipWatchDogTimeout; + + uint16_t XipIncrOpcode; + uint16_t XipWrapOpcode; +}; + +/* XSPI control commands */ +#define XSPI_CTRL_ENTER_XIP 0x01 +#define XSPI_CTRL_EXIT_XIP 0x02 +#define XSPI_CTRL_GET_XIP_ADDR 0x03 + +rt_err_t rt_hw_xspi_device_attach(const char *bus_name, const char *device_name, + rt_uint8_t data_line_width, + void (*enter_qspi_mode)(struct rt_qspi_device *), + void (*exit_qspi_mode)(struct rt_qspi_device *), + struct n32_xspi_config *cfg); + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_XSPI_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c index ee1df1437c..1e6df69057 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c @@ -22,8 +22,8 @@ #include "drv_config.h" static struct n32_sdio_config sdio_config = SDIO_BUS_CONFIG; -static struct n32_sdio_class sdio_obj; -static struct rt_mmcsd_host *host; +static struct n32_sdio_class sdio_obj; +static struct rt_mmcsd_host *host; #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000) @@ -33,17 +33,17 @@ static struct rt_mmcsd_host *host; struct sdio_pkg { struct rt_mmcsd_cmd *cmd; - void *buff; - rt_uint32_t flag; + void *buff; + rt_uint32_t flag; }; struct rt_hw_sdio { struct rt_mmcsd_host *host; - struct n32_sdio_des sdio_des; - struct rt_event event; - struct rt_mutex mutex; - struct sdio_pkg *pkg; + struct n32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; }; ALIGN(SDIO_ALIGN_LEN) @@ -125,10 +125,10 @@ static int get_order(rt_uint32_t data) */ static void rt_hw_sdio_wait_completed(struct rt_hw_sdio *sdio) { - rt_uint32_t status; - struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; - struct rt_mmcsd_data *data = cmd->data; - struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, rt_tick_from_millisecond(5000), &status) != RT_EOK) @@ -215,9 +215,9 @@ static void rt_hw_sdio_wait_completed(struct rt_hw_sdio *sdio) static void rt_hw_sdio_transfer_by_dma(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg) { struct rt_mmcsd_data *data; - int size; - void *buff; - struct n32_sdio *hw_sdio; + int size; + void *buff; + struct n32_sdio *hw_sdio; if ((RT_NULL == pkg) || (RT_NULL == sdio)) { @@ -239,7 +239,7 @@ static void rt_hw_sdio_transfer_by_dma(struct rt_hw_sdio *sdio, struct sdio_pkg return; } hw_sdio = sdio->sdio_des.hw_sdio; - size = data->blks * data->blksize; + size = data->blks * data->blksize; if (data->flags & DATA_DIR_WRITE) { @@ -261,10 +261,10 @@ static void rt_hw_sdio_transfer_by_dma(struct rt_hw_sdio *sdio, struct sdio_pkg */ static void rt_hw_sdio_send_command(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg) { - struct rt_mmcsd_cmd *cmd = pkg->cmd; - struct rt_mmcsd_data *data = cmd->data; - struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; - rt_uint32_t reg_cmd; + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; /* save pkg */ sdio->pkg = pkg; @@ -288,24 +288,30 @@ static void rt_hw_sdio_send_command(struct rt_hw_sdio *sdio, struct sdio_pkg *pk /* config cmd reg */ reg_cmd = (cmd->cmd_code) << 8 | HW_SDIO_CPSM_ENABLE; if (resp_type(cmd) == RESP_NONE) + { reg_cmd |= HW_SDIO_RESPONSE_NO; + } else if (resp_type(cmd) == RESP_R2) + { reg_cmd |= HW_SDIO_RESPONSE_LONG; + } else + { reg_cmd |= HW_SDIO_RESPONSE_SHORT; + } /* config data reg */ if (data != RT_NULL) { - rt_uint32_t dir = 0; + rt_uint32_t dir = 0; rt_uint32_t size = data->blks * data->blksize; - int order; + int order; - hw_sdio->dctrl = 0; + hw_sdio->dctrl = 0; hw_sdio->dtimer = HW_SDIO_DATATIMEOUT; - hw_sdio->dlen = size; - order = get_order(data->blksize); - dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0; + hw_sdio->dlen = size; + order = get_order(data->blksize); + dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0; /* HW_SDIO_IO_ENABLE | */ hw_sdio->dctrl = (order << 8) | dir; } @@ -361,8 +367,8 @@ static void rt_hw_sdio_send_command(struct rt_hw_sdio *sdio, struct sdio_pkg *pk */ static void rt_hw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - struct sdio_pkg pkg; - struct rt_hw_sdio *sdio = host->private_data; + struct sdio_pkg pkg; + struct rt_hw_sdio *sdio = host->private_data; struct rt_mmcsd_data *data; RT_HW_SDIO_LOCK(sdio); @@ -370,7 +376,7 @@ static void rt_hw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req * if (req->cmd != RT_NULL) { memset(&pkg, 0, sizeof(pkg)); - data = req->cmd->data; + data = req->cmd->data; pkg.cmd = req->cmd; if (data != RT_NULL) @@ -418,10 +424,10 @@ static void rt_hw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req * */ static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkcr, div, clk_src; - rt_uint32_t clk = io_cfg->clock; - struct rt_hw_sdio *sdio = host->private_data; - struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rt_hw_sdio *sdio = host->private_data; + struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); if (clk_src < 400 * 1000) @@ -431,7 +437,9 @@ static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg } if (clk > host->freq_max) + { clk = host->freq_max; + } if (clk > clk_src) { @@ -465,8 +473,8 @@ static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg { div = 0x1FF; } - div -= 2; - clkcr = div | HW_SDIO_CLK_ENABLE; + div -= 2; + clkcr = div | HW_SDIO_CLK_ENABLE; } if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) @@ -511,8 +519,8 @@ static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg */ void rt_hw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) { - struct rt_hw_sdio *sdio = host->private_data; - struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + struct rt_hw_sdio *sdio = host->private_data; + struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; if (enable) { @@ -619,10 +627,10 @@ static void handle_sdioit(struct rt_mmcsd_host *host, struct n32_sdio *hw_sdio) */ void rt_hw_sdio_irq_process(struct rt_mmcsd_host *host) { - int complete = 0; - struct rt_hw_sdio *sdio = host->private_data; - struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; - rt_uint32_t intstatus = hw_sdio->sta; + int complete = 0; + struct rt_hw_sdio *sdio = host->private_data; + struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->sta; if (intstatus & HW_SDIO_ERRORS) { @@ -647,7 +655,7 @@ void rt_hw_sdio_irq_process(struct rt_mmcsd_host *host) if (intstatus & HW_SDIO_IT_DATAEND) { hw_sdio->icr = HW_SDIO_IT_DATAEND; - complete = handle_dataend(); + complete = handle_dataend(); } } @@ -678,7 +686,7 @@ static const struct rt_mmcsd_host_ops ops = { struct rt_mmcsd_host *sdio_host_create(struct n32_sdio_des *sdio_des) { struct rt_mmcsd_host *host; - struct rt_hw_sdio *sdio = RT_NULL; + struct rt_hw_sdio *sdio = RT_NULL; if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) { @@ -713,22 +721,22 @@ struct rt_mmcsd_host *sdio_host_create(struct n32_sdio_des *sdio_des) rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO); /* set host defautl attributes */ - host->ops = &ops; - host->freq_min = 400 * 1000; - host->freq_max = SDIO_MAX_FREQ; + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; host->valid_ocr = 0X00FFFF80;/* the voltage range supported is 1.65v-3.6v */ #ifndef SDIO_USING_1_BIT host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; #else host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; #endif - host->max_seg_size = SDIO_BUFF_SIZE; - host->max_dma_segs = 1; - host->max_blk_size = 512; + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; host->max_blk_count = 512; /* link up host and sdio */ - sdio->host = host; + sdio->host = host; host->private_data = sdio; rt_hw_sdio_irq_update(host, 1); @@ -757,17 +765,17 @@ void sd_lowlevel_dmatx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size DMA_DeInit(sdio_config.dma_tx.DMAChx); /*!< DMA2 Channel2 Config */ - sdio_obj.dma.handle_tx.PeriphAddr = (uint32_t)dst; - sdio_obj.dma.handle_tx.MemAddr = (uint32_t)src; - sdio_obj.dma.handle_tx.Direction = DMA_DIR_PERIPH_DST; - sdio_obj.dma.handle_tx.BufSize = buffer_size; - sdio_obj.dma.handle_tx.PeriphInc = DMA_PERIPH_INC_DISABLE; - sdio_obj.dma.handle_tx.MemoryInc = DMA_MEM_INC_ENABLE; + sdio_obj.dma.handle_tx.PeriphAddr = (uint32_t)dst; + sdio_obj.dma.handle_tx.MemAddr = (uint32_t)src; + sdio_obj.dma.handle_tx.Direction = DMA_DIR_PERIPH_DST; + sdio_obj.dma.handle_tx.BufSize = buffer_size; + sdio_obj.dma.handle_tx.PeriphInc = DMA_PERIPH_INC_DISABLE; + sdio_obj.dma.handle_tx.MemoryInc = DMA_MEM_INC_ENABLE; sdio_obj.dma.handle_tx.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD; - sdio_obj.dma.handle_tx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD; - sdio_obj.dma.handle_tx.CircularMode = DMA_MODE_NORMAL; - sdio_obj.dma.handle_tx.Priority = DMA_PRIORITY_HIGH; - sdio_obj.dma.handle_tx.Mem2Mem = DMA_M2M_DISABLE; + sdio_obj.dma.handle_tx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD; + sdio_obj.dma.handle_tx.CircularMode = DMA_MODE_NORMAL; + sdio_obj.dma.handle_tx.Priority = DMA_PRIORITY_HIGH; + sdio_obj.dma.handle_tx.Mem2Mem = DMA_M2M_DISABLE; DMA_Init(sdio_config.dma_tx.DMAChx, &sdio_obj.dma.handle_tx); @@ -796,17 +804,17 @@ void sd_lowlevel_dmarx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size DMA_DeInit(sdio_config.dma_rx.DMAChx); /*!< DMA2 Channel2 Config */ - sdio_obj.dma.handle_rx.PeriphAddr = (uint32_t)src; - sdio_obj.dma.handle_rx.MemAddr = (uint32_t)dst; - sdio_obj.dma.handle_rx.Direction = DMA_DIR_PERIPH_SRC; - sdio_obj.dma.handle_rx.BufSize = buffer_size; - sdio_obj.dma.handle_rx.PeriphInc = DMA_PERIPH_INC_DISABLE; - sdio_obj.dma.handle_rx.MemoryInc = DMA_MEM_INC_ENABLE; + sdio_obj.dma.handle_rx.PeriphAddr = (uint32_t)src; + sdio_obj.dma.handle_rx.MemAddr = (uint32_t)dst; + sdio_obj.dma.handle_rx.Direction = DMA_DIR_PERIPH_SRC; + sdio_obj.dma.handle_rx.BufSize = buffer_size; + sdio_obj.dma.handle_rx.PeriphInc = DMA_PERIPH_INC_DISABLE; + sdio_obj.dma.handle_rx.MemoryInc = DMA_MEM_INC_ENABLE; sdio_obj.dma.handle_rx.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD; - sdio_obj.dma.handle_rx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD; - sdio_obj.dma.handle_rx.CircularMode = DMA_MODE_NORMAL; - sdio_obj.dma.handle_rx.Priority = DMA_PRIORITY_HIGH; - sdio_obj.dma.handle_rx.Mem2Mem = DMA_M2M_DISABLE; + sdio_obj.dma.handle_rx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD; + sdio_obj.dma.handle_rx.CircularMode = DMA_MODE_NORMAL; + sdio_obj.dma.handle_rx.Priority = DMA_PRIORITY_HIGH; + sdio_obj.dma.handle_rx.Mem2Mem = DMA_M2M_DISABLE; DMA_Init(sdio_config.dma_rx.DMAChx, &sdio_obj.dma.handle_rx); @@ -867,8 +875,8 @@ int rt_hw_sdio_init(void) NVIC_SetPriority(SDIO_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0)); NVIC_EnableIRQ(SDIO_IRQn); - sdio_des.clk_get = n32_sdio_clock_get; - sdio_des.hw_sdio = (struct n32_sdio *)SDCARD_INSTANCE; + sdio_des.clk_get = n32_sdio_clock_get; + sdio_des.hw_sdio = (struct n32_sdio *)SDCARD_INSTANCE; sdio_des.rxconfig = dma_rx_config; sdio_des.txconfig = dma_tx_config; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h index d5739edd1f..c22cf1039f 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h @@ -149,30 +149,30 @@ struct n32_sdio volatile rt_uint32_t fifo; }; -typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); -typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); typedef rt_uint32_t (*sdio_clk_get)(struct n32_sdio *hw_sdio); struct n32_sdio_des { struct n32_sdio *hw_sdio; - dma_txconfig txconfig; - dma_rxconfig rxconfig; - sdio_clk_get clk_get; + dma_txconfig txconfig; + dma_rxconfig rxconfig; + sdio_clk_get clk_get; }; struct n32_sdio_config { SDCARD_INSTANCE_TYPE *sdio_x; - struct dma_config dma_rx, dma_tx; + struct dma_config dma_rx, dma_tx; }; /* n32 sdio dirver class */ struct n32_sdio_class { - struct n32_sdio_des *des; + struct n32_sdio_des *des; const struct n32_sdio_config *cfg; - struct rt_mmcsd_host host; + struct rt_mmcsd_host host; struct { DMA_InitType handle_rx; @@ -189,16 +189,16 @@ extern void n32_mmcsd_change(void); { \ .sdio_x = SDIO, \ .dma_rx = { \ - .DMAy = SDIO_RX_DMA, \ - .DMAChx = SDIO_TX_DMA_CHType, \ + .DMAy = SDIO_RX_DMA, \ + .DMAChx = SDIO_TX_DMA_CHType, \ .dma_irq = SDIO_TX_DMA_IRQ, \ .dma_rcc = SDIO_TX_DMA_RCC, \ .request = SDIO_TX_DMA_REQUEST, \ .channel = SDIO_TX_DMA_CHANNEL \ }, \ .dma_tx = { \ - .DMAy = SDIO_TX_DMA, \ - .DMAChx = SDIO_RX_DMA_CHType, \ + .DMAy = SDIO_TX_DMA, \ + .DMAChx = SDIO_RX_DMA_CHType, \ .dma_irq = SDIO_RX_DMA_IRQ, \ .dma_rcc = SDIO_RX_DMA_RCC, \ .request = SDIO_RX_DMA_REQUEST, \ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c new file mode 100644 index 0000000000..34e76c09bd --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-21 ox-horse first version for N32, based on N32 SDK bsp_sdram.c + */ + +#include <board.h> +#include <rtthread.h> + +#ifdef BSP_USING_SDRAM +#include <sdram_port.h> +#include <n32h7xx_rcc.h> +#include <n32h7xx_sdram.h> + +#define DRV_DEBUG +#define LOG_TAG "drv.sdram" +#include <drv_log.h> + +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif + +static SDRAM_DeviceType sdram_device; + +/*---------------------------------------------------------------------------- + * Macro translation: standard sdram_port.h -> N32 HAL + *---------------------------------------------------------------------------*/ + +/* Row bits + Column bits -> N32 address configuration */ +#if SDRAM_ROW_BITS == 11 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL2048 +#endif +#elif SDRAM_ROW_BITS == 12 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL2048 +#endif +#elif SDRAM_ROW_BITS == 13 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL2048 +#endif +#endif + +/* Data width -> N32 bus width */ +#if SDRAM_DATA_WIDTH == 8 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_8BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_8 +#define SDRAM_LOADMODE_BURSTLEN 3 +#elif SDRAM_DATA_WIDTH == 16 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_16BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_4 +#define SDRAM_LOADMODE_BURSTLEN 2 +#elif SDRAM_DATA_WIDTH == 32 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_32BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_2 +#define SDRAM_LOADMODE_BURSTLEN 1 +#endif + +/* CAS latency -> N32 CAS */ +#ifdef BSP_SDRAM_CAS_LATENCY_1 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_1 +#define SDRAM_LOADMODE_CASLATENCY 1 +#endif /* BSP_SDRAM_CAS_LATENCY_1 */ +#ifdef BSP_SDRAM_CAS_LATENCY_2 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_2 +#define SDRAM_LOADMODE_CASLATENCY 2 +#endif /* BSP_SDRAM_CAS_LATENCY_2 */ +#ifdef BSP_SDRAM_CAS_LATENCY_3 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_3 +#define SDRAM_LOADMODE_CASLATENCY 3 +#endif /* BSP_SDRAM_CAS_LATENCY_3 */ + +/* Target bank -> device select */ +#ifdef BSP_SDRAM_BANK1 +#define SDRAM_CS_SELECT SDRAM_CS_SDRAM1_ONLY +#endif +#ifdef BSP_SDRAM_BANK2 +#define SDRAM_CS_SELECT SDRAM_CS_SDRAM2_ONLY +#endif + + +#ifndef SDRAM_RP_DELAY +#define SDRAM_RP_DELAY (RPDELAY) +#endif +#ifndef SDRAM_REFRESH_CYCLE +#define SDRAM_REFRESH_CYCLE (ROWCYCLEDELAY) +#endif +#ifndef SDRAM_ADDRESS_MASK +#define SDRAM_ADDRESS_MASK ((uint32_t)(0xFFFFFFFF - ((BSP_SDRAM_SIZE * 1024U * 1024U) - 1))) +#endif + +/*---------------------------------------------------------------------------- + * SDRAM Load Mode Register type (from N32 SDK bsp_sdram.h) + * Represents the value sent to the SDRAM chip via LOADMODE command. + *---------------------------------------------------------------------------*/ +typedef union +{ + uint32_t cmd; + struct + { + uint32_t BurstLen : 3; /* M2:0 Burst Length */ + uint32_t BurstType : 1; /* M3 Burst Type */ + uint32_t CASLatency : 3; /* M6:4 CAS Latency */ + uint32_t OpMode : 2; /* M8:7 Operating Mode */ + uint32_t WBMode : 1; /* M9 Write Burst Mode */ + uint32_t Reserved : 22; + } Bits; +} SDRAM_LoadModeRegisterType; + +/* Mode register field values (from N32 SDK bsp_sdram.h) */ +#define LOADMODE_BURSTLEN_1 0 +#define LOADMODE_BURSTLEN_2 1 +#define LOADMODE_BURSTLEN_4 2 +#define LOADMODE_BURSTLEN_8 3 +#define LOADMODE_BURSTTYPE_SEQUENTIAL 0 +#define LOADMODE_BURSTTYPE_INTERLEAVED 1 +#define LOADMODE_CASLATENCY_2 2 +#define LOADMODE_CASLATENCY_3 3 +#define LOADMODE_OPMODE_STANDARD 0 +#define LOADMODE_WBMODE_BURST 0 +#define LOADMODE_WBMODE_SINGLE 1 + +/*---------------------------------------------------------------------------- + * SDRAM RCC Clock Configuration (rt_weak, override in board.c if needed) + *---------------------------------------------------------------------------*/ +rt_weak void rt_hw_sdram_clock_init(void) +{ + /* Configure SDRAM delay chain (board-specific, default 0.2ns step) */ + RCC_ConfigSDRAMDelay(RCC_SDRAM_DELAY_0_2NS); + RCC_EnableSDRAMDelayChain(ENABLE); +} + +/*---------------------------------------------------------------------------- + * SDRAM Initialization Sequence + * Based on N32 SDK SDRAM_DeviceInit() + SDRAM_OperationInit() pattern. + *---------------------------------------------------------------------------*/ +static void SDRAM_Initialization_Sequence(SDRAM_DeviceType device) +{ + SDRAM_LoadModeRegisterType load_mode; + __IO uint32_t delay; + int i; + + /*--- Configure device: address, refresh, timing, bus width, etc. ---*/ + + /* Step 1: Set device base address and address mask */ + SDRAM_SetDeviceAddress(device, SDRAM_BANK_ADDR, SDRAM_ADDRESS_MASK); + + /* Step 2: Set refresh interval */ + SDRAM_RefreshIntervalInit(SDRAM_REFRESH_COUNT); + + /* Step 3: Configure timing parameters + * Mapping: STM32-style macro -> N32 SDRAM_TimingType register field + * SELFREFRESHTIME -> RowActiveTime (tRAS) + * ROWCYCLEDELAY -> RowCycleTime (tRC) + * SDRAM_RP_DELAY -> RowActToRowActDelay (tRRD) + * RPDELAY -> PrechargeTime (tRP) + * WRITERECOVERYTIME -> WriteRecoveryTime (tWR) + * SDRAM_REFRESH_CYCLE -> RefreshCycleTime (tRFC) + * RCDDELAY -> RAstoCASDelay (tRCD) + */ + SDRAM_TimingType SDRAM_Timing; + SDRAM_Timing.RowActiveTime = SELFREFRESHTIME; + SDRAM_Timing.RowCycleTime = ROWCYCLEDELAY; + SDRAM_Timing.RowActToRowActDelay = SDRAM_RP_DELAY; + SDRAM_Timing.PrechargeTime = RPDELAY; + SDRAM_Timing.WriteRecoveryTime = WRITERECOVERYTIME; + SDRAM_Timing.RefreshCycleTime = SDRAM_REFRESH_CYCLE; + SDRAM_Timing.RAStoCASDelay = RCDDELAY; + SDRAM_TimingInit(&SDRAM_Timing); + + /* Step 4: Configure device parameters (same as SDRAM_ConfigurationInit in SDK) */ + SDRAM_EnableDevice(device, ENABLE); + SDRAM_EnableRefreshCMD(device, ENABLE); + SDRAM_EnableAutoPrecharge(device, DISABLE); + SDRAM_EnablePrefetchRead(device, DISABLE); + SDRAM_EnableSOM(device, ENABLE); + SDRAM_EnableBankInterleave(device, DISABLE); + SDRAM_ConfigBusWidth(device, SDRAM_HAL_BUS_WIDTH); + SDRAM_ConfigBurstLength(device, SDRAM_HAL_BURSTLEN); + SDRAM_ConfigCASLatency(device, SDRAM_HAL_CAS_LATENCY); + SDRAM_ConfigAddress(device, SDRAM_ADDR_CFG); + + /*--- Send command sequence: Precharge -> Auto-Refresh -> Load Mode ---*/ + + /* Step 5: Precharge all banks + * Per SDK pattern: set clock enable + opcode + chip select + bank + address, + * then trigger by dummy-read of SDRAM->OR register. */ + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_PRECHRG); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(0); + (void)(SDRAM->OR); /* dummy access triggers the operation */ + + /* Step 6: Auto refresh (2 cycles, per SDK convention) */ + for (i = 0; i < 2; i++) + { + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_REFRESH); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(0); + (void)(SDRAM->OR); + } + + /* Step 7: Load mode register */ + load_mode.cmd = 0; + load_mode.Bits.BurstLen = SDRAM_LOADMODE_BURSTLEN; + load_mode.Bits.BurstType = LOADMODE_BURSTTYPE_SEQUENTIAL; + load_mode.Bits.CASLatency = SDRAM_LOADMODE_CASLATENCY; + load_mode.Bits.OpMode = LOADMODE_OPMODE_STANDARD; + load_mode.Bits.WBMode = LOADMODE_WBMODE_BURST; + + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_LOADMODE); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(load_mode.cmd); + (void)(SDRAM->OR); + + /* Wait at least 300us for SDRAM stabilization (per SDK) */ + for (delay = 0; delay < 0xFFFF; delay++); +} +int sdram_test(void); +/*---------------------------------------------------------------------------- + * SDRAM Init (called via INIT_BOARD_EXPORT) + *---------------------------------------------------------------------------*/ +static int SDRAM_Init(void) +{ + int result = RT_EOK; + +#ifdef BSP_SDRAM_BANK1 + sdram_device = SDRAM_DEVICE_1; +#endif +#ifdef BSP_SDRAM_BANK2 + sdram_device = SDRAM_DEVICE_2; +#endif + + /* Reset SDRAM peripheral to default state */ + SDRAM_DeInit(); + + /* Initialize SDRAM clock (board-specific, weak function) */ + rt_hw_sdram_clock_init(); + + /* Configure and initialize the SDRAM device */ + SDRAM_Initialization_Sequence(sdram_device); + + LOG_D("sdram init success, mapped at 0x%X, size is %u bytes, data width is %d", + SDRAM_BANK_ADDR, (BSP_SDRAM_SIZE * 1024U * 1024U), SDRAM_DATA_WIDTH); + +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* Register SDRAM as system heap */ + rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, (BSP_SDRAM_SIZE * 1024U * 1024U)); + LOG_D("memheap registered: name=%s, start=0x%X, size=%u", + ((struct rt_object *)&system_heap)->name, + system_heap.start_addr, system_heap.pool_size); +#endif + + + return result; +} +INIT_BOARD_EXPORT(SDRAM_Init); + +/*---------------------------------------------------------------------------- + * SDRAM Test Command (Finsh shell, enabled by DRV_DEBUG) + *---------------------------------------------------------------------------*/ +#ifdef DRV_DEBUG +//#ifdef FINSH_USING_MSH +int sdram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if SDRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; +#elif SDRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; +#else + char data_width = 4; + uint32_t data = 0; +#endif + + /* Write data */ + LOG_D("Writing %u bytes data, waiting...", (BSP_SDRAM_SIZE * 1024U * 1024U)); + start_time = rt_tick_get(); + for (i = 0; i < (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width; i++) + { +#if SDRAM_DATA_WIDTH == 8 + *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100); +#elif SDRAM_DATA_WIDTH == 16 + *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000); +#else + *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000); +#endif + } + time_cast = rt_tick_get() - start_time; + LOG_D("Write done, time: %d.%03dS.", + time_cast / RT_TICK_PER_SECOND, + time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND + 999) / 1000)); + + /* Read and verify */ + LOG_D("Reading and verifying data, waiting..."); + for (i = 0; i < (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width; i++) + { +#if SDRAM_DATA_WIDTH == 8 + data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != (uint8_t)(i % 100)) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#elif SDRAM_DATA_WIDTH == 16 + data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != (uint16_t)(i % 1000)) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#else + data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != i % 1000) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#endif + } + + if (i >= (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width) + { + LOG_D("SDRAM test success!"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(sdram_test, sdram read / write test) +//#endif /* FINSH_USING_MSH */ +#endif /* DRV_DEBUG */ + +#endif /* BSP_USING_SDRAM */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c index 0c0dd3d99b..62a747423b 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c @@ -1063,7 +1063,8 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m rt_memcpy(dma_aligned_buffer, send_buf, send_length); p_txrx_buffer = dma_aligned_buffer; } - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); + if ((SCB->CCR &(uint32_t)SCB_CCR_DC_Msk) != 0U) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); #else if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4) && send_buf != RT_NULL) /* aligned with 4 bytes? */ { @@ -1214,7 +1215,8 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m if (recv_buf != RT_NULL) { #if defined(SOC_SERIES_N32H7xx) - rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length); + if ((SCB->CCR &(uint32_t)SCB_CCR_DC_Msk) != 0U) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length); #endif /* SOC_SERIES_N32H7xx */ rt_memcpy(recv_buf, p_txrx_buffer, send_length); } diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c index f8bc39a083..8c3f2acb9b 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c @@ -75,21 +75,29 @@ static int int_pow(int x, int y) { if (y == 0) + { return 1; + } if (x == 0) { if (y > 0) + { return 0; + } else + { return -1; + } } if (y < 0) + { return -1; + } - int result = 1; - int base = x; + int result = 1; + int base = x; int exponent = y; /* Fast exponentiation algorithm (binary exponentiation) */ @@ -97,17 +105,23 @@ static int int_pow(int x, int y) { /* Check for overflow */ if (result > INT_MAX / base) + { return -1; + } if (exponent % 2 == 1) + { result *= base; + } exponent /= 2; if (exponent > 0) { if (base > INT_MAX / base) + { return -1; + } base *= base; } @@ -124,7 +138,7 @@ void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div) *div = 1; #if defined(SOC_SERIES_N32H7xx) - rt_uint8_t tim_div, i; + rt_uint8_t tim_div, i; const rt_uint8_t div_group[] = { 0x00U, 0x04U, 0x05U, 0x06U, 0x07U }; if ((timer == BTIM1) || (timer == BTIM2) || (timer == BTIM3) || (timer == BTIM4)) @@ -342,9 +356,9 @@ enum struct n32_clock_timer { rt_clock_timer_t time_device; - TIM_Module *timer; - IRQn_Type tim_irqn; - char *name; + TIM_Module *timer; + IRQn_Type tim_irqn; + char *name; }; static struct n32_clock_timer n32_clock_timer_obj[] = { @@ -423,11 +437,11 @@ static struct n32_clock_timer n32_clock_timer_obj[] = { static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { - uint32_t prescaler_value = 0; - rt_uint32_t tim_div; + uint32_t prescaler_value = 0; + rt_uint32_t tim_div; struct n32_clock_timer *tim_device = RT_NULL; - RCC_ClocksTypeDef RCC_Clocks; - TIM_TimeBaseInitType TIM_TimeBaseStructure; + RCC_ClocksTypeDef RCC_Clocks; + TIM_TimeBaseInitType TIM_TimeBaseStructure; RT_ASSERT(timer != RT_NULL); if (state) @@ -467,9 +481,8 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); TIM_TimeBaseStructure.Period = 10000 - 1; - ; TIM_TimeBaseStructure.Prescaler = prescaler_value; - TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { @@ -540,11 +553,11 @@ static void timer_stop(rt_clock_timer_t *timer) static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { - struct n32_clock_timer *tim_device = RT_NULL; - rt_err_t result = -RT_ERROR; - uint32_t prescaler_value = 0; - rt_uint32_t tim_div; - RCC_ClocksTypeDef RCC_Clocks; + struct n32_clock_timer *tim_device = RT_NULL; + rt_err_t result = -RT_ERROR; + uint32_t prescaler_value = 0; + rt_uint32_t tim_div; + RCC_ClocksTypeDef RCC_Clocks; RT_ASSERT(timer != RT_NULL); RT_ASSERT(arg != RT_NULL); @@ -616,11 +629,11 @@ static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; static const struct rt_clock_timer_ops _ops = { - .init = timer_init, - .start = timer_start, - .stop = timer_stop, + .init = timer_init, + .start = timer_start, + .stop = timer_stop, .count_get = timer_counter_get, - .control = timer_ctrl, + .control = timer_ctrl, }; #ifdef BSP_USING_ATIM1 @@ -877,13 +890,13 @@ void BTIM4_IRQHandler(void) static int n32_clock_timer_init(void) { - rt_uint32_t i = 0; - int result = RT_EOK; + rt_uint32_t i = 0; + int result = RT_EOK; for (i = 0; i < sizeof(n32_clock_timer_obj) / sizeof(n32_clock_timer_obj[0]); i++) { n32_clock_timer_obj[i].time_device.info = &_info; - n32_clock_timer_obj[i].time_device.ops = &_ops; + n32_clock_timer_obj[i].time_device.ops = &_ops; if (rt_clock_timer_register(&n32_clock_timer_obj[i].time_device, n32_clock_timer_obj[i].name, RT_NULL) == RT_EOK) { diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c index 6b02e1a697..04b74d68f5 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c @@ -18,22 +18,22 @@ #define BSP_N32_UART_V1_TX_TIMEOUT 2000 //#define DRV_DEBUG -#define LOG_TAG "drv.usart" +#define LOG_TAG "drv.usart" #include <drv_log.h> -#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ - !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ - !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_UART9) && \ +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_UART9) && \ !defined(BSP_USING_UART10) && !defined(BSP_USING_UART11) && !defined(BSP_USING_UART12) && \ !defined(BSP_USING_UART13) && !defined(BSP_USING_UART14) && !defined(BSP_USING_UART15) && \ !defined(BSP_USING_LPUART1) && !defined(BSP_USING_LPUART2) - #error "Please define at least one BSP_USING_UARTx" +#error "Please define at least one BSP_USING_UARTx" /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif #ifdef RT_SERIAL_USING_DMA - static rt_err_t UART_DMA_Transmit(struct n32_uart *uart); +static rt_err_t UART_DMA_Transmit(struct n32_uart *uart); #endif enum @@ -91,8 +91,7 @@ enum #endif }; -static struct n32_uart_config uart_config[] = -{ +static struct n32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 UART1_CONFIG, #endif @@ -153,7 +152,7 @@ static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_fl { struct n32_uart *uart; rt_base_t level; - rt_size_t recv_len = 0; + rt_size_t recv_len = 0; RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct n32_uart, serial); @@ -253,9 +252,9 @@ static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_fl rt_hw_interrupt_enable(level); } -#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ - defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \ - defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \ +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \ + defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \ defined(BSP_UART10_RX_USING_DMA) || defined(BSP_UART11_RX_USING_DMA) || defined(BSP_UART12_RX_USING_DMA) || \ defined(BSP_UART13_RX_USING_DMA) || defined(BSP_UART14_RX_USING_DMA) || defined(BSP_UART15_RX_USING_DMA) @@ -274,8 +273,8 @@ static void uart_rx_dma_isr(struct n32_uart *uart_drv) } #elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart_drv->config->dma_rx->DMAChx < DMA2_BASE ? DMA1 : DMA2); - uint32_t dma_int_ht = 0; - uint32_t dma_int_tc = 0; + uint32_t dma_int_ht = 0; + uint32_t dma_int_tc = 0; /* Obtain the corresponding interrupt flag macro based on the channel (refer to the TX implementation) */ if (uart_drv->config->dma_rx->DMAChx == DMA1_CH1) @@ -378,9 +377,9 @@ static void uart_rx_dma_isr(struct n32_uart *uart_drv) } #endif -#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \ - defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART5_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || \ - defined(BSP_UART7_TX_USING_DMA) || defined(BSP_UART8_TX_USING_DMA) || defined(BSP_UART9_TX_USING_DMA) || \ +#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \ + defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART5_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || \ + defined(BSP_UART7_TX_USING_DMA) || defined(BSP_UART8_TX_USING_DMA) || defined(BSP_UART9_TX_USING_DMA) || \ defined(BSP_UART10_TX_USING_DMA) || defined(BSP_UART11_TX_USING_DMA) || defined(BSP_UART12_TX_USING_DMA) || \ defined(BSP_UART13_TX_USING_DMA) || defined(BSP_UART14_TX_USING_DMA) || defined(BSP_UART15_TX_USING_DMA) @@ -420,40 +419,72 @@ static void uart_tx_dma_isr(struct n32_uart *uart_drv) #elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart_drv->config->dma_tx->DMAChx < DMA2_BASE ? DMA1 : DMA2); - uint32_t dma_int_tc = 0; + uint32_t dma_int_tc = 0; if (uart_drv->config->dma_tx->DMAChx == DMA1_CH1) + { dma_int_tc = DMA_INT_TXC1; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH2) + { dma_int_tc = DMA_INT_TXC2; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH3) + { dma_int_tc = DMA_INT_TXC3; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH4) + { dma_int_tc = DMA_INT_TXC4; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH5) + { dma_int_tc = DMA_INT_TXC5; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH6) + { dma_int_tc = DMA_INT_TXC6; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH7) + { dma_int_tc = DMA_INT_TXC7; + } else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH8) + { dma_int_tc = DMA_INT_TXC8; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH1) + { dma_int_tc = DMA_INT_TXC1; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH2) + { dma_int_tc = DMA_INT_TXC2; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH3) + { dma_int_tc = DMA_INT_TXC3; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH4) + { dma_int_tc = DMA_INT_TXC4; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH5) + { dma_int_tc = DMA_INT_TXC5; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH6) + { dma_int_tc = DMA_INT_TXC6; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH7) + { dma_int_tc = DMA_INT_TXC7; + } else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH8) + { dma_int_tc = DMA_INT_TXC8; + } if (dma_int_tc != 0 && DMA_GetIntStatus(dma_int_tc, dma_module) == SET) { @@ -485,8 +516,8 @@ static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag #if defined(SOC_SERIES_N32H7xx) - rt_size_t i = 0; - rt_err_t result = RT_EOK; + rt_size_t i = 0; + rt_err_t result = RT_EOK; /* DMA Initialize */ if (RT_DEVICE_FLAG_DMA_RX == flag) { @@ -501,7 +532,9 @@ static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag } if (!DMA_ControllerIsEnabled(uart->config->dma_rx->Instance)) + { DMA_ControllerCmd(uart->config->dma_rx->Instance, ENABLE); + } /* Initialize the specified DMA channel and Whether the specified channel was successfully initialized */ if (DMA_ChannelInit(uart->config->dma_rx->Instance, &uart->dma.RX_DMA_ChInitStr, uart->config->dma_rx->dma_channel) == 0U) @@ -652,10 +685,12 @@ static rt_err_t UART_DMA_Transmit(struct n32_uart *uart) DMA_ChannelCmd(uart->config->dma_tx->Instance, uart->config->dma_tx->dma_channel, DISABLE); if (!DMA_ControllerIsEnabled(uart->config->dma_tx->Instance)) + { DMA_ControllerCmd(uart->config->dma_tx->Instance, ENABLE); + } - uart->dma.TX_DMA_ChInitStr.IntEn = 1U; - uart->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)send_buf; + uart->dma.TX_DMA_ChInitStr.IntEn = 1U; + uart->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)send_buf; uart->dma.TX_DMA_ChInitStr.BlkTfrSize = send_length; DMA_ControllerCmd(uart->config->dma_tx->Instance, ENABLE); @@ -684,7 +719,7 @@ static rt_err_t UART_DMA_Transmit(struct n32_uart *uart) #elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) send_length = uart->dma.tx_dma.total_length; - send_buf = uart->dma.tx_dma.buf; + send_buf = uart->dma.tx_dma.buf; if (send_length == 0 || send_buf == RT_NULL) { @@ -695,42 +730,74 @@ static rt_err_t UART_DMA_Transmit(struct n32_uart *uart) DMA_EnableChannel(uart->config->dma_tx->DMAChx, DISABLE); /* Clear the previous transfer complete flag (to prevent false triggering). */ - DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart->config->dma_tx->DMAChx < DMA2_BASE ? DMA1 : DMA2); - uint32_t dma_flag_tc = 0; + DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart->config->dma_tx->DMAChx < DMA2_BASE ? DMA1 : DMA2); + uint32_t dma_flag_tc = 0; /* Map the channel to the flag. */ if (uart->config->dma_tx->DMAChx == DMA1_CH1) + { dma_flag_tc = DMA_FLAG_TC1; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH2) + { dma_flag_tc = DMA_FLAG_TC2; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH3) + { dma_flag_tc = DMA_FLAG_TC3; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH4) + { dma_flag_tc = DMA_FLAG_TC4; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH5) + { dma_flag_tc = DMA_FLAG_TC5; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH6) + { dma_flag_tc = DMA_FLAG_TC6; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH7) + { dma_flag_tc = DMA_FLAG_TC7; + } else if (uart->config->dma_tx->DMAChx == DMA1_CH8) + { dma_flag_tc = DMA_FLAG_TC8; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH1) + { dma_flag_tc = DMA_FLAG_TC1; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH2) + { dma_flag_tc = DMA_FLAG_TC2; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH3) + { dma_flag_tc = DMA_FLAG_TC3; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH4) + { dma_flag_tc = DMA_FLAG_TC4; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH5) + { dma_flag_tc = DMA_FLAG_TC5; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH6) + { dma_flag_tc = DMA_FLAG_TC6; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH7) + { dma_flag_tc = DMA_FLAG_TC7; + } else if (uart->config->dma_tx->DMAChx == DMA2_CH8) + { dma_flag_tc = DMA_FLAG_TC8; + } if (dma_flag_tc != 0) { @@ -771,11 +838,11 @@ rt_uint32_t n32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) { if (parity == USART_PE_NO) { - mask = 0x00FFU ; + mask = 0x00FFU; } else { - mask = 0x007FU ; + mask = 0x007FU; } } #ifdef USART_WL_9B @@ -783,11 +850,11 @@ rt_uint32_t n32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) { if (parity == USART_PE_NO) { - mask = 0x01FFU ; + mask = 0x01FFU; } else { - mask = 0x00FFU ; + mask = 0x00FFU; } } #endif @@ -808,7 +875,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con USART_StructInit(&USART_InitStructure); USART_InitStructure.BaudRate = cfg->baud_rate; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; #ifdef USART_CTRL1_OSPM USART_InitStructure.OverSampling = cfg->baud_rate > 5000000 ? USART_8OVER : USART_16OVER; @@ -833,9 +900,13 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con { case DATA_BITS_8: if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + { USART_InitStructure.WordLength = USART_WL_9B; + } else + { USART_InitStructure.WordLength = USART_WL_8B; + } break; case DATA_BITS_9: USART_InitStructure.WordLength = USART_WL_9B; @@ -900,7 +971,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct n32_uart *uart; - rt_uint32_t direction; + rt_uint32_t direction; #ifdef RT_SERIAL_USING_DMA rt_ubase_t ctrl_arg = (rt_ubase_t)arg; #endif @@ -1012,13 +1083,14 @@ static int n32_putc(struct rt_serial_device *serial, char c) /* Clear transmission complete flag */ if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) != RESET) + { USART_ClrFlag(uart->config->Instance, USART_FLAG_TXC); + } /* Send data */ USART_SendData(uart->config->Instance, c); - while ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) == RESET) && --block_timeout) - ; + while ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) == RESET) && --block_timeout); return (block_timeout != 0) ? 1 : -1; } @@ -1056,13 +1128,13 @@ static rt_ssize_t n32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t * if (RT_SERIAL_DMA_TX == direction) { #if defined(SOC_SERIES_N32H7xx) - uart->dma.tx_dma.record_length = size; - uart->dma.tx_dma.total_length = size; + uart->dma.tx_dma.record_length = size; + uart->dma.tx_dma.total_length = size; uart->dma.tx_dma.already_send_length = 0U; - uart->dma.tx_dma.buf = buf; + uart->dma.tx_dma.buf = buf; #elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x) uart->dma.tx_dma.total_length = size; - uart->dma.tx_dma.buf = buf; + uart->dma.tx_dma.buf = buf; #endif /* SOC_SERIES_N32H7xx */ /* start once data exchange in DMA mode */ @@ -1082,7 +1154,7 @@ static void uart_isr(struct rt_serial_device *serial) /* UART in mode Receiver */ if ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXDNE) != RESET) && - (USART_GetIntStatus(uart->config->Instance, USART_INT_RXDNE) != RESET)) + (USART_GetIntStatus(uart->config->Instance, USART_INT_RXDNE) != RESET)) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } @@ -1104,9 +1176,9 @@ static void uart_isr(struct rt_serial_device *serial) else { if ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_OREF) != RESET) || - (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_NEF) != RESET) || - (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_FEF) != RESET) || - (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_PEF) != RESET)) + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_NEF) != RESET) || + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_FEF) != RESET) || + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_PEF) != RESET)) { USART_GetFlagStatus(uart->config->Instance, USART_FLAG_OREF | USART_FLAG_NEF | USART_FLAG_FEF | USART_FLAG_PEF); USART_ReceiveData(uart->config->Instance); @@ -1926,8 +1998,7 @@ static void n32_uart_get_dma_config(void) #endif } -static const struct rt_uart_ops n32_uart_ops = -{ +static const struct rt_uart_ops n32_uart_ops = { .configure = n32_configure, .control = n32_control, .putc = n32_putc, @@ -1945,8 +2016,8 @@ int rt_hw_usart_init(void) for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct n32_uart); i++) { /* init UART object */ - uart_obj[i].config = &uart_config[i]; - uart_obj[i].serial.ops = &n32_uart_ops; + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &n32_uart_ops; uart_obj[i].serial.config = config; #ifdef RT_SERIAL_USING_DMA @@ -1966,29 +2037,29 @@ int rt_hw_usart_init(void) /* UART TX DMA Channel1 configuration ---------------------------------------------*/ DMA_ChannelStructInit(&uart_obj[i].dma.TX_DMA_ChInitStr); - uart_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; - uart_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = RT_NULL; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - uart_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - uart_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - uart_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; - uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; - uart_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; - uart_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; - uart_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = RT_NULL; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = RT_NULL; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + uart_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + uart_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; + uart_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = RT_NULL; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterInterval = 0x0U; - uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; - uart_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; - uart_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; - uart_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; - uart_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; - uart_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = uart_obj[i].config->dma_tx->HsInterface; + uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + uart_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; + uart_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + uart_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = uart_obj[i].config->dma_tx->HsInterface; /* DMA controller must be enabled before initializing the channel */ DMA_ControllerCmd(uart_obj[i].config->dma_tx->Instance, ENABLE); @@ -2018,17 +2089,17 @@ int rt_hw_usart_init(void) DMA_DeInit(uart_obj[i].config->dma_tx->DMAChx); DMA_StructInit(&uart_obj[i].dma.TX_DMA_ChInitStr); - uart_obj[i].dma.TX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; - uart_obj[i].dma.TX_DMA_ChInitStr.MemAddr = RT_NULL; - uart_obj[i].dma.TX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_DST; - uart_obj[i].dma.TX_DMA_ChInitStr.BufSize = 0U; - uart_obj[i].dma.TX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE; - uart_obj[i].dma.TX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE; + uart_obj[i].dma.TX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.TX_DMA_ChInitStr.MemAddr = RT_NULL; + uart_obj[i].dma.TX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_DST; + uart_obj[i].dma.TX_DMA_ChInitStr.BufSize = 0U; + uart_obj[i].dma.TX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE; + uart_obj[i].dma.TX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE; uart_obj[i].dma.TX_DMA_ChInitStr.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_BYTE; - uart_obj[i].dma.TX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE; - uart_obj[i].dma.TX_DMA_ChInitStr.CircularMode = DMA_MODE_NORMAL; - uart_obj[i].dma.TX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH; - uart_obj[i].dma.TX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE; + uart_obj[i].dma.TX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE; + uart_obj[i].dma.TX_DMA_ChInitStr.CircularMode = DMA_MODE_NORMAL; + uart_obj[i].dma.TX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH; + uart_obj[i].dma.TX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE; DMA_Init(uart_obj[i].config->dma_tx->DMAChx, &uart_obj[i].dma.TX_DMA_ChInitStr); @@ -2044,9 +2115,7 @@ int rt_hw_usart_init(void) uart_obj[i].dma.rx_dma.block_num = uart_obj[i].serial.config.bufsz / DMA_BLOCK_SIZE + 1; /* Calculate the remain length */ - uart_obj[i].dma.rx_dma.remain_len = ((uart_obj[i].serial.config.bufsz > DMA_BLOCK_SIZE) ? - (uart_obj[i].serial.config.bufsz - DMA_BLOCK_SIZE * (uart_obj[i].dma.rx_dma.block_num - 1U)) : - uart_obj[i].serial.config.bufsz); + uart_obj[i].dma.rx_dma.remain_len = ((uart_obj[i].serial.config.bufsz > DMA_BLOCK_SIZE) ? (uart_obj[i].serial.config.bufsz - DMA_BLOCK_SIZE * (uart_obj[i].dma.rx_dma.block_num - 1U)) : uart_obj[i].serial.config.bufsz); } else { @@ -2071,49 +2140,49 @@ int rt_hw_usart_init(void) /* UART RX DMA Channel1 configuration ---------------------------------------------*/ DMA_ChannelStructInit(&uart_obj[i].dma.RX_DMA_ChInitStr); - uart_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; - uart_obj[i].dma.RX_DMA_ChInitStr.DstAddr = RT_NULL; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - uart_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - uart_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - uart_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; - uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; - uart_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; - uart_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = DMA_BLOCK_SIZE; - uart_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = uart_obj[i].dma.rx_dma.Read_LinkList; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.RX_DMA_ChInitStr.DstAddr = RT_NULL; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + uart_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + uart_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = DMA_BLOCK_SIZE; + uart_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = uart_obj[i].dma.rx_dma.Read_LinkList; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterInterval = 0x0U; - uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; - uart_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED; - uart_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; - uart_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; - uart_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = uart_obj[i].config->dma_rx->HsInterface; + uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED; + uart_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + uart_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = uart_obj[i].config->dma_rx->HsInterface; /* Set LLI control information */ for (rt_size_t j = 0; j < uart_obj[i].dma.rx_dma.block_num; j++) { /* Link List Config */ - uart_obj[i].dma.rx_dma.Read_LinkList[j].IntEn = 0x1U; - uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; - uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddr = RT_NULL; - uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; - uart_obj[i].dma.rx_dma.Read_LinkList[j].DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.rx_dma.Read_LinkList[j].IntEn = 0x1U; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddr = RT_NULL; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; - uart_obj[i].dma.rx_dma.Read_LinkList[j].DstBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcBurstLen = DMA_CH_BURST_LENGTH_1; - uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcGatherEn = false; - uart_obj[i].dma.rx_dma.Read_LinkList[j].DstScatterEn = false; - uart_obj[i].dma.rx_dma.Read_LinkList[j].TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; - uart_obj[i].dma.rx_dma.Read_LinkList[j].BlkTfrSize = DMA_BLOCK_SIZE; - uart_obj[i].dma.rx_dma.Read_LinkList[j].DstLinkedListEn = true; - uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcLinkedListEn = false; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcGatherEn = false; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstScatterEn = false; + uart_obj[i].dma.rx_dma.Read_LinkList[j].TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + uart_obj[i].dma.rx_dma.Read_LinkList[j].BlkTfrSize = DMA_BLOCK_SIZE; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstLinkedListEn = true; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcLinkedListEn = false; /* The last block, so need to link to first block */ if ((j + 1U) == uart_obj[i].dma.rx_dma.block_num) @@ -2142,17 +2211,17 @@ int rt_hw_usart_init(void) DMA_DeInit(uart_obj[i].config->dma_rx->DMAChx); DMA_StructInit(&uart_obj[i].dma.RX_DMA_ChInitStr); - uart_obj[i].dma.RX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; - uart_obj[i].dma.RX_DMA_ChInitStr.MemAddr = RT_NULL; - uart_obj[i].dma.RX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_SRC; - uart_obj[i].dma.RX_DMA_ChInitStr.BufSize = 0U; - uart_obj[i].dma.RX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE; - uart_obj[i].dma.RX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE; + uart_obj[i].dma.RX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.RX_DMA_ChInitStr.MemAddr = RT_NULL; + uart_obj[i].dma.RX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_SRC; + uart_obj[i].dma.RX_DMA_ChInitStr.BufSize = 0U; + uart_obj[i].dma.RX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE; + uart_obj[i].dma.RX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE; uart_obj[i].dma.RX_DMA_ChInitStr.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_BYTE; - uart_obj[i].dma.RX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE; - uart_obj[i].dma.RX_DMA_ChInitStr.CircularMode = DMA_MODE_CIRCULAR; - uart_obj[i].dma.RX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH; - uart_obj[i].dma.RX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE; + uart_obj[i].dma.RX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE; + uart_obj[i].dma.RX_DMA_ChInitStr.CircularMode = DMA_MODE_CIRCULAR; + uart_obj[i].dma.RX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH; + uart_obj[i].dma.RX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE; DMA_Init(uart_obj[i].config->dma_rx->DMAChx, &uart_obj[i].dma.RX_DMA_ChInitStr); diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h index 06353c212e..8abb2b16e4 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h @@ -47,7 +47,7 @@ struct n32_uart { struct n32_uart_config *config; rt_uint32_t DR_mask; - rt_uint32_t tx_block_timeout; + rt_uint32_t tx_block_timeout; #ifdef RT_SERIAL_USING_DMA #if defined(SOC_SERIES_N32H7xx) @@ -85,7 +85,7 @@ struct n32_uart DMA_InitType TX_DMA_ChInitStr; struct { - rt_size_t total_length; + rt_size_t total_length; rt_uint8_t *buf; } tx_dma; diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c index c65357b610..f779883524 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c @@ -21,9 +21,9 @@ struct n32_wdt_obj { rt_watchdog_t watchdog; - IWDG_Module *IWDGx; - uint32_t IWDG_Clk; - void (*IWDGX_ClkCmd)(uint32_t periph, FunctionalState Cmd); + IWDG_Module *IWDGx; + uint32_t IWDG_Clk; + void (*IWDGX_ClkCmd)(uint32_t periph, FunctionalState Cmd); rt_uint32_t current_threshold_s; rt_uint32_t Reload; @@ -31,7 +31,7 @@ struct n32_wdt_obj rt_uint16_t is_start; }; -static struct n32_wdt_obj n32_wdt; +static struct n32_wdt_obj n32_wdt; static struct rt_watchdog_ops ops; static rt_uint32_t wdt_get_prescaler_factor(rt_uint16_t prescaler) @@ -85,7 +85,7 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) return -RT_EBUSY; } - reload_value = (*(rt_uint32_t *)arg); + reload_value = (*(rt_uint32_t *)arg); prescaler_factor = wdt_get_prescaler_factor(n32_wdt.Prescaler); if (LSI_VALUE) @@ -153,17 +153,17 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) int rt_wdt_init(void) { #if defined(SOC_SERIES_N32H7xx) - n32_wdt.IWDGx = IWDG1; - n32_wdt.IWDG_Clk = (RCC_APB5_PERIPHEN_IWDG1PCLK | RCC_APB5_PERIPHEN_IWDG1PCLKLP); + n32_wdt.IWDGx = IWDG1; + n32_wdt.IWDG_Clk = (RCC_APB5_PERIPHEN_IWDG1PCLK | RCC_APB5_PERIPHEN_IWDG1PCLKLP); n32_wdt.IWDGX_ClkCmd = RCC_EnableAPB5PeriphClk2; #endif n32_wdt.Prescaler = IWDG_PRESCALER_DIV256; - n32_wdt.Reload = 0xFFFU; - n32_wdt.is_start = 0U; + n32_wdt.Reload = 0xFFFU; + n32_wdt.is_start = 0U; - ops.init = &wdt_init; - ops.control = &wdt_control; + ops.init = &wdt_init; + ops.control = &wdt_control; n32_wdt.watchdog.ops = &ops; /* register watchdog device */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml index e4646070a9..5e023f9e94 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml @@ -8,3 +8,38 @@ nano: kconfig: - CONFIG_RT_USING_NANO=y +# ------ lcd ------ +lcd: + <<: *scons + kconfig: + - CONFIG_RT_USING_GRAPHIC=y + - CONFIG_BSP_USING_LCD=y + - CONFIG_BSP_LCD_PIXEL_FORMAT_RGB565=y + - CONFIG_BSP_BITS_PER_PIXEL=16 + - CONFIG_BSP_LCD_WIDTH_PIXEL=800 + - CONFIG_BSP_LCD_HEIGHT_PIXEL=480 + - CONFIG_BSP_LCD_HSYNC_WIDTH_PIXEL=34 + - CONFIG_BSP_LCD_VSYNC_HEIGHT_PIXEL=10 + - CONFIG_BSP_LCD_HBP_PIXEL=46 + - CONFIG_BSP_LCD_VBP_PIXEL=23 + - CONFIG_BSP_LCD_HFP_PIXEL=210 + - CONFIG_BSP_LCD_VFP_PIXEL=22 + +# ------ sdram ------ +sdram: + <<: *scons + kconfig: + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_BSP_SDRAM_BANK1=y + - CONFIG_BSP_SDRAM_DATA_WIDTH_32=y + - CONFIG_BSP_SDRAM_COLUMN_BIT_9=y + - CONFIG_BSP_SDRAM_ROW_BIT_12=y + - CONFIG_BSP_SDRAM_CAS_LATENCY_3=y + - CONFIG_BSP_SDRAM_SIZE=32 + +# ------ qspi ------ +qspi: + <<: *scons + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_USING_QSPI2=y diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.config b/bsp/n32/n32hxxx/n32h760zil7-stb/.config index 30312c895c..e495a65abe 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/.config +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.config @@ -1486,6 +1486,8 @@ CONFIG_SOC_SERIES_N32H7xx=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_LCD is not set # CONFIG_BSP_USING_ETH is not set # end of Onboard Peripheral Drivers @@ -1500,7 +1502,7 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_HARD_I2C is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_ADC is not set diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx Binary files differindex b5de00848e..506b1fb808 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h index ee919a8a8f..8015ca89bd 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h @@ -29,7 +29,7 @@ extern "C" { /* NTFx CODE START Extern*/ extern void SysTick_Delayms(uint32_t Delayms); -extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); +extern void DMA_SetPerMemAddr(DMA_ChannelType *DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); extern bool RCC_Configuration(void); extern bool NVIC_Configuration(void); extern bool DMA_Configuration(void); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c index e59369ba84..82162ec4a7 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c @@ -39,7 +39,7 @@ void SysTick_Delayms(uint32_t Delayms) *@param DstAddr Destination address *@return status */ -void DMA_SetSrcDstAddr(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) +void DMA_SetSrcDstAddr(DMA_Module * const DMAy, DMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) { /* Sets channel n source address register */ WRITE_REG(DMAy->CH[ChNum].SA, SrcAddr); @@ -72,7 +72,7 @@ void DMA_SetSrcDstAddr(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Src *@param DstAddr Destination address *@return status */ -void MDMA_SetSrcDstAddr(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) +void MDMA_SetSrcDstAddr(MDMA_Module * const MDMAy, MDMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) { /* Sets channel n source address register */ WRITE_REG(MDMAy->CH[ChNum].SA, SrcAddr); @@ -95,7 +95,10 @@ bool RCC_Configuration(void) RCC_EnableHsi(ENABLE); /* Wait till HSI is ready */ ClockStatus = RCC_WaitHsiStable(); - if (ClockStatus != SUCCESS) return false; + if (ClockStatus != SUCCESS) + { + return false; + } RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); /*Configures the Periph clock source as HSI*/ @@ -147,7 +150,6 @@ bool RCC_Configuration(void) */ bool NVIC_Configuration(void) { - /* NTFx CODE END */ return true; @@ -160,7 +162,6 @@ bool NVIC_Configuration(void) */ bool DMA_Configuration(void) { - /* NTFx CODE END */ return true; @@ -173,7 +174,6 @@ bool DMA_Configuration(void) */ bool GPIO_Configuration(void) { - GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); /* Enable the GPIO clock*/ @@ -182,19 +182,19 @@ bool GPIO_Configuration(void) /*Initialize input GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; - GPIO_InitStructure.Pin = GPIO_PIN_10; + GPIO_InitStructure.Pin = GPIO_PIN_10; GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); /*Initialize AF_PP GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW; - GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; + GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; GPIO_InitStructure.GPIO_Alternate = GPIO_AF7; - GPIO_InitStructure.Pin = GPIO_PIN_9; + GPIO_InitStructure.Pin = GPIO_PIN_9; GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); /* NTFx CODE END */ @@ -215,13 +215,13 @@ bool USART_Configuration(void) /*********initialize the USART1************/ USART_DeInit(USART1); - USART_InitStructure.BaudRate = 115200; - USART_InitStructure.WordLength = USART_WL_8B; - USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - USART_InitStructure.OverSampling = USART_16OVER ; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER; /* Configure USART1 */ USART_Init(USART1, &USART_InitStructure); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig index 206c291e66..1f1614fdd4 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig @@ -2,6 +2,176 @@ menu "Hardware Drivers Config" menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_SDRAM + bool "Enable SDRAM" + default n + if BSP_USING_SDRAM + choice BSP_SDRAM_BANK_SEL + prompt "Select SDRAM Bank" + default BSP_SDRAM_BANK1 + + config BSP_SDRAM_BANK1 + bool "Select SDRAM Bank1" + + config BSP_SDRAM_BANK2 + bool "Select SDRAM Bank2" + endchoice + + choice BSP_SDRAM_DATA_WIDTH_SEL + prompt "Select SDRAM Data Width" + default BSP_SDRAM_DATA_WIDTH_32 + + config BSP_SDRAM_DATA_WIDTH_8 + bool "SDRAM Data Width 8-bits" + + config BSP_SDRAM_DATA_WIDTH_16 + bool "SDRAM Data Width 16-bits" + + config BSP_SDRAM_DATA_WIDTH_32 + bool "SDRAM Data Width 32-bits" + endchoice + + choice BSP_SDRAM_COLUMN_BITS_SEL + prompt "Select SDRAM Column Bits" + default BSP_SDRAM_COLUMN_BIT_9 + + config BSP_SDRAM_COLUMN_BIT_8 + bool "SDRAM SDRAM Column Bits 8-bits" + + config BSP_SDRAM_COLUMN_BIT_9 + bool "SDRAM SDRAM Column Bits 9-bits" + + config BSP_SDRAM_COLUMN_BIT_10 + bool "SDRAM SDRAM Column Bits 10-bits" + + config BSP_SDRAM_COLUMN_BIT_11 + bool "SDRAM SDRAM Column Bits 11-bits" + endchoice + + choice BSP_SDRAM_ROW_BITS_SEL + prompt "Select SDRAM Row Bits" + default BSP_SDRAM_ROW_BIT_12 + + config BSP_SDRAM_ROW_BIT_11 + bool "SDRAM SDRAM Row Bits 11-bits" + + config BSP_SDRAM_ROW_BIT_12 + bool "SDRAM SDRAM Row Bits 12-bits" + + config BSP_SDRAM_ROW_BIT_13 + bool "SDRAM SDRAM Row Bits 13-bits" + endchoice + + choice BSP_SDRAM_CAS_LATENCY_SEL + prompt "Select SDRAM CAS Latency" + default BSP_SDRAM_CAS_LATENCY_3 + + config BSP_SDRAM_CAS_LATENCY_1 + bool "SDRAM SDRAM CAS Latency 1" + + config BSP_SDRAM_CAS_LATENCY_2 + bool "SDRAM SDRAM CAS Latency 2" + + config BSP_SDRAM_CAS_LATENCY_3 + bool "SDRAM SDRAM CAS Latency 3" + endchoice + + config BSP_SDRAM_SIZE + int "SDRAM Size (MBytes)" + range 8 256 + default 32 + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + select BSP_USING_SDRAM + if BSP_USING_LCD + config BSP_BITS_PER_PIXEL + int "LCD Bits Per Pixel" + default 16 + + choice BSP_LCD_PIXEL_FORMAT_SEL + prompt "Select LCD PIXEL FORMAT" + default BSP_LCD_PIXEL_FORMAT_RGB565 + + config BSP_LCD_PIXEL_FORMAT_RGB565 + bool "SDRAM LCD Pixel Format RGB565" + + config BSP_LCD_PIXEL_FORMAT_ARGB8888 + bool "SDRAM LCD Pixel Format ARGB8888" + + config BSP_LCD_PIXEL_FORMAT_RGB888 + bool "SDRAM LCD Pixel Format RGB888" + endchoice + + config BSP_LCD_WIDTH_PIXEL + int "LCD Width Pixel" + default 800 + + config BSP_LCD_HEIGHT_PIXEL + int "LCD Height Pixel" + default 480 + + config BSP_LCD_HSYNC_WIDTH_PIXEL + int "LCD Hsync Width Pixel" + default 34 + + config BSP_LCD_VSYNC_HEIGHT_PIXEL + int "LCD Vsync Height Pixel" + default 10 + + config BSP_LCD_HBP_PIXEL + int "LCD HBP Pixel" + default 46 + + config BSP_LCD_VBP_PIXEL + int "LCD VBP Pixel" + default 23 + + config BSP_LCD_HFP_PIXEL + int "LCD HFP Pixel" + default 210 + + config BSP_LCD_VFP_PIXEL + int "LCD VFP Pixel" + default 22 + + choice BSP_LCD_BACKLIGHT_SEL + prompt "Select LCD BACKLIGHT Control Type" + default BSP_LCD_BACKLIGHT_USING_GPIO + + config BSP_LCD_BACKLIGHT_USING_GPIO + bool "LCD BACKLIGHT Using GPIO Control" + + config BSP_LCD_BACKLIGHT_USING_PWM + bool "LCD BACKLIGHT Using PWM Control" + select RT_USING_PWM + select BSP_USING_PWM + endchoice + + if BSP_LCD_BACKLIGHT_USING_GPIO + config BSP_LCD_BACKLIGHT_PIN + int "Backlight GPIO Port" + default 115 + + config BSP_LCD_DISPLAY_PIN + int "Display GPIO Pin" + default 26 + endif + + if BSP_LCD_BACKLIGHT_USING_PWM + config BSP_LCD_PWM_DEV_NAME + string "PWM Device Name" + default "pwm1" + + config BSP_LCD_PWM_DEV_CHANNEL + int "PWM Channel" + default 1 + endif + endif + + menuconfig BSP_USING_ETH bool "Enable Ethernet" default n @@ -219,6 +389,17 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + menuconfig BSP_USING_QSPI + bool "Enable QSPI Quad SPI BUS" + default n + select RT_USING_QSPI + select RT_USING_SPI + if BSP_USING_QSPI + config BSP_USING_QSPI2 + bool "Enable QSPI2 BUS" + default n + endif + config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h new file mode 100644 index 0000000000..cf09cfcec6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-21 ox-horse first version for N32H760ZIL7-STB (IS42S32800J) + */ +/* + * SDRAM Chip: IS42S32800J + * 4 Banks x 2M words x 32 bits = 32 MB + * 12 row address bits, 9 column address bits + * + * + * N32H760 SDRAM Controller: + * SDRAM1 base: 0xC0000000 (can remap to 0x60000000) + * SDRAM2 base: 0xD0000000 + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +#include "board.h" + +/*============================================================================ + * Part 0: N32cube SDRAM clock and GPIO Configuration + *============================================================================*/ +/* clock config in RCC_Configuration()*/ +/* gpio config in GPIO_Configuration()*/ + +/*============================================================================ + * Part 1: SDRAM Device Configuration + *============================================================================*/ + +/* Bank select: 1 = SDRAM1 (0xC0000000), 2 = SDRAM2 (0xD0000000) */ +#ifdef BSP_SDRAM_BANK1 +#define SDRAM_BANK_ADDR ((uint32_t)0xC0000000) +#endif /* BSP_SDRAM_BANK1 */ +#ifdef BSP_SDRAM_BANK2 +#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) +#endif /* BSP_SDRAM_BANK2 */ + +/* Data bus width: 8 / 16 / 32 */ +#ifdef BSP_SDRAM_DATA_WIDTH_8 +#define SDRAM_DATA_WIDTH 8 +#endif /* BSP_SDRAM_DATA_WIDTH_8 */ +#ifdef BSP_SDRAM_DATA_WIDTH_16 +#define SDRAM_DATA_WIDTH 16 +#endif /* BSP_SDRAM_DATA_WIDTH_16 */ +#ifdef BSP_SDRAM_DATA_WIDTH_32 +#define SDRAM_DATA_WIDTH 32 +#endif /* BSP_SDRAM_DATA_WIDTH_32 */ + + +/* Column address bits: 8-256 / 9-512 / 10-1024 / 11-2048 */ +#ifdef BSP_SDRAM_COLUMN_BIT_8 +#define SDRAM_COLUMN_BITS 8 +#endif /* BSP_SDRAM_COLUMN_BIT_8 */ +#ifdef BSP_SDRAM_COLUMN_BIT_9 +#define SDRAM_COLUMN_BITS 9 +#endif /* BSP_SDRAM_COLUMN_BIT_9 */ +#ifdef BSP_SDRAM_COLUMN_BIT_10 +#define SDRAM_COLUMN_BITS 10 +#endif /* BSP_SDRAM_COLUMN_BIT_10 */ +#ifdef BSP_SDRAM_COLUMN_BIT_11 +#define SDRAM_COLUMN_BITS 11 +#endif /* BSP_SDRAM_COLUMN_BIT_11 */ + +/* Row address bits: 11-2048 / 12-4096 / 13-8192 */ +#ifdef BSP_SDRAM_ROW_BIT_11 +#define SDRAM_ROW_BITS 11 +#endif /* BSP_SDRAM_ROW_BIT_11 */ +#ifdef BSP_SDRAM_ROW_BIT_12 +#define SDRAM_ROW_BITS 12 +#endif /* BSP_SDRAM_ROW_BIT_12 */ +#ifdef BSP_SDRAM_ROW_BIT_13 +#define SDRAM_ROW_BITS 13 +#endif /* BSP_SDRAM_ROW_BIT_13 */ + +/* Address mask for device chip-select matching */ +#define SDRAM_ADDRESS_MASK ((uint32_t)(0xFFFFFFFF - ((BSP_SDRAM_SIZE * 1024U * 1024U) - 1))) + +/*============================================================================ + * Part 2: Timing Parameters (unit: SDRAM clock cycles) + * All values below assume SDRAM clock = 100 MHz (tCK = 10 ns). + * Recalculate when using a different SDRAM frequency. + *============================================================================*/ + +/* tRAS: Row Active Time (min 42ns → ceil(42/10) = 5) */ +#define SELFREFRESHTIME 7 + +/* tRC: Row Cycle Time (min 60ns → ceil(60/10) = 6) */ +#define ROWCYCLEDELAY 9 + +/* tRP: Precharge Time (min 18ns → ceil(18/10) = 2) */ +#define RPDELAY 4 + +/* tWR: Write Recovery (min 12ns → ceil(12/10) = 2) */ +#define WRITERECOVERYTIME 3 + +/* tRCD: RAS to CAS Delay (min 18ns → ceil(18/10) = 2) */ +#define RCDDELAY 4 + +/* tRRD: Row Activate to Row Activate delay (min 12ns → ceil(12/10) = 2) */ +#define SDRAM_RP_DELAY 3 + +/* tRFC: Refresh Cycle Time (min 67.5ns for 256Mb → ceil(67.5/10) = 7) */ +#define SDRAM_REFRESH_CYCLE 9 + +/* Auto-refresh interval counter value + * Formula: RefreshInterval = SDRAM_CLK_MHz * tREF_ms * 1000 / Nrows + * For example: SDRAM_CLK=133MHz, tREF=64ms, rows=4096: + * = 133 * 64 * 1000 / 4096 ≈ 0x07A1 + * Adjust based on actual SDRAMMEMCLK configuration. */ +#define SDRAM_REFRESH_COUNT ((uint32_t)0x0750) /* whichever is smaller */ + +/*============================================================================ + * Part 3: SDRAM Chip Mode Register Value (sent via LOADMODE command) + * These macros are also defined internally in drv_sdram.c. + *============================================================================*/ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +#endif /* __SDRAM_PORT_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx index d4cb02535c..8646d492b6 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx @@ -181,4 +181,1020 @@ </TargetOption> </Target> + <Group> + <GroupName>Applications</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>applications\main.c</PathWithFileName> + <FilenameWithoutPath>main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>CPU</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + 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<PathWithFileName>packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_usart.c</PathWithFileName> + <FilenameWithoutPath>n32h7xx_usart.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Libraries-CMSIS</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>10</GroupNumber> + <FileNumber>76</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>packages\n32h7xx_cmsis_driver-latest\device\system_n32h7xx.c</PathWithFileName> + <FilenameWithoutPath>system_n32h7xx.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>10</GroupNumber> + <FileNumber>77</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>packages\n32h7xx_cmsis_driver-latest\device\startup\startup_n32h73x_76x.s</PathWithFileName> + <FilenameWithoutPath>startup_n32h73x_76x.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>10</GroupNumber> + <FileNumber>78</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>packages\n32h7xx_cmsis_driver-latest\device\soc_mdk.c</PathWithFileName> + <FilenameWithoutPath>soc_mdk.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + </ProjectOpt> diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx index db303dddbd..d0e5eb56e7 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx @@ -1,7 +1,10 @@ <?xml version="1.0" encoding="UTF-8" standalone="no" ?> <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + <SchemaVersion>2.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> <Target> <TargetName>rt-thread</TargetName> @@ -16,28 +19,28 @@ <PackID>Nationstech.N32H7xx_DFP.1.2.0</PackID> <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x24000000,0x20000) IROM(0x15000000,0x1E0000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu> - <FlashUtilSpec /> - <StartupFile /> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048 -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash\N32H76x_2048.FLM))</FlashDriverDll> <DeviceId>0</DeviceId> <RegisterFile>$$Device:N32H760xIx7$firmware\CMSIS\device\N32H76x.h</RegisterFile> - <MemoryEnv /> - <Cmp /> - <Asm /> - <Linker /> - <OHString /> - <InfinionOptionDll /> - <SLE66CMisc /> - <SLE66AMisc /> - <SLE66LinkerMisc /> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> <SFDFile>$$Device:N32H760xIx7$svd\N32H76x.svd</SFDFile> <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> - <BinPath /> - <IncludePath /> - <LibPath /> - <RegisterFilePath /> - <DBRegisterFilePath /> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> <TargetStatus> <Error>0</Error> <ExitCodeStop>0</ExitCodeStop> @@ -59,8 +62,8 @@ <BeforeCompile> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopU1X>0</nStopU1X> @@ -69,8 +72,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -80,14 +83,14 @@ <RunUserProg1>1</RunUserProg1> <RunUserProg2>0</RunUserProg2> <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> - <UserProg2Name /> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopA1X>0</nStopA1X> <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString /> + <SVCSIdString></SVCSIdString> </TargetCommonOption> <CommonProperty> <UseCPPCompiler>0</UseCPPCompiler> @@ -101,8 +104,8 @@ <AssembleAssemblyFile>0</AssembleAssemblyFile> <PublicsOnly>0</PublicsOnly> <StopOnExitCode>3</StopOnExitCode> - <CustomArgument /> - <IncludeLibraryModules /> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> <ComprImg>1</ComprImg> </CommonProperty> <DllOption> @@ -135,11 +138,11 @@ </Flash1> <bUseTDR>1</bUseTDR> <Flash2>BIN\UL2CM3.DLL</Flash2> - <Flash3 /> - <Flash4 /> - <pFcarmOut /> - <pFcarmGrp /> - <pFcArmRoot /> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> @@ -172,7 +175,7 @@ <RvctClst>0</RvctClst> <GenPPlst>0</GenPPlst> <AdsCpuType>"Cortex-M7"</AdsCpuType> - <RvctDeviceName /> + <RvctDeviceName></RvctDeviceName> <mOS>0</mOS> <uocRom>0</uocRom> <uocRam>0</uocRam> @@ -306,7 +309,7 @@ <Size>0x0</Size> </OCR_RVCT10> </OnChipMemories> - <RvctStartVector /> + <RvctStartVector></RvctStartVector> </ArmAdsMisc> <Cads> <interw>1</interw> @@ -333,10 +336,10 @@ <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls /> - <Define>USING_TCM, __DCACHE_PRESENT=1, RT_USING_LIBC, __STDC_LIMIT_MACROS, CORE_CM7, N32H76x, __RTTHREAD__, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, __ICACHE_PRESENT=1, __CLK_TCK=RT_TICK_PER_SECOND</Define> - <Undefine /> - <IncludePath>board;..\libraries\N32_Drivers\drivers;..\..\..\..\libcpu\arm\cortex-m7;applications;..\..\..\..\libcpu\arm\common;..\..\..\..\components\libc\posix\io\poll;..\libraries\N32_Drivers\drivers\config;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\epoll;.;board\Cube_Config\USER\inc;..\..\..\..\components\finsh;..\..\..\..\components\net\utest;..\..\..\..\components\drivers\smp_call;..\..\..\..\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\N32_Drivers;..\..\..\..\components\drivers\include;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\..\components\drivers\include</IncludePath> + <MiscControls></MiscControls> + <Define>N32H76x, RT_USING_LIBC, __ICACHE_PRESENT=1, __CLK_TCK=RT_TICK_PER_SECOND, __DCACHE_PRESENT=1, CORE_CM7, USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, USING_TCM, __RTTHREAD__</Define> + <Undefine></Undefine> + <IncludePath>..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\include;board;..\..\..\..\components\libc\posix\ipc;..\libraries\N32_Drivers\drivers\config;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;applications;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\net\utest;board\Cube_Config\USER\inc;..\..\..\..\libcpu\arm\cortex-m7;..\..\..\..\components\drivers\include;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\common;..\libraries\N32_Drivers;..\..\..\..\components\finsh;..\libraries\N32_Drivers\drivers;..\..\..\..\components\libc\compilers\common\extension;.</IncludePath> </VariousControls> </Cads> <Aads> @@ -351,10 +354,10 @@ <useXO>0</useXO> <ClangAsOpt>4</ClangAsOpt> <VariousControls> - <MiscControls /> - <Define /> - <Undefine /> - <IncludePath /> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> </VariousControls> </Aads> <LDads> @@ -366,13 +369,13 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> - <pXoBase /> + <pXoBase></pXoBase> <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile> - <IncludeLibs /> - <IncludeLibsPath /> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> <Misc>--entry Reset_Handler</Misc> - <LinkerInputFile /> - <DisabledWarnings /> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> </LDads> </TargetArmAds> </TargetOption> @@ -395,36 +398,26 @@ <FileType>1</FileType> <FilePath>..\..\..\..\libcpu\arm\common\atomic_arm.c</FilePath> </File> - </Files> - <Files> <File> <FileName>div0.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\libcpu\arm\common\div0.c</FilePath> </File> - </Files> - <Files> <File> <FileName>showmem.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\libcpu\arm\common\showmem.c</FilePath> </File> - </Files> - <Files> <File> <FileName>context_rvds.S</FileName> <FileType>2</FileType> <FilePath>..\..\..\..\libcpu\arm\cortex-m7\context_rvds.S</FilePath> </File> - </Files> - <Files> <File> <FileName>cpu_cache.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</FilePath> </File> - </Files> - <Files> <File> <FileName>cpuport.c</FileName> <FileType>1</FileType> @@ -440,222 +433,668 @@ <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\core\device.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>completion_comm.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\completion_comm.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>completion_up.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\completion_up.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>condvar.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\condvar.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>dataqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\dataqueue.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>pipe.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\pipe.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>ringblk_buf.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>ringbuffer.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\ringbuffer.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>waitqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\waitqueue.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>workqueue.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\ipc\workqueue.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>dev_pin.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\pin\dev_pin.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>dev_serial.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\drivers\serial\dev_serial.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_IPC_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> @@ -671,29 +1110,21 @@ <FileType>1</FileType> <FilePath>..\libraries\N32_Drivers\drivers\drv_gpio.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_usart.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\N32_Drivers\drivers\drv_usart.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_common.c</FileName> <FileType>1</FileType> <FilePath>..\libraries\N32_Drivers\drv_common.c</FilePath> </File> - </Files> - <Files> <File> <FileName>n32h7xx_cfg.c</FileName> <FileType>1</FileType> <FilePath>board\Cube_Config\USER\src\n32h7xx_cfg.c</FilePath> </File> - </Files> - <Files> <File> <FileName>board.c</FileName> <FileType>1</FileType> @@ -702,6 +1133,459 @@ </Files> </Group> <Group> + <GroupName>Filesystem</GroupName> + <Files> + <File> + <FileName>devfs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>dfs_elm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>ff.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>ffunicode.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>dfs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\src\dfs.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>dfs_file.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\src\dfs_file.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>dfs_fs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\src\dfs_fs.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>dfs_posix.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\dfs\dfs_v1\src\dfs_posix.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls> --c99</MiscControls> + <Define> </Define> + <Undefine> </Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + </Files> + </Group> + <Group> <GroupName>Finsh</GroupName> <Files> <File> @@ -709,27 +1593,26 @@ <FileType>1</FileType> <FilePath>..\..\..\..\components\finsh\shell.c</FilePath> </File> - </Files> - <Files> <File> <FileName>msh.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\finsh\msh.c</FilePath> </File> - </Files> - <Files> <File> <FileName>msh_parse.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\finsh\msh_parse.c</FilePath> </File> - </Files> - <Files> <File> <FileName>cmd.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\components\finsh\cmd.c</FilePath> </File> + <File> + <FileName>msh_file.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\components\finsh\msh_file.c</FilePath> + </File> </Files> </Group> <Group> @@ -740,279 +1623,836 @@ <FileType>1</FileType> <FilePath>..\..\..\..\src\clock.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>components.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\components.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>cpu_up.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\cpu_up.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>defunct.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\defunct.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>idle.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\idle.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>ipc.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\ipc.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>irq.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\irq.c</FilePath> <FileOption> + <CommonProperty> + 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<v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>kservice.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\kservice.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>mem.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\mem.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>mempool.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\mempool.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>object.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\object.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>scheduler_comm.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\scheduler_comm.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>scheduler_up.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\scheduler_up.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>thread.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\thread.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> </FileOption> </File> - </Files> - <Files> <File> <FileName>timer.c</FileName> <FileType>1</FileType> <FilePath>..\..\..\..\src\timer.c</FilePath> <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> <FileArmAds> <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <uGnu>2</uGnu> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> <VariousControls> <MiscControls> </MiscControls> <Define>__RT_KERNEL_SOURCE__</Define> <Undefine> </Undefine> - <IncludePath> </IncludePath> + <IncludePath></IncludePath> </VariousControls> </Cads> </FileArmAds> @@ -1028,85 +2468,61 @@ <FileType>1</FileType> <FilePath>..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath> </File> - </Files> - <Files> <File> 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<FileName>n32h7xx_rcc.c</FileName> <FileType>1</FileType> <FilePath>packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_rcc.c</FilePath> </File> - </Files> - <Files> <File> <FileName>n32h7xx_dbg.c</FileName> <FileType>1</FileType> <FilePath>packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dbg.c</FilePath> </File> - </Files> - <Files> <File> <FileName>n32h7xx_exti.c</FileName> <FileType>1</FileType> <FilePath>packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_exti.c</FilePath> </File> - </Files> - <Files> <File> <FileName>n32h7xx_usart.c</FileName> <FileType>1</FileType> @@ -1195,15 +2593,11 @@ <FileType>1</FileType> <FilePath>packages\n32h7xx_cmsis_driver-latest\device\system_n32h7xx.c</FilePath> </File> - </Files> - <Files> <File> <FileName>startup_n32h73x_76x.s</FileName> <FileType>2</FileType> <FilePath>packages\n32h7xx_cmsis_driver-latest\device\startup\startup_n32h73x_76x.s</FilePath> </File> - </Files> - <Files> <File> <FileName>soc_mdk.c</FileName> <FileType>1</FileType> @@ -1214,9 +2608,20 @@ </Groups> </Target> </Targets> + <RTE> - <apis /> - <components /> - <files /> + <apis/> + <components/> + <files/> </RTE> + + <LayerInfo> + <Layers> + <Layer> + <LayName>project</LayName> + <LayPrjMark>1</LayPrjMark> + </Layer> + </Layers> + </LayerInfo> + </Project> |