diff options
| author | wdfk-prog <[email protected]> | 2024-08-05 23:56:29 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2026-03-15 13:02:57 +0800 |
| commit | b7686b8d793527b14d3ff52a7db42a01f9dc6f69 (patch) | |
| tree | 7920a074d09f8052c395cad09184cc6808b95e78 | |
| parent | e10d364f4e201f648a999b1a38878d7f92496308 (diff) | |
[libcpu][cortex-m7]Canonical alignment
| -rw-r--r-- | libcpu/arm/cortex-m7/cpu_cache.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 058abe49c2..8f9d8ae243 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ rt_base_t rt_hw_cpu_icache_status(void) void rt_hw_cpu_icache_ops(int ops, void* addr, int size) { - rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); + rt_uint32_t address = RT_ALIGN_DOWN((rt_uint32_t)addr, L1CACHE_LINESIZE_BYTE); rt_int32_t size_byte = size + address - (rt_uint32_t)addr; rt_uint32_t linesize = 32U; if (ops & RT_HW_CACHE_INVALIDATE) @@ -70,7 +70,7 @@ rt_base_t rt_hw_cpu_dcache_status(void) void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) { - rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); + rt_uint32_t startAddr = RT_ALIGN_DOWN((rt_uint32_t)addr, L1CACHE_LINESIZE_BYTE); rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; rt_uint32_t clean_invalid = RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE; |