[gd32/arm][drivers]: add support for the H7 series and optimize the GPIO driver

2 files changed, 285 insertions, 106 deletions

diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
index cb43335dea..01e800cb84 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
@@ -6,29 +6,30 @@
  * Change Logs:
  * Date           Author            Notes
  * 2021-08-20     BruceOu           the first version
+ * 2025-11-13     RealThread        general GD driver adaptation
  */
 
 #include <rtdevice.h>
 #include <rthw.h>
 #include <rtconfig.h>
+#include <stdlib.h>
 
 #ifdef RT_USING_PIN
 
 #include "drv_gpio.h"
 
-static const struct pin_index pins[] =
-{
+static const struct pin_index pins[] = {
 #ifdef GPIOA
-    GD32_PIN(0,  A, 0),
-    GD32_PIN(1,  A, 1),
-    GD32_PIN(2,  A, 2),
-    GD32_PIN(3,  A, 3),
-    GD32_PIN(4,  A, 4),
-    GD32_PIN(5,  A, 5),
-    GD32_PIN(6,  A, 6),
-    GD32_PIN(7,  A, 7),
-    GD32_PIN(8,  A, 8),
-    GD32_PIN(9,  A, 9),
+    GD32_PIN(0, A, 0),
+    GD32_PIN(1, A, 1),
+    GD32_PIN(2, A, 2),
+    GD32_PIN(3, A, 3),
+    GD32_PIN(4, A, 4),
+    GD32_PIN(5, A, 5),
+    GD32_PIN(6, A, 6),
+    GD32_PIN(7, A, 7),
+    GD32_PIN(8, A, 8),
+    GD32_PIN(9, A, 9),
     GD32_PIN(10, A, 10),
     GD32_PIN(11, A, 11),
     GD32_PIN(12, A, 12),
@@ -183,65 +184,62 @@ static const struct pin_index pins[] =
 };
 
 #if defined SOC_SERIES_GD32E23x
-static const struct pin_irq_map pin_irq_map[] =
-{
-    {GPIO_PIN_0,  EXTI0_1_IRQn},
-    {GPIO_PIN_1,  EXTI0_1_IRQn},
-    {GPIO_PIN_2,  EXTI2_3_IRQn},
-    {GPIO_PIN_3,  EXTI2_3_IRQn},
-    {GPIO_PIN_4,  EXTI4_15_IRQn},
-    {GPIO_PIN_5,  EXTI4_15_IRQn},
-    {GPIO_PIN_6,  EXTI4_15_IRQn},
-    {GPIO_PIN_7,  EXTI4_15_IRQn},
-    {GPIO_PIN_8,  EXTI4_15_IRQn},
-    {GPIO_PIN_9,  EXTI4_15_IRQn},
-    {GPIO_PIN_10, EXTI4_15_IRQn},
-    {GPIO_PIN_11, EXTI4_15_IRQn},
-    {GPIO_PIN_12, EXTI4_15_IRQn},
-    {GPIO_PIN_13, EXTI4_15_IRQn},
-    {GPIO_PIN_14, EXTI4_15_IRQn},
-    {GPIO_PIN_15, EXTI4_15_IRQn},
+static const struct pin_irq_map pin_irq_map[] = {
+    { GPIO_PIN_0, EXTI0_1_IRQn },
+    { GPIO_PIN_1, EXTI0_1_IRQn },
+    { GPIO_PIN_2, EXTI2_3_IRQn },
+    { GPIO_PIN_3, EXTI2_3_IRQn },
+    { GPIO_PIN_4, EXTI4_15_IRQn },
+    { GPIO_PIN_5, EXTI4_15_IRQn },
+    { GPIO_PIN_6, EXTI4_15_IRQn },
+    { GPIO_PIN_7, EXTI4_15_IRQn },
+    { GPIO_PIN_8, EXTI4_15_IRQn },
+    { GPIO_PIN_9, EXTI4_15_IRQn },
+    { GPIO_PIN_10, EXTI4_15_IRQn },
+    { GPIO_PIN_11, EXTI4_15_IRQn },
+    { GPIO_PIN_12, EXTI4_15_IRQn },
+    { GPIO_PIN_13, EXTI4_15_IRQn },
+    { GPIO_PIN_14, EXTI4_15_IRQn },
+    { GPIO_PIN_15, EXTI4_15_IRQn },
 };
 #else
-static const struct pin_irq_map pin_irq_map[] =
-{
-    {GPIO_PIN_0,  EXTI0_IRQn},
-    {GPIO_PIN_1,  EXTI1_IRQn},
-    {GPIO_PIN_2,  EXTI2_IRQn},
-    {GPIO_PIN_3,  EXTI3_IRQn},
-    {GPIO_PIN_4,  EXTI4_IRQn},
-    {GPIO_PIN_5,  EXTI5_9_IRQn},
-    {GPIO_PIN_6,  EXTI5_9_IRQn},
-    {GPIO_PIN_7,  EXTI5_9_IRQn},
-    {GPIO_PIN_8,  EXTI5_9_IRQn},
-    {GPIO_PIN_9,  EXTI5_9_IRQn},
-    {GPIO_PIN_10, EXTI10_15_IRQn},
-    {GPIO_PIN_11, EXTI10_15_IRQn},
-    {GPIO_PIN_12, EXTI10_15_IRQn},
-    {GPIO_PIN_13, EXTI10_15_IRQn},
-    {GPIO_PIN_14, EXTI10_15_IRQn},
-    {GPIO_PIN_15, EXTI10_15_IRQn},
+static const struct pin_irq_map pin_irq_map[] = {
+    { GPIO_PIN_0, EXTI0_IRQn },
+    { GPIO_PIN_1, EXTI1_IRQn },
+    { GPIO_PIN_2, EXTI2_IRQn },
+    { GPIO_PIN_3, EXTI3_IRQn },
+    { GPIO_PIN_4, EXTI4_IRQn },
+    { GPIO_PIN_5, EXTI5_9_IRQn },
+    { GPIO_PIN_6, EXTI5_9_IRQn },
+    { GPIO_PIN_7, EXTI5_9_IRQn },
+    { GPIO_PIN_8, EXTI5_9_IRQn },
+    { GPIO_PIN_9, EXTI5_9_IRQn },
+    { GPIO_PIN_10, EXTI10_15_IRQn },
+    { GPIO_PIN_11, EXTI10_15_IRQn },
+    { GPIO_PIN_12, EXTI10_15_IRQn },
+    { GPIO_PIN_13, EXTI10_15_IRQn },
+    { GPIO_PIN_14, EXTI10_15_IRQn },
+    { GPIO_PIN_15, EXTI10_15_IRQn },
 };
 #endif
 
-struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
-{
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] = {
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
+    { -1, 0, RT_NULL, RT_NULL },
 };
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
@@ -259,7 +257,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     {
         index = &pins[pin];
         if (index->index == -1)
-        index = RT_NULL;
+            index = RT_NULL;
     }
     else
     {
@@ -269,6 +267,175 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 }
 
+int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk)
+{
+    if (pin_name == NULL || port == NULL || pin == NULL || clk == NULL)
+    {
+        return -RT_ERROR;
+    }
+
+    if (rt_strlen(pin_name) < 3 || pin_name[0] != 'P')
+    {
+        return -RT_ERROR;
+    }
+
+    char port_letter = pin_name[1];
+    switch (port_letter)
+    {
+#ifdef GPIOA
+    case 'A':
+        *port = GPIOA;
+        *clk = RCU_GPIOA;
+        break;
+#endif /* GPIOA */
+#ifdef GPIOB
+    case 'B':
+        *port = GPIOB;
+        *clk = RCU_GPIOB;
+        break;
+#endif /* GPIOB */
+#ifdef GPIOC
+    case 'C':
+        *port = GPIOC;
+        *clk = RCU_GPIOC;
+        break;
+#endif /* GPIOC */
+#ifdef GPIOD
+    case 'D':
+        *port = GPIOD;
+        *clk = RCU_GPIOD;
+        break;
+#endif /* GPIOD */
+#ifdef GPIOE
+    case 'E':
+        *port = GPIOE;
+        *clk = RCU_GPIOE;
+        break;
+#endif /* GPIOE */
+#ifdef GPIOF
+    case 'F':
+        *port = GPIOF;
+        *clk = RCU_GPIOF;
+        break;
+#endif /* GPIOF */
+#ifdef GPIOG
+    case 'G':
+        *port = GPIOG;
+        *clk = RCU_GPIOG;
+        break;
+#endif /* GPIOG */
+#ifdef GPIOH
+    case 'H':
+        *port = GPIOH;
+        *clk = RCU_GPIOH;
+        break;
+#endif /* GPIOH */
+#ifdef GPIOI
+    case 'I':
+        *port = GPIOI;
+        *clk = RCU_GPIOI;
+        break;
+#endif /* GPIOI */
+#ifdef GPIOJ
+    case 'J':
+        *port = GPIOJ;
+        *clk = RCU_GPIOJ;
+        break;
+#endif /* GPIOJ */
+#ifdef GPIOK
+    case 'K':
+        *port = GPIOK;
+        *clk = RCU_GPIOK;
+        break;
+#endif /* GPIOK */
+    default:
+        return -RT_ERROR;
+    }
+
+    int pin_num = atoi(pin_name + 2);
+    if (pin_num < 0 || pin_num > 15)
+    {
+        return -RT_ERROR;
+    }
+    *pin = GPIO_PIN_0 << pin_num;
+
+    return 0;
+}
+
+int pin_alternate_config(const char *alternate, uint32_t *af)
+{
+    if (alternate == NULL || af == NULL)
+    {
+        return -RT_ERROR;
+    }
+
+    if (alternate[0] != 'A' || alternate[1] != 'F')
+    {
+        return -RT_ERROR;
+    }
+
+    int af_num = atoi(alternate + 2);
+    if (af_num < 0 || af_num > 15)
+    {
+        return -RT_ERROR;
+    }
+
+    switch (af_num)
+    {
+#ifdef GPIO_AF_0
+        case 0: *af = GPIO_AF_0; break;
+#endif /* GPIO_AF_0 */
+#ifdef GPIO_AF_1
+        case 1: *af = GPIO_AF_1; break;
+#endif /* GPIO_AF_1 */
+#ifdef GPIO_AF_2
+        case 2: *af = GPIO_AF_2; break;
+#endif /* GPIO_AF_2 */
+#ifdef GPIO_AF_3
+        case 3: *af = GPIO_AF_3; break;
+#endif /* GPIO_AF_3 */
+#ifdef GPIO_AF_4
+        case 4: *af = GPIO_AF_4; break;
+#endif /* GPIO_AF_4 */
+#ifdef GPIO_AF_5
+        case 5: *af = GPIO_AF_5; break;
+#endif /* GPIO_AF_5 */
+#ifdef GPIO_AF_6
+        case 6: *af = GPIO_AF_6; break;
+#endif /* GPIO_AF_6 */
+#ifdef GPIO_AF_7
+        case 7: *af = GPIO_AF_7; break;
+#endif /* GPIO_AF_7 */
+#ifdef GPIO_AF_8
+        case 8: *af = GPIO_AF_8; break;
+#endif /* GPIO_AF_8 */
+#ifdef GPIO_AF_9
+        case 9: *af = GPIO_AF_9; break;
+#endif /* GPIO_AF_9 */
+#ifdef GPIO_AF_10
+        case 10: *af = GPIO_AF_10; break;
+#endif /* GPIO_AF_10 */
+#ifdef GPIO_AF_11
+        case 11: *af = GPIO_AF_11; break;
+#endif /* GPIO_AF_11 */
+#ifdef GPIO_AF_12
+        case 12: *af = GPIO_AF_12; break;
+#endif /* GPIO_AF_12 */
+#ifdef GPIO_AF_13
+        case 13: *af = GPIO_AF_13; break;
+#endif /* GPIO_AF_13 */
+#ifdef GPIO_AF_14
+        case 14: *af = GPIO_AF_14; break;
+#endif /* GPIO_AF_14 */
+#ifdef GPIO_AF_15
+        case 15: *af = GPIO_AF_15; break;
+#endif /* GPIO_AF_15 */
+        default: return -1;
+    }
+
+    return 0;
+}
+
 /**
   * @brief  set pin mode
   * @param  dev, pin, mode
@@ -279,8 +446,8 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
     const struct pin_index *index = RT_NULL;
     rt_uint32_t pin_mode = 0;
 
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
-      rt_uint32_t pin_pupd = 0, pin_odpp = 0;
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+    rt_uint32_t pin_pupd = 0, pin_odpp = 0;
 #endif
 
     index = get_pin(pin);
@@ -291,17 +458,17 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 
     /* GPIO Periph clock enable */
     rcu_periph_clock_enable(index->clk);
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
-        pin_mode = GPIO_MODE_OUTPUT;
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+    pin_mode = GPIO_MODE_OUTPUT;
 #else
     pin_mode = GPIO_MODE_OUT_PP;
 #endif
 
-    switch(mode)
+    switch (mode)
     {
     case PIN_MODE_OUTPUT:
         /* output setting */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         pin_mode = GPIO_MODE_OUTPUT;
         pin_pupd = GPIO_PUPD_NONE;
         pin_odpp = GPIO_OTYPE_PP;
@@ -311,7 +478,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
         break;
     case PIN_MODE_OUTPUT_OD:
         /* output setting: od. */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         pin_mode = GPIO_MODE_OUTPUT;
         pin_pupd = GPIO_PUPD_NONE;
         pin_odpp = GPIO_OTYPE_OD;
@@ -321,7 +488,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
         break;
     case PIN_MODE_INPUT:
         /* input setting: not pull. */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         pin_mode = GPIO_MODE_INPUT;
         pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN;
 #else
@@ -330,7 +497,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
         break;
     case PIN_MODE_INPUT_PULLUP:
         /* input setting: pull up. */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         pin_mode = GPIO_MODE_INPUT;
         pin_pupd = GPIO_PUPD_PULLUP;
 #else
@@ -339,7 +506,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
         break;
     case PIN_MODE_INPUT_PULLDOWN:
         /* input setting: pull down. */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         pin_mode = GPIO_MODE_INPUT;
         pin_pupd = GPIO_PUPD_PULLDOWN;
 #else
@@ -347,23 +514,23 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 #endif
         break;
     default:
-            break;
+        break;
     }
 
 #if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
     gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin);
-    if(pin_mode == GPIO_MODE_OUTPUT)
+    if (pin_mode == GPIO_MODE_OUTPUT)
     {
         gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin);
     }
-#elif defined SOC_SERIES_GD32H7xx
+#elif defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E
     gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin);
-    if(pin_mode == GPIO_MODE_OUTPUT)
+    if (pin_mode == GPIO_MODE_OUTPUT)
     {
         gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_60MHZ, index->pin);
     }
 #else
-        gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
+    gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
 #endif
 }
 
@@ -444,7 +611,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
   * @retval None
   */
 static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
-                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -562,21 +729,21 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
 
         switch (pin_irq_hdr_tab[hdr_index].mode)
         {
-            case PIN_IRQ_MODE_RISING:
-                trigger_mode = EXTI_TRIG_RISING;
-                break;
-            case PIN_IRQ_MODE_FALLING:
-                trigger_mode = EXTI_TRIG_FALLING;
-                break;
-            case PIN_IRQ_MODE_RISING_FALLING:
-                trigger_mode = EXTI_TRIG_BOTH;
-                break;
-            default:
-                rt_hw_interrupt_enable(level);
-                return -RT_EINVAL;
+        case PIN_IRQ_MODE_RISING:
+            trigger_mode = EXTI_TRIG_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            trigger_mode = EXTI_TRIG_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            trigger_mode = EXTI_TRIG_BOTH;
+            break;
+        default:
+            rt_hw_interrupt_enable(level);
+            return -RT_EINVAL;
         }
 
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx
         rcu_periph_clock_enable(RCU_SYSCFG);
 #elif defined SOC_SERIES_GD32E23x
         rcu_periph_clock_enable(RCU_CFGCMP);
@@ -591,15 +758,15 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
         nvic_irq_enable(irqmap->irqno, 5U, 0U);
 #endif
         /* connect EXTI line to  GPIO pin */
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
         syscfg_exti_line_config(index->port_src, index->pin_src);
 #else
         gpio_exti_source_select(index->port_src, index->pin_src);
 #endif
 
         /* configure EXTI line */
-        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
-        exti_interrupt_flag_clear((exti_line_enum)(index->pin));
+        exti_init((exti_line_enum)(index->exit_line), EXTI_INTERRUPT, trigger_mode);
+        exti_interrupt_flag_clear((exti_line_enum)(index->exit_line));
 
         rt_hw_interrupt_enable(level);
     }
@@ -620,13 +787,12 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
     return RT_EOK;
 }
 
-const static struct rt_pin_ops gd32_pin_ops =
-{
+const static struct rt_pin_ops gd32_pin_ops = {
     .pin_mode = gd32_pin_mode,
     .pin_write = gd32_pin_write,
     .pin_read = gd32_pin_read,
     .pin_attach_irq = gd32_pin_attach_irq,
-    .pin_detach_irq= gd32_pin_detach_irq,
+    .pin_detach_irq = gd32_pin_detach_irq,
     .pin_irq_enable = gd32_pin_irq_enable,
     RT_NULL,
 };
@@ -651,10 +817,16 @@ rt_inline void pin_irq_hdr(int irqno)
   */
 void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
 {
-    if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
+#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
+    exti_line_enum pin_exti_line = exti_line;
+#else
+    exti_line_enum pin_exti_line = 1 << exti_line;
+#endif
+
+    if (RESET != exti_interrupt_flag_get(pin_exti_line))
     {
         pin_irq_hdr(exti_line);
-        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
+        exti_interrupt_flag_clear(pin_exti_line);
     }
 }
 
diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h
index 7e31b6c72d..a79efc7d9c 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h
@@ -29,6 +29,8 @@ extern "C" {
 #include "gd32f4xx_gpio.h"
 #elif defined SOC_SERIES_GD32H7xx
 #include "gd32h7xx_gpio.h"
+#elif defined SOC_SERIES_GD32H75e
+#include "gd32h75e_gpio.h"
 #elif defined SOC_SERIES_GD32E50x
 #include "gd32e50x_gpio.h"
 #elif defined SOC_SERIES_GD32F5xx
@@ -39,11 +41,12 @@ extern "C" {
 
 #define __GD32_PORT(port)  GPIO##port
 
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32H7xx
 #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port,      \
                                     GPIO##port, GPIO_PIN_##pin, \
                                     EXTI_SOURCE_GPIO##port,     \
-                                    EXTI_SOURCE_PIN##pin}
+                                    EXTI_SOURCE_PIN##pin,       \
+                                    EXTI_##pin}
 #else
 #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port,        \
                                     GPIO##port, GPIO_PIN_##pin,   \
@@ -70,6 +73,7 @@ struct pin_index
     rt_uint32_t pin;
     rt_uint8_t port_src;
     rt_uint8_t pin_src;
+    rt_uint32_t exit_line;
 };
 
 struct pin_irq_map
@@ -78,6 +82,9 @@ struct pin_irq_map
     IRQn_Type irqno;
 };
 
+int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk);
+int pin_alternate_config(const char *alternate, uint32_t *af);
+
 #ifdef __cplusplus
 }
 #endif