diff options
| author | Meco Jianting Man <[email protected]> | 2021-03-31 14:44:02 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-03-31 14:44:02 +0800 |
| commit | ebe9d15d6f3760455e479546c829b7a4e25cddba (patch) | |
| tree | a082cb39a09e0d26e97b07edc1cb5170f64a7bdb | |
| parent | 1ba020f3c89fbf2ac2a5b58424852e501fd59a91 (diff) | |
| parent | a225ca8014aae63f2d6ef46811fe8d689981e54a (diff) | |
Merge pull request #32 from RT-Thread/master
pr
580 files changed, 25176 insertions, 26453 deletions
diff --git a/bsp/allwinner_tina/applications/main.c b/bsp/allwinner_tina/applications/main.c index 7aaf1f8db3..e974c71ec2 100644 --- a/bsp/allwinner_tina/applications/main.c +++ b/bsp/allwinner_tina/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/board.c b/bsp/allwinner_tina/drivers/board.c index e3b54b3536..c9be412067 100644 --- a/bsp/allwinner_tina/drivers/board.c +++ b/bsp/allwinner_tina/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/board.h b/bsp/allwinner_tina/drivers/board.h index 11c6a9a15f..7b05b21c66 100644 --- a/bsp/allwinner_tina/drivers/board.h +++ b/bsp/allwinner_tina/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/drv_clock.c b/bsp/allwinner_tina/drivers/drv_clock.c index b55cd6af4c..9fec431f4b 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.c +++ b/bsp/allwinner_tina/drivers/drv_clock.c @@ -1,21 +1,7 @@ /* - * File : drv_clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -541,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) *mmc_clk &= ~(0x1 << 31); return RT_EOK; } - + if (hz <= 24000000) { pll = (0x0 << 24); @@ -593,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) oclk_dly = 1; sclk_dly = 4; } - + *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \ (n << 16) | (oclk_dly << 8) | (div - 1); diff --git a/bsp/allwinner_tina/drivers/drv_clock.h b/bsp/allwinner_tina/drivers/drv_clock.h index c1cb87af0a..1623791672 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.h +++ b/bsp/allwinner_tina/drivers/drv_clock.h @@ -1,21 +1,7 @@ /* - * File : drv_clock.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -252,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate); rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate); rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz); -#endif
\ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/drv_gpio.c b/bsp/allwinner_tina/drivers/drv_gpio.c index 999ab473a0..099ea7621d 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.c +++ b/bsp/allwinner_tina/drivers/drv_gpio.c @@ -1,21 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/drv_gpio.h b/bsp/allwinner_tina/drivers/drv_gpio.h index 35d368f1c8..74dd5a9be0 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.h +++ b/bsp/allwinner_tina/drivers/drv_gpio.h @@ -1,21 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -241,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler); void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg); int rt_hw_gpio_init(void); -#endif /* __DRV_GPIO_H__ */
\ No newline at end of file +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/allwinner_tina/drivers/drv_sdio.c b/bsp/allwinner_tina/drivers/drv_sdio.c index 11b5a63d02..f19cd60d5c 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.c +++ b/bsp/allwinner_tina/drivers/drv_sdio.c @@ -1,21 +1,7 @@ /* - * File : drv_sdio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,10 +20,10 @@ #define DBG_TAG "MMC" -// #define DBG_LVL DBG_LOG -// #define DBG_LVL DBG_INFO +// #define DBG_LVL DBG_LOG +// #define DBG_LVL DBG_INFO #define DBG_LVL DBG_WARNING -// #define DBG_LVL DBG_ERROR +// #define DBG_LVL DBG_ERROR #include <rtdbg.h> #ifdef RT_USING_SDIO @@ -47,12 +33,12 @@ struct mmc_xfe_des { rt_uint32_t size; /* block size */ - rt_uint32_t num; /* block num */ - rt_uint8_t *buff; /* buff addr */ - rt_uint32_t flag; /* write or read or stream */ -#define MMC_DATA_WRITE (1 << 0) -#define MMC_DATA_READ (1 << 1) -#define MMC_DATA_STREAM (1 << 2) + rt_uint32_t num; /* block num */ + rt_uint8_t *buff; /* buff addr */ + rt_uint32_t flag; /* write or read or stream */ +#define MMC_DATA_WRITE (1 << 0) +#define MMC_DATA_READ (1 << 1) +#define MMC_DATA_STREAM (1 << 2) }; struct mmc_flag @@ -71,7 +57,7 @@ struct sdio_drv tina_mmc_t mmc_des; rt_uint8_t *mmc_buf; rt_uint8_t usedma; - + }; #ifdef CONFIG_MMC_USE_DMA @@ -136,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc) mmc->risr_reg = mmc->risr_reg; return RT_EOK; } - + static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) { ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32) @@ -145,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) unsigned length = xfe->size * xfe->num; unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT; unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1); - + if (remain) { buff_frag_num ++; @@ -156,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } memset(pdes, 0, sizeof(pdes)); mmu_clean_dcache((rt_uint32_t)(xfe->buff), length); - for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) + for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) { // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1)); pdes[des_idx].des_chain = 1; @@ -182,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) pdes[des_idx].last_des = 1; pdes[des_idx].end_of_ring = 1; pdes[des_idx].buf_addr_ptr2 = 0; - } - else + } + else { pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1]; } @@ -217,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */ rval = mmc->idie_reg & (~3); if (xfe->flag == MMC_DATA_WRITE) - rval |= (1 << 0); + rval |= (1 << 0); else rval |= (1 << 1); mmc->idie_reg = rval; @@ -236,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) if (xfe->flag == MMC_DATA_WRITE) { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 3))); @@ -251,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } else { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 2))); @@ -290,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) { mmc_set_clk(SDMMC1, clk); } - + /* Re-enable card clock */ rval = mmc->ckcr_reg; rval |= (0x1 << 16); //(3 << 16); @@ -383,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) cmdval |= (1 << 7); if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4)) cmdval |= (1 << 8); - + if (data) { cmdval |= (1 << 9) | (1 << 13); @@ -606,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r memset(&sdio->flag, 0, sizeof(struct mmc_flag)); mmc_send_cmd(host, req->cmd); - + return; } diff --git a/bsp/allwinner_tina/drivers/drv_sdio.h b/bsp/allwinner_tina/drivers/drv_sdio.h index 742d5362e1..ef7a7c4108 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.h +++ b/bsp/allwinner_tina/drivers/drv_sdio.h @@ -1,21 +1,7 @@ /* - * File : drv_sdio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -133,8 +119,8 @@ REG[31] : Load cmd #define SDXC_UPDATE_CLOCK_CMD BIT(21) #define SDXC_LOAD_CMD BIT(31) -/* - SD status reg +/* + SD status reg REG[0] : FIFO_RX_LEVEL REG[1] : FIFO_TX_LEVEL REG[2] : FIFO_EMPTY @@ -143,7 +129,7 @@ REG[4-7] : FSM_STA REG[8] : CARD_PRESENT REG[9] : CARD_BUSY REG[10] : FSM_BUSY -REG[11-16]: RESP_IDX +REG[11-16]: RESP_IDX REG[17-21]: FIFO_LEVEL REG[31] : DMA_REQ */ diff --git a/bsp/allwinner_tina/drivers/drv_uart.c b/bsp/allwinner_tina/drivers/drv_uart.c index ede0eee4e4..a2889c598f 100644 --- a/bsp/allwinner_tina/drivers/drv_uart.c +++ b/bsp/allwinner_tina/drivers/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -324,4 +310,4 @@ void uart_irq_handler(int irqno, void *param) } -#endif
\ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/drv_uart.h b/bsp/allwinner_tina/drivers/drv_uart.h index 25cb271c6e..d7c923d373 100644 --- a/bsp/allwinner_tina/drivers/drv_uart.h +++ b/bsp/allwinner_tina/drivers/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi.c b/bsp/allwinner_tina/drivers/spi/drv_spi.c index d57cc15d7c..cd1f2aa383 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi.c @@ -1,21 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi.h b/bsp/allwinner_tina/drivers/spi/drv_spi.h index e9b9981542..1384663774 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi.h +++ b/bsp/allwinner_tina/drivers/spi/drv_spi.h @@ -1,21 +1,7 @@ /* - * File : drv_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c index 7aecc5411d..5e4edc9c6b 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c @@ -1,21 +1,7 @@ /* - * File : drv_spi_flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -65,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init); #endif -#endif
\ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/libcpu/cpu.c b/bsp/allwinner_tina/libcpu/cpu.c index 23953dea42..19baa4d9fe 100644 --- a/bsp/allwinner_tina/libcpu/cpu.c +++ b/bsp/allwinner_tina/libcpu/cpu.c @@ -1,21 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/cpuport.c b/bsp/allwinner_tina/libcpu/cpuport.c index 5def9905f8..94f2baf415 100644 --- a/bsp/allwinner_tina/libcpu/cpuport.c +++ b/bsp/allwinner_tina/libcpu/cpuport.c @@ -1,21 +1,7 @@ /* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/interrupt.c b/bsp/allwinner_tina/libcpu/interrupt.c index ccf19b0114..7c4e5cda1b 100644 --- a/bsp/allwinner_tina/libcpu/interrupt.c +++ b/bsp/allwinner_tina/libcpu/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/interrupt.h b/bsp/allwinner_tina/libcpu/interrupt.h index 2790d05ec5..bdc0d33c39 100644 --- a/bsp/allwinner_tina/libcpu/interrupt.h +++ b/bsp/allwinner_tina/libcpu/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017-2021, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/mmu.c b/bsp/allwinner_tina/libcpu/mmu.c index 177668a23b..a30f613ca9 100644 --- a/bsp/allwinner_tina/libcpu/mmu.c +++ b/bsp/allwinner_tina/libcpu/mmu.c @@ -1,21 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/mmu.h b/bsp/allwinner_tina/libcpu/mmu.h index b73f59c288..63853e6d34 100644 --- a/bsp/allwinner_tina/libcpu/mmu.h +++ b/bsp/allwinner_tina/libcpu/mmu.h @@ -1,21 +1,7 @@ /* - * File : mmu.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/rt_low_level_init.c b/bsp/allwinner_tina/libcpu/rt_low_level_init.c index 807b9b203d..eb576979c4 100644 --- a/bsp/allwinner_tina/libcpu/rt_low_level_init.c +++ b/bsp/allwinner_tina/libcpu/rt_low_level_init.c @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/stack.c b/bsp/allwinner_tina/libcpu/stack.c index 8f4c218ee1..69e50a9b47 100644 --- a/bsp/allwinner_tina/libcpu/stack.c +++ b/bsp/allwinner_tina/libcpu/stack.c @@ -1,21 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/trap.c b/bsp/allwinner_tina/libcpu/trap.c index 84bb3e7f8a..daf3501c68 100644 --- a/bsp/allwinner_tina/libcpu/trap.c +++ b/bsp/allwinner_tina/libcpu/trap.c @@ -1,21 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/applications/main.c b/bsp/amebaz/applications/main.c index 381b026867..5cbf749d76 100644 --- a/bsp/amebaz/applications/main.c +++ b/bsp/amebaz/applications/main.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/applications/smartconfig_app.c b/bsp/amebaz/applications/smartconfig_app.c index 582bbf5d98..e91f940f1b 100644 --- a/bsp/amebaz/applications/smartconfig_app.c +++ b/bsp/amebaz/applications/smartconfig_app.c @@ -1,21 +1,7 @@ /* - * File : smartconfig_demo.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/board.c b/bsp/amebaz/drivers/board.c index ffdc9fc680..7631bd13d6 100644 --- a/bsp/amebaz/drivers/board.c +++ b/bsp/amebaz/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -44,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...) * length. */ length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); if (length > RT_CONSOLEBUF_SIZE - 1) - length = RT_CONSOLEBUF_SIZE - 1; + length = RT_CONSOLEBUF_SIZE - 1; rt_kprintf("%s", rt_log_buf); va_end(args); } @@ -89,11 +85,11 @@ void rt_hw_board_init(void) #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_hw_uart_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); diff --git a/bsp/amebaz/drivers/board.h b/bsp/amebaz/drivers/board.h index 3baf67a4d5..5c6b8104ed 100644 --- a/bsp/amebaz/drivers/board.h +++ b/bsp/amebaz/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/drv_uart.c b/bsp/amebaz/drivers/drv_uart.c index 1bf659e79f..008fa3bda5 100644 --- a/bsp/amebaz/drivers/drv_uart.c +++ b/bsp/amebaz/drivers/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -125,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial) { struct device_uart* uart = serial->parent.user_data; - if(!serial_readable(&uart->serial)) + if(!serial_readable(&uart->serial)) return -1; /* Receive Data Available */ @@ -140,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui static void ameba_uart_irq(uint32_t id, SerialIrq event) { struct rt_serial_device *serial = (struct rt_serial_device *)id; - if(event == RxIrq) + if(event == RxIrq) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - } - else if(event == TxIrq) + } + else if(event == TxIrq) { - } + } } static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg); @@ -155,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c); static int dbg_getc(struct rt_serial_device *serial); static struct rt_serial_device ameba_dbg_serial; -const struct rt_uart_ops _ambed_dbg_ops = +const struct rt_uart_ops _ambed_dbg_ops = { dbg_configure, dbg_control, @@ -177,7 +163,7 @@ void dbg_uart_irq_handler(void * data) DiagSetIsrEnReg(0); rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND); - + DiagSetIsrEnReg(IrqEn); } @@ -192,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg) case RT_DEVICE_CTRL_SET_INT: /* install interrupt */ - DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); + DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); /* Enable the UART Interrupt */ - NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ + NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ break; } @@ -214,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial) if(!UART_Readable(UART2_DEV)) return -1; - + c = DiagGetChar(_FALSE); return c; } - + /* * UART Initiation */ @@ -231,7 +217,7 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART0 { struct device_uart *uart; - + serial = &serial0; uart = &uart0; @@ -256,7 +242,7 @@ int rt_hw_uart_init(void) serial->ops = &_ambed_dbg_ops; serial->config = config; - + rt_hw_serial_register(serial, RT_CONSOLE_DEVICE_NAME, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, diff --git a/bsp/amebaz/drivers/drv_uart.h b/bsp/amebaz/drivers/drv_uart.h index a4d326da58..e91cc568b0 100644 --- a/bsp/amebaz/drivers/drv_uart.h +++ b/bsp/amebaz/drivers/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.c b/bsp/amebaz/drivers/wlan/drv_wifi.c index 12865bfc3b..7d8cade15e 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.c +++ b/bsp/amebaz/drivers/wlan/drv_wifi.c @@ -1,21 +1,7 @@ /* - * File : drv_wifi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -115,7 +101,7 @@ void netif_pre_sleep_processing(void) } unsigned char *rltk_wlan_get_ip(int idx) -{ +{ struct ameba_wifi *wifi; wifi = rthw_wifi_get_dev(idx); @@ -130,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx) int netif_is_valid_IP(int idx, unsigned char *ip_dest) { - LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, + LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]); return 1; } @@ -376,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str ssid = &sta_info->ssid.val[0]; if (sta_info->key.len > 0) key = &sta_info->key.val[0]; - LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", + LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5], - ssid, + ssid, sta_info->ssid.len, key, sta_info->key.len @@ -608,7 +594,7 @@ exit: return RT_EOK; } -static const struct rt_wlan_dev_ops ops = +static const struct rt_wlan_dev_ops ops = { .wlan_init = rthw_wlan_init , .wlan_mode = rthw_wlan_mode , diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.h b/bsp/amebaz/drivers/wlan/drv_wifi.h index b92658d470..2ca7c799c8 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.h +++ b/bsp/amebaz/drivers/wlan/drv_wifi.h @@ -1,27 +1,13 @@ /* - * File : drv_wifi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-5-30 Bernard the first version */ - + #ifndef __DRV_WIFI_H__ #define __DRV_WIFI_H__ diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.c b/bsp/amebaz/drivers/wlan/drv_wlan.c index c414470633..1eedea54c0 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.c +++ b/bsp/amebaz/drivers/wlan/drv_wlan.c @@ -1,21 +1,7 @@ /* - * File : drv_wlan.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -151,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel) return -1; } - while(1) + while(1) { char essid[33]; if(wext_get_ssid(name, (unsigned char *) essid) > 0) { - if(strcmp((const char *) essid, (const char *)ssid) == 0) + if(strcmp((const char *) essid, (const char *)ssid) == 0) { rt_kprintf("%s started\n", ssid); break; } } - if(timeout == 0) + if(timeout == 0) { - rt_kprintf("Start AP timeout\n"); + rt_kprintf("Start AP timeout\n"); return -1; } rt_thread_delay(1 * RT_TICK_PER_SECOND); @@ -183,7 +169,7 @@ static int rthw_wifi_disconnect(char *name) if (name == RT_NULL) return -1; - if (wext_get_ssid(name, (unsigned char *) essid) < 0) + if (wext_get_ssid(name, (unsigned char *) essid) < 0) { rt_kprintf("\nWIFI disconnected!\n"); return -1; @@ -203,7 +189,7 @@ static int rthw_wifi_disconnect(char *name) break; } - if(timeout == 0) + if(timeout == 0) { rt_kprintf("ERROR: Deassoc timeout!\n"); return -1; @@ -259,7 +245,7 @@ int rthw_wifi_ap_disconnect(void) int rthw_wifi_rssi_get(void) { - int rssi = 0; + int rssi = 0; wifi_get_rssi(&rssi); return rssi; } diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.h b/bsp/amebaz/drivers/wlan/drv_wlan.h index 03a8db01e8..ad300b18eb 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.h +++ b/bsp/amebaz/drivers/wlan/drv_wlan.h @@ -1,21 +1,7 @@ /* - * File : drv_wlan.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,14 +11,14 @@ #ifndef __DRV_WLAN_H__ #define __DRV_WLAN_H__ -typedef enum +typedef enum { - RTHW_MODE_NONE = 0, - RTHW_MODE_STA, - RTHW_MODE_AP, - RTHW_MODE_STA_AP, - RTHW_MODE_PROMISC, - RTHW_MODE_P2P + RTHW_MODE_NONE = 0, + RTHW_MODE_STA, + RTHW_MODE_AP, + RTHW_MODE_STA_AP, + RTHW_MODE_PROMISC, + RTHW_MODE_P2P }rthw_mode_t; #define SHARED_ENABLED 0x00008000 @@ -66,7 +52,7 @@ typedef enum { typedef enum { RTHW_WIFI_EVENT_CONNECT = 0, RTHW_WIFI_EVENT_DISCONNECT = 1, - RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, + RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3, RTHW_WIFI_EVENT_SCAN_DONE = 4, RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5, diff --git a/bsp/apollo2/applications/main.c b/bsp/apollo2/applications/main.c index b058fc7711..4761cae664 100644 --- a/bsp/apollo2/applications/main.c +++ b/bsp/apollo2/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/adc.c b/bsp/apollo2/board/adc.c index a0044bcc37..26b926a209 100644 --- a/bsp/apollo2/board/adc.c +++ b/bsp/apollo2/board/adc.c @@ -1,21 +1,7 @@ /* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,15 +18,15 @@ struct rt_messagequeue adcbat_mq; #define BATTERY_GPIO 35 /* Battery */ -#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 -#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC�ɼ�ͨ�� */ -#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC�ɼ�ͨ���� */ +#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 +#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */ +#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */ -#define ADC_CTIMER_NUM 3 /* ADCʹ�ö�ʱ�� */ +#define ADC_CTIMER_NUM 3 /* ADC使用定时器 */ #define ADC_CTIMER_COUNT (2048/512 - 1) -#define ADC_CHANNEL_NUM 1 /* ADC�ɼ�ͨ������ */ -#define ADC_SAMPLE_NUM 8 /* ADC�������� */ +#define ADC_CHANNEL_NUM 1 /* ADC采集通道个数 */ +#define ADC_SAMPLE_NUM 8 /* ADC采样个数 */ rt_uint8_t bat_adc_cnt = 0; static rt_uint8_t am_adcbat_buffer_pool[256]; @@ -52,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz if (channel == BATTERY_ADC_CHANNELNUM) { - /* wait adc message forever */ + /* wait adc message forever */ rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); } diff --git a/bsp/apollo2/board/adc.h b/bsp/apollo2/board/adc.h index 4e4396bae3..552b704ab8 100644 --- a/bsp/apollo2/board/adc.h +++ b/bsp/apollo2/board/adc.h @@ -1,21 +1,7 @@ /* - * File : adc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/board.c b/bsp/apollo2/board/board.c index 23bc332af4..907455a998 100644 --- a/bsp/apollo2/board/board.c +++ b/bsp/apollo2/board/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/board.h b/bsp/apollo2/board/board.h index 67dfdd5e39..ef21bdb05f 100644 --- a/bsp/apollo2/board/board.h +++ b/bsp/apollo2/board/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/flash.c b/bsp/apollo2/board/flash.c index ae224e85a1..2d28920daf 100644 --- a/bsp/apollo2/board/flash.c +++ b/bsp/apollo2/board/flash.c @@ -1,21 +1,7 @@ /* - * File : flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -77,7 +63,7 @@ static rt_err_t rt_flash_control(rt_device_t dev, int cmd, void *args) ui32CurrentPage = AM_HAL_FLASH_ADDR2PAGE(erase->addrstart); ui32CurrentBlock = AM_HAL_FLASH_ADDR2INST(erase->addrstart); - am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); //�������������� + am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); //单扇区擦除命令 erase->addrstart += 8192; } } diff --git a/bsp/apollo2/board/flash.h b/bsp/apollo2/board/flash.h index c9c8f9492c..b628983ce3 100644 --- a/bsp/apollo2/board/flash.h +++ b/bsp/apollo2/board/flash.h @@ -1,21 +1,7 @@ /* - * File : flash.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index c985e0f2a7..edfaef1431 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -1,21 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -70,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) else if (value == PIN_HIGH) { am_hal_gpio_out_bit_set(pin); - } + } } int am_pin_read(rt_device_t dev, rt_base_t pin) diff --git a/bsp/apollo2/board/gpio.h b/bsp/apollo2/board/gpio.h index 1ea3c42013..495fde6f6e 100644 --- a/bsp/apollo2/board/gpio.h +++ b/bsp/apollo2/board/gpio.h @@ -1,27 +1,13 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-09-16 Haley the first version */ - + #ifndef __GPIO_H #define __GPIO_H diff --git a/bsp/apollo2/board/i2c.c b/bsp/apollo2/board/i2c.c index 6d1bcdc0c0..0a1311d7e6 100644 --- a/bsp/apollo2/board/i2c.c +++ b/bsp/apollo2/board/i2c.c @@ -1,21 +1,7 @@ /* - * File :_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -133,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops = }; #ifdef RT_USING_I2C0 -static struct am_i2c_bus am_i2c_bus_0 = +static struct am_i2c_bus am_i2c_bus_0 = { {0}, AM_I2C0_IOM_INST @@ -141,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 = #endif #ifdef RT_USING_I2C1 -static struct am_i2c_bus am_i2c_bus_1 = +static struct am_i2c_bus am_i2c_bus_1 = { {1}, AM_I2C1_IOM_INST @@ -149,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 = #endif #ifdef RT_USING_I2C2 -static struct am_i2c_bus am_i2c_bus_2 = +static struct am_i2c_bus am_i2c_bus_2 = { {2}, AM_I2C2_IOM_INST @@ -157,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 = #endif #ifdef RT_USING_I2C3 -static struct am_i2c_bus am_i2c_bus_3 = +static struct am_i2c_bus am_i2c_bus_3 = { {3}, AM_I2C3_IOM_INST @@ -165,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 = #endif #ifdef RT_USING_I2C4 -static struct am_i2c_bus am_i2c_bus_4 = +static struct am_i2c_bus am_i2c_bus_4 = { {4}, AM_I2C4_IOM_INST diff --git a/bsp/apollo2/board/i2c.h b/bsp/apollo2/board/i2c.h index 004d5eb3c1..b0a24b51cd 100644 --- a/bsp/apollo2/board/i2c.h +++ b/bsp/apollo2/board/i2c.h @@ -1,21 +1,7 @@ /* - * File : i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/led.c b/bsp/apollo2/board/led.c index d8eb2fb753..5364667679 100644 --- a/bsp/apollo2/board/led.c +++ b/bsp/apollo2/board/led.c @@ -1,21 +1,7 @@ /* - * File :_led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/led.h b/bsp/apollo2/board/led.h index c6f6bd8728..76832e32b9 100644 --- a/bsp/apollo2/board/led.h +++ b/bsp/apollo2/board/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pdm.c b/bsp/apollo2/board/pdm.c index 3eb46f7411..f1b719c6d1 100644 --- a/bsp/apollo2/board/pdm.c +++ b/bsp/apollo2/board/pdm.c @@ -1,21 +1,7 @@ /* - * File :_pdm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -66,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) { rt_uint8_t pdm_rbufftemp[340]; - /* wait pdm message forever */ + /* wait pdm message forever */ rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); /* copy the data */ diff --git a/bsp/apollo2/board/pdm.h b/bsp/apollo2/board/pdm.h index 43ed075da8..2975c8aad1 100644 --- a/bsp/apollo2/board/pdm.h +++ b/bsp/apollo2/board/pdm.h @@ -1,21 +1,7 @@ /* - * File : pdm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pwm.c b/bsp/apollo2/board/pwm.c index 7591291eac..8b23a8c290 100644 --- a/bsp/apollo2/board/pwm.c +++ b/bsp/apollo2/board/pwm.c @@ -1,21 +1,7 @@ /* - * File :_pwm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pwm.h b/bsp/apollo2/board/pwm.h index 53a6571264..973848c6f6 100644 --- a/bsp/apollo2/board/pwm.h +++ b/bsp/apollo2/board/pwm.h @@ -1,21 +1,7 @@ /* - * File : pwm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index dbae7cf3c1..5c8fbb13fe 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -1,21 +1,7 @@ /* - * File :_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -116,7 +102,7 @@ int rt_hw_rtc_init(void) /* Select LFRC for RTC clock source */ am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); #endif - + #if RTC_CLK_SRC == XT /* Enable the XT for the RTC */ am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); @@ -129,12 +115,12 @@ int rt_hw_rtc_init(void) am_hal_rtc_osc_enable(); /* register rtc device */ - rtc.type = RT_Device_Class_RTC; - rtc.init = RT_NULL; - rtc.open = rt_rtc_open; - rtc.close = RT_NULL; - rtc.read = rt_rtc_read; - rtc.write = RT_NULL; + rtc.type = RT_Device_Class_RTC; + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; rtc.control = rt_rtc_control; /* no private */ diff --git a/bsp/apollo2/board/rtc.h b/bsp/apollo2/board/rtc.h index 83087bc47e..a4a7fbd5e7 100644 --- a/bsp/apollo2/board/rtc.h +++ b/bsp/apollo2/board/rtc.h @@ -1,27 +1,13 @@ /* - * File : rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-09-14 Haley the first version */ - + #ifndef __RTC_H #define __RTC_H diff --git a/bsp/apollo2/board/smbus.c b/bsp/apollo2/board/smbus.c index ae41f9fac6..7437b68ffa 100644 --- a/bsp/apollo2/board/smbus.c +++ b/bsp/apollo2/board/smbus.c @@ -1,21 +1,7 @@ /* - * File : smbus.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -42,8 +28,8 @@ #define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ #define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ -#define ACK 0 -#define NACK 1 +#define ACK 0 +#define NACK 1 /* SCL keep time */ static void keep_delay(void) @@ -60,7 +46,7 @@ static void few_delay(void) } static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit) -{ +{ mSDA_OUT(); few_delay(); @@ -128,7 +114,7 @@ static void am_smbus_stop_bit(void) static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte) { - int i; + int i; rt_uint8_t ack_bit; rt_uint8_t bit_out; @@ -176,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u int i; am_smbus_start_bit(); /* Start condition */ - + if(am_smbus_tx_byte(SlaveAddress)) /* Send SlaveAddress and write */ return 1; diff --git a/bsp/apollo2/board/smbus.h b/bsp/apollo2/board/smbus.h index 6f518b8f9e..62f8afc1b9 100644 --- a/bsp/apollo2/board/smbus.h +++ b/bsp/apollo2/board/smbus.h @@ -1,21 +1,7 @@ /* - * File : smbus.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/spi.c b/bsp/apollo2/board/spi.c index 783f359af0..f59610975f 100644 --- a/bsp/apollo2/board/spi.c +++ b/bsp/apollo2/board/spi.c @@ -1,21 +1,7 @@ /* - * File : spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -180,7 +166,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes am_hal_gpio_out_bit_clear(am_spi_cs->chip_select); } - // ������ + // 读数据 if (recv_ptr != RT_NULL) { while (u32BytesRemaining) @@ -213,7 +199,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } } - // д���� + // 写数据 else { while (u32BytesRemaining) @@ -225,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes u32TransferSize = 64; am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); - + } else { @@ -257,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops = }; #ifdef RT_USING_SPI0 -static struct am_spi_bus am_spi_bus_0 = +static struct am_spi_bus am_spi_bus_0 = { {0}, AM_SPI0_IOM_INST diff --git a/bsp/apollo2/board/spi.h b/bsp/apollo2/board/spi.h index d88bb587e9..4c23f54621 100644 --- a/bsp/apollo2/board/spi.h +++ b/bsp/apollo2/board/spi.h @@ -1,21 +1,7 @@ /* - * File : spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -27,7 +13,7 @@ #include <rtthread.h> -/* Ƭѡ�źŽṹ���� */ +/* 片选信号结构声明 */ struct am_spi_cs { rt_uint32_t chip_select; diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c index fc3884bf2d..ec97599b80 100644 --- a/bsp/apollo2/board/uart.c +++ b/bsp/apollo2/board/uart.c @@ -1,21 +1,7 @@ /* - * File : uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -164,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf else if (cfg->stop_bits == STOP_BITS_2) uart_cfg.bTwoStopBits = true; - if (cfg->parity == PARITY_NONE) + if (cfg->parity == PARITY_NONE) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; - else if (cfg->parity == PARITY_ODD) + else if (cfg->parity == PARITY_ODD) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; - else if (cfg->parity == PARITY_EVEN) + else if (cfg->parity == PARITY_EVEN) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; diff --git a/bsp/apollo2/board/uart.h b/bsp/apollo2/board/uart.h index 8e92068d5d..d858d68b21 100644 --- a/bsp/apollo2/board/uart.h +++ b/bsp/apollo2/board/uart.h @@ -1,21 +1,7 @@ /* - * File : uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at32/Libraries/rt_drivers/drv_adc.c b/bsp/at32/Libraries/rt_drivers/drv_adc.c index 02e7b602af..25760e512b 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_adc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include <drv_log.h> struct at32_adc -{ +{ struct rt_adc_device at32_adc_device; ADC_Type *ADC_Handler; char *name; @@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann ADC_InitType ADC_InitStructure; RT_ASSERT(device != RT_NULL); at32_adc_handler = device->parent.user_data; - + at32_msp_adc_init(at32_adc_handler); - + /* ADCx configuration ------------------------------------------------------*/ ADC_StructInit(&ADC_InitStructure); ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; @@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; ADC_InitStructure.ADC_NumOfChannel = 1; ADC_Init(at32_adc_handler, &ADC_InitStructure); - - /* ADCx regular channels configuration */ - ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); - + + /* ADCx regular channels configuration */ + ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); + /* Enable ADCx */ ADC_Ctrl(at32_adc_handler, ENABLE); - - /* Enable ADCx reset calibration register */ + + /* Enable ADCx reset calibration register */ ADC_RstCalibration(at32_adc_handler); /* Check the end of ADCx reset calibration register */ while(ADC_GetResetCalibrationStatus(at32_adc_handler)); @@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha at32_adc_handler = device->parent.user_data; - /* Start ADCx Software Conversion */ + /* Start ADCx Software Conversion */ ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE); /* Wait for the ADC to convert */ diff --git a/bsp/at32/Libraries/rt_drivers/drv_adc.h b/bsp/at32/Libraries/rt_drivers/drv_adc.h index d113d1338a..0991b0fe80 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_adc.h +++ b/bsp/at32/Libraries/rt_drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,32 +19,32 @@ extern "C" { #endif #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) - + #ifndef ADC1_CONFIG #define ADC1_CONFIG \ { \ .ADC_Handler = ADC1, \ .name = "adc1", \ - } + } #endif /* ADC1_CONFIG */ - + #ifndef ADC2_CONFIG #define ADC2_CONFIG \ { \ .ADC_Handler = ADC2, \ .name = "adc2", \ - } + } #endif /* ADC2_CONFIG */ - + #ifndef ADC3_CONFIG #define ADC3_CONFIG \ { \ .ADC_Handler = ADC3, \ .name = "adc3", \ - } -#endif /* ADC3_CONFIG */ - -#endif + } +#endif /* ADC3_CONFIG */ + +#endif #ifdef __cplusplus diff --git a/bsp/at32/Libraries/rt_drivers/drv_can.c b/bsp/at32/Libraries/rt_drivers/drv_can.c index 43f5a287e3..47a4bb3667 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_can.c +++ b/bsp/at32/Libraries/rt_drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -311,8 +311,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU); can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF; - can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) | - (filter_cfg->items[i].ide << 2) | + can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF; can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF; @@ -499,7 +499,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) else pmsg->ide = RxMessage.ExtId; pmsg->rtr = RxMessage.RTR; - + return RT_EOK; } diff --git a/bsp/at32/Libraries/rt_drivers/drv_can.h b/bsp/at32/Libraries/rt_drivers/drv_can.h index d89bacda26..19afb93040 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_can.h +++ b/bsp/at32/Libraries/rt_drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { #define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ #define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ #define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ - + struct at32_baud_rate_tab { rt_uint32_t baud_rate; diff --git a/bsp/at32/Libraries/rt_drivers/drv_eth.c b/bsp/at32/Libraries/rt_drivers/drv_eth.c index 3a14d9b918..e44429e0ea 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_eth.c +++ b/bsp/at32/Libraries/rt_drivers/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,8 +28,8 @@ //#define DRV_DEBUG #define LOG_TAG "drv.emac" -#define ETH_RXBUFNB 4 -#define ETH_TXBUFNB 2 +#define ETH_RXBUFNB 4 +#define ETH_TXBUFNB 2 #define LINK_THREAD_STACK_SIZE 256 #define LINK_THREAD_PREORITY 21 @@ -131,14 +131,14 @@ void NVIC_Configuration(void) NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); /* 2 bit for pre-emption priority, 2 bits for subpriority */ - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); /* Enable the Ethernet global Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + NVIC_Init(&NVIC_InitStructure); } /** @@ -173,7 +173,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOC, &GPIO_InitStructure); - /*MII Mode GPIO configuration*/ + /*MII Mode GPIO configuration*/ #ifdef MII_MODE /**********************MII Tx Pin Define****************************/ /* @@ -193,7 +193,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOC, &GPIO_InitStructure); - /**********************MII Rx Pin Define****************************/ + /**********************MII Rx Pin Define****************************/ #if MII_RX_REMAP /*IO PIN remaped*/ /* ETH_MII_RX_DV-->PD8 @@ -208,7 +208,7 @@ void GPIO_Configuration(void) */ GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -233,11 +233,11 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOB, &GPIO_InitStructure); @@ -255,8 +255,8 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOB, &GPIO_InitStructure); - - /**********************RMII Rx Pin Define****************************/ + + /**********************RMII Rx Pin Define****************************/ #if MII_RX_REMAP /*IO PIN remaped*/ /* ETH_RMII_RX_DV-->PD8 @@ -266,7 +266,7 @@ void GPIO_Configuration(void) */ GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pins = GPIO_Pins_1; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -282,7 +282,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOC, &GPIO_InitStructure); @@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX | RCC_AHBPERIPH_ETHMACRX, ENABLE); - + /* MII/RMII Media interface selection ------------------------------------------*/ #ifdef MII_MODE /* Mode MII with AT32F407-EVAL */ GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII); @@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif - /*------------------------ DMA -----------------------------------*/ + /*------------------------ DMA -----------------------------------*/ - /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: - the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ - ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; - ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; - ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; - ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; /* Configure Ethernet, check error */ if(ETH_Init(Ð_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) { return RT_ERROR; - } + } /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ - ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE); + ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE); /* Initialize Tx Descriptors list: Chain Mode */ ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); @@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]); /* Enable ETH transmition and recetion */ - ETH_Start(); + ETH_Start(); return RT_EOK; } @@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev) { rt_uint32_t i; rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr); - + AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len); for(i=0; i<p->tot_len; i++) { diff --git a/bsp/at32/Libraries/rt_drivers/drv_eth.h b/bsp/at32/Libraries/rt_drivers/drv_eth.h index 398b4bdc0c..d5a5a05cc5 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_eth.h +++ b/bsp/at32/Libraries/rt_drivers/drv_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_flash.c b/bsp/at32/Libraries/rt_drivers/drv_flash.c index 8104f9b612..a1b381beaa 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_flash.c +++ b/bsp/at32/Libraries/rt_drivers/drv_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -160,14 +160,14 @@ int at32_flash_erase(rt_uint32_t addr, size_t size) addr += FLASH_PAGE_SIZE; } - FLASH_Lock(); - -__exit: + FLASH_Lock(); + +__exit: if(result != RT_EOK) { return result; } - + return size; } @@ -177,7 +177,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); static int fal_flash_erase(long offset, size_t size); -const struct fal_flash_dev at32_onchip_flash = +const struct fal_flash_dev at32_onchip_flash = { "onchip_flash", AT32_FLASH_START_ADRESS, diff --git a/bsp/at32/Libraries/rt_drivers/drv_flash.h b/bsp/at32/Libraries/rt_drivers/drv_flash.h index 9392ff4303..7ec0a18632 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_flash.h +++ b/bsp/at32/Libraries/rt_drivers/drv_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_gpio.c b/bsp/at32/Libraries/rt_drivers/drv_gpio.c index d6fd0594dc..bc9f6b87bb 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_gpio.c +++ b/bsp/at32/Libraries/rt_drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #ifdef RT_USING_PIN -static const struct pin_index pins[] = +static const struct pin_index pins[] = { #if defined(GPIOA) __AT32_PIN(0 , A, 0 ), @@ -414,7 +414,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin, /* Configure GPIO_InitStructure */ GPIO_StructInit(&GPIO_InitStruct); EXTI_StructInit(&EXTI_InitStruct); - GPIO_InitStruct.GPIO_Pins = irqmap->pinbit; + GPIO_InitStruct.GPIO_Pins = irqmap->pinbit; GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; EXTI_InitStruct.EXTI_Line = irqmap->pinbit; EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt; @@ -462,24 +462,24 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin, if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 )) { if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9))) - { + { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; } } else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 )) { if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15))) - { + { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; } } else { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; - } + } NVIC_Init(&NVIC_InitStruct); - rt_hw_interrupt_enable(level); + rt_hw_interrupt_enable(level); } else { diff --git a/bsp/at32/Libraries/rt_drivers/drv_gpio.h b/bsp/at32/Libraries/rt_drivers/drv_gpio.h index 63870611f5..a8f5b7474e 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_gpio.h +++ b/bsp/at32/Libraries/rt_drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c index 97788d22c9..dede483e54 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2020-03-16 Leo first version */ - + #include <board.h> #include "drv_hwtimer.h" @@ -20,35 +20,35 @@ enum { #ifdef BSP_USING_HWTMR1 TMR1_INDEX, -#endif - +#endif + #ifdef BSP_USING_HWTMR2 TMR2_INDEX, -#endif - +#endif + #ifdef BSP_USING_HWTMR3 TMR3_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR4 TMR4_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR5 TMR5_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR6 TMR6_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR7 TMR7_INDEX, -#endif +#endif #ifdef BSP_USING_HW_TMR8 TMR8_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR9 TMR9_INDEX, @@ -56,11 +56,11 @@ enum #ifdef BSP_USING_HWTMR10 TMR10_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR11 TMR11_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR12 TMR12_INDEX, @@ -68,11 +68,11 @@ enum #ifdef BSP_USING_HWTMR13 TMR13_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR14 TMR14_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR15 TMR15_INDEX, @@ -91,48 +91,48 @@ static struct at32_hwtimer at32_hwtimer_obj[] = { #ifdef BSP_USING_HWTMR1 TMR1_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR2 TMR2_CONFIG, #endif - + #ifdef BSP_USING_HWTMR3 TMR3_CONFIG, #endif - + #ifdef BSP_USING_HWTMR4 TMR4_CONFIG, #endif #ifdef BSP_USING_HWTMR5 TMR5_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR6 TMR6_CONFIG, #endif - + #ifdef BSP_USING_HWTMR7 TMR7_CONFIG, #endif - + #ifdef BSP_USING_HWTMR8 TMR8_CONFIG, #endif #ifdef BSP_USING_HWTMR9 TMR9_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR10 TMR10_CONFIG, #endif - + #ifdef BSP_USING_HWTMR11 TMR11_CONFIG, #endif - + #ifdef BSP_USING_HWTMR12 TMR12_CONFIG, #endif @@ -164,20 +164,20 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { tim = (TMR_Type *)timer->parent.user_data; tim_device = (struct at32_hwtimer *)timer; - + /* timer clock enable */ at32_msp_hwtmr_init(tim); - + /* timer init */ RCC_GetClocksFreq(&RCC_ClockStruct); /* Set timer clock is 1Mhz */ prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1; - + TMR_TMReBaseStructure.TMR_Period = 10000 - 1; TMR_TMReBaseStructure.TMR_DIV = prescaler_value; TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1; TMR_TMReBaseStructure.TMR_RepetitionCounter = 0; - + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) { TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up; @@ -186,21 +186,21 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down; } - + TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure); - + /* Enable the TMRx global Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - + TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE); TMR_ClearITPendingBit(tim, TMR_INT_Overflow); - + LOG_D("%s init success", tim_device->name); - } + } } static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) @@ -211,7 +211,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_ RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + /* set tim cnt */ TMR_SetCounter(tim, 0); /* set tim arr */ @@ -225,10 +225,10 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_ { TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive); } - + /* start timer */ TMR_Cmd(tim, ENABLE); - + return result; } @@ -239,7 +239,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer) RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + /* stop timer */ TMR_Cmd(tim, ENABLE); /* set tim cnt */ @@ -253,7 +253,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer) RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + return tim->CNT; } @@ -267,22 +267,22 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) RT_ASSERT(arg != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + switch(cmd) { case HWTIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val; - + /* set timer frequence */ freq = *((rt_uint32_t *)arg); - + /* time init */ RCC_GetClocksFreq(&RCC_ClockStruct); - + val = RCC_ClockStruct.SYSCLK_Freq / freq; - + TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate); } break; @@ -292,7 +292,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) } break; } - + return result; } @@ -311,13 +311,13 @@ void TMR2_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device); TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -329,13 +329,13 @@ void TMR3_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device); TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -347,13 +347,13 @@ void TMR4_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device); TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -365,13 +365,13 @@ void TMR5_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device); TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); diff --git a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h index 9ae4981e3f..9acfb8d468 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ extern "C" { .maxcnt = 0xFFFF, \ .cntmode = HWTIMER_CNTMODE_UP, \ } -#endif /* TIM_DEV_INFO_CONFIG */ +#endif /* TIM_DEV_INFO_CONFIG */ #ifdef BSP_USING_HWTMR2 #ifndef TMR2_CONFIG @@ -36,9 +36,9 @@ extern "C" { .tim_irqn = TMR2_GLOBAL_IRQn, \ .name = "timer2", \ } -#endif /* TMR2_CONFIG */ -#endif /* BSP_USING_HWTMR2 */ - +#endif /* TMR2_CONFIG */ +#endif /* BSP_USING_HWTMR2 */ + #ifdef BSP_USING_HWTMR3 #ifndef TMR3_CONFIG #define TMR3_CONFIG \ @@ -47,8 +47,8 @@ extern "C" { .tim_irqn = TMR3_GLOBAL_IRQn, \ .name = "timer3", \ } -#endif /* TMR3_CONFIG */ -#endif /* BSP_USING_HWTMR3 */ +#endif /* TMR3_CONFIG */ +#endif /* BSP_USING_HWTMR3 */ #ifdef BSP_USING_HWTMR4 #ifndef TMR4_CONFIG @@ -58,9 +58,9 @@ extern "C" { .tim_irqn = TMR4_GLOBAL_IRQn, \ .name = "timer4", \ } -#endif /* TMR4_CONFIG */ +#endif /* TMR4_CONFIG */ #endif /* BSP_USING_HWTMR4 */ - + #ifdef BSP_USING_HWTMR5 #ifndef TMR5_CONFIG #define TMR5_CONFIG \ @@ -69,9 +69,9 @@ extern "C" { .tim_irqn = TMR5_GLOBAL_IRQn, \ .name = "timer5", \ } -#endif /* TMR5_CONFIG */ -#endif /* BSP_USING_HWTMR5 */ - +#endif /* TMR5_CONFIG */ +#endif /* BSP_USING_HWTMR5 */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_log.h b/bsp/at32/Libraries/rt_drivers/drv_log.h index a813acb0cb..d91f70d37c 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_log.h +++ b/bsp/at32/Libraries/rt_drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_pwm.c b/bsp/at32/Libraries/rt_drivers/drv_pwm.c index 78b1b2d7a9..9a188681ed 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_pwm.c +++ b/bsp/at32/Libraries/rt_drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,52 +37,52 @@ struct at32_pwm char *name; }; -static struct at32_pwm at32_pwm_obj[] = +static struct at32_pwm at32_pwm_obj[] = { #ifdef BSP_USING_TMR1_CH1 PWM1_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH2 PWM2_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH3 PWM3_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH4 PWM4_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH1 PWM5_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH2 PWM6_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH3 PWM7_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH4 PWM8_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH1 PWM9_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH2 PWM10_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH3 PWM11_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH4 PWM12_CONFIG, #endif @@ -97,7 +97,7 @@ static struct rt_pwm_ops drv_ops = static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable) { /* Get the value of channel */ - rt_uint32_t channel = configuration->channel; + rt_uint32_t channel = configuration->channel; if (!enable) { @@ -137,7 +137,7 @@ static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *conf TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable); } } - + /* TMRx enable counter */ TMR_Cmd(TMRx, ENABLE); @@ -173,7 +173,7 @@ static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configu configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock; if(channel == 4) configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock; - + return RT_EOK; } @@ -185,15 +185,15 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu rt_uint64_t psc; /* Get the channel number */ rt_uint32_t channel = configuration->channel; - + /* Init timer pin and enable clock */ at32_msp_tmr_init(TMRx); - + /* Convert nanosecond to frequency and duty cycle. */ period = (unsigned long long)configuration->period ; psc = period / MAX_PERIOD + 1; period = period / psc; - + /* TMRe base configuration */ TMR_TimeBaseStructInit(&TMR_TMReBaseStructure); TMR_TMReBaseStructure.TMR_Period = period; @@ -204,14 +204,14 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure); pulse = (unsigned long long)configuration->pulse; - + /* PWM1 Mode configuration: Channel1 */ TMR_OCStructInit(&TMR_OCInitStructure); TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1; TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable; TMR_OCInitStructure.TMR_Pulse = pulse; TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High; - + if(channel == 1) { TMR_OC1Init(TMRx, &TMR_OCInitStructure); @@ -232,7 +232,7 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu TMR_OC4Init(TMRx, &TMR_OCInitStructure); TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable); } - + TMR_ARPreloadConfig(TMRx, ENABLE); #if defined (SOC_SERIES_AT32F415) @@ -271,7 +271,7 @@ static int rt_hw_pwm_init(void) { int i = 0; int result = RT_EOK; - + for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++) { if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK) @@ -280,9 +280,9 @@ static int rt_hw_pwm_init(void) } else { - LOG_D("%s register failed", at32_pwm_obj[i].name); - result = -RT_ERROR; - } + LOG_D("%s register failed", at32_pwm_obj[i].name); + result = -RT_ERROR; + } } return result; diff --git a/bsp/at32/Libraries/rt_drivers/drv_pwm.h b/bsp/at32/Libraries/rt_drivers/drv_pwm.h index 6cdcfc6415..720a810f79 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_pwm.h +++ b/bsp/at32/Libraries/rt_drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ extern "C" { } #endif /* PWM1_CONFIG */ #endif /* BSP_USING_TMR1_CH1 */ - + #ifdef BSP_USING_TMR1_CH2 #ifndef PWM2_CONFIG #define PWM2_CONFIG \ @@ -72,7 +72,7 @@ extern "C" { } #endif /* PWM5_CONFIG */ #endif /* BSP_USING_TMR2_CH1 */ - + #ifdef BSP_USING_TMR2_CH2 #ifndef PWM6_CONFIG #define PWM6_CONFIG \ @@ -82,8 +82,8 @@ extern "C" { .channel = 2 \ } #endif /* PWM6_CONFIG */ -#endif /* BSP_USING_TMR2_CH2 */ - +#endif /* BSP_USING_TMR2_CH2 */ + #ifdef BSP_USING_TMR2_CH3 #ifndef PWM7_CONFIG #define PWM7_CONFIG \ @@ -93,7 +93,7 @@ extern "C" { .channel = 3 \ } #endif /* PWM7_CONFIG */ -#endif /* BSP_USING_TMR2_CH3 */ +#endif /* BSP_USING_TMR2_CH3 */ #ifdef BSP_USING_TMR2_CH4 #ifndef PWM8_CONFIG @@ -115,7 +115,7 @@ extern "C" { .channel = 1 \ } #endif /* PWM9_CONFIG */ -#endif /* BSP_USING_TMR3_CH1 */ +#endif /* BSP_USING_TMR3_CH1 */ #ifdef BSP_USING_TMR3_CH2 #ifndef PWM10_CONFIG @@ -149,7 +149,7 @@ extern "C" { } #endif /* PWM12_CONFIG */ #endif /* BSP_USING_TMR3_CH4 */ - + #ifdef __cplusplus } #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_rtc.c b/bsp/at32/Libraries/rt_drivers/drv_rtc.c index bd4d89a9ed..d943123e88 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -79,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return -RT_ERROR; } #else - /* Set the RTC counter value */ - RTC_SetCounter(time_stamp); - /* Wait until last write operation on RTC registers has finished */ - RTC_WaitForLastTask(); + /* Set the RTC counter value */ + RTC_SetCounter(time_stamp); + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); #endif /* SOC_SERIES_AT32F415 */ LOG_D("set rtc time."); #ifdef SOC_SERIES_AT32F415 @@ -117,7 +117,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) ERTC_InitType ERTC_InitStructure; #endif /* Allow access to BKP Domain */ - PWR_BackupAccessCtrl(ENABLE); + PWR_BackupAccessCtrl(ENABLE); #ifdef SOC_SERIES_AT32F415 #ifdef BSP_RTC_USING_LSI @@ -148,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) #else if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA) #endif - { + { LOG_I("RTC hasn't been configured, please use <date> command to config."); #ifdef SOC_SERIES_AT32F415 /* Configure the ERTC data register and ERTC prescaler */ diff --git a/bsp/at32/Libraries/rt_drivers/drv_sdio.c b/bsp/at32/Libraries/rt_drivers/drv_sdio.c index eb721033b5..9bbfa910c2 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sdio.c +++ b/bsp/at32/Libraries/rt_drivers/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_sdio.h b/bsp/at32/Libraries/rt_drivers/drv_sdio.h index cd0f05b9fb..de993881c9 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sdio.h +++ b/bsp/at32/Libraries/rt_drivers/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c index 266209c245..3112da34f8 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c +++ b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -205,10 +205,10 @@ int rt_hw_i2c_init(void) result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); RT_ASSERT(result == RT_EOK); at32_i2c_bus_unlock(&soft_i2c_config[i]); - + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h index 2743259ef6..193c8cd4aa 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h +++ b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ struct at32_i2c .bus_name = "i2c1", \ } #endif - + #ifdef BSP_USING_I2C2 #define i2c_bus_CONFIG \ { \ @@ -46,7 +46,7 @@ struct at32_i2c .bus_name = "i2c2", \ } #endif - + #ifdef BSP_USING_I2C3 #define I2C3_BUS_CONFIG \ { \ @@ -55,7 +55,7 @@ struct at32_i2c .bus_name = "i2c3", \ } #endif - + #ifdef BSP_USING_I2C4 #define I2C4_BUS_CONFIG \ { \ diff --git a/bsp/at32/Libraries/rt_drivers/drv_spi.c b/bsp/at32/Libraries/rt_drivers/drv_spi.c index c7821d4053..161845702f 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_spi.c +++ b/bsp/at32/Libraries/rt_drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2020-01-09 shelton first version */ - + #include <board.h> #include "drv_spi.h" @@ -24,7 +24,7 @@ #ifdef DEBUG #define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) #else -#define DEBUG_PRINTF(...) +#define DEBUG_PRINTF(...) #endif /* private rt-thread spi ops function */ @@ -81,13 +81,13 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) { - struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; + struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; struct at32_spi *spi_instance = (struct at32_spi *)spi_bus->parent.user_data; - + SPI_InitType SPI_InitStruct; - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); at32_msp_spi_init(spi_instance->config->spix); @@ -162,7 +162,7 @@ static rt_err_t configure(struct rt_spi_device* device, SPI_InitStruct.SPI_MCLKP = SPI_MCLKP_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -172,11 +172,11 @@ static rt_err_t configure(struct rt_spi_device* device, case RT_SPI_MODE_1: SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_LOW; - break; + break; case RT_SPI_MODE_2: SPI_InitStruct.SPI_CPHA = SPI_CPHA_1EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH; - break; + break; case RT_SPI_MODE_3: SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH; @@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device, /* init SPI */ SPI_Init(spi_instance->config->spix, &SPI_InitStruct); /* Enable SPI_MASTER */ - SPI_Enable(spi_instance->config->spix, ENABLE); + SPI_Enable(spi_instance->config->spix, ENABLE); SPI_CRCEN(spi_instance->config->spix, DISABLE); return RT_EOK; @@ -213,9 +213,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes struct rt_spi_configuration * config = &device->config; struct at32_spi_cs * at32_spi_cs = device->parent.user_data; - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + /* take CS */ if(message->cs_take) { @@ -229,7 +229,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -240,12 +240,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by at32 lib //Wait until the transmit buffer is empty while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE)); // Send the byte - SPI_I2S_TxData(spi_instance->config->spix, data); + SPI_I2S_TxData(spi_instance->config->spix, data); //Wait until a data is received while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE)); @@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes //Wait until the transmit buffer is empty while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE)); // Send the byte - SPI_I2S_TxData(spi_instance->config->spix, data); + SPI_I2S_TxData(spi_instance->config->spix, data); //Wait until a data is received while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE)); @@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes /* release CS */ if(message->cs_release) { - GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin); + GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin); DEBUG_PRINTF("spi release cs\n"); } @@ -306,7 +306,7 @@ static struct at32_spi_config configs[] = { #ifdef BSP_USING_SPI1 {SPI1, "spi1"}, #endif - + #ifdef BSP_USING_SPI2 {SPI2, "spi2"}, #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_spi.h b/bsp/at32/Libraries/rt_drivers/drv_spi.h index d3134b00f0..cd90c9b2b0 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_spi.h +++ b/bsp/at32/Libraries/rt_drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_sram.c b/bsp/at32/Libraries/rt_drivers/drv_sram.c index e601b0e1a5..d77b900728 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sram.c +++ b/bsp/at32/Libraries/rt_drivers/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ static int rt_hw_sram_Init(void) /* Init XMC pin */ at32_msp_xmc_init(XMC); - + /*-- FSMC Configuration ------------------------------------------------------*/ p.XMC_AdrOpTime = 0x04; p.XMC_AdrHoldTime = 0x04; @@ -53,7 +53,7 @@ static int rt_hw_sram_Init(void) XMC_NORSRAMInitStructure.XMC_Dev = XMC_Dev_SRAM; XMC_NORSRAMInitStructure.XMC_BusType = XMC_BusType_16b; XMC_NORSRAMInitStructure.XMC_EnableBurstMode = XMC_BurstMode_Disable; - XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable; + XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable; XMC_NORSRAMInitStructure.XMC_WaitSignalLv = XMC_WaitSignalLv_Low; XMC_NORSRAMInitStructure.XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable; XMC_NORSRAMInitStructure.XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState; @@ -63,9 +63,9 @@ static int rt_hw_sram_Init(void) XMC_NORSRAMInitStructure.XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable; XMC_NORSRAMInitStructure.XMC_RWTimingStruct = &p; XMC_NORSRAMInitStructure.XMC_WTimingStruct = &p; - - XMC_NORSRAMInit(&XMC_NORSRAMInitStructure); - + + XMC_NORSRAMInit(&XMC_NORSRAMInitStructure); + /*!< Enable FSMC Bank1_SRAM Bank */ XMC_NORSRAMCmd(XMC_Bank1_NORSRAM3, ENABLE); @@ -73,7 +73,7 @@ static int rt_hw_sram_Init(void) /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, SRAM_LENGTH); #endif - + return result; } INIT_BOARD_EXPORT(rt_hw_sram_Init); @@ -81,11 +81,11 @@ INIT_BOARD_EXPORT(rt_hw_sram_Init); #ifdef DRV_DEBUG #ifdef FINSH_USING_MSH /** - * @brief Writes a Half-word buffer to the FSMC SRAM memory. - * @param pBuffer : pointer to buffer. - * @param WriteAddr : SRAM memory internal address from which the data will be + * @brief Writes a Half-word buffer to the FSMC SRAM memory. + * @param pBuffer : pointer to buffer. + * @param WriteAddr : SRAM memory internal address from which the data will be * written. - * @param NumHalfwordToWrite : number of half-words to write. + * @param NumHalfwordToWrite : number of half-words to write. * @retval None */ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) @@ -94,15 +94,15 @@ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t Num { /*!< Transfer data to the memory */ *(uint16_t *) (EXT_SRAM_BEGIN + WriteAddr) = *pBuffer++; - - /*!< Increment the address*/ + + /*!< Increment the address*/ WriteAddr += 2; - } + } } /** * @brief Reads a block of data from the FSMC SRAM memory. - * @param pBuffer : pointer to the buffer that receives the data read from the + * @param pBuffer : pointer to the buffer that receives the data read from the * SRAM memory. * @param ReadAddr : SRAM memory internal address to read from. * @param NumHalfwordToRead : number of half-words to read. @@ -115,9 +115,9 @@ static void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHa /*!< Read a half-word from the memory */ *pBuffer++ = *(__IO uint16_t*) (EXT_SRAM_BEGIN + ReadAddr); - /*!< Increment the address*/ + /*!< Increment the address*/ ReadAddr += 2; - } + } } /** @@ -146,9 +146,9 @@ int sram_test(void) /* Read data from XMC SRAM memory */ - SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE); + SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE); - /* Read back SRAM memory and check content correctness */ + /* Read back SRAM memory and check content correctness */ for (Index = 0x00; (Index < RT_BUFFER_SIZE) && (WriteReadStatus == 0); Index++) { if (RT_RxBuffer[Index] != RT_TxBuffer[Index]) @@ -156,7 +156,7 @@ int sram_test(void) WriteReadStatus = Index + 1; } } - + if(WriteReadStatus == 0) { LOG_D("SRAM test success!"); @@ -165,7 +165,7 @@ int sram_test(void) { LOG_E("SRAM test failed!"); } - + return RT_EOK; } MSH_CMD_EXPORT(sram_test, sram test) diff --git a/bsp/at32/Libraries/rt_drivers/drv_sram.h b/bsp/at32/Libraries/rt_drivers/drv_sram.h index 05b07e4155..0f83c429d8 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sram.h +++ b/bsp/at32/Libraries/rt_drivers/drv_sram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_usart.c b/bsp/at32/Libraries/rt_drivers/drv_usart.c index 226d9afeda..04838bf2ac 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_usart.c +++ b/bsp/at32/Libraries/rt_drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ !defined(BSP_USING_UART3) #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig �� RT-Thread Components �� Device Drivers */ + /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #endif struct at32_usart { diff --git a/bsp/at32/Libraries/rt_drivers/drv_usart.h b/bsp/at32/Libraries/rt_drivers/drv_usart.h index 1002a6fd51..fc493d42da 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_usart.h +++ b/bsp/at32/Libraries/rt_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_wdt.c b/bsp/at32/Libraries/rt_drivers/drv_wdt.c index 8ab3de703d..0b304ad1ff 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_wdt.c +++ b/bsp/at32/Libraries/rt_drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/applications/main.c b/bsp/at32/at32f403a-start/applications/main.c index cb63824e27..0234d32b04 100644 --- a/bsp/at32/at32f403a-start/applications/main.c +++ b/bsp/at32/at32f403a-start/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/board/board.c b/bsp/at32/at32f403a-start/board/board.c index 4ce5bb3909..27b672b4da 100644 --- a/bsp/at32/at32f403a-start/board/board.c +++ b/bsp/at32/at32f403a-start/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include <stdint.h> #include <rthw.h> #include <rtthread.h> diff --git a/bsp/at32/at32f403a-start/board/board.h b/bsp/at32/at32f403a-start/board/board.h index 976863d3eb..1f2a4f3f3c 100644 --- a/bsp/at32/at32f403a-start/board/board.h +++ b/bsp/at32/at32f403a-start/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/board/msp/at32_msp.c b/bsp/at32/at32f403a-start/board/msp/at32_msp.c index 1392b0e0cf..5d159850cc 100644 --- a/bsp/at32/at32f403a-start/board/msp/at32_msp.c +++ b/bsp/at32/at32f403a-start/board/msp/at32_msp.c @@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance) GPIO_InitType GPIO_InitStruct; ADC_Type *ADCx = (ADC_Type *)Instance; -#ifdef BSP_USING_ADC1 +#ifdef BSP_USING_ADC1 if(ADCx == ADC1) - { + { /* ADC1 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); - + } #endif -#ifdef BSP_USING_ADC2 +#ifdef BSP_USING_ADC2 if(ADCx == ADC2) { /* ADC2 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); } -#endif +#endif } #endif /* BSP_USING_ADC */ @@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance) /* TMR3 clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE); } -#endif +#endif #ifdef BSP_USING_HWTMR4 if(TMRx == TMR4) diff --git a/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c b/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c index ce151e2d4a..edd9b8d1d6 100644 --- a/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c +++ b/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c @@ -17,7 +17,7 @@ * * <h2><center>© COPYRIGHT 2018 ArteryTek</center></h2> ****************************************************************************** - */ + */ /** @addtogroup CMSIS * @{ @@ -68,23 +68,23 @@ Clock (MHz) PLL from HSE or HSI - SYSCLK HCLK PCLK2 PCLK1 - 24 24 24 24 - 36 36 36 36 - 48 48 48 24 - 56 56 56 28 - 72 72 72 36 - 96 96 48 48 - 108 108 54 54 - 120 120 60 60 - 144 144 72 72 - 150 150 75 75 - 168 168 84 84 - 176 176 88 88 - 192 192 96 96 - 200 200 100 100 - 224 224 112 112 - 240 240 120 120 + SYSCLK HCLK PCLK2 PCLK1 + 24 24 24 24 + 36 36 36 36 + 48 48 48 24 + 56 56 56 28 + 72 72 72 36 + 96 96 48 48 + 108 108 54 54 + 120 120 60 60 + 144 144 72 72 + 150 150 75 75 + 168 168 84 84 + 176 176 88 88 + 192 192 96 96 + 200 200 100 100 + 224 224 112 112 + 240 240 120 120 */ #if defined (AT32F403xx) || defined (AT32F413xx) || \ @@ -143,7 +143,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -573,7 +573,7 @@ static void SetSysClock(void) /** * @brief Setup the external memory controller. * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted + * This function configures the external SRAM mounted * (AT32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None @@ -654,7 +654,7 @@ static void SetSysClockToHSE(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -674,7 +674,7 @@ static void SetSysClockToHSE(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -725,7 +725,7 @@ static void SetSysClockTo24M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -745,7 +745,7 @@ static void SetSysClockTo24M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -811,7 +811,7 @@ static void SetSysClockTo36M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -831,7 +831,7 @@ static void SetSysClockTo36M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -897,7 +897,7 @@ static void SetSysClockTo48M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -917,7 +917,7 @@ static void SetSysClockTo48M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -984,7 +984,7 @@ static void SetSysClockTo56M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void) /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ RCC->CFG &= RCC_CFG_PLLCFG_MASK; - + #if defined (AT32F415xx) RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); #else @@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void) * @} */ -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ +/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/bsp/at32/at32f407-start/applications/main.c b/bsp/at32/at32f407-start/applications/main.c index cb63824e27..0234d32b04 100644 --- a/bsp/at32/at32f407-start/applications/main.c +++ b/bsp/at32/at32f407-start/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f407-start/board/board.c b/bsp/at32/at32f407-start/board/board.c index 4ce5bb3909..27b672b4da 100644 --- a/bsp/at32/at32f407-start/board/board.c +++ b/bsp/at32/at32f407-start/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include <stdint.h> #include <rthw.h> #include <rtthread.h> diff --git a/bsp/at32/at32f407-start/board/board.h b/bsp/at32/at32f407-start/board/board.h index 976863d3eb..1f2a4f3f3c 100644 --- a/bsp/at32/at32f407-start/board/board.h +++ b/bsp/at32/at32f407-start/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f407-start/board/msp/at32_msp.c b/bsp/at32/at32f407-start/board/msp/at32_msp.c index 1392b0e0cf..5d159850cc 100644 --- a/bsp/at32/at32f407-start/board/msp/at32_msp.c +++ b/bsp/at32/at32f407-start/board/msp/at32_msp.c @@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance) GPIO_InitType GPIO_InitStruct; ADC_Type *ADCx = (ADC_Type *)Instance; -#ifdef BSP_USING_ADC1 +#ifdef BSP_USING_ADC1 if(ADCx == ADC1) - { + { /* ADC1 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); - + } #endif -#ifdef BSP_USING_ADC2 +#ifdef BSP_USING_ADC2 if(ADCx == ADC2) { /* ADC2 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); } -#endif +#endif } #endif /* BSP_USING_ADC */ @@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance) /* TMR3 clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE); } -#endif +#endif #ifdef BSP_USING_HWTMR4 if(TMRx == TMR4) diff --git a/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c b/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c index efda1bc90b..3205197d67 100644 --- a/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c +++ b/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c @@ -17,7 +17,7 @@ * * <h2><center>© COPYRIGHT 2018 ArteryTek</center></h2> ****************************************************************************** - */ + */ /** @addtogroup CMSIS * @{ @@ -68,23 +68,23 @@ Clock (MHz) PLL from HSE or HSI - SYSCLK HCLK PCLK2 PCLK1 - 24 24 24 24 - 36 36 36 36 - 48 48 48 24 - 56 56 56 28 - 72 72 72 36 - 96 96 48 48 - 108 108 54 54 - 120 120 60 60 - 144 144 72 72 - 150 150 75 75 - 168 168 84 84 - 176 176 88 88 - 192 192 96 96 - 200 200 100 100 - 224 224 112 112 - 240 240 120 120 + SYSCLK HCLK PCLK2 PCLK1 + 24 24 24 24 + 36 36 36 36 + 48 48 48 24 + 56 56 56 28 + 72 72 72 36 + 96 96 48 48 + 108 108 54 54 + 120 120 60 60 + 144 144 72 72 + 150 150 75 75 + 168 168 84 84 + 176 176 88 88 + 192 192 96 96 + 200 200 100 100 + 224 224 112 112 + 240 240 120 120 */ #if defined (AT32F403xx) || defined (AT32F413xx) || \ @@ -143,7 +143,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -573,7 +573,7 @@ static void SetSysClock(void) /** * @brief Setup the external memory controller. * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted + * This function configures the external SRAM mounted * (AT32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None @@ -654,7 +654,7 @@ static void SetSysClockToHSE(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -674,7 +674,7 @@ static void SetSysClockToHSE(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -725,7 +725,7 @@ static void SetSysClockTo24M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -745,7 +745,7 @@ static void SetSysClockTo24M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -811,7 +811,7 @@ static void SetSysClockTo36M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -831,7 +831,7 @@ static void SetSysClockTo36M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -897,7 +897,7 @@ static void SetSysClockTo48M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -917,7 +917,7 @@ static void SetSysClockTo48M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -984,7 +984,7 @@ static void SetSysClockTo56M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void) /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ RCC->CFG &= RCC_CFG_PLLCFG_MASK; - + #if defined (AT32F415xx) RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); #else @@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void) * @} */ -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ +/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/bsp/efm32/EFM32GG_DK3750/dvk.h b/bsp/efm32/EFM32GG_DK3750/dvk.h index 41af36b264..870c8b4121 100644 --- a/bsp/efm32/EFM32GG_DK3750/dvk.h +++ b/bsp/efm32/EFM32GG_DK3750/dvk.h @@ -164,7 +164,7 @@ int DVK_BRD3600A_usbVBUSGetOCFlagState(void); /* For "backward compatibility" with DVK */ /** DVK_enablePeripheral() backward compatibility */ -#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true) +#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true) /** DVK_disablePeripheral() backward compatibility */ #define DVK_disablePeripheral(X) DVK_peripheralAccess(X, false) @@ -193,7 +193,7 @@ __STATIC_INLINE uint16_t DVK_EBI_readRegister(volatile uint16_t *addr) /**************************************************************************//** * @brief Read data from 16-bit board control register * @param addr Register to read - * @return Value of board controller register + * @return Value of board controller register *****************************************************************************/ __STATIC_INLINE uint16_t DVK_readRegister(volatile uint16_t *addr) { diff --git a/bsp/efm32/EFM32GG_DK3750/trace.c b/bsp/efm32/EFM32GG_DK3750/trace.c index 5450de0270..2d5ffd71a5 100644 --- a/bsp/efm32/EFM32GG_DK3750/trace.c +++ b/bsp/efm32/EFM32GG_DK3750/trace.c @@ -125,7 +125,7 @@ void TRACE_SWOSetup(void) /**************************************************************************//** * @brief Profiler configuration for EFM32GG990F11024/EFM32GG-DK3750 * @return true if energyAware Profiler/SWO is enabled, false if not - * @note If first word of the user page is zero, this will not + * @note If first word of the user page is zero, this will not * enable SWO profiler output *****************************************************************************/ bool TRACE_ProfilerSetup(void) @@ -141,7 +141,7 @@ bool TRACE_ProfilerSetup(void) { TRACE_SWOSetup(); return true; - } + } } /** @} (end group BSP) */ diff --git a/bsp/efm32/EFM32GG_DK3750/trace.h b/bsp/efm32/EFM32GG_DK3750/trace.h index c45e35846c..0a812381ef 100644 --- a/bsp/efm32/EFM32GG_DK3750/trace.h +++ b/bsp/efm32/EFM32GG_DK3750/trace.h @@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void); * for TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run, * no example project will enable SWO trace. * @param[in] enable - * @note Add "em_msc.c" to build to use this function. + * @note Add "em_msc.c" to build to use this function. *****************************************************************************/ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) { @@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) data = *userpage; if(enable) { - if(data == 0xFFFFFFFF) + if(data == 0xFFFFFFFF) { return; } diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk.c b/bsp/efm32/EFM32_Gxxx_DK/dvk.c index 38569358e5..b1489c6c79 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk.c @@ -52,7 +52,7 @@ bool DVK_init(void) #endif #ifdef DVK_SPI_CONTROL ret = DVK_SPI_init(); -#endif +#endif if ( ret == false ) { /* Board is configured in wrong mode, please restart KIT! */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h b/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h index 813d22e545..70b427d7ff 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h @@ -73,7 +73,7 @@ #define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14)) /**< HW version */ #define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15)) /**< FW build number */ #define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16)) /**< FW version */ -#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */ +#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */ #define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18)) /**< Scratch EFM0 */ #define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19)) /**< Scratch EFM1 */ #define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A)) /**< Scratch EFM2 */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c index 72855106fc..a309df8204 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c @@ -155,7 +155,7 @@ uint16_t DVK_getPushButtons(void) /* Check state */ aemState = DVK_readRegister(BC_AEMSTATE); /* Read pushbutton status */ - if ( aemState == BC_AEMSTATE_EFM ) + if ( aemState == BC_AEMSTATE_EFM ) { pb = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f; } @@ -174,7 +174,7 @@ uint16_t DVK_getJoystick(void) /* Check state */ aemState = DVK_readRegister(BC_AEMSTATE); /* Read pushbutton status */ - if ( aemState == BC_AEMSTATE_EFM ) + if ( aemState == BC_AEMSTATE_EFM ) { joyStick = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f; } diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c index 02f6c0b303..0fed351767 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c @@ -163,7 +163,7 @@ bool DVK_EBI_init(void) * be configured for EBI access */ ebiMagic = DVK_EBI_readRegister(BC_MAGIC); while ((ebiMagic != BC_MAGIC_VALUE) && retry) - { + { DVK_EBI_disable(); /* Enable SPI interface */ DVK_SPI_init(); @@ -172,13 +172,13 @@ bool DVK_EBI_init(void) DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI); /* Disable SPI */ DVK_SPI_disable(); - + /* Now setup EBI again */ DVK_EBI_configure(); /* Wait until ready */ ebiMagic = DVK_EBI_readRegister(BC_MAGIC); if (ebiMagic == BC_MAGIC_VALUE) break; - + retry--; } if ( ! retry ) return false; diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c index 358b62bc9a..d4c536e21b 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c @@ -106,7 +106,7 @@ static void spiInit(void) /* Configure SPI bus connect pins, DOUT set to 0, disable EBI */ GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModePushPull, 0); GPIO_PinModeSet(PORT_EBIBUS_CONNECT, PIN_EBIBUS_CONNECT, gpioModePushPull, 1); - + /* Configure SPI pins */ GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0); GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModePushPull, 0); @@ -164,11 +164,11 @@ static uint16_t spiAccess(uint8_t spiaddr, uint8_t rw, uint16_t spidata) /* Just ignore data read back */ USART_Rx(USART_USED); - /* SPI data LSB */ + /* SPI data LSB */ USART_Tx(USART_USED, spidata & 0xFF); tmp = (uint16_t)USART_Rx(USART_USED); - /* SPI data MSB */ + /* SPI data MSB */ USART_Tx(USART_USED, spidata >> 8); tmp |= (uint16_t)USART_Rx(USART_USED) << 8; @@ -213,7 +213,7 @@ bool DVK_SPI_init(void) if(spiMagic != BC_MAGIC_VALUE) { return false; - } + } else { return true; diff --git a/bsp/efm32/EFM32_Gxxx_DK/trace.c b/bsp/efm32/EFM32_Gxxx_DK/trace.c index 0ef4438a29..ef1617cc1f 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/trace.c +++ b/bsp/efm32/EFM32_Gxxx_DK/trace.c @@ -89,7 +89,7 @@ void TRACE_SWOSetup(void) /**************************************************************************//** * @brief Profiler configuration * @return true if energyAware Profiler/SWO is enabled, false if not - * @note If first word of the user page is zero, this will not + * @note If first word of the user page is zero, this will not * enable SWO profiler output, see trace.h *****************************************************************************/ bool TRACE_ProfilerSetup(void) @@ -105,7 +105,7 @@ bool TRACE_ProfilerSetup(void) { TRACE_SWOSetup(); return true; - } + } } /** @} (end group BSP) */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/trace.h b/bsp/efm32/EFM32_Gxxx_DK/trace.h index 311e7ed357..1abb391a6c 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/trace.h +++ b/bsp/efm32/EFM32_Gxxx_DK/trace.h @@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void); * in TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run, * no example project will enable SWO trace. * @param[in] enable - * @note Add "em_msc.c" to build to use this function. + * @note Add "em_msc.c" to build to use this function. *****************************************************************************/ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) { @@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) data = *userpage; if(enable) { - if(data == 0xFFFFFFFF) + if(data == 0xFFFFFFFF) { return; } @@ -81,7 +81,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) return; } } - + /* Initialize MSC */ MSC_Init(); diff --git a/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h index 8c35ef2bd5..ee55e5dc79 100644 --- a/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h +++ b/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h @@ -1,24 +1,24 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* * Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. * -------------------------------------------------------------------- */ #ifndef _ARM_COMMON_TABLES_H diff --git a/bsp/efm32/Libraries/CMSIS/Include/arm_math.h b/bsp/efm32/Libraries/CMSIS/Include/arm_math.h index 7266c3efb3..96e0b65a01 100644 --- a/bsp/efm32/Libraries/CMSIS/Include/arm_math.h +++ b/bsp/efm32/Libraries/CMSIS/Include/arm_math.h @@ -1,33 +1,33 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * $Date: 15. February 2012 - * $Revision: V1.1.0 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * $Date: 15. February 2012 + * $Revision: V1.1.0 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.1.0 2012/02/15 - * Updated with more optimizations, bug fixes and minor API changes. - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. + * + * Version 1.1.0 2012/02/15 + * Updated with more optimizations, bug fixes and minor API changes. + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. * -------------------------------------------------------------------- */ /** @@ -35,10 +35,10 @@ * * <b>Introduction</b> * - * This user manual describes the CMSIS DSP software library, + * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * - * The library is divided into a number of functions each covering a specific category: + * The library is divided into a number of functions each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions @@ -51,40 +51,40 @@ * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. + * 32-bit integer and 32-bit floating-point values. + * + * <b>Pre-processor Macros</b> + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: * - * <b>Pre-processor Macros</b> - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * * Define macro ARM_MATH_ROUNDING for rounding on support functions * * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on cortex-M0 target. - * + * * - __FPU_PRESENT: * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries * * <b>Toolchain Support</b> * - * The library has been developed and tested with MDK-ARM version 4.23. + * The library has been developed and tested with MDK-ARM version 4.23. * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * <b>Using the Library</b> @@ -100,9 +100,9 @@ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) * * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 depending on the target processor in the application. * * <b>Examples</b> @@ -115,7 +115,7 @@ * - arm_cortexM0b_math.uvproj * - arm_cortexM0l_math.uvproj * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj + * - arm_cortexM3l_math.uvproj * - arm_cortexM4b_math.uvproj * - arm_cortexM4l_math.uvproj * - arm_cortexM4bf_math.uvproj @@ -272,7 +272,7 @@ #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif @@ -282,27 +282,27 @@ extern "C" * @brief Macros required for reciprocal calculation in Normalized LMS */ -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F #ifndef PI -#define PI 3.14159265358979f +#define PI 3.14159265358979f #endif /** * @brief Macros required for SINE and COSINE Fast math approximations */ -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 +#define INPUT_SPACING 0xB60B61 /** * @brief Macro for Unaligned Support @@ -315,7 +315,7 @@ extern "C" #else #define ALIGN4 __align(4) #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. @@ -371,7 +371,7 @@ extern "C" #else #define __SIMD32(addr) (*(__packed int32_t **) & (addr)) #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr)) -#endif +#endif #define __SIMD64(addr) (*(int64_t **) & (addr)) @@ -392,16 +392,16 @@ extern "C" */ #ifndef ARM_MATH_BIG_ENDIAN -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif @@ -1169,11 +1169,11 @@ extern "C" /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. */ void arm_fir_init_q31( arm_fir_instance_q31 * S, @@ -1199,11 +1199,11 @@ extern "C" /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. */ void arm_fir_init_f32( arm_fir_instance_f32 * S, @@ -1463,7 +1463,7 @@ extern "C" * @brief Floating-point matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ @@ -1476,7 +1476,7 @@ extern "C" * @brief Q15 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ @@ -1488,7 +1488,7 @@ extern "C" * @brief Q31 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ @@ -1531,7 +1531,7 @@ extern "C" * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results + * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ @@ -1665,7 +1665,7 @@ extern "C" * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ @@ -1680,7 +1680,7 @@ extern "C" * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ @@ -1695,7 +1695,7 @@ extern "C" * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ @@ -2187,7 +2187,7 @@ extern "C" /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function + * Internal functions prototypes FFT function ----------------------------------------------------------------------*/ /** @@ -2256,7 +2256,7 @@ extern "C" * @brief Core function for the f32 FFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of f32 data type. * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] *pCoef points to Twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @return none. */ @@ -2267,14 +2267,14 @@ extern "C" float32_t * pCoef, uint16_t twidCoefModifier); - /** - * @brief Core function for the Radix-2 Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ + /** + * @brief Core function for the Radix-2 Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ void arm_radix2_butterfly_q31( q31_t * pSrc, @@ -2282,14 +2282,14 @@ extern "C" q31_t * pCoef, uint16_t twidCoefModifier); - /** - * @brief Core function for the Radix-2 Q15 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ + /** + * @brief Core function for the Radix-2 Q15 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ void arm_radix2_butterfly_q15( q15_t * pSrc, @@ -2297,14 +2297,14 @@ extern "C" q15_t * pCoef, uint16_t twidCoefModifier); - /** - * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ + /** + * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ void arm_radix2_butterfly_inverse_q15( q15_t * pSrc, @@ -2312,14 +2312,14 @@ extern "C" q15_t * pCoef, uint16_t twidCoefModifier); - /** - * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ + /** + * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ void arm_radix2_butterfly_inverse_q31( q31_t * pSrc, @@ -2331,9 +2331,9 @@ extern "C" * @brief Core function for the f32 IFFT butterfly process. * @param[in, out] *pSrc points to the in-place buffer of f32 data type. * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] *pCoef points to Twiddle coefficient buffer. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen 1/fftLenfth + * @param[in] onebyfftLen 1/fftLenfth * @return none. */ @@ -2489,7 +2489,7 @@ extern "C" * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. */ arm_status arm_rfft_init_q15( @@ -2519,7 +2519,7 @@ extern "C" * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. */ arm_status arm_rfft_init_q31( @@ -2536,7 +2536,7 @@ extern "C" * @param[in] fftLenReal length of the FFT. * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value. */ arm_status arm_rfft_init_f32( @@ -2582,7 +2582,7 @@ extern "C" * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length. */ arm_status arm_dct4_init_f32( @@ -2629,7 +2629,7 @@ extern "C" * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ arm_status arm_dct4_init_q31( @@ -2676,7 +2676,7 @@ extern "C" * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ arm_status arm_dct4_init_q15( @@ -3155,7 +3155,7 @@ extern "C" q31_t * pDst, uint32_t blockSize); /** - * @brief Copies the elements of a floating-point vector. + * @brief Copies the elements of a floating-point vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3167,7 +3167,7 @@ extern "C" uint32_t blockSize); /** - * @brief Copies the elements of a Q7 vector. + * @brief Copies the elements of a Q7 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3179,7 +3179,7 @@ extern "C" uint32_t blockSize); /** - * @brief Copies the elements of a Q15 vector. + * @brief Copies the elements of a Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3191,7 +3191,7 @@ extern "C" uint32_t blockSize); /** - * @brief Copies the elements of a Q31 vector. + * @brief Copies the elements of a Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3202,7 +3202,7 @@ extern "C" q31_t * pDst, uint32_t blockSize); /** - * @brief Fills a constant value into a floating-point vector. + * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3214,7 +3214,7 @@ extern "C" uint32_t blockSize); /** - * @brief Fills a constant value into a Q7 vector. + * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3226,7 +3226,7 @@ extern "C" uint32_t blockSize); /** - * @brief Fills a constant value into a Q15 vector. + * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3238,7 +3238,7 @@ extern "C" uint32_t blockSize); /** - * @brief Fills a constant value into a Q31 vector. + * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process @@ -3249,14 +3249,14 @@ extern "C" q31_t * pDst, uint32_t blockSize); -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. */ void arm_conv_f32( @@ -3266,17 +3266,17 @@ extern "C" uint32_t srcBLen, float32_t * pDst); - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. */ @@ -3290,14 +3290,14 @@ extern "C" q15_t * pScratch2); -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. */ void arm_conv_q15( @@ -3318,11 +3318,11 @@ extern "C" */ void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 @@ -3331,9 +3331,9 @@ extern "C" * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. */ void arm_conv_fast_opt_q15( @@ -3382,16 +3382,16 @@ extern "C" q31_t * pDst); - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. */ void arm_conv_opt_q7( @@ -3444,18 +3444,18 @@ extern "C" uint32_t firstIndex, uint32_t numPoints); - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( @@ -3504,13 +3504,13 @@ extern "C" */ arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3522,9 +3522,9 @@ extern "C" * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( @@ -3583,18 +3583,18 @@ extern "C" uint32_t numPoints); - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( @@ -4086,8 +4086,8 @@ extern "C" * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ @@ -4654,15 +4654,15 @@ extern "C" float32_t * pDst); - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. */ void arm_correlate_opt_q15( q15_t * pSrcA, @@ -4701,11 +4701,11 @@ extern "C" */ void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); @@ -4716,7 +4716,7 @@ extern "C" * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @return none. */ @@ -4764,16 +4764,16 @@ extern "C" - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. */ void arm_correlate_opt_q7( @@ -5019,9 +5019,9 @@ extern "C" /* * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. * @return none. */ @@ -5032,9 +5032,9 @@ extern "C" /* * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. * @return none. */ @@ -5132,7 +5132,7 @@ extern "C" /** * @defgroup PID PID Motor Control * - * A Proportional Integral Derivative (PID) controller is a generic feedback control + * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * @@ -5151,39 +5151,39 @@ extern "C" * * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. */ /** @@ -5225,13 +5225,13 @@ extern "C" * @param[in] in input sample to process * @return out processed output sample. * - * <b>Scaling and Overflow Behavior:</b> - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ __STATIC_INLINE q31_t arm_pid_q31( @@ -5272,13 +5272,13 @@ extern "C" * @param[in] in input sample to process * @return out processed output sample. * - * <b>Scaling and Overflow Behavior:</b> - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ @@ -5366,7 +5366,7 @@ extern "C" * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code> * can be calculated using only <code>Ia</code> and <code>Ib</code>. * - * The function operates on a single sample of data and each call to the function returns the processed output. + * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif @@ -5470,8 +5470,8 @@ extern "C" /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. + * + * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif @@ -5513,7 +5513,7 @@ extern "C" } /** - * @brief Inverse Clarke transform for Q31 version + * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] *pIa points to output three-phase coordinate <code>a</code> @@ -5575,19 +5575,19 @@ extern "C" * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents - * from the stationary to the moving reference frame and control the spatial relationship between + * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents + * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * - * The function operates on a single sample of data and each call to the function returns the processed output. + * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif - * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components, - * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the + * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components, + * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. @@ -5604,8 +5604,8 @@ extern "C" * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. @@ -5631,7 +5631,7 @@ extern "C" } /** - * @brief Park transform for Q31 version + * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] *pId points to output rotor reference frame d @@ -5704,12 +5704,12 @@ extern "C" * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * - * The function operates on a single sample of data and each call to the function returns the processed output. + * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif - * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components, - * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the + * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components, + * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. @@ -5751,7 +5751,7 @@ extern "C" /** - * @brief Inverse Park transform for Q31 version + * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha @@ -5827,7 +5827,7 @@ extern "C" * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * - * \par + * \par * \image html LinearInterp.gif "Linear interpolation" * * \par @@ -5847,10 +5847,10 @@ extern "C" * sample of data and each call to the function returns a single processed value. * <code>S</code> points to an instance of the Linear Interpolate function data structure. * <code>x</code> is the input sample value. The functions returns the output value. - * + * * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. */ /** @@ -5982,7 +5982,7 @@ extern "C" * * \par * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. + * This function can support maximum of table size 2^12. * */ @@ -6162,7 +6162,7 @@ extern "C" * @defgroup SQRT Square Root * * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. + * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * <pre> @@ -7072,11 +7072,11 @@ extern "C" uint32_t numSamples); /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. + * @param[in] blockSize length of the input vector + * @return none. */ void arm_float_to_q31( float32_t * pSrc, @@ -7084,10 +7084,10 @@ extern "C" uint32_t blockSize); /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector + * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q15( @@ -7096,10 +7096,10 @@ extern "C" uint32_t blockSize); /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector + * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q7( @@ -7219,12 +7219,12 @@ extern "C" * + f(XF, YF+1) * (1-(x-XF))*(y-YF) * + f(XF+1, YF+1) * (x-XF)*(y-YF) * </pre> - * Note that the coordinates (x, y) contain integer and fractional components. + * Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** @@ -7543,7 +7543,7 @@ extern "C" -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h b/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h index 0173893fbd..350d452093 100644 --- a/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h +++ b/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h @@ -636,14 +636,14 @@ typedef struct __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; + uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; + uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; + uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h b/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h index a965537402..2a67fa2a41 100644 --- a/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h +++ b/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h @@ -669,14 +669,14 @@ typedef struct __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; + uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; + uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; + uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h b/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h index 7e56b0f332..4176fe8d5d 100644 --- a/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h +++ b/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h @@ -607,14 +607,14 @@ typedef struct __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; + uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; + uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; + uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ diff --git a/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h b/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h index 2ccfd17504..db29415c55 100644 --- a/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h +++ b/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h @@ -1,20 +1,20 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2012 ARM Limited. All rights reserved. - * +/* ---------------------------------------------------------------------- + * Copyright (C) 2012 ARM Limited. All rights reserved. + * * $Date: 5. March 2012 * $Revision: V0.03 - * + * * Project: CMSIS-RTOS API * Title: cmsis_os.h template header file - * + * * Version 0.02 - * Initial Proposal Phase + * Initial Proposal Phase * Version 0.03 * osKernelStart added, optional feature: main started as thread * osSemaphores have standard behaviour * osTimerCreate does not start the timer, added osTimerStart - * osThreadPass is renamed to osThreadYield - * -------------------------------------------------------------------- */ + * osThreadPass is renamed to osThreadYield + * -------------------------------------------------------------------- */ /** \page cmsis_os_h Header File Template: cmsis_os.h @@ -35,8 +35,8 @@ The file cmsis_os.h contains: All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed \b os_ are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. - -Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation. + +Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel. Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer @@ -52,7 +52,7 @@ The following CMSIS-RTOS functions can be called from threads and interrupt serv - \ref osMessagePut, \ref osMessageGet - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree -Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. @@ -73,11 +73,11 @@ extern void thread_sample (void const *argument); // function protot osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); // Pool definition -osPoolDef(MyPool, 10, long); +osPoolDef(MyPool, 10, long); \endcode -This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is +This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project. @@ -92,7 +92,7 @@ used throughout the whole project. \endcode */ - + #ifndef _CMSIS_OS_H #define _CMSIS_OS_H @@ -100,7 +100,7 @@ used throughout the whole project. #define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0]) /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number. -#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. #define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string @@ -113,7 +113,7 @@ used throughout the whole project. #define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread #define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function #define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available - + #include <stdint.h> #include <stddef.h> @@ -133,7 +133,7 @@ typedef enum { osPriorityBelowNormal = -1, ///< priority: below normal osPriorityNormal = 0, ///< priority: normal (default) osPriorityAboveNormal = +1, ///< priority: above normal - osPriorityHigh = +2, ///< priority: high + osPriorityHigh = +2, ///< priority: high osPriorityRealtime = +3, ///< priority: realtime (highest) osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority } osPriority; @@ -160,23 +160,23 @@ typedef enum { osErrorValue = 0x86, ///< value of a parameter is out of range. osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. -} osStatus; +} osStatus; /// Timer type value for the timer definition /// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. typedef enum { - osTimerOnce = 0, ///< one-shot timer - osTimerPeriodic = 1 ///< repeating timer -} os_timer_type; + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; /// Entry point of a thread. /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); +typedef void (*os_pthread) (void const *argument); /// Entry point of a timer call back function. /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); +typedef void (*os_ptimer) (void const *argument); // >>> the following data type definitions may shall adapted towards a specific RTOS @@ -240,7 +240,7 @@ typedef const struct os_semaphore_def { /// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. typedef const struct os_pool_def { uint32_t pool_sz; ///< number of items (elements) in the pool - uint32_t item_sz; ///< size of an item + uint32_t item_sz; ///< size of an item void *pool; ///< pointer to memory for pool } osPoolDef_t; @@ -248,7 +248,7 @@ typedef const struct os_pool_def { /// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. typedef const struct os_messageQ_def { uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item + uint32_t item_sz; ///< size of an item void *pool; ///< memory array for messages } osMessageQDef_t; @@ -256,23 +256,23 @@ typedef const struct os_messageQ_def { /// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. typedef const struct os_mailQ_def { uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item + uint32_t item_sz; ///< size of an item void *pool; ///< memory array for mail } osMailQDef_t; -/// Event structure contains detailed information about an event. -/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. /// However the struct may be extended at the end. typedef struct { osStatus status; ///< status code: event or error information union { - uint32_t v; ///< message as 32-bit value + uint32_t v; ///< message as 32-bit value void *p; ///< message or mail as void pointer - int32_t signals; ///< signal flags + int32_t signals; ///< signal flags } value; ///< event value union { - osMailQId mail_id; ///< mail id obtained by \ref osMailCreate - osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate } def; ///< event definition } osEvent; @@ -283,11 +283,11 @@ typedef struct { /// \param[in] thread_def thread definition referenced with \ref osThread. /// \param[in] argument pointer that is passed to the thread function as start argument. /// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. osStatus osKernelStart (osThreadDef_t *thread_def, void *argument); - + /// Check if the RTOS kernel is already started. -/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. /// \return 0 RTOS is not started, 1 RTOS is started. int32_t osKernelRunning(void); @@ -299,7 +299,7 @@ int32_t osKernelRunning(void); /// \param priority initial priority of the thread function. /// \param instances number of possible thread instances. /// \param stacksz stack size (in bytes) requirements for the thread function. -/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osThreadDef(name, priority, instances, stacksz) \ @@ -312,7 +312,7 @@ osThreadDef_t os_thread_def_##name = \ /// Access a Thread defintion. /// \param name name of the thread definition object. -/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osThread(name) \ &os_thread_def_##name @@ -341,7 +341,7 @@ osStatus osThreadTerminate (osThreadId thread_id); /// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. osStatus osThreadYield (void); -/// Change priority of an active thread. +/// Change priority of an active thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] priority new priority value for the thread function. /// \return status code that indicates the execution status of the function. @@ -359,7 +359,7 @@ osPriority osThreadGetPriority (osThreadId thread_id); // ==== Generic Wait Functions ==== /// Wait for Timeout (Time Delay) -/// \param[in] millisec time delay value +/// \param[in] millisec time delay value /// \return status code that indicates the execution status of the function. osStatus osDelay (uint32_t millisec); @@ -378,7 +378,7 @@ osEvent osWait (uint32_t millisec); /// Define a Timer object. /// \param name name of the timer object. /// \param function name of the timer call back function. -/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osTimerDef(name, function) \ @@ -391,7 +391,7 @@ osTimerDef_t os_timer_def_##name = \ /// Access a Timer definition. /// \param name name of the timer object. -/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osTimer(name) \ &os_timer_def_##name @@ -452,7 +452,7 @@ osEvent osSignalWait (int32_t signals, uint32_t millisec); /// Define a Mutex. /// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osMutexDef(name) \ @@ -464,7 +464,7 @@ osMutexDef_t os_mutex_def_##name = { 0 } /// Access a Mutex defintion. /// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osMutex(name) \ &os_mutex_def_##name @@ -495,7 +495,7 @@ osStatus osMutexRelease (osMutexId mutex_id); /// Define a Semaphore object. /// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osSemaphoreDef(name) \ @@ -507,7 +507,7 @@ osSemaphoreDef_t os_semaphore_def_##name = { 0 } /// Access a Semaphore definition. /// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osSemaphore(name) \ &os_semaphore_def_##name @@ -533,7 +533,7 @@ int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); #endif // Semaphore available - + // ==== Memory Pool Management Functions ==== #if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available @@ -542,7 +542,7 @@ osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); /// \param name name of the memory pool. /// \param no maximum number of objects (elements) in the memory pool. /// \param type data type of a single object (element). -/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osPoolDef(name, no, type) \ @@ -555,7 +555,7 @@ osPoolDef_t os_pool_def_##name = \ /// \brief Access a Memory Pool definition. /// \param name name of the memory pool -/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osPool(name) \ &os_pool_def_##name @@ -572,7 +572,7 @@ osPoolId osPoolCreate (osPoolDef_t *pool_def); /// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. void *osPoolAlloc (osPoolId pool_id); -/// Allocate a memory block from a memory pool and set memory block to zero +/// Allocate a memory block from a memory pool and set memory block to zero /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \return address of the allocated memory block or NULL in case of no memory available. /// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. @@ -596,7 +596,7 @@ osStatus osPoolFree (osPoolId pool_id, void *block); /// \param name name of the queue. /// \param queue_sz maximum number of messages in the queue. /// \param type data type of a single message element (for debugger). -/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osMessageQDef(name, queue_sz, type) \ @@ -609,7 +609,7 @@ osMessageQDef_t os_messageQ_def_##name = \ /// \brief Access a Message Queue Definition. /// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osMessageQ(name) \ &os_messageQ_def_##name @@ -647,7 +647,7 @@ osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); /// \param name name of the queue /// \param queue_sz maximum number of messages in queue /// \param type data type of a single message element -/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #if defined (osObjectsExternal) // object is external #define osMailQDef(name, queue_sz, type) \ @@ -657,10 +657,10 @@ extern osMailQDef_t os_mailQ_def_##name osMailQDef_t os_mailQ_def_##name = \ { (queue_sz), sizeof (type) } #endif - + /// \brief Access a Mail Queue Definition /// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the /// macro body is implementation specific in every CMSIS-RTOS. #define osMailQ(name) \ &os_mailQ_def_##name @@ -706,7 +706,7 @@ osEvent osMailGet (osMailQId queue_id, uint32_t millisec); /// \return status code that indicates the execution status of the function. /// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. osStatus osMailFree (osMailQId queue_id, void *mail); - + #endif // Mail Queues available diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c index 1713a1aed5..2328977341 100644 --- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c +++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c @@ -39,7 +39,7 @@ extern void __iar_program_start(void); extern void SystemInit(void); /* Auto defined by linker */ -extern unsigned char CSTACK$$Limit; +extern unsigned char CSTACK$$Limit; __weak void Reset_Handler(void) { diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c index d343bd4357..a11e3de7a2 100644 --- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c +++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c @@ -64,18 +64,18 @@ /* Do not define variable if HF crystal oscillator not present */ #if (EFM32_HFXO_FREQ > 0) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System HFXO clock. */ +/** System HFXO clock. */ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif -#ifndef EFM32_LFXO_FREQ +#ifndef EFM32_LFXO_FREQ #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) #endif /* Do not define variable if LF crystal oscillator not present */ #if (EFM32_LFXO_FREQ > 0) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System LFXO clock. */ +/** System LFXO clock. */ static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif @@ -118,13 +118,13 @@ uint32_t SystemCoreClock; uint32_t SystemCoreClockGet(void) { uint32_t ret; - + ret = SystemHFClockGet(); #if defined (_EFM32_GIANT_FAMILY) /* Leopard/Giant Gecko has an additional divider */ ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT)); #endif - ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> + ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; /* Keep CMSIS variable up-to-date just in case */ @@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void) uint32_t SystemHFClockGet(void) { uint32_t ret; - + switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) { @@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void) ret = 0; #endif break; - + case CMU_STATUS_LFRCOSEL: ret = EFM32_LFRCO_FREQ; break; - + case CMU_STATUS_HFXOSEL: #if (EFM32_HFXO_FREQ > 0) ret = SystemHFXOClock; @@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void) ret = 0; #endif break; - + default: /* CMU_STATUS_HFRCOSEL */ switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) { diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c index 0e3124dcea..356dec376b 100644 --- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c +++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c @@ -39,7 +39,7 @@ extern void __iar_program_start(void); extern void SystemInit(void); /* Auto defined by linker */ -extern unsigned char CSTACK$$Limit; +extern unsigned char CSTACK$$Limit; __weak void Reset_Handler(void) { diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c index c7709f9a64..841ac171b6 100644 --- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c +++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c @@ -64,18 +64,18 @@ /* Do not define variable if HF crystal oscillator not present */ #if (EFM32_HFXO_FREQ > 0) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System HFXO clock. */ +/** System HFXO clock. */ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif -#ifndef EFM32_LFXO_FREQ +#ifndef EFM32_LFXO_FREQ #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) #endif /* Do not define variable if LF crystal oscillator not present */ #if (EFM32_LFXO_FREQ > 0) /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System LFXO clock. */ +/** System LFXO clock. */ static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ #endif @@ -118,13 +118,13 @@ uint32_t SystemCoreClock; uint32_t SystemCoreClockGet(void) { uint32_t ret; - + ret = SystemHFClockGet(); #if defined (_EFM32_GIANT_FAMILY) /* Leopard/Giant Gecko has an additional divider */ ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT)); #endif - ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> + ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; /* Keep CMSIS variable up-to-date just in case */ @@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void) uint32_t SystemHFClockGet(void) { uint32_t ret; - + switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) { @@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void) ret = 0; #endif break; - + case CMU_STATUS_LFRCOSEL: ret = EFM32_LFRCO_FREQ; break; - + case CMU_STATUS_HFXOSEL: #if (EFM32_HFXO_FREQ > 0) ret = SystemHFXOClock; @@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void) ret = 0; #endif break; - + default: /* CMU_STATUS_HFRCOSEL */ switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) { diff --git a/bsp/efm32/Libraries/emlib/inc/em_acmp.h b/bsp/efm32/Libraries/emlib/inc/em_acmp.h index 0c20ead97f..bc36e3c618 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_acmp.h +++ b/bsp/efm32/Libraries/emlib/inc/em_acmp.h @@ -173,7 +173,7 @@ typedef struct * power used by the VDD and bandgap references. */ bool lowPowerReferenceEnabled; - /** Vdd reference value. VDD_SCALED = VDD � VDDLEVEL � 50mV/3.8V. + /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V. * Valid values are in the range 0-63. */ uint32_t vddLevel; @@ -229,7 +229,7 @@ typedef struct * power used by the VDD and bandgap references. */ bool lowPowerReferenceEnabled; - /** Vdd reference value. VDD_SCALED = VDD � VDDLEVEL � 50mV/3.8V. + /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V. * Valid values are in the range 0-63. */ uint32_t vddLevel; diff --git a/bsp/efm32/Libraries/emlib/inc/em_burtc.h b/bsp/efm32/Libraries/emlib/inc/em_burtc.h index 3f7233a5c5..8e6d11ec6a 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_burtc.h +++ b/bsp/efm32/Libraries/emlib/inc/em_burtc.h @@ -289,8 +289,8 @@ __STATIC_INLINE void BURTC_Enable(bool enable) if( enable ) { BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0); - } - else + } + else { BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1); } diff --git a/bsp/efm32/Libraries/emlib/inc/em_cmu.h b/bsp/efm32/Libraries/emlib/inc/em_cmu.h index 7f0a3fbd4c..881fd77174 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_cmu.h +++ b/bsp/efm32/Libraries/emlib/inc/em_cmu.h @@ -432,7 +432,7 @@ typedef enum #endif #if defined(USB_PRESENT) - cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) | + cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) | @@ -441,7 +441,7 @@ typedef enum #endif #if defined(USB_PRESENT) - cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | + cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) | diff --git a/bsp/efm32/Libraries/emlib/inc/em_dma.h b/bsp/efm32/Libraries/emlib/inc/em_dma.h index 5ce256296f..544ccb5bc3 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_dma.h +++ b/bsp/efm32/Libraries/emlib/inc/em_dma.h @@ -251,7 +251,7 @@ typedef struct /** Enable repeated loop */ bool enable; /** Width of transfer, reload value for nMinus1 */ - uint16_t nMinus1; + uint16_t nMinus1; } DMA_CfgLoop_TypeDef; @@ -335,20 +335,20 @@ typedef struct * Pointer to the controlblock in memory holding descriptors (channel * control data structures). This memory must be properly aligned * according to requirements. - * + * * Alignment requirements are * a) 5 bits base requirement, bits [4:0] * b) Add the number of bits needed to represent the wanted number * of channels * c) Align structure with this number of bits set to zero - * + * * Examples: 4 channels, 5 + 2 (channels 0 to 3) = 7 bits * 7 bit alignment, 64 byte address alignment * 8 channels, 5 + 3 (channels 0 to 7) = 8 bits * 8 bit alignment, 256 byte address alignment * 12 channels, 5 + 4 (channels 0 to 11) = 9 bits * 9 bit alignment, 512 byte address alignment - * + * * Please refer to the reference manual, DMA chapter for more details. * * It is possible to provide a smaller memory block, only covering diff --git a/bsp/efm32/Libraries/emlib/inc/em_ebi.h b/bsp/efm32/Libraries/emlib/inc/em_ebi.h index 43bf58de2c..dbfe09e74e 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_ebi.h +++ b/bsp/efm32/Libraries/emlib/inc/em_ebi.h @@ -157,7 +157,7 @@ typedef enum } EBI_ALow_TypeDef; /** Adress Pin Enable, high limit - higher limit of pins to enable */ -typedef enum +typedef enum { /** All EBI_A pins are disabled */ ebiAHighA0 = EBI_ROUTE_APEN_A0, @@ -218,9 +218,9 @@ typedef enum { /** EBI PIN I/O Location 1 */ ebiLocation1 = EBI_ROUTE_LOCATION_LOC1, /** EBI PIN I/O Location 2 */ - ebiLocation2 = EBI_ROUTE_LOCATION_LOC2, + ebiLocation2 = EBI_ROUTE_LOCATION_LOC2, /** EBI PIN I/O Location 3 */ - // ebiLocation3 = EBI_ROUTE_LOCATION_LOC3, + // ebiLocation3 = EBI_ROUTE_LOCATION_LOC3, } EBI_Location_TypeDef; #endif @@ -626,7 +626,7 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color) ******************************************************************************/ __STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend) { - EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend; + EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend; } @@ -676,7 +676,7 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void) /***************************************************************************//** - * @brief Set Frame Buffer Trigger + * @brief Set Frame Buffer Trigger * Frame buffer pointer will be updated either on each horizontal line (hsync) * or vertical update (vsync)( ******************************************************************************/ diff --git a/bsp/efm32/Libraries/emlib/inc/em_emu.h b/bsp/efm32/Libraries/emlib/inc/em_emu.h index ea000c6c2f..c6687d41a0 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_emu.h +++ b/bsp/efm32/Libraries/emlib/inc/em_emu.h @@ -62,8 +62,8 @@ typedef enum /** Select ULFRCO as duty oscillator in EM4 */ emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, /** Select LFXO as duty oscillator in EM4 */ - emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, - /** Select LFRCO as duty oscillator in EM4 */ + emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, + /** Select LFRCO as duty oscillator in EM4 */ emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO } EMU_EM4Osc_TypeDef; @@ -124,15 +124,15 @@ typedef enum #if defined(_EFM32_GIANT_FAMILY) /** Energy Mode 4 initialization structure */ -typedef struct +typedef struct { /** Lock configuration of regulator, BOD and oscillator */ bool lockConfig; /** EM4 duty oscillator */ - EMU_EM4Osc_TypeDef osc; + EMU_EM4Osc_TypeDef osc; /** Wake up on EM4 BURTC interrupt */ bool buRtcWakeup; - /** Enable EM4 voltage regulator */ + /** Enable EM4 voltage regulator */ bool vreg; } EMU_EM4Init_TypeDef; @@ -145,7 +145,7 @@ typedef struct } /** Backup Power Domain Initialization structure */ -typedef struct +typedef struct { /* Backup Power Domain power configuration */ @@ -153,7 +153,7 @@ typedef struct EMU_Probe_TypeDef probe; /** Enable BOD calibration mode */ bool bodCal; - /** Enable BU_STAT status pin for active BU mode */ + /** Enable BU_STAT status pin for active BU mode */ bool statusPinEnable; /* Backup Power Domain connection configuration */ diff --git a/bsp/efm32/Libraries/emlib/inc/em_msc.h b/bsp/efm32/Libraries/emlib/inc/em_msc.h index 0af96f9271..ac00aac98a 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_msc.h +++ b/bsp/efm32/Libraries/emlib/inc/em_msc.h @@ -88,7 +88,7 @@ typedef enum #if defined (_EFM32_GIANT_FAMILY) /** Strategy for prioritized bus access */ -typedef enum { +typedef enum { mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */ mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */ mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */ diff --git a/bsp/efm32/Libraries/emlib/inc/em_rmu.h b/bsp/efm32/Libraries/emlib/inc/em_rmu.h index c180344616..8ee5ebec33 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_rmu.h +++ b/bsp/efm32/Libraries/emlib/inc/em_rmu.h @@ -59,10 +59,10 @@ typedef enum { #if defined(_EFM32_GIANT_FAMILY) /** Reset control over Backup Power Domain */ - rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT, + rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT, #endif /** Allow Cortex-M3 lock up signal */ - rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT + rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT } RMU_Reset_TypeDef; /******************************************************************************* diff --git a/bsp/efm32/Libraries/emlib/inc/em_usart.h b/bsp/efm32/Libraries/emlib/inc/em_usart.h index e30d75c7fe..d36209bc37 100644 --- a/bsp/efm32/Libraries/emlib/inc/em_usart.h +++ b/bsp/efm32/Libraries/emlib/inc/em_usart.h @@ -276,7 +276,7 @@ typedef struct #if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) /** USART PRS trigger enable */ -typedef struct +typedef struct { #if defined(_EFM32_GIANT_FAMILY) /** Enable AUTOTX */ diff --git a/bsp/efm32/Libraries/emlib/src/em_burtc.c b/bsp/efm32/Libraries/emlib/src/em_burtc.c index 005c7770fb..dac6645c67 100644 --- a/bsp/efm32/Libraries/emlib/src/em_burtc.c +++ b/bsp/efm32/Libraries/emlib/src/em_burtc.c @@ -87,7 +87,7 @@ __STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div) * Configures the BURTC peripheral. * * @note - * Before initialization, BURTC module must first be enabled by clearing the + * Before initialization, BURTC module must first be enabled by clearing the * reset bit in the RMU, i.e. * @verbatim * RMU_ResetControl(rmuResetBU, false); @@ -123,7 +123,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) presc = BURTC_DivToLog2(burtcInit->clkDiv); /* Make sure all registers are updated simultaneously */ - if (burtcInit->enable) + if (burtcInit->enable) { BURTC_FreezeEnable(true); } @@ -132,7 +132,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) BURTC->LPMODE = (uint32_t)(burtcInit->lowPowerMode); /* New configuration */ - ctrl = ((BURTC_CTRL_RSTEN) | + ctrl = ((BURTC_CTRL_RSTEN) | (burtcInit->mode) | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) | diff --git a/bsp/efm32/Libraries/emlib/src/em_cmu.c b/bsp/efm32/Libraries/emlib/src/em_cmu.c index 974ff932d6..516f7b68ca 100644 --- a/bsp/efm32/Libraries/emlib/src/em_cmu.c +++ b/bsp/efm32/Libraries/emlib/src/em_cmu.c @@ -1377,14 +1377,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) /* frequencies above 32MHz */ if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE) { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | - CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ | + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | + CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ | /* Must have HFLE enabled to access some LE peripherals >=32MHz */ CMU_CTRL_HFLE; } else { /* This can happen if the user configures the EFM32_HFXO_FREQ to */ /* use another oscillator frequency */ - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; } #endif @@ -1475,7 +1475,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1); /* Enable DIV4 factor for peripheral clock */ - BITBAND_Peripheral(&(CMU->HFCORECLKDIV), + BITBAND_Peripheral(&(CMU->HFCORECLKDIV), _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1); } #endif diff --git a/bsp/efm32/Libraries/emlib/src/em_ebi.c b/bsp/efm32/Libraries/emlib/src/em_ebi.c index 8f8439e7fa..52ef36716b 100644 --- a/bsp/efm32/Libraries/emlib/src/em_ebi.c +++ b/bsp/efm32/Libraries/emlib/src/em_ebi.c @@ -105,7 +105,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT); ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT); ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT); - if ( ebiInit->enable) + if ( ebiInit->enable) { ctrl |= EBI_CTRL_BANK0EN; } @@ -117,13 +117,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) _EBI_CTRL_ARDY1EN_MASK| _EBI_CTRL_ARDYTO1DIS_MASK| _EBI_CTRL_NOIDLE1_MASK| - _EBI_CTRL_BANK1EN_MASK); + _EBI_CTRL_BANK1EN_MASK); ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT); ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT); ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT); ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT); ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT); - if ( ebiInit->enable) + if ( ebiInit->enable) { ctrl |= EBI_CTRL_BANK1EN; } @@ -141,7 +141,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT); ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT); ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT); - if ( ebiInit->enable) + if ( ebiInit->enable) { ctrl |= EBI_CTRL_BANK2EN; } @@ -153,13 +153,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) _EBI_CTRL_ARDY3EN_MASK| _EBI_CTRL_ARDYTO3DIS_MASK| _EBI_CTRL_NOIDLE3_MASK| - _EBI_CTRL_BANK3EN_MASK); + _EBI_CTRL_BANK3EN_MASK); ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT); ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT); ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT); ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT); ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT); - if ( ebiInit->enable) + if ( ebiInit->enable) { ctrl |= EBI_CTRL_BANK3EN; } @@ -172,7 +172,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) _EBI_CTRL_BANK1EN_MASK| _EBI_CTRL_BANK2EN_MASK| _EBI_CTRL_BANK3EN_MASK); - if ( ebiInit->enable) + if ( ebiInit->enable) { if ( ebiInit->banks & EBI_BANK0 ) { @@ -265,7 +265,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit) EBI_ChipSelectEnable(ebiInit->csLines, true); /* Activate new configuration */ - EBI->CTRL = ctrl; + EBI->CTRL = ctrl; } diff --git a/bsp/efm32/Libraries/emlib/src/em_emu.c b/bsp/efm32/Libraries/emlib/src/em_emu.c index fc8587636c..5df9fb577a 100644 --- a/bsp/efm32/Libraries/emlib/src/em_emu.c +++ b/bsp/efm32/Libraries/emlib/src/em_emu.c @@ -402,16 +402,16 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4init) _EMU_EM4CONF_OSC_MASK| _EMU_EM4CONF_BURTCWU_MASK| _EMU_EM4CONF_VREGEN_MASK); - + /* Configure new settings */ em4conf |= ( (em4init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)| (em4init->osc)| (em4init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)| (em4init->vreg << _EMU_EM4CONF_VREGEN_SHIFT)); - + /* Apply configuration. Note that lock can be set after this stage. */ - EMU->EM4CONF = em4conf; + EMU->EM4CONF = em4conf; } @@ -432,15 +432,15 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) _EMU_PWRCONF_VOUTSTRONG_MASK| _EMU_PWRCONF_VOUTMED_MASK| _EMU_PWRCONF_VOUTWEAK_MASK); - + reg |= (bupdInit->resistor| (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)| (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)| - (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT)); - + (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT)); + EMU->PWRCONF = reg; - /* Set backup domain inactive mode configuration */ + /* Set backup domain inactive mode configuration */ reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); reg |= (bupdInit->inactivePower); EMU->BUINACT = reg; @@ -456,14 +456,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) _EMU_BUCTRL_BODCAL_MASK| _EMU_BUCTRL_STATEN_MASK| _EMU_BUCTRL_EN_MASK); - - /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and + + /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and release reset */ reg |= (bupdInit->probe| (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)| (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)| (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT)); - + /* Enable configuration */ EMU->BUCTRL = reg; @@ -479,14 +479,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) * @brief * Configure Backup Power Domain BOD Threshold value * @note - * These values are precalibrated + * These values are precalibrated * @param[in] mode Active or Inactive mode * @param[in] value ******************************************************************************/ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) { EFM_ASSERT(value<4); - + switch(mode) { case emuBODMode_Active: @@ -503,7 +503,7 @@ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) * @brief * Configure Backup Power Domain BOD Threshold Range * @note - * These values are precalibrated + * These values are precalibrated * @param[in] mode Active or Inactive mode * @param[in] value ******************************************************************************/ diff --git a/bsp/efm32/Libraries/emlib/src/em_lesense.c b/bsp/efm32/Libraries/emlib/src/em_lesense.c index 8dc9c1ec7d..4482b20cce 100644 --- a/bsp/efm32/Libraries/emlib/src/em_lesense.c +++ b/bsp/efm32/Libraries/emlib/src/em_lesense.c @@ -533,7 +533,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, /* Channel specific configuration of clocks, sample mode, excitation pin mode * alternate excitation usage and interrupt mode on scan channel chIdx in * LESENSE_CHchIdx_INTERACT. */ - LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk << + LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk << _LESENSE_CH_INTERACT_EXCLK_SHIFT) | ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT) | diff --git a/bsp/efm32/Libraries/emlib/src/em_msc.c b/bsp/efm32/Libraries/emlib/src/em_msc.c index f42811219e..47f01e6168 100644 --- a/bsp/efm32/Libraries/emlib/src/em_msc.c +++ b/bsp/efm32/Libraries/emlib/src/em_msc.c @@ -55,7 +55,7 @@ * @brief * Enables the flash controller for writing. * @note - * IMPORTANT: This function must be called before flash operations when + * IMPORTANT: This function must be called before flash operations when * AUXHFRCO clock has been changed from default 14MHz band. ******************************************************************************/ void MSC_Init(void) diff --git a/bsp/efm32/Libraries/emlib/src/em_opamp.c b/bsp/efm32/Libraries/emlib/src/em_opamp.c index f12551430f..c44ab9c4a6 100644 --- a/bsp/efm32/Libraries/emlib/src/em_opamp.c +++ b/bsp/efm32/Libraries/emlib/src/em_opamp.c @@ -243,7 +243,7 @@ void OPAMP_Disable( DAC_TypeDef *dac, OPAMP_TypeDef opa ) void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init ) { uint32_t offset; - + EFM_ASSERT( DAC_REF_VALID( dac ) ); EFM_ASSERT( DAC_OPA_VALID( opa ) ); EFM_ASSERT( init->bias <= ( _DAC_BIASPROG_BIASPROG_MASK >> @@ -267,13 +267,13 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef } else { - EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >> + EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >> _DAC_CAL_CH0OFFSET_SHIFT ) ); - + dac->CAL = ( dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK ) | - ( init->offset << _DAC_CAL_CH0OFFSET_SHIFT ); + ( init->offset << _DAC_CAL_CH0OFFSET_SHIFT ); } - + dac->OPA0MUX = (uint32_t)init->resSel | (uint32_t)init->outMode | init->outPen | @@ -315,11 +315,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef } else { - EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >> + EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >> _DAC_CAL_CH1OFFSET_SHIFT ) ); - + dac->CAL = ( dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK ) | - ( init->offset << _DAC_CAL_CH1OFFSET_SHIFT ); + ( init->offset << _DAC_CAL_CH1OFFSET_SHIFT ); } dac->OPA1MUX = (uint32_t)init->resSel | @@ -370,11 +370,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef } else { - EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >> + EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT ) ); - + dac->CAL = ( dac->CAL & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK ) | - ( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT ); + ( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT ); } dac->OPA2MUX = (uint32_t)init->resSel | diff --git a/bsp/efm32/Libraries/emlib/src/em_rmu.c b/bsp/efm32/Libraries/emlib/src/em_rmu.c index 93da92dee0..8a45d668cf 100644 --- a/bsp/efm32/Libraries/emlib/src/em_rmu.c +++ b/bsp/efm32/Libraries/emlib/src/em_rmu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Reset Management Unit (RMU) peripheral module peripheral API - * + * * @author Energy Micro AS * @version 3.0.0 ******************************************************************************* diff --git a/bsp/efm32/Libraries/emlib/src/em_timer.c b/bsp/efm32/Libraries/emlib/src/em_timer.c index b7d8c8930e..cdca54573f 100644 --- a/bsp/efm32/Libraries/emlib/src/em_timer.c +++ b/bsp/efm32/Libraries/emlib/src/em_timer.c @@ -136,7 +136,7 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) { timer->CMD = TIMER_CMD_STOP; } - + /* Reset counter */ timer->CNT = _TIMER_CNT_RESETVALUE; diff --git a/bsp/efm32/Libraries/emlib/src/em_usart.c b/bsp/efm32/Libraries/emlib/src/em_usart.c index d33fe9e30c..33a944f216 100644 --- a/bsp/efm32/Libraries/emlib/src/em_usart.c +++ b/bsp/efm32/Libraries/emlib/src/em_usart.c @@ -82,7 +82,7 @@ #endif #if (UART_COUNT == 1) -#define UART_REF_VALID(ref) ((ref)==UART0) +#define UART_REF_VALID(ref) ((ref)==UART0) #elif (UART_COUNT == 2) #define UART_REF_VALID(ref) (((ref)==UART0) || ((ref)==UART1)) #else @@ -733,8 +733,8 @@ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) * @brief * Initialize automatic transmissions using PRS channel as trigger * @note - * Initialize USART with USART_Init() before setting up PRS configuration - * + * Initialize USART with USART_Init() before setting up PRS configuration + * * @param[in] usart Pointer to USART to configure * @param[in] init Pointer to initialization structure ******************************************************************************/ diff --git a/bsp/efm32/Libraries/emlib/src/em_vcmp.c b/bsp/efm32/Libraries/emlib/src/em_vcmp.c index 6a83a22ae8..2e0d33da03 100644 --- a/bsp/efm32/Libraries/emlib/src/em_vcmp.c +++ b/bsp/efm32/Libraries/emlib/src/em_vcmp.c @@ -133,7 +133,7 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit) while(!VCMP_Ready()); VCMP_LowPowerRefSet(vcmpInit->lowPowerRef); } - + /* Clear edge interrupt */ VCMP_IntClear(VCMP_IF_EDGE); } diff --git a/bsp/efm32/board.c b/bsp/efm32/board.c index cdd44767f1..ea8b0640d2 100644 --- a/bsp/efm32/board.c +++ b/bsp/efm32/board.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file board.c - * @brief Board support of RT-Thread RTOS for EFM32 + * @file board.c + * @brief Board support of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,12 +10,12 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2010-12-21 onelife Initial creation for EFM32 - * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support - * 2011-07-12 onelife Add SWO output enable function - * 2011-12-08 onelife Add giant gecko development kit support - * 2011-12-09 onelife Add giant gecko support + * Date Author Notes + * 2010-12-21 onelife Initial creation for EFM32 + * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support + * 2011-07-12 onelife Add SWO output enable function + * 2011-12-08 onelife Add giant gecko development kit support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add LEUART module support * 2011-12-14 onelife Add LFXO enabling routine in driver initialization * function @@ -37,19 +37,19 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \ - ((VECTTAB) == FLASH_MEM_BASE)) -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \ + ((VECTTAB) == FLASH_MEM_BASE)) +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /***************************************************************************//** * @addtogroup SysTick_clock_source * @{ ******************************************************************************/ #define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004) -#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000) -#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \ - ((SOURCE) == SysTick_CLKSource_HFCORECLK)) +#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000) +#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \ + ((SOURCE) == SysTick_CLKSource_HFCORECLK)) /***************************************************************************//** * @} ******************************************************************************/ @@ -67,20 +67,20 @@ * @note * * @param[in] NVIC_VectTab - * Indicate the vector table is allocated in RAM or ROM + * Indicate the vector table is allocated in RAM or ROM * * @param[in] Offset * The vector table offset ******************************************************************************/ static void NVIC_SetVectorTable( - rt_uint32_t NVIC_VectTab, - rt_uint32_t Offset) + rt_uint32_t NVIC_VectTab, + rt_uint32_t Offset) { - /* Check the parameters */ - RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab)); - RT_ASSERT(IS_NVIC_OFFSET(Offset)); + /* Check the parameters */ + RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab)); + RT_ASSERT(IS_NVIC_OFFSET(Offset)); - SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80); + SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80); } /***************************************************************************//** @@ -95,19 +95,19 @@ static void NVIC_SetVectorTable( static void NVIC_Configuration(void) { #ifdef VECT_TAB_RAM - /* Set the vector table allocated at 0x20000000 */ - NVIC_SetVectorTable(RAM_MEM_BASE, 0x0); + /* Set the vector table allocated at 0x20000000 */ + NVIC_SetVectorTable(RAM_MEM_BASE, 0x0); #else /* VECT_TAB_FLASH */ - /* Set the vector table allocated at 0x00000000 */ - NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0); + /* Set the vector table allocated at 0x00000000 */ + NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0); #endif - /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for - subpriority */ - NVIC_SetPriorityGrouping(0x7UL); + /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for + subpriority */ + NVIC_SetPriorityGrouping(0x7UL); - /* Set Base Priority Mask Register */ - __set_BASEPRI(EFM32_BASE_PRI_DEFAULT); + /* Set Base Priority Mask Register */ + __set_BASEPRI(EFM32_BASE_PRI_DEFAULT); } /***************************************************************************//** @@ -119,13 +119,13 @@ static void NVIC_Configuration(void) * @note * * @param[in] SysTick_CLKSource - * Specifies the SysTick clock source. + * Specifies the SysTick clock source. * * @arg SysTick_CLKSource_HCLK_Div8 - * AHB clock divided by 8 selected as SysTick clock source. + * AHB clock divided by 8 selected as SysTick clock source. * * @arg SysTick_CLKSource_HCLK - * AHB clock selected as SysTick clock source. + * AHB clock selected as SysTick clock source. ******************************************************************************/ static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource) { @@ -184,14 +184,14 @@ static void SysTick_Configuration(void) /* Start LETIMER0 */ LETIMER_Init(LETIMER0, &letimerInit); #else - rt_uint32_t coreClk; - rt_uint32_t cnts; + rt_uint32_t coreClk; + rt_uint32_t cnts; - coreClk = SystemCoreClockGet(); - cnts = coreClk / RT_TICK_PER_SECOND; + coreClk = SystemCoreClockGet(); + cnts = coreClk / RT_TICK_PER_SECOND; - SysTick_Config(cnts); - SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK); + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK); #endif } @@ -206,9 +206,9 @@ static void SysTick_Configuration(void) ******************************************************************************/ void Swo_Configuration(void) { - rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000; - rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010; - rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0; + rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000; + rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010; + rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0; CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; /* Enable Serial wire output pin */ @@ -258,12 +258,12 @@ void Swo_Configuration(void) ******************************************************************************/ void rt_hw_board_init(void) { - /* Chip errata */ - CHIP_Init(); + /* Chip errata */ + CHIP_Init(); /* Initialize DVK board register access */ #if defined(EFM32_GXXX_DK) - DVK_init(); + DVK_init(); #elif defined(EFM32GG_DK3750) DVK_init(DVK_Init_EBI); @@ -272,12 +272,12 @@ void rt_hw_board_init(void) DVK_clearInterruptFlags(BC_INTFLAG_MASK); #endif - /* config NVIC Configuration */ - NVIC_Configuration(); + /* config NVIC Configuration */ + NVIC_Configuration(); #if defined(EFM32_USING_HFXO) - /* Configure external oscillator */ - SystemHFXOClockSet(EFM32_HFXO_FREQUENCY); + /* Configure external oscillator */ + SystemHFXOClockSet(EFM32_HFXO_FREQUENCY); /* Switching the CPU clock source to HFXO */ CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); @@ -293,15 +293,15 @@ void rt_hw_board_init(void) #if defined(EFM32_SWO_ENABLE) /* Enable SWO */ - Swo_Configuration(); + Swo_Configuration(); #endif - /* Enable high frequency peripheral clock */ - CMU_ClockEnable(cmuClock_HFPER, true); - /* Enabling clock to the interface of the low energy modules */ - CMU_ClockEnable(cmuClock_CORELE, true); + /* Enable high frequency peripheral clock */ + CMU_ClockEnable(cmuClock_HFPER, true); + /* Enabling clock to the interface of the low energy modules */ + CMU_ClockEnable(cmuClock_CORELE, true); /* Enable GPIO clock */ - CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(cmuClock_GPIO, true); /* Configure the SysTick */ SysTick_Configuration(); @@ -318,8 +318,8 @@ void rt_hw_board_init(void) ******************************************************************************/ void rt_hw_driver_init(void) { - /* Initialize DMA */ - rt_hw_dma_init(); + /* Initialize DMA */ + rt_hw_dma_init(); /* Select LFXO for specified module (and wait for it to stabilize) */ #if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC)) @@ -331,11 +331,11 @@ void rt_hw_driver_init(void) #error "Low frequency clock source is needed for using LEUART" #endif - /* Initialize USART */ + /* Initialize USART */ #if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \ defined(RT_USING_USART2) || defined(RT_USING_UART0) || \ defined(RT_USING_UART1)) - rt_hw_usart_init(); + rt_hw_usart_init(); #endif /* Initialize LEUART */ @@ -343,7 +343,7 @@ void rt_hw_driver_init(void) rt_hw_leuart_init(); #endif - /* Setup Console */ + /* Setup Console */ #if defined(EFM32_GXXX_DK) DVK_enablePeripheral(DVK_RS232A); DVK_enablePeripheral(DVK_SPI); @@ -354,31 +354,31 @@ void rt_hw_driver_init(void) DVK_enablePeripheral(DVK_RS232_LEUART); #endif #endif - rt_console_set_device(CONSOLE_DEVICE); + rt_console_set_device(CONSOLE_DEVICE); - /* Initialize Timer */ + /* Initialize Timer */ #if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2)) - rt_hw_timer_init(); + rt_hw_timer_init(); #endif - /* Initialize ADC */ + /* Initialize ADC */ #if defined(RT_USING_ADC0) - rt_hw_adc_init(); + rt_hw_adc_init(); #endif - /* Initialize ACMP */ + /* Initialize ACMP */ #if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1)) - rt_hw_acmp_init(); + rt_hw_acmp_init(); #endif - /* Initialize IIC */ + /* Initialize IIC */ #if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1)) - rt_hw_iic_init(); + rt_hw_iic_init(); #endif - /* Initialize RTC */ + /* Initialize RTC */ #if defined(RT_USING_RTC) - rt_hw_rtc_init(); + rt_hw_rtc_init(); #endif /* Enable SPI access to MicroSD card */ diff --git a/bsp/efm32/board.h b/bsp/efm32/board.h index a97b0d9bc0..b92e10194b 100644 --- a/bsp/efm32/board.h +++ b/bsp/efm32/board.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file board.h - * @brief Board support of RT-Thread RTOS for EFM32 + * @file board.h + * @brief Board support of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,18 +10,18 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2010-12-21 onelife Initial creation for EFM32 - * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support - * 2011-07-12 onelife Add prototype for SWO output enable and interrupt + * Date Author Notes + * 2010-12-21 onelife Initial creation for EFM32 + * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support + * 2011-07-12 onelife Add prototype for SWO output enable and interrupt * context check functions - * 2011-12-08 onelife Add giant gecko development kit support - * 2011-12-09 onelife Add giant gecko support + * 2011-12-08 onelife Add giant gecko development kit support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add LEUART module support * 2011-12-14 onelife Add LFXO enabling routine in driver initialization * function * 2011-12-20 onelife Move SPI Auto-CS setting to "rtconfig.h" - * 2012-05-15 onelife Modified to compatible with CMSIS v3 + * 2012-05-15 onelife Modified to compatible with CMSIS v3 ******************************************************************************/ #ifndef __BOARD_H__ #define __BOARD_H__ @@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status; #define EFM32_SWO_ENABLE #endif -#define EFM32_NO_DATA (0) -#define EFM32_NO_POINTER (RT_NULL) -#define EFM32_NO_OFFSET (-1) -#define EFM32_NO_DMA (-1) +#define EFM32_NO_DATA (0) +#define EFM32_NO_POINTER (RT_NULL) +#define EFM32_NO_OFFSET (-1) +#define EFM32_NO_DMA (-1) /* SECTION: SPI Flash */ #if defined(EFM32_USING_SFLASH) -#define SFLASH_CS_PORT (gpioPortC) -#define SFLASH_CS_PIN (8) +#define SFLASH_CS_PORT (gpioPortC) +#define SFLASH_CS_PIN (8) #endif /* SECTION: Micro SD */ @@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: SYSTEM */ -#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE) -#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5) -#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5) +#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE) +#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5) +#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5) /* SECTION: CLOCK */ #define EFM32_USING_HFXO @@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status; #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK)) #define EFM32_HFXO_FREQUENCY (32000000) #elif defined(EFM32GG_DK3750) - #define EFM32_HFXO_FREQUENCY (48000000) + #define EFM32_HFXO_FREQUENCY (48000000) #else - #define EFM32_HFXO_FREQUENCY (00000000) + #define EFM32_HFXO_FREQUENCY (00000000) #endif #endif #if defined(EFM32_USING_LFXO) @@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: USART */ -#define USART_RX_BUFFER_SIZE (64) -#define LEUART_RX_BUFFER_SIZE (64) +#define USART_RX_BUFFER_SIZE (64) +#define LEUART_RX_BUFFER_SIZE (64) /* Location count (start from 0) */ #if defined(_EFM32_GECKO_FAMILY) #define EFM32_USART_LOCATION_COUNT (3) @@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SUBSECTION: UART */ -#define UART_BAUDRATE (115200) +#define UART_BAUDRATE (115200) /* SUBSECTION: SPI */ /* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */ -#define SPI_BAUDRATE (4000000) +#define SPI_BAUDRATE (4000000) /* SECTION: I2C */ -#define IIC_RX_BUFFER_SIZE (32) +#define IIC_RX_BUFFER_SIZE (32) #if defined(_EFM32_GECKO_FAMILY) #define EFM32_IIC_LOCATION_COUNT (4) #elif defined(_EFM32_GIANT_FAMILY) @@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status; #endif /* SECTION: ADC */ -#define ADC_CALI_REF (adcRef2V5) -#define ADC_CALI_CH (adcSingleInpCh5) -#define ADC_CONVERT_FREQUENCY (7000000) +#define ADC_CALI_REF (adcRef2V5) +#define ADC_CALI_CH (adcSingleInpCh5) +#define ADC_CONVERT_FREQUENCY (7000000) #if (RT_CONSOLE_DEVICE == EFM_USART0) -#define CONSOLE_DEVICE RT_USART0_NAME +#define CONSOLE_DEVICE RT_USART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_USART1) -#define CONSOLE_DEVICE RT_USART1_NAME +#define CONSOLE_DEVICE RT_USART1_NAME #elif (RT_CONSOLE_DEVICE == EFM_USART2) -#define CONSOLE_DEVICE RT_USART2_NAME +#define CONSOLE_DEVICE RT_USART2_NAME #elif (RT_CONSOLE_DEVICE == EFM_UART0) -#define CONSOLE_DEVICE RT_UART0_NAME +#define CONSOLE_DEVICE RT_UART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_UART1) -#define CONSOLE_DEVICE RT_UART1_NAME +#define CONSOLE_DEVICE RT_UART1_NAME #elif (RT_CONSOLE_DEVICE == EFM_LEUART0) -#define CONSOLE_DEVICE RT_LEUART0_NAME +#define CONSOLE_DEVICE RT_LEUART0_NAME #elif (RT_CONSOLE_DEVICE == EFM_LEUART1) -#define CONSOLE_DEVICE RT_LEUART1_NAME +#define CONSOLE_DEVICE RT_LEUART1_NAME #else -#define CONSOLE_DEVICE "NONE" +#define CONSOLE_DEVICE "NONE" #endif /* The following defines should be consistent with those in diskio.h */ -#define CTRL_SYNC 0 -#define GET_SECTOR_COUNT 1 -#define GET_SECTOR_SIZE 2 -#define GET_BLOCK_SIZE 3 -#define MMC_GET_TYPE 10 -#define MMC_GET_CSD 11 -#define MMC_GET_CID 12 -#define MMC_GET_OCR 13 -#define MMC_GET_SDSTAT 14 +#define CTRL_SYNC 0 +#define GET_SECTOR_COUNT 1 +#define GET_SECTOR_SIZE 2 +#define GET_BLOCK_SIZE 3 +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 /* The above defines should be consistent with those in diskio.h */ /* I/O control options */ -#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC -#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT -#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE -#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE -#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE -#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD -#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID -#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR -#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT +#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC +#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT +#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE +#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE +#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE +#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD +#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID +#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR +#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT /*! fixme: move the following define to Rtdef.h */ -#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */ -#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */ -#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */ -#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */ -#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */ -#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */ -#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */ -#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */ +#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */ +#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */ +#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */ +#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */ +#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */ +#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */ +#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */ +#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */ /* Exported functions ------------------------------------------------------- */ void rt_hw_board_init(void); diff --git a/bsp/efm32/dev_accel.c b/bsp/efm32/dev_accel.c index fb2c05174b..07fcc25ded 100644 --- a/bsp/efm32/dev_accel.c +++ b/bsp/efm32/dev_accel.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_accel.c - * @brief Accelerometer driver of RT-Thread RTOS for EFM32 + * @file dev_accel.c + * @brief Accelerometer driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,10 +10,10 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-13 onelife Initial creation for using EFM32 ADC module to + * Date Author Notes + * 2011-07-13 onelife Initial creation for using EFM32 ADC module to * interface the Freescale MMA7361L - * 2011-08-02 onelife Add digital interface support of using EFM32 IIC + * 2011-08-02 onelife Add digital interface support of using EFM32 IIC * module for the Freescale MMA7455L ******************************************************************************/ @@ -38,23 +38,23 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_ACCEL_DEBUG -#define accel_debug(format,args...) rt_kprintf(format, ##args) +#define accel_debug(format,args...) rt_kprintf(format, ##args) #else #define accel_debug(format,args...) #endif /* Private constants ---------------------------------------------------------*/ -static rt_device_t accel; +static rt_device_t accel; #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) -static struct efm32_adc_control_t control = \ - {ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}}; -static struct efm32_accel_result_t accelOffset = {0}; +static struct efm32_adc_control_t control = \ + {ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}}; +static struct efm32_accel_result_t accelOffset = {0}; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -static const struct efm32_iic_control_t control = \ - {IIC_STATE_MASTER, 0x0000}; +static const struct efm32_iic_control_t control = \ + {IIC_STATE_MASTER, 0x0000}; #endif -static rt_bool_t accelInTime = true; -static rt_uint32_t accelConfig = 0; +static rt_bool_t accelInTime = true; +static rt_uint32_t accelConfig = 0; /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -68,99 +68,99 @@ static rt_uint32_t accelConfig = 0; * @note * * @param[out] data - * Pointer to output buffer + * Pointer to output buffer * * @param[in] lowResolution - * Resolution selection + * Resolution selection * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, - rt_bool_t lowResolution) + rt_bool_t lowResolution) { - RT_ASSERT(accel != RT_NULL); + RT_ASSERT(accel != RT_NULL); - rt_err_t ret; + rt_err_t ret; - if (data == RT_NULL) - { - return -RT_ERROR; - } + if (data == RT_NULL) + { + return -RT_ERROR; + } - ret = RT_EOK; - do - { - /* --------- ADC interface --------- */ + ret = RT_EOK; + do + { + /* --------- ADC interface --------- */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - struct efm32_adc_result_t result; + struct efm32_adc_result_t result; - result.mode = control.mode; - result.buffer = (void *)data; - if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME, - (void *)&result)) != RT_EOK) - { - break; - } - if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \ - (void *)&result)) != RT_EOK) - { - break; - } + result.mode = control.mode; + result.buffer = (void *)data; + if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME, + (void *)&result)) != RT_EOK) + { + break; + } + if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \ + (void *)&result)) != RT_EOK) + { + break; + } - data->x += accelOffset.x - 0x800; - data->y += accelOffset.y - 0x800; - data->z += accelOffset.z - 0x800; - if (lowResolution) - { - data->x >>= 4; - data->y >>= 4; - data->z >>= 4; - } + data->x += accelOffset.x - 0x800; + data->y += accelOffset.y - 0x800; + data->z += accelOffset.z - 0x800; + if (lowResolution) + { + data->x >>= 4; + data->y >>= 4; + data->z >>= 4; + } - /* --------- IIC interface --------- */ + /* --------- IIC interface --------- */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - if (lowResolution || \ - ((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G)) - { - rt_int8_t buf[3]; + if (lowResolution || \ + ((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G)) + { + rt_int8_t buf[3]; - buf[0] = XOUT8; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ - sizeof(buf)) == 0) - { - ret = -RT_ERROR; - break; - } - data->x = buf[0]; - data->y = buf[1]; - data->z = buf[2]; - } - else - { - rt_uint8_t buf[6]; - rt_uint16_t *temp = (rt_uint16_t *)&buf; + buf[0] = XOUT8; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ + sizeof(buf)) == 0) + { + ret = -RT_ERROR; + break; + } + data->x = buf[0]; + data->y = buf[1]; + data->z = buf[2]; + } + else + { + rt_uint8_t buf[6]; + rt_uint16_t *temp = (rt_uint16_t *)&buf; - buf[0] = XOUTL; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ - sizeof(buf)) == 0) - { - ret = -RT_ERROR; - break; - } - data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ - ((rt_uint32_t)*temp & 0x3FF); - } + buf[0] = XOUTL; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \ + sizeof(buf)) == 0) + { + ret = -RT_ERROR; + break; + } + data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \ + ((rt_uint32_t)*temp & 0x3FF); + } #endif - return RT_EOK; - } while (0); + return RT_EOK; + } while (0); - accel_debug("Accel err: Get data failed!\n"); - return ret; + accel_debug("Accel err: Get data failed!\n"); + return ret; } /***************************************************************************//** @@ -172,357 +172,357 @@ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, * @note * * @param[in] parameter - * Parameter + * Parameter ******************************************************************************/ static void efm_accel_timer(void* parameter) { - accelInTime = false; + accelInTime = false; } #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) /***************************************************************************//** * @brief - * Accelerometer level and pulse detection interrupts handler + * Accelerometer level and pulse detection interrupts handler * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ static void efm_accel_isr(rt_device_t device) { - rt_uint8_t buf[2]; + rt_uint8_t buf[2]; - if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT) - { - /* Read detection source */ - buf[0] = DETSRC; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) - { - accel_debug("Accel: read error\n"); - return; - } - accel_debug("Accel: DETSRC %x\n", buf[0]); + if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT) + { + /* Read detection source */ + buf[0] = DETSRC; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) + { + accel_debug("Accel: read error\n"); + return; + } + accel_debug("Accel: DETSRC %x\n", buf[0]); - /* Reset the interrupt flags: Part 1 */ - buf[0] = INTRST; - buf[1] = INTRST_INT_1 | INTRST_INT_2; - accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); + /* Reset the interrupt flags: Part 1 */ + buf[0] = INTRST; + buf[1] = INTRST_INT_1 | INTRST_INT_2; + accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); - /* Read status to waste some time */ - buf[0] = STATUS; - if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) - { - accel_debug("Accel: read error\n"); - return; - } - accel_debug("Accel: STATUS %x\n", buf[0]); + /* Read status to waste some time */ + buf[0] = STATUS; + if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1) + { + accel_debug("Accel: read error\n"); + return; + } + accel_debug("Accel: STATUS %x\n", buf[0]); - /* Reset the interrupt flags: Part 2 */ - buf[0] = INTRST; - buf[1] = 0x00; - accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); - } + /* Reset the interrupt flags: Part 2 */ + buf[0] = INTRST; + buf[1] = 0x00; + accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2); + } } /***************************************************************************//** * @brief - * Accelerometer configuration function + * Accelerometer configuration function * * @details * * @note * * @param[in] config - * Configuration options + * Configuration options * * @param[in] level_threshold - * Level detection threshold + * Level detection threshold * * @param[in] pulse_threshold - * Pulse detection threshold + * Pulse detection threshold * * @param[in] pulse_duration - * Time window for 1st pulse + * Time window for 1st pulse * * @param[in] pulse_latency - * Pulse latency Time + * Pulse latency Time * * @param[in] pulse_duration2 - * Time window for 2nd pulse + * Time window for 2nd pulse * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_config(rt_uint32_t config, - rt_uint8_t level_threshold, - rt_uint8_t pulse_threshold, - rt_uint8_t pulse_duration, - rt_uint8_t pulse_latency, - rt_uint8_t pulse_duration2) + rt_uint8_t level_threshold, + rt_uint8_t pulse_threshold, + rt_uint8_t pulse_duration, + rt_uint8_t pulse_latency, + rt_uint8_t pulse_duration2) { - rt_err_t ret; - rt_uint8_t buf[2]; - rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg; + rt_err_t ret; + rt_uint8_t buf[2]; + rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg; - ret = RT_EOK; - mctl_reg = 0; - ctl1_reg = 0; - ctl2_reg = 0; + ret = RT_EOK; + mctl_reg = 0; + ctl1_reg = 0; + ctl2_reg = 0; - /* Modify MCTL */ - mode = config & ACCEL_MASK_MODE; - switch (mode) - { - case ACCEL_MODE_STANDBY: - mctl_reg |= MCTL_MODE_STANDBY; - break; - case ACCEL_MODE_MEASUREMENT: - mctl_reg |= MCTL_MODE_MEASUREMENT; - break; - case ACCEL_MODE_LEVEL: - mctl_reg |= MCTL_MODE_LEVEL; - break; - case ACCEL_MODE_PULSE: - mctl_reg |= MCTL_MODE_PULSE; - break; - default: - return -RT_ERROR; - } + /* Modify MCTL */ + mode = config & ACCEL_MASK_MODE; + switch (mode) + { + case ACCEL_MODE_STANDBY: + mctl_reg |= MCTL_MODE_STANDBY; + break; + case ACCEL_MODE_MEASUREMENT: + mctl_reg |= MCTL_MODE_MEASUREMENT; + break; + case ACCEL_MODE_LEVEL: + mctl_reg |= MCTL_MODE_LEVEL; + break; + case ACCEL_MODE_PULSE: + mctl_reg |= MCTL_MODE_PULSE; + break; + default: + return -RT_ERROR; + } - switch (config & ACCEL_MASK_RANGE) - { - case ACCEL_RANGE_8G: - mctl_reg |= MCTL_RANGE_8G; - break; - case ACCEL_RANGE_4G: - mctl_reg |= MCTL_RANGE_4G; - break; - case ACCEL_RANGE_2G: - mctl_reg |= MCTL_RANGE_2G; - break; - default: - return -RT_ERROR; - } + switch (config & ACCEL_MASK_RANGE) + { + case ACCEL_RANGE_8G: + mctl_reg |= MCTL_RANGE_8G; + break; + case ACCEL_RANGE_4G: + mctl_reg |= MCTL_RANGE_4G; + break; + case ACCEL_RANGE_2G: + mctl_reg |= MCTL_RANGE_2G; + break; + default: + return -RT_ERROR; + } - if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) - { - mctl_reg |= MCTL_PIN_INT1; - } + if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) + { + mctl_reg |= MCTL_PIN_INT1; + } - /* Modify CTL1 */ - if (config & ACCEL_INTPIN_INVERSE) - { - ctl1_reg |= CTL1_INTPIN_INVERSE; - } + /* Modify CTL1 */ + if (config & ACCEL_INTPIN_INVERSE) + { + ctl1_reg |= CTL1_INTPIN_INVERSE; + } - switch (config & ACCEL_MASK_INT) - { - case ACCEL_INT_LEVEL_PULSE: - ctl1_reg |= CTL1_INT_LEVEL_PULSE; - break; - case ACCEL_INT_PULSE_LEVEL: - ctl1_reg |= CTL1_INT_PULSE_LEVEL; - break; - case ACCEL_INT_SINGLE_DOUBLE: - ctl1_reg |= CTL1_INT_SINGLE_DOUBLE; - break; - default: - break; - } + switch (config & ACCEL_MASK_INT) + { + case ACCEL_INT_LEVEL_PULSE: + ctl1_reg |= CTL1_INT_LEVEL_PULSE; + break; + case ACCEL_INT_PULSE_LEVEL: + ctl1_reg |= CTL1_INT_PULSE_LEVEL; + break; + case ACCEL_INT_SINGLE_DOUBLE: + ctl1_reg |= CTL1_INT_SINGLE_DOUBLE; + break; + default: + break; + } - switch (config & ACCEL_MASK_DISABLE) - { - case ACCEL_DISABLE_X: - ctl1_reg |= CTL1_X_DISABLE; - break; - case ACCEL_DISABLE_Y: - ctl1_reg |= CTL1_Y_DISABLE; - break; - case ACCEL_DISABLE_Z: - ctl1_reg |= CTL1_Z_DISABLE; - break; - default: - break; - } + switch (config & ACCEL_MASK_DISABLE) + { + case ACCEL_DISABLE_X: + ctl1_reg |= CTL1_X_DISABLE; + break; + case ACCEL_DISABLE_Y: + ctl1_reg |= CTL1_Y_DISABLE; + break; + case ACCEL_DISABLE_Z: + ctl1_reg |= CTL1_Z_DISABLE; + break; + default: + break; + } - if (config & ACCEL_THRESHOLD_INTEGER) - { - ctl1_reg |= CTL1_THRESHOLD_INTEGER; - } + if (config & ACCEL_THRESHOLD_INTEGER) + { + ctl1_reg |= CTL1_THRESHOLD_INTEGER; + } - if (config & ACCEL_BANDWIDTH_125HZ) - { - ctl1_reg |= CTL1_BANDWIDTH_125HZ; - } + if (config & ACCEL_BANDWIDTH_125HZ) + { + ctl1_reg |= CTL1_BANDWIDTH_125HZ; + } - /* Modify CTL2 */ - if (config & ACCEL_LEVEL_AND) - { - ctl2_reg |= CTL2_LEVEL_AND; - } - if (config & ACCEL_PULSE_AND) - { - ctl2_reg |= CTL2_PULSE_AND; - } - if (config & ACCEL_DRIVE_STRONG) - { - ctl2_reg |= CTL2_DRIVE_STRONG; - } + /* Modify CTL2 */ + if (config & ACCEL_LEVEL_AND) + { + ctl2_reg |= CTL2_LEVEL_AND; + } + if (config & ACCEL_PULSE_AND) + { + ctl2_reg |= CTL2_PULSE_AND; + } + if (config & ACCEL_DRIVE_STRONG) + { + ctl2_reg |= CTL2_DRIVE_STRONG; + } - do - { - /* Write registers */ - buf[0] = MCTL; - buf[1] = mctl_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: MCTL %x\n", mctl_reg); + do + { + /* Write registers */ + buf[0] = MCTL; + buf[1] = mctl_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: MCTL %x\n", mctl_reg); - buf[0] = CTL1; - buf[1] = ctl1_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: CTL1 %x\n", ctl1_reg); + buf[0] = CTL1; + buf[1] = ctl1_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: CTL1 %x\n", ctl1_reg); - buf[0] = CTL2; - buf[1] = ctl2_reg; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: CTL2 %x\n", ctl2_reg); - accelConfig = config; + buf[0] = CTL2; + buf[1] = ctl2_reg; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: CTL2 %x\n", ctl2_reg); + accelConfig = config; - if (mode == ACCEL_MODE_PULSE) - { - buf[0] = PDTH; - buf[1] = pulse_threshold; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: PDTH %x\n", buf[1]); + if (mode == ACCEL_MODE_PULSE) + { + buf[0] = PDTH; + buf[1] = pulse_threshold; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: PDTH %x\n", buf[1]); - buf[0] = PW; - buf[1] = pulse_duration; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: PW %x\n", buf[1]); + buf[0] = PW; + buf[1] = pulse_duration; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: PW %x\n", buf[1]); - buf[0] = LT; - buf[1] = pulse_latency; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: LT %x\n", buf[1]); + buf[0] = LT; + buf[1] = pulse_latency; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: LT %x\n", buf[1]); - buf[0] = TW; - buf[1] = pulse_duration2; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: TW %x\n", buf[1]); - } + buf[0] = TW; + buf[1] = pulse_duration2; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: TW %x\n", buf[1]); + } - if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) - { - efm32_irq_hook_init_t hook; + if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE)) + { + efm32_irq_hook_init_t hook; - /* Reset the interrupt flags: Part 1 */ - buf[0] = INTRST; - buf[1] = INTRST_INT_1 | INTRST_INT_2; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } + /* Reset the interrupt flags: Part 1 */ + buf[0] = INTRST; + buf[1] = INTRST_INT_1 | INTRST_INT_2; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } - /* Set level detection threshold */ - buf[0] = LDTH; - if (config & ACCEL_THRESHOLD_INTEGER) - { - buf[1] = level_threshold; - } - else - { - buf[1] = level_threshold & 0x7f; - } - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - accel_debug("Accel: LDTH %x\n", buf[1]); + /* Set level detection threshold */ + buf[0] = LDTH; + if (config & ACCEL_THRESHOLD_INTEGER) + { + buf[1] = level_threshold; + } + else + { + buf[1] = level_threshold & 0x7f; + } + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + accel_debug("Accel: LDTH %x\n", buf[1]); - /* Config interrupt */ - hook.type = efm32_irq_type_gpio; - hook.unit = ACCEL_INT1_PIN; - hook.cbFunc = efm_accel_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); - hook.unit = ACCEL_INT2_PIN; - efm32_irq_hook_register(&hook); - /* Clear pending interrupt */ - BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL); - BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL); - /* Set raising edge interrupt and clear/enable it */ - GPIO_IntConfig( - ACCEL_INT1_PORT, - ACCEL_INT1_PIN, - true, - false, - true); - GPIO_IntConfig( - ACCEL_INT2_PORT, - ACCEL_INT2_PIN, - true, - false, - true); - if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ - ((rt_uint8_t)ACCEL_INT2_PORT % 2)) - { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ - !((rt_uint8_t)ACCEL_INT2_PORT % 2)) - { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } + /* Config interrupt */ + hook.type = efm32_irq_type_gpio; + hook.unit = ACCEL_INT1_PIN; + hook.cbFunc = efm_accel_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); + hook.unit = ACCEL_INT2_PIN; + efm32_irq_hook_register(&hook); + /* Clear pending interrupt */ + BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL); + BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL); + /* Set raising edge interrupt and clear/enable it */ + GPIO_IntConfig( + ACCEL_INT1_PORT, + ACCEL_INT1_PIN, + true, + false, + true); + GPIO_IntConfig( + ACCEL_INT2_PORT, + ACCEL_INT2_PIN, + true, + false, + true); + if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ + ((rt_uint8_t)ACCEL_INT2_PORT % 2)) + { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \ + !((rt_uint8_t)ACCEL_INT2_PORT % 2)) + { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } - /* Reset the interrupt flags: Part 2 */ - buf[0] = INTRST; - buf[1] = 0x00; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) - { - ret = -RT_ERROR; - break; - } - } - } while (0); + /* Reset the interrupt flags: Part 2 */ + buf[0] = INTRST; + buf[1] = 0x00; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0) + { + ret = -RT_ERROR; + break; + } + } + } while (0); - return ret; + return ret; } #endif @@ -536,203 +536,203 @@ rt_err_t efm_accel_config(rt_uint32_t config, * @note * * @param[in] mode - * 0, simple mode (assuming the device is placed on flat surface) - * 1, interaction method + * 0, simple mode (assuming the device is placed on flat surface) + * 1, interaction method * * @param[in] period - * Time period to perform auto-zero calibration + * Time period to perform auto-zero calibration * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period) { - RT_ASSERT(accel != RT_NULL); + RT_ASSERT(accel != RT_NULL); - rt_timer_t calTimer; - struct efm32_accel_result_t min = {0, 0, 0}; - struct efm32_accel_result_t max = {0, 0, 0}; - struct efm32_accel_result_t temp, sum; - rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE; - rt_uint8_t cmd[7] = {0}; - rt_uint8_t i, j; + rt_timer_t calTimer; + struct efm32_accel_result_t min = {0, 0, 0}; + struct efm32_accel_result_t max = {0, 0, 0}; + struct efm32_accel_result_t temp, sum; + rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE; + rt_uint8_t cmd[7] = {0}; + rt_uint8_t i, j; - /* Reset offset */ + /* Reset offset */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - accelOffset.x = 0; - accelOffset.y = 0; - accelOffset.z = 0; + accelOffset.x = 0; + accelOffset.y = 0; + accelOffset.z = 0; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - cmd[0] = XOFFL; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } + cmd[0] = XOFFL; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } #endif - if (mode == ACCEL_CAL_SIMPLE) - { - /* Simple mode */ - for (j = 0; j < ACCEL_CAL_ROUND; j++) - { - sum.x = 0x0; - sum.y = 0x0; - sum.z = 0x0; + if (mode == ACCEL_CAL_SIMPLE) + { + /* Simple mode */ + for (j = 0; j < ACCEL_CAL_ROUND; j++) + { + sum.x = 0x0; + sum.y = 0x0; + sum.z = 0x0; - for (i = 0; i < ACCEL_CAL_SAMPLES; i++) - { + for (i = 0; i < ACCEL_CAL_SAMPLES; i++) + { #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Waiting for data ready */ - while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); + /* Waiting for data ready */ + while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); #endif - if (efm_accel_get_data(&temp, false) != RT_EOK) - { - return -RT_ERROR; - } - sum.x += temp.x; - sum.y += temp.y; - sum.z += temp.z; - } + if (efm_accel_get_data(&temp, false) != RT_EOK) + { + return -RT_ERROR; + } + sum.x += temp.x; + sum.y += temp.y; + sum.z += temp.z; + } #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - temp.x = sum.x / ACCEL_CAL_SAMPLES; - temp.y = sum.y / ACCEL_CAL_SAMPLES; - temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT]; - if ((temp.x == 0) && (temp.y == 0) && \ - (temp.z == 0)) - { - accel_debug("Accel: Offset %+d %+d %+d\n", - accelOffset.x, accelOffset.y, accelOffset.z); - break; - } - accelOffset.x -= temp.x; - accelOffset.y -= temp.y; - accelOffset.z -= temp.z; + temp.x = sum.x / ACCEL_CAL_SAMPLES; + temp.y = sum.y / ACCEL_CAL_SAMPLES; + temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT]; + if ((temp.x == 0) && (temp.y == 0) && \ + (temp.z == 0)) + { + accel_debug("Accel: Offset %+d %+d %+d\n", + accelOffset.x, accelOffset.y, accelOffset.z); + break; + } + accelOffset.x -= temp.x; + accelOffset.y -= temp.y; + accelOffset.z -= temp.z; #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1); - temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1); - temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \ - - (simpleOffset[ACCEL_G_SELECT] << 1); - if ((temp.x == 0) && (temp.y == 0) && \ - (temp.z == 0)) - { - break; - } + temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1); + temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1); + temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \ + - (simpleOffset[ACCEL_G_SELECT] << 1); + if ((temp.x == 0) && (temp.y == 0) && \ + (temp.z == 0)) + { + break; + } - /* Set offset drift registers */ - max.x -= temp.x; - max.y -= temp.y; - max.z -= temp.z; - *(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x; - *(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y; - *(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z; - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } - accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \ - *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); + /* Set offset drift registers */ + max.x -= temp.x; + max.y -= temp.y; + max.z -= temp.z; + *(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x; + *(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y; + *(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z; + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } + accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \ + *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); #endif - rt_thread_sleep(1); - } - } - else - { - /* Interact mode */ - if ((calTimer = rt_timer_create( - "cal_tmr", - efm_accel_timer, - RT_NULL, - period, - RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL) - { - accel_debug("Accel err: Create timer failed!\n"); - return -RT_ERROR; - } + rt_thread_sleep(1); + } + } + else + { + /* Interact mode */ + if ((calTimer = rt_timer_create( + "cal_tmr", + efm_accel_timer, + RT_NULL, + period, + RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL) + { + accel_debug("Accel err: Create timer failed!\n"); + return -RT_ERROR; + } - accelInTime = true; - rt_timer_start(calTimer); - do - { - sum.x = 0x0; - sum.y = 0x0; - sum.z = 0x0; + accelInTime = true; + rt_timer_start(calTimer); + do + { + sum.x = 0x0; + sum.y = 0x0; + sum.z = 0x0; - for (i = 0; i < ACCEL_CAL_SAMPLES; i++) - { + for (i = 0; i < ACCEL_CAL_SAMPLES; i++) + { #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Waiting for data ready */ - while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); + /* Waiting for data ready */ + while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN)); #endif - if (efm_accel_get_data(&temp, false) != RT_EOK) - { - return -RT_ERROR; - } - sum.x += temp.x; - sum.y += temp.y; - sum.z += temp.z; - } - sum.x /= ACCEL_CAL_SAMPLES; - sum.y /= ACCEL_CAL_SAMPLES; - sum.z /= ACCEL_CAL_SAMPLES; - if (sum.x < min.x) - { - min.x = sum.x; - } - if (sum.y < min.y) - { - min.y = sum.y; - } - if (sum.z < min.z) - { - min.z = sum.z; - } - if (sum.x > max.x) - { - max.x = sum.x; - } - if (sum.y > max.y) - { - max.y = sum.y; - } - if (sum.z > max.z) - { - max.z = sum.z; - } - rt_thread_sleep(1); - } while (accelInTime); + if (efm_accel_get_data(&temp, false) != RT_EOK) + { + return -RT_ERROR; + } + sum.x += temp.x; + sum.y += temp.y; + sum.z += temp.z; + } + sum.x /= ACCEL_CAL_SAMPLES; + sum.y /= ACCEL_CAL_SAMPLES; + sum.z /= ACCEL_CAL_SAMPLES; + if (sum.x < min.x) + { + min.x = sum.x; + } + if (sum.y < min.y) + { + min.y = sum.y; + } + if (sum.z < min.z) + { + min.z = sum.z; + } + if (sum.x > max.x) + { + max.x = sum.x; + } + if (sum.y > max.y) + { + max.y = sum.y; + } + if (sum.z > max.z) + { + max.z = sum.z; + } + rt_thread_sleep(1); + } while (accelInTime); - accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n", - min.x, min.y, min.z, max.x, max.y, max.z); + accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n", + min.x, min.y, min.z, max.x, max.y, max.z); #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - accelOffset.x = -((min.x + max.x) >> 1); - accelOffset.y = -((min.y + max.y) >> 1); - accelOffset.z = -((min.z + max.z) >> 1); + accelOffset.x = -((min.x + max.x) >> 1); + accelOffset.y = -((min.y + max.y) >> 1); + accelOffset.z = -((min.z + max.z) >> 1); - accel_debug("Accel: Offset %+d %+d %+d\n", - accelOffset.x, accelOffset.y, accelOffset.z); + accel_debug("Accel: Offset %+d %+d %+d\n", + accelOffset.x, accelOffset.y, accelOffset.z); #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - /* Set offset drift registers */ - *(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x); - *(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y); - *(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z); - if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) - { - return -RT_ERROR; - } + /* Set offset drift registers */ + *(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x); + *(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y); + *(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z); + if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0) + { + return -RT_ERROR; + } - accel_debug("Accel: Offset %+d %+d %+d\n", - *(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); + accel_debug("Accel: Offset %+d %+d %+d\n", + *(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]); #endif - rt_timer_delete(calTimer); - } + rt_timer_delete(calTimer); + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -744,147 +744,147 @@ rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period) * @note * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm_accel_init(void) { - rt_err_t ret; + rt_err_t ret; - ret = RT_EOK; - do - { - /* Find ADC device */ - accel = rt_device_find(ACCEL_USING_DEVICE_NAME); - if (accel == RT_NULL) - { - accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME); - ret = -RT_ERROR; - break; - } - accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME); + ret = RT_EOK; + do + { + /* Find ADC device */ + accel = rt_device_find(ACCEL_USING_DEVICE_NAME); + if (accel == RT_NULL) + { + accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME); + ret = -RT_ERROR; + break; + } + accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME); - /* --------- ADC interface --------- */ + /* --------- ADC interface --------- */ #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) - ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT; + ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT; #if defined(EFM32_GXXX_DK) - /* Enable accelerometer */ - DVK_enablePeripheral(DVK_ACCEL); - /* Select g-range */ + /* Enable accelerometer */ + DVK_enablePeripheral(DVK_ACCEL); + /* Select g-range */ #if (ACCEL_G_SELECT == 0) - DVK_disablePeripheral(DVK_ACCEL_GSEL); + DVK_disablePeripheral(DVK_ACCEL_GSEL); #elif (ACCEL_G_SELECT == 1) - DVK_enablePeripheral(DVK_ACCEL_GSEL); + DVK_enablePeripheral(DVK_ACCEL_GSEL); #else #error "Wrong value for ACCEL_G_SELECT" #endif #endif - /* Init ADC for scan mode */ - scanInit.reference = adcRefVDD; - scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH; + /* Init ADC for scan mode */ + scanInit.reference = adcRefVDD; + scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH; - control.scan.init = &scanInit; - if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \ - (void *)&control)) != RT_EOK) - { - break; - } + control.scan.init = &scanInit; + if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \ + (void *)&control)) != RT_EOK) + { + break; + } - /* --------- IIC interface --------- */ + /* --------- IIC interface --------- */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) - rt_uint8_t cmd[2]; + rt_uint8_t cmd[2]; - /* Initialize */ - if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \ - (void *)&control)) != RT_EOK) - { - break; - } + /* Initialize */ + if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \ + (void *)&control)) != RT_EOK) + { + break; + } - if (efm_accel_config( - ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA) != RT_EOK) - { - break; - } + if (efm_accel_config( + ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA) != RT_EOK) + { + break; + } - /* Config interrupt pin1 */ - GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0); - /* Config interrupt pin2 */ - GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0); + /* Config interrupt pin1 */ + GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0); + /* Config interrupt pin2 */ + GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0); #endif - accel_debug("Accel: Init OK\n"); - return RT_EOK; - } while (0); + accel_debug("Accel: Init OK\n"); + return RT_EOK; + } while (0); - accel_debug("Accel err: Init failed!\n"); - return -RT_ERROR; + accel_debug("Accel err: Init failed!\n"); + return -RT_ERROR; } /******************************************************************************* - * Export to FINSH + * Export to FINSH ******************************************************************************/ #ifdef RT_USING_FINSH #include <finsh.h> void accel_cal(rt_uint8_t mode, rt_uint32_t second) { - if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK) - { - rt_kprintf("Error occurred."); - return; - } + if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK) + { + rt_kprintf("Error occurred."); + return; + } - rt_kprintf("Calibration done.\n"); + rt_kprintf("Calibration done.\n"); } FINSH_FUNCTION_EXPORT(accel_cal, auto-zero calibration.) void list_accel(void) { - struct efm32_accel_result_t data; + struct efm32_accel_result_t data; - efm_accel_get_data(&data, false); - rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z); + efm_accel_get_data(&data, false); + rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z); } FINSH_FUNCTION_EXPORT(list_accel, list accelerometer info.) void test_accel(rt_uint8_t mode) { - if (mode == 0) - { - if (efm_accel_config( - ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \ - ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y, - 0x1f, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA, - EFM32_NO_DATA) != RT_EOK) - { - rt_kprintf("efm_accel_config(): error\n"); - return; - } - } - else - { - if (efm_accel_config( - ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \ - ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y, - 0x1f, - 0x1f, - 200, - 255, - 255) != RT_EOK) - { - rt_kprintf("efm_accel_config(): error\n"); - return; - } - } + if (mode == 0) + { + if (efm_accel_config( + ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \ + ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y, + 0x1f, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA, + EFM32_NO_DATA) != RT_EOK) + { + rt_kprintf("efm_accel_config(): error\n"); + return; + } + } + else + { + if (efm_accel_config( + ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \ + ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y, + 0x1f, + 0x1f, + 200, + 255, + 255) != RT_EOK) + { + rt_kprintf("efm_accel_config(): error\n"); + return; + } + } } FINSH_FUNCTION_EXPORT(test_accel, list accelerometer info.) #endif diff --git a/bsp/efm32/dev_accel.h b/bsp/efm32/dev_accel.h index 2e12d797d3..cc75631834 100644 --- a/bsp/efm32/dev_accel.h +++ b/bsp/efm32/dev_accel.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_accel.h - * @brief Accelerometer driver of RT-Thread RTOS for EFM32 + * @file dev_accel.h + * @brief Accelerometer driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,10 +10,10 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-13 onelife Initial creation for using EFM32 ADC module to + * Date Author Notes + * 2011-07-13 onelife Initial creation for using EFM32 ADC module to * interface the Freescale MMA7361L - * 2011-08-02 onelife Add digital interface support of using EFM32 IIC + * 2011-08-02 onelife Add digital interface support of using EFM32 IIC * module for the Freescale MMA7455L ******************************************************************************/ #ifndef __DEV_ACCEL_H__ @@ -27,95 +27,95 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_accel_result_t { - rt_int32_t x; - rt_int32_t y; - rt_int32_t z; + rt_int32_t x; + rt_int32_t y; + rt_int32_t z; }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/* MMA7361LC - g-Select g-Range Sensitivity - 0 1.5 g 800 mV/g - 1 6 g 206 mV/g +/* MMA7361LC + g-Select g-Range Sensitivity + 0 1.5 g 800 mV/g + 1 6 g 206 mV/g - MMA7455L - g-Select g-Range Sensitivity - 0 2 g 64 LSB/g - 1 4 g 32 LSB/g - 2 8 g 16 LSB/g + MMA7455L + g-Select g-Range Sensitivity + 0 2 g 64 LSB/g + 1 4 g 32 LSB/g + 2 8 g 16 LSB/g */ -#define ACCEL_G_SELECT (0) +#define ACCEL_G_SELECT (0) -#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */ -#define ACCEL_CAL_ROUND (50) -#define ACCEL_CAL_SIMPLE (0) -#define ACCEL_CAL_INTERACT (1) +#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */ +#define ACCEL_CAL_ROUND (50) +#define ACCEL_CAL_SIMPLE (0) +#define ACCEL_CAL_INTERACT (1) #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) /* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */ -#define ACCEL_CAL_1G_VALUE {993, 256} +#define ACCEL_CAL_1G_VALUE {993, 256} -#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2 -#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3 -#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4 +#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2 +#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3 +#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f} +#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f} #define ACCEL_IIC_SLAVE_ADDRESS (0x1d) -#define ACCEL_INT1_PORT (gpioPortD) -#define ACCEL_INT1_PIN (13) -#define ACCEL_INT2_PORT (gpioPortD) -#define ACCEL_INT2_PIN (12) +#define ACCEL_INT1_PORT (gpioPortD) +#define ACCEL_INT1_PIN (13) +#define ACCEL_INT2_PORT (gpioPortD) +#define ACCEL_INT2_PIN (12) -#define ACCEL_MODE_STANDBY (1 << 0) -#define ACCEL_MODE_MEASUREMENT (1 << 1) -#define ACCEL_MODE_LEVEL (1 << 2) -#define ACCEL_MODE_PULSE (1 << 3) -#define ACCEL_RANGE_8G (1 << 4) -#define ACCEL_RANGE_4G (1 << 5) -#define ACCEL_RANGE_2G (1 << 6) -#define ACCEL_INTPIN_INVERSE (1 << 7) -#define ACCEL_INT_LEVEL_PULSE (1 << 8) -#define ACCEL_INT_PULSE_LEVEL (1 << 9) -#define ACCEL_INT_SINGLE_DOUBLE (1 << 10) -#define ACCEL_DISABLE_X (1 << 11) -#define ACCEL_DISABLE_Y (1 << 12) -#define ACCEL_DISABLE_Z (1 << 13) -#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */ -#define ACCEL_BANDWIDTH_125HZ (1 << 15) -#define ACCEL_LEVEL_AND (1 << 16) -#define ACCEL_PULSE_AND (1 << 17) -#define ACCEL_DRIVE_STRONG (1 << 18) -#define ACCEL_SOURCE_LEVEL_X (1 << 19) -#define ACCEL_SOURCE_LEVEL_Y (1 << 20) -#define ACCEL_SOURCE_LEVEL_Z (1 << 21) -#define ACCEL_SOURCE_PULSE_X (1 << 22) -#define ACCEL_SOURCE_PULSE_Y (1 << 23) -#define ACCEL_SOURCE_PULSE_Z (1 << 24) +#define ACCEL_MODE_STANDBY (1 << 0) +#define ACCEL_MODE_MEASUREMENT (1 << 1) +#define ACCEL_MODE_LEVEL (1 << 2) +#define ACCEL_MODE_PULSE (1 << 3) +#define ACCEL_RANGE_8G (1 << 4) +#define ACCEL_RANGE_4G (1 << 5) +#define ACCEL_RANGE_2G (1 << 6) +#define ACCEL_INTPIN_INVERSE (1 << 7) +#define ACCEL_INT_LEVEL_PULSE (1 << 8) +#define ACCEL_INT_PULSE_LEVEL (1 << 9) +#define ACCEL_INT_SINGLE_DOUBLE (1 << 10) +#define ACCEL_DISABLE_X (1 << 11) +#define ACCEL_DISABLE_Y (1 << 12) +#define ACCEL_DISABLE_Z (1 << 13) +#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */ +#define ACCEL_BANDWIDTH_125HZ (1 << 15) +#define ACCEL_LEVEL_AND (1 << 16) +#define ACCEL_PULSE_AND (1 << 17) +#define ACCEL_DRIVE_STRONG (1 << 18) +#define ACCEL_SOURCE_LEVEL_X (1 << 19) +#define ACCEL_SOURCE_LEVEL_Y (1 << 20) +#define ACCEL_SOURCE_LEVEL_Z (1 << 21) +#define ACCEL_SOURCE_PULSE_X (1 << 22) +#define ACCEL_SOURCE_PULSE_Y (1 << 23) +#define ACCEL_SOURCE_PULSE_Z (1 << 24) -#define ACCEL_SHIFT_MODE (0) -#define ACCEL_SHIFT_RANGE (4) -#define ACCEL_SHIFT_INT (8) -#define ACCEL_SHIFT_DISABLE (11) -#define ACCEL_SHIFT_SOURCE (19) +#define ACCEL_SHIFT_MODE (0) +#define ACCEL_SHIFT_RANGE (4) +#define ACCEL_SHIFT_INT (8) +#define ACCEL_SHIFT_DISABLE (11) +#define ACCEL_SHIFT_SOURCE (19) -#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE) -#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE) -#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT) -#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE) -#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE) +#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE) +#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE) +#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT) +#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE) +#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE) #endif /* Exported functions ------------------------------------------------------- */ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data, - rt_bool_t lowResolution); + rt_bool_t lowResolution); rt_err_t efm_accel_config(rt_uint32_t config, - rt_uint8_t level_threshold, - rt_uint8_t pulse_threshold, - rt_uint8_t pulse_duration, - rt_uint8_t pulse_latency, - rt_uint8_t pulse_duration2); + rt_uint8_t level_threshold, + rt_uint8_t pulse_threshold, + rt_uint8_t pulse_duration, + rt_uint8_t pulse_latency, + rt_uint8_t pulse_duration2); rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period); rt_err_t efm_accel_init(void); diff --git a/bsp/efm32/dev_keys.c b/bsp/efm32/dev_keys.c index a7a58ff20f..15d306b36b 100644 --- a/bsp/efm32/dev_keys.c +++ b/bsp/efm32/dev_keys.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_keys.c - * @brief Keys driver of RT-Thread RTOS for EFM32 + * @file dev_keys.c + * @brief Keys driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board ******************************************************************************/ @@ -48,14 +48,14 @@ static rt_bool_t click; /* Private functions ---------------------------------------------------------*/ /***************************************************************************//** * @brief - * Keys interrupt handler + * Keys interrupt handler * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ static void efm32_keys_isr(rt_device_t dev) { @@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev) /***************************************************************************//** * @brief - * Keys timeout handler + * Keys timeout handler * * @details * * @note * * @param[in] param - * Parameter + * Parameter ******************************************************************************/ static void efm32_keys_timer_isr(void *param) { - rt_uint16_t joystick; + rt_uint16_t joystick; joystick = DVK_getJoystick(); @@ -277,11 +277,11 @@ void efm32_hw_keys_init(void) GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true); efm32_irq_hook_init_t hook; - hook.type = efm32_irq_type_gpio; - hook.unit = KEYS_INT_PIN; - hook.cbFunc = efm32_keys_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); + hook.type = efm32_irq_type_gpio; + hook.unit = KEYS_INT_PIN; + hook.cbFunc = efm32_keys_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); if ((rt_uint8_t)KEYS_INT_PIN % 2) { @@ -299,12 +299,12 @@ void efm32_hw_keys_init(void) /* Enable DVK joystick interrupt */ DVK_enableInterrupt(BC_INTEN_JOYSTICK); - rt_timer_init(&joy.timer, - "joy_tmr", - efm32_keys_timer_isr, - RT_NULL, - KEYS_POLL_TIME, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&joy.timer, + "joy_tmr", + efm32_keys_timer_isr, + RT_NULL, + KEYS_POLL_TIME, + RT_TIMER_FLAG_PERIODIC); joy_dev.init = efm32_keys_init; joy_dev.open = RT_NULL; diff --git a/bsp/efm32/dev_keys.h b/bsp/efm32/dev_keys.h index 6e66617331..87f8fe95fd 100644 --- a/bsp/efm32/dev_keys.h +++ b/bsp/efm32/dev_keys.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_keys.h - * @brief Keys driver of RT-Thread RTOS for EFM32 + * @file dev_keys.h + * @brief Keys driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board ******************************************************************************/ #ifndef __DEV_KEYS_H__ diff --git a/bsp/efm32/dev_lcd.c b/bsp/efm32/dev_lcd.c index 0a2d469d78..c4cbbcce21 100644 --- a/bsp/efm32/dev_lcd.c +++ b/bsp/efm32/dev_lcd.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_lcd.c - * @brief LCD driver of RT-Thread RTOS for EFM32 + * @file dev_lcd.c + * @brief LCD driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-16 onelife Initial creation of address mapped method (pixel * drive) for EFM32GG_DK3750 board * 2011-12-29 onelife Add direct drive method (frame buffer) support @@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data) /***************************************************************************//** * @brief - * Register LCD device + * Register LCD device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] iic - * Pointer to IIC device descriptor + * Pointer to IIC device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t efm32_spiLcd_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - void *data) + rt_device_t device, + const char *name, + rt_uint32_t flag, + void *data) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Graphic; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = RT_NULL; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = efm32_spiLcd_control; - device->user_data = data; + device->type = RT_Device_Class_Graphic; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = efm32_spiLcd_control; + device->user_data = data; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /***************************************************************************//** @@ -511,18 +511,18 @@ void efm32_spiLcd_init(void) DMD_DisplayGeometry *geometry; rt_uint32_t ret; - do - { + do + { USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; - /* Find SPI device */ - lcd = rt_device_find(LCD_USING_DEVICE_NAME); - if (lcd == RT_NULL) - { - lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME); - break; - } - lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME); + /* Find SPI device */ + lcd = rt_device_find(LCD_USING_DEVICE_NAME); + if (lcd == RT_NULL) + { + lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME); + break; + } + lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME); /* Config CS pin */ usart = (struct efm32_usart_device_t *)(lcd->user_data); @@ -647,7 +647,7 @@ void efm32_spiLcd_init(void) } /* Init LCD info */ - flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX; + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX; lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; lcd_info.bits_per_pixel = 16; lcd_info.width = geometry->xSize; diff --git a/bsp/efm32/dev_lcd.h b/bsp/efm32/dev_lcd.h index 075bed64ba..4c59286ef6 100644 --- a/bsp/efm32/dev_lcd.h +++ b/bsp/efm32/dev_lcd.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file dev_lcd.h - * @brief LCD driver of RT-Thread RTOS for EFM32 + * @file dev_lcd.h + * @brief LCD driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-16 onelife Initial creation of address mapped method (pixel * drive) for EFM32GG_DK3750 board ******************************************************************************/ diff --git a/bsp/efm32/dev_sflash.h b/bsp/efm32/dev_sflash.h index ae72ec678a..b7d2860f0d 100644 --- a/bsp/efm32/dev_sflash.h +++ b/bsp/efm32/dev_sflash.h @@ -20,85 +20,85 @@ /* Exported types ------------------------------------------------------------*/ enum sflash_inst_type_t { - /* Instruction only */ - sflash_inst_wren = 0x00, - sflash_inst_wrdi, - sflash_inst_rdid_l, - sflash_inst_rdid_s, - sflash_inst_rdsr, - sflash_inst_wrsr, - sflash_inst_be, - sflash_inst_dp, - sflash_inst_rdp, - /* Instruction and address */ - sflash_inst_wrlr, - sflash_inst_rdlr, - sflash_inst_read, - sflash_inst_potp, - sflash_inst_pp, - sflash_inst_difp, - sflash_inst_sse, - sflash_inst_se, - /* Instruction, address and dummy read */ - sflash_inst_read_f, - sflash_inst_dofr, - sflash_inst_rotp + /* Instruction only */ + sflash_inst_wren = 0x00, + sflash_inst_wrdi, + sflash_inst_rdid_l, + sflash_inst_rdid_s, + sflash_inst_rdsr, + sflash_inst_wrsr, + sflash_inst_be, + sflash_inst_dp, + sflash_inst_rdp, + /* Instruction and address */ + sflash_inst_wrlr, + sflash_inst_rdlr, + sflash_inst_read, + sflash_inst_potp, + sflash_inst_pp, + sflash_inst_difp, + sflash_inst_sse, + sflash_inst_se, + /* Instruction, address and dummy read */ + sflash_inst_read_f, + sflash_inst_dofr, + sflash_inst_rotp }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define SFLASH_SPI_COMMAND_SKIP (1) -#define SFLASH_SPI_READ_SKIP (2) +#define SFLASH_SPI_COMMAND_SKIP (1) +#define SFLASH_SPI_READ_SKIP (2) -#define SFLASH_INST_CODE_WREN (0x06) -#define SFLASH_INST_CODE_WRDI (0x04) -#define SFLASH_INST_CODE_RDID_L (0x9F) -#define SFLASH_INST_CODE_RDID_S (0x9E) -#define SFLASH_INST_CODE_RDSR (0x05) -#define SFLASH_INST_CODE_WRSR (0x01) -#define SFLASH_INST_CODE_WRLR (0xE5) -#define SFLASH_INST_CODE_RDLR (0xE8) -#define SFLASH_INST_CODE_READ (0x03) -#define SFLASH_INST_CODE_READ_F (0x0B) -#define SFLASH_INST_CODE_DOFR (0x3B) -#define SFLASH_INST_CODE_ROTP (0x4B) -#define SFLASH_INST_CODE_POTP (0x42) -#define SFLASH_INST_CODE_PP (0x02) -#define SFLASH_INST_CODE_DIFP (0xA2) -#define SFLASH_INST_CODE_SSE (0x20) -#define SFLASH_INST_CODE_SE (0xD8) -#define SFLASH_INST_CODE_BE (0xC7) -#define SFLASH_INST_CODE_DP (0xB9) -#define SFLASH_INST_CODE_RDP (0xAB) +#define SFLASH_INST_CODE_WREN (0x06) +#define SFLASH_INST_CODE_WRDI (0x04) +#define SFLASH_INST_CODE_RDID_L (0x9F) +#define SFLASH_INST_CODE_RDID_S (0x9E) +#define SFLASH_INST_CODE_RDSR (0x05) +#define SFLASH_INST_CODE_WRSR (0x01) +#define SFLASH_INST_CODE_WRLR (0xE5) +#define SFLASH_INST_CODE_RDLR (0xE8) +#define SFLASH_INST_CODE_READ (0x03) +#define SFLASH_INST_CODE_READ_F (0x0B) +#define SFLASH_INST_CODE_DOFR (0x3B) +#define SFLASH_INST_CODE_ROTP (0x4B) +#define SFLASH_INST_CODE_POTP (0x42) +#define SFLASH_INST_CODE_PP (0x02) +#define SFLASH_INST_CODE_DIFP (0xA2) +#define SFLASH_INST_CODE_SSE (0x20) +#define SFLASH_INST_CODE_SE (0xD8) +#define SFLASH_INST_CODE_BE (0xC7) +#define SFLASH_INST_CODE_DP (0xB9) +#define SFLASH_INST_CODE_RDP (0xAB) -#define SFLASH_REPLY_LEN_WREN (0) -#define SFLASH_REPLY_LEN_WRDI (0) -#define SFLASH_REPLY_LEN_RDID_L (20) -#define SFLASH_REPLY_LEN_RDID_S (3) -#define SFLASH_REPLY_LEN_RDSR (1) -#define SFLASH_REPLY_LEN_WRSR (1) -#define SFLASH_REPLY_LEN_WRLR (1) -#define SFLASH_REPLY_LEN_RDLR (1) -#define SFLASH_REPLY_LEN_READ (-1) -#define SFLASH_REPLY_LEN_READ_F (-1) -#define SFLASH_REPLY_LEN_DOFR (-1) -#define SFLASH_REPLY_LEN_ROTP (65) -#define SFLASH_REPLY_LEN_POTP (65) -#define SFLASH_REPLY_LEN_PP (256) -#define SFLASH_REPLY_LEN_DIFP (256) -#define SFLASH_REPLY_LEN_SSE (0) -#define SFLASH_REPLY_LEN_SE (0) -#define SFLASH_REPLY_LEN_BE (0) -#define SFLASH_REPLY_LEN_DP (0) -#define SFLASH_REPLY_LEN_RDP (0) +#define SFLASH_REPLY_LEN_WREN (0) +#define SFLASH_REPLY_LEN_WRDI (0) +#define SFLASH_REPLY_LEN_RDID_L (20) +#define SFLASH_REPLY_LEN_RDID_S (3) +#define SFLASH_REPLY_LEN_RDSR (1) +#define SFLASH_REPLY_LEN_WRSR (1) +#define SFLASH_REPLY_LEN_WRLR (1) +#define SFLASH_REPLY_LEN_RDLR (1) +#define SFLASH_REPLY_LEN_READ (-1) +#define SFLASH_REPLY_LEN_READ_F (-1) +#define SFLASH_REPLY_LEN_DOFR (-1) +#define SFLASH_REPLY_LEN_ROTP (65) +#define SFLASH_REPLY_LEN_POTP (65) +#define SFLASH_REPLY_LEN_PP (256) +#define SFLASH_REPLY_LEN_DIFP (256) +#define SFLASH_REPLY_LEN_SSE (0) +#define SFLASH_REPLY_LEN_SE (0) +#define SFLASH_REPLY_LEN_BE (0) +#define SFLASH_REPLY_LEN_DP (0) +#define SFLASH_REPLY_LEN_RDP (0) /* Exported functions ------------------------------------------------------- */ rt_err_t efm_spiFlash_init(void); rt_err_t efm_spiFlash_deinit(void); rt_uint32_t efm_spiFlash_cmd( - enum sflash_inst_type_t command, - rt_uint32_t address, - rt_uint8_t *buffer, - rt_uint32_t size); + enum sflash_inst_type_t command, + rt_uint32_t address, + rt_uint8_t *buffer, + rt_uint32_t size); #endif /* __DEV_SFLASH_H__ */ diff --git a/bsp/efm32/drv_acmp.c b/bsp/efm32/drv_acmp.c index 1961fc4695..b9d24e8ebd 100644 --- a/bsp/efm32/drv_acmp.c +++ b/bsp/efm32/drv_acmp.c @@ -30,18 +30,18 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_ACMP_DEBUG -#define acmp_debug(format,args...) rt_kprintf(format, ##args) +#define acmp_debug(format,args...) rt_kprintf(format, ##args) #else #define acmp_debug(format,args...) #endif /* Private variables ---------------------------------------------------------*/ #ifdef RT_USING_ACMP0 - static struct rt_device acmp0_device; + static struct rt_device acmp0_device; #endif #ifdef RT_USING_ACMP1 - static struct rt_device acmp1_device; + static struct rt_device acmp1_device; #endif /* Private function prototypes -----------------------------------------------*/ @@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq); ******************************************************************************/ static rt_err_t rt_acmp_init(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; - acmp = (struct efm32_acmp_device_t *)(dev->user_data); + acmp = (struct efm32_acmp_device_t *)(dev->user_data); - acmp->hook.cbFunc = RT_NULL; - acmp->hook.userPtr = RT_NULL; + acmp->hook.cbFunc = RT_NULL; + acmp->hook.userPtr = RT_NULL; - return RT_EOK; + return RT_EOK; } /***************************************************************************//** * @brief - * Configure ACMP device + * Configure ACMP device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] cmd - * ACMP control command + * ACMP control command * * @param[in] args - * Arguments + * Arguments * * @return - * Error code + * Error code ******************************************************************************/ static rt_err_t rt_acmp_control( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; - acmp = (struct efm32_acmp_device_t *)(dev->user_data); + acmp = (struct efm32_acmp_device_t *)(dev->user_data); - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - ACMP_Disable(acmp->acmp_device); - break; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + ACMP_Disable(acmp->acmp_device); + break; - case RT_DEVICE_CTRL_RESUME: - /* Resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - ACMP_Enable(acmp->acmp_device); - break; + case RT_DEVICE_CTRL_RESUME: + /* Resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + ACMP_Enable(acmp->acmp_device); + break; - case RT_DEVICE_CTRL_ACMP_INIT: - { - rt_bool_t int_en = false; - struct efm32_acmp_control_t *control; + case RT_DEVICE_CTRL_ACMP_INIT: + { + rt_bool_t int_en = false; + struct efm32_acmp_control_t *control; - control = (struct efm32_acmp_control_t *)args; - acmp_debug("ACMP: control -> init start\n"); + control = (struct efm32_acmp_control_t *)args; + acmp_debug("ACMP: control -> init start\n"); - /* Configure ACMPn */ - if (control->init == RT_NULL) - { - return -RT_ERROR; - } - ACMP_Init(acmp->acmp_device, control->init); - ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput); - if (control->output != RT_NULL) - { - ACMP_GPIOSetup( - acmp->acmp_device, - control->output->location, - control->output->enable, - control->output->invert); - int_en = true; - } - if (control->hook.cbFunc != RT_NULL) - { - acmp->hook.cbFunc = control->hook.cbFunc; - acmp->hook.userPtr = control->hook.userPtr; - int_en = true; - } + /* Configure ACMPn */ + if (control->init == RT_NULL) + { + return -RT_ERROR; + } + ACMP_Init(acmp->acmp_device, control->init); + ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput); + if (control->output != RT_NULL) + { + ACMP_GPIOSetup( + acmp->acmp_device, + control->output->location, + control->output->enable, + control->output->invert); + int_en = true; + } + if (control->hook.cbFunc != RT_NULL) + { + acmp->hook.cbFunc = control->hook.cbFunc; + acmp->hook.userPtr = control->hook.userPtr; + int_en = true; + } - if (int_en) - { - /* Enable edge interrupt */ - ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE); - ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE); + if (int_en) + { + /* Enable edge interrupt */ + ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE); + ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE); - /* Enable ACMP0/1 interrupt vector in NVIC */ - NVIC_ClearPendingIRQ(ACMP0_IRQn); - NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(ACMP0_IRQn); - } - } - break; + /* Enable ACMP0/1 interrupt vector in NVIC */ + NVIC_ClearPendingIRQ(ACMP0_IRQn); + NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(ACMP0_IRQn); + } + } + break; - case RT_DEVICE_CTRL_ACMP_OUTPUT: - *((rt_bool_t *)args) = \ - (acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false; - break; + case RT_DEVICE_CTRL_ACMP_OUTPUT: + *((rt_bool_t *)args) = \ + (acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false; + break; - default: - return -RT_ERROR; - } + default: + return -RT_ERROR; + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** * @brief - * Register ACMP device + * Register ACMP device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] acmp - * Pointer to ACMP device descriptor + * Pointer to ACMP device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t rt_hw_acmp_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_acmp_device_t *acmp) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_acmp_device_t *acmp) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; /* fixme: should be acmp type */ - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_acmp_init; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_acmp_control; - device->user_data = acmp; + device->type = RT_Device_Class_Char; /* fixme: should be acmp type */ + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_acmp_init; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_acmp_control; + device->user_data = acmp; - /* register a character device */ - return rt_device_register(device, name, flag); + /* register a character device */ + return rt_device_register(device, name, flag); } /***************************************************************************//** * @brief - * ACMP edge trigger interrupt handler + * ACMP edge trigger interrupt handler * * @details * @@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register( ******************************************************************************/ void rt_hw_acmp_isr(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; - acmp = (struct efm32_acmp_device_t *)(dev->user_data); + acmp = (struct efm32_acmp_device_t *)(dev->user_data); - if (acmp->hook.cbFunc != RT_NULL) - { - (acmp->hook.cbFunc)(acmp->hook.userPtr); - } + if (acmp->hook.cbFunc != RT_NULL) + { + (acmp->hook.cbFunc)(acmp->hook.userPtr); + } } /***************************************************************************//** * @brief - * Initialize the specified ACMP unit + * Initialize the specified ACMP unit * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] unitNumber - * Unit number + * Unit number * * @return - * Pointer to ACMP device + * Pointer to ACMP device ******************************************************************************/ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init( - rt_device_t device, - rt_uint8_t unitNumber) + rt_device_t device, + rt_uint8_t unitNumber) { - struct efm32_acmp_device_t *acmp; - efm32_irq_hook_init_t hook; - CMU_Clock_TypeDef acmpClock; + struct efm32_acmp_device_t *acmp; + efm32_irq_hook_init_t hook; + CMU_Clock_TypeDef acmpClock; - do - { - /* Allocate device */ - acmp = rt_malloc(sizeof(struct efm32_acmp_device_t)); - if (acmp == RT_NULL) - { - acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber); - break; - } + do + { + /* Allocate device */ + acmp = rt_malloc(sizeof(struct efm32_acmp_device_t)); + if (acmp == RT_NULL) + { + acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber); + break; + } - /* Initialization */ - if (unitNumber >= ACMP_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - acmp->acmp_device = ACMP0; - acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0; - break; + /* Initialization */ + if (unitNumber >= ACMP_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + acmp->acmp_device = ACMP0; + acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0; + break; - case 1: - acmp->acmp_device = ACMP1; - acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1; - break; + case 1: + acmp->acmp_device = ACMP1; + acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1; + break; - default: - break; - } + default: + break; + } - /* Enable ACMP clock */ - CMU_ClockEnable(acmpClock, true); + /* Enable ACMP clock */ + CMU_ClockEnable(acmpClock, true); - /* Reset */ - ACMP_Reset(acmp->acmp_device); + /* Reset */ + ACMP_Reset(acmp->acmp_device); - /* Config interrupt and NVIC */ - hook.type = efm32_irq_type_acmp; - hook.unit = unitNumber; - hook.cbFunc = rt_hw_acmp_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); + /* Config interrupt and NVIC */ + hook.type = efm32_irq_type_acmp; + hook.unit = unitNumber; + hook.cbFunc = rt_hw_acmp_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); - return acmp; - } while(0); + return acmp; + } while(0); - if (acmp) - { - rt_free(acmp); - } - rt_kprintf("ACMP: Init failed!\n"); - return RT_NULL; + if (acmp) + { + rt_free(acmp); + } + rt_kprintf("ACMP: Init failed!\n"); + return RT_NULL; } /***************************************************************************//** @@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init( ******************************************************************************/ void rt_hw_acmp_init(void) { - struct efm32_acmp_device_t *acmp; + struct efm32_acmp_device_t *acmp; #ifdef RT_USING_ACMP0 - if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL) - { - rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp); - } + if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL) + { + rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp); + } #endif #ifdef RT_USING_ACMP1 - if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL) - { - rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp); - } + if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL) + { + rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp); + } #endif } @@ -369,50 +369,50 @@ void rt_hw_acmp_init(void) ******************************************************************************/ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq) { - if (!hfperFreq) - { - hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); + if (!hfperFreq) + { + hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER); - /* Just in case, make sure we get non-zero freq for below calculation */ - if (!hfperFreq) - { - hfperFreq = 1; - } - } + /* Just in case, make sure we get non-zero freq for below calculation */ + if (!hfperFreq) + { + hfperFreq = 1; + } + } - /* Determine number of HFPERCLK cycle >= 10us */ - if (4 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime4; - } - else if (8 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime8; - } - else if (16 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime16; - } - else if (32 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime32; - } - else if (64 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime64; - } - else if (128 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime128; - } - else if (256 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime256; - } - else if (512 * 1000000 / hfperFreq > 10) - { - return acmpWarmTime512; - } + /* Determine number of HFPERCLK cycle >= 10us */ + if (4 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime4; + } + else if (8 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime8; + } + else if (16 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime16; + } + else if (32 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime32; + } + else if (64 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime64; + } + else if (128 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime128; + } + else if (256 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime256; + } + else if (512 * 1000000 / hfperFreq > 10) + { + return acmpWarmTime512; + } } #endif diff --git a/bsp/efm32/drv_acmp.h b/bsp/efm32/drv_acmp.h index 50b4738afc..fd7f858669 100644 --- a/bsp/efm32/drv_acmp.h +++ b/bsp/efm32/drv_acmp.h @@ -23,24 +23,24 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_acmp_device_t { - ACMP_TypeDef *acmp_device; - efm32_irq_hook_t hook; + ACMP_TypeDef *acmp_device; + efm32_irq_hook_t hook; }; struct efm32_acmp_output_t { - rt_uint32_t location; - rt_bool_t enable; - rt_bool_t invert; + rt_uint32_t location; + rt_bool_t enable; + rt_bool_t invert; }; struct efm32_acmp_control_t { - ACMP_Init_TypeDef *init; - ACMP_Channel_TypeDef posInput; - ACMP_Channel_TypeDef negInput; - struct efm32_acmp_output_t *output; - efm32_irq_hook_t hook; + ACMP_Init_TypeDef *init; + ACMP_Channel_TypeDef posInput; + ACMP_Channel_TypeDef negInput; + struct efm32_acmp_output_t *output; + efm32_irq_hook_t hook; }; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/drv_adc.c b/bsp/efm32/drv_adc.c index e1eeafb36e..2a072507e0 100644 --- a/bsp/efm32/drv_adc.c +++ b/bsp/efm32/drv_adc.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_adc.c - * @brief ADC driver of RT-Thread RTOS for EFM32 + * @file drv_adc.c + * @brief ADC driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ /***************************************************************************//** @@ -29,7 +29,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_ADC_DEBUG -#define adc_debug(format,args...) rt_kprintf(format, ##args) +#define adc_debug(format,args...) rt_kprintf(format, ##args) #else #define adc_debug(format,args...) #endif @@ -71,132 +71,132 @@ static rt_uint32_t adcErrataShift = 0; * No need to load the calibration values after the function returns. ******************************************************************************/ rt_uint32_t efm32_adc_calibration( - ADC_TypeDef *adc, - ADC_Ref_TypeDef ref, - ADC_SingleInput_TypeDef input) + ADC_TypeDef *adc, + ADC_Ref_TypeDef ref, + ADC_SingleInput_TypeDef input) { - rt_uint32_t cal; - rt_int32_t sample; - rt_int8_t high, mid, low, tmp; - ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT; + rt_uint32_t cal; + rt_int32_t sample; + rt_int8_t high, mid, low, tmp; + ADC_InitSingle_TypeDef singleInit = ADC_INITSINGLE_DEFAULT; - /* Init for single conversion use, measure diff 0 with selected reference. */ - singleInit.reference = ref; - singleInit.input = adcSingleInpDiff0; - singleInit.acqTime = adcAcqTime32; - singleInit.diff = true; - /* Enable oversampling rate */ - singleInit.resolution = adcResOVS; - ADC_InitSingle(adc, &singleInit); + /* Init for single conversion use, measure diff 0 with selected reference. */ + singleInit.reference = ref; + singleInit.input = adcSingleInpDiff0; + singleInit.acqTime = adcAcqTime32; + singleInit.diff = true; + /* Enable oversampling rate */ + singleInit.resolution = adcResOVS; + ADC_InitSingle(adc, &singleInit); - /* ADC is now set up for offset calibration */ - /* Offset calibration register is a 7 bit signed 2's complement value. */ - /* Use unsigned indexes for binary search, and convert when calibration */ - /* register is written to. */ - high = 63; - low = -64; + /* ADC is now set up for offset calibration */ + /* Offset calibration register is a 7 bit signed 2's complement value. */ + /* Use unsigned indexes for binary search, and convert when calibration */ + /* register is written to. */ + high = 63; + low = -64; - /* Do binary search for offset calibration*/ - while (low < high) - { - /* Calculate midpoint */ - mid = low + (high - low) / 2; + /* Do binary search for offset calibration*/ + while (low < high) + { + /* Calculate midpoint */ + mid = low + (high - low) / 2; - /* Midpoint is converted to 2's complement and written to both scan and */ - /* single calibration registers */ - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK); - tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid; - cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT; - cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT; - adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp); - adc->CAL = cal; + /* Midpoint is converted to 2's complement and written to both scan and */ + /* single calibration registers */ + cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK); + tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid; + cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT; + cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT; + adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp); + adc->CAL = cal; - /* Do a conversion */ - ADC_Start(adc, adcStartSingle); + /* Do a conversion */ + ADC_Start(adc, adcStartSingle); - /* Wait while conversion is active */ - while (adc->STATUS & ADC_STATUS_SINGLEACT) ; + /* Wait while conversion is active */ + while (adc->STATUS & ADC_STATUS_SINGLEACT) ; - /* Get ADC result */ - sample = ADC_DataSingleGet(adc); + /* Get ADC result */ + sample = ADC_DataSingleGet(adc); - /* Check result and decide in which part of to repeat search */ - /* Calibration register has negative effect on result */ - if (sample < 0) - { - /* Repeat search in bottom half. */ - high = mid; - } - else if (sample > 0) - { - /* Repeat search in top half. */ - low = mid + 1; - } - else - { - /* Found it, exit while loop */ - break; - } - } - adc_debug("adc->CAL = %x\n", adc->CAL); + /* Check result and decide in which part of to repeat search */ + /* Calibration register has negative effect on result */ + if (sample < 0) + { + /* Repeat search in bottom half. */ + high = mid; + } + else if (sample > 0) + { + /* Repeat search in top half. */ + low = mid + 1; + } + else + { + /* Found it, exit while loop */ + break; + } + } + adc_debug("adc->CAL = %x\n", adc->CAL); - /* Now do gain calibration, only input and diff settings needs to be changed */ - adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK); - adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT); - adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT); + /* Now do gain calibration, only input and diff settings needs to be changed */ + adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK); + adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT); + adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT); - /* ADC is now set up for gain calibration */ - /* Gain calibration register is a 7 bit unsigned value. */ - high = 127; - low = 0; + /* ADC is now set up for gain calibration */ + /* Gain calibration register is a 7 bit unsigned value. */ + high = 127; + low = 0; - /* Do binary search for gain calibration */ - while (low < high) - { - /* Calculate midpoint and write to calibration register */ - mid = low + (high - low) / 2; + /* Do binary search for gain calibration */ + while (low < high) + { + /* Calculate midpoint and write to calibration register */ + mid = low + (high - low) / 2; - /* Midpoint is converted to 2's complement */ - cal = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK); - cal |= mid << _ADC_CAL_SINGLEGAIN_SHIFT; - cal |= mid << _ADC_CAL_SCANGAIN_SHIFT; - adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid); - adc->CAL = cal; + /* Midpoint is converted to 2's complement */ + cal = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK); + cal |= mid << _ADC_CAL_SINGLEGAIN_SHIFT; + cal |= mid << _ADC_CAL_SCANGAIN_SHIFT; + adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid); + adc->CAL = cal; - /* Do a conversion */ - ADC_Start(adc, adcStartSingle); + /* Do a conversion */ + ADC_Start(adc, adcStartSingle); - /* Wait while conversion is active */ - while (adc->STATUS & ADC_STATUS_SINGLEACT) ; + /* Wait while conversion is active */ + while (adc->STATUS & ADC_STATUS_SINGLEACT) ; - /* Get ADC result */ - sample = ADC_DataSingleGet(adc); + /* Get ADC result */ + sample = ADC_DataSingleGet(adc); - /* Check result and decide in which part to repeat search */ - /* Compare with a value atleast one LSB's less than top to avoid overshooting */ - /* Since oversampling is used, the result is 16 bits, but a couple of lsb's */ - /* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */ - /* is in turn 0xffe0 in the 16 bit result. */ - /* Calibration register has positive effect on result */ - if (sample > 0xffd0) - { - /* Repeat search in bottom half. */ - high = mid; - } - else if (sample < 0xffd0) - { - /* Repeat search in top half. */ - low = mid + 1; - } - else - { - /* Found it, exit while loop */ - break; - } - } - adc_debug("adc->CAL = %x\n", adc->CAL); + /* Check result and decide in which part to repeat search */ + /* Compare with a value atleast one LSB's less than top to avoid overshooting */ + /* Since oversampling is used, the result is 16 bits, but a couple of lsb's */ + /* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */ + /* is in turn 0xffe0 in the 16 bit result. */ + /* Calibration register has positive effect on result */ + if (sample > 0xffd0) + { + /* Repeat search in bottom half. */ + high = mid; + } + else if (sample < 0xffd0) + { + /* Repeat search in top half. */ + low = mid + 1; + } + else + { + /* Found it, exit while loop */ + break; + } + } + adc_debug("adc->CAL = %x\n", adc->CAL); - return adc->CAL; + return adc->CAL; } /***************************************************************************//** @@ -217,52 +217,52 @@ rt_uint32_t efm32_adc_calibration( * DMA channel ******************************************************************************/ void efm32_adc_cfg_dma( - ADC_TypeDef *adc_device, - rt_uint8_t mode, - rt_uint8_t channel) + ADC_TypeDef *adc_device, + rt_uint8_t mode, + rt_uint8_t channel) { - DMA_CfgChannel_TypeDef chnlCfg; - DMA_CfgDescr_TypeDef descrCfg; + DMA_CfgChannel_TypeDef chnlCfg; + DMA_CfgDescr_TypeDef descrCfg; - if (channel == (rt_uint8_t)EFM32_NO_DMA) - { - return; - } + if (channel == (rt_uint8_t)EFM32_NO_DMA) + { + return; + } - /* Set up DMA channel */ - chnlCfg.highPri = false; - chnlCfg.enableInt = false; - if (adc_device == ADC0) - { - switch (mode & ADC_MASK_MODE) - { - case ADC_MODE_SINGLE: - chnlCfg.select = DMAREQ_ADC0_SINGLE; - break; + /* Set up DMA channel */ + chnlCfg.highPri = false; + chnlCfg.enableInt = false; + if (adc_device == ADC0) + { + switch (mode & ADC_MASK_MODE) + { + case ADC_MODE_SINGLE: + chnlCfg.select = DMAREQ_ADC0_SINGLE; + break; - case ADC_MODE_SCAN: - chnlCfg.select = DMAREQ_ADC0_SCAN; - break; + case ADC_MODE_SCAN: + chnlCfg.select = DMAREQ_ADC0_SCAN; + break; - default: - return; - } - } - else - { - // TODO: Any other channel? - return; - } - chnlCfg.cb = RT_NULL; - DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg); + default: + return; + } + } + else + { + // TODO: Any other channel? + return; + } + chnlCfg.cb = RT_NULL; + DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg); - /* Setting up DMA channel descriptor */ - descrCfg.dstInc = dmaDataInc4; - descrCfg.srcInc = dmaDataIncNone; - descrCfg.size = dmaDataSize4; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg); + /* Setting up DMA channel descriptor */ + descrCfg.dstInc = dmaDataInc4; + descrCfg.srcInc = dmaDataIncNone; + descrCfg.size = dmaDataSize4; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg); } /***************************************************************************//** @@ -289,38 +289,38 @@ void efm32_adc_cfg_dma( * Pointer to ADC results buffer ******************************************************************************/ void efm32_adc_on_dma( - ADC_TypeDef *adc_device, - rt_uint8_t mode, - rt_uint8_t count, - rt_uint8_t channel, - void *buffer) + ADC_TypeDef *adc_device, + rt_uint8_t mode, + rt_uint8_t count, + rt_uint8_t channel, + void *buffer) { - switch (mode & ADC_MASK_MODE) - { - case ADC_MODE_SINGLE: - /* Activate DMA */ - DMA_ActivateBasic( - (rt_uint32_t)channel, - true, - false, - buffer, - (void *)&(adc_device->SINGLEDATA), - count - 1); - break; + switch (mode & ADC_MASK_MODE) + { + case ADC_MODE_SINGLE: + /* Activate DMA */ + DMA_ActivateBasic( + (rt_uint32_t)channel, + true, + false, + buffer, + (void *)&(adc_device->SINGLEDATA), + count - 1); + break; - case ADC_MODE_SCAN: - DMA_ActivateBasic( - (rt_uint32_t)channel, - true, - false, - buffer, - (void *)&(adc_device->SCANDATA), - count - 1); - break; + case ADC_MODE_SCAN: + DMA_ActivateBasic( + (rt_uint32_t)channel, + true, + false, + buffer, + (void *)&(adc_device->SCANDATA), + count - 1); + break; - default: - return; - } + default: + return; + } } /***************************************************************************//** @@ -339,468 +339,468 @@ void efm32_adc_on_dma( ******************************************************************************/ static rt_err_t rt_adc_init(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - rt_uint32_t temp; + rt_uint32_t temp; - struct efm32_adc_device_t *adc; + struct efm32_adc_device_t *adc; - adc = (struct efm32_adc_device_t *)(dev->user_data); + adc = (struct efm32_adc_device_t *)(dev->user_data); - temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH); + temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH); - adc_debug("adc->CAL = %x\n", temp); - return RT_EOK; + adc_debug("adc->CAL = %x\n", temp); + return RT_EOK; } /***************************************************************************//** * @brief - * Configure ADC device + * Configure ADC device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] cmd - * ADC control command + * ADC control command * * @param[in] args - * Arguments + * Arguments * * @return - * Error code + * Error code ******************************************************************************/ static rt_err_t rt_adc_control( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_adc_device_t *adc; + struct efm32_adc_device_t *adc; - adc = (struct efm32_adc_device_t *)(dev->user_data); + adc = (struct efm32_adc_device_t *)(dev->user_data); - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; - break; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; + break; - case RT_DEVICE_CTRL_RESUME: - { - /* Resume device */ - struct efm32_adc_result_t *control = \ - (struct efm32_adc_result_t *)args; + case RT_DEVICE_CTRL_RESUME: + { + /* Resume device */ + struct efm32_adc_result_t *control = \ + (struct efm32_adc_result_t *)args; - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - switch (control->mode) - { - case ADC_MODE_SINGLE: - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - control->buffer); - } - ADC_Start(adc->adc_device, adcStartSingle); - break; + switch (control->mode) + { + case ADC_MODE_SINGLE: + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + control->buffer); + } + ADC_Start(adc->adc_device, adcStartSingle); + break; - case ADC_MODE_SCAN: - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - control->buffer); - } - ADC_Start(adc->adc_device, adcStartScan); - break; + case ADC_MODE_SCAN: + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + control->buffer); + } + ADC_Start(adc->adc_device, adcStartScan); + break; - case ADC_MODE_TAILGATE: - { - void *index = control->buffer; + case ADC_MODE_TAILGATE: + { + void *index = control->buffer; - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - index); - index += adc->scanCount; - } - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - index); - index += adc->singleCount; - } - ADC_Start(adc->adc_device, adcStartScanAndSingle); - } + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + index); + index += adc->scanCount; + } + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + index); + index += adc->singleCount; + } + ADC_Start(adc->adc_device, adcStartScanAndSingle); + } - break; + break; - default: - return -RT_ERROR; - } - } - break; + default: + return -RT_ERROR; + } + } + break; - case RT_DEVICE_CTRL_ADC_MODE: - { - /* change device setting */ - struct efm32_adc_control_t *control = \ - (struct efm32_adc_control_t *)args; + case RT_DEVICE_CTRL_ADC_MODE: + { + /* change device setting */ + struct efm32_adc_control_t *control = \ + (struct efm32_adc_control_t *)args; - switch (control->mode) - { - case ADC_MODE_SINGLE: - ADC_InitSingle(adc->adc_device, control->single.init); - break; + switch (control->mode) + { + case ADC_MODE_SINGLE: + ADC_InitSingle(adc->adc_device, control->single.init); + break; - case ADC_MODE_SCAN: - ADC_InitScan(adc->adc_device, control->scan.init); - break; + case ADC_MODE_SCAN: + ADC_InitScan(adc->adc_device, control->scan.init); + break; - case ADC_MODE_TAILGATE: - ADC_InitSingle(adc->adc_device, control->single.init); - ADC_InitScan(adc->adc_device, control->scan.init); - break; + case ADC_MODE_TAILGATE: + ADC_InitSingle(adc->adc_device, control->single.init); + ADC_InitScan(adc->adc_device, control->scan.init); + break; - default: - return -RT_ERROR; - } + default: + return -RT_ERROR; + } - if (control->mode == ADC_MODE_TAILGATE) - { - adc->mode = ADC_MODE_TAILGATE; - } - else - { - adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE; - adc->mode |= control->mode; - } - if ((control->mode == ADC_MODE_TAILGATE) || \ - (control->mode == ADC_MODE_SINGLE)) - { - if (control->single.init->rep) - { - adc->mode |= ADC_OP_SINGLE_REPEAT; - } - adc->singleCount = control->single.count; - adc->singleDmaChannel = control->single.dmaChannel; - efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel); - } - if ((control->mode == ADC_MODE_TAILGATE) || \ - (control->mode == ADC_MODE_SCAN)) - { - if (control->scan.init->rep) - { - adc->mode |= ADC_OP_SCAN_REPEAT; - } - adc->scanCount = control->scan.count; - adc->scanDmaChannel = control->scan.dmaChannel; - efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel); - } - } - break; + if (control->mode == ADC_MODE_TAILGATE) + { + adc->mode = ADC_MODE_TAILGATE; + } + else + { + adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE; + adc->mode |= control->mode; + } + if ((control->mode == ADC_MODE_TAILGATE) || \ + (control->mode == ADC_MODE_SINGLE)) + { + if (control->single.init->rep) + { + adc->mode |= ADC_OP_SINGLE_REPEAT; + } + adc->singleCount = control->single.count; + adc->singleDmaChannel = control->single.dmaChannel; + efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel); + } + if ((control->mode == ADC_MODE_TAILGATE) || \ + (control->mode == ADC_MODE_SCAN)) + { + if (control->scan.init->rep) + { + adc->mode |= ADC_OP_SCAN_REPEAT; + } + adc->scanCount = control->scan.count; + adc->scanDmaChannel = control->scan.dmaChannel; + efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel); + } + } + break; - case RT_DEVICE_CTRL_ADC_RESULT: - { - struct efm32_adc_result_t *control = \ - (struct efm32_adc_result_t *)args; + case RT_DEVICE_CTRL_ADC_RESULT: + { + struct efm32_adc_result_t *control = \ + (struct efm32_adc_result_t *)args; - switch (control->mode) - { - case ADC_MODE_SINGLE: - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SINGLE_REPEAT) - { - if (!(DMA->IF & (1 << adc->singleDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - control->buffer); - } - while (!(DMA->IF & (1 << adc->singleDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - *((rt_uint32_t *)control->buffer) = \ - ADC_DataSingleGet(adc->adc_device) << adcErrataShift; - } - break; + switch (control->mode) + { + case ADC_MODE_SINGLE: + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SINGLE_REPEAT) + { + if (!(DMA->IF & (1 << adc->singleDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + control->buffer); + } + while (!(DMA->IF & (1 << adc->singleDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + *((rt_uint32_t *)control->buffer) = \ + ADC_DataSingleGet(adc->adc_device) << adcErrataShift; + } + break; - case ADC_MODE_SCAN: - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SCAN_REPEAT) - { - if (!(DMA->IF & (1 << adc->scanDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - control->buffer); - } - while (!(DMA->IF & (1 << adc->scanDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - *((rt_uint32_t *)control->buffer) = \ - ADC_DataScanGet(adc->adc_device) << adcErrataShift; - } - break; + case ADC_MODE_SCAN: + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SCAN_REPEAT) + { + if (!(DMA->IF & (1 << adc->scanDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + control->buffer); + } + while (!(DMA->IF & (1 << adc->scanDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + *((rt_uint32_t *)control->buffer) = \ + ADC_DataScanGet(adc->adc_device) << adcErrataShift; + } + break; - case ADC_MODE_TAILGATE: - { - void *index = control->buffer; + case ADC_MODE_TAILGATE: + { + void *index = control->buffer; - if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ - !(adc->mode & ADC_OP_SCAN_REPEAT)) - { - index += adc->scanCount; - } - if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ - !(adc->mode & ADC_OP_SINGLE_REPEAT)) - { - index += adc->singleCount; - } + if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ + !(adc->mode & ADC_OP_SCAN_REPEAT)) + { + index += adc->scanCount; + } + if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \ + !(adc->mode & ADC_OP_SINGLE_REPEAT)) + { + index += adc->singleCount; + } - if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SCAN_REPEAT) - { - if (!(DMA->IF & (1 << adc->scanDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->scanCount, - adc->scanDmaChannel, - index); - index += adc->scanCount; - } - while (!(DMA->IF & (1 << adc->scanDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); - *(rt_uint32_t *)(index++) = \ - ADC_DataScanGet(adc->adc_device) << adcErrataShift; - } - if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) - { - if (adc->mode & ADC_OP_SINGLE_REPEAT) - { - if (!(DMA->IF & (1 << adc->singleDmaChannel))) - { - efm32_adc_on_dma( - adc->adc_device, - control->mode, - adc->singleCount, - adc->singleDmaChannel, - index); - index += adc->singleCount; - } - while (!(DMA->IF & (1 << adc->singleDmaChannel))); - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - } - } - else - { - while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); - *(rt_uint32_t *)(index++) = \ - ADC_DataSingleGet(adc->adc_device) << adcErrataShift; - } - } - break; + if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SCAN_REPEAT) + { + if (!(DMA->IF & (1 << adc->scanDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->scanCount, + adc->scanDmaChannel, + index); + index += adc->scanCount; + } + while (!(DMA->IF & (1 << adc->scanDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SCANACT); + *(rt_uint32_t *)(index++) = \ + ADC_DataScanGet(adc->adc_device) << adcErrataShift; + } + if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) + { + if (adc->mode & ADC_OP_SINGLE_REPEAT) + { + if (!(DMA->IF & (1 << adc->singleDmaChannel))) + { + efm32_adc_on_dma( + adc->adc_device, + control->mode, + adc->singleCount, + adc->singleDmaChannel, + index); + index += adc->singleCount; + } + while (!(DMA->IF & (1 << adc->singleDmaChannel))); + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + } + } + else + { + while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT); + *(rt_uint32_t *)(index++) = \ + ADC_DataSingleGet(adc->adc_device) << adcErrataShift; + } + } + break; - default: - return -RT_ERROR; - } - } - break; + default: + return -RT_ERROR; + } + } + break; - default: - return -RT_ERROR; - } + default: + return -RT_ERROR; + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** * @brief - * Register ADC device + * Register ADC device * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] name - * Device name + * Device name * * @param[in] flag - * Configuration flags + * Configuration flags * * @param[in] adc - * Pointer to ADC device descriptor + * Pointer to ADC device descriptor * * @return - * Error code + * Error code ******************************************************************************/ rt_err_t rt_hw_adc_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_adc_device_t *adc) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_adc_device_t *adc) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; /* fixme: should be adc type */ - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_adc_init; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_adc_control; - device->user_data = adc; + device->type = RT_Device_Class_Char; /* fixme: should be adc type */ + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_adc_init; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = rt_adc_control; + device->user_data = adc; - /* register a character device */ - return rt_device_register(device, name, flag); + /* register a character device */ + return rt_device_register(device, name, flag); } /***************************************************************************//** * @brief - * Initialize the specified ADC unit + * Initialize the specified ADC unit * * @details * * @note * * @param[in] device - * Pointer to device descriptor + * Pointer to device descriptor * * @param[in] unitNumber - * Unit number + * Unit number * * @return - * Pointer to ADC device + * Pointer to ADC device ******************************************************************************/ static struct efm32_adc_device_t *rt_hw_adc_unit_init( - rt_device_t device, - rt_uint8_t unitNumber) + rt_device_t device, + rt_uint8_t unitNumber) { - struct efm32_adc_device_t *adc; - CMU_Clock_TypeDef adcClock; - ADC_Init_TypeDef init = ADC_INIT_DEFAULT; + struct efm32_adc_device_t *adc; + CMU_Clock_TypeDef adcClock; + ADC_Init_TypeDef init = ADC_INIT_DEFAULT; - do - { - /* Allocate device and set default value */ - adc = rt_malloc(sizeof(struct efm32_adc_device_t)); - if (adc == RT_NULL) - { - adc_debug("no memory for ADC%d driver\n", unitNumber); - break; - } - adc->mode = 0; - adc->singleCount = 0; - adc->singleDmaChannel = (rt_uint8_t)EFM32_NO_DMA; - adc->scanCount = 0; - adc->scanDmaChannel = (rt_uint8_t)EFM32_NO_DMA; + do + { + /* Allocate device and set default value */ + adc = rt_malloc(sizeof(struct efm32_adc_device_t)); + if (adc == RT_NULL) + { + adc_debug("no memory for ADC%d driver\n", unitNumber); + break; + } + adc->mode = 0; + adc->singleCount = 0; + adc->singleDmaChannel = (rt_uint8_t)EFM32_NO_DMA; + adc->scanCount = 0; + adc->scanDmaChannel = (rt_uint8_t)EFM32_NO_DMA; - /* Initialization */ - if (unitNumber >= ADC_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - adc->adc_device = ADC0; - adcClock = (CMU_Clock_TypeDef)cmuClock_ADC0; - break; + /* Initialization */ + if (unitNumber >= ADC_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + adc->adc_device = ADC0; + adcClock = (CMU_Clock_TypeDef)cmuClock_ADC0; + break; - default: - break; - } + default: + break; + } - /* Enable ADC clock */ - CMU_ClockEnable(adcClock, true); + /* Enable ADC clock */ + CMU_ClockEnable(adcClock, true); - /* Reset */ - ADC_Reset(adc->adc_device); + /* Reset */ + ADC_Reset(adc->adc_device); - /* Configure ADC */ - // TODO: Fixed oversampling rate? - init.ovsRateSel = adcOvsRateSel4096; - init.timebase = ADC_TimebaseCalc(0); - init.prescale = ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0); - ADC_Init(adc->adc_device, &init); + /* Configure ADC */ + // TODO: Fixed oversampling rate? + init.ovsRateSel = adcOvsRateSel4096; + init.timebase = ADC_TimebaseCalc(0); + init.prescale = ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0); + ADC_Init(adc->adc_device, &init); - return adc; - } while(0); + return adc; + } while(0); - if (adc) - { - rt_free(adc); - } - rt_kprintf("ADC: Init failed!\n"); - return RT_NULL; + if (adc) + { + rt_free(adc); + } + rt_kprintf("ADC: Init failed!\n"); + return RT_NULL; } /***************************************************************************//** * @brief - * Initialize all ADC module related hardware and register ADC device to kernel + * Initialize all ADC module related hardware and register ADC device to kernel * * @details * @@ -809,23 +809,23 @@ static struct efm32_adc_device_t *rt_hw_adc_unit_init( ******************************************************************************/ void rt_hw_adc_init(void) { - SYSTEM_ChipRevision_TypeDef chipRev; - struct efm32_adc_device_t *adc; + SYSTEM_ChipRevision_TypeDef chipRev; + struct efm32_adc_device_t *adc; #ifdef RT_USING_ADC0 - if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL) - { - rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc); - } + if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL) + { + rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc); + } #endif - /* ADC errata for rev B when using VDD as reference, need to multiply */ - /* result by 2 */ - SYSTEM_ChipRevisionGet(&chipRev); - if ((chipRev.major == 0x01) && (chipRev.minor == 0x01)) - { - adcErrataShift = 1; - } + /* ADC errata for rev B when using VDD as reference, need to multiply */ + /* result by 2 */ + SYSTEM_ChipRevisionGet(&chipRev); + if ((chipRev.major == 0x01) && (chipRev.minor == 0x01)) + { + adcErrataShift = 1; + } } #endif diff --git a/bsp/efm32/drv_adc.h b/bsp/efm32/drv_adc.h index b3b81d94e1..f15d074835 100644 --- a/bsp/efm32/drv_adc.h +++ b/bsp/efm32/drv_adc.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_adc.h - * @brief ADC driver of RT-Thread RTOS for EFM32 + * @file drv_adc.h + * @brief ADC driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ #ifndef __DRV_ADC_H__ #define __DRV_ADC_H__ @@ -21,50 +21,50 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_adc_device_t { - ADC_TypeDef *adc_device; - rt_uint8_t mode; - rt_uint8_t singleCount; - rt_uint8_t singleDmaChannel; - rt_uint8_t scanCount; - rt_uint8_t scanDmaChannel; + ADC_TypeDef *adc_device; + rt_uint8_t mode; + rt_uint8_t singleCount; + rt_uint8_t singleDmaChannel; + rt_uint8_t scanCount; + rt_uint8_t scanDmaChannel; }; struct efm32_adc_control_single_t { - rt_uint8_t count; - rt_uint8_t dmaChannel; - ADC_InitSingle_TypeDef *init; + rt_uint8_t count; + rt_uint8_t dmaChannel; + ADC_InitSingle_TypeDef *init; }; struct efm32_adc_control_scan_t { - rt_uint8_t count; - rt_uint8_t dmaChannel; - ADC_InitScan_TypeDef *init; + rt_uint8_t count; + rt_uint8_t dmaChannel; + ADC_InitScan_TypeDef *init; }; struct efm32_adc_control_t { - rt_uint8_t mode; - struct efm32_adc_control_scan_t scan; - struct efm32_adc_control_single_t single; + rt_uint8_t mode; + struct efm32_adc_control_scan_t scan; + struct efm32_adc_control_single_t single; }; struct efm32_adc_result_t { - rt_uint8_t mode; - void *buffer; + rt_uint8_t mode; + void *buffer; }; /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define ADC_MODE_SINGLE (0x01) -#define ADC_MODE_SCAN (0x02) -#define ADC_MODE_TAILGATE (0x04) -#define ADC_OP_SINGLE_REPEAT (0x10) -#define ADC_OP_SCAN_REPEAT (0x20) -#define ADC_MASK_MODE (0x0f) -#define ADC_MASK_OP (0xf0) +#define ADC_MODE_SINGLE (0x01) +#define ADC_MODE_SCAN (0x02) +#define ADC_MODE_TAILGATE (0x04) +#define ADC_OP_SINGLE_REPEAT (0x10) +#define ADC_OP_SCAN_REPEAT (0x20) +#define ADC_MASK_MODE (0x0f) +#define ADC_MASK_OP (0xf0) /* Exported functions ------------------------------------------------------- */ void rt_hw_adc_init(void); diff --git a/bsp/efm32/drv_emu.c b/bsp/efm32/drv_emu.c index 9a5fc8e97e..18eeca1a43 100644 --- a/bsp/efm32/drv_emu.c +++ b/bsp/efm32/drv_emu.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_emu.c - * @brief EMU driver of RT-Thread RTOS for EFM32 + * @file drv_emu.c + * @brief EMU driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2012-02-21 onelife Initial creation for EFM32 + * Date Author Notes + * 2012-02-21 onelife Initial creation for EFM32 ******************************************************************************/ /***************************************************************************//** @@ -27,7 +27,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_EMU_DEBUG -#define emu_debug(format,args...) rt_kprintf(format, ##args) +#define emu_debug(format,args...) rt_kprintf(format, ##args) #else #define emu_debug(format,args...) #endif @@ -176,7 +176,7 @@ void emu_em4_enable(void) /***************************************************************************//** * @brief - * Initialize EMU module related hardware + * Initialize EMU module related hardware * * @details * @@ -213,22 +213,22 @@ void efm32_emu_init(void) break; } - /* init thread */ + /* init thread */ if (rt_thread_init( &emu_task.thread, "EMU", - emu_task_main_loop, (void *)&emu_task, + emu_task_main_loop, (void *)&emu_task, (void *)&emu_task.stack, sizeof(emu_task.stack), - RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK) + RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK) { break; } - /* startup */ - if (rt_thread_startup(&emu_task.thread) != RT_EOK) - { + /* startup */ + if (rt_thread_startup(&emu_task.thread) != RT_EOK) + { break; - } + } } while (0); rt_kprintf("EMU err: init failed!\n"); diff --git a/bsp/efm32/drv_emu.h b/bsp/efm32/drv_emu.h index 3e491665ba..df46264295 100644 --- a/bsp/efm32/drv_emu.h +++ b/bsp/efm32/drv_emu.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_emu.h - * @brief EMU driver of RT-Thread RTOS for EFM32 + * @file drv_emu.h + * @brief EMU driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-02-21 onelife Initial creation for EFM32 - * 2011-07-14 onelife Add multiple channels support for scan mode + * Date Author Notes + * 2011-02-21 onelife Initial creation for EFM32 + * 2011-07-14 onelife Add multiple channels support for scan mode ******************************************************************************/ #ifndef __DRV_EMU_H__ #define __DRV_EMU_H__ diff --git a/bsp/efm32/drv_ethernet.c b/bsp/efm32/drv_ethernet.c index e6bc25bbcc..db99de583a 100644 --- a/bsp/efm32/drv_ethernet.c +++ b/bsp/efm32/drv_ethernet.c @@ -1,11 +1,11 @@ /***************************************************************************//** - * @file drv_ethernet.c - * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART + * @file drv_ethernet.c + * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART * module - * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet + * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet * controller with SPI interface. * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -13,11 +13,11 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-06-22 onelife Initial creation for using EFM32 USART module - * 2011-07-25 onelife Add lock (semaphore) to prevent simultaneously + * Date Author Notes + * 2011-06-22 onelife Initial creation for using EFM32 USART module + * 2011-07-25 onelife Add lock (semaphore) to prevent simultaneously * access - * 2011-07-28 onelife Add get_ip() and update_ip() utilities + * 2011-07-28 onelife Add get_ip() and update_ip() utilities ******************************************************************************/ /***************************************************************************//** @@ -38,21 +38,21 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef EFM32_ETHERNET_DEBUG -#define eth_debug(format,args...) rt_kprintf(format, ##args) +#define eth_debug(format,args...) rt_kprintf(format, ##args) #else #define eth_debug(format,args...) #endif /* Private constants ---------------------------------------------------------*/ -static const rt_uint8_t eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT; +static const rt_uint8_t eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT; /* Private variables ---------------------------------------------------------*/ -static struct eth_device eth_dev; -static struct rt_semaphore ethLock; -static rt_uint8_t ethBank; -static rt_uint16_t ethNxtPkt; -static rt_device_t spi = RT_NULL; -static rt_bool_t ethAutoCs = true; +static struct eth_device eth_dev; +static struct rt_semaphore ethLock; +static rt_uint8_t ethBank; +static rt_uint16_t ethNxtPkt; +static rt_device_t spi = RT_NULL; +static rt_bool_t ethAutoCs = true; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -69,17 +69,17 @@ static rt_bool_t ethAutoCs = true; ******************************************************************************/ static void efm_eth_cs(rt_uint8_t enable) { - if (!ethAutoCs) - { - if (enable) - { - GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN); - } - else - { - GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN); - } - } + if (!ethAutoCs) + { + if (enable) + { + GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN); + } + else + { + GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN); + } + } } /***************************************************************************//** @@ -103,93 +103,93 @@ static void efm_eth_cs(rt_uint8_t enable) * Error code ******************************************************************************/ static rt_err_t efm_eth_cmd( - rt_uint8_t cmd, - rt_uint8_t addr, - rt_uint8_t *data) + rt_uint8_t cmd, + rt_uint8_t addr, + rt_uint8_t *data) { - RT_ASSERT(spi != RT_NULL); + RT_ASSERT(spi != RT_NULL); - rt_uint8_t buf_ins[6], buf_res[2]; - rt_uint8_t len_ins, len_res; + rt_uint8_t buf_ins[6], buf_res[2]; + rt_uint8_t len_ins, len_res; - len_ins = 0; - do - { - /* Build instruction buffer */ - /* Check if need to read back */ - if (cmd == ENC28J60_READ_CTRL_REG) - { - buf_ins[len_ins++] = 1; /* Instruction length */ - } - /* Byte 0: Check if no address section */ - if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \ - cmd == ENC28J60_SOFT_RESET) - { - buf_ins[len_ins++] = cmd; - } - else - { - buf_ins[len_ins++] = cmd | (addr & ADDR_MASK); - } - /* Byte 1: Check if data section is present */ - if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \ - cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM) - { - buf_ins[len_ins++] = *data; - } + len_ins = 0; + do + { + /* Build instruction buffer */ + /* Check if need to read back */ + if (cmd == ENC28J60_READ_CTRL_REG) + { + buf_ins[len_ins++] = 1; /* Instruction length */ + } + /* Byte 0: Check if no address section */ + if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \ + cmd == ENC28J60_SOFT_RESET) + { + buf_ins[len_ins++] = cmd; + } + else + { + buf_ins[len_ins++] = cmd | (addr & ADDR_MASK); + } + /* Byte 1: Check if data section is present */ + if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \ + cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM) + { + buf_ins[len_ins++] = *data; + } - /* Check if reading */ - if (cmd == ENC28J60_READ_CTRL_REG) - { - *(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res; /* Pointer to RX buffer */ - len_ins += 4; + /* Check if reading */ + if (cmd == ENC28J60_READ_CTRL_REG) + { + *(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res; /* Pointer to RX buffer */ + len_ins += 4; - /* Check if MAC or MII register */ - if (addr & SPRD_MASK) - { - len_res = 2; - } - else - { - len_res = 1; - } + /* Check if MAC or MII register */ + if (addr & SPRD_MASK) + { + len_res = 2; + } + else + { + len_res = 1; + } - /* Send command and get response */ - efm_eth_cs(1); - if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0) - { - break; - } - *data = buf_res[len_res - 1]; -// eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res); -// eth_debug("ETH: ** read RX %x %x (%d)\n", -// buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4], -// buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9], -// len_res); - } - else - { -// eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0], -// buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5], -// len_ins); - /* Send command and get response */ - efm_eth_cs(1); - if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0) - { - break; - } - } + /* Send command and get response */ + efm_eth_cs(1); + if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0) + { + break; + } + *data = buf_res[len_res - 1]; +// eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res); +// eth_debug("ETH: ** read RX %x %x (%d)\n", +// buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4], +// buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9], +// len_res); + } + else + { +// eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0], +// buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5], +// len_ins); + /* Send command and get response */ + efm_eth_cs(1); + if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0) + { + break; + } + } - if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM)) - { - efm_eth_cs(0); - } - return RT_EOK; - } while(0); + if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM)) + { + efm_eth_cs(0); + } + return RT_EOK; + } while(0); - eth_debug("ETH: Send command failed!\n"); - efm_eth_cs(0); - return -RT_ERROR; + eth_debug("ETH: Send command failed!\n"); + efm_eth_cs(0); + return -RT_ERROR; } /***************************************************************************//** @@ -213,37 +213,37 @@ static rt_err_t efm_eth_cmd( * Error code ******************************************************************************/ static rt_err_t efm_eth_sendCmd( - rt_uint8_t cmd, - rt_uint8_t addr, - rt_uint8_t *data) + rt_uint8_t cmd, + rt_uint8_t addr, + rt_uint8_t *data) { - rt_err_t ret; + rt_err_t ret; - eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data); - do - { - /* Change bank */ - if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1))) - { - rt_uint8_t temp; + eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data); + do + { + /* Change bank */ + if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1))) + { + rt_uint8_t temp; - if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK) - { - break; - } - temp &= 0xFC; - ethBank = (addr & BANK_MASK); - temp |= ethBank >> BANK_SHIFT; - if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK) - { - break; - } - } - /* Send command */ - ret = efm_eth_cmd(cmd, addr, data); - } while(0); + if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK) + { + break; + } + temp &= 0xFC; + ethBank = (addr & BANK_MASK); + temp |= ethBank >> BANK_SHIFT; + if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK) + { + break; + } + } + /* Send command */ + ret = efm_eth_cmd(cmd, addr, data); + } while(0); - return ret; + return ret; } /***************************************************************************//** @@ -262,11 +262,11 @@ static rt_err_t efm_eth_sendCmd( ******************************************************************************/ static rt_uint8_t efm_eth_readReg(rt_uint8_t addr) { - rt_uint8_t data; + rt_uint8_t data; - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data); + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data); - return data; + return data; } /***************************************************************************//** @@ -285,7 +285,7 @@ static rt_uint8_t efm_eth_readReg(rt_uint8_t addr) ******************************************************************************/ static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data) { - efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data); + efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data); } /***************************************************************************//** @@ -304,25 +304,25 @@ static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data) ******************************************************************************/ static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr) { - rt_uint16_t ret; + rt_uint16_t ret; - eth_debug("ETH: *** read PHY %x\n", addr); + eth_debug("ETH: *** read PHY %x\n", addr); - /* Set PHY register address */ - efm_eth_writeReg(MIREGADR, addr); + /* Set PHY register address */ + efm_eth_writeReg(MIREGADR, addr); - /* Start read operation */ - efm_eth_writeReg(MICMD, MICMD_MIIRD); - /* Waiting for at least 10.24 uS */ - while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); + /* Start read operation */ + efm_eth_writeReg(MICMD, MICMD_MIIRD); + /* Waiting for at least 10.24 uS */ + while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); - /* Stop read operation */ - efm_eth_writeReg(MICMD, 0x00); + /* Stop read operation */ + efm_eth_writeReg(MICMD, 0x00); - /* Get the result */ - ret = (rt_uint16_t)efm_eth_readReg(MIRDL); - ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8; - return ret; + /* Get the result */ + ret = (rt_uint16_t)efm_eth_readReg(MIRDL); + ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8; + return ret; } /***************************************************************************//** @@ -341,82 +341,82 @@ static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr) ******************************************************************************/ static void efm_eth_writePhy(rt_uint8_t addr, rt_uint16_t data) { - eth_debug("ETH: *** write PHY %x (%x)\n", addr, data); + eth_debug("ETH: *** write PHY %x (%x)\n", addr, data); - /* Set PHY register address */ - efm_eth_writeReg(MIREGADR, addr); + /* Set PHY register address */ + efm_eth_writeReg(MIREGADR, addr); - /* Set data */ - efm_eth_writeReg(MIWRL, data); - efm_eth_writeReg(MIWRH, data >> 8); - /* Waiting for at least 10.24 uS */ - while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); + /* Set data */ + efm_eth_writeReg(MIWRL, data); + efm_eth_writeReg(MIWRH, data >> 8); + /* Waiting for at least 10.24 uS */ + while(efm_eth_readReg(MISTAT) & MISTAT_BUSY); } /***************************************************************************//** * @brief - * Interrupt handler of Ethernet device + * Interrupt handler of Ethernet device * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void efm_eth_isr(rt_device_t dev) { - rt_uint8_t reg_eir, data; - volatile rt_uint8_t cnt; + rt_uint8_t reg_eir, data; + volatile rt_uint8_t cnt; - /* Disable RX and other interrutps */ - data = EIE_PKTIE | EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + /* Disable RX and other interrutps */ + data = EIE_PKTIE | EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - /* Get interrupt flag */ - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir); + /* Get interrupt flag */ + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir); - data = 0; - /* DMA completed */ - if (reg_eir & EIR_DMAIF) - { - data |= (rt_uint8_t)EIR_DMAIF; - } - /* Link Changed */ - if (reg_eir & EIR_LINKIF) - { - /* Read PHIR to clear the flag */ - efm_eth_readPhy(PHIR); - } - /* TX done */ - if (reg_eir & EIR_TXIF) - { - data |= (rt_uint8_t)EIR_TXIF; - } - /* TX error */ - if (reg_eir & EIR_TXERIF) - { - data |= (rt_uint8_t)EIR_TXERIF; - } - /* RX error */ - if (reg_eir & EIR_RXERIF) - { - data |= (rt_uint8_t)EIR_RXERIF; - } - /* Clear flags */ - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + data = 0; + /* DMA completed */ + if (reg_eir & EIR_DMAIF) + { + data |= (rt_uint8_t)EIR_DMAIF; + } + /* Link Changed */ + if (reg_eir & EIR_LINKIF) + { + /* Read PHIR to clear the flag */ + efm_eth_readPhy(PHIR); + } + /* TX done */ + if (reg_eir & EIR_TXIF) + { + data |= (rt_uint8_t)EIR_TXIF; + } + /* TX error */ + if (reg_eir & EIR_TXERIF) + { + data |= (rt_uint8_t)EIR_TXERIF; + } + /* RX error */ + if (reg_eir & EIR_RXERIF) + { + data |= (rt_uint8_t)EIR_RXERIF; + } + /* Clear flags */ + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - /* Get packet counter (Errata 6) */ - efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt); - if (cnt) - { - /* Inform Ethernet thread */ - eth_device_ready(ð_dev); - } + /* Get packet counter (Errata 6) */ + efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt); + if (cnt) + { + /* Inform Ethernet thread */ + eth_device_ready(ð_dev); + } - /* Enable other interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + /* Enable other interrupts */ + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); } /***************************************************************************//** @@ -435,119 +435,119 @@ void efm_eth_isr(rt_device_t dev) ******************************************************************************/ static rt_err_t efm_eth_init(rt_device_t dev) { - rt_uint16_t reg_phy; - rt_uint8_t data; + rt_uint16_t reg_phy; + rt_uint8_t data; - /* Reset chip select */ - efm_eth_cs(0); - /* Software reset */ - efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER); - /* Waiting for at least 1 ms (Errata 2) */ - rt_thread_delay(ETH_PERIOD_WAIT_INIT); - ethNxtPkt = RXSTART_INIT; - ethBank = 0; + /* Reset chip select */ + efm_eth_cs(0); + /* Software reset */ + efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER); + /* Waiting for at least 1 ms (Errata 2) */ + rt_thread_delay(ETH_PERIOD_WAIT_INIT); + ethNxtPkt = RXSTART_INIT; + ethBank = 0; - /* Init RX buffer */ - efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF); - efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8); - efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF); - efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8); - efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF); - efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8); + /* Init RX buffer */ + efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF); + efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8); + efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF); + efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8); + efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF); + efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8); - /* Init TX buffer */ - efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8); - efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF); - efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8); - efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); + /* Init TX buffer */ + efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8); + efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF); + efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8); + efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); - /* Init RX filters */ - /* For broadcast packets we allow only ARP packtets - All other packets should be unicast only for our mac (MAADR) + /* Init RX filters */ + /* For broadcast packets we allow only ARP packtets + All other packets should be unicast only for our mac (MAADR) - The pattern to match on is therefore - Type ETH.DST - ARP BROADCAST - 06 08 -- -- -- -- -- -- ff ff ff ff ff ff - These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex - Checksum for theses bytes is: f7 f9 */ - efm_eth_writeReg(EPMM0, 0x3f); - efm_eth_writeReg(EPMM1, 0x30); - efm_eth_writeReg(EPMCSL, 0xf9); - efm_eth_writeReg(EPMCSH, 0xf7); - efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN); - //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); - /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS) - pass after Power-on Reset or wake-up from Power-Down mode occurs */ + The pattern to match on is therefore + Type ETH.DST + ARP BROADCAST + 06 08 -- -- -- -- -- -- ff ff ff ff ff ff + These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex + Checksum for theses bytes is: f7 f9 */ + efm_eth_writeReg(EPMM0, 0x3f); + efm_eth_writeReg(EPMM1, 0x30); + efm_eth_writeReg(EPMCSL, 0xf9); + efm_eth_writeReg(EPMCSH, 0xf7); + efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN); + //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); + /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS) + pass after Power-on Reset or wake-up from Power-Down mode occurs */ - /* Init MAC */ - /* Enable RX, IEEE defined flow control */ - efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); - /* Enable padding to 60 bytes, CRC and frame length status reporting */ + /* Init MAC */ + /* Enable RX, IEEE defined flow control */ + efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); + /* Enable padding to 60 bytes, CRC and frame length status reporting */ #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); - efm_eth_writeReg(MACON4, MACON4_DEFER); + efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); + efm_eth_writeReg(MACON4, MACON4_DEFER); #else - efm_eth_writeReg(MACON3, \ - MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); + efm_eth_writeReg(MACON3, \ + MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); #endif - /* Set the maximum packet length */ - efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF); - efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8); - /* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */ + /* Set the maximum packet length */ + efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF); + efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8); + /* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */ #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MABBIPG, 0x12); + efm_eth_writeReg(MABBIPG, 0x12); #else - efm_eth_writeReg(MABBIPG, 0x15); + efm_eth_writeReg(MABBIPG, 0x15); #endif - /* Set inter-packet gap (non-back-to-back). - Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */ - efm_eth_writeReg(MAIPGL, 0x12); + /* Set inter-packet gap (non-back-to-back). + Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */ + efm_eth_writeReg(MAIPGL, 0x12); #if defined(ETH_HALF_DUPLEX) - efm_eth_writeReg(MAIPGH, 0x0C); - /* Set retransmission and collision window */ - efm_eth_writeReg(MACLCON1, 0x0F); - efm_eth_writeReg(MACLCON2, 0x37); + efm_eth_writeReg(MAIPGH, 0x0C); + /* Set retransmission and collision window */ + efm_eth_writeReg(MACLCON1, 0x0F); + efm_eth_writeReg(MACLCON2, 0x37); #endif - /* Set MAC address - NOTE: MAC address in ENC28J60 is byte-backward */ - efm_eth_writeReg(MAADR1, eth_addr[0]); - efm_eth_writeReg(MAADR2, eth_addr[1]); - efm_eth_writeReg(MAADR3, eth_addr[2]); - efm_eth_writeReg(MAADR4, eth_addr[3]); - efm_eth_writeReg(MAADR5, eth_addr[4]); - efm_eth_writeReg(MAADR6, eth_addr[5]); + /* Set MAC address + NOTE: MAC address in ENC28J60 is byte-backward */ + efm_eth_writeReg(MAADR1, eth_addr[0]); + efm_eth_writeReg(MAADR2, eth_addr[1]); + efm_eth_writeReg(MAADR3, eth_addr[2]); + efm_eth_writeReg(MAADR4, eth_addr[3]); + efm_eth_writeReg(MAADR5, eth_addr[4]); + efm_eth_writeReg(MAADR6, eth_addr[5]); - /* Init PHY */ + /* Init PHY */ #if defined(ETH_HALF_DUPLEX) - reg_phy = efm_eth_readPhy(PHCON2); - efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS); + reg_phy = efm_eth_readPhy(PHCON2); + efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS); #else - reg_phy = efm_eth_readPhy(PHCON1); - efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD); + reg_phy = efm_eth_readPhy(PHCON1); + efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD); #endif - /* LEDA: Display link status; - LEDB: Display transmit and receive activity */ - reg_phy = efm_eth_readPhy(PHLCON); - efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470); + /* LEDA: Display link status; + LEDB: Display transmit and receive activity */ + reg_phy = efm_eth_readPhy(PHLCON); + efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470); - /* Disable clock output */ - efm_eth_writeReg(ECOCON, 0x00); + /* Disable clock output */ + efm_eth_writeReg(ECOCON, 0x00); - /* Clear interrutp flags */ - data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - /* Enable interrutps */ - data = EIE_INTIE | EIE_PKTIE | EIE_TXIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); - /* Enable RX */ - data = ECON1_RXEN; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + /* Clear interrutp flags */ + data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + /* Enable interrutps */ + data = EIE_INTIE | EIE_PKTIE | EIE_TXIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + /* Enable RX */ + data = ECON1_RXEN; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - eth_debug("ETH: Init OK\n"); - return RT_EOK; + eth_debug("ETH: Init OK\n"); + return RT_EOK; } /***************************************************************************//** @@ -569,8 +569,8 @@ static rt_err_t efm_eth_init(rt_device_t dev) ******************************************************************************/ static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag) { - eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag); - return RT_EOK; + eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag); + return RT_EOK; } /***************************************************************************//** @@ -589,8 +589,8 @@ static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag) ******************************************************************************/ static rt_err_t efm_eth_close(rt_device_t dev) { - eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag); - return RT_EOK; + eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag); + return RT_EOK; } /***************************************************************************//** @@ -617,10 +617,10 @@ static rt_err_t efm_eth_close(rt_device_t dev) * Number of read bytes ******************************************************************************/ static rt_size_t efm_eth_read( - rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size) { rt_set_errno(-RT_ENOSYS); return 0; @@ -650,10 +650,10 @@ static rt_size_t efm_eth_read( * Number of written bytes ******************************************************************************/ static rt_size_t efm_eth_write ( - rt_device_t dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) { rt_set_errno(-RT_ENOSYS); return 0; @@ -674,35 +674,35 @@ static rt_size_t efm_eth_write ( * Ethernet control command * * @param[in] args -* Arguments +* Arguments * * @return * Error code ******************************************************************************/ static rt_err_t efm_eth_control ( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - rt_err_t ret; + rt_err_t ret; - ret = -RT_ERROR; - switch(cmd) - { - case NIOCTL_GADDR: - /* Get MAC address */ - if(args) - { - rt_memcpy(args, eth_addr, sizeof(eth_addr)); - ret = RT_EOK; - } - break; + ret = -RT_ERROR; + switch(cmd) + { + case NIOCTL_GADDR: + /* Get MAC address */ + if(args) + { + rt_memcpy(args, eth_addr, sizeof(eth_addr)); + ret = RT_EOK; + } + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -721,43 +721,43 @@ static rt_err_t efm_eth_control ( ******************************************************************************/ struct pbuf *efm_eth_rx(rt_device_t dev) { - rt_uint8_t buf_ins[5], buf_read[6]; - rt_uint8_t data, reg_eie; - rt_uint16_t len_rx, sta_rx; - struct pbuf* p; + rt_uint8_t buf_ins[5], buf_read[6]; + rt_uint8_t data, reg_eie; + rt_uint16_t len_rx, sta_rx; + struct pbuf* p; /* Lock device */ rt_sem_take(ðLock, RT_WAITING_FOREVER); /* Disable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - p = RT_NULL; - reg_eie = 0; + p = RT_NULL; + reg_eie = 0; if (efm_eth_readReg(EPKTCNT)) { /* Set read pointer to the start of RX packet */ efm_eth_writeReg(ERDPTL, ethNxtPkt & 0xFF); efm_eth_writeReg(ERDPTH, ethNxtPkt >> 8); - /* Send read buffer command */ - efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER); - /* Build instruction buffer */ - buf_ins[0] = 0x00; - *(rt_uint8_t **)(&buf_ins[1]) = buf_read; - /* Read packet header */ - if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0) - { - eth_debug("ETH: RX header failed!\n"); - } + /* Send read buffer command */ + efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER); + /* Build instruction buffer */ + buf_ins[0] = 0x00; + *(rt_uint8_t **)(&buf_ins[1]) = buf_read; + /* Read packet header */ + if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0) + { + eth_debug("ETH: RX header failed!\n"); + } - ethNxtPkt = buf_read[0] | (buf_read[1] << 8); - len_rx = buf_read[2] | (buf_read[3] << 8); - sta_rx = buf_read[4] | (buf_read[5] << 8); - eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n", - ethNxtPkt, len_rx, sta_rx); - /* Check if OK */ + ethNxtPkt = buf_read[0] | (buf_read[1] << 8); + len_rx = buf_read[2] | (buf_read[3] << 8); + sta_rx = buf_read[4] | (buf_read[5] << 8); + eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n", + ethNxtPkt, len_rx, sta_rx); + /* Check if OK */ if (sta_rx & 0x80) { /* Allocate pbuf */ @@ -768,67 +768,67 @@ struct pbuf *efm_eth_rx(rt_device_t dev) for (q = p; q != RT_NULL; q= q->next) { - /* Build instruction buffer */ - buf_ins[0] = 0x00; - *(rt_uint8_t **)(&buf_ins[1]) = q->payload; - /* Read packet header */ - if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0) - { - eth_debug("ETH: RX payload failed!\n"); - } + /* Build instruction buffer */ + buf_ins[0] = 0x00; + *(rt_uint8_t **)(&buf_ins[1]) = q->payload; + /* Read packet header */ + if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0) + { + eth_debug("ETH: RX payload failed!\n"); + } #ifdef EFM32_ETHERNET_DEBUG - { - rt_uint8_t *temp = (rt_uint8_t *)q->payload; - rt_uint32_t i; + { + rt_uint8_t *temp = (rt_uint8_t *)q->payload; + rt_uint32_t i; - eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len); - for (i = 0; i < q->len; i += 8) - { - eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); - } - } + eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len); + for (i = 0; i < q->len; i += 8) + { + eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); + } + } #endif } } - else - { - eth_debug("ETH: No memory for pbuf!!!\n"); - } + else + { + eth_debug("ETH: No memory for pbuf!!!\n"); + } } - else - { + else + { eth_debug("ETH: Invalid CRC or symbol error occurred!\n"); } - efm_eth_cs(0); + efm_eth_cs(0); /* Free buffer */ efm_eth_writeReg(ERXRDPTL, ethNxtPkt & 0xFF); efm_eth_writeReg(ERXRDPTH, ethNxtPkt >> 8); /* Decrease counter */ - data = ECON2_PKTDEC; + data = ECON2_PKTDEC; efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON2, &data); } - else - { - /* Enable RX */ - data = ECON1_RXEN; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + else + { + /* Enable RX */ + data = ECON1_RXEN; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - reg_eie |= EIE_PKTIE; - eth_debug("ETH: Enable RX interrupt\n"); - } - eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT)); + reg_eie |= EIE_PKTIE; + eth_debug("ETH: Enable RX interrupt\n"); + } + eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT)); /* Enable interrupts */ - reg_eie |= EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie); + reg_eie |= EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie); - /* Unlock device */ + /* Unlock device */ rt_sem_release(ðLock); return p; @@ -849,76 +849,76 @@ struct pbuf *efm_eth_rx(rt_device_t dev) * Pointer to packet buffer * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p) { - rt_uint8_t data; - struct pbuf* q; + rt_uint8_t data; + struct pbuf* q; /* Lock device */ rt_sem_take(ðLock, RT_WAITING_FOREVER); /* Disable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data); - /* Set write pointer to the start of TX buffer */ - efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); - efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); - /* Set buffer end pointer according to the packet size */ - efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF); - efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8); + /* Set write pointer to the start of TX buffer */ + efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); + efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); + /* Set buffer end pointer according to the packet size */ + efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF); + efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8); - /* Send write buffer command */ - data = 0x00; /* Control byte */ - efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data); - /* Send data */ - for (q = p; q != NULL; q = q->next) - { - if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0) - { - eth_debug("ETH: TX failed!\n"); - return -RT_ERROR; - } + /* Send write buffer command */ + data = 0x00; /* Control byte */ + efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data); + /* Send data */ + for (q = p; q != NULL; q = q->next) + { + if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0) + { + eth_debug("ETH: TX failed!\n"); + return -RT_ERROR; + } #ifdef EFM32_ETHERNET_DEBUG - { - rt_uint8_t *temp = (rt_uint8_t *)q->payload; - rt_uint32_t i; + { + rt_uint8_t *temp = (rt_uint8_t *)q->payload; + rt_uint32_t i; - eth_debug("ETH: ***** write TX (len %d) *****\n", p->len); - for (i = 0; i < q->len; i += 8) - { - eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], - temp[i], temp[i + 1], temp[i + 2], temp[i + 3], - temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); - } - } + eth_debug("ETH: ***** write TX (len %d) *****\n", p->len); + for (i = 0; i < q->len; i += 8) + { + eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n", + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7], + temp[i], temp[i + 1], temp[i + 2], temp[i + 3], + temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]); + } + } #endif - } - efm_eth_cs(0); - /* Start TX */ - data = ECON1_TXRTS; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - /* Errata 12 */ - if (efm_eth_readReg(EIR) & EIR_TXERIF) - { - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data); - data = EIR_TXERIF; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); - data = ECON1_TXRTS; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); - } + } + efm_eth_cs(0); + /* Start TX */ + data = ECON1_TXRTS; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + /* Errata 12 */ + if (efm_eth_readReg(EIR) & EIR_TXERIF) + { + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data); + data = EIR_TXERIF; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data); + data = ECON1_TXRTS; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data); + } - /* Waiting for a while */ - rt_thread_delay(ETH_PERIOD_WAIT_INIT); + /* Waiting for a while */ + rt_thread_delay(ETH_PERIOD_WAIT_INIT); /* Enable interrupts */ - data = EIE_INTIE; - efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); + data = EIE_INTIE; + efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data); - /* Unlock device */ + /* Unlock device */ rt_sem_release(ðLock); return RT_EOK; @@ -926,164 +926,164 @@ rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p) /***************************************************************************//** * @brief -* Initialize all Ethernet related hardware and register the device to kernel +* Initialize all Ethernet related hardware and register the device to kernel * * @details * * @note * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t efm_hw_eth_init(void) { - struct efm32_usart_device_t *usart; - efm32_irq_hook_init_t hook; + struct efm32_usart_device_t *usart; + efm32_irq_hook_init_t hook; - do - { - /* Find SPI device */ - spi = rt_device_find(ETH_USING_DEVICE_NAME); - if (spi == RT_NULL) - { - eth_debug("ETH: Can't find device %s!\n", - ETH_USING_DEVICE_NAME); - break; - } - eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME); + do + { + /* Find SPI device */ + spi = rt_device_find(ETH_USING_DEVICE_NAME); + if (spi == RT_NULL) + { + eth_debug("ETH: Can't find device %s!\n", + ETH_USING_DEVICE_NAME); + break; + } + eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME); - /* Config chip slect pin */ - usart = (struct efm32_usart_device_t *)(spi->user_data); - if (!(usart->state & USART_STATE_AUTOCS)) - { - GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1); - ethAutoCs = false; - } - /* Config reset pin */ - GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0); - /* Config interrupt pin */ - GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1); + /* Config chip slect pin */ + usart = (struct efm32_usart_device_t *)(spi->user_data); + if (!(usart->state & USART_STATE_AUTOCS)) + { + GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1); + ethAutoCs = false; + } + /* Config reset pin */ + GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0); + /* Config interrupt pin */ + GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1); - /* Config interrupt */ - hook.type = efm32_irq_type_gpio; - hook.unit = ETH_INT_PIN; - hook.cbFunc = efm_eth_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); - /* Clear pending interrupt */ - BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL); - /* Set falling edge interrupt and clear/enable it */ - GPIO_IntConfig( - ETH_INT_PORT, - ETH_INT_PIN, - false, - true, - true); - if ((rt_uint8_t)ETH_INT_PIN % 2) - { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - else - { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } + /* Config interrupt */ + hook.type = efm32_irq_type_gpio; + hook.unit = ETH_INT_PIN; + hook.cbFunc = efm_eth_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); + /* Clear pending interrupt */ + BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL); + /* Set falling edge interrupt and clear/enable it */ + GPIO_IntConfig( + ETH_INT_PORT, + ETH_INT_PIN, + false, + true, + true); + if ((rt_uint8_t)ETH_INT_PIN % 2) + { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + else + { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } - /* Set SPI speed */ - USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX); + /* Set SPI speed */ + USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX); - /* Initialize semaphore */ - rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO); + /* Initialize semaphore */ + rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO); - /* Register Ethernet device */ - eth_dev.parent.init = efm_eth_init; - eth_dev.parent.open = efm_eth_open; - eth_dev.parent.close = efm_eth_close; - eth_dev.parent.read = efm_eth_read; - eth_dev.parent.write = efm_eth_write; - eth_dev.parent.control = efm_eth_control; - eth_dev.eth_rx = efm_eth_rx; - eth_dev.eth_tx = efm_eth_tx; - eth_device_init(ð_dev, ETH_DEVICE_NAME); + /* Register Ethernet device */ + eth_dev.parent.init = efm_eth_init; + eth_dev.parent.open = efm_eth_open; + eth_dev.parent.close = efm_eth_close; + eth_dev.parent.read = efm_eth_read; + eth_dev.parent.write = efm_eth_write; + eth_dev.parent.control = efm_eth_control; + eth_dev.eth_rx = efm_eth_rx; + eth_dev.eth_tx = efm_eth_tx; + eth_device_init(ð_dev, ETH_DEVICE_NAME); - /* Start device */ - GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN); + /* Start device */ + GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN); - eth_debug("ETH: HW init OK\n"); - return RT_EOK; - } while (0); + eth_debug("ETH: HW init OK\n"); + return RT_EOK; + } while (0); - /* Release buffer */ - rt_kprintf("ETH: HW init failed!\n"); - return -RT_ERROR; + /* Release buffer */ + rt_kprintf("ETH: HW init failed!\n"); + return -RT_ERROR; } /******************************************************************************* - * Export to FINSH + * Export to FINSH ******************************************************************************/ -#if defined(EFM32_USING_ETH_UTILS) +#if defined(EFM32_USING_ETH_UTILS) #ifdef RT_USING_FINSH #include <finsh.h> void list_eth(void) { - rt_uint16_t reg_phy; - rt_uint8_t data; + rt_uint16_t reg_phy; + rt_uint8_t data; - rt_kprintf(" ENC28J60 on %s\n", ETH_USING_DEVICE_NAME); - rt_kprintf(" ------------------------------\n"); - reg_phy = efm_eth_readPhy(PHSTAT2); - if (reg_phy & PHSTAT2_PLRITY) - { - rt_kprintf(" Cable polarity is reversed\n"); - } - else - { - rt_kprintf(" Cable polarity is correct\n"); - } - if (reg_phy & PHSTAT2_DPXSTAT) - { - rt_kprintf(" Full-duplex mode\n"); - } - else - { - rt_kprintf(" Half-duplex mode\n"); - } - if (reg_phy & PHSTAT2_LSTAT) - { - rt_kprintf(" Link is up\n"); - } - else - { - rt_kprintf(" Link is down\n"); - } - if (reg_phy & PHSTAT2_COLSTAT) - { - rt_kprintf(" Collision is occuring\n"); - } - else - { - rt_kprintf(" No collision\n"); - } - if (reg_phy & PHSTAT2_RXSTAT) - { - rt_kprintf(" RX is busy\n"); - } - else - { - rt_kprintf(" RX is idle\n"); - } - if (reg_phy & PHSTAT2_TXSTAT) - { - rt_kprintf(" TX is busy\n"); - } - else - { - rt_kprintf(" TX is idle\n"); - } + rt_kprintf(" ENC28J60 on %s\n", ETH_USING_DEVICE_NAME); + rt_kprintf(" ------------------------------\n"); + reg_phy = efm_eth_readPhy(PHSTAT2); + if (reg_phy & PHSTAT2_PLRITY) + { + rt_kprintf(" Cable polarity is reversed\n"); + } + else + { + rt_kprintf(" Cable polarity is correct\n"); + } + if (reg_phy & PHSTAT2_DPXSTAT) + { + rt_kprintf(" Full-duplex mode\n"); + } + else + { + rt_kprintf(" Half-duplex mode\n"); + } + if (reg_phy & PHSTAT2_LSTAT) + { + rt_kprintf(" Link is up\n"); + } + else + { + rt_kprintf(" Link is down\n"); + } + if (reg_phy & PHSTAT2_COLSTAT) + { + rt_kprintf(" Collision is occuring\n"); + } + else + { + rt_kprintf(" No collision\n"); + } + if (reg_phy & PHSTAT2_RXSTAT) + { + rt_kprintf(" RX is busy\n"); + } + else + { + rt_kprintf(" RX is idle\n"); + } + if (reg_phy & PHSTAT2_TXSTAT) + { + rt_kprintf(" TX is busy\n"); + } + else + { + rt_kprintf(" TX is idle\n"); + } } FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.) @@ -1091,108 +1091,108 @@ FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.) rt_err_t get_ip(char *ip) { - err_t ret; - struct ip_addr server_ip; - struct netconn *conn; - struct netbuf *buf; - char *rq, *rq2; - u16_t len; - const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n"; - const char find[] = "body"; + err_t ret; + struct ip_addr server_ip; + struct netconn *conn; + struct netbuf *buf; + char *rq, *rq2; + u16_t len; + const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n"; + const char find[] = "body"; - do - { + do + { #if defined(RT_LWIP_DNS) - ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip); - if (ret != ERR_OK) - { - break; - } + ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip); + if (ret != ERR_OK) + { + break; + } #else - IP4_ADDR(&server_ip, 216,146,38,70); // IP address of "checkip.dyndns.com" + IP4_ADDR(&server_ip, 216,146,38,70); // IP address of "checkip.dyndns.com" #endif - conn = netconn_new(NETCONN_TCP); - if (conn == NULL) - { - break; - } + conn = netconn_new(NETCONN_TCP); + if (conn == NULL) + { + break; + } - ret = netconn_connect(conn, &server_ip, 80); - if (ret != ERR_OK) - { - break; - } + ret = netconn_connect(conn, &server_ip, 80); + if (ret != ERR_OK) + { + break; + } - /* Send the query */ - ret = netconn_write(conn, query, sizeof(query) - 1, 0); - if (ret != ERR_OK) - { - break; - } + /* Send the query */ + ret = netconn_write(conn, query, sizeof(query) - 1, 0); + if (ret != ERR_OK) + { + break; + } - buf = netconn_recv(conn); - if (buf != NULL) - { - /* Get the response */ - ret = netbuf_data(buf, (void **)&rq, &len); - if (ret != ERR_OK) - { - break; - } + buf = netconn_recv(conn); + if (buf != NULL) + { + /* Get the response */ + ret = netbuf_data(buf, (void **)&rq, &len); + if (ret != ERR_OK) + { + break; + } - /* Find the IP address */ - rq = rt_strstr(rq, find); - if (rq == RT_NULL) - { - break; - } - rq += 5; - rq2 = rq; - rq2 = rt_strstr(rq2, find); - if (rq2 == RT_NULL) - { - break; - } - rq2 -= 2; - *rq2 = 0x0; -// rt_kprintf("[%s]\n", rq); - } - else - { - break; - } + /* Find the IP address */ + rq = rt_strstr(rq, find); + if (rq == RT_NULL) + { + break; + } + rq += 5; + rq2 = rq; + rq2 = rt_strstr(rq2, find); + if (rq2 == RT_NULL) + { + break; + } + rq2 -= 2; + *rq2 = 0x0; +// rt_kprintf("[%s]\n", rq); + } + else + { + break; + } - /* Copy the IP address to buffer */ - if (ip != NULL) - { - while(*rq < '0' || *rq > '9') - { - rq++; - } - rt_memcpy(ip, rq, rq2 - rq + 1); - } - netconn_delete(conn); - netbuf_delete(buf); - return RT_EOK; - } while (0); + /* Copy the IP address to buffer */ + if (ip != NULL) + { + while(*rq < '0' || *rq > '9') + { + rq++; + } + rt_memcpy(ip, rq, rq2 - rq + 1); + } + netconn_delete(conn); + netbuf_delete(buf); + return RT_EOK; + } while (0); - netconn_delete(conn); - netbuf_delete(buf); - return -RT_ERROR; + netconn_delete(conn); + netbuf_delete(buf); + return -RT_ERROR; } void list_myip(void) { - rt_uint8_t ip[20]; + rt_uint8_t ip[20]; - if (get_ip(ip) != RT_EOK) - { - rt_kprintf("Get IP failed!\n"); - return; - } + if (get_ip(ip) != RT_EOK) + { + rt_kprintf("Get IP failed!\n"); + return; + } - rt_kprintf("Current IP: [%s]\n", ip); + rt_kprintf("Current IP: [%s]\n", ip); } FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.) @@ -1202,122 +1202,122 @@ FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.) rt_err_t update_ip(char *ip) { - err_t ret; - struct ip_addr server_ip; - struct netconn *conn; - struct netbuf *buf; - char *rq; - u16_t len, len2; - char query[200] = "GET /nic/update?hostname="; - const char query2[] = "&myip="; - const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic "; - const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n"; - const char find[] = "good"; + err_t ret; + struct ip_addr server_ip; + struct netconn *conn; + struct netbuf *buf; + char *rq; + u16_t len, len2; + char query[200] = "GET /nic/update?hostname="; + const char query2[] = "&myip="; + const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic "; + const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n"; + const char find[] = "good"; - /* Make the query */ - len = rt_strlen(query); - len2 = sizeof(hostName) - 1; - rt_memcpy(&query[len], hostName, len2); - len += len2; + /* Make the query */ + len = rt_strlen(query); + len2 = sizeof(hostName) - 1; + rt_memcpy(&query[len], hostName, len2); + len += len2; - len2 = sizeof(query2) - 1; - rt_memcpy(&query[len], query2, len2); - len += len2; + len2 = sizeof(query2) - 1; + rt_memcpy(&query[len], query2, len2); + len += len2; - len2 = rt_strlen(ip); - rt_memcpy(&query[len], ip, len2); - len += len2; + len2 = rt_strlen(ip); + rt_memcpy(&query[len], ip, len2); + len += len2; - len2 = sizeof(query3) - 1; - rt_memcpy(&query[len], query3, len2); - len += len2; + len2 = sizeof(query3) - 1; + rt_memcpy(&query[len], query3, len2); + len += len2; - len2 = sizeof(userPwdB64) - 1; - rt_memcpy(&query[len], userPwdB64, len2); - len += len2; + len2 = sizeof(userPwdB64) - 1; + rt_memcpy(&query[len], userPwdB64, len2); + len += len2; - len2 = sizeof(query4) - 1; - rt_memcpy(&query[len], query4, len2); - len += len2; + len2 = sizeof(query4) - 1; + rt_memcpy(&query[len], query4, len2); + len += len2; - query[len] = 0x0; -// rt_kprintf("Query: %s\n", &query[100]); + query[len] = 0x0; +// rt_kprintf("Query: %s\n", &query[100]); - do - { + do + { #if defined(RT_LWIP_DNS) - ret = netconn_gethostbyname("members.dyndns.org", &server_ip); - if (ret != ERR_OK) - { - break; - } + ret = netconn_gethostbyname("members.dyndns.org", &server_ip); + if (ret != ERR_OK) + { + break; + } #else - IP4_ADDR(&server_ip, 204,13,248,112); // IP address of "members.dyndns.org" + IP4_ADDR(&server_ip, 204,13,248,112); // IP address of "members.dyndns.org" #endif - conn = netconn_new(NETCONN_TCP); - if (conn == NULL) - { - break; - } + conn = netconn_new(NETCONN_TCP); + if (conn == NULL) + { + break; + } - ret = netconn_connect(conn, &server_ip, 80); - if (ret != ERR_OK) - { - break; - } + ret = netconn_connect(conn, &server_ip, 80); + if (ret != ERR_OK) + { + break; + } - /* Send the query */ - ret = netconn_write(conn, query, len, 0); - if (ret != ERR_OK) - { - break; - } + /* Send the query */ + ret = netconn_write(conn, query, len, 0); + if (ret != ERR_OK) + { + break; + } - /* Get the response */ - buf = netconn_recv(conn); - if (buf != NULL) - { - ret = netbuf_data(buf, (void **)&rq, &len); - if (ret != ERR_OK) - { - break; - } + /* Get the response */ + buf = netconn_recv(conn); + if (buf != NULL) + { + ret = netbuf_data(buf, (void **)&rq, &len); + if (ret != ERR_OK) + { + break; + } - /* Find the result */ - rq = rt_strstr(rq, find); - if (rq == RT_NULL) - { - break; - } -// rt_kprintf("[%s]\n", rq); - } - else - { - break; - } + /* Find the result */ + rq = rt_strstr(rq, find); + if (rq == RT_NULL) + { + break; + } +// rt_kprintf("[%s]\n", rq); + } + else + { + break; + } - netconn_delete(conn); - netbuf_delete(buf); - return RT_EOK; - } while (0); + netconn_delete(conn); + netbuf_delete(buf); + return RT_EOK; + } while (0); - netconn_delete(conn); - netbuf_delete(buf); - return -RT_ERROR; + netconn_delete(conn); + netbuf_delete(buf); + return -RT_ERROR; } void update_myip(char *ip) { - rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip); + rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip); - if (update_ip(ip) != RT_EOK) - { - rt_kprintf("failed!\n"); - return; - } + if (update_ip(ip) != RT_EOK) + { + rt_kprintf("failed!\n"); + return; + } - rt_kprintf("succeeded.\n", ip); + rt_kprintf("succeeded.\n", ip); } FINSH_FUNCTION_EXPORT(update_myip, update DDNS with specified IP address.) diff --git a/bsp/efm32/drv_ethernet.h b/bsp/efm32/drv_ethernet.h index 146182f86d..87e12493f6 100644 --- a/bsp/efm32/drv_ethernet.h +++ b/bsp/efm32/drv_ethernet.h @@ -1,11 +1,11 @@ /***************************************************************************//** - * @file drv_ethernet.h - * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART + * @file drv_ethernet.h + * @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART * module - * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet + * This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet * controller with SPI interface. * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -13,8 +13,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-06-22 onelife Initial creation for using EFM32 USART module + * Date Author Notes + * 2011-06-22 onelife Initial creation for using EFM32 USART module ******************************************************************************/ #ifndef __DEV_ETHERNET_H__ #define __DEV_ETHERNET_H__ @@ -25,18 +25,18 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -#define ETH_ADDR_LEN (6) -#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */ +#define ETH_ADDR_LEN (6) +#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */ //#define ETH_HALF_DUPLEX -#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100) -#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100) -#define ETH_SPI_RX_SKIP (1) +#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100) +#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100) +#define ETH_SPI_RX_SKIP (1) -#define ETH_RESET_PORT (gpioPortB) -#define ETH_RESET_PIN (9) -#define ETH_INT_PORT (gpioPortB) -#define ETH_INT_PIN (10) +#define ETH_RESET_PORT (gpioPortB) +#define ETH_RESET_PIN (9) +#define ETH_INT_PORT (gpioPortB) +#define ETH_INT_PIN (10) /* Exported functions ------------------------------------------------------- */ rt_err_t efm_hw_eth_init(void); diff --git a/bsp/efm32/drv_leuart.c b/bsp/efm32/drv_leuart.c index 23addb48a9..7422956003 100644 --- a/bsp/efm32/drv_leuart.c +++ b/bsp/efm32/drv_leuart.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_leuart.c - * @brief LEUART driver of RT-Thread RTOS for EFM32 + * @file drv_leuart.c + * @brief LEUART driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,9 +10,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-12-09 onelife Initial creation for EFM32 - * 2011-12-27 onelife Utilize "LEUART_PRESENT" and "LEUART_COUNT" + * Date Author Notes + * 2011-12-09 onelife Initial creation for EFM32 + * 2011-12-27 onelife Utilize "LEUART_PRESENT" and "LEUART_COUNT" ******************************************************************************/ /***************************************************************************//** @@ -41,10 +41,10 @@ /* Private variables ---------------------------------------------------------*/ #if defined(RT_USING_LEUART0) #if (RT_USING_LEUART0 >= EFM32_LEUART_LOCATION_COUNT) - #error "Wrong location number" + #error "Wrong location number" #endif - struct rt_device leuart0_device; - static struct rt_semaphore leuart0_lock; + struct rt_device leuart0_device; + static struct rt_semaphore leuart0_lock; #endif #if defined(RT_USING_LEUART1) @@ -52,10 +52,10 @@ #error "Wrong unit number" #endif #if (RT_USING_LEUART1 >= EFM32_LEUART_LOCATION_COUNT) - #error "Wrong location number" + #error "Wrong location number" #endif - struct rt_device leuart1_device; - static struct rt_semaphore leuart1_lock; + struct rt_device leuart1_device; + static struct rt_semaphore leuart1_lock; #endif /* Private function prototypes -----------------------------------------------*/ @@ -76,37 +76,37 @@ ******************************************************************************/ static rt_err_t rt_leuart_init (rt_device_t dev) { - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - struct efm32_leuart_dma_mode_t *dma_tx; + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + struct efm32_leuart_dma_mode_t *dma_tx; - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - leuart->state |= LEUART_STATE_RX_BUSY; - } + leuart->state |= LEUART_STATE_RX_BUSY; + } - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - struct efm32_leuart_int_mode_t *int_rx; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + struct efm32_leuart_int_mode_t *int_rx; - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - int_rx->data_ptr = RT_NULL; - } + int_rx->data_ptr = RT_NULL; + } - /* Enable LEUART */ - LEUART_Enable(leuart->leuart_device, leuartEnable); + /* Enable LEUART */ + LEUART_Enable(leuart->leuart_device, leuartEnable); - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -128,68 +128,68 @@ static rt_err_t rt_leuart_init (rt_device_t dev) ******************************************************************************/ static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - IRQn_Type rxIrq; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + IRQn_Type rxIrq; - //if (leuart->state & LEUART_STATE_CONSOLE) - { /* Allocate new RX buffer */ - struct efm32_leuart_int_mode_t *int_mode; + //if (leuart->state & LEUART_STATE_CONSOLE) + { /* Allocate new RX buffer */ + struct efm32_leuart_int_mode_t *int_mode; - int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - return -RT_ENOMEM; - } - rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE); - int_mode->data_size = LEUART_RX_BUFFER_SIZE; - int_mode->read_index = 0; - int_mode->save_index = 0; - } + if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + return -RT_ENOMEM; + } + rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE); + int_mode->data_size = LEUART_RX_BUFFER_SIZE; + int_mode->read_index = 0; + int_mode->save_index = 0; + } - /* Enable RX interrupt */ - leuart->leuart_device->IEN = LEUART_IEN_RXDATAV; + /* Enable RX interrupt */ + leuart->leuart_device->IEN = LEUART_IEN_RXDATAV; - /* Enable IRQ */ - switch (leuart->unit) - { - case 0: + /* Enable IRQ */ + switch (leuart->unit) + { + case 0: rxIrq = LEUART0_IRQn; - break; + break; #if (LEUART_COUNT > 1) - case 1: + case 1: rxIrq = LEUART1_IRQn; - break; + break; #endif } - if (oflag != RT_DEVICE_OFLAG_WRONLY) - { - NVIC_ClearPendingIRQ(rxIrq); - NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(rxIrq); - } - } + if (oflag != RT_DEVICE_OFLAG_WRONLY) + { + NVIC_ClearPendingIRQ(rxIrq); + NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(rxIrq); + } + } /* Clear Flag */ leuart->leuart_device->IFC = _LEUART_IFC_MASK; - if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY)) - { - /* DMA IRQ is enabled by DMA_Init() */ - NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT); - } + if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY)) + { + /* DMA IRQ is enabled by DMA_Init() */ + NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT); + } - leuart->counter++; - leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag); - return RT_EOK; + leuart->counter++; + leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag); + return RT_EOK; } /***************************************************************************//** @@ -208,26 +208,26 @@ static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag) ******************************************************************************/ static rt_err_t rt_leuart_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - struct efm32_leuart_device_t *leuart; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - if (--leuart->counter == 0) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - struct efm32_leuart_int_mode_t *int_rx; + if (--leuart->counter == 0) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + struct efm32_leuart_int_mode_t *int_rx; - int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode; + int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode; - rt_free(int_rx->data_ptr); - int_rx->data_ptr = RT_NULL; - } - } + rt_free(int_rx->data_ptr); + int_rx->data_ptr = RT_NULL; + } + } - return RT_EOK; + return RT_EOK; } /***************************************************************************//** @@ -254,105 +254,105 @@ static rt_err_t rt_leuart_close(rt_device_t dev) * Number of read bytes ******************************************************************************/ static rt_size_t rt_leuart_read ( - rt_device_t dev, - rt_off_t pos, - void *buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size) { - struct efm32_leuart_device_t *leuart; - rt_uint8_t *ptr; - rt_err_t err_code; - rt_size_t read_len; + struct efm32_leuart_device_t *leuart; + rt_uint8_t *ptr; + rt_err_t err_code; + rt_size_t read_len; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - rt_set_errno(err_code); - return 0; - } + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + rt_set_errno(err_code); + return 0; + } - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - ptr = buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + ptr = buffer; - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; - struct efm32_leuart_int_mode_t *int_rx; + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; + struct efm32_leuart_int_mode_t *int_rx; - int_rx = (struct efm32_leuart_int_mode_t *)\ - (((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode); + int_rx = (struct efm32_leuart_int_mode_t *)\ + (((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode); - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - if (int_rx->read_index != int_rx->save_index) - { - /* read a character */ - *ptr++ = int_rx->data_ptr[int_rx->read_index]; - size--; + if (int_rx->read_index != int_rx->save_index) + { + /* read a character */ + *ptr++ = int_rx->data_ptr[int_rx->read_index]; + size--; - /* move to next position */ - int_rx->read_index ++; - if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) - { - int_rx->read_index = 0; - } - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; + /* move to next position */ + int_rx->read_index ++; + if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) + { + int_rx->read_index = 0; + } + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } - read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else - { - LEUART_TypeDef *leuart_device; + read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else + { + LEUART_TypeDef *leuart_device; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device; - ptr = buffer; + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device; + ptr = buffer; - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (leuart_device->STATUS & LEUART_STATUS_RXDATAV) - { - *ptr = leuart_device->RXDATA & 0xff; - ptr ++; - } - } + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (leuart_device->STATUS & LEUART_STATUS_RXDATAV) + { + *ptr = leuart_device->RXDATA & 0xff; + ptr ++; + } + } - read_len = size; - } + read_len = size; + } - /* Unlock device */ - rt_sem_release(leuart->lock); + /* Unlock device */ + rt_sem_release(leuart->lock); - /* set error code */ - rt_set_errno(err_code); - return read_len; + /* set error code */ + rt_set_errno(err_code); + return read_len; } /***************************************************************************//** @@ -379,504 +379,504 @@ static rt_size_t rt_leuart_read ( * Number of written bytes ******************************************************************************/ static rt_size_t rt_leuart_write ( - rt_device_t dev, - rt_off_t pos, - const void* buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + const void* buffer, + rt_size_t size) { - rt_err_t err_code; - rt_size_t write_size; - struct efm32_leuart_device_t* leuart; + rt_err_t err_code; + rt_size_t write_size; + struct efm32_leuart_device_t* leuart; - write_size = 0; - leuart = (struct efm32_leuart_device_t*)(dev->user_data); + write_size = 0; + leuart = (struct efm32_leuart_device_t*)(dev->user_data); - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - rt_set_errno(err_code); - return 0; - } + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + rt_set_errno(err_code); + return 0; + } - if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2)) - { /* DMA mode Tx */ - struct efm32_leuart_dma_mode_t *dma_tx; + if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2)) + { /* DMA mode Tx */ + struct efm32_leuart_dma_mode_t *dma_tx; - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - if (*((rt_uint8_t *)buffer + size - 1) == '\n') - { - *((rt_uint8_t *)buffer + size - 1) = '\r'; - *((rt_uint8_t *)buffer + size++) = '\n'; - *((rt_uint8_t *)buffer + size) = 0; - } - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + if (*((rt_uint8_t *)buffer + size - 1) == '\n') + { + *((rt_uint8_t *)buffer + size - 1) = '\r'; + *((rt_uint8_t *)buffer + size++) = '\n'; + *((rt_uint8_t *)buffer + size) = 0; + } + } - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - dma_tx->data_ptr = (rt_uint32_t *)buffer; - dma_tx->data_size = size; + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + dma_tx->data_ptr = (rt_uint32_t *)buffer; + dma_tx->data_size = size; - leuart->state |= LEUART_STATE_TX_BUSY; + leuart->state |= LEUART_STATE_TX_BUSY; - DMA_ActivateBasic( - dma_tx->dma_channel, - true, - false, - (void *)&(leuart->leuart_device->TXDATA), - (void *)buffer, - (rt_uint32_t)(size - 1)); + DMA_ActivateBasic( + dma_tx->dma_channel, + true, + false, + (void *)&(leuart->leuart_device->TXDATA), + (void *)buffer, + (rt_uint32_t)(size - 1)); - /* Wait, otherwise the TX buffer is overwrite */ -// if (leuart->state & LEUART_STATE_CONSOLE) -// { - while(leuart->state & LEUART_STATE_TX_BUSY); -// } -// else -// { -// while(leuart->state & LEUART_STATE_TX_BUSY) -// { -// rt_thread_sleep(LEUART_WAIT_TIME_TX); -// } -// } + /* Wait, otherwise the TX buffer is overwrite */ +// if (leuart->state & LEUART_STATE_CONSOLE) +// { + while(leuart->state & LEUART_STATE_TX_BUSY); +// } +// else +// { +// while(leuart->state & LEUART_STATE_TX_BUSY) +// { +// rt_thread_sleep(LEUART_WAIT_TIME_TX); +// } +// } // TODO: This function blocks the process - write_size = size; - } - else - { /* polling mode */ - rt_uint8_t *ptr = (rt_uint8_t *)buffer; + write_size = size; + } + else + { /* polling mode */ + rt_uint8_t *ptr = (rt_uint8_t *)buffer; - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = '\r'; - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = '\r'; + } - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); - leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; - ++ptr; --size; - } - } + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL)); + leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr; + ++ptr; --size; + } + } - write_size = (rt_size_t)ptr - (rt_size_t)buffer; - } + write_size = (rt_size_t)ptr - (rt_size_t)buffer; + } - /* Unlock device */ - rt_sem_release(leuart->lock); + /* Unlock device */ + rt_sem_release(leuart->lock); - /* set error code */ - rt_set_errno(err_code); - return write_size; + /* set error code */ + rt_set_errno(err_code); + return write_size; } /***************************************************************************//** * @brief -* Configure LEUART device +* Configure LEUART device * * @details * * @note * * @param[in] dev -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] cmd -* IIC control command +* IIC control command * * @param[in] args -* Arguments +* Arguments * * @return -* Error code +* Error code ******************************************************************************/ static rt_err_t rt_leuart_control ( - rt_device_t dev, - rt_uint8_t cmd, - void *args) + rt_device_t dev, + rt_uint8_t cmd, + void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - rt_err_t err_code; - struct efm32_leuart_device_t *leuart; + rt_err_t err_code; + struct efm32_leuart_device_t *leuart; - leuart = (struct efm32_leuart_device_t *)(dev->user_data); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); - /* Lock device */ - if (rt_hw_interrupt_check()) - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); - } - else - { - err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); - } - if (err_code != RT_EOK) - { - return err_code; - } + /* Lock device */ + if (rt_hw_interrupt_check()) + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_NO); + } + else + { + err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER); + } + if (err_code != RT_EOK) + { + return err_code; + } - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* Suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - LEUART_Enable(leuart->leuart_device, leuartDisable); - break; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* Suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + LEUART_Enable(leuart->leuart_device, leuartDisable); + break; - case RT_DEVICE_CTRL_RESUME: - /* Resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - LEUART_Enable(leuart->leuart_device, leuartEnable); - break; + case RT_DEVICE_CTRL_RESUME: + /* Resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + LEUART_Enable(leuart->leuart_device, leuartEnable); + break; - case RT_DEVICE_CTRL_LEUART_RBUFFER: - /* Set RX buffer */ - { - struct efm32_leuart_int_mode_t *int_rx; - rt_uint8_t size; + case RT_DEVICE_CTRL_LEUART_RBUFFER: + /* Set RX buffer */ + { + struct efm32_leuart_int_mode_t *int_rx; + rt_uint8_t size; - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL); + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL); - /* Free previous RX buffer */ - if (int_rx->data_ptr != RT_NULL) - { - if (size == 0) - { /* Free RX buffer */ - rt_free(int_rx->data_ptr); - int_rx->data_ptr = RT_NULL; - } - else if (size != int_rx->data_size) - { - /* Re-allocate RX buffer */ - if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \ - == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - err_code = -RT_ENOMEM; - break; - } - // TODO: Is the following line necessary? - //rt_memset(int_rx->data_ptr, 0, size); - } - } - else - { - /* Allocate new RX buffer */ - if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); - err_code = -RT_ENOMEM; - break; - } - } - int_rx->data_size = size; - int_rx->read_index = 0; - int_rx->save_index = 0; - } - break; + /* Free previous RX buffer */ + if (int_rx->data_ptr != RT_NULL) + { + if (size == 0) + { /* Free RX buffer */ + rt_free(int_rx->data_ptr); + int_rx->data_ptr = RT_NULL; + } + else if (size != int_rx->data_size) + { + /* Re-allocate RX buffer */ + if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \ + == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + err_code = -RT_ENOMEM; + break; + } + // TODO: Is the following line necessary? + //rt_memset(int_rx->data_ptr, 0, size); + } + } + else + { + /* Allocate new RX buffer */ + if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit); + err_code = -RT_ENOMEM; + break; + } + } + int_rx->data_size = size; + int_rx->read_index = 0; + int_rx->save_index = 0; + } + break; - } + } - /* Unlock device */ - rt_sem_release(leuart->lock); + /* Unlock device */ + rt_sem_release(leuart->lock); - return err_code; + return err_code; } /***************************************************************************//** * @brief - * LEUART RX data valid interrupt handler + * LEUART RX data valid interrupt handler * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void rt_hw_leuart_rx_isr(rt_device_t dev) { - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_int_mode_t *int_rx; + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_int_mode_t *int_rx; rt_uint32_t flag; - /* interrupt mode receive */ - RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX); + /* interrupt mode receive */ + RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX); - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode); - RT_ASSERT(int_rx->data_ptr != RT_NULL); + RT_ASSERT(int_rx->data_ptr != RT_NULL); - /* Set status */ - leuart->state |= LEUART_STATE_RX_BUSY; + /* Set status */ + leuart->state |= LEUART_STATE_RX_BUSY; - /* save into rx buffer */ - while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV) - { - rt_base_t level; + /* save into rx buffer */ + while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV) + { + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* save character */ - int_rx->data_ptr[int_rx->save_index] = \ - (rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL); - int_rx->save_index ++; - if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE) - int_rx->save_index = 0; + /* save character */ + int_rx->data_ptr[int_rx->save_index] = \ + (rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL); + int_rx->save_index ++; + if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE) + int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (int_rx->save_index == int_rx->read_index) - { - int_rx->read_index ++; - if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) - { - int_rx->read_index = 0; - } - } + /* if the next position is read index, discard this 'read char' */ + if (int_rx->save_index == int_rx->read_index) + { + int_rx->read_index ++; + if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE) + { + int_rx->read_index = 0; + } + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } - /* invoke callback */ - if (dev->rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (dev->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = int_rx->read_index > int_rx->save_index ? - LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \ - int_rx->save_index - int_rx->read_index; + /* get rx length */ + rx_length = int_rx->read_index > int_rx->save_index ? + LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \ + int_rx->save_index - int_rx->read_index; - dev->rx_indicate(dev, rx_length); - } + dev->rx_indicate(dev, rx_length); + } } /***************************************************************************//** * @brief - * DMA for LEUART TX interrupt handler + * DMA for LEUART TX interrupt handler * * @details * * @note * * @param[in] dev - * Pointer to device descriptor + * Pointer to device descriptor ******************************************************************************/ void rt_hw_leuart_dma_tx_isr(rt_device_t dev) { - /* DMA mode receive */ - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_dma_mode_t *dma_tx; + /* DMA mode receive */ + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_dma_mode_t *dma_tx; - RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX); + RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX); - leuart = (struct efm32_leuart_device_t *)(dev->user_data); - dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); + leuart = (struct efm32_leuart_device_t *)(dev->user_data); + dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode); - /* invoke call to notify tx complete */ - if (dev->tx_complete != RT_NULL) - { - dev->tx_complete(dev, dma_tx->data_ptr); - } + /* invoke call to notify tx complete */ + if (dev->tx_complete != RT_NULL) + { + dev->tx_complete(dev, dma_tx->data_ptr); + } - /* Set status */ - leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY; + /* Set status */ + leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY; } /***************************************************************************//** * @brief -* Register LEUART device +* Register LEUART device * * @details * * @note * * @param[in] device -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] name -* Device name +* Device name * * @param[in] flag -* Configuration flags +* Configuration flags * * @param[in] leuart -* Pointer to LEUART device descriptor +* Pointer to LEUART device descriptor * * @return -* Error code +* Error code ******************************************************************************/ rt_err_t rt_hw_leuart_register( - rt_device_t device, - const char *name, - rt_uint32_t flag, - struct efm32_leuart_device_t *leuart) + rt_device_t device, + const char *name, + rt_uint32_t flag, + struct efm32_leuart_device_t *leuart) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_leuart_init; - device->open = rt_leuart_open; - device->close = rt_leuart_close; - device->read = rt_leuart_read; - device->write = rt_leuart_write; - device->control = rt_leuart_control; - device->user_data = leuart; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_leuart_init; + device->open = rt_leuart_open; + device->close = rt_leuart_close; + device->read = rt_leuart_read; + device->write = rt_leuart_write; + device->control = rt_leuart_control; + device->user_data = leuart; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /***************************************************************************//** * @brief -* Initialize the specified LEUART unit +* Initialize the specified LEUART unit * * @details * * @note * * @param[in] device -* Pointer to device descriptor +* Pointer to device descriptor * * @param[in] unitNumber -* Unit number +* Unit number * * @param[in] location -* Pin location number +* Pin location number * * @param[in] flag -* Configuration flag +* Configuration flag * * @param[in] dmaChannel -* DMA channel number for TX +* DMA channel number for TX * * @param[in] console -* Indicate if using as console +* Indicate if using as console * * @return -* Pointer to LEUART device +* Pointer to LEUART device ******************************************************************************/ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( - rt_device_t device, - rt_uint8_t unitNumber, - rt_uint8_t location, - rt_uint32_t flag, - rt_uint32_t dmaChannel, - rt_uint8_t config) + rt_device_t device, + rt_uint8_t unitNumber, + rt_uint8_t location, + rt_uint32_t flag, + rt_uint32_t dmaChannel, + rt_uint8_t config) { - struct efm32_leuart_device_t *leuart; - struct efm32_leuart_dma_mode_t *dma_mode; - DMA_CB_TypeDef *callback; - CMU_Clock_TypeDef leuartClock; - rt_uint32_t txDmaSelect; - GPIO_Port_TypeDef port_tx, port_rx, port_clk, port_cs; - rt_uint32_t pin_tx, pin_rx, pin_clk, pin_cs; + struct efm32_leuart_device_t *leuart; + struct efm32_leuart_dma_mode_t *dma_mode; + DMA_CB_TypeDef *callback; + CMU_Clock_TypeDef leuartClock; + rt_uint32_t txDmaSelect; + GPIO_Port_TypeDef port_tx, port_rx, port_clk, port_cs; + rt_uint32_t pin_tx, pin_rx, pin_clk, pin_cs; LEUART_Init_TypeDef init = LEUART_INIT_DEFAULT; - efm32_irq_hook_init_t hook; + efm32_irq_hook_init_t hook; - do - { - /* Allocate device */ - leuart = rt_malloc(sizeof(struct efm32_leuart_device_t)); - if (leuart == RT_NULL) - { - leuart_debug("LEUART%d err: no mem\n", unitNumber); - break; - } - leuart->counter = 0; - leuart->unit = unitNumber; - leuart->state = config; - leuart->tx_mode = RT_NULL; - leuart->rx_mode = RT_NULL; + do + { + /* Allocate device */ + leuart = rt_malloc(sizeof(struct efm32_leuart_device_t)); + if (leuart == RT_NULL) + { + leuart_debug("LEUART%d err: no mem\n", unitNumber); + break; + } + leuart->counter = 0; + leuart->unit = unitNumber; + leuart->state = config; + leuart->tx_mode = RT_NULL; + leuart->rx_mode = RT_NULL; - /* Allocate TX */ - dma_mode = RT_NULL; - if (flag & RT_DEVICE_FLAG_DMA_TX) - { - leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t)); - if (dma_mode == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber); - break; - } - dma_mode->dma_channel = dmaChannel; - } + /* Allocate TX */ + dma_mode = RT_NULL; + if (flag & RT_DEVICE_FLAG_DMA_TX) + { + leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t)); + if (dma_mode == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber); + break; + } + dma_mode->dma_channel = dmaChannel; + } - /* Allocate RX */ - if (flag & RT_DEVICE_FLAG_INT_RX) - { - leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t)); - if (leuart->rx_mode == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber"); - break; - } - } + /* Allocate RX */ + if (flag & RT_DEVICE_FLAG_INT_RX) + { + leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t)); + if (leuart->rx_mode == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber"); + break; + } + } - /* Initialization */ - if (unitNumber >= LEUART_COUNT) - { - break; - } - switch (unitNumber) - { - case 0: - leuart->leuart_device = LEUART0; - leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART0; - txDmaSelect = DMAREQ_LEUART0_TXBL; - port_tx = AF_LEUART0_TX_PORT(location); - pin_tx = AF_LEUART0_TX_PIN(location); - port_rx = AF_LEUART0_RX_PORT(location); - pin_rx = AF_LEUART0_RX_PIN(location); - break; + /* Initialization */ + if (unitNumber >= LEUART_COUNT) + { + break; + } + switch (unitNumber) + { + case 0: + leuart->leuart_device = LEUART0; + leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART0; + txDmaSelect = DMAREQ_LEUART0_TXBL; + port_tx = AF_LEUART0_TX_PORT(location); + pin_tx = AF_LEUART0_TX_PIN(location); + port_rx = AF_LEUART0_RX_PORT(location); + pin_rx = AF_LEUART0_RX_PIN(location); + break; #if (LEUART_COUNT > 1) - case 1: - leuart->leuart_device = LEUART1; - leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART1; - txDmaSelect = DMAREQ_LEUART1_TXBL; - port_tx = AF_LEUART1_TX_PORT(location); - pin_tx = AF_LEUART1_TX_PIN(location); - port_rx = AF_LEUART1_RX_PORT(location); - pin_rx = AF_LEUART1_RX_PIN(location); - break; + case 1: + leuart->leuart_device = LEUART1; + leuartClock = (CMU_Clock_TypeDef)cmuClock_LEUART1; + txDmaSelect = DMAREQ_LEUART1_TXBL; + port_tx = AF_LEUART1_TX_PORT(location); + pin_tx = AF_LEUART1_TX_PIN(location); + port_rx = AF_LEUART1_RX_PORT(location); + pin_rx = AF_LEUART1_RX_PIN(location); + break; #endif - default: - break; - } + default: + break; + } /* Do not prescale clock */ CMU_ClockDivSet(leuartClock, cmuClkDiv_1); @@ -884,98 +884,98 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( /* Enable LEUART clock */ CMU_ClockEnable(leuartClock, true); - /* Config GPIO */ - GPIO_PinModeSet( - port_tx, - pin_tx, - gpioModePushPull, - 0); - GPIO_PinModeSet( - port_rx, - pin_rx, - gpioModeInputPull, - 1); + /* Config GPIO */ + GPIO_PinModeSet( + port_tx, + pin_tx, + gpioModePushPull, + 0); + GPIO_PinModeSet( + port_rx, + pin_rx, + gpioModeInputPull, + 1); - /* Config interrupt and NVIC */ - if (flag & RT_DEVICE_FLAG_INT_RX) - { - hook.type = efm32_irq_type_leuart; - hook.unit = unitNumber; - hook.cbFunc = rt_hw_leuart_rx_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); - } + /* Config interrupt and NVIC */ + if (flag & RT_DEVICE_FLAG_INT_RX) + { + hook.type = efm32_irq_type_leuart; + hook.unit = unitNumber; + hook.cbFunc = rt_hw_leuart_rx_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); + } - /* Config DMA */ - if (flag & RT_DEVICE_FLAG_DMA_TX) - { - DMA_CfgChannel_TypeDef chnlCfg; - DMA_CfgDescr_TypeDef descrCfg; + /* Config DMA */ + if (flag & RT_DEVICE_FLAG_DMA_TX) + { + DMA_CfgChannel_TypeDef chnlCfg; + DMA_CfgDescr_TypeDef descrCfg; - hook.type = efm32_irq_type_dma; - hook.unit = dmaChannel; - hook.cbFunc = rt_hw_leuart_dma_tx_isr; - hook.userPtr = device; - efm32_irq_hook_register(&hook); + hook.type = efm32_irq_type_dma; + hook.unit = dmaChannel; + hook.cbFunc = rt_hw_leuart_dma_tx_isr; + hook.userPtr = device; + efm32_irq_hook_register(&hook); - callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef)); - if (callback == RT_NULL) - { - leuart_debug("LEUART%d err: no mem for callback\n", unitNumber); - break; - } - callback->cbFunc = DMA_IRQHandler_All; - callback->userPtr = RT_NULL; - callback->primary = 0; + callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef)); + if (callback == RT_NULL) + { + leuart_debug("LEUART%d err: no mem for callback\n", unitNumber); + break; + } + callback->cbFunc = DMA_IRQHandler_All; + callback->userPtr = RT_NULL; + callback->primary = 0; - /* Setting up DMA channel */ - chnlCfg.highPri = false; /* Can't use with peripherals */ - chnlCfg.enableInt = true; /* Interrupt for callback function */ - chnlCfg.select = txDmaSelect; - chnlCfg.cb = callback; - DMA_CfgChannel(dmaChannel, &chnlCfg); + /* Setting up DMA channel */ + chnlCfg.highPri = false; /* Can't use with peripherals */ + chnlCfg.enableInt = true; /* Interrupt for callback function */ + chnlCfg.select = txDmaSelect; + chnlCfg.cb = callback; + DMA_CfgChannel(dmaChannel, &chnlCfg); - /* Setting up DMA channel descriptor */ - descrCfg.dstInc = dmaDataIncNone; - descrCfg.srcInc = dmaDataInc1; - descrCfg.size = dmaDataSize1; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr(dmaChannel, true, &descrCfg); - } + /* Setting up DMA channel descriptor */ + descrCfg.dstInc = dmaDataIncNone; + descrCfg.srcInc = dmaDataInc1; + descrCfg.size = dmaDataSize1; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr(dmaChannel, true, &descrCfg); + } - /* Init specified LEUART unit */ + /* Init specified LEUART unit */ LEUART_Init(leuart->leuart_device, &init); - /* Enable RX and TX pins and set location */ - leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \ - (location << _LEUART_ROUTE_LOCATION_SHIFT); + /* Enable RX and TX pins and set location */ + leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \ + (location << _LEUART_ROUTE_LOCATION_SHIFT); - /* Clear RX/TX buffers */ - leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; + /* Clear RX/TX buffers */ + leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; - return leuart; - } while(0); + return leuart; + } while(0); - if (leuart->rx_mode) - { - rt_free(leuart->rx_mode); - } - if (leuart->tx_mode) - { - rt_free(leuart->tx_mode); - } - if (leuart) - { - rt_free(leuart); - } - if (callback) - { - rt_free(leuart); - } + if (leuart->rx_mode) + { + rt_free(leuart->rx_mode); + } + if (leuart->tx_mode) + { + rt_free(leuart->tx_mode); + } + if (leuart) + { + rt_free(leuart); + } + if (callback) + { + rt_free(leuart); + } leuart_debug("LEUART%d err: init failed!\n", unitNumber); - return RT_NULL; + return RT_NULL; } /***************************************************************************//** @@ -989,12 +989,12 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init( ******************************************************************************/ void rt_hw_leuart_init(void) { - struct efm32_leuart_device_t *leuart; - rt_uint32_t flag; - rt_uint8_t config; + struct efm32_leuart_device_t *leuart; + rt_uint32_t flag; + rt_uint8_t config; - do - { + do + { #ifdef RT_USING_LEUART0 config = 0; flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; @@ -1073,11 +1073,11 @@ void rt_hw_leuart_init(void) } #endif - leuart_debug("LEUART: H/W init OK!\n"); - return; - } while (0); + leuart_debug("LEUART: H/W init OK!\n"); + return; + } while (0); - rt_kprintf("LEUART: H/W init failed!\n"); + rt_kprintf("LEUART: H/W init failed!\n"); } #endif /* (defined(RT_USING_LEUART0) || defined(RT_USING_LEUART1)) */ diff --git a/bsp/efm32/drv_leuart.h b/bsp/efm32/drv_leuart.h index 692ff0d520..b7c24bb025 100644 --- a/bsp/efm32/drv_leuart.h +++ b/bsp/efm32/drv_leuart.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file drv_leuart.h - * @brief LEUART driver of RT-Thread RTOS for EFM32 + * @file drv_leuart.h + * @brief LEUART driver of RT-Thread RTOS for EFM32 * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-12-09 onelife Initial creation for EFM32 + * Date Author Notes + * 2011-12-09 onelife Initial creation for EFM32 ******************************************************************************/ #ifndef __DRV_LEUSART_H__ #define __DRV_LEUSART_H__ @@ -20,37 +20,37 @@ /* Exported types ------------------------------------------------------------*/ struct efm32_leuart_int_mode_t { - rt_uint8_t *data_ptr; - rt_uint8_t data_size; - rt_uint32_t read_index, save_index; + rt_uint8_t *data_ptr; + rt_uint8_t data_size; + rt_uint32_t read_index, save_index; }; struct efm32_leuart_dma_mode_t { - /* DMA Channel */ - rt_uint32_t dma_channel; + /* DMA Channel */ + rt_uint32_t dma_channel; - /* buffer info */ - rt_uint32_t *data_ptr; - rt_uint8_t data_size; + /* buffer info */ + rt_uint32_t *data_ptr; + rt_uint8_t data_size; }; struct efm32_leuart_device_t { - /* Counter */ - rt_uint32_t counter; - /* Lock */ - struct rt_semaphore *lock; - /* Unit number */ - rt_uint8_t unit; - /* State */ - volatile rt_uint8_t state; - /* Pointer to LEUART device structure */ - LEUART_TypeDef *leuart_device; - /* Pointer to RX structure */ - void *rx_mode; - /* Pointer to TX structure */ - void *tx_mode; + /* Counter */ + rt_uint32_t counter; + /* Lock */ + struct rt_semaphore *lock; + /* Unit number */ + rt_uint8_t unit; + /* State */ + volatile rt_uint8_t state; + /* Pointer to LEUART device structure */ + LEUART_TypeDef *leuart_device; + /* Pointer to RX structure */ + void *rx_mode; + /* Pointer to TX structure */ + void *tx_mode; }; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/drv_rtc.c b/bsp/efm32/drv_rtc.c index 16604a3919..75713fe3b4 100644 --- a/bsp/efm32/drv_rtc.c +++ b/bsp/efm32/drv_rtc.c @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2009-01-05 Bernard the first version * 2010-12-27 onelife Modify for EFM32 * 2011-06-16 onelife Modify init function for efm32lib v2 upgrading @@ -33,7 +33,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_RTC_DEBUG -#define rtc_debug(format,args...) rt_kprintf(format, ##args) +#define rtc_debug(format,args...) rt_kprintf(format, ##args) #else #define rtc_debug(format,args...) #endif @@ -55,10 +55,10 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) } static rt_size_t rt_rtc_read( - rt_device_t dev, - rt_off_t pos, - void* buffer, - rt_size_t size) + rt_device_t dev, + rt_off_t pos, + void* buffer, + rt_size_t size) { return 0; } @@ -91,16 +91,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) { case RT_DEVICE_CTRL_RTC_GET_TIME: *(rt_uint32_t *)args = rtc_time + RTC_CounterGet(); - rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet()); + rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet()); break; case RT_DEVICE_CTRL_RTC_SET_TIME: { rtc_time = *(rt_uint32_t *)args; - rtc_debug("RTC: set rtc_time %x\n", rtc_time); + rtc_debug("RTC: set rtc_time %x\n", rtc_time); - /* Reset counter */ - RTC_CounterReset(); + /* Reset counter */ + RTC_CounterReset(); } break; } @@ -118,12 +118,12 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) ******************************************************************************/ void rt_hw_rtc_isr(rt_device_t device) { - if (RTC->IF & RTC_IFC_OF) - { - rtc_time += _RTC_CNT_MASK; - } + if (RTC->IF & RTC_IFC_OF) + { + rtc_time += _RTC_CNT_MASK; + } - RTC->IFC = _RTC_IFC_MASK; + RTC->IFC = _RTC_IFC_MASK; } /***************************************************************************//** @@ -147,25 +147,25 @@ void rt_hw_rtc_isr(rt_device_t device) * Error code ******************************************************************************/ rt_err_t rt_hw_rtc_register( - rt_device_t device, - const char *name, - rt_uint32_t flag) + rt_device_t device, + const char *name, + rt_uint32_t flag) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_RTC; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = RT_NULL; - device->open = rt_rtc_open; - device->close = RT_NULL; - device->read = rt_rtc_read; - device->write = RT_NULL; - device->control = rt_rtc_control; - device->user_data = RT_NULL; /* no private */ + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = RT_NULL; + device->open = rt_rtc_open; + device->close = RT_NULL; + device->read = rt_rtc_read; + device->write = RT_NULL; + device->control = rt_rtc_control; + device->user_data = RT_NULL; /* no private */ - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } @@ -179,50 +179,50 @@ rt_err_t rt_hw_rtc_register( ******************************************************************************/ void rt_hw_rtc_init(void) { - rt_uint32_t reset; + rt_uint32_t reset; - reset = RMU_ResetCauseGet(); + reset = RMU_ResetCauseGet(); - // TODO: What is the current reset mode? - if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST) + // TODO: What is the current reset mode? + if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST) { - RTC_Init_TypeDef rtcInit; - efm32_irq_hook_init_t hook; + RTC_Init_TypeDef rtcInit; + efm32_irq_hook_init_t hook; - rtcInit.enable = true; - rtcInit.debugRun = false; - rtcInit.comp0Top = false; + rtcInit.enable = true; + rtcInit.debugRun = false; + rtcInit.comp0Top = false; - rtc_time = 0UL; + rtc_time = 0UL; rt_kprintf("rtc is not configured\n"); rt_kprintf("please configure with set_date and set_time\n"); - /* Configuring clock */ + /* Configuring clock */ CMU_ClockDivSet(cmuClock_RTC,cmuClkDiv_32768); CMU_ClockEnable(cmuClock_RTC, true); - /* Initialize and enable RTC */ - RTC_Reset(); - RTC_Init(&rtcInit); + /* Initialize and enable RTC */ + RTC_Reset(); + RTC_Init(&rtcInit); - hook.type = efm32_irq_type_rtc; - hook.unit = 0; - hook.cbFunc = rt_hw_rtc_isr; - hook.userPtr = RT_NULL; - efm32_irq_hook_register(&hook); + hook.type = efm32_irq_type_rtc; + hook.unit = 0; + hook.cbFunc = rt_hw_rtc_isr; + hook.userPtr = RT_NULL; + efm32_irq_hook_register(&hook); - /* Enabling Interrupt from RTC */ - RTC_IntEnable(RTC_IFC_OF); - RTC_IntClear(RTC_IFC_OF); + /* Enabling Interrupt from RTC */ + RTC_IntEnable(RTC_IFC_OF); + RTC_IntClear(RTC_IFC_OF); - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT); - NVIC_EnableIRQ(RTC_IRQn); + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT); + NVIC_EnableIRQ(RTC_IRQn); } /* register rtc device */ - rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA); + rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA); } #endif diff --git a/bsp/efm32/drv_rtc.h b/bsp/efm32/drv_rtc.h index 492fc59d56..7e33c03896 100644 --- a/bsp/efm32/drv_rtc.h +++ b/bsp/efm32/drv_rtc.h @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2009-01-05 Bernard the first version * 2010-12-27 onelife Modification for EFM32 *********************************************************************/ diff --git a/bsp/efm32/drv_sdcard.h b/bsp/efm32/drv_sdcard.h index 17c94209c9..2c9a1bfc39 100644 --- a/bsp/efm32/drv_sdcard.h +++ b/bsp/efm32/drv_sdcard.h @@ -1,9 +1,9 @@ /***************************************************************************//** - * @file drv_sdcard.h - * @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32 + * @file drv_sdcard.h + * @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32 * USART module * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -11,9 +11,9 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-05-13 onelife Initial creation for using EFM32 USART module - * 2011-07-07 onelife Modify initialization function to return error code + * Date Author Notes + * 2011-05-13 onelife Initial creation for using EFM32 USART module + * 2011-07-07 onelife Modify initialization function to return error code ******************************************************************************/ #ifndef __DEV_SDCARD_H__ #define __DEV_SDCARD_H__ @@ -33,43 +33,43 @@ #error "EFM32 SPI clock should not be more than (EFM32_HFXO_FREQUENCY/2)" #endif -#define SD_SPEED_LOW (0) -#define SD_SPEED_HIGH (1) -#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND) +#define SD_SPEED_LOW (0) +#define SD_SPEED_HIGH (1) +#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND) -#define SD_SECTOR_SIZE_SHIFT (9) -#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT) -#define SD_BLOCK_SIZE_CSD (16) -#define SD_BLOCK_SIZE_CID (16) -#define SD_BLOCK_SIZE_OCR (4) -#define SD_BLOCK_SIZE_SDSTAT (64) +#define SD_SECTOR_SIZE_SHIFT (9) +#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT) +#define SD_BLOCK_SIZE_CSD (16) +#define SD_BLOCK_SIZE_CID (16) +#define SD_BLOCK_SIZE_OCR (4) +#define SD_BLOCK_SIZE_SDSTAT (64) /* Card type definitions (CardType) */ -#define CT_MMC (0x01) -#define CT_SD1 (0x02) -#define CT_SD2 (0x04) -#define CT_SDC (CT_SD1|CT_SD2) -#define CT_BLOCK (0x08) +#define CT_MMC (0x01) +#define CT_SD1 (0x02) +#define CT_SD2 (0x04) +#define CT_SDC (CT_SD1|CT_SD2) +#define CT_BLOCK (0x08) /* Definitions for MMC/SDC command */ -#define CMD0 (0) /* GO_IDLE_STATE */ -#define CMD1 (1) /* SEND_OP_COND */ -#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ -#define CMD8 (8) /* SEND_IF_COND */ -#define CMD9 (9) /* SEND_CSD */ -#define CMD10 (10) /* SEND_CID */ -#define CMD12 (12) /* STOP_TRANSMISSION */ -#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ -#define CMD16 (16) /* SET_BLOCKLEN */ -#define CMD17 (17) /* READ_SINGLE_BLOCK */ -#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (23) /* SET_BLOCK_COUNT */ -#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ -#define CMD24 (24) /* WRITE_BLOCK */ -#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD41 (41) /* SEND_OP_COND (ACMD) */ -#define CMD55 (55) /* APP_CMD */ -#define CMD58 (58) /* READ_OCR */ +#define CMD0 (0) /* GO_IDLE_STATE */ +#define CMD1 (1) /* SEND_OP_COND */ +#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ +#define CMD8 (8) /* SEND_IF_COND */ +#define CMD9 (9) /* SEND_CSD */ +#define CMD10 (10) /* SEND_CID */ +#define CMD12 (12) /* STOP_TRANSMISSION */ +#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ +#define CMD16 (16) /* SET_BLOCKLEN */ +#define CMD17 (17) /* READ_SINGLE_BLOCK */ +#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (23) /* SET_BLOCK_COUNT */ +#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (24) /* WRITE_BLOCK */ +#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (55) /* APP_CMD */ +#define CMD58 (58) /* READ_OCR */ /* Exported functions ------------------------------------------------------- */ rt_err_t efm_spiSd_init(void); diff --git a/bsp/efm32/drv_timer.c b/bsp/efm32/drv_timer.c index ccfb96ab0e..12e347544c 100644 --- a/bsp/efm32/drv_timer.c +++ b/bsp/efm32/drv_timer.c @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-01-18 onelife Initial creation for EFM32 * 2011-06-17 onelife Modify init function for efm32lib v2 upgrading ******************************************************************************/ diff --git a/bsp/efm32/drv_usart.c b/bsp/efm32/drv_usart.c index 7cfb50b0a7..c511a31475 100644 --- a/bsp/efm32/drv_usart.c +++ b/bsp/efm32/drv_usart.c @@ -34,9 +34,9 @@ * 2011-12-20 onelife Add 9-bit SPI mode support * 2011-12-20 onelife Change SPI write format (same as SPI read) * 2011-12-20 onelife Change USART status format - * 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT", + * 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT", * "UART_PRESENT" and "UART_COUNT" - * 2012-05-16 onelife Fix a bug in rt_hw_usart_init() + * 2012-05-16 onelife Fix a bug in rt_hw_usart_init() ******************************************************************************/ /***************************************************************************//** diff --git a/bsp/efm32/enc28j60.h b/bsp/efm32/enc28j60.h index 1351e145a3..1c97d9e10c 100644 --- a/bsp/efm32/enc28j60.h +++ b/bsp/efm32/enc28j60.h @@ -197,9 +197,9 @@ #define MACON3_FRMLNEN 0x02 #define MACON3_FULDPX 0x01 // ENC28J60 MACON4 Register Bit Definitions -#define MACON4_DEFER (1<<6) -#define MACON4_BPEN (1<<5) -#define MACON4_NOBKOFF (1<<4) +#define MACON4_DEFER (1<<6) +#define MACON4_BPEN (1<<5) +#define MACON4_NOBKOFF (1<<4) // ENC28J60 MICMD Register Bit Definitions #define MICMD_MIISCAN 0x02 #define MICMD_MIIRD 0x01 @@ -218,12 +218,12 @@ #define PHSTAT1_LLSTAT 0x0004 #define PHSTAT1_JBSTAT 0x0002 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */ -#define PHSTAT2_TXSTAT (1 << 13) -#define PHSTAT2_RXSTAT (1 << 12) -#define PHSTAT2_COLSTAT (1 << 11) -#define PHSTAT2_LSTAT (1 << 10) -#define PHSTAT2_DPXSTAT (1 << 9) -#define PHSTAT2_PLRITY (1 << 5) +#define PHSTAT2_TXSTAT (1 << 13) +#define PHSTAT2_RXSTAT (1 << 12) +#define PHSTAT2_COLSTAT (1 << 11) +#define PHSTAT2_LSTAT (1 << 10) +#define PHSTAT2_DPXSTAT (1 << 9) +#define PHSTAT2_PLRITY (1 << 5) // ENC28J60 PHY PHCON2 Register Bit Definitions #define PHCON2_FRCLINK 0x4000 #define PHCON2_TXDIS 0x2000 @@ -282,13 +282,13 @@ #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0) // SPI operation codes -#define ENC28J60_READ_CTRL_REG (0x00) -#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A) -#define ENC28J60_WRITE_CTRL_REG (0x40) -#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A) -#define ENC28J60_BIT_FIELD_SET (0x80) -#define ENC28J60_BIT_FIELD_CLR (0xA0) -#define ENC28J60_SOFT_RESET (0xE0 | 0x1F) +#define ENC28J60_READ_CTRL_REG (0x00) +#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A) +#define ENC28J60_WRITE_CTRL_REG (0x40) +#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A) +#define ENC28J60_BIT_FIELD_SET (0x80) +#define ENC28J60_BIT_FIELD_CLR (0xA0) +#define ENC28J60_SOFT_RESET (0xE0 | 0x1F) // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata // buffer boundaries applied to internal 8K ram @@ -296,17 +296,17 @@ // // start with recbuf at 0/ -#define RXSTART_INIT 0x0 +#define RXSTART_INIT 0x0 // receive buffer end -#define RXSTOP_INIT (0x1FFF - 0x0600 - 1) +#define RXSTOP_INIT (0x1FFF - 0x0600 - 1) // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) -#define TXSTART_INIT (0x1FFF - 0x0600) +#define TXSTART_INIT (0x1FFF - 0x0600) // stp TX buffer at end of mem -#define TXSTOP_INIT 0x1FFF +#define TXSTOP_INIT 0x1FFF // max frame length which the conroller will accept: -#define MAX_FRAMELEN 1518 +#define MAX_FRAMELEN 1518 void rt_hw_enc28j60_init(void); diff --git a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h index bb7b7b571b..f6a53d04f9 100644 --- a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h +++ b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h @@ -127,11 +127,11 @@ EMSTATUS DMD_setClippingArea(uint16_t xStart, uint16_t yStart, uint16_t width, uint16_t height); EMSTATUS DMD_writeData(uint16_t x, uint16_t y, const uint8_t data[], uint32_t numPixels); -EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, +EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, const uint8_t *data); -EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, - const uint8_t *data, - int red, int green, int blue, int weight); +EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, + const uint8_t *data, + int red, int green, int blue, int weight); EMSTATUS DMD_readData(uint16_t x, uint16_t y, uint8_t data[], uint32_t numPixels); EMSTATUS DMD_writeColor(uint16_t x, uint16_t y, uint8_t red, diff --git a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c index 73ba5b4ab5..7925891f95 100644 --- a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c +++ b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c @@ -425,8 +425,8 @@ EMSTATUS DMD_writeData(uint16_t x, uint16_t y, const uint8_t data[], * DMD_OK on success, otherwise error code ******************************************************************************/ EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, - const uint8_t *data, - int red, int green, int blue, int weight) + const uint8_t *data, + int red, int green, int blue, int weight) { uint32_t color = 0; int xpos, ypos; diff --git a/bsp/efm32/graphics/tftspi.h b/bsp/efm32/graphics/tftspi.h index 1399fc552e..27e8ce8078 100644 --- a/bsp/efm32/graphics/tftspi.h +++ b/bsp/efm32/graphics/tftspi.h @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file tftspi.h - * @brief Stub functions of EFM32 LCD driver + * @file tftspi.h + * @brief Stub functions of EFM32 LCD driver * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,7 +10,7 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2011-12-20 onelife Initial creation for EFM32 ******************************************************************************/ #ifndef __TFTSPI_H__ diff --git a/bsp/efm32/hdl_interrupt.c b/bsp/efm32/hdl_interrupt.c index de91a9f9a0..8017414e55 100644 --- a/bsp/efm32/hdl_interrupt.c +++ b/bsp/efm32/hdl_interrupt.c @@ -13,10 +13,10 @@ * Date Author Notes * 2010-12-29 onelife Initial creation for EFM32 * 2011-07-12 onelife Disable interrupts in GPIO handler - * 2011-12-09 onelife Add giant gecko support + * 2011-12-09 onelife Add giant gecko support * 2011-12-09 onelife Add UART module support * 2011-12-09 onelife Add LEUART module support - * 2011-12-27 onelife Utilize "XXX_PRESENT" and "XXX_COUNT" + * 2011-12-27 onelife Utilize "XXX_PRESENT" and "XXX_COUNT" ******************************************************************************/ /* Includes ------------------------------------------------------------------*/ @@ -32,20 +32,20 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ #ifdef RT_IRQHDL_DEBUG -#define hdl_debug(format,args...) rt_kprintf(format, ##args) +#define hdl_debug(format,args...) rt_kprintf(format, ##args) #else #define hdl_debug(format,args...) #endif /* Private variables ---------------------------------------------------------*/ -efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2] = {RT_NULL}; -efm32_irq_hook_t timerCbTable[TIMER_COUNT] = {RT_NULL}; +efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2] = {RT_NULL}; +efm32_irq_hook_t timerCbTable[TIMER_COUNT] = {RT_NULL}; #if defined(LETIMER_PRESENT) efm32_irq_hook_t letimerCbTable[LETIMER_COUNT] = {RT_NULL}; #endif -efm32_irq_hook_t rtcCbTable[RTC_COUNT] = {RT_NULL}; -efm32_irq_hook_t gpioCbTable[16] = {RT_NULL}; -efm32_irq_hook_t acmpCbTable[ACMP_COUNT] = {RT_NULL}; +efm32_irq_hook_t rtcCbTable[RTC_COUNT] = {RT_NULL}; +efm32_irq_hook_t gpioCbTable[16] = {RT_NULL}; +efm32_irq_hook_t acmpCbTable[ACMP_COUNT] = {RT_NULL}; #if defined(USART_PRESENT) #if defined(UART_PRESENT) efm32_irq_hook_t usartCbTable[USART_COUNT * 2 + UART_COUNT * 2] = {RT_NULL}; @@ -57,7 +57,7 @@ efm32_irq_hook_t usartCbTable[USART_COUNT * 2] = {RT_NULL}; efm32_irq_hook_t leuartCbTable[LEUART_COUNT] = {RT_NULL}; #endif #if defined(I2C_PRESENT) -efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; +efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; #endif /* Private function prototypes -----------------------------------------------*/ @@ -65,7 +65,7 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; /***************************************************************************//** * @brief - * NMI exception handler + * NMI exception handler * * @details * @@ -73,12 +73,12 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] = {RT_NULL}; ******************************************************************************/ void NMI_Handler(void) { - hdl_debug("[NMI_Handler: NOP]\n"); + hdl_debug("[NMI_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * Memory manage exception handler + * Memory manage exception handler * * @details * @@ -86,13 +86,13 @@ void NMI_Handler(void) ******************************************************************************/ void MemManage_Handler(void) { - hdl_debug("[MemManage_Handler: infinite loop]\n"); - while (1); + hdl_debug("[MemManage_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Bus fault exception handler + * Bus fault exception handler * * @details * @@ -100,13 +100,13 @@ void MemManage_Handler(void) ******************************************************************************/ void BusFault_Handler(void) { - hdl_debug("[BusFault_Handler: infinite loop]\n"); - while (1); + hdl_debug("[BusFault_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Usage fault exception handler + * Usage fault exception handler * * @details * @@ -114,13 +114,13 @@ void BusFault_Handler(void) ******************************************************************************/ void UsageFault_Handler(void) { - hdl_debug("[UsageFault_Handler: infinite loop]\n"); - while (1); + hdl_debug("[UsageFault_Handler: infinite loop]\n"); + while (1); } /***************************************************************************//** * @brief - * Supervisor call exception handler + * Supervisor call exception handler * * @details * @@ -128,12 +128,12 @@ void UsageFault_Handler(void) ******************************************************************************/ void SVC_Handler(void) { - hdl_debug("[SVC_Handler: NOP]\n"); + hdl_debug("[SVC_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * Debug monitor exception handler + * Debug monitor exception handler * * @details * @@ -141,12 +141,12 @@ void SVC_Handler(void) ******************************************************************************/ void DebugMon_Handler(void) { - hdl_debug("[DebugMon_Handler: NOP]\n"); + hdl_debug("[DebugMon_Handler: NOP]\n"); } /***************************************************************************//** * @brief - * System tick timer interrupt handler + * System tick timer interrupt handler * * @details * @@ -155,13 +155,13 @@ void DebugMon_Handler(void) ******************************************************************************/ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /******************************************************************************* @@ -173,7 +173,7 @@ void SysTick_Handler(void) /***************************************************************************//** * @brief - * Common DMA interrupt handler + * Common DMA interrupt handler * * @details * @@ -185,11 +185,11 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user) /* enter interrupt */ rt_interrupt_enter(); - /* invoke callback function */ - if (dmaCbTable[channel].cbFunc != RT_NULL) - { - (dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr); - } + /* invoke callback function */ + if (dmaCbTable[channel].cbFunc != RT_NULL) + { + (dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr); + } /* leave interrupt */ rt_interrupt_leave(); @@ -197,95 +197,95 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user) /***************************************************************************//** * @brief - * Common Timer0 interrupt handler + * Common Timer0 interrupt handler * * @details - * This function handles Timer0 counter overflow interrupt request + * This function handles Timer0 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER0_IRQHandler(void) { - if (TIMER0->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[0].cbFunc != RT_NULL) - { - (timerCbTable[0].cbFunc)(timerCbTable[0].userPtr); - } + if (TIMER0->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[0].cbFunc != RT_NULL) + { + (timerCbTable[0].cbFunc)(timerCbTable[0].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } /***************************************************************************//** * @brief - * Common Timer1 interrupt handler + * Common Timer1 interrupt handler * * @details - * This function handles Timer1 counter overflow interrupt request + * This function handles Timer1 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER1_IRQHandler(void) { - if (TIMER1->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[1].cbFunc != RT_NULL) - { - (timerCbTable[1].cbFunc)(timerCbTable[1].userPtr); - } + if (TIMER1->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[1].cbFunc != RT_NULL) + { + (timerCbTable[1].cbFunc)(timerCbTable[1].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } /***************************************************************************//** * @brief - * Common Timer2 interrupt handler + * Common Timer2 interrupt handler * * @details - * This function handles Timer2 counter overflow interrupt request + * This function handles Timer2 counter overflow interrupt request * * @note * ******************************************************************************/ void TIMER2_IRQHandler(void) { - if (TIMER2->IF & TIMER_IF_OF) - { - /* invoke callback function */ - if (timerCbTable[2].cbFunc != RT_NULL) - { - (timerCbTable[2].cbFunc)(timerCbTable[2].userPtr); - } + if (TIMER2->IF & TIMER_IF_OF) + { + /* invoke callback function */ + if (timerCbTable[2].cbFunc != RT_NULL) + { + (timerCbTable[2].cbFunc)(timerCbTable[2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL); + } } #if defined(LETIMER_PRESENT) /***************************************************************************//** * @brief - * Common Low Energy Timer0 interrupt handler + * Common Low Energy Timer0 interrupt handler * * @details - * This function handles Timer0 counter overflow interrupt request + * This function handles Timer0 counter overflow interrupt request * * @note * ******************************************************************************/ void LETIMER0_IRQHandler(void) { - if (LETIMER0->IF & LETIMER_IF_UF) - { + if (LETIMER0->IF & LETIMER_IF_UF) + { /* enter interrupt */ rt_interrupt_enter(); @@ -294,24 +294,24 @@ void LETIMER0_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); - /* invoke callback function */ -/* if (letimerCbTable[0].cbFunc != RT_NULL) - { - (letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr); - } + /* invoke callback function */ +/* if (letimerCbTable[0].cbFunc != RT_NULL) + { + (letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr); + } */ - /* clear interrupt */ - BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL); + } } #endif /***************************************************************************//** * @brief - * Common RTC interrupt handler + * Common RTC interrupt handler * * @details - * This function handles RTC counter overflow interrupt request + * This function handles RTC counter overflow interrupt request * * @note * @@ -321,14 +321,14 @@ void RTC_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (RTC->IF & RTC_IF_OF) - { - /* invoke callback function */ - if (rtcCbTable[0].cbFunc != RT_NULL) - { - (rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr); - } - } + if (RTC->IF & RTC_IF_OF) + { + /* invoke callback function */ + if (rtcCbTable[0].cbFunc != RT_NULL) + { + (rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr); + } + } /* leave interrupt */ rt_interrupt_leave(); @@ -336,7 +336,7 @@ void RTC_IRQHandler(void) /***************************************************************************//** * @brief - * Common even number GPIO interrupt handler + * Common even number GPIO interrupt handler * * @details * @@ -345,36 +345,36 @@ void RTC_IRQHandler(void) ******************************************************************************/ void GPIO_EVEN_IRQHandler(void) { - rt_uint16_t flag, n; - rt_base_t level; + rt_uint16_t flag, n; + rt_base_t level; - /* Disable interrupt */ - level = rt_hw_interrupt_disable(); + /* Disable interrupt */ + level = rt_hw_interrupt_disable(); /* Enter ISR */ rt_interrupt_enter(); - /* invoke callback function */ - flag = (rt_uint16_t)(GPIO->IF & 0xFFFF); - for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2) - { - if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) - { - (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); - } - } + /* invoke callback function */ + flag = (rt_uint16_t)(GPIO->IF & 0xFFFF); + for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2) + { + if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) + { + (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); + } + } - /* clear interrupt */ - GPIO->IFC = 0x5555UL; + /* clear interrupt */ + GPIO->IFC = 0x5555UL; /* Leave ISR */ - rt_interrupt_leave(); - /* Enable interrupt */ + rt_interrupt_leave(); + /* Enable interrupt */ rt_hw_interrupt_enable(level); } /***************************************************************************//** * @brief - * Common odd number GPIO interrupt handler + * Common odd number GPIO interrupt handler * * @details * @@ -383,39 +383,39 @@ void GPIO_EVEN_IRQHandler(void) ******************************************************************************/ void GPIO_ODD_IRQHandler(void) { - rt_uint16_t flag, n; - rt_base_t level; + rt_uint16_t flag, n; + rt_base_t level; - /* Disable interrupt */ - level = rt_hw_interrupt_disable(); - /* Enter ISR */ + /* Disable interrupt */ + level = rt_hw_interrupt_disable(); + /* Enter ISR */ rt_interrupt_enter(); - /* invoke callback function */ - flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1; - for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2) - { - if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) - { - (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); - } - } + /* invoke callback function */ + flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1; + for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2) + { + if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL)) + { + (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr); + } + } - /* clear interrupt */ - GPIO->IFC = 0xAAAAUL; + /* clear interrupt */ + GPIO->IFC = 0xAAAAUL; /* Leave ISR */ - rt_interrupt_leave(); - /* Enable interrupt */ + rt_interrupt_leave(); + /* Enable interrupt */ rt_hw_interrupt_enable(level); } /***************************************************************************//** * @brief - * Common ACMP interrupt handler + * Common ACMP interrupt handler * * @details - * This function handles ACMP edge trigger interrupt request + * This function handles ACMP edge trigger interrupt request * * @note * @@ -425,29 +425,29 @@ void ACMP0_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (ACMP0->IF & ACMP_IF_EDGE) - { - /* invoke callback function */ - if (acmpCbTable[0].cbFunc != RT_NULL) - { - (acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr); - } + if (ACMP0->IF & ACMP_IF_EDGE) + { + /* invoke callback function */ + if (acmpCbTable[0].cbFunc != RT_NULL) + { + (acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); + } - if (ACMP1->IF & ACMP_IF_EDGE) - { - /* invoke callback function */ - if (acmpCbTable[1].cbFunc != RT_NULL) - { - (acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr); - } + if (ACMP1->IF & ACMP_IF_EDGE) + { + /* invoke callback function */ + if (acmpCbTable[1].cbFunc != RT_NULL) + { + (acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -456,10 +456,10 @@ void ACMP0_IRQHandler(void) #if defined(USART_PRESENT) /***************************************************************************//** * @brief - * Common USART0 TX interrupt handler + * Common USART0 TX interrupt handler * * @details - * This function handles USART0 TX complete interrupt request + * This function handles USART0 TX complete interrupt request * * @note * @@ -469,17 +469,17 @@ void USART0_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART0->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[0].cbFunc != RT_NULL) - { - (usartCbTable[0].cbFunc)(usartCbTable[0].userPtr); - } + if (USART0->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[0].cbFunc != RT_NULL) + { + (usartCbTable[0].cbFunc)(usartCbTable[0].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -487,34 +487,34 @@ void USART0_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART0 RX interrupt handler + * Common USART0 RX interrupt handler * * @details - * This function handles USART0 RX data valid interrupt request + * This function handles USART0 RX data valid interrupt request * * @note * ******************************************************************************/ void USART0_RX_IRQHandler(void) { - if (USART0->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[1].cbFunc != RT_NULL) - { - (usartCbTable[1].cbFunc)(usartCbTable[1].userPtr); - } - } + if (USART0->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[1].cbFunc != RT_NULL) + { + (usartCbTable[1].cbFunc)(usartCbTable[1].userPtr); + } + } } #endif #if (defined(USART_PRESENT) && (USART_COUNT > 1)) /***************************************************************************//** * @brief - * Common USART1 TX interrupt handler + * Common USART1 TX interrupt handler * * @details - * This function handles USART1 TX complete interrupt request + * This function handles USART1 TX complete interrupt request * * @note * @@ -524,17 +524,17 @@ void USART1_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART1->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[2].cbFunc != RT_NULL) - { - (usartCbTable[2].cbFunc)(usartCbTable[2].userPtr); - } + if (USART1->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[2].cbFunc != RT_NULL) + { + (usartCbTable[2].cbFunc)(usartCbTable[2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -542,34 +542,34 @@ void USART1_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART1 RX interrupt handler + * Common USART1 RX interrupt handler * * @details - * This function handles USART1 RX data valid interrupt request + * This function handles USART1 RX data valid interrupt request * * @note * ******************************************************************************/ void USART1_RX_IRQHandler(void) { - if (USART1->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[3].cbFunc != RT_NULL) - { - (usartCbTable[3].cbFunc)(usartCbTable[3].userPtr); - } - } + if (USART1->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[3].cbFunc != RT_NULL) + { + (usartCbTable[3].cbFunc)(usartCbTable[3].userPtr); + } + } } #endif #if (defined(USART_PRESENT) && (USART_COUNT > 2)) /***************************************************************************//** * @brief - * Common USART2 TX interrupt handler + * Common USART2 TX interrupt handler * * @details - * This function handles USART2 TX complete interrupt request + * This function handles USART2 TX complete interrupt request * * @note * @@ -579,17 +579,17 @@ void USART2_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (USART2->IF & USART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[4].cbFunc != RT_NULL) - { - (usartCbTable[4].cbFunc)(usartCbTable[4].userPtr); - } + if (USART2->IF & USART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[4].cbFunc != RT_NULL) + { + (usartCbTable[4].cbFunc)(usartCbTable[4].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -597,34 +597,34 @@ void USART2_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common USART2 RX interrupt handler + * Common USART2 RX interrupt handler * * @details - * This function handles USART2 RX data valid interrupt request + * This function handles USART2 RX data valid interrupt request * * @note * ******************************************************************************/ void USART2_RX_IRQHandler(void) { - if (USART2->IF & USART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[5].cbFunc != RT_NULL) - { - (usartCbTable[5].cbFunc)(usartCbTable[5].userPtr); - } - } + if (USART2->IF & USART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[5].cbFunc != RT_NULL) + { + (usartCbTable[5].cbFunc)(usartCbTable[5].userPtr); + } + } } #endif #if defined(UART_PRESENT) /***************************************************************************//** * @brief - * Common UART0 TX interrupt handler + * Common UART0 TX interrupt handler * * @details - * This function handles UART0 TX complete interrupt request + * This function handles UART0 TX complete interrupt request * * @note * @@ -634,17 +634,17 @@ void UART0_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (UART0->IF & UART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr); - } + if (UART0->IF & UART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -652,34 +652,34 @@ void UART0_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common UART0 RX interrupt handler + * Common UART0 RX interrupt handler * * @details - * This function handles UART0 RX data valid interrupt request + * This function handles UART0 RX data valid interrupt request * * @note * ******************************************************************************/ void UART0_RX_IRQHandler(void) { - if (UART0->IF & UART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr); - } - } + if (UART0->IF & UART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr); + } + } } #endif #if (defined(UART_PRESENT) && (UART_COUNT > 1)) /***************************************************************************//** * @brief - * Common UART1 TX interrupt handler + * Common UART1 TX interrupt handler * * @details - * This function handles UART1 TX complete interrupt request + * This function handles UART1 TX complete interrupt request * * @note * @@ -689,17 +689,17 @@ void UART1_TX_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (UART1->IF & UART_IF_TXC) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr); - } + if (UART1->IF & UART_IF_TXC) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr); + } - /* clear interrupt */ - BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL); - } + /* clear interrupt */ + BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL); + } /* leave interrupt */ rt_interrupt_leave(); @@ -707,106 +707,106 @@ void UART1_TX_IRQHandler(void) /***************************************************************************//** * @brief - * Common UART1 RX interrupt handler + * Common UART1 RX interrupt handler * * @details - * This function handles UART1 RX data valid interrupt request + * This function handles UART1 RX data valid interrupt request * * @note * ******************************************************************************/ void UART1_RX_IRQHandler(void) { - if (UART1->IF & UART_IF_RXDATAV) - { - /* invoke callback function */ - if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL) - { - (usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr); - } - } + if (UART1->IF & UART_IF_RXDATAV) + { + /* invoke callback function */ + if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL) + { + (usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr); + } + } } #endif #if defined(LEUART_PRESENT) /***************************************************************************//** * @brief - * Common LEUART0 interrupt handler + * Common LEUART0 interrupt handler * * @details - * This function handles LEUART0 interrupt request + * This function handles LEUART0 interrupt request * * @note * ******************************************************************************/ void LEUART0_IRQHandler(void) { - if (LEUART0->IF & LEUART_IF_RXDATAV) - { - /* invoke callback function */ - if (leuartCbTable[0].cbFunc != RT_NULL) - { - (leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr); - } - } + if (LEUART0->IF & LEUART_IF_RXDATAV) + { + /* invoke callback function */ + if (leuartCbTable[0].cbFunc != RT_NULL) + { + (leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr); + } + } } #endif #if (defined(LEUART_PRESENT) && (LEUART_COUNT > 1)) /***************************************************************************//** * @brief - * Common LEUART1 interrupt handler + * Common LEUART1 interrupt handler * * @details - * This function handles LEUART1 interrupt request + * This function handles LEUART1 interrupt request * * @note * ******************************************************************************/ void LEUART1_IRQHandler(void) { - if (LEUART1->IF & LEUART_IF_RXDATAV) - { - /* invoke callback function */ - if (leuartCbTable[1].cbFunc != RT_NULL) - { - (leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr); - } - } + if (LEUART1->IF & LEUART_IF_RXDATAV) + { + /* invoke callback function */ + if (leuartCbTable[1].cbFunc != RT_NULL) + { + (leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr); + } + } } #endif #if defined(I2C_PRESENT) /***************************************************************************//** * @brief - * Common IIC0 interrupt handler + * Common IIC0 interrupt handler * * @details - * This function handles IIC0 slave mode interrupt requests + * This function handles IIC0 slave mode interrupt requests * * @note * ******************************************************************************/ void I2C0_IRQHandler(void) { - if ((I2C0->IF & I2C_IF_ADDR) || \ - (I2C0->IF & I2C_IF_RXDATAV) || \ - (I2C0->IF & I2C_IF_SSTOP)) - { - /* invoke callback function */ - if (iicCbTable[0].cbFunc != RT_NULL) - { - (iicCbTable[0].cbFunc)(iicCbTable[0].userPtr); - } - } + if ((I2C0->IF & I2C_IF_ADDR) || \ + (I2C0->IF & I2C_IF_RXDATAV) || \ + (I2C0->IF & I2C_IF_SSTOP)) + { + /* invoke callback function */ + if (iicCbTable[0].cbFunc != RT_NULL) + { + (iicCbTable[0].cbFunc)(iicCbTable[0].userPtr); + } + } - I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP); + I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP); } #endif /***************************************************************************//** * @brief - * EFM32 common interrupt handlers register function + * EFM32 common interrupt handlers register function * * @details * @@ -815,42 +815,42 @@ void I2C0_IRQHandler(void) ******************************************************************************/ void efm32_irq_hook_register(efm32_irq_hook_init_t *hook) { - switch (hook->type) - { - case efm32_irq_type_dma: - dmaCbTable[hook->unit].cbFunc = hook->cbFunc; - dmaCbTable[hook->unit].userPtr = hook->userPtr; - break; + switch (hook->type) + { + case efm32_irq_type_dma: + dmaCbTable[hook->unit].cbFunc = hook->cbFunc; + dmaCbTable[hook->unit].userPtr = hook->userPtr; + break; - case efm32_irq_type_rtc: - rtcCbTable[hook->unit].cbFunc = hook->cbFunc; - rtcCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_rtc: + rtcCbTable[hook->unit].cbFunc = hook->cbFunc; + rtcCbTable[hook->unit].userPtr = hook->userPtr; + break; - case efm32_irq_type_timer: - timerCbTable[hook->unit].cbFunc = hook->cbFunc; - timerCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_timer: + timerCbTable[hook->unit].cbFunc = hook->cbFunc; + timerCbTable[hook->unit].userPtr = hook->userPtr; + break; - case efm32_irq_type_letimer: - letimerCbTable[hook->unit].cbFunc = hook->cbFunc; - letimerCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_letimer: + letimerCbTable[hook->unit].cbFunc = hook->cbFunc; + letimerCbTable[hook->unit].userPtr = hook->userPtr; + break; - case efm32_irq_type_gpio: - gpioCbTable[hook->unit].cbFunc = hook->cbFunc; - gpioCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_gpio: + gpioCbTable[hook->unit].cbFunc = hook->cbFunc; + gpioCbTable[hook->unit].userPtr = hook->userPtr; + break; - case efm32_irq_type_acmp: - acmpCbTable[hook->unit].cbFunc = hook->cbFunc; - acmpCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_acmp: + acmpCbTable[hook->unit].cbFunc = hook->cbFunc; + acmpCbTable[hook->unit].userPtr = hook->userPtr; + break; #if defined(USART_PRESENT) - case efm32_irq_type_usart: - usartCbTable[hook->unit].cbFunc = hook->cbFunc; - usartCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_usart: + usartCbTable[hook->unit].cbFunc = hook->cbFunc; + usartCbTable[hook->unit].userPtr = hook->userPtr; + break; #endif #if defined(LEUART_PRESENT) case efm32_irq_type_leuart: @@ -859,17 +859,17 @@ void efm32_irq_hook_register(efm32_irq_hook_init_t *hook) break; #endif #if defined(I2C_PRESENT) - case efm32_irq_type_iic: - iicCbTable[hook->unit].cbFunc = hook->cbFunc; - iicCbTable[hook->unit].userPtr = hook->userPtr; - break; + case efm32_irq_type_iic: + iicCbTable[hook->unit].cbFunc = hook->cbFunc; + iicCbTable[hook->unit].userPtr = hook->userPtr; + break; #endif - default: - break; - } + default: + break; + } - hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \ - hook->type, hook->unit, hook->cbFunc, hook->userPtr); + hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \ + hook->type, hook->unit, hook->cbFunc, hook->userPtr); } /***************************************************************************//** diff --git a/bsp/efm32/hdl_interrupt.h b/bsp/efm32/hdl_interrupt.h index 01f7adf9f8..d2f73bda57 100644 --- a/bsp/efm32/hdl_interrupt.h +++ b/bsp/efm32/hdl_interrupt.h @@ -21,31 +21,31 @@ /* Exported types ------------------------------------------------------------*/ enum efm32_irq_hook_type_t { - efm32_irq_type_dma = 0, - efm32_irq_type_rtc, - efm32_irq_type_timer, + efm32_irq_type_dma = 0, + efm32_irq_type_rtc, + efm32_irq_type_timer, efm32_irq_type_letimer, - efm32_irq_type_gpio, - efm32_irq_type_acmp, - efm32_irq_type_usart, - efm32_irq_type_leuart, - efm32_irq_type_iic + efm32_irq_type_gpio, + efm32_irq_type_acmp, + efm32_irq_type_usart, + efm32_irq_type_leuart, + efm32_irq_type_iic }; typedef void (*efm32_irq_callback_t)(rt_device_t device); typedef struct { - enum efm32_irq_hook_type_t type; - rt_uint8_t unit; - efm32_irq_callback_t cbFunc; - void *userPtr; + enum efm32_irq_hook_type_t type; + rt_uint8_t unit; + efm32_irq_callback_t cbFunc; + void *userPtr; } efm32_irq_hook_init_t; typedef struct { - efm32_irq_callback_t cbFunc; - void *userPtr; + efm32_irq_callback_t cbFunc; + void *userPtr; } efm32_irq_hook_t; /* Exported constants --------------------------------------------------------*/ diff --git a/bsp/efm32/httpd.c b/bsp/efm32/httpd.c index c7094d509a..02c81be84d 100644 --- a/bsp/efm32/httpd.c +++ b/bsp/efm32/httpd.c @@ -1,8 +1,8 @@ /***************************************************************************//** - * @file httpd.c - * @brief Simple http server demo application + * @file httpd.c + * @brief Simple http server demo application * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -10,8 +10,8 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-07-04 onelife Derive from Energy Micro demo application + * Date Author Notes + * 2011-07-04 onelife Derive from Energy Micro demo application ******************************************************************************/ /**************************************************************************//** @@ -94,29 +94,29 @@ static int temp, vdd; static char indexdata[700]; static const char indexdata1[] = - "HTTP/1.0 200 OK\r\n\ - Content-type: text/html\r\n\ - Pragma: no-cache\r\n\ - Refresh: 5\r\n\ - \r\n\ - <html>\ - <head><title>EFM32 HTTPD DEMO</title><head>\ - <body>\ - <h1>This is a simple http server</h1>\ - <br><br><B>Ethernet controller: ENC28J60</B>\ - <br><br><B>Refreshing timers: "; + "HTTP/1.0 200 OK\r\n\ + Content-type: text/html\r\n\ + Pragma: no-cache\r\n\ + Refresh: 5\r\n\ + \r\n\ + <html>\ + <head><title>EFM32 HTTPD DEMO</title><head>\ + <body>\ + <h1>This is a simple http server</h1>\ + <br><br><B>Ethernet controller: ENC28J60</B>\ + <br><br><B>Refreshing timers: "; static const char indexdata2[] = - "<br><br><B>Current Vdd: "; + "<br><br><B>Current Vdd: "; static const char indexdata3[] = - " V</B>\ - <br><br><B>Current temperature: "; + " V</B>\ + <br><br><B>Current temperature: "; static const char indexdata4[] = - " C</B>\ - </body>\ - </html>"; + " C</B>\ + </body>\ + </html>"; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -169,9 +169,9 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err counter++; } - vdd = rt_hw_get_vdd(); - rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100); - counter += 4; + vdd = rt_hw_get_vdd(); + rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100); + counter += 4; for (i = 0; i < sizeof(indexdata3) - 1; i++) { @@ -179,15 +179,15 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err counter++; } - temp = rt_hw_get_temp(); + temp = rt_hw_get_temp(); /*Set temperature sign*/ if (temp < 0) { indexdata[counter] = '-'; counter++; } - rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100); - counter += 5; + rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100); + counter += 5; for (i = 0; i < sizeof(indexdata4); i++) { diff --git a/bsp/efm32/mma7455l.h b/bsp/efm32/mma7455l.h index 2ea2cdf34e..c746fd45da 100644 --- a/bsp/efm32/mma7455l.h +++ b/bsp/efm32/mma7455l.h @@ -1,9 +1,9 @@ /***************************************************************************//** - * @file mma7455l.c - * @brief Header file of Freescale MMA7455L 3 axis Low-g digital output + * @file mma7455l.c + * @brief Header file of Freescale MMA7455L 3 axis Low-g digital output * accelerometer * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author onelife + * @author onelife * @version 1.0 ******************************************************************************* * @section License @@ -11,101 +11,101 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes - * 2011-08-02 onelife Initial creation + * Date Author Notes + * 2011-08-02 onelife Initial creation ******************************************************************************/ #ifndef __MMA7455L_H__ #define __MMA7455L_H__ -#define XOUTL 0x00 //00 10 bits output value X LSB (Read only) -#define XOUTH 0x01 //01 10 bits output value X MSB (Read only) -#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only) -#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only) -#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only) -#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only) -#define XOUT8 0x06 //06 8 bits Output value X (Read only) -#define YOUT8 0x07 //07 8 bits Output value Y (Read only) -#define ZOUT8 0x08 //08 8 bits Output value Z (Read only) -#define STATUS 0x09 //09 Status registers (Read only) -#define DETSRC 0x0A //10 Detection source registers (Read only) -#define TOUT 0x0B //11 Temperature output value (Optional) -#define RESERVED1 0x0C //12 Reserved -#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write) -#define USRINF 0x0E //14 User information (Optional, Read only) -#define WHOAMI 0x0F //15 Who am I value (Optional, Read only) -#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write) -#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write) -#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write) -#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write) -#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write) -#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write) -#define MCTL 0x16 //22 Mode control (Read/Write) -#define INTRST 0x17 //23 Interrupt latch reset (Read/Write) -#define CTL1 0x18 //24 Control 1 (Read/Write) -#define CTL2 0x19 //25 Control 2 (Read/Write) -#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write) -#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write) -#define PW 0x1C //28 Pulse duration value (Read/Write) -#define LT 0x1D //29 Latency time value (Read/Write) -#define TW 0x1E //30 Time window for second pulse value(Read/Write) -#define RESERVED2 0x1F //31 Reserved +#define XOUTL 0x00 //00 10 bits output value X LSB (Read only) +#define XOUTH 0x01 //01 10 bits output value X MSB (Read only) +#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only) +#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only) +#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only) +#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only) +#define XOUT8 0x06 //06 8 bits Output value X (Read only) +#define YOUT8 0x07 //07 8 bits Output value Y (Read only) +#define ZOUT8 0x08 //08 8 bits Output value Z (Read only) +#define STATUS 0x09 //09 Status registers (Read only) +#define DETSRC 0x0A //10 Detection source registers (Read only) +#define TOUT 0x0B //11 Temperature output value (Optional) +#define RESERVED1 0x0C //12 Reserved +#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write) +#define USRINF 0x0E //14 User information (Optional, Read only) +#define WHOAMI 0x0F //15 Who am I value (Optional, Read only) +#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write) +#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write) +#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write) +#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write) +#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write) +#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write) +#define MCTL 0x16 //22 Mode control (Read/Write) +#define INTRST 0x17 //23 Interrupt latch reset (Read/Write) +#define CTL1 0x18 //24 Control 1 (Read/Write) +#define CTL2 0x19 //25 Control 2 (Read/Write) +#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write) +#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write) +#define PW 0x1C //28 Pulse duration value (Read/Write) +#define LT 0x1D //29 Latency time value (Read/Write) +#define TW 0x1E //30 Time window for second pulse value(Read/Write) +#define RESERVED2 0x1F //31 Reserved /* For DETSRC */ -#define DETSRC_INT_1 (0x01 << 0) -#define DETSRC_INT_2 (0x01 << 1) -#define DETSRC_PULSE_Z (0x01 << 2) -#define DETSRC_PULSE_Y (0x01 << 3) -#define DETSRC_PULSE_X (0x01 << 4) -#define DETSRC_LEVEL_Z (0x01 << 5) -#define DETSRC_LEVEL_Y (0x01 << 6) -#define DETSRC_LEVEL_X (0x01 << 7) +#define DETSRC_INT_1 (0x01 << 0) +#define DETSRC_INT_2 (0x01 << 1) +#define DETSRC_PULSE_Z (0x01 << 2) +#define DETSRC_PULSE_Y (0x01 << 3) +#define DETSRC_PULSE_X (0x01 << 4) +#define DETSRC_LEVEL_Z (0x01 << 5) +#define DETSRC_LEVEL_Y (0x01 << 6) +#define DETSRC_LEVEL_X (0x01 << 7) /* For MCTL */ -#define MCTL_SHIFT_MODE (0) -#define MCTL_SHIFT_G (2) -#define MCTL_MASK_MODE (0x03) -#define MCTL_MASK_G (0x0c) -#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE) -#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE) -#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE) -#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE) -#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G) -#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G) -#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G) -#define MCTL_PIN_INT1 (0x01 << 6) +#define MCTL_SHIFT_MODE (0) +#define MCTL_SHIFT_G (2) +#define MCTL_MASK_MODE (0x03) +#define MCTL_MASK_G (0x0c) +#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE) +#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE) +#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE) +#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE) +#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G) +#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G) +#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G) +#define MCTL_PIN_INT1 (0x01 << 6) /* For INTRST */ -#define INTRST_INT_1 (0x01 << 0) -#define INTRST_INT_2 (0x01 << 1) +#define INTRST_INT_1 (0x01 << 0) +#define INTRST_INT_2 (0x01 << 1) /* For CTL1 */ -#define CTL1_SHIFT_INTPIN (0) -#define CTL1_SHIFT_INT (1) -#define CTL1_SHIFT_AXES (3) -#define CTL1_SHIFT_THRESHOLD (6) -#define CTL1_SHIFT_BANDWIDTH (7) -#define CTL1_MASK_AXES (0x38) -#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN) -#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT) -#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT) -#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT) -#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES) -#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES) -#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES) -#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD) -#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD) -#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH) -#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH) +#define CTL1_SHIFT_INTPIN (0) +#define CTL1_SHIFT_INT (1) +#define CTL1_SHIFT_AXES (3) +#define CTL1_SHIFT_THRESHOLD (6) +#define CTL1_SHIFT_BANDWIDTH (7) +#define CTL1_MASK_AXES (0x38) +#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN) +#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT) +#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT) +#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT) +#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES) +#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES) +#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES) +#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD) +#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD) +#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH) +#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH) /* For CTL2 */ -#define CTL1_SHIFT_LEVEL (0) -#define CTL1_SHIFT_PULSE (1) -#define CTL1_SHIFT_DRIVE (2) -#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL) -#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL) -#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE) -#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE) -#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE) -#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE) +#define CTL1_SHIFT_LEVEL (0) +#define CTL1_SHIFT_PULSE (1) +#define CTL1_SHIFT_DRIVE (2) +#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL) +#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL) +#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE) +#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE) +#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE) +#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE) #endif /* __MMA7455L_H__ */ diff --git a/bsp/efm32/rtconfig.h b/bsp/efm32/rtconfig.h index 58159f90b3..3f62ec7195 100644 --- a/bsp/efm32/rtconfig.h +++ b/bsp/efm32/rtconfig.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file rtconfig.h * @brief RT-Thread config file - * COPYRIGHT (C) 2009, RT-Thread Development Team + * COPYRIGHT (C) 2009, RT-Thread Development Team * @author * @version 1.0 ******************************************************************************* @@ -22,23 +22,23 @@ #define EFM32GG_DK3750 /* RT_NAME_MAX */ -#define RT_NAME_MAX (8) +#define RT_NAME_MAX (8) /* RT_ALIGN_SIZE */ -#define RT_ALIGN_SIZE (4) +#define RT_ALIGN_SIZE (4) /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX (32) +#define RT_THREAD_PRIORITY_MAX (32) /* Tick per Second */ -#define RT_TICK_PER_SECOND (100) +#define RT_TICK_PER_SECOND (100) /* SECTION: RT_DEBUG */ #define RT_DEBUG #define RT_DEBUG_COLOR -//#define RT_DEBUG_MEM (1) -//#define RT_DEBUG_SCHEDULER (1) -//#define RT_DEBUG_IPC (1) +//#define RT_DEBUG_MEM (1) +//#define RT_DEBUG_SCHEDULER (1) +//#define RT_DEBUG_IPC (1) //#define THREAD_DEBUG //#define IRQ_DEBUG #define RT_USING_OVERFLOW_CHECK @@ -69,9 +69,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO (4) -#define RT_TIMER_THREAD_STACK_SIZE (512) -#define RT_TIMER_TICK_PER_SECOND (10) +#define RT_TIMER_THREAD_PRIO (4) +#define RT_TIMER_THREAD_STACK_SIZE (512) +#define RT_TIMER_TICK_PER_SECOND (10) /* SECTION: IPC */ /* Using Semaphore*/ @@ -134,10 +134,10 @@ #define EFM32_SPI_CLK_MODE(mode) (mode << 3) /* clock mode */ #if defined(EFM32_G8XX_STK) -//#define RT_USING_USART0 (0x0UL) -//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER) -//#define RT_USART0_NAME "spi0" -//#define RT_USART0_USING_DMA (0x1UL) +//#define RT_USING_USART0 (0x0UL) +//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER) +//#define RT_USART0_NAME "spi0" +//#define RT_USART0_USING_DMA (0x1UL) #elif defined(EFM32_GXXX_DK) #define RT_USING_USART0 (0x2UL) #define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \ @@ -165,28 +165,28 @@ #endif /* SECTION: IIC options */ -//#define RT_USING_IIC0 0x3UL -#define RT_IIC0_NAME "iic0" +//#define RT_USING_IIC0 0x3UL +#define RT_IIC0_NAME "iic0" /* SECTION: ACMP options */ //#define RT_USING_ACMP0 -#define RT_ACMP0_NAME "acmp0" +#define RT_ACMP0_NAME "acmp0" /* SECTION: ADC options */ #define RT_USING_ADC0 -#define RT_ADC0_NAME "adc0" +#define RT_ADC0_NAME "adc0" #if defined(RT_USING_ADC0) #define RT_USING_MISC #endif /* SECTION: TIMER options */ -//#define RT_USING_TIMER2 (0x00) /* Continuous mode */ -#define RT_TIMER2_NAME "tmr2" +//#define RT_USING_TIMER2 (0x00) /* Continuous mode */ +#define RT_TIMER2_NAME "tmr2" /* SECTION: RTC options */ #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750)) #define RT_USING_RTC -#define RT_RTC_NAME "rtc" +#define RT_RTC_NAME "rtc" #endif /* SECTION: Serial options */ @@ -199,9 +199,9 @@ #define EFM_LEUART1 (0x21UL) #if defined(EFM32_G8XX_STK) -#define RT_CONSOLE_DEVICE (EFM_USART1) +#define RT_CONSOLE_DEVICE (EFM_USART1) #elif defined(EFM32_GXXX_DK) -#define RT_CONSOLE_DEVICE (EFM_USART1) +#define RT_CONSOLE_DEVICE (EFM_USART1) #elif defined(EFM32GG_DK3750) #if defined(EFM32GG_DK3750_USING_LEUART1) #define RT_CONSOLE_DEVICE (EFM_LEUART1) @@ -217,7 +217,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE (128) +#define RT_CONSOLEBUF_SIZE (128) /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -226,12 +226,12 @@ #define FINSH_USING_DESCRIPTION /* SECTION: Peripheral devices */ -#define EFM32_INTERFACE_ADC (0) -#define EFM32_INTERFACE_IIC (1) -#define EFM32_INTERFACE_SPI (2) +#define EFM32_INTERFACE_ADC (0) +#define EFM32_INTERFACE_IIC (1) +#define EFM32_INTERFACE_SPI (2) #if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750)) -//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */ -//#define EFM32_USING_SFLASH /* SPI Flash */ +//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */ +//#define EFM32_USING_SFLASH /* SPI Flash */ #define EFM32_USING_SPISD /* MicroSD card */ //#define EFM32_USING_ETHERNET /* Ethernet controller */ //#define EFM32_USING_LCD /* TFT LCD */ @@ -240,30 +240,30 @@ #if defined(EFM32_USING_ACCEL) #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC) -#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME -#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */ +#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME +#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */ #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC) -#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME +#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME #endif #endif #if defined(EFM32_USING_SFLASH) -#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME +#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME #endif #if defined(EFM32_USING_SPISD) -#define SPISD_USING_DEVICE_NAME RT_USART0_NAME -#define SPISD_DEVICE_NAME "spiSd" +#define SPISD_USING_DEVICE_NAME RT_USART0_NAME +#define SPISD_DEVICE_NAME "spiSd" #endif #if defined(EFM32_USING_ETHERNET) #if defined(EFM32_GXXX_DK) - #define ETH_USING_DEVICE_NAME RT_USART2_NAME + #define ETH_USING_DEVICE_NAME RT_USART2_NAME #elif defined(EFM32GG_DK3750) - #define ETH_USING_DEVICE_NAME RT_USART1_NAME + #define ETH_USING_DEVICE_NAME RT_USART1_NAME #endif -#define ETH_DEVICE_NAME "spiEth" -#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05} +#define ETH_DEVICE_NAME "spiEth" +#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05} #endif /* SECTION: device filesystem */ @@ -271,9 +271,9 @@ #define RT_USING_DFS /* the max number of mounted filesystem */ #define DFS_FILESYSTEMS_MAX (2) -/* the max number of opened files */ +/* the max number of opened files */ #define DFS_FD_MAX (4) -/* the max number of cached sector */ +/* the max number of cached sector */ #define DFS_CACHE_MAX_NUM (4) #endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */ #if defined(EFM32_USING_SPISD) @@ -288,8 +288,8 @@ #if defined(EFM32_USING_ETHERNET) #define EFM32_USING_ETH_HTTPD //#define EFM32_USING_ETH_UTILS -//#define hostName "onelife.dyndns.org" -//#define userPwdB64 "dXNlcjpwYXNzd2Q=" +//#define hostName "onelife.dyndns.org" +//#define userPwdB64 "dXNlcjpwYXNzd2Q=" //#define RT_USING_LWIP //#define RT_USING_NETUTILS @@ -308,37 +308,37 @@ //#define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM (2) +#define RT_LWIP_TCP_PCB_NUM (2) /* ip address of target*/ -#define RT_LWIP_IPADDR0 (192) -#define RT_LWIP_IPADDR1 (168) -#define RT_LWIP_IPADDR2 (1) -#define RT_LWIP_IPADDR3 (118) +#define RT_LWIP_IPADDR0 (192) +#define RT_LWIP_IPADDR1 (168) +#define RT_LWIP_IPADDR2 (1) +#define RT_LWIP_IPADDR3 (118) /* gateway address of target*/ -#define RT_LWIP_GWADDR0 (192) -#define RT_LWIP_GWADDR1 (168) -#define RT_LWIP_GWADDR2 (1) -#define RT_LWIP_GWADDR3 (1) +#define RT_LWIP_GWADDR0 (192) +#define RT_LWIP_GWADDR1 (168) +#define RT_LWIP_GWADDR2 (1) +#define RT_LWIP_GWADDR3 (1) /* mask address of target*/ -#define RT_LWIP_MSKADDR0 (255) -#define RT_LWIP_MSKADDR1 (255) -#define RT_LWIP_MSKADDR2 (255) -#define RT_LWIP_MSKADDR3 (0) +#define RT_LWIP_MSKADDR0 (255) +#define RT_LWIP_MSKADDR1 (255) +#define RT_LWIP_MSKADDR2 (255) +#define RT_LWIP_MSKADDR3 (0) /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY (12) -#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4) -#define RT_LWIP_TCPTHREAD_STACKSIZE (1024) +#define RT_LWIP_TCPTHREAD_PRIORITY (12) +#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4) +#define RT_LWIP_TCPTHREAD_STACKSIZE (1024) /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY (15) -#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4) -#define RT_LWIP_ETHTHREAD_STACKSIZE (512) +#define RT_LWIP_ETHTHREAD_PRIORITY (15) +#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4) +#define RT_LWIP_ETHTHREAD_STACKSIZE (512) #endif /* defined(EFM32_USING_ETHERNET) */ /* SECTION: RTGUI support */ #if defined(EFM32_USING_LCD) -#define LCD_USING_DEVICE_NAME RT_USART1_NAME +#define LCD_USING_DEVICE_NAME RT_USART1_NAME #define LCD_DEVICE_NAME "lcd" /* using RTGUI support */ // #define RT_USING_RTGUI diff --git a/bsp/efm32/startup.c b/bsp/efm32/startup.c index 9a70f1278a..d769bbf99c 100644 --- a/bsp/efm32/startup.c +++ b/bsp/efm32/startup.c @@ -10,12 +10,12 @@ * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE ******************************************************************************* * @section Change Logs - * Date Author Notes + * Date Author Notes * 2006-08-31 Bernard first implementation * 2010-12-29 onelife Modify for EFM32 * 2011-12-20 onelife Add RTGUI initialization routine * 2012-02-21 onelife Add energy management initialization routine - * 2012-05-15 onelife Modified to compatible with CMSIS v3 + * 2012-05-15 onelife Modified to compatible with CMSIS v3 ******************************************************************************/ /***************************************************************************//** diff --git a/bsp/fh8620/applications/main.c b/bsp/fh8620/applications/main.c index fe690504d1..366245b48a 100644 --- a/bsp/fh8620/applications/main.c +++ b/bsp/fh8620/applications/main.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -27,18 +27,18 @@ void init_thread(void *parameter) { - rt_components_init(); + rt_components_init(); - return ; + return ; } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - tid = rt_thread_create("init", init_thread, RT_NULL, - 4096, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid) rt_thread_startup(tid); + tid = rt_thread_create("init", init_thread, RT_NULL, + 4096, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid) rt_thread_startup(tid); - return 0; + return 0; } diff --git a/bsp/fh8620/drivers/acw.c b/bsp/fh8620/drivers/acw.c index 49e10a3bda..6099ff0aa3 100644 --- a/bsp/fh8620/drivers/acw.c +++ b/bsp/fh8620/drivers/acw.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -30,12 +30,12 @@ #include "dma.h" #ifdef RT_USING_FH_ACW #if 1 -typedef struct +typedef struct { - unsigned int base; - void *vbase; - unsigned int size; - unsigned int align; + unsigned int base; + void *vbase; + unsigned int size; + unsigned int align; }MEM_DESC; #define ACW_SELFTEST 0 int buffer_malloc_withname(MEM_DESC *mem, int size, int align, char* name); @@ -222,9 +222,9 @@ void fh_acw_stop_playback(struct fh_audio_cfg *audio_config) audio_config->playback.state = stopping; writel(0, audio_dev.reg_base + ACW_TXFIFO_CTRL);//tx fifo disable if(audio_config->plauback_trans->channel_number != ACW_PLY_DMA_CHAN) - goto free_mem; + goto free_mem; if(!audio_config->plauback_trans->first_lli) - goto free_channel; + goto free_channel; audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->plauback_trans); audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->plauback_trans); free_channel: @@ -259,9 +259,9 @@ void fh_acw_stop_capture(struct fh_audio_cfg *audio_config) writel(0, audio_dev.reg_base + 8);//rx fifo disable if(audio_config->capture_trans->channel_number != ACW_CAP_DMA_CHAN) - goto free_mem; + goto free_mem; if(!audio_config->capture_trans->first_lli) - goto free_channel; + goto free_channel; audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->capture_trans); audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->capture_trans); @@ -286,10 +286,10 @@ void switch_io_type(enum audio_type type, enum io_select io_type) { rt_kprintf("audio input changed to mic_in\n"); writel( reg & (~(1<<1)),audio_dev.reg_base + ACW_ADC_PATH_CTRL); - reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL); - reg = reg & (~(1<<3)); - reg |=(0x1<<3); - writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL); + reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL); + reg = reg & (~(1<<3)); + reg |=(0x1<<3); + writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL); } else if (line_in == io_type) { @@ -397,7 +397,7 @@ void switch_input_volume(int volume) param = get_param_from_volume(volume); if (param < 0) { - rt_kprintf("capture volume error\n"); + rt_kprintf("capture volume error\n"); return; } @@ -511,25 +511,25 @@ int register_tx_dma(struct fh_audio_cfg *audio_config) if(playback_trans->channel_number == ACW_PLY_DMA_CHAN){ - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans); - if(ret){ - rt_kprintf("can't playback cyclic prepare \n"); - return RT_ERROR; - } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans); - if(ret){ - rt_kprintf("can't playback cyclic start \n"); - return RT_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans); + if(ret){ + rt_kprintf("can't playback cyclic prepare \n"); + return RT_ERROR; + } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans); + if(ret){ + rt_kprintf("can't playback cyclic start \n"); + return RT_ERROR; + } } else - return RT_ERROR; + return RT_ERROR; return 0; } int register_rx_dma( struct fh_audio_cfg *audio_config) { - int ret; + int ret; struct dma_transfer *capture_slave; capture_slave = audio_config->capture_trans; struct rt_dma_device *rt_dma_dev; @@ -546,19 +546,19 @@ int register_rx_dma( struct fh_audio_cfg *audio_config) return RT_ERROR; } if(capture_slave->channel_number==ACW_CAP_DMA_CHAN){ - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave); - if(ret){ - rt_kprintf("can't capture cyclic prepare \n"); - return RT_ERROR; - } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave); - if(ret){ - rt_kprintf("can't capture cyclic start \n"); - return RT_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave); + if(ret){ + rt_kprintf("can't capture cyclic prepare \n"); + return RT_ERROR; + } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave); + if(ret){ + rt_kprintf("can't capture cyclic start \n"); + return RT_ERROR; + } } else - return RT_ERROR; + return RT_ERROR; writel(0x11,audio_dev.reg_base + ACW_RXFIFO_CTRL);//clear rx fifo writel(0x30029,audio_dev.reg_base + ACW_RXFIFO_CTRL);/*enable rx fifo*/ @@ -614,13 +614,13 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config) audio_config->playback.state = running; ret = audio_request_playback_channel(audio_config); if(ret){ - rt_kprintf("can't request playback channel\n"); - return ret; + rt_kprintf("can't request playback channel\n"); + return ret; } ret = register_tx_dma(audio_config); if (ret < 0) { - rt_kprintf("can't register tx dma\n"); + rt_kprintf("can't register tx dma\n"); return ret; } rt_list_init(&(playback_wq.list)); @@ -638,7 +638,7 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config) int fh_acw_start_capture(struct fh_audio_cfg *audio_config) { - int ret; + int ret; if(audio_config->capture.state == running) { return 0; @@ -654,8 +654,8 @@ int fh_acw_start_capture(struct fh_audio_cfg *audio_config) audio_config->capture.state = running; ret = audio_request_capture_channel(audio_config); if(ret){ - rt_kprintf("can't request capture channel \n"); - return ret; + rt_kprintf("can't request capture channel \n"); + return ret; } return register_rx_dma(audio_config); @@ -698,12 +698,12 @@ static void fh_acw_tx_dma_done(void *arg) audio_config->playback.hw_ptr = audio_config->playback.hw_ptr - audio_config->playback.size; } - int avail = avail_data_len(playback,audio_config); - if (avail > audio_config->playback.cfg.period_bytes) - { + int avail = avail_data_len(playback,audio_config); + if (avail > audio_config->playback.cfg.period_bytes) + { - rt_sem_release(&audio_config->sem_playback); - } + rt_sem_release(&audio_config->sem_playback); + } #endif } @@ -719,12 +719,12 @@ int arg_config_support(struct fh_audio_cfg_arg * cfg) ret = get_param_from_volume(cfg->volume); if (ret < 0) { - rt_kprintf("invalid volume\n"); + rt_kprintf("invalid volume\n"); return -EINVAL; } ret = get_factor_from_table(cfg->rate); if (ret < 0) { - rt_kprintf("invalid rate\n"); + rt_kprintf("invalid rate\n"); return -EINVAL; } return 0; @@ -1084,7 +1084,7 @@ static void fh_audio_interrupt(int irq, void *param) void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg *audio_config) { - if(aiaotype == mic_in || aiaotype == line_in){ + if(aiaotype == mic_in || aiaotype == line_in){ audio_config->capture.area = (void *)fh_dma_mem_malloc(audio_config->capture.cfg.buffer_bytes \ + audio_config->capture.cfg.period_bytes); @@ -1093,8 +1093,8 @@ void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg *audio_config) rt_kprintf("no enough mem for capture buffer alloc\n"); return ; } - } - if(aiaotype == speaker_out || aiaotype == line_out){ + } + if(aiaotype == speaker_out || aiaotype == line_out){ audio_config->playback.area = (void *)fh_dma_mem_malloc(audio_config->playback.cfg.buffer_bytes \ + audio_config->playback.cfg.period_bytes); @@ -1169,9 +1169,9 @@ int audio_request_capture_channel(struct fh_audio_cfg *audio_config){ rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_rx_transfer); ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_rx_transfer); if(ret){ - rt_kprintf("can't request capture channel\n"); - dma_rx_transfer->channel_number =0xff; - return -ret; + rt_kprintf("can't request capture channel\n"); + dma_rx_transfer->channel_number =0xff; + return -ret; } } @@ -1219,9 +1219,9 @@ int audio_request_playback_channel(struct fh_audio_cfg *audio_config) rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_tx_transfer); ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_tx_transfer); if(ret){ - rt_kprintf("can't request playbak channel\n"); - dma_tx_transfer->channel_number = 0xff; - return -ret; + rt_kprintf("can't request playbak channel\n"); + dma_tx_transfer->channel_number = 0xff; + return -ret; } return 0; @@ -1320,7 +1320,7 @@ void fh_acw_test(){ cfg.frame_bit = 16; cfg.io_type = mic_in; - + cfg.period_size = BUFF_SIZE/8; cfg.rate = 8000; cfg.volume = 80; @@ -1344,18 +1344,18 @@ void fh_acw_test(){ ret = acw_dev->control(acw_dev,AC_AI_EN,&cfg); if(ret) - acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg); + acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg); cfg.io_type = line_out; acw_dev->control(acw_dev,AC_INIT_PLAYBACK_MEM,&cfg); ret = acw_dev->control(acw_dev,AC_AO_EN,&cfg); if(ret){ - acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg); + acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg); // acw_dev->control(acw_dev,AC_SET_OUTPUT_MODE,&output); - return ; + return ; } - for(i=0;i<100;i++) + for(i=0;i<100;i++) { rx: @@ -1374,7 +1374,7 @@ tx: acw_dev->write(acw_dev,0,&rx_buff[0],1024*8); } - acw_dev->close(acw_dev); + acw_dev->close(acw_dev); } #ifdef RT_USING_FINSH diff --git a/bsp/fh8620/drivers/acw.h b/bsp/fh8620/drivers/acw.h index 2156d343f4..82fce3b9ff 100644 --- a/bsp/fh8620/drivers/acw.h +++ b/bsp/fh8620/drivers/acw.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ACW_H_ #define ACW_H_ #include <rtthread.h> @@ -37,86 +37,86 @@ typedef unsigned long long dma_addr_t; struct scatterlist { #ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; + unsigned long sg_magic; #endif - unsigned long page_link; - unsigned int offset; - unsigned int length; - dma_addr_t dma_address; + unsigned long page_link; + unsigned int offset; + unsigned int length; + dma_addr_t dma_address; #ifdef CONFIG_NEED_SG_DMA_LENGTH - unsigned int dma_length; + unsigned int dma_length; #endif }; #define readl(a) (*(volatile rt_uint32_t *)(a)) -#define rkqueue_struct rt_workqueue -#define work_struct rt_work -#define INIT_WORK(work,func) rt_work_init(work,func,RT_NULL); -#define queue_work rt_workqueue_dowork +#define rkqueue_struct rt_workqueue +#define work_struct rt_work +#define INIT_WORK(work,func) rt_work_init(work,func,RT_NULL); +#define queue_work rt_workqueue_dowork //timer -#define timer_list rt_timer -#define wait_queue_head_t struct rt_event -#define init_waitqueue_head(event_t) rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO) +#define timer_list rt_timer +#define wait_queue_head_t struct rt_event +#define init_waitqueue_head(event_t) rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO) typedef enum{ - AC_SR_8K = 8000, - AC_SR_16K = 16000, - AC_SR_32K = 32000, - AC_SR_441K = 44100, - AC_SR_48K = 48000, + AC_SR_8K = 8000, + AC_SR_16K = 16000, + AC_SR_32K = 32000, + AC_SR_441K = 44100, + AC_SR_48K = 48000, } FH_AC_SAMPLE_RATE_E; typedef enum{ - AC_BW_8 = 8, - AC_BW_16 = 16, - AC_BW_24 = 24, + AC_BW_8 = 8, + AC_BW_16 = 16, + AC_BW_24 = 24, } FH_AC_BIT_WIDTH_E; enum io_select{ - mic_in = 0, - line_in = 1, - speaker_out = 2, - line_out = 3, + mic_in = 0, + line_in = 1, + speaker_out = 2, + line_out = 3, }; struct fh_audio_cfg_arg{ - enum io_select io_type; - int volume; - int rate; - int frame_bit; - int channels; - int buffer_size; - int period_size; + enum io_select io_type; + int volume; + int rate; + int frame_bit; + int channels; + int buffer_size; + int period_size; }; typedef struct{ - unsigned int len; - unsigned char *data; + unsigned int len; + unsigned char *data; }FH_AC_FRAME_S; typedef enum{ - FH_AC_MIC_IN = 0, - FH_AC_LINE_IN = 1, - FH_AC_SPK_OUT = 2, - FH_AC_LINE_OUT = 3 + FH_AC_MIC_IN = 0, + FH_AC_LINE_IN = 1, + FH_AC_SPK_OUT = 2, + FH_AC_LINE_OUT = 3 }FH_AC_IO_TYPE_E; typedef struct { - FH_AC_IO_TYPE_E io_type; - FH_AC_SAMPLE_RATE_E sample_rate; - FH_AC_BIT_WIDTH_E bit_width; - unsigned int channels; - unsigned int period_size; - unsigned int volume; + FH_AC_IO_TYPE_E io_type; + FH_AC_SAMPLE_RATE_E sample_rate; + FH_AC_BIT_WIDTH_E bit_width; + unsigned int channels; + unsigned int period_size; + unsigned int volume; } FH_AC_CONFIG; struct device_dma_parameters { - /* - * a low level driver may set these to teach IOMMU code about - * sg limitations. - */ - unsigned int max_segment_size; - unsigned long segment_boundary_mask; + /* + * a low level driver may set these to teach IOMMU code about + * sg limitations. + */ + unsigned int max_segment_size; + unsigned long segment_boundary_mask; }; struct list_head { @@ -124,32 +124,32 @@ struct list_head { struct list_head *prev; }; struct dma_coherent_mem { - void *virt_base; - dma_addr_t device_base; - int size; - int flags; - unsigned long *bitmap; + void *virt_base; + dma_addr_t device_base; + int size; + int flags; + unsigned long *bitmap; }; struct device_acw{ - unsigned long long *dma_mask; /* dma mask (if dma'able device) */ - unsigned long long coherent_dma_mask;/* Like dma_mask, but for - alloc_coherent mappings as - not all hardware supports - 64 bit addresses for consistent - allocations such descriptors. */ - struct device_dma_parameters *dma_parms; + unsigned long long *dma_mask; /* dma mask (if dma'able device) */ + unsigned long long coherent_dma_mask;/* Like dma_mask, but for + alloc_coherent mappings as + not all hardware supports + 64 bit addresses for consistent + allocations such descriptors. */ + struct device_dma_parameters *dma_parms; - struct list_head dma_pools; + struct list_head dma_pools; - struct dma_coherent_mem *dma_mem; + struct dma_coherent_mem *dma_mem; }; #define false 0 #define true 1 -#define AC_INIT_CAPTURE_MEM 0x10 -#define AC_INIT_PLAYBACK_MEM 0x11 +#define AC_INIT_CAPTURE_MEM 0x10 +#define AC_INIT_PLAYBACK_MEM 0x11 #define AC_SET_VOL 0x12 @@ -160,73 +160,73 @@ struct device_acw{ #define AC_AI_EN 0x15 #define AC_AO_EN 0x16 #define AC_AI_DISABLE 0x17 -#define AC_AO_DISABLE 0x18 -#define AC_AI_PAUSE 0x19 -#define AC_AI_RESUME 0x1a -#define AC_AO_PAUSE 0x1b -#define AC_AO_RESUME 0x1c -#define AC_MIC_BOOST 0x1d +#define AC_AO_DISABLE 0x18 +#define AC_AI_PAUSE 0x19 +#define AC_AI_RESUME 0x1a +#define AC_AO_PAUSE 0x1b +#define AC_AO_RESUME 0x1c +#define AC_MIC_BOOST 0x1d -#define POLLIN 0x001 /* There is data to read. */ -#define POLLPRI 0x002 /* There is urgent data to read. */ -#define POLLOUT 0x004 /* Writing now will not block. */ +#define POLLIN 0x001 /* There is data to read. */ +#define POLLPRI 0x002 /* There is urgent data to read. */ +#define POLLOUT 0x004 /* Writing now will not block. */ /* These values are defined in XPG4.2. */ -# define POLLRDNORM 0x040 /* Normal data may be read. */ -# define POLLRDBAND 0x080 /* Priority data may be read. */ -# define POLLWRNORM 0x100 /* Writing now will not block. */ -# define POLLWRBAND 0x200 /* Priority data may be written. */ +# define POLLRDNORM 0x040 /* Normal data may be read. */ +# define POLLRDBAND 0x080 /* Priority data may be read. */ +# define POLLWRNORM 0x100 /* Writing now will not block. */ +# define POLLWRBAND 0x200 /* Priority data may be written. */ /* These are extensions for Linux. */ -# define POLLMSG 0x400 -# define POLLREMOVE 0x1000 -# define POLLRDHUP 0x2000 +# define POLLMSG 0x400 +# define POLLREMOVE 0x1000 +# define POLLRDHUP 0x2000 /* Event types always implicitly polled for. These bits need not be set in `events', but they will appear in `revents' to indicate the status of the file descriptor. */ -#define POLLERR 0x008 /* Error condition. */ -#define POLLHUP 0x010 /* Hung up. */ -#define POLLNVAL 0x020 /* Invalid polling request. */ +#define POLLERR 0x008 /* Error condition. */ +#define POLLHUP 0x010 /* Hung up. */ +#define POLLNVAL 0x020 /* Invalid polling request. */ -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Argument list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ extern void fh_audio_init(void); extern void fh_acw_test(); #endif diff --git a/bsp/fh8620/drivers/dma.c b/bsp/fh8620/drivers/dma.c index 394ac2a6a3..3105f9261b 100644 --- a/bsp/fh8620/drivers/dma.c +++ b/bsp/fh8620/drivers/dma.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -88,7 +88,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev, *****************************************************************************/ static rt_err_t rt_dma_init(struct rt_device *dev) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -107,7 +107,7 @@ static rt_err_t rt_dma_open(struct rt_device *dev, rt_uint16_t oflag) static rt_err_t rt_dma_close(struct rt_device *dev) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -124,7 +124,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev, rt_uint8_t cmd, void *args) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -141,7 +141,7 @@ rt_err_t rt_hw_dma_register(struct rt_dma_device *dma, rt_uint32_t flag, void *data) { - rt_uint32_t ret; + rt_uint32_t ret; struct rt_device *device; RT_ASSERT(dma != RT_NULL); diff --git a/bsp/fh8620/drivers/dma.h b/bsp/fh8620/drivers/dma.h index c8c3fbf574..2ef3253196 100644 --- a/bsp/fh8620/drivers/dma.h +++ b/bsp/fh8620/drivers/dma.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,31 +29,31 @@ #include <rtthread.h> /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ -#define RT_DEVICE_CTRL_DMA_OPEN (1) -#define RT_DEVICE_CTRL_DMA_CLOSE (2) -#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL (3) -#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL (4) -#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER (5) +#define RT_DEVICE_CTRL_DMA_OPEN (1) +#define RT_DEVICE_CTRL_DMA_CLOSE (2) +#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL (3) +#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL (4) +#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER (5) //cyclic add func below.... -#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE (6) -#define RT_DEVICE_CTRL_DMA_CYCLIC_START (7) -#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP (8) -#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE (9) +#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE (6) +#define RT_DEVICE_CTRL_DMA_CYCLIC_START (7) +#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP (8) +#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE (9) -//#define RT_DEVICE_CTRL_ (3) /* get the left time before reboot(in seconds) */ +//#define RT_DEVICE_CTRL_ (3) /* get the left time before reboot(in seconds) */ //#define RT_DEVICE_CTRL_ (4) /* refresh watchdog */ //#define RT_DEVICE_CTRL_ (5) /* start watchdog */ //#define RT_DEVICE_CTRL_ (6) /* stop watchdog */ @@ -64,13 +64,13 @@ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ struct rt_dma_ops; struct rt_dma_device { - // the parent must be the fitst para.. + // the parent must be the fitst para.. struct rt_device parent; struct rt_dma_ops *ops; }; @@ -91,7 +91,7 @@ struct rt_dma_ops /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ rt_err_t rt_hw_dma_register(struct rt_dma_device *dma, const char *name, diff --git a/bsp/fh8620/drivers/dma_mem.c b/bsp/fh8620/drivers/dma_mem.c index 52c9e56b4a..9360ab5b81 100644 --- a/bsp/fh8620/drivers/dma_mem.c +++ b/bsp/fh8620/drivers/dma_mem.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -86,27 +86,27 @@ static struct rt_memheap dma_heap = {0}; * what does this function returned? *****************************************************************************/ rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size){ - return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size); + return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size); } void *fh_dma_mem_malloc(rt_uint32_t size){ - return rt_memheap_alloc(&dma_heap, size); + return rt_memheap_alloc(&dma_heap, size); } void fh_dma_mem_free(void *ptr){ - rt_memheap_free(ptr); + rt_memheap_free(ptr); } #ifdef FH_TEST_DMA_MEM int dma_mem_debug(void *ptr){ - //rt_memheap_free(ptr); - rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr); - rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size); - rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size); - rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size); - return 0; + //rt_memheap_free(ptr); + rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr); + rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size); + rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size); + rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size); + return 0; } #endif diff --git a/bsp/fh8620/drivers/dma_mem.h b/bsp/fh8620/drivers/dma_mem.h index b431703a4a..fea4222432 100644 --- a/bsp/fh8620/drivers/dma_mem.h +++ b/bsp/fh8620/drivers/dma_mem.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef DMA_MEM_H_ #define DMA_MEM_H_ @@ -36,20 +36,20 @@ #include <rtthread.h> /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ @@ -61,7 +61,7 @@ /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ #ifdef RT_USING_DMA_MEM rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size); diff --git a/bsp/fh8620/drivers/fh_dma.c b/bsp/fh8620/drivers/fh_dma.c index c50ae1e1df..d44ecf4e1f 100644 --- a/bsp/fh8620/drivers/fh_dma.c +++ b/bsp/fh8620/drivers/fh_dma.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -45,187 +45,187 @@ //#define DMA_DEBUG #ifdef DMA_DEBUG -#define FH_DMA_DEBUG(fmt, args...) \ - rt_kprintf(fmt,##args); +#define FH_DMA_DEBUG(fmt, args...) \ + rt_kprintf(fmt,##args); #else #define FH_DMA_DEBUG(fmt, args...) #endif -#define DMA_REG_BASE (0xEE000000) -#define DMA_CONTROLLER_NUMBER (1) +#define DMA_REG_BASE (0xEE000000) +#define DMA_CONTROLLER_NUMBER (1) -#define WORK_QUEUE_STACK_SIZE 512 -#define WORK_QUEUE_PRIORITY 12 +#define WORK_QUEUE_STACK_SIZE 512 +#define WORK_QUEUE_PRIORITY 12 -#define TEST_PER_NO (10) +#define TEST_PER_NO (10) -#define DESC_MAX_SIZE (20) +#define DESC_MAX_SIZE (20) /********************************* * * copy from the linux core start * *********************************/ //this is the ip reg offset....don't change!!!!!!! -#define DW_DMA_MAX_NR_CHANNELS 8 +#define DW_DMA_MAX_NR_CHANNELS 8 /* * Redefine this macro to handle differences between 32- and 64-bit * addressing, big vs. little endian, etc. */ -#define DW_REG(name) rt_uint32_t name; rt_uint32_t __pad_##name +#define DW_REG(name) rt_uint32_t name; rt_uint32_t __pad_##name /* Hardware register definitions. */ struct dw_dma_chan_regs { - DW_REG(SAR); /* Source Address Register */ - DW_REG(DAR); /* Destination Address Register */ - DW_REG(LLP); /* Linked List Pointer */ - rt_uint32_t CTL_LO; /* Control Register Low */ - rt_uint32_t CTL_HI; /* Control Register High */ - DW_REG(SSTAT); - DW_REG(DSTAT); - DW_REG(SSTATAR); - DW_REG(DSTATAR); - rt_uint32_t CFG_LO; /* Configuration Register Low */ - rt_uint32_t CFG_HI; /* Configuration Register High */ - DW_REG(SGR); - DW_REG(DSR); + DW_REG(SAR); /* Source Address Register */ + DW_REG(DAR); /* Destination Address Register */ + DW_REG(LLP); /* Linked List Pointer */ + rt_uint32_t CTL_LO; /* Control Register Low */ + rt_uint32_t CTL_HI; /* Control Register High */ + DW_REG(SSTAT); + DW_REG(DSTAT); + DW_REG(SSTATAR); + DW_REG(DSTATAR); + rt_uint32_t CFG_LO; /* Configuration Register Low */ + rt_uint32_t CFG_HI; /* Configuration Register High */ + DW_REG(SGR); + DW_REG(DSR); }; struct dw_dma_irq_regs { - DW_REG(XFER); - DW_REG(BLOCK); - DW_REG(SRC_TRAN); - DW_REG(DST_TRAN); - DW_REG(ERROR); + DW_REG(XFER); + DW_REG(BLOCK); + DW_REG(SRC_TRAN); + DW_REG(DST_TRAN); + DW_REG(ERROR); }; struct dw_dma_regs { - /* per-channel registers */ - struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; + /* per-channel registers */ + struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; - /* irq handling */ - struct dw_dma_irq_regs RAW; /* r */ - struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ - struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ - struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ + /* irq handling */ + struct dw_dma_irq_regs RAW; /* r */ + struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ + struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ + struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ - DW_REG(STATUS_INT); /* r */ + DW_REG(STATUS_INT); /* r */ - /* software handshaking */ - DW_REG(REQ_SRC); - DW_REG(REQ_DST); - DW_REG(SGL_REQ_SRC); - DW_REG(SGL_REQ_DST); - DW_REG(LAST_SRC); - DW_REG(LAST_DST); + /* software handshaking */ + DW_REG(REQ_SRC); + DW_REG(REQ_DST); + DW_REG(SGL_REQ_SRC); + DW_REG(SGL_REQ_DST); + DW_REG(LAST_SRC); + DW_REG(LAST_DST); - /* miscellaneous */ - DW_REG(CFG); - DW_REG(CH_EN); - DW_REG(ID); - DW_REG(TEST); + /* miscellaneous */ + DW_REG(CFG); + DW_REG(CH_EN); + DW_REG(ID); + DW_REG(TEST); - /* optional encoded params, 0x3c8..0x3 */ + /* optional encoded params, 0x3c8..0x3 */ }; /* Bitfields in CTL_LO */ -#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ -#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ -#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) +#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ +#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ +#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) #define DWC_CTLL_DST_INC_MODE(n) ((n)<<7) -#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ -#define DWC_CTLL_DST_DEC (1<<7) -#define DWC_CTLL_DST_FIX (2<<7) +#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ +#define DWC_CTLL_DST_DEC (1<<7) +#define DWC_CTLL_DST_FIX (2<<7) #define DWC_CTLL_SRC_INC_MODE(n) ((n)<<9) -#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ -#define DWC_CTLL_SRC_DEC (1<<9) -#define DWC_CTLL_SRC_FIX (2<<9) -#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ -#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) -#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ -#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ -#define DWC_CTLL_FC(n) ((n) << 20) -#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ -#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ -#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ -#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ +#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ +#define DWC_CTLL_SRC_DEC (1<<9) +#define DWC_CTLL_SRC_FIX (2<<9) +#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ +#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) +#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ +#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ +#define DWC_CTLL_FC(n) ((n) << 20) +#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ +#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ +#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ +#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ /* plus 4 transfer types for peripheral-as-flow-controller */ -#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ -#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ -#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ -#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ +#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ +#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ +#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ +#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ /* Bitfields in CTL_HI */ -#define DWC_CTLH_DONE 0x00001000 -#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff +#define DWC_CTLH_DONE 0x00001000 +#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ -#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ -#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ -#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ -#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ +#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ +#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ +#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ +#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ -#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ -#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ -#define DWC_CFGL_MAX_BURST(x) ((x) << 20) -#define DWC_CFGL_RELOAD_SAR (1 << 30) -#define DWC_CFGL_RELOAD_DAR (1 << 31) +#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ +#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ +#define DWC_CFGL_MAX_BURST(x) ((x) << 20) +#define DWC_CFGL_RELOAD_SAR (1 << 30) +#define DWC_CFGL_RELOAD_DAR (1 << 31) /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */ -#define DWC_CFGH_DS_UPD_EN (1 << 5) -#define DWC_CFGH_SS_UPD_EN (1 << 6) +#define DWC_CFGH_DS_UPD_EN (1 << 5) +#define DWC_CFGH_SS_UPD_EN (1 << 6) /* Bitfields in SGR */ -#define DWC_SGR_SGI(x) ((x) << 0) -#define DWC_SGR_SGC(x) ((x) << 20) +#define DWC_SGR_SGI(x) ((x) << 0) +#define DWC_SGR_SGC(x) ((x) << 20) /* Bitfields in DSR */ -#define DWC_DSR_DSI(x) ((x) << 0) -#define DWC_DSR_DSC(x) ((x) << 20) +#define DWC_DSR_DSI(x) ((x) << 0) +#define DWC_DSR_DSC(x) ((x) << 20) /* Bitfields in CFG */ -#define DW_CFG_DMA_EN (1 << 0) +#define DW_CFG_DMA_EN (1 << 0) -#define DW_REGLEN 0x400 +#define DW_REGLEN 0x400 /* Platform-configurable bits in CFG_HI */ -#define DWC_CFGH_FCMODE (1 << 0) -#define DWC_CFGH_FIFO_MODE (1 << 1) -#define DWC_CFGH_PROTCTL(x) ((x) << 2) -#define DWC_CFGH_SRC_PER(x) ((x) << 7) -#define DWC_CFGH_DST_PER(x) ((x) << 11) +#define DWC_CFGH_FCMODE (1 << 0) +#define DWC_CFGH_FIFO_MODE (1 << 1) +#define DWC_CFGH_PROTCTL(x) ((x) << 2) +#define DWC_CFGH_SRC_PER(x) ((x) << 7) +#define DWC_CFGH_DST_PER(x) ((x) << 11) /* Platform-configurable bits in CFG_LO */ -#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ -#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) -#define DWC_CFGL_LOCK_CH_XACT (2 << 12) -#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ -#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) -#define DWC_CFGL_LOCK_BUS_XACT (2 << 14) -#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ -#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ -#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ -#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ +#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ +#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) +#define DWC_CFGL_LOCK_CH_XACT (2 << 12) +#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ +#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) +#define DWC_CFGL_LOCK_BUS_XACT (2 << 14) +#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ +#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ +#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ +#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ -#define lift_shift_bit_num(bit_num) (1<<bit_num) +#define lift_shift_bit_num(bit_num) (1<<bit_num) #define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) @@ -243,28 +243,28 @@ struct dw_dma_regs { #define dw_readl(dw, name) \ - __raw_readl(&(((struct dw_dma_regs *)dw->regs)->name)) + __raw_readl(&(((struct dw_dma_regs *)dw->regs)->name)) #define dw_writel(dw, name, val) \ - __raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name)) + __raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name)) #define dw_readw(dw, name) \ - __raw_readw(&(((struct dw_dma_regs *)dw->regs)->name)) + __raw_readw(&(((struct dw_dma_regs *)dw->regs)->name)) #define dw_writew(dw, name, val) \ - __raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name)) + __raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name)) -#define CHANNEL0 (lift_shift_bit_num(0)) -#define CHANNEL1 (lift_shift_bit_num(1)) -#define CHANNEL2 (lift_shift_bit_num(2)) -#define CHANNEL3 (lift_shift_bit_num(3)) +#define CHANNEL0 (lift_shift_bit_num(0)) +#define CHANNEL1 (lift_shift_bit_num(1)) +#define CHANNEL2 (lift_shift_bit_num(2)) +#define CHANNEL3 (lift_shift_bit_num(3)) #define channel_set_bit(dw, reg, mask) \ - dw_writel(dw, reg, ((mask) << 8) | (mask)) + dw_writel(dw, reg, ((mask) << 8) | (mask)) #define channel_clear_bit(dw, reg, mask) \ - dw_writel(dw, reg, ((mask) << 8) | 0) + dw_writel(dw, reg, ((mask) << 8) | 0) @@ -275,83 +275,83 @@ struct dw_dma_regs { ***************************************************************************/ struct dw_dma{ - //vadd - void *regs; - //padd - rt_uint32_t paddr; - rt_uint32_t irq; - rt_uint32_t channel_max_number; + //vadd + void *regs; + //padd + rt_uint32_t paddr; + rt_uint32_t irq; + rt_uint32_t channel_max_number; -#define CONTROLLER_STATUS_CLOSED (0) -#define CONTROLLER_STATUS_OPEN (1) - rt_uint32_t controller_status; -#define FH81_DMA_INIT_NOT_YET (0) -#define FH81_DMA_INIT_ALREADY (1) - rt_uint32_t init; - rt_uint32_t id; - char *name; - rt_uint32_t channel_work_done; +#define CONTROLLER_STATUS_CLOSED (0) +#define CONTROLLER_STATUS_OPEN (1) + rt_uint32_t controller_status; +#define FH81_DMA_INIT_NOT_YET (0) +#define FH81_DMA_INIT_ALREADY (1) + rt_uint32_t init; + rt_uint32_t id; + char *name; + rt_uint32_t channel_work_done; }; struct dma_channel { -#define CHANNEL_STATUS_CLOSED (0) -#define CHANNEL_STATUS_OPEN (1) -#define CHANNEL_STATUS_IDLE (2) -#define CHANNEL_STATUS_BUSY (3) +#define CHANNEL_STATUS_CLOSED (0) +#define CHANNEL_STATUS_OPEN (1) +#define CHANNEL_STATUS_IDLE (2) +#define CHANNEL_STATUS_BUSY (3) - rt_uint32_t channel_status; //open, busy ,closed - rt_uint32_t desc_trans_size; + rt_uint32_t channel_status; //open, busy ,closed + rt_uint32_t desc_trans_size; - //isr will set it complete. - struct rt_completion transfer_completion; - //add lock,when set the channel.lock it - struct rt_semaphore channel_lock; - //struct rt_mutex lock; - //rt_enter_critical(); - rt_list_t queue; - //active transfer now!!! - struct dma_transfer *active_trans; + //isr will set it complete. + struct rt_completion transfer_completion; + //add lock,when set the channel.lock it + struct rt_semaphore channel_lock; + //struct rt_mutex lock; + //rt_enter_critical(); + rt_list_t queue; + //active transfer now!!! + struct dma_transfer *active_trans; -#define SINGLE_TRANSFER (0) -#define CYCLIC_TRANSFER (1) -#define DEFAULT_TRANSFER SINGLE_TRANSFER - rt_uint32_t open_flag; - // +#define SINGLE_TRANSFER (0) +#define CYCLIC_TRANSFER (1) +#define DEFAULT_TRANSFER SINGLE_TRANSFER + rt_uint32_t open_flag; + // - //new add para... - rt_uint32_t desc_total_no; - rt_uint32_t free_index; - rt_uint32_t used_index; - rt_uint32_t desc_left_cnt; + //new add para... + rt_uint32_t desc_total_no; + rt_uint32_t free_index; + rt_uint32_t used_index; + rt_uint32_t desc_left_cnt; - rt_uint32_t allign_malloc; - struct dw_lli *base_lli; + rt_uint32_t allign_malloc; + struct dw_lli *base_lli; }; struct fh81_dma{ - //core use ,this must be the first para!!!! - struct rt_dma_device parent; - //myown - struct dw_dma dwc; - //channel obj - struct dma_channel dma_channel[FH81_MAX_CHANNEL]; + //core use ,this must be the first para!!!! + struct rt_dma_device parent; + //myown + struct dw_dma dwc; + //channel obj + struct dma_channel dma_channel[FH81_MAX_CHANNEL]; - //struct rt_workqueue* isr_workqueue; - //struct rt_work *isr_work; + //struct rt_workqueue* isr_workqueue; + //struct rt_work *isr_work; }; -#define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ - n = rt_list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ + n = rt_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) /****************************************************************************** @@ -384,8 +384,8 @@ static void rt_fh_dma_cyclic_free(struct dma_transfer *p); static struct rt_dma_ops fh81_dma_ops = { - init, - control + init, + control }; @@ -398,7 +398,7 @@ static struct rt_dma_ops fh81_dma_ops = * e.g. * static uint8_t ufoo; *****************************************************************************/ -static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; +static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; /* function body */ /***************************************************************************** @@ -411,80 +411,80 @@ static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; *****************************************************************************/ static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){ - return (in_addr + allign_size-1) & (~(allign_size - 1)); + return (in_addr + allign_size-1) & (~(allign_size - 1)); } struct dw_lli * get_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer,rt_uint32_t lli_size){ - struct dw_lli * ret_lli; - rt_uint32_t free_index; - rt_uint32_t allign_left; - rt_uint32_t totoal_desc; - rt_uint32_t actual_get_desc; - rt_uint32_t totoal_free_desc; - totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt; - free_index = p_dma->dma_channel[p_transfer->channel_number].free_index; - totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - allign_left = totoal_desc - free_index; + struct dw_lli * ret_lli; + rt_uint32_t free_index; + rt_uint32_t allign_left; + rt_uint32_t totoal_desc; + rt_uint32_t actual_get_desc; + rt_uint32_t totoal_free_desc; + totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt; + free_index = p_dma->dma_channel[p_transfer->channel_number].free_index; + totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + allign_left = totoal_desc - free_index; - //check first.. - if(totoal_free_desc < lli_size){ - rt_kprintf("not enough desc to get...\n"); - rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc); - return RT_NULL; - } - //rt_kprintf("get desc in...\n"); + //check first.. + if(totoal_free_desc < lli_size){ + rt_kprintf("not enough desc to get...\n"); + rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc); + return RT_NULL; + } + //rt_kprintf("get desc in...\n"); - //rt_kprintf("lli size is %d\n",lli_size); - if(lli_size > allign_left){ - //if allign desc not enough...just reset null.... - if((totoal_free_desc - allign_left) < lli_size){ - rt_kprintf("not enough desc to get...\n"); - rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left); - rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size)); - return RT_NULL; - } - else{ - actual_get_desc = allign_left +lli_size; - free_index = 0; - } - } + //rt_kprintf("lli size is %d\n",lli_size); + if(lli_size > allign_left){ + //if allign desc not enough...just reset null.... + if((totoal_free_desc - allign_left) < lli_size){ + rt_kprintf("not enough desc to get...\n"); + rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left); + rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size)); + return RT_NULL; + } + else{ + actual_get_desc = allign_left +lli_size; + free_index = 0; + } + } - //ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; + //ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; - ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; -// rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]); -// rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli); -// rt_kprintf("get desc request size:%08x\n",lli_size); -// rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no); -// rt_kprintf("one desc size is:%08x\n",sizeof( struct dw_lli)); + ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; +// rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]); +// rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli); +// rt_kprintf("get desc request size:%08x\n",lli_size); +// rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no); +// rt_kprintf("one desc size is:%08x\n",sizeof( struct dw_lli)); - p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc; + p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc; - //rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]); + //rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]); - p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc; - p_transfer->lli_size = lli_size; - p_transfer->actual_lli_size = actual_get_desc; - return ret_lli; + p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc; + p_transfer->lli_size = lli_size; + p_transfer->actual_lli_size = actual_get_desc; + return ret_lli; } rt_uint32_t put_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - struct dw_lli * ret_lli; - rt_uint32_t used_index; - rt_uint32_t lli_size; - //rt_kprintf("put desc in...\n"); - used_index = p_dma->dma_channel[p_transfer->channel_number].used_index; - lli_size = p_transfer->actual_lli_size; - p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size; - p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size; - p_transfer->lli_size = 0; - p_transfer->actual_lli_size = 0; - return 0; + struct dw_lli * ret_lli; + rt_uint32_t used_index; + rt_uint32_t lli_size; + //rt_kprintf("put desc in...\n"); + used_index = p_dma->dma_channel[p_transfer->channel_number].used_index; + lli_size = p_transfer->actual_lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size; + p_transfer->lli_size = 0; + p_transfer->actual_lli_size = 0; + return 0; } /***************************************************************************** @@ -499,17 +499,17 @@ rt_uint32_t put_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ static rt_err_t init (struct rt_dma_device *dma){ - //init the clk table + //init the clk table - struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; + struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; - FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own); + FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own); - //check the user data - RT_ASSERT(my_own != RT_NULL); + //check the user data + RT_ASSERT(my_own != RT_NULL); - return RT_EOK; + return RT_EOK; } @@ -528,12 +528,12 @@ static rt_err_t init (struct rt_dma_device *dma){ static void handle_dma_open(struct fh81_dma *p_dma){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; - dw_writel(temp_dwc, CFG, 1); - p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN; + dw_writel(temp_dwc, CFG, 1); + p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN; } @@ -549,27 +549,27 @@ static void handle_dma_open(struct fh81_dma *p_dma){ static void handle_dma_close(struct fh81_dma *p_dma){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; - //take lock - for(i=0;i<p_dma->dwc.channel_max_number;i++){ - rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER); + //take lock + for(i=0;i<p_dma->dwc.channel_max_number;i++){ + rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER); - channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i)); - p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; - } - dw_writel(temp_dwc, CFG, 0); - p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i)); + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + } + dw_writel(temp_dwc, CFG, 0); + p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED; - //release lock - for(i=0;i<p_dma->dwc.channel_max_number;i++){ - rt_sem_release(&p_dma->dma_channel[i].channel_lock); - } + //release lock + for(i=0;i<p_dma->dwc.channel_max_number;i++){ + rt_sem_release(&p_dma->dma_channel[i].channel_lock); + } - //destroy the workqueue.. - //rt_workqueue_destroy(p_dma->isr_workqueue); + //destroy the workqueue.. + //rt_workqueue_destroy(p_dma->isr_workqueue); } @@ -584,26 +584,26 @@ static void handle_dma_close(struct fh81_dma *p_dma){ * what does this function returned? *****************************************************************************/ -#define CHANNEL_REAL_FREE (0) -#define CHANNEL_NOT_FREE (1) +#define CHANNEL_REAL_FREE (0) +#define CHANNEL_NOT_FREE (1) static rt_uint32_t check_channel_real_free(struct fh81_dma *p_dma,rt_uint32_t channel_number){ - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_uint32_t ret_status; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_uint32_t ret_status; - RT_ASSERT(channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(channel_number < p_dma->dwc.channel_max_number); - ret_status = dw_readl(temp_dwc, CH_EN); - if(ret_status & lift_shift_bit_num(channel_number)){ - //the channel is still busy!!!error here - //FH_DMA_DEBUG("auto request channel error\n"); - return CHANNEL_NOT_FREE; - } - return CHANNEL_REAL_FREE; + ret_status = dw_readl(temp_dwc, CH_EN); + if(ret_status & lift_shift_bit_num(channel_number)){ + //the channel is still busy!!!error here + //FH_DMA_DEBUG("auto request channel error\n"); + return CHANNEL_NOT_FREE; + } + return CHANNEL_REAL_FREE; } @@ -620,110 +620,110 @@ static rt_uint32_t check_channel_real_free(struct fh81_dma *p_dma,rt_uint32_t c static rt_err_t handle_request_channel(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_err_t ret_status = RT_EOK; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_err_t ret_status = RT_EOK; - //handle if auto check channel... - if(p_transfer->channel_number == AUTO_FIND_CHANNEL){ - //check each channel lock,find a free channel... - for(i=0;i<p_dma->dwc.channel_max_number;i++){ - ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock); - if(ret_status == RT_EOK){ - break; - } - } + //handle if auto check channel... + if(p_transfer->channel_number == AUTO_FIND_CHANNEL){ + //check each channel lock,find a free channel... + for(i=0;i<p_dma->dwc.channel_max_number;i++){ + ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock); + if(ret_status == RT_EOK){ + break; + } + } - if(i < p_dma->dwc.channel_max_number){ - ret_status = check_channel_real_free(p_dma,i); - if(ret_status!= CHANNEL_REAL_FREE){ - FH_DMA_DEBUG("auto request channel error\n"); - RT_ASSERT(ret_status == CHANNEL_REAL_FREE); - } - //caution : channel is already locked here.... - p_transfer->channel_number = i; - //bind to the controller. - //p_transfer->dma_controller = p_dma; - p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN; - } - else - return -RT_ENOMEM; + if(i < p_dma->dwc.channel_max_number){ + ret_status = check_channel_real_free(p_dma,i); + if(ret_status!= CHANNEL_REAL_FREE){ + FH_DMA_DEBUG("auto request channel error\n"); + RT_ASSERT(ret_status == CHANNEL_REAL_FREE); + } + //caution : channel is already locked here.... + p_transfer->channel_number = i; + //bind to the controller. + //p_transfer->dma_controller = p_dma; + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN; + } + else + return -RT_ENOMEM; - } + } - // request channel by user - else{ - // + // request channel by user + else{ + // - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50); - if(ret_status != RT_EOK) - return -RT_ENOMEM; - //rt_enter_critical(); - ret_status = check_channel_real_free(p_dma,p_transfer->channel_number); - if(ret_status!= CHANNEL_REAL_FREE){ - FH_DMA_DEBUG("user request channel error\n"); - RT_ASSERT(ret_status == CHANNEL_REAL_FREE); - } + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50); + if(ret_status != RT_EOK) + return -RT_ENOMEM; + //rt_enter_critical(); + ret_status = check_channel_real_free(p_dma,p_transfer->channel_number); + if(ret_status!= CHANNEL_REAL_FREE){ + FH_DMA_DEBUG("user request channel error\n"); + RT_ASSERT(ret_status == CHANNEL_REAL_FREE); + } - //bind to the controller - //p_transfer->dma_controller = p_dma; - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN; - //rt_exit_critical(); - } + //bind to the controller + //p_transfer->dma_controller = p_dma; + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN; + //rt_exit_critical(); + } - //malloc desc for this one channel... - //fix me.... + //malloc desc for this one channel... + //fix me.... - p_dma->dma_channel[p_transfer->channel_number].allign_malloc = (rt_uint32_t) rt_malloc( - (p_dma->dma_channel[p_transfer->channel_number].desc_total_no - * sizeof(struct dw_lli)) + CACHE_LINE_SIZE); + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = (rt_uint32_t) rt_malloc( + (p_dma->dma_channel[p_transfer->channel_number].desc_total_no + * sizeof(struct dw_lli)) + CACHE_LINE_SIZE); - if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){ - //release channel - rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number); - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; - rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); - return -RT_ENOMEM; - } + if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){ + //release channel + rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number); + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; + rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); + return -RT_ENOMEM; + } - p_dma->dma_channel[p_transfer->channel_number].base_lli = - (struct dw_lli *) allign_func( - p_dma->dma_channel[p_transfer->channel_number].allign_malloc, - CACHE_LINE_SIZE); + p_dma->dma_channel[p_transfer->channel_number].base_lli = + (struct dw_lli *) allign_func( + p_dma->dma_channel[p_transfer->channel_number].allign_malloc, + CACHE_LINE_SIZE); - FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli); - //t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE); + FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli); + //t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE); - if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){ - FH_DMA_DEBUG("request desc failed..\n"); - RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL); - } + if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){ + FH_DMA_DEBUG("request desc failed..\n"); + RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL); + } - if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){ - rt_kprintf("malloc is not cache allign.."); + if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){ + rt_kprintf("malloc is not cache allign.."); - } + } - //rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); - rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli, - 0, - p_dma->dma_channel[p_transfer->channel_number].desc_total_no - * sizeof(struct dw_lli)); + //rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); + rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli, + 0, + p_dma->dma_channel[p_transfer->channel_number].desc_total_no + * sizeof(struct dw_lli)); - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].free_index = 0; - p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; - return RT_EOK; + return RT_EOK; } @@ -747,40 +747,40 @@ static rt_err_t handle_request_channel(struct fh81_dma *p_dma,struct dma_transf static rt_uint32_t handle_release_channel(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_uint32_t ret_status; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_uint32_t ret_status; - //rt_enter_critical(); - ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + //rt_enter_critical(); + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - if(ret_status == CHANNEL_STATUS_CLOSED){ - FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n"); - RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); - } + if(ret_status == CHANNEL_STATUS_CLOSED){ + FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n"); + RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } - channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number)); - rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); - //p_transfer->dma_controller = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; - p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER; - //rt_exit_critical(); + channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number)); + rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); + //p_transfer->dma_controller = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; + p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER; + //rt_exit_critical(); - //release this channel malloc mem... - //fix me..... - rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc); - p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].free_index = 0; - p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + //release this channel malloc mem... + //fix me..... + rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc); + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; - return RT_EOK; + return RT_EOK; } @@ -788,26 +788,26 @@ static rt_uint32_t handle_release_channel(struct fh81_dma *p_dma,struct dma_tra static rt_uint32_t cal_lli_size(struct dma_transfer *p_transfer){ - RT_ASSERT(p_transfer != RT_NULL); - RT_ASSERT(p_transfer->dma_controller != RT_NULL); - RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT); - rt_uint32_t lli_number = 0; - rt_uint32_t channel_max_trans_per_lli = 0; - channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; + RT_ASSERT(p_transfer != RT_NULL); + RT_ASSERT(p_transfer->dma_controller != RT_NULL); + RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT); + rt_uint32_t lli_number = 0; + rt_uint32_t channel_max_trans_per_lli = 0; + channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; - lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0; - lli_number += p_transfer->trans_len / channel_max_trans_per_lli; + lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0; + lli_number += p_transfer->trans_len / channel_max_trans_per_lli; - return lli_number; + return lli_number; } static void dump_lli(struct dw_lli *p_lli){ - FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n", - (rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp, - p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat); + FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n", + (rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp, + p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat); } /***************************************************************************** * Description: @@ -820,296 +820,296 @@ static void dump_lli(struct dw_lli *p_lli){ static void handle_single_transfer(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - volatile rt_uint32_t ret_status; - rt_list_t *p_controller_list; - rt_uint32_t lli_size,max_trans_size; - struct dw_lli *p_lli = RT_NULL; - struct dma_transfer *dma_trans_desc; - struct dma_transfer *_dma_trans_desc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + volatile rt_uint32_t ret_status; + rt_list_t *p_controller_list; + rt_uint32_t lli_size,max_trans_size; + struct dw_lli *p_lli = RT_NULL; + struct dma_transfer *dma_trans_desc; + struct dma_transfer *_dma_trans_desc; - rt_uint32_t temp_src_add; - rt_uint32_t temp_dst_add; - rt_uint32_t trans_total_len = 0; - rt_uint32_t temp_trans_size = 0; - //rt_uint32_t dma_channl_no = 0; + rt_uint32_t temp_src_add; + rt_uint32_t temp_dst_add; + rt_uint32_t trans_total_len = 0; + rt_uint32_t temp_trans_size = 0; + //rt_uint32_t dma_channl_no = 0; - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER); - RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma); - //when the dma transfer....the lock should be 0!!!! - //or user may not request the channel... - RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0); + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER); + RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma); + //when the dma transfer....the lock should be 0!!!! + //or user may not request the channel... + RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0); - ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; - if(ret_status == CHANNEL_STATUS_CLOSED){ - FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n"); - RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); - } - p_transfer->dma_controller = p_dma; + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + if(ret_status == CHANNEL_STATUS_CLOSED){ + FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n"); + RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } + p_transfer->dma_controller = p_dma; - rt_list_init(&p_transfer->transfer_list); - max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; - //add transfer to the controller's queue list - //here should insert before and handle after....this could be a fifo... - rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list); + rt_list_init(&p_transfer->transfer_list); + max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; + //add transfer to the controller's queue list + //here should insert before and handle after....this could be a fifo... + rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list); - p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue; + p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue; - //here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~ - //but now,this is a easy version...,just handle the transfer now!!! - list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) { + //here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~ + //but now,this is a easy version...,just handle the transfer now!!! + list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) { - //the dma controller could see the active transfer ..... - p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; + //the dma controller could see the active transfer ..... + p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; - trans_total_len = p_transfer->trans_len; + trans_total_len = p_transfer->trans_len; - //handle desc - //step1:cal lli size... - lli_size = cal_lli_size(dma_trans_desc); - //step2:malloc lli_size mem - //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli)); + //handle desc + //step1:cal lli size... + lli_size = cal_lli_size(dma_trans_desc); + //step2:malloc lli_size mem + //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli)); - dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size); + dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size); - //not enough mem.. - if(dma_trans_desc->first_lli == RT_NULL){ + //not enough mem.. + if(dma_trans_desc->first_lli == RT_NULL){ - FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); - RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); - } + FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); + RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); + } - //bug here.... - rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); + //bug here.... + rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); - p_lli = dma_trans_desc->first_lli; + p_lli = dma_trans_desc->first_lli; - //warnning!!!!must check if the add is 32bits ally... - RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0); + //warnning!!!!must check if the add is 32bits ally... + RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0); - RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); - RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); - //step3: set the mem.. - for(i=0;i<lli_size;i++){ - //parse trans para... - //para add: + RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); + RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); + //step3: set the mem.. + for(i=0;i<lli_size;i++){ + //parse trans para... + //para add: - switch(dma_trans_desc->dst_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<<dma_trans_desc->dst_width); - break; - case DW_DMA_SLAVE_DEC: - temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<<dma_trans_desc->dst_width); - break; - case DW_DMA_SLAVE_FIX: - temp_dst_add = dma_trans_desc->dst_add; - break; + switch(dma_trans_desc->dst_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<<dma_trans_desc->dst_width); + break; + case DW_DMA_SLAVE_DEC: + temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<<dma_trans_desc->dst_width); + break; + case DW_DMA_SLAVE_FIX: + temp_dst_add = dma_trans_desc->dst_add; + break; - } + } - switch(dma_trans_desc->src_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<<dma_trans_desc->src_width); - break; - case DW_DMA_SLAVE_DEC: - temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<<dma_trans_desc->src_width); - break; - case DW_DMA_SLAVE_FIX: - temp_src_add = dma_trans_desc->src_add ; - break; + switch(dma_trans_desc->src_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<<dma_trans_desc->src_width); + break; + case DW_DMA_SLAVE_DEC: + temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<<dma_trans_desc->src_width); + break; + case DW_DMA_SLAVE_FIX: + temp_src_add = dma_trans_desc->src_add ; + break; - } + } - p_lli[i].sar = temp_src_add; - p_lli[i].dar = temp_dst_add; + p_lli[i].sar = temp_src_add; + p_lli[i].dar = temp_dst_add; - //para ctl - temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size); - trans_total_len -= temp_trans_size; + //para ctl + temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size); + trans_total_len -= temp_trans_size; - RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); + RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); - p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) - |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) - |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) - |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); - //block size - p_lli[i].ctlhi = temp_trans_size; + p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) + |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) + |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) + |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); + //block size + p_lli[i].ctlhi = temp_trans_size; - if(trans_total_len > 0){ - p_lli[i].llp = (rt_uint32_t)&p_lli[i+1]; - p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - } + if(trans_total_len > 0){ + p_lli[i].llp = (rt_uint32_t)&p_lli[i+1]; + p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + } - //flush cache to mem - mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli)); + //flush cache to mem + mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli)); - dump_lli(&p_lli[i]); - } + dump_lli(&p_lli[i]); + } - //clear the isr status + //clear the isr status - //set the dma config reg - //clear cfg reload reg - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - //ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); + //set the dma config reg + //clear cfg reload reg + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + //ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); - //set the first link add - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP); - ret_status = 0; - ret_status = (rt_uint32_t)&p_lli[0]; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status); + //set the first link add + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP); + ret_status = 0; + ret_status = (rt_uint32_t)&p_lli[0]; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status); - //set link enable - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO); - ret_status = 0; - ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status); + //set link enable + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO); + ret_status = 0; + ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0); - //set handshaking + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0); + //set handshaking - RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); - RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); - if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status |= DWC_CFGL_HS_DST; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } - else{ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status &= ~DWC_CFGL_HS_DST; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } + if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status |= DWC_CFGL_HS_DST; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } + else{ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status &= ~DWC_CFGL_HS_DST; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } - if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status |= DWC_CFGL_HS_SRC; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } - else{ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status &= ~DWC_CFGL_HS_SRC; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } + if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status |= DWC_CFGL_HS_SRC; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } + else{ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status &= ~DWC_CFGL_HS_SRC; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } - //only hw handshaking need this.. - switch(dma_trans_desc->fc_mode){ - case DMA_M2M: - break; - case DMA_M2P: - //set dst per... - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + //only hw handshaking need this.. + switch(dma_trans_desc->fc_mode){ + case DMA_M2M: + break; + case DMA_M2P: + //set dst per... + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 43 ~ 46 bit - ret_status &= ~0x7800; + //clear 43 ~ 46 bit + ret_status &= ~0x7800; - ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - //DWC_CFGH_SRC_PER + ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + //DWC_CFGH_SRC_PER - break; - case DMA_P2M: - //set src per... - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2M: + //set src per... + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 39 ~ 42 bit - ret_status &= ~0x780; + //clear 39 ~ 42 bit + ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - case DMA_P2P: - //set src and dst.. - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2P: + //set src and dst.. + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - ret_status &= ~0x7800; - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x7800; + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - default: - break; - } + break; + default: + break; + } - dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; - //enable isr... - channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number)); - channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number)); - //close - channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number)); + dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; + //enable isr... + channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number)); + channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number)); + //close + channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number)); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc, MASK.BLOCK); - FH_DMA_DEBUG("mask block value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc, MASK.BLOCK); + FH_DMA_DEBUG("mask block value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc, MASK.XFER); - FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc, MASK.XFER); + FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status); - if(dma_trans_desc->prepare_callback){ - dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); - } - //enable the channle to transfer - channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number)); + if(dma_trans_desc->prepare_callback){ + dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); + } + //enable the channle to transfer + channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number)); - } + } } @@ -1124,85 +1124,85 @@ static void handle_single_transfer(struct fh81_dma *p_dma,struct dma_transfer * static rt_err_t control (struct rt_dma_device *dma, int cmd, void *arg){ - struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; - rt_uint32_t i; - struct dw_dma *dwc; - dwc = &my_own->dwc; + struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; + rt_uint32_t i; + struct dw_dma *dwc; + dwc = &my_own->dwc; - rt_err_t ret = RT_EOK; + rt_err_t ret = RT_EOK; - struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg; + struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg; - //FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer); + //FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer); - RT_ASSERT(my_own != RT_NULL); - RT_ASSERT(dwc != RT_NULL); + RT_ASSERT(my_own != RT_NULL); + RT_ASSERT(dwc != RT_NULL); - switch(cmd){ - case RT_DEVICE_CTRL_DMA_OPEN: + switch(cmd){ + case RT_DEVICE_CTRL_DMA_OPEN: - //open the controller.. - handle_dma_open(my_own); - break; - case RT_DEVICE_CTRL_DMA_CLOSE: + //open the controller.. + handle_dma_open(my_own); + break; + case RT_DEVICE_CTRL_DMA_CLOSE: - //close the controller.. - handle_dma_close(my_own); - break; - case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL: - //request a channel for the user - RT_ASSERT(p_dma_transfer != RT_NULL); - ret = handle_request_channel(my_own,p_dma_transfer); + //close the controller.. + handle_dma_close(my_own); + break; + case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL: + //request a channel for the user + RT_ASSERT(p_dma_transfer != RT_NULL); + ret = handle_request_channel(my_own,p_dma_transfer); - break; - case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL: - //release a channel - RT_ASSERT(p_dma_transfer != RT_NULL); + break; + case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL: + //release a channel + RT_ASSERT(p_dma_transfer != RT_NULL); - ret = handle_release_channel(my_own,p_dma_transfer); + ret = handle_release_channel(my_own,p_dma_transfer); - break; + break; - case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER: - //make a channel to transfer data. - RT_ASSERT(p_dma_transfer != RT_NULL); - //check if the dma channel is open,or return error. + case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER: + //make a channel to transfer data. + RT_ASSERT(p_dma_transfer != RT_NULL); + //check if the dma channel is open,or return error. - my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER; - handle_single_transfer(my_own,p_dma_transfer); - //then wait for the channel is complete.. - //caution that::we should be in the "rt_enter_critical()"when set the dma to work. - break; + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER; + handle_single_transfer(my_own,p_dma_transfer); + //then wait for the channel is complete.. + //caution that::we should be in the "rt_enter_critical()"when set the dma to work. + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE: - RT_ASSERT(p_dma_transfer != RT_NULL); - my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER; - rt_fh_dma_cyclic_prep(my_own,p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE: + RT_ASSERT(p_dma_transfer != RT_NULL); + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER; + rt_fh_dma_cyclic_prep(my_own,p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_START: - rt_fh_dma_cyclic_start(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_START: + rt_fh_dma_cyclic_start(p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_STOP: - rt_fh_dma_cyclic_stop(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_STOP: + rt_fh_dma_cyclic_stop(p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_FREE: - rt_fh_dma_cyclic_free(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_FREE: + rt_fh_dma_cyclic_free(p_dma_transfer); + break; - default: - break; + default: + break; - } + } - return ret; + return ret; } @@ -1213,55 +1213,55 @@ static void rt_fh81_dma_isr(int irq, void *param) { - RT_ASSERT(irq == DMAC_IRQn); - rt_uint32_t isr_channel_x,i,error,isr_channel_b; - struct fh81_dma *my_own = (struct fh81_dma *)param; - struct dw_dma *dwc; - struct dma_transfer *p_transfer; - dwc = &my_own->dwc; - //p_transfer = - //rt_kprintf("dma isr get in~~~\n"); - error = dw_readl(dwc,STATUS.ERROR); - if(error != 0){ - FH_DMA_DEBUG("dma isr error!!!!\n"); - RT_ASSERT(error == RT_NULL); - } + RT_ASSERT(irq == DMAC_IRQn); + rt_uint32_t isr_channel_x,i,error,isr_channel_b; + struct fh81_dma *my_own = (struct fh81_dma *)param; + struct dw_dma *dwc; + struct dma_transfer *p_transfer; + dwc = &my_own->dwc; + //p_transfer = + //rt_kprintf("dma isr get in~~~\n"); + error = dw_readl(dwc,STATUS.ERROR); + if(error != 0){ + FH_DMA_DEBUG("dma isr error!!!!\n"); + RT_ASSERT(error == RT_NULL); + } - isr_channel_x = dw_readl(dwc,STATUS.XFER); - isr_channel_b = dw_readl(dwc,STATUS.BLOCK); - //for single check the transfer status - //check which channel... + isr_channel_x = dw_readl(dwc,STATUS.XFER); + isr_channel_b = dw_readl(dwc,STATUS.BLOCK); + //for single check the transfer status + //check which channel... - for(i=0;i<my_own->dwc.channel_max_number;i++){ + for(i=0;i<my_own->dwc.channel_max_number;i++){ - if(my_own->dma_channel[i].open_flag == SINGLE_TRANSFER){ - if(isr_channel_x & 1<<i){ - dw_writel(dwc, CLEAR.XFER, 1<<i); + if(my_own->dma_channel[i].open_flag == SINGLE_TRANSFER){ + if(isr_channel_x & 1<<i){ + dw_writel(dwc, CLEAR.XFER, 1<<i); - p_transfer = my_own->dma_channel[i].active_trans; + p_transfer = my_own->dma_channel[i].active_trans; - if(p_transfer->complete_callback){ - p_transfer->complete_callback(p_transfer->complete_para); - } - p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE; - //here is a bug...do not free here - //rt_free(p_transfer->first_lli); - put_desc(my_own,p_transfer); - rt_list_remove(&p_transfer->transfer_list); - } + if(p_transfer->complete_callback){ + p_transfer->complete_callback(p_transfer->complete_para); + } + p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE; + //here is a bug...do not free here + //rt_free(p_transfer->first_lli); + put_desc(my_own,p_transfer); + rt_list_remove(&p_transfer->transfer_list); + } - } + } - else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){ - if(isr_channel_b & 1<<i){ - p_transfer = my_own->dma_channel[i].active_trans; - dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number)); - if(p_transfer->complete_callback){ - p_transfer->complete_callback(p_transfer->complete_para); - } - } - } - } + else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){ + if(isr_channel_b & 1<<i){ + p_transfer = my_own->dma_channel[i].active_trans; + dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number)); + if(p_transfer->complete_callback){ + p_transfer->complete_callback(p_transfer->complete_para); + } + } + } + } } @@ -1278,55 +1278,55 @@ static void rt_fh81_dma_isr(int irq, void *param) *****************************************************************************/ const char *channel_lock_name[FH81_MAX_CHANNEL] = { - "channel_0_lock", - "channel_1_lock", - "channel_2_lock", - "channel_3_lock", + "channel_0_lock", + "channel_1_lock", + "channel_2_lock", + "channel_3_lock", }; rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, char * dma_name){ - rt_uint32_t i; + rt_uint32_t i; - RT_ASSERT(fh81_dma_p != RT_NULL); - RT_ASSERT(dma_name != RT_NULL); - //RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY); + RT_ASSERT(fh81_dma_p != RT_NULL); + RT_ASSERT(dma_name != RT_NULL); + //RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY); - if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY) - return 0; + if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY) + return 0; - struct rt_dma_device *rt_dma; - rt_dma = &fh81_dma_p->parent; - rt_dma->ops = &fh81_dma_ops; + struct rt_dma_device *rt_dma; + rt_dma = &fh81_dma_p->parent; + rt_dma->ops = &fh81_dma_ops; - //soc para set - fh81_dma_p->dwc.name = dma_name; - fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE; - fh81_dma_p->dwc.paddr = DMA_REG_BASE; - fh81_dma_p->dwc.irq = DMAC_IRQn; - fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL; - fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED; - fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY; - fh81_dma_p->dwc.id = 0; - //channel set - for(i=0;i<FH81_MAX_CHANNEL;i++){ - fh81_dma_p->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; - fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE; - //rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion)); - rt_list_init(&(fh81_dma_p->dma_channel[i].queue)); - fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE; - rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO); - } + //soc para set + fh81_dma_p->dwc.name = dma_name; + fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE; + fh81_dma_p->dwc.paddr = DMA_REG_BASE; + fh81_dma_p->dwc.irq = DMAC_IRQn; + fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL; + fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY; + fh81_dma_p->dwc.id = 0; + //channel set + for(i=0;i<FH81_MAX_CHANNEL;i++){ + fh81_dma_p->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE; + //rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion)); + rt_list_init(&(fh81_dma_p->dma_channel[i].queue)); + fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE; + rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO); + } - //isr - rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr, - (void *)fh81_dma_p, "dma_isr"); - rt_hw_interrupt_umask(fh81_dma_p->dwc.irq); + //isr + rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr, + (void *)fh81_dma_p, "dma_isr"); + rt_hw_interrupt_umask(fh81_dma_p->dwc.irq); - return rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p); + return rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p); } @@ -1334,10 +1334,10 @@ rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); } @@ -1345,45 +1345,45 @@ static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){ static void rt_fh_dma_cyclic_start(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - p_lli = p->first_lli; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + p_lli = p->first_lli; - //32bit ally - RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); + //32bit ally + RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); - dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); - //enable isr - channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number)); - //disable isr - channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number)); + //enable isr + channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number)); + //disable isr + channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number)); - ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO); - ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); - dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status); + ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO); + ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); + dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status); - //set the first link add - ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP); - ret_status = (uint32_t)&p_lli[0]; - dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status); + //set the first link add + ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP); + ret_status = (uint32_t)&p_lli[0]; + dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status); - //set link enable - //ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO); - ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status); + //set link enable + //ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO); + ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status); - //clear ctl_hi - dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0); + //clear ctl_hi + dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0); - //enable channle - channel_set_bit(dwc, CH_EN, 1<<(p->channel_number)); + //enable channle + channel_set_bit(dwc, CH_EN, 1<<(p->channel_number)); } @@ -1391,228 +1391,228 @@ static void rt_fh_dma_cyclic_start(struct dma_transfer *p){ static void rt_fh_dma_cyclic_prep(struct fh81_dma * fh81_dma_p,struct dma_transfer *p) { - //bind the controller to the transfer - p->dma_controller = fh81_dma_p; - //bind active transfer - fh81_dma_p->dma_channel[p->channel_number].active_trans = p; - //p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - uint32_t periods,i; - uint32_t temp_src_add; - uint32_t temp_dst_add; - uint32_t buf_len = p->trans_len; - uint32_t period_len = p->period_len; + //bind the controller to the transfer + p->dma_controller = fh81_dma_p; + //bind active transfer + fh81_dma_p->dma_channel[p->channel_number].active_trans = p; + //p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + uint32_t periods,i; + uint32_t temp_src_add; + uint32_t temp_dst_add; + uint32_t buf_len = p->trans_len; + uint32_t period_len = p->period_len; - struct dma_transfer * dma_trans_desc = p; - //check first... - RT_ASSERT(buf_len % period_len == 0); + struct dma_transfer * dma_trans_desc = p; + //check first... + RT_ASSERT(buf_len % period_len == 0); - //cal the periods... - periods = buf_len / period_len; + //cal the periods... + periods = buf_len / period_len; - //get desc.... - //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli)); - dma_trans_desc->first_lli = get_desc(fh81_dma_p,dma_trans_desc,periods); + //get desc.... + //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli)); + dma_trans_desc->first_lli = get_desc(fh81_dma_p,dma_trans_desc,periods); - if(dma_trans_desc->first_lli == RT_NULL){ + if(dma_trans_desc->first_lli == RT_NULL){ - FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); - RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); - } + FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); + RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); + } - rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli)); - p_lli = dma_trans_desc->first_lli; + rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli)); + p_lli = dma_trans_desc->first_lli; - RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); + RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); - RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); - RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); - //step3: set the mem.. - for(i=0;i<periods;i++){ - //parse trans para... - //para add: - switch(dma_trans_desc->dst_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<<dma_trans_desc->dst_width); - break; - case DW_DMA_SLAVE_DEC: - temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<<dma_trans_desc->dst_width); - break; - case DW_DMA_SLAVE_FIX: - temp_dst_add = dma_trans_desc->dst_add; - break; + RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); + RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); + //step3: set the mem.. + for(i=0;i<periods;i++){ + //parse trans para... + //para add: + switch(dma_trans_desc->dst_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<<dma_trans_desc->dst_width); + break; + case DW_DMA_SLAVE_DEC: + temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<<dma_trans_desc->dst_width); + break; + case DW_DMA_SLAVE_FIX: + temp_dst_add = dma_trans_desc->dst_add; + break; - } + } - switch(dma_trans_desc->src_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_src_add = dma_trans_desc->src_add + i * period_len * (1<<dma_trans_desc->src_width); - break; - case DW_DMA_SLAVE_DEC: - temp_src_add = dma_trans_desc->src_add - i * period_len * (1<<dma_trans_desc->src_width); - break; - case DW_DMA_SLAVE_FIX: - temp_src_add = dma_trans_desc->src_add ; - break; + switch(dma_trans_desc->src_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_src_add = dma_trans_desc->src_add + i * period_len * (1<<dma_trans_desc->src_width); + break; + case DW_DMA_SLAVE_DEC: + temp_src_add = dma_trans_desc->src_add - i * period_len * (1<<dma_trans_desc->src_width); + break; + case DW_DMA_SLAVE_FIX: + temp_src_add = dma_trans_desc->src_add ; + break; - } + } - p_lli[i].sar = temp_src_add; - p_lli[i].dar = temp_dst_add; + p_lli[i].sar = temp_src_add; + p_lli[i].dar = temp_dst_add; - //para ctl + //para ctl - RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); + RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); - p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) - |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) - |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) - |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); - //block size - p_lli[i].ctlhi = period_len; + p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) + |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) + |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) + |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); + //block size + p_lli[i].ctlhi = period_len; - p_lli[i].llp = (uint32_t)&p_lli[i+1]; - p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + p_lli[i].llp = (uint32_t)&p_lli[i+1]; + p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - //flush cache to mem - mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli)); + //flush cache to mem + mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli)); - dump_lli(&p_lli[i]); - } - //make a ring here - p_lli[periods -1 ].llp = (uint32_t)&p_lli[0]; + dump_lli(&p_lli[i]); + } + //make a ring here + p_lli[periods -1 ].llp = (uint32_t)&p_lli[0]; - mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli)); + mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli)); - //parse the handshake - RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); - RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); + //parse the handshake + RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); - //dst handshake - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); - ret_status = 0; - if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ - ret_status |= DWC_CFGL_HS_DST; - } - else{ - ret_status &= ~DWC_CFGL_HS_DST; - } - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + //dst handshake + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); + ret_status = 0; + if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ + ret_status |= DWC_CFGL_HS_DST; + } + else{ + ret_status &= ~DWC_CFGL_HS_DST; + } + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - //src handshake - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ - ret_status |= DWC_CFGL_HS_SRC; - } - else{ - ret_status &= ~DWC_CFGL_HS_SRC; - } - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + //src handshake + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ + ret_status |= DWC_CFGL_HS_SRC; + } + else{ + ret_status &= ~DWC_CFGL_HS_SRC; + } + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - //only hw handshaking need this.. - switch(dma_trans_desc->fc_mode){ - case DMA_M2M: - break; - case DMA_M2P: - //set dst per... - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 43 ~ 46 bit - ret_status &= ~0x7800; - ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - //DWC_CFGH_SRC_PER + //only hw handshaking need this.. + switch(dma_trans_desc->fc_mode){ + case DMA_M2M: + break; + case DMA_M2P: + //set dst per... + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + //clear 43 ~ 46 bit + ret_status &= ~0x7800; + ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + //DWC_CFGH_SRC_PER - break; - case DMA_P2M: - //set src per... - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 39 ~ 42 bit - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + break; + case DMA_P2M: + //set src per... + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + //clear 39 ~ 42 bit + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - case DMA_P2P: - //set src and dst.. - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2P: + //set src and dst.. + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - ret_status &= ~0x7800; - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x7800; + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - default: - break; - } + break; + default: + break; + } - dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; + dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; - if(dma_trans_desc->prepare_callback){ - dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); - } + if(dma_trans_desc->prepare_callback){ + dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); + } } static void rt_fh_dma_cyclic_free(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - p_lli = p->first_lli; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + p_lli = p->first_lli; - //close channel first.. - channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); + //close channel first.. + channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); - //check if close really - while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number)); + //check if close really + while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); - //rt_free(p->first_lli); - put_desc(my_own,p); + //rt_free(p->first_lli); + put_desc(my_own,p); } void rt_fh_dma_init(void){ - fh81_dma_register(&fh81_dma_controller[0],"fh81_dma"); + fh81_dma_register(&fh81_dma_controller[0],"fh81_dma"); } diff --git a/bsp/fh8620/drivers/fh_dma.h b/bsp/fh8620/drivers/fh_dma.h index faceac2deb..477718d0a5 100644 --- a/bsp/fh8620/drivers/fh_dma.h +++ b/bsp/fh8620/drivers/fh_dma.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,19 +18,19 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_DMA_H_ #define FH_DMA_H_ /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ #include <rtthread.h> @@ -43,24 +43,24 @@ *********************************/ -#define FH81_MAX_CHANNEL (4) -#define FH81_CHANNEL_MAX_TRANSFER_SIZE (4095) +#define FH81_MAX_CHANNEL (4) +#define FH81_CHANNEL_MAX_TRANSFER_SIZE (4095) enum DMA_HW_HS_MAP{ - ACODEC_RX = 0, - ACODEC_TX, - SPI0_RX, - SPI0_TX, - SPI1_RX, - SPI1_TX, - UART0_RX, - UART0_TX, - UART1_RX, - UART1_TX, - DMA_HW_HS_END, + ACODEC_RX = 0, + ACODEC_TX, + SPI0_RX, + SPI0_TX, + SPI1_RX, + SPI1_TX, + UART0_RX, + UART0_TX, + UART1_RX, + UART1_TX, + DMA_HW_HS_END, }; /********************************* @@ -76,7 +76,7 @@ typedef void (*user_prepare)(void *prepare_para); -/**************************** i'm cut-off line ************************************/ +/**************************** i'm cut-off line ************************************/ @@ -88,128 +88,128 @@ struct fh81_dma; struct dw_lli { - /* values that are not changed by hardware */ - rt_uint32_t sar; - rt_uint32_t dar; - rt_uint32_t llp; /* chain to next lli */ - rt_uint32_t ctllo; - /* values that may get written back: */ - rt_uint32_t ctlhi; - /* sstat and dstat can snapshot peripheral register state. - * silicon config may discard either or both... - */ - rt_uint32_t sstat; - rt_uint32_t dstat; - rt_uint32_t reserve; + /* values that are not changed by hardware */ + rt_uint32_t sar; + rt_uint32_t dar; + rt_uint32_t llp; /* chain to next lli */ + rt_uint32_t ctllo; + /* values that may get written back: */ + rt_uint32_t ctlhi; + /* sstat and dstat can snapshot peripheral register state. + * silicon config may discard either or both... + */ + rt_uint32_t sstat; + rt_uint32_t dstat; + rt_uint32_t reserve; }; //transfer use below struct dma_transfer{ - //this is private for the dma drive....app don't touch it,the driver will manger it - //link interface for more transfer to the controller... - rt_list_t transfer_list; - struct fh81_dma *dma_controller; - //this the mem add....the dma controller will load the setting to move data .... - //user don't touch it - struct dw_lli *first_lli; - rt_uint32_t lli_size; - //new add for allign get desc... - rt_uint32_t actual_lli_size; + //this is private for the dma drive....app don't touch it,the driver will manger it + //link interface for more transfer to the controller... + rt_list_t transfer_list; + struct fh81_dma *dma_controller; + //this the mem add....the dma controller will load the setting to move data .... + //user don't touch it + struct dw_lli *first_lli; + rt_uint32_t lli_size; + //new add for allign get desc... + rt_uint32_t actual_lli_size; - //user could set paras below~~~ -#define AUTO_FIND_CHANNEL (0xff) - //transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel. - rt_uint32_t channel_number; - //which dma you want to use...for fh81....only 0!!! - rt_uint32_t dma_number; + //user could set paras below~~~ +#define AUTO_FIND_CHANNEL (0xff) + //transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel. + rt_uint32_t channel_number; + //which dma you want to use...for fh81....only 0!!! + rt_uint32_t dma_number; - //user should set the para below -#define DMA_M2M (0) // MEM <=> MEM -#define DMA_M2P (1) // MEM => peripheral A -#define DMA_P2M (2) // MEM <= peripheral A -#define DMA_P2P (3) // peripheral A <=> peripheral B - rt_uint32_t fc_mode;//ip->mem. mem->mem. mem->ip + //user should set the para below +#define DMA_M2M (0) // MEM <=> MEM +#define DMA_M2P (1) // MEM => peripheral A +#define DMA_P2M (2) // MEM <= peripheral A +#define DMA_P2P (3) // peripheral A <=> peripheral B + rt_uint32_t fc_mode;//ip->mem. mem->mem. mem->ip -#define DMA_HW_HANDSHAKING (0) -#define DMA_SW_HANDSHAKING (1) - rt_uint32_t src_hs; //src - //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined - rt_uint32_t src_per; //src hw handshake number - //rt_uint32_t irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr) +#define DMA_HW_HANDSHAKING (0) +#define DMA_SW_HANDSHAKING (1) + rt_uint32_t src_hs; //src + //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined + rt_uint32_t src_per; //src hw handshake number + //rt_uint32_t irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr) -#define DW_DMA_SLAVE_WIDTH_8BIT (0) -#define DW_DMA_SLAVE_WIDTH_16BIT (1) -#define DW_DMA_SLAVE_WIDTH_32BIT (2) - rt_uint32_t src_width; +#define DW_DMA_SLAVE_WIDTH_8BIT (0) +#define DW_DMA_SLAVE_WIDTH_16BIT (1) +#define DW_DMA_SLAVE_WIDTH_32BIT (2) + rt_uint32_t src_width; - //the user should reference the hw handshaking watermark.. -#define DW_DMA_SLAVE_MSIZE_1 (0) -#define DW_DMA_SLAVE_MSIZE_4 (1) -#define DW_DMA_SLAVE_MSIZE_8 (2) -#define DW_DMA_SLAVE_MSIZE_16 (3) -#define DW_DMA_SLAVE_MSIZE_32 (4) -#define DW_DMA_SLAVE_MSIZE_64 (5) -#define DW_DMA_SLAVE_MSIZE_128 (6) -#define DW_DMA_SLAVE_MSIZE_256 (7) - rt_uint32_t src_msize; - rt_uint32_t src_add; -#define DW_DMA_SLAVE_INC (0) -#define DW_DMA_SLAVE_DEC (1) -#define DW_DMA_SLAVE_FIX (2) - rt_uint32_t src_inc_mode; //increase mode: increase or not change + //the user should reference the hw handshaking watermark.. +#define DW_DMA_SLAVE_MSIZE_1 (0) +#define DW_DMA_SLAVE_MSIZE_4 (1) +#define DW_DMA_SLAVE_MSIZE_8 (2) +#define DW_DMA_SLAVE_MSIZE_16 (3) +#define DW_DMA_SLAVE_MSIZE_32 (4) +#define DW_DMA_SLAVE_MSIZE_64 (5) +#define DW_DMA_SLAVE_MSIZE_128 (6) +#define DW_DMA_SLAVE_MSIZE_256 (7) + rt_uint32_t src_msize; + rt_uint32_t src_add; +#define DW_DMA_SLAVE_INC (0) +#define DW_DMA_SLAVE_DEC (1) +#define DW_DMA_SLAVE_FIX (2) + rt_uint32_t src_inc_mode; //increase mode: increase or not change -//#define DMA_DST_HW_HANDSHAKING (0) -//#define DMA_DST_SW_HANDSHAKING (1) - rt_uint32_t dst_hs; //src - //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined - rt_uint32_t dst_per; //dst hw handshake number -//#define DW_DMA_SLAVE_WIDTH_8BIT (0) -//#define DW_DMA_SLAVE_WIDTH_16BIT (1) -//#define DW_DMA_SLAVE_WIDTH_32BIT (2) - rt_uint32_t dst_width; -//#define DW_DMA_SLAVE_MSIZE_1 (0) -//#define DW_DMA_SLAVE_MSIZE_4 (1) -//#define DW_DMA_SLAVE_MSIZE_8 (2) -//#define DW_DMA_SLAVE_MSIZE_16 (3) -//#define DW_DMA_SLAVE_MSIZE_32 (4) -//#define DW_DMA_SLAVE_MSIZE_64 (5) -//#define DW_DMA_SLAVE_MSIZE_128 (6) -//#define DW_DMA_SLAVE_MSIZE_256 (7) - rt_uint32_t dst_msize; - rt_uint32_t dst_add; -//#define DW_DMA_SLAVE_INC (0) -//#define DW_DMA_SLAVE_DEC (1) -//#define DW_DMA_SLAVE_FIX (2) - rt_uint32_t dst_inc_mode; //increase mode: increase or not change +//#define DMA_DST_HW_HANDSHAKING (0) +//#define DMA_DST_SW_HANDSHAKING (1) + rt_uint32_t dst_hs; //src + //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined + rt_uint32_t dst_per; //dst hw handshake number +//#define DW_DMA_SLAVE_WIDTH_8BIT (0) +//#define DW_DMA_SLAVE_WIDTH_16BIT (1) +//#define DW_DMA_SLAVE_WIDTH_32BIT (2) + rt_uint32_t dst_width; +//#define DW_DMA_SLAVE_MSIZE_1 (0) +//#define DW_DMA_SLAVE_MSIZE_4 (1) +//#define DW_DMA_SLAVE_MSIZE_8 (2) +//#define DW_DMA_SLAVE_MSIZE_16 (3) +//#define DW_DMA_SLAVE_MSIZE_32 (4) +//#define DW_DMA_SLAVE_MSIZE_64 (5) +//#define DW_DMA_SLAVE_MSIZE_128 (6) +//#define DW_DMA_SLAVE_MSIZE_256 (7) + rt_uint32_t dst_msize; + rt_uint32_t dst_add; +//#define DW_DMA_SLAVE_INC (0) +//#define DW_DMA_SLAVE_DEC (1) +//#define DW_DMA_SLAVE_FIX (2) + rt_uint32_t dst_inc_mode; //increase mode: increase or not change - //total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT... - //exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes.. - //exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes.. - rt_uint32_t trans_len; + //total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT... + //exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes.. + //exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes.. + rt_uint32_t trans_len; - //this is used when dma finish transfer job - dma_complete_callback complete_callback; - void *complete_para; //for the driver data use the dma driver. + //this is used when dma finish transfer job + dma_complete_callback complete_callback; + void *complete_para; //for the driver data use the dma driver. - //this is used when dma before work..the user maybe need to set his own private para.. - user_prepare prepare_callback; - void *prepare_para; + //this is used when dma before work..the user maybe need to set his own private para.. + user_prepare prepare_callback; + void *prepare_para; - //add cyclic para... - //period len.. - rt_uint32_t period_len; + //add cyclic para... + //period len.. + rt_uint32_t period_len; }; @@ -223,13 +223,13 @@ struct dma_transfer{ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ @@ -240,7 +240,7 @@ struct dma_transfer{ /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, char * dma_name); diff --git a/bsp/fh8620/drivers/gpio.c b/bsp/fh8620/drivers/gpio.c index fc3fff639e..7a0dca36df 100644 --- a/bsp/fh8620/drivers/gpio.c +++ b/bsp/fh8620/drivers/gpio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -410,10 +410,10 @@ int fh_gpio_probe(void *priv_data) int i; if(gpio_obj->id == 0){ - rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0"); + rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0"); } else if(gpio_obj->id == 1){ - rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1"); + rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1"); } diff --git a/bsp/fh8620/drivers/gpio.h b/bsp/fh8620/drivers/gpio.h index 7fe4d236b7..97b613871b 100644 --- a/bsp/fh8620/drivers/gpio.h +++ b/bsp/fh8620/drivers/gpio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef GPIO_H_ #define GPIO_H_ diff --git a/bsp/fh8620/drivers/i2c.c b/bsp/fh8620/drivers/i2c.c index 0f9636853d..66931666ea 100644 --- a/bsp/fh8620/drivers/i2c.c +++ b/bsp/fh8620/drivers/i2c.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rtdevice.h> #include <rthw.h> #include "i2c.h" @@ -50,25 +50,25 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - rt_uint32_t ic_con; + rt_uint32_t ic_con; - /* if the slave address is ten bit address, ERROR*/ + /* if the slave address is ten bit address, ERROR*/ if (msgs[i2c_drv->msg_write_idx].flags & I2C_M_TEN) { rt_kprintf("ERROR: %s, ten bit address is NOT supported\n", __func__); return; } - /* Disable the adapter */ - I2C_WaitMasterIdle(i2c_obj); + /* Disable the adapter */ + I2C_WaitMasterIdle(i2c_obj); - I2C_Enable(i2c_obj, RT_FALSE); + I2C_Enable(i2c_obj, RT_FALSE); - /* set the slave (target) address */ - I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr); + /* set the slave (target) address */ + I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr); - /* Enable interrupts */ - I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK); + /* Enable interrupts */ + I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK); /* Enable the adapter */ I2C_Enable(i2c_obj, RT_TRUE); @@ -76,30 +76,30 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev, - struct rt_i2c_msg msgs[], rt_uint32_t num) + struct rt_i2c_msg msgs[], rt_uint32_t num) { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; int ret; - struct rt_i2c_msg *pmsg = RT_NULL; + struct rt_i2c_msg *pmsg = RT_NULL; - PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__); + PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__); rt_completion_init(&i2c_drv->transfer_completion); ret = rt_mutex_take(i2c_drv->lock, RT_WAITING_FOREVER); - if (ret != RT_EOK) { - goto done; - } + if (ret != RT_EOK) { + goto done; + } - i2c_drv->msgs = msgs; - i2c_drv->msgs_num = num; - i2c_drv->msg_read_idx = 0; - i2c_drv->msg_write_idx = 0; - i2c_drv->cmd_err = 0; - i2c_drv->msg_err = 0; - i2c_drv->status = STATUS_IDLE; - i2c_obj->abort_source = 0; + i2c_drv->msgs = msgs; + i2c_drv->msgs_num = num; + i2c_drv->msg_read_idx = 0; + i2c_drv->msg_write_idx = 0; + i2c_drv->cmd_err = 0; + i2c_drv->msg_err = 0; + i2c_drv->status = STATUS_IDLE; + i2c_obj->abort_source = 0; ret = I2C_WaitDeviceIdle(i2c_obj); if (ret < 0) @@ -108,51 +108,51 @@ static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev, //goto done; } - fh_i2c_xfer_init(dev, msgs, num); + fh_i2c_xfer_init(dev, msgs, num); - ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND); - PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait"); + ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND); + PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait"); if(ret) - { + { rt_kprintf("ERROR: %s, transfer timeout\n", __func__); I2C_SetDataCmd(i2c_obj, 0x200); I2C_Init(i2c_obj); - ret = -RT_ETIMEOUT; - goto done; - } + ret = -RT_ETIMEOUT; + goto done; + } - if (i2c_drv->msg_err) - { - rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err); - ret = i2c_drv->msg_err; - goto done; - } + if (i2c_drv->msg_err) + { + rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err); + ret = i2c_drv->msg_err; + goto done; + } - /* no error */ - if (!i2c_drv->cmd_err) - { - /* Disable the adapter */ - I2C_WaitMasterIdle(i2c_obj); - I2C_Enable(i2c_obj, RT_FALSE); - ret = num; - goto done; - } + /* no error */ + if (!i2c_drv->cmd_err) + { + /* Disable the adapter */ + I2C_WaitMasterIdle(i2c_obj); + I2C_Enable(i2c_obj, RT_FALSE); + ret = num; + goto done; + } - /* We have an error */ - if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT) - { - rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__); - ret = I2C_HandleTxAbort(i2c_obj); - goto done; - } + /* We have an error */ + if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT) + { + rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__); + ret = I2C_HandleTxAbort(i2c_obj); + goto done; + } - ret = 1; + ret = 1; done: I2C_Enable(i2c_obj, RT_FALSE); rt_mutex_release(i2c_drv->lock); PRINT_I2C_DBG(">>>>>>>>>>>>>%s end\n", __func__); - return ret; + return ret; } @@ -167,164 +167,164 @@ static void i2c_fh_xfer_msg(struct rt_i2c_bus_device *dev) { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - struct rt_i2c_msg *msgs = i2c_drv->msgs; - rt_uint32_t intr_mask, cmd; - int tx_limit, rx_limit; - rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr; - rt_uint32_t buf_len = i2c_drv->tx_buf_len; - rt_uint8_t *buf = i2c_drv->tx_buf; + struct rt_i2c_msg *msgs = i2c_drv->msgs; + rt_uint32_t intr_mask, cmd; + int tx_limit, rx_limit; + rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr; + rt_uint32_t buf_len = i2c_drv->tx_buf_len; + rt_uint8_t *buf = i2c_drv->tx_buf; - PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx); + PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx); - intr_mask = DW_IC_INTR_DEFAULT_MASK; + intr_mask = DW_IC_INTR_DEFAULT_MASK; - for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++) - { - /* - * if target address has changed, we need to - * reprogram the target address in the i2c - * adapter when we are done with this transfer - */ - if (msgs[i2c_drv->msg_write_idx].addr != addr) { - rt_kprintf( - "ERROR: %s, invalid target address\n", __func__); - i2c_drv->msg_err = 1; - break; - } + for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++) + { + /* + * if target address has changed, we need to + * reprogram the target address in the i2c + * adapter when we are done with this transfer + */ + if (msgs[i2c_drv->msg_write_idx].addr != addr) { + rt_kprintf( + "ERROR: %s, invalid target address\n", __func__); + i2c_drv->msg_err = 1; + break; + } - if (msgs[i2c_drv->msg_write_idx].len == 0) { - rt_kprintf( - "ERROR: %s, invalid message length\n", __func__); - i2c_drv->msg_err = 1; - break; - } + if (msgs[i2c_drv->msg_write_idx].len == 0) { + rt_kprintf( + "ERROR: %s, invalid message length\n", __func__); + i2c_drv->msg_err = 1; + break; + } - if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS)) - { - /* new i2c_msg */ - buf = msgs[i2c_drv->msg_write_idx].buf; - buf_len = msgs[i2c_drv->msg_write_idx].len; + if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS)) + { + /* new i2c_msg */ + buf = msgs[i2c_drv->msg_write_idx].buf; + buf_len = msgs[i2c_drv->msg_write_idx].len; - PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]); - } + PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]); + } - tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj); - rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj); + tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj); + rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj); - while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) - { - if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD) - { - cmd = 0x100; - rx_limit--; - } - else - { - cmd = *buf++; - } + while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) + { + if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD) + { + cmd = 0x100; + rx_limit--; + } + else + { + cmd = *buf++; + } - tx_limit--; buf_len--; + tx_limit--; buf_len--; - if(!buf_len) - { - //2015-11-8 ar0130 bug fixed - while(I2C_GetTransmitFifoLevel(i2c_obj)); - cmd |= 0x200; - } + if(!buf_len) + { + //2015-11-8 ar0130 bug fixed + while(I2C_GetTransmitFifoLevel(i2c_obj)); + cmd |= 0x200; + } - I2C_SetDataCmd(i2c_obj, cmd); - } + I2C_SetDataCmd(i2c_obj, cmd); + } - i2c_drv->tx_buf = buf; - i2c_drv->tx_buf_len = buf_len; + i2c_drv->tx_buf = buf; + i2c_drv->tx_buf_len = buf_len; - if (buf_len > 0) - { - /* more bytes to be written */ - i2c_drv->status |= STATUS_WRITE_IN_PROGRESS; - break; - } - else - { - i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS; - } - } + if (buf_len > 0) + { + /* more bytes to be written */ + i2c_drv->status |= STATUS_WRITE_IN_PROGRESS; + break; + } + else + { + i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS; + } + } - /* - * If i2c_msg index search is completed, we don't need TX_EMPTY - * interrupt any more. - */ + /* + * If i2c_msg index search is completed, we don't need TX_EMPTY + * interrupt any more. + */ - if (i2c_drv->msg_write_idx == i2c_drv->msgs_num) - intr_mask &= ~DW_IC_INTR_TX_EMPTY; + if (i2c_drv->msg_write_idx == i2c_drv->msgs_num) + intr_mask &= ~DW_IC_INTR_TX_EMPTY; - if (i2c_drv->msg_err) - { - rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err); - intr_mask = 0; - } + if (i2c_drv->msg_err) + { + rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err); + intr_mask = 0; + } - I2C_SetInterruptMask(i2c_obj, intr_mask); + I2C_SetInterruptMask(i2c_obj, intr_mask); - PRINT_I2C_DBG("%s end\n", __func__); + PRINT_I2C_DBG("%s end\n", __func__); } static void i2c_fh_read(struct rt_i2c_bus_device *dev) { - struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; - struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - struct rt_i2c_msg *msgs = i2c_drv->msgs; - int rx_valid; + struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; + struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; + struct rt_i2c_msg *msgs = i2c_drv->msgs; + int rx_valid; - PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx); + PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx); - for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++) - { - rt_uint32_t len; - rt_uint8_t *buf; + for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++) + { + rt_uint32_t len; + rt_uint8_t *buf; - if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD)) - continue; + if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD)) + continue; - if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS)) - { - len = msgs[i2c_drv->msg_read_idx].len; - buf = msgs[i2c_drv->msg_read_idx].buf; - } - else - { - PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n"); - len = i2c_drv->rx_buf_len; - buf = i2c_drv->rx_buf; - } + if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS)) + { + len = msgs[i2c_drv->msg_read_idx].len; + buf = msgs[i2c_drv->msg_read_idx].buf; + } + else + { + PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n"); + len = i2c_drv->rx_buf_len; + buf = i2c_drv->rx_buf; + } - rx_valid = I2C_GetReceiveFifoLevel(i2c_obj); + rx_valid = I2C_GetReceiveFifoLevel(i2c_obj); - if(rx_valid == 0) - { - rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__); - } - PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid); - for (; len > 0 && rx_valid > 0; len--, rx_valid--) - { - *buf++ = I2C_GetData(i2c_obj); - } + if(rx_valid == 0) + { + rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__); + } + PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid); + for (; len > 0 && rx_valid > 0; len--, rx_valid--) + { + *buf++ = I2C_GetData(i2c_obj); + } - PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]); + PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]); - if (len > 0) - { - PRINT_I2C_DBG("len > 0\n"); - i2c_drv->status |= STATUS_READ_IN_PROGRESS; - i2c_drv->rx_buf_len = len; - i2c_drv->rx_buf = buf; - return; - } - else - i2c_drv->status &= ~STATUS_READ_IN_PROGRESS; - } + if (len > 0) + { + PRINT_I2C_DBG("len > 0\n"); + i2c_drv->status |= STATUS_READ_IN_PROGRESS; + i2c_drv->rx_buf_len = len; + i2c_drv->rx_buf = buf; + return; + } + else + i2c_drv->status &= ~STATUS_READ_IN_PROGRESS; + } - PRINT_I2C_DBG("%s end\n", __func__); + PRINT_I2C_DBG("%s end\n", __func__); } /* @@ -336,44 +336,44 @@ static void fh_i2c_interrupt(int this_irq, void *dev_id) struct i2c_driver *i2c_drv = dev_id; struct rt_i2c_bus_device *i2c_bus_dev = i2c_drv->i2c_bus_dev; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - rt_uint32_t stat; + rt_uint32_t stat; - stat = I2C_ClearAndGetInterrupts(i2c_obj); - PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj)); + stat = I2C_ClearAndGetInterrupts(i2c_obj); + PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj)); - if (stat & DW_IC_INTR_TX_ABRT) - { - PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n"); - i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT; - i2c_drv->status = STATUS_IDLE; + if (stat & DW_IC_INTR_TX_ABRT) + { + PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n"); + i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT; + i2c_drv->status = STATUS_IDLE; - /* - * Anytime TX_ABRT is set, the contents of the tx/rx - * buffers are flushed. Make sure to skip them. - */ - I2C_SetInterruptMask(i2c_obj, 0); - goto tx_aborted; - } + /* + * Anytime TX_ABRT is set, the contents of the tx/rx + * buffers are flushed. Make sure to skip them. + */ + I2C_SetInterruptMask(i2c_obj, 0); + goto tx_aborted; + } - if (stat & DW_IC_INTR_RX_FULL) - { - i2c_fh_read(i2c_bus_dev); - } + if (stat & DW_IC_INTR_RX_FULL) + { + i2c_fh_read(i2c_bus_dev); + } - if (stat & DW_IC_INTR_TX_EMPTY) - { - i2c_fh_xfer_msg(i2c_bus_dev); - } + if (stat & DW_IC_INTR_TX_EMPTY) + { + i2c_fh_xfer_msg(i2c_bus_dev); + } - /* - * No need to modify or disable the interrupt mask here. - * i2c_fh_xfer_msg() will take care of it according to - * the current transmit status. - */ + /* + * No need to modify or disable the interrupt mask here. + * i2c_fh_xfer_msg() will take care of it according to + * the current transmit status. + */ tx_aborted: - if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err) - rt_completion_done(&i2c_drv->transfer_completion); + if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err) + rt_completion_done(&i2c_drv->transfer_completion); } @@ -464,64 +464,64 @@ void rt_hw_i2c_init(void) } static rt_err_t fh_i2c_read_reg(struct rt_i2c_bus_device *fh81_i2c, - rt_uint16_t reg, rt_uint8_t *data) { - struct rt_i2c_msg msg[2]; - rt_uint8_t send_buf[2]; - rt_uint8_t recv_buf[1] = {0}; + rt_uint16_t reg, rt_uint8_t *data) { + struct rt_i2c_msg msg[2]; + rt_uint8_t send_buf[2]; + rt_uint8_t recv_buf[1] = {0}; - PRINT_I2C_DBG("%s start\n", __func__); + PRINT_I2C_DBG("%s start\n", __func__); - // send_buf[0] = ((reg >> 8) & 0xff); - send_buf[0] = (reg & 0xFF); + // send_buf[0] = ((reg >> 8) & 0xff); + send_buf[0] = (reg & 0xFF); - msg[0].addr = 0x51; - msg[0].flags = RT_I2C_WR; - msg[0].len = 1; - msg[0].buf = send_buf; + msg[0].addr = 0x51; + msg[0].flags = RT_I2C_WR; + msg[0].len = 1; + msg[0].buf = send_buf; - msg[1].addr = 0x51; - msg[1].flags = RT_I2C_RD; - msg[1].len = 1; - msg[1].buf = recv_buf; + msg[1].addr = 0x51; + msg[1].flags = RT_I2C_RD; + msg[1].len = 1; + msg[1].buf = recv_buf; - rt_i2c_transfer(fh81_i2c, msg, 2); - *data = recv_buf[0]; - return RT_EOK; + rt_i2c_transfer(fh81_i2c, msg, 2); + *data = recv_buf[0]; + return RT_EOK; } static rt_err_t fh_i2c_write_reg(struct rt_i2c_bus_device *fh81_i2c, - rt_uint16_t reg, rt_uint8_t data) { - struct rt_i2c_msg msg; - rt_uint8_t send_buf[3]; + rt_uint16_t reg, rt_uint8_t data) { + struct rt_i2c_msg msg; + rt_uint8_t send_buf[3]; - PRINT_I2C_DBG("%s start\n", __func__); + PRINT_I2C_DBG("%s start\n", __func__); - // send_buf[0] = ((reg >> 8) & 0xff); - send_buf[1] = (reg & 0xFF); - send_buf[2] = data; + // send_buf[0] = ((reg >> 8) & 0xff); + send_buf[1] = (reg & 0xFF); + send_buf[2] = data; - msg.addr = 0x51; - msg.flags = RT_I2C_WR; - msg.len = 2; - msg.buf = send_buf; + msg.addr = 0x51; + msg.flags = RT_I2C_WR; + msg.len = 2; + msg.buf = send_buf; - rt_i2c_transfer(fh81_i2c, &msg, 1); - PRINT_I2C_DBG("%s end\n", __func__); - return RT_EOK; + rt_i2c_transfer(fh81_i2c, &msg, 1); + PRINT_I2C_DBG("%s end\n", __func__); + return RT_EOK; } void i2c_test_sensor() { - struct rt_i2c_bus_device *fh81_i2c; - struct rt_i2c_msg msg[2]; - rt_uint8_t data[1] = { 0x00 }; + struct rt_i2c_bus_device *fh81_i2c; + struct rt_i2c_msg msg[2]; + rt_uint8_t data[1] = { 0x00 }; - fh81_i2c = rt_i2c_bus_device_find("i2c1"); + fh81_i2c = rt_i2c_bus_device_find("i2c1"); - fh_i2c_write_reg(fh81_i2c, 0x04, 0x02); + fh_i2c_write_reg(fh81_i2c, 0x04, 0x02); - fh_i2c_read_reg(fh81_i2c, 0x02, data); + fh_i2c_read_reg(fh81_i2c, 0x02, data); - rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]); - PRINT_I2C_DBG("%s end\n", __func__); + rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]); + PRINT_I2C_DBG("%s end\n", __func__); } #ifdef RT_USING_FINSH #include <finsh.h> diff --git a/bsp/fh8620/drivers/i2c.h b/bsp/fh8620/drivers/i2c.h index 9046bd81cb..15e4d7e8f2 100644 --- a/bsp/fh8620/drivers/i2c.h +++ b/bsp/fh8620/drivers/i2c.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/interrupt.c b/bsp/fh8620/drivers/interrupt.c index ab522fab70..4cb250d8e5 100644 --- a/bsp/fh8620/drivers/interrupt.c +++ b/bsp/fh8620/drivers/interrupt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -105,10 +105,10 @@ void rt_hw_interrupt_init(void) { rt_int32_t i; register rt_uint32_t idx; - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; - ictl_close_all_isr(p); + ictl_close_all_isr(p); /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) { @@ -137,27 +137,27 @@ void rt_hw_interrupt_init(void) void rt_hw_interrupt_mask(int irq) { - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; /* Disable irq on AIC */ - ictl_mask_isr(p,irq); + ictl_mask_isr(p,irq); -// if (irq < 32) -// p->IRQ_EN_L &= ~(1 << irq); -// else -// p->IRQ_EN_H &= ~(1 << (irq - 32)); +// if (irq < 32) +// p->IRQ_EN_L &= ~(1 << irq); +// else +// p->IRQ_EN_H &= ~(1 << (irq - 32)); } void rt_hw_interrupt_umask(int irq) { - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; /* Enable irq on AIC */ - ictl_unmask_isr(p,irq); + ictl_unmask_isr(p,irq); // if (irq < 32) -// p->IRQ_EN_L |= 1 << irq; -// else -// p->IRQ_EN_H |= 1 << (irq - 32); +// p->IRQ_EN_L |= 1 << irq; +// else +// p->IRQ_EN_H |= 1 << (irq - 32); } /** @@ -168,7 +168,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -182,7 +182,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -195,7 +195,7 @@ void list_irq(void) { #ifdef RT_USING_INTERRUPT_INFO - int irq; + int irq; rt_kprintf("number\tcount\tname\n"); for (irq = 0; irq < MAX_HANDLERS; irq++) { diff --git a/bsp/fh8620/drivers/interrupt.h b/bsp/fh8620/drivers/interrupt.h index fd4283b95c..6f62b0d95a 100644 --- a/bsp/fh8620/drivers/interrupt.h +++ b/bsp/fh8620/drivers/interrupt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -35,6 +35,6 @@ void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int irq); void rt_hw_interrupt_umask(int irq); rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); + void *param, const char *name); #endif /* INTERRUPT_H_ */ diff --git a/bsp/fh8620/drivers/mem_process.c b/bsp/fh8620/drivers/mem_process.c index 4ef7e2d599..e1424bd6ac 100644 --- a/bsp/fh8620/drivers/mem_process.c +++ b/bsp/fh8620/drivers/mem_process.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -28,52 +28,52 @@ #include <rtdevice.h> #include "mmu.h" -#define CHANGLINE_SIZE (1) +#define CHANGLINE_SIZE (1) //#define FH_DBG_MEM_PROCESS #ifdef FH_DBG_MEM_PROCESS void mem_input(rt_uint32_t t_addr, rt_uint32_t t_size, rt_uint8_t t_value) { - rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size, - t_value); + rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size, + t_value); - rt_memset((void *) t_addr, t_value, t_size); + rt_memset((void *) t_addr, t_value, t_size); - mmu_clean_invalidated_dcache(t_addr, t_size); + mmu_clean_invalidated_dcache(t_addr, t_size); } void mem_output(rt_uint32_t t_addr, rt_uint32_t t_size) { - rt_uint32_t i; - rt_uint32_t cnt = 0; - rt_uint32_t value; - rt_uint32_t addr, size; + rt_uint32_t i; + rt_uint32_t cnt = 0; + rt_uint32_t value; + rt_uint32_t addr, size; - addr = t_addr; - if (t_size % 4) { - rt_kprintf("mem must be alligned\n"); - } - size = t_size / 4; - rt_int32_t *p = (rt_uint32_t *) t_addr; + addr = t_addr; + if (t_size % 4) { + rt_kprintf("mem must be alligned\n"); + } + size = t_size / 4; + rt_int32_t *p = (rt_uint32_t *) t_addr; - //mmu_clean_invalidated_dcache(addr,t_size); - rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size); - rt_kprintf("0x%08x:", addr); - for (i = 0; i < size; i++) { - value = *p++; - if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) { - rt_kprintf("\n"); - } - if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) { - rt_kprintf("0x%08x:", addr + i * 4); - } - rt_kprintf("\t%08x", value); - cnt++; + //mmu_clean_invalidated_dcache(addr,t_size); + rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size); + rt_kprintf("0x%08x:", addr); + for (i = 0; i < size; i++) { + value = *p++; + if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) { + rt_kprintf("\n"); + } + if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) { + rt_kprintf("0x%08x:", addr + i * 4); + } + rt_kprintf("\t%08x", value); + cnt++; - } - rt_kprintf("\n"); + } + rt_kprintf("\n"); } #endif diff --git a/bsp/fh8620/drivers/mmc.c b/bsp/fh8620/drivers/mmc.c index 399efd5829..1b10974975 100644 --- a/bsp/fh8620/drivers/mmc.c +++ b/bsp/fh8620/drivers/mmc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/mmc.h b/bsp/fh8620/drivers/mmc.h index 5de1f5643f..1a0a6c66dc 100644 --- a/bsp/fh8620/drivers/mmc.h +++ b/bsp/fh8620/drivers/mmc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/pwm.c b/bsp/fh8620/drivers/pwm.c index 58c9703d78..497527a2f4 100644 --- a/bsp/fh8620/drivers/pwm.c +++ b/bsp/fh8620/drivers/pwm.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -193,7 +193,7 @@ int fh_pwm_probe(void *priv_data) rt_kprintf("ERROR: %s rt_device calloc failed\n", __func__); return -RT_ENOMEM; } - + pwm_dev->user_data = &pwm_drv; pwm_dev->open =fh_pwm_open; pwm_dev->close = fh_pwm_close; diff --git a/bsp/fh8620/drivers/pwm.h b/bsp/fh8620/drivers/pwm.h index 3693ab7973..b40fa89ff9 100644 --- a/bsp/fh8620/drivers/pwm.h +++ b/bsp/fh8620/drivers/pwm.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef PWM_H_ #define PWM_H_ diff --git a/bsp/fh8620/drivers/sadc.c b/bsp/fh8620/drivers/sadc.c index b1654d295c..403b92cd71 100644 --- a/bsp/fh8620/drivers/sadc.c +++ b/bsp/fh8620/drivers/sadc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -50,123 +50,123 @@ -#define __raw_writeb(v,a) ( *(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) ( *(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) ( *(volatile unsigned int *)(a) = (v)) +#define __raw_writeb(v,a) ( *(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) ( *(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) ( *(volatile unsigned int *)(a) = (v)) -#define __raw_readb(a) ( *(volatile unsigned char *)(a)) -#define __raw_readw(a) ( *(volatile unsigned short *)(a)) -#define __raw_readl(a) ( *(volatile unsigned int *)(a)) +#define __raw_readb(a) ( *(volatile unsigned char *)(a)) +#define __raw_readw(a) ( *(volatile unsigned short *)(a)) +#define __raw_readl(a) ( *(volatile unsigned int *)(a)) #define wrap_readl(wrap, name) \ - __raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writel(wrap, name, val) \ - __raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_readw(wrap, name) \ - __raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writew(wrap, name, val) \ - __raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_readb(wrap, name) \ - __raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writeb(wrap, name, val) \ - __raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) -#define IOCTL_GET_SADC_DATA 1 -#define IOCTL_SADC_POWER_DOWN 0xff -#define SADC_WRAP_BASE (0xf1200000) -#define SADC_IRQn (23) -#define SADC_MAX_CONTROLLER (1) -#define SADC_STATUS_COLESD (0) -#define SADC_STATUS_OPEN (1) +#define IOCTL_GET_SADC_DATA 1 +#define IOCTL_SADC_POWER_DOWN 0xff +#define SADC_WRAP_BASE (0xf1200000) +#define SADC_IRQn (23) +#define SADC_MAX_CONTROLLER (1) +#define SADC_STATUS_COLESD (0) +#define SADC_STATUS_OPEN (1) rt_err_t fh_sadc_isr_read_data(struct wrap_sadc_obj *sadc, rt_uint32_t channel, - rt_uint16_t *buf) { - rt_uint32_t xainsel = 1 << channel; - rt_uint32_t xversel = 0; - rt_uint32_t xpwdb = 1; - //cnt - rt_uint32_t sel2sam_pre_cnt = 2; - rt_uint32_t sam_cnt = 2; - rt_uint32_t sam2sel_pos_cnt = 2; - //time out - rt_uint32_t eoc_tos = 0xff; - rt_uint32_t eoc_toe = 0xff; - rt_uint32_t time_out = 0xffff; - //set isr en.. - rt_uint32_t sadc_isr = 0x01; - //start - rt_uint32_t sadc_cmd = 0x01; - //get data - rt_uint32_t temp_data = 0; - rt_err_t ret; + rt_uint16_t *buf) { + rt_uint32_t xainsel = 1 << channel; + rt_uint32_t xversel = 0; + rt_uint32_t xpwdb = 1; + //cnt + rt_uint32_t sel2sam_pre_cnt = 2; + rt_uint32_t sam_cnt = 2; + rt_uint32_t sam2sel_pos_cnt = 2; + //time out + rt_uint32_t eoc_tos = 0xff; + rt_uint32_t eoc_toe = 0xff; + rt_uint32_t time_out = 0xffff; + //set isr en.. + rt_uint32_t sadc_isr = 0x01; + //start + rt_uint32_t sadc_cmd = 0x01; + //get data + rt_uint32_t temp_data = 0; + rt_err_t ret; - //control... - wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12)); + //control... + wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12)); - wrap_writel(sadc, sadc_cnt, - sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16)); + wrap_writel(sadc, sadc_cnt, + sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16)); - wrap_writel(sadc, sadc_timeout, - eoc_tos | (eoc_toe << 8) | (time_out << 16)); + wrap_writel(sadc, sadc_timeout, + eoc_tos | (eoc_toe << 8) | (time_out << 16)); - wrap_writel(sadc, sadc_ier, sadc_isr); + wrap_writel(sadc, sadc_ier, sadc_isr); - wrap_writel(sadc, sadc_cmd, sadc_cmd); + wrap_writel(sadc, sadc_cmd, sadc_cmd); // ret = rt_completion_wait(&sadc->completion, RT_TICK_PER_SECOND / 2); - ret = rt_sem_take(&sadc->completion, 5000); - if(ret != RT_EOK) - return ret; + ret = rt_sem_take(&sadc->completion, 5000); + if(ret != RT_EOK) + return ret; - switch (channel) { - case 0: - case 1: - //read channel 0 1 - temp_data = wrap_readl(sadc, sadc_dout0); - break; + switch (channel) { + case 0: + case 1: + //read channel 0 1 + temp_data = wrap_readl(sadc, sadc_dout0); + break; - case 2: - case 3: - //read channel 2 3 - temp_data = wrap_readl(sadc, sadc_dout1); - break; + case 2: + case 3: + //read channel 2 3 + temp_data = wrap_readl(sadc, sadc_dout1); + break; - case 4: - case 5: - //read channel 4 5 - temp_data = wrap_readl(sadc, sadc_dout2); - break; + case 4: + case 5: + //read channel 4 5 + temp_data = wrap_readl(sadc, sadc_dout2); + break; - case 6: - case 7: - //read channel 6 7 - temp_data = wrap_readl(sadc, sadc_dout3); - break; - default: - break; - } - if (channel % 2) { - //read low 16bit - *buf = (rt_uint16_t) (temp_data & 0xffff); - } else { - //read high 16bit - *buf = (rt_uint16_t) (temp_data >> 16); - } - return RT_EOK; + case 6: + case 7: + //read channel 6 7 + temp_data = wrap_readl(sadc, sadc_dout3); + break; + default: + break; + } + if (channel % 2) { + //read low 16bit + *buf = (rt_uint16_t) (temp_data & 0xffff); + } else { + //read high 16bit + *buf = (rt_uint16_t) (temp_data >> 16); + } + return RT_EOK; } @@ -204,41 +204,41 @@ static rt_err_t fh_sadc_close(rt_device_t dev) static rt_err_t fh_sadc_ioctl(rt_device_t dev, int cmd, void *arg) { - rt_uint32_t control_reg; - struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data; - rt_uint32_t ad_data; - rt_uint16_t ad_raw_data; + rt_uint32_t control_reg; + struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data; + rt_uint32_t ad_data; + rt_uint16_t ad_raw_data; - SADC_INFO *sadc_info = (SADC_INFO *)arg; - rt_err_t ret; - switch(cmd){ - case SADC_CMD_READ_RAW_DATA: - ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); - if(ret != RT_EOK) - return ret; - sadc_info->sadc_data = ad_raw_data; + SADC_INFO *sadc_info = (SADC_INFO *)arg; + rt_err_t ret; + switch(cmd){ + case SADC_CMD_READ_RAW_DATA: + ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); + if(ret != RT_EOK) + return ret; + sadc_info->sadc_data = ad_raw_data; - break; - case SADC_CMD_READ_VOLT: - ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); - if(ret != RT_EOK) - return ret; + break; + case SADC_CMD_READ_VOLT: + ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); + if(ret != RT_EOK) + return ret; - ad_data = ad_raw_data * SADC_REF; - ad_data /= SADC_MAX_AD_VALUE; - sadc_info->sadc_data = ad_data; + ad_data = ad_raw_data * SADC_REF; + ad_data /= SADC_MAX_AD_VALUE; + sadc_info->sadc_data = ad_data; - break; - case SADC_CMD_DISABLE: - control_reg = wrap_readl(sadc_pri, sadc_control); - control_reg &= ~(1 << 12); - wrap_writel(sadc_pri, sadc_control, control_reg); + break; + case SADC_CMD_DISABLE: + control_reg = wrap_readl(sadc_pri, sadc_control); + control_reg &= ~(1 << 12); + wrap_writel(sadc_pri, sadc_control, control_reg); - break; - default : - rt_kprintf("wrong para...\n"); - return RT_EIO; - } + break; + default : + rt_kprintf("wrong para...\n"); + return RT_EIO; + } return RT_EOK; } @@ -249,25 +249,25 @@ static void fh_sadc_interrupt(int irq, void *param) { rt_uint32_t isr_status; - struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param; + struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param; - isr_status = wrap_readl(sadc, sadc_int_status); + isr_status = wrap_readl(sadc, sadc_int_status); - if (isr_status & 0x01) { - //close isr - rt_uint32_t sadc_isr = 0x00; + if (isr_status & 0x01) { + //close isr + rt_uint32_t sadc_isr = 0x00; - wrap_writel(sadc, sadc_ier, sadc_isr); - //clear status.. + wrap_writel(sadc, sadc_ier, sadc_isr); + //clear status.. - wrap_writel(sadc, sadc_int_status, isr_status); + wrap_writel(sadc, sadc_int_status, isr_status); - rt_sem_release(&sadc->completion); - // rt_completion_done(&sadc->completion); - } else { - //add error handle process - rt_kprintf("sadc maybe error!\n"); - } + rt_sem_release(&sadc->completion); + // rt_completion_done(&sadc->completion); + } else { + //add error handle process + rt_kprintf("sadc maybe error!\n"); + } } @@ -282,13 +282,13 @@ int fh_sadc_probe(void *priv_data) //caution this is a read only data...if the driver want to use.malloc and copy it.. struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; if(sadc_obj->init_flag == SADC_INIT_ALREADY) - return RT_EFULL; + return RT_EFULL; //malloc a rt device.. sadc_dev = RT_KERNEL_MALLOC(sizeof(struct rt_device)); if(!sadc_dev){ - return RT_ENOMEM; + return RT_ENOMEM; } rt_memset(sadc_dev, 0, sizeof(struct rt_device)); PRINT_SADC_DBG("id:%d,\treg:%x,\tirq:%d\n",sadc_obj->id,(rt_uint32_t)sadc_obj->regs,sadc_obj->irq_no); @@ -304,8 +304,8 @@ int fh_sadc_probe(void *priv_data) struct wrap_sadc_obj *sadc_pri = RT_KERNEL_MALLOC(sizeof(struct wrap_sadc_obj)); if(!sadc_pri){ - RT_KERNEL_FREE(sadc_dev); - return RT_ENOMEM; + RT_KERNEL_FREE(sadc_dev); + return RT_ENOMEM; } //copy platform data to pri data.. @@ -349,23 +349,23 @@ int fh_sadc_probe(void *priv_data) int fh_sadc_exit(void *priv_data) { - PRINT_SADC_DBG("%s\n",__func__); - struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; + PRINT_SADC_DBG("%s\n",__func__); + struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; - struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data; - //release sem; - rt_sem_detach(&sadc_pri->completion); - //sadc_pri->completion = RT_NULL; + struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data; + //release sem; + rt_sem_detach(&sadc_pri->completion); + //sadc_pri->completion = RT_NULL; - //release lock; - rt_mutex_detach(&sadc_pri->lock); + //release lock; + rt_mutex_detach(&sadc_pri->lock); - RT_KERNEL_FREE(sadc_obj->rt_dev->user_data); + RT_KERNEL_FREE(sadc_obj->rt_dev->user_data); - sadc_obj->rt_dev->user_data = RT_NULL; - RT_KERNEL_FREE(sadc_obj->rt_dev); - sadc_obj->rt_dev = RT_NULL; + sadc_obj->rt_dev->user_data = RT_NULL; + RT_KERNEL_FREE(sadc_obj->rt_dev); + sadc_obj->rt_dev = RT_NULL; return 0; } @@ -386,23 +386,23 @@ void rt_hw_sadc_init(void) #ifdef FH_TEST_SADC int fh_sadc_test(void){ - rt_device_t sadc_dev; - SADC_INFO info; - info.channel = 0; - info.sadc_data = 0; - sadc_dev = rt_device_find("sadc"); - if(!sadc_dev){ - rt_kprintf("cann't find the sadc dev\n"); - } - sadc_dev->init(sadc_dev); - sadc_dev->open(sadc_dev,0); - while(1) - { - sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info); - rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data); - } + rt_device_t sadc_dev; + SADC_INFO info; + info.channel = 0; + info.sadc_data = 0; + sadc_dev = rt_device_find("sadc"); + if(!sadc_dev){ + rt_kprintf("cann't find the sadc dev\n"); + } + sadc_dev->init(sadc_dev); + sadc_dev->open(sadc_dev,0); + while(1) + { + sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info); + rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data); + } - return 0; + return 0; } #endif diff --git a/bsp/fh8620/drivers/sadc.h b/bsp/fh8620/drivers/sadc.h index d28ed9ba24..afe168bd2e 100644 --- a/bsp/fh8620/drivers/sadc.h +++ b/bsp/fh8620/drivers/sadc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef SADC_H_ #define SADC_H_ @@ -33,57 +33,57 @@ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ //#define FH_SADC_PROC_FILE "driver/sadc" -#define MAX_CHANNEL_NO (8) -#define SADC_REF (3300) -#define SADC_MAX_AD_VALUE (0x3ff) -#define LOOP_MODE (0x55) -#define ISR_MODE (0xAA) +#define MAX_CHANNEL_NO (8) +#define SADC_REF (3300) +#define SADC_MAX_AD_VALUE (0x3ff) +#define LOOP_MODE (0x55) +#define ISR_MODE (0xAA) -#define SADC_INIT_ALREADY (0x33) -#define SADC_INIT_NOT_YET (0) +#define SADC_INIT_ALREADY (0x33) +#define SADC_INIT_NOT_YET (0) -#define SADC_CMD_READ_RAW_DATA (0x22) -#define SADC_CMD_READ_VOLT (0x33) -#define SADC_CMD_DISABLE (0x44) +#define SADC_CMD_READ_RAW_DATA (0x22) +#define SADC_CMD_READ_VOLT (0x33) +#define SADC_CMD_DISABLE (0x44) /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ struct wrap_sadc_reg { - rt_uint32_t sadc_cmd; - rt_uint32_t sadc_control; - rt_uint32_t sadc_ier; - rt_uint32_t sadc_int_status; - rt_uint32_t sadc_dout0; - rt_uint32_t sadc_dout1; - rt_uint32_t sadc_dout2; - rt_uint32_t sadc_dout3; - rt_uint32_t sadc_debuge0; - rt_uint32_t sadc_status; - rt_uint32_t sadc_cnt; - rt_uint32_t sadc_timeout; + rt_uint32_t sadc_cmd; + rt_uint32_t sadc_control; + rt_uint32_t sadc_ier; + rt_uint32_t sadc_int_status; + rt_uint32_t sadc_dout0; + rt_uint32_t sadc_dout1; + rt_uint32_t sadc_dout2; + rt_uint32_t sadc_dout3; + rt_uint32_t sadc_debuge0; + rt_uint32_t sadc_status; + rt_uint32_t sadc_cnt; + rt_uint32_t sadc_timeout; }; struct wrap_sadc_obj { - rt_uint32_t id; - void *regs; - rt_uint32_t irq_no; - rt_uint32_t init_flag; - rt_uint32_t active_channel_no; - rt_uint32_t active_channel_status; - rt_uint16_t channel_data[MAX_CHANNEL_NO]; - rt_uint32_t error_rec; - rt_uint32_t en_isr; - rt_uint32_t sample_mode; - struct rt_mutex lock; - struct rt_semaphore completion; + rt_uint32_t id; + void *regs; + rt_uint32_t irq_no; + rt_uint32_t init_flag; + rt_uint32_t active_channel_no; + rt_uint32_t active_channel_status; + rt_uint16_t channel_data[MAX_CHANNEL_NO]; + rt_uint32_t error_rec; + rt_uint32_t en_isr; + rt_uint32_t sample_mode; + struct rt_mutex lock; + struct rt_semaphore completion; //bind to the rtdev.. rt_device_t rt_dev; @@ -91,8 +91,8 @@ struct wrap_sadc_obj { }; typedef struct{ - rt_uint32_t channel; - rt_uint32_t sadc_data; + rt_uint32_t channel; + rt_uint32_t sadc_data; }SADC_INFO; @@ -102,7 +102,7 @@ typedef struct{ /**************************************************************************** * section - * add function prototype here if any + * add function prototype here if any ***************************************************************************/ void rt_hw_sadc_init(void); #endif diff --git a/bsp/fh8620/drivers/spi_fh_adapt.c b/bsp/fh8620/drivers/spi_fh_adapt.c index 291fe9a4f9..437b30d1c9 100644 --- a/bsp/fh8620/drivers/spi_fh_adapt.c +++ b/bsp/fh8620/drivers/spi_fh_adapt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /* * spi_fh_adapt.c * @@ -60,9 +60,9 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#define WX_MANU_ID 0xEF +#define WX_MANU_ID 0xEF #define AT_MANU_ID 0x1F /* atmel */ -#define SST_MANU_ID 0xBF +#define SST_MANU_ID 0xBF #define GD_MANU_ID 0xC8 @@ -70,50 +70,50 @@ #define SPI_ADAPT_DEBUG #ifdef SPI_ADAPT_DEBUG -#define CMD_JEDEC_ID 0x9f +#define CMD_JEDEC_ID 0x9f -#define FH_SPI_ADAPT_DEBUG(fmt, args...) \ - rt_kprintf(fmt,##args); +#define FH_SPI_ADAPT_DEBUG(fmt, args...) \ + rt_kprintf(fmt,##args); #else #define FH_SPI_ADAPT_DEBUG(fmt, args...) #endif struct fh_flash_id{ - unsigned char id; - rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash); - char *name; + unsigned char id; + rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash); + char *name; }; const struct fh_flash_id id_map[] = { #ifdef RT_USING_W25QXX - WX_MANU_ID,w25qxx_init,"winbond", + WX_MANU_ID,w25qxx_init,"winbond", #endif #ifdef RT_USING_AT45DBXX - AT_MANU_ID,at45dbxx_init,"atmel", + AT_MANU_ID,at45dbxx_init,"atmel", #endif #ifdef RT_USING_SST25VFXX - SST_MANU_ID,sst25vfxx_init,"SST", + SST_MANU_ID,sst25vfxx_init,"SST", #endif #ifdef RT_USING_GD - GD_MANU_ID,gd_init,"GD", + GD_MANU_ID,gd_init,"GD", #endif }; struct fh_flash_id * fh_flash_check_id_map(unsigned char id){ - struct fh_flash_id *p_map = RT_NULL; - unsigned int i; - for (i = 0; i < ARRAY_SIZE(id_map); i++) { - p_map = (struct fh_flash_id *)&id_map[i]; - if (p_map->id == id){ - return p_map; - } - } - return RT_NULL; + struct fh_flash_id *p_map = RT_NULL; + unsigned int i; + for (i = 0; i < ARRAY_SIZE(id_map); i++) { + p_map = (struct fh_flash_id *)&id_map[i]; + if (p_map->id == id){ + return p_map; + } + } + return RT_NULL; } @@ -144,50 +144,50 @@ int fh_flash_adapt_probe(void *priv_data) /* init flash */ - rt_uint8_t cmd; - rt_uint8_t id_recv[3]; - uint16_t memory_type_capacity; - rt_err_t ret; + rt_uint8_t cmd; + rt_uint8_t id_recv[3]; + uint16_t memory_type_capacity; + rt_err_t ret; - cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */ - rt_spi_send(rt_spi_device, &cmd, 1); - /* read flash id */ - cmd = CMD_JEDEC_ID; - rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3); + cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */ + rt_spi_send(rt_spi_device, &cmd, 1); + /* read flash id */ + cmd = CMD_JEDEC_ID; + rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3); - //if the flash is already connect. - if(id_recv[0] != 0xff){ - flash_model =fh_flash_check_id_map(id_recv[0]); - if(flash_model){ - ret = flash_model->fh_flash_init(plat_flash); - if(ret != RT_EOK){ - rt_kprintf("flash:%s init error\n",flash_model->name); - rt_kprintf("use default flash ops..\n"); - //flash_model->fh_flash_adapt_init =flash_default_init; - ret = flash_default_init(plat_flash); - } - } - else{ - rt_kprintf( - "use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n", - id_recv[0], id_recv[1], id_recv[2]); - ret = flash_default_init(plat_flash); + //if the flash is already connect. + if(id_recv[0] != 0xff){ + flash_model =fh_flash_check_id_map(id_recv[0]); + if(flash_model){ + ret = flash_model->fh_flash_init(plat_flash); + if(ret != RT_EOK){ + rt_kprintf("flash:%s init error\n",flash_model->name); + rt_kprintf("use default flash ops..\n"); + //flash_model->fh_flash_adapt_init =flash_default_init; + ret = flash_default_init(plat_flash); + } + } + else{ + rt_kprintf( + "use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n", + id_recv[0], id_recv[1], id_recv[2]); + ret = flash_default_init(plat_flash); - } + } - int i; - for(i=0; i<plat_flash->nr_parts; i++) - { - fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]); - } + int i; + for(i=0; i<plat_flash->nr_parts; i++) + { + fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]); + } - return ret; + return ret; - } - else{ - rt_kprintf("please check if you connect the flash already...\n"); - return RT_ENOSYS; - } + } + else{ + rt_kprintf("please check if you connect the flash already...\n"); + return RT_ENOSYS; + } } diff --git a/bsp/fh8620/drivers/spi_fh_adapt.h b/bsp/fh8620/drivers/spi_fh_adapt.h index 171fdf7184..3e3cc365ab 100644 --- a/bsp/fh8620/drivers/spi_fh_adapt.h +++ b/bsp/fh8620/drivers/spi_fh_adapt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /* * spi_fh_adapt.h * diff --git a/bsp/fh8620/drivers/ssi.c b/bsp/fh8620/drivers/ssi.c index e5cb99042e..c87a4352ae 100644 --- a/bsp/fh8620/drivers/ssi.c +++ b/bsp/fh8620/drivers/ssi.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rtdevice.h> #include <drivers/spi.h> #include "fh_arch.h" @@ -49,20 +49,20 @@ #endif -#define RX_DMA_CHANNEL AUTO_FIND_CHANNEL -#define TX_DMA_CHANNEL AUTO_FIND_CHANNEL +#define RX_DMA_CHANNEL AUTO_FIND_CHANNEL +#define TX_DMA_CHANNEL AUTO_FIND_CHANNEL -#define DMA_OR_ISR_THRESHOLD 20 -#define MALLOC_DMA_MEM_SIZE 0x1000 +#define DMA_OR_ISR_THRESHOLD 20 +#define MALLOC_DMA_MEM_SIZE 0x1000 //static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){ -// return (in_addr + allign_size-1) & (~(allign_size - 1)); +// return (in_addr + allign_size-1) & (~(allign_size - 1)); //} void * fh_get_spi_dev_pri_data(struct rt_spi_device* device){ - return device->parent.user_data; + return device->parent.user_data; } static rt_err_t fh_spi_configure(struct rt_spi_device* device, @@ -87,54 +87,54 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device, PRINT_SPI_DBG("\tmax_hz: 0x%x\n", configuration->max_hz); do{ - status = SPI_ReadStatus(spi_obj); - } + status = SPI_ReadStatus(spi_obj); + } while(status & SPI_STATUS_BUSY); - /* data_width */ - if(configuration->data_width <= 8){ - config->data_size = SPI_DATA_SIZE_8BIT; - } - else if(configuration->data_width <= 16){ - config->data_size = SPI_DATA_SIZE_16BIT; - } - else{ - return -RT_ERROR; - } + /* data_width */ + if(configuration->data_width <= 8){ + config->data_size = SPI_DATA_SIZE_8BIT; + } + else if(configuration->data_width <= 16){ + config->data_size = SPI_DATA_SIZE_16BIT; + } + else{ + return -RT_ERROR; + } - if(configuration->max_hz > spi_control->max_hz) - spi_hz = spi_control->max_hz; - else - spi_hz = configuration->max_hz; + if(configuration->max_hz > spi_control->max_hz) + spi_hz = spi_control->max_hz; + else + spi_hz = configuration->max_hz; - //fixme: div - config->clk_div = spi_control->clk_in/spi_hz; - //config->clk_div = 8; - PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div); - /* CPOL */ - if(configuration->mode & RT_SPI_CPOL){ - config->clk_polarity = SPI_POLARITY_HIGH; - } - else{ - config->clk_polarity = SPI_POLARITY_LOW; - } + //fixme: div + config->clk_div = spi_control->clk_in/spi_hz; + //config->clk_div = 8; + PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div); + /* CPOL */ + if(configuration->mode & RT_SPI_CPOL){ + config->clk_polarity = SPI_POLARITY_HIGH; + } + else{ + config->clk_polarity = SPI_POLARITY_LOW; + } - /* CPHA */ - if(configuration->mode & RT_SPI_CPHA){ - config->clk_phase = SPI_PHASE_TX_FIRST; - } - else{ - config->clk_phase = SPI_PHASE_RX_FIRST; - } + /* CPHA */ + if(configuration->mode & RT_SPI_CPHA){ + config->clk_phase = SPI_PHASE_TX_FIRST; + } + else{ + config->clk_phase = SPI_PHASE_RX_FIRST; + } - config->frame_format = SPI_FORMAT_MOTOROLA; - config->transfer_mode = SPI_MODE_TX_RX; + config->frame_format = SPI_FORMAT_MOTOROLA; + config->transfer_mode = SPI_MODE_TX_RX; - SPI_Enable(spi_obj, 0); - SPI_SetParameter(spi_obj); - SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL); - SPI_Enable(spi_obj, 1); + SPI_Enable(spi_obj, 0); + SPI_SetParameter(spi_obj); + SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL); + SPI_Enable(spi_obj, 1); return RT_EOK; } @@ -142,8 +142,8 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device, static void xfer_dma_done(void *arg) { - struct spi_controller *spi_control = (struct spi_controller *)arg; - spi_control->dma_complete_times++; + struct spi_controller *spi_control = (struct spi_controller *)arg; + spi_control->dma_complete_times++; struct fh_spi_obj *spi_obj; int ret; @@ -151,72 +151,72 @@ static void xfer_dma_done(void *arg) spi_obj = &spi_control->obj; - //rt_kprintf("spi dma isr done.....\n"); - if (spi_control->dma_complete_times == 2) { - spi_control->dma_complete_times = 0; + //rt_kprintf("spi dma isr done.....\n"); + if (spi_control->dma_complete_times == 2) { + spi_control->dma_complete_times = 0; - //add memcpy to user buff - if(spi_control->current_message->recv_buf){ - rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length); - } + //add memcpy to user buff + if(spi_control->current_message->recv_buf){ + rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length); + } - SPI_Enable(spi_obj,0); - SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); - SPI_Enable(spi_obj,1); + SPI_Enable(spi_obj,0); + SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); + SPI_Enable(spi_obj,1); - rt_completion_done(&spi_control->transfer_completion); - } + rt_completion_done(&spi_control->transfer_completion); + } } void dma_set_tx_data(struct spi_controller *spi_control){ - struct dma_transfer *trans; - rt_uint32_t hs_no; - struct rt_spi_message* current_message = spi_control->current_message; - trans = &spi_control->dma.tx_trans; - hs_no = spi_control->dma.tx_hs; + struct dma_transfer *trans; + rt_uint32_t hs_no; + struct rt_spi_message* current_message = spi_control->current_message; + trans = &spi_control->dma.tx_trans; + hs_no = spi_control->dma.tx_hs; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - if(current_message->length > MALLOC_DMA_MEM_SIZE){ - rt_kprintf("[spi_dma]message len too large..\n"); - rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE); - RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); - } + if(current_message->length > MALLOC_DMA_MEM_SIZE){ + rt_kprintf("[spi_dma]message len too large..\n"); + rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE); + RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); + } - rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length); - //copy tx data.... - if(current_message->send_buf){ - rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length); - } + rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length); + //copy tx data.... + if(current_message->send_buf){ + rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length); + } - trans->dma_number = 0; - trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); + trans->dma_number = 0; + trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); - trans->dst_hs = DMA_HW_HANDSHAKING; - trans->dst_inc_mode = DW_DMA_SLAVE_FIX; - trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; - trans->dst_per = hs_no; - trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->fc_mode = DMA_M2P; + trans->dst_hs = DMA_HW_HANDSHAKING; + trans->dst_inc_mode = DW_DMA_SLAVE_FIX; + trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; + trans->dst_per = hs_no; + trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->fc_mode = DMA_M2P; - trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff; + trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff; - trans->src_inc_mode = DW_DMA_SLAVE_INC; - trans->src_msize = DW_DMA_SLAVE_MSIZE_1; + trans->src_inc_mode = DW_DMA_SLAVE_INC; + trans->src_msize = DW_DMA_SLAVE_MSIZE_1; - trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->trans_len = current_message->length; + trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->trans_len = current_message->length; - trans->complete_callback = (void *)xfer_dma_done; - trans->complete_para = (void *)spi_control; + trans->complete_callback = (void *)xfer_dma_done; + trans->complete_para = (void *)spi_control; @@ -225,153 +225,153 @@ void dma_set_tx_data(struct spi_controller *spi_control){ void dma_set_rx_data(struct spi_controller *spi_control){ - struct dma_transfer *trans; - rt_uint32_t hs_no; - struct rt_spi_message* current_message = spi_control->current_message; - trans = &spi_control->dma.rx_trans; - hs_no = spi_control->dma.rx_hs; + struct dma_transfer *trans; + rt_uint32_t hs_no; + struct rt_spi_message* current_message = spi_control->current_message; + trans = &spi_control->dma.rx_trans; + hs_no = spi_control->dma.rx_hs; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - if(current_message->length > MALLOC_DMA_MEM_SIZE){ - rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length); - RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); - } + if(current_message->length > MALLOC_DMA_MEM_SIZE){ + rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length); + RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); + } - //rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE); + //rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE); - trans->dma_number = 0; - trans->fc_mode = DMA_P2M; + trans->dma_number = 0; + trans->fc_mode = DMA_P2M; - trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff; - trans->dst_inc_mode = DW_DMA_SLAVE_INC; - trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; - trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff; + trans->dst_inc_mode = DW_DMA_SLAVE_INC; + trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; + trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); - trans->src_inc_mode = DW_DMA_SLAVE_FIX; - trans->src_msize = DW_DMA_SLAVE_MSIZE_1; - trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->src_hs = DMA_HW_HANDSHAKING; - trans->src_per = hs_no; - trans->trans_len = current_message->length; + trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); + trans->src_inc_mode = DW_DMA_SLAVE_FIX; + trans->src_msize = DW_DMA_SLAVE_MSIZE_1; + trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->src_hs = DMA_HW_HANDSHAKING; + trans->src_per = hs_no; + trans->trans_len = current_message->length; - trans->complete_callback = (void *)xfer_dma_done; - trans->complete_para = (void *)spi_control; + trans->complete_callback = (void *)xfer_dma_done; + trans->complete_para = (void *)spi_control; } rt_uint32_t xfer_data_dma(struct spi_controller *spi_control){ - int ret; + int ret; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - struct rt_dma_device *dma_dev = spi_control->dma.dma_dev; + struct rt_dma_device *dma_dev = spi_control->dma.dma_dev; - //tx data prepare - dma_set_tx_data(spi_control); - //rx data prepare - dma_set_rx_data(spi_control); - //dma go... + //tx data prepare + dma_set_tx_data(spi_control); + //rx data prepare + dma_set_rx_data(spi_control); + //dma go... - SPI_Enable(spi_obj,0); + SPI_Enable(spi_obj,0); - //SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4); - SPI_WriteTxDmaLevel(spi_obj,1); - //SPI_WriteTxDmaLevel(spi_obj,0); - SPI_WriteRxDmaLevel(spi_obj,0); - SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); - SPI_Enable(spi_obj,1); + //SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4); + SPI_WriteTxDmaLevel(spi_obj,1); + //SPI_WriteTxDmaLevel(spi_obj,0); + SPI_WriteRxDmaLevel(spi_obj,0); + SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); + SPI_Enable(spi_obj,1); - dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans); - dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans); + dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans); + dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans); - ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); - //release channel.. + ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); + //release channel.. - //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans); - //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans); + //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans); + //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans); - if(ret) - { - rt_kprintf("ERROR: %s, transfer timeout\n", __func__); - return -RT_ETIMEOUT; - } + if(ret) + { + rt_kprintf("ERROR: %s, transfer timeout\n", __func__); + return -RT_ETIMEOUT; + } - return RT_EOK; + return RT_EOK; } rt_uint32_t xfer_data_isr(struct spi_controller *spi_control){ - int ret; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + int ret; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; SPI_SetTxLevel(spi_obj, SPI_FIFO_DEPTH / 2); SPI_EnableInterrupt(spi_obj, SPI_IRQ_TXEIM); - ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); - if(ret) - { - rt_kprintf("ERROR: %s, transfer timeout\n", __func__); - return -RT_ETIMEOUT; - } + ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); + if(ret) + { + rt_kprintf("ERROR: %s, transfer timeout\n", __func__); + return -RT_ETIMEOUT; + } - return RT_EOK; + return RT_EOK; } void fix_spi_xfer_mode(struct spi_controller *spi_control){ - //switch dma or isr....first check dma ...is error .use isr xfer... - struct rt_dma_device * rt_dma_dev; - struct dma_transfer *tx_trans; - struct dma_transfer *rx_trans; - int ret; - //retry to check if the dma status... - if(spi_control->dma.dma_flag == DMA_BIND_OK){ - //if transfer data too short...use isr.. - if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){ - spi_control->xfer_mode = XFER_USE_ISR; - return; - } + //switch dma or isr....first check dma ...is error .use isr xfer... + struct rt_dma_device * rt_dma_dev; + struct dma_transfer *tx_trans; + struct dma_transfer *rx_trans; + int ret; + //retry to check if the dma status... + if(spi_control->dma.dma_flag == DMA_BIND_OK){ + //if transfer data too short...use isr.. + if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){ + spi_control->xfer_mode = XFER_USE_ISR; + return; + } #if(0) - rt_dma_dev = spi_control->dma.dma_dev; - //first request channel + rt_dma_dev = spi_control->dma.dma_dev; + //first request channel - tx_trans = &spi_control->dma.tx_trans; - rx_trans = &spi_control->dma.rx_trans; - tx_trans->channel_number = TX_DMA_CHANNEL; - rx_trans->channel_number = RX_DMA_CHANNEL; + tx_trans = &spi_control->dma.tx_trans; + rx_trans = &spi_control->dma.rx_trans; + tx_trans->channel_number = TX_DMA_CHANNEL; + rx_trans->channel_number = RX_DMA_CHANNEL; - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); - if(ret != RT_EOK){ - spi_control->xfer_mode = XFER_USE_ISR; - return; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); + if(ret != RT_EOK){ + spi_control->xfer_mode = XFER_USE_ISR; + return; + } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); - if(ret != RT_EOK){ - //release tx channel... - rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); - spi_control->xfer_mode = XFER_USE_ISR; - return; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); + if(ret != RT_EOK){ + //release tx channel... + rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); + spi_control->xfer_mode = XFER_USE_ISR; + return; + } #endif - spi_control->xfer_mode = XFER_USE_DMA; - //if error use isr mode - } - else - spi_control->xfer_mode = XFER_USE_ISR; + spi_control->xfer_mode = XFER_USE_DMA; + //if error use isr mode + } + else + spi_control->xfer_mode = XFER_USE_ISR; @@ -392,7 +392,7 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa spi_control->transfered_len = 0; spi_control->received_len = 0; - rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER); + rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER); rt_completion_init(&spi_control->transfer_completion); @@ -400,52 +400,52 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa /* take CS */ if(message->cs_take) { - if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) - gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); - else - gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); + if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) + gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); + else + gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); - //here will always use the slave_0 because that the cs is gpio... - SPI_EnableSlaveen(spi_obj, 0); + //here will always use the slave_0 because that the cs is gpio... + SPI_EnableSlaveen(spi_obj, 0); } //fix transfer mode ..... fix_spi_xfer_mode(spi_control); - switch(spi_control->xfer_mode){ - case XFER_USE_DMA: - PRINT_SPI_DBG("use dma xfer.....###############\n"); - ret = xfer_data_dma(spi_control); - if(ret == RT_EOK){ - break; - } - else{ - //use the isr mode to transfer - spi_control->xfer_mode = XFER_USE_ISR; - rt_kprintf("%s dma transfer error no:%x\n",__func__,ret); - } - case XFER_USE_ISR: - PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n"); - ret = xfer_data_isr(spi_control); - if(ret != RT_EOK) - rt_kprintf("%s isr transfer error no:%x\n",__func__,ret); - break; + switch(spi_control->xfer_mode){ + case XFER_USE_DMA: + PRINT_SPI_DBG("use dma xfer.....###############\n"); + ret = xfer_data_dma(spi_control); + if(ret == RT_EOK){ + break; + } + else{ + //use the isr mode to transfer + spi_control->xfer_mode = XFER_USE_ISR; + rt_kprintf("%s dma transfer error no:%x\n",__func__,ret); + } + case XFER_USE_ISR: + PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n"); + ret = xfer_data_isr(spi_control); + if(ret != RT_EOK) + rt_kprintf("%s isr transfer error no:%x\n",__func__,ret); + break; - default: - rt_kprintf("%s unknow xfer func...\n",__func__); - while(1) - ; - } + default: + rt_kprintf("%s unknow xfer func...\n",__func__); + while(1) + ; + } /* release CS */ if(message->cs_release) { - if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) - gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); - else - gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); - SPI_DisableSlaveen(spi_obj, 0); + if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) + gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); + else + gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); + SPI_DisableSlaveen(spi_obj, 0); } rt_sem_release(&spi_control->xfer_lock); @@ -479,73 +479,73 @@ static void fh_spi_interrupt(int irq, void *param) // - if(spi_control->current_message == RT_NULL){ - rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__); - } + if(spi_control->current_message == RT_NULL){ + rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__); + } - status = SPI_InterruptStatus(spi_obj); - PRINT_SPI_DBG("status: 0x%x\n", status); - //fixme: ??recv overflow, underflow; tran overflow?? - if(status & SPI_ISR_ERROR){ - rt_kprintf("ERROR: %s, status=%d\n", __func__, status); - SPI_ClearInterrupt(spi_obj); - //fixme: handle error - return; - } + status = SPI_InterruptStatus(spi_obj); + PRINT_SPI_DBG("status: 0x%x\n", status); + //fixme: ??recv overflow, underflow; tran overflow?? + if(status & SPI_ISR_ERROR){ + rt_kprintf("ERROR: %s, status=%d\n", __func__, status); + SPI_ClearInterrupt(spi_obj); + //fixme: handle error + return; + } - rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj); - tx_fifo_capability = MIN( - (SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2, - (spi_control->current_message->length - spi_control->transfered_len)); + rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj); + tx_fifo_capability = MIN( + (SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2, + (spi_control->current_message->length - spi_control->transfered_len)); - PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability); + PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability); - //rx - spi_control->received_len += rx_fifo_capability; - while(rx_fifo_capability) - { - data = SPI_ReadData(spi_obj); - if(spi_control->current_message->recv_buf){ - *(rt_uint8_t *)spi_control->current_message->recv_buf++ = data; - } - PRINT_SPI_DBG("rx, data: 0x%x\n", data); - //rt_kprintf("rx, data: 0x%x\n", data); - rx_fifo_capability--; - } + //rx + spi_control->received_len += rx_fifo_capability; + while(rx_fifo_capability) + { + data = SPI_ReadData(spi_obj); + if(spi_control->current_message->recv_buf){ + *(rt_uint8_t *)spi_control->current_message->recv_buf++ = data; + } + PRINT_SPI_DBG("rx, data: 0x%x\n", data); + //rt_kprintf("rx, data: 0x%x\n", data); + rx_fifo_capability--; + } - if(spi_control->received_len == spi_control->current_message->length) - { + if(spi_control->received_len == spi_control->current_message->length) + { - //rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj"); - SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG); - PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len); - rt_completion_done(&spi_control->transfer_completion); + //rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj"); + SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG); + PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len); + rt_completion_done(&spi_control->transfer_completion); - return; - } + return; + } - //tx + //tx - spi_control->transfered_len +=tx_fifo_capability; - if(spi_control->current_message->send_buf){ - p = (rt_uint8_t *)spi_control->current_message->send_buf; - while(tx_fifo_capability){ - PRINT_SPI_DBG("tx, data: 0x%x\n", *p); - //rt_kprintf("tx, data: 0x%x\n", *p); - SPI_WriteData(spi_obj, *p++); - tx_fifo_capability--; - } - spi_control->current_message->send_buf = p; - } - else{ - while(tx_fifo_capability){ + spi_control->transfered_len +=tx_fifo_capability; + if(spi_control->current_message->send_buf){ + p = (rt_uint8_t *)spi_control->current_message->send_buf; + while(tx_fifo_capability){ + PRINT_SPI_DBG("tx, data: 0x%x\n", *p); + //rt_kprintf("tx, data: 0x%x\n", *p); + SPI_WriteData(spi_obj, *p++); + tx_fifo_capability--; + } + spi_control->current_message->send_buf = p; + } + else{ + while(tx_fifo_capability){ - SPI_WriteData(spi_obj, 0xff); - tx_fifo_capability--; - } - } + SPI_WriteData(spi_obj, 0xff); + tx_fifo_capability--; + } + } @@ -568,28 +568,28 @@ int fh_spi_probe(void *priv_data) struct spi_control_platform_data *plat_data; int i,ret; - struct rt_dma_device * rt_dma_dev; - struct dma_transfer *tx_trans; - struct dma_transfer *rx_trans; + struct rt_dma_device * rt_dma_dev; + struct dma_transfer *tx_trans; + struct dma_transfer *rx_trans; //check data... plat_data = (struct spi_control_platform_data *)priv_data; if(!plat_data){ - rt_kprintf("ERROR:platform data null...\n"); - return -RT_ENOMEM; + rt_kprintf("ERROR:platform data null...\n"); + return -RT_ENOMEM; } if(plat_data->slave_no > FH_SPI_SLAVE_MAX_NO){ - rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no); - return -RT_ENOMEM; + rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no); + return -RT_ENOMEM; } //malloc data spi_control = (struct spi_controller*)rt_malloc(sizeof(struct spi_controller)); if(!spi_control){ - rt_kprintf("ERROR:no mem for malloc the spi controller..\n"); - goto error_malloc_bus; + rt_kprintf("ERROR:no mem for malloc the spi controller..\n"); + goto error_malloc_bus; } rt_memset(spi_control, 0, sizeof(struct spi_controller)); @@ -624,77 +624,77 @@ int fh_spi_probe(void *priv_data) if(plat_data->transfer_mode == USE_DMA_TRANSFER){ spi_control->dma.dma_dev = (struct rt_dma_device *)rt_device_find(plat_data->dma_name); - if(spi_control->dma.dma_dev == RT_NULL){ - rt_kprintf("can't find dma dev\n"); - //goto error_malloc_slave; - //spi_control->dma_xfer_flag = USE_ISR_TRANSFER; -// spi_control->dma.dma_flag = DMA_BIND_ERROR; -// spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } - else{ + if(spi_control->dma.dma_dev == RT_NULL){ + rt_kprintf("can't find dma dev\n"); + //goto error_malloc_slave; + //spi_control->dma_xfer_flag = USE_ISR_TRANSFER; +// spi_control->dma.dma_flag = DMA_BIND_ERROR; +// spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } + else{ - spi_control->dma.control = spi_control; - spi_control->dma.rx_hs = plat_data->rx_hs_no; - spi_control->dma.tx_hs = plat_data->tx_hs_no; - spi_control->dma.dma_name = plat_data->dma_name; + spi_control->dma.control = spi_control; + spi_control->dma.rx_hs = plat_data->rx_hs_no; + spi_control->dma.tx_hs = plat_data->tx_hs_no; + spi_control->dma.dma_name = plat_data->dma_name; - spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); - if(!spi_control->dma.rx_dummy_buff){ - rt_kprintf("malloc rx dma buff failed...\n"); - //spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } + spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); + if(!spi_control->dma.rx_dummy_buff){ + rt_kprintf("malloc rx dma buff failed...\n"); + //spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } - spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); - if(!spi_control->dma.tx_dummy_buff){ - rt_kprintf("malloc tx dma buff failed...\n"); - fh_dma_mem_free(spi_control->dma.rx_dummy_buff); - //spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } + spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); + if(!spi_control->dma.tx_dummy_buff){ + rt_kprintf("malloc tx dma buff failed...\n"); + fh_dma_mem_free(spi_control->dma.rx_dummy_buff); + //spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } - if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){ - rt_kprintf("dma malloc buff not allign..\n"); - fh_dma_mem_free(spi_control->dma.rx_dummy_buff); - fh_dma_mem_free(spi_control->dma.tx_dummy_buff); - goto BIND_DMA_ERROR; - } + if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){ + rt_kprintf("dma malloc buff not allign..\n"); + fh_dma_mem_free(spi_control->dma.rx_dummy_buff); + fh_dma_mem_free(spi_control->dma.tx_dummy_buff); + goto BIND_DMA_ERROR; + } - //open dma dev. - spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL); + //open dma dev. + spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL); - //request channel - rt_dma_dev = spi_control->dma.dma_dev; - //first request channel - tx_trans = &spi_control->dma.tx_trans; - rx_trans = &spi_control->dma.rx_trans; - tx_trans->channel_number = TX_DMA_CHANNEL; - rx_trans->channel_number = RX_DMA_CHANNEL; + //request channel + rt_dma_dev = spi_control->dma.dma_dev; + //first request channel + tx_trans = &spi_control->dma.tx_trans; + rx_trans = &spi_control->dma.rx_trans; + tx_trans->channel_number = TX_DMA_CHANNEL; + rx_trans->channel_number = RX_DMA_CHANNEL; - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); - if(ret != RT_EOK){ - goto BIND_DMA_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); + if(ret != RT_EOK){ + goto BIND_DMA_ERROR; + } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); - if(ret != RT_EOK){ - //release tx channel... - rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); - goto BIND_DMA_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); + if(ret != RT_EOK){ + //release tx channel... + rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); + goto BIND_DMA_ERROR; + } - //spi_control->xfer_mode = XFER_USE_DMA; - spi_control->dma.dma_flag = DMA_BIND_OK; - } + //spi_control->xfer_mode = XFER_USE_DMA; + spi_control->dma.dma_flag = DMA_BIND_OK; + } } else{ BIND_DMA_ERROR: - spi_control->dma.dma_flag = DMA_BIND_ERROR; - //spi_control->xfer_mode = XFER_USE_ISR; + spi_control->dma.dma_flag = DMA_BIND_ERROR; + //spi_control->xfer_mode = XFER_USE_ISR; } @@ -702,80 +702,80 @@ BIND_DMA_ERROR: control_slave = &spi_control->spi_slave; for(i=0;i<plat_data->slave_no;i++){ - spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info)); - if(!spi_slave){ - rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i); - goto error_malloc_slave; - } - rt_memset(spi_slave, 0, sizeof(struct spi_slave_info)); + spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info)); + if(!spi_slave){ + rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i); + goto error_malloc_slave; + } + rt_memset(spi_slave, 0, sizeof(struct spi_slave_info)); - //parse platform data... - spi_slave->id = i; - //bind to the spi control....will easy to find all the data... - spi_slave->control = spi_control; - spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin; - spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level; - rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id); + //parse platform data... + spi_slave->id = i; + //bind to the spi control....will easy to find all the data... + spi_slave->control = spi_control; + spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin; + spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level; + rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id); - *control_slave = spi_slave; - control_slave = &spi_slave->next; + *control_slave = spi_slave; + control_slave = &spi_slave->next; - //register slave dev... - ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave); - if(ret != RT_EOK){ - rt_kprintf("register dev to bus failed...\n"); - goto error_malloc_slave; - } + //register slave dev... + ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave); + if(ret != RT_EOK){ + rt_kprintf("register dev to bus failed...\n"); + goto error_malloc_slave; + } } //request gpio... - spi_slave = spi_control->spi_slave; - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; + spi_slave = spi_control->spi_slave; + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; - ret = gpio_request(spi_slave->plat_slave.cs_pin); - if(ret!=0){ - rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin); - goto error_malloc_slave; - } + ret = gpio_request(spi_slave->plat_slave.cs_pin); + if(ret!=0){ + rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin); + goto error_malloc_slave; + } - PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id, - spi_slave->plat_slave.cs_pin, - spi_slave->plat_slave.actice_level); - spi_slave = next_slave; - } + PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id, + spi_slave->plat_slave.cs_pin, + spi_slave->plat_slave.actice_level); + spi_slave = next_slave; + } - //this will be used in platform exit.. - plat_data->control = spi_control; + //this will be used in platform exit.. + plat_data->control = spi_control; return RT_EOK; error_malloc_slave: - //free the slaveinfo already malloc - spi_slave = spi_control->spi_slave; - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; - gpio_release(spi_slave->plat_slave.cs_pin); - rt_free(spi_slave); - spi_slave = next_slave; - } - //mask isr - rt_hw_interrupt_mask(spi_control->irq); - //release sem .. - rt_sem_detach(&spi_control->xfer_lock); + //free the slaveinfo already malloc + spi_slave = spi_control->spi_slave; + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; + gpio_release(spi_slave->plat_slave.cs_pin); + rt_free(spi_slave); + spi_slave = next_slave; + } + //mask isr + rt_hw_interrupt_mask(spi_control->irq); + //release sem .. + rt_sem_detach(&spi_control->xfer_lock); - //free the control malloc . - rt_free(spi_control); + //free the control malloc . + rt_free(spi_control); - //fixme:unregister spi_bus... + //fixme:unregister spi_bus... error_malloc_bus: - return -RT_ENOMEM; + return -RT_ENOMEM; @@ -793,22 +793,22 @@ int fh_spi_exit(void *priv_data) plat_data = (struct spi_control_platform_data *)priv_data; spi_control = plat_data->control; - spi_slave = spi_control->spi_slave; + spi_slave = spi_control->spi_slave; - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; - gpio_release(spi_slave->plat_slave.cs_pin); - rt_free(spi_slave); - spi_slave = next_slave; - } - //mask isr - rt_hw_interrupt_mask(spi_control->irq); - //release sem .. - rt_sem_detach(&spi_control->xfer_lock); + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; + gpio_release(spi_slave->plat_slave.cs_pin); + rt_free(spi_slave); + spi_slave = next_slave; + } + //mask isr + rt_hw_interrupt_mask(spi_control->irq); + //release sem .. + rt_sem_detach(&spi_control->xfer_lock); - //free the control malloc . - rt_free(spi_control); + //free the control malloc . + rt_free(spi_control); //fixme free all the malloc data ... return 0; @@ -835,20 +835,20 @@ void rt_hw_spi_init(void) } #if(0) -#define TEST_SPI_BUFF_SIZE 0x100 +#define TEST_SPI_BUFF_SIZE 0x100 static rt_uint8_t tx_buf[TEST_SPI_BUFF_SIZE] = {0}; static rt_uint8_t rx_buf[TEST_SPI_BUFF_SIZE] = {0}; int ssi_test(void){ - struct rt_spi_device * rt_spi_device; + struct rt_spi_device * rt_spi_device; - int ret; - rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0"); + int ret; + rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0"); - if(rt_spi_device == RT_NULL) - { - rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0"); - return -RT_ENOSYS; - } + if(rt_spi_device == RT_NULL) + { + rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0"); + return -RT_ENOSYS; + } /* config spi */ { @@ -865,7 +865,7 @@ int ssi_test(void){ ret = rt_memcmp(tx_buf,rx_buf,TEST_SPI_BUFF_SIZE); if(ret != 0){ - rt_kprintf("compare error ..error data %x\n",ret); + rt_kprintf("compare error ..error data %x\n",ret); } rt_kprintf("test done \n"); return 0; diff --git a/bsp/fh8620/drivers/ssi.h b/bsp/fh8620/drivers/ssi.h index 3559729ca3..bad2df8381 100644 --- a/bsp/fh8620/drivers/ssi.h +++ b/bsp/fh8620/drivers/ssi.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef SSI_H_ #define SSI_H_ #include "libraries/inc/fh_driverlib.h" @@ -32,37 +32,37 @@ #include "fh_dma.h" #define SPI_PRIV(drv) ( (struct fh_spi_obj)(drv->priv) ) -#define FH_SPI_SLAVE_MAX_NO 2 +#define FH_SPI_SLAVE_MAX_NO 2 struct spi_controller; //platform use below struct spi_slave_platform_data{ - rt_uint32_t cs_pin; -#define ACTIVE_LOW 1 -#define ACTIVE_HIGH 2 - rt_uint32_t actice_level; + rt_uint32_t cs_pin; +#define ACTIVE_LOW 1 +#define ACTIVE_HIGH 2 + rt_uint32_t actice_level; }; struct spi_control_platform_data{ - rt_uint32_t id; - rt_uint32_t irq; - rt_uint32_t base; - rt_uint32_t max_hz; - rt_uint32_t slave_no; - rt_uint32_t clk_in; - //handshake no... - rt_uint32_t rx_hs_no; - rt_uint32_t tx_hs_no; + rt_uint32_t id; + rt_uint32_t irq; + rt_uint32_t base; + rt_uint32_t max_hz; + rt_uint32_t slave_no; + rt_uint32_t clk_in; + //handshake no... + rt_uint32_t rx_hs_no; + rt_uint32_t tx_hs_no; - char *dma_name; - //isr will be the default... -#define USE_ISR_TRANSFER 0 -#define USE_DMA_TRANSFER 1 - rt_uint32_t transfer_mode; - struct spi_controller *control; - struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO]; + char *dma_name; + //isr will be the default... +#define USE_ISR_TRANSFER 0 +#define USE_DMA_TRANSFER 1 + rt_uint32_t transfer_mode; + struct spi_controller *control; + struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO]; }; @@ -81,15 +81,15 @@ struct spi_slave_info struct spi_dma { - char *dma_name; -#define DMA_BIND_OK 0 -#define DMA_BIND_ERROR 1 - rt_uint32_t dma_flag; + char *dma_name; +#define DMA_BIND_OK 0 +#define DMA_BIND_ERROR 1 + rt_uint32_t dma_flag; //bind to the dma dev.. - rt_uint32_t rx_hs; - rt_uint32_t tx_hs; - rt_uint8_t *rx_dummy_buff; - rt_uint8_t *tx_dummy_buff; + rt_uint32_t rx_hs; + rt_uint32_t tx_hs; + rt_uint8_t *rx_dummy_buff; + rt_uint8_t *tx_dummy_buff; struct rt_dma_device *dma_dev; struct dma_transfer tx_trans; struct dma_transfer rx_trans; @@ -98,28 +98,28 @@ struct spi_dma struct spi_controller { - rt_uint32_t id; - rt_uint32_t irq; - rt_uint32_t base; - rt_uint32_t max_hz; - rt_uint32_t slave_no; - rt_uint32_t clk_in; - //bind to the platform data.... - struct spi_control_platform_data *plat_data; + rt_uint32_t id; + rt_uint32_t irq; + rt_uint32_t base; + rt_uint32_t max_hz; + rt_uint32_t slave_no; + rt_uint32_t clk_in; + //bind to the platform data.... + struct spi_control_platform_data *plat_data; - //rt_uint32_t dma_xfer_flag; + //rt_uint32_t dma_xfer_flag; -#define XFER_USE_ISR 0 -#define XFER_USE_DMA 1 - rt_uint32_t xfer_mode; +#define XFER_USE_ISR 0 +#define XFER_USE_DMA 1 + rt_uint32_t xfer_mode; - struct spi_dma dma; - rt_uint32_t dma_complete_times; + struct spi_dma dma; + rt_uint32_t dma_complete_times; struct rt_spi_bus spi_bus; struct spi_slave_info *spi_slave; struct rt_spi_message* current_message; struct rt_completion transfer_completion; - struct rt_semaphore xfer_lock; + struct rt_semaphore xfer_lock; struct fh_spi_obj obj; rt_uint32_t received_len; rt_uint32_t transfered_len; diff --git a/bsp/fh8620/drivers/trap.c b/bsp/fh8620/drivers/trap.c index 7d81057956..b12004918a 100644 --- a/bsp/fh8620/drivers/trap.c +++ b/bsp/fh8620/drivers/trap.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rthw.h> #include <armv6.h> #include "fh_arch.h" @@ -47,13 +47,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -66,15 +66,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -88,10 +88,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -104,15 +104,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -125,15 +125,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -145,45 +145,45 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { - rt_isr_handler_t isr_func; - rt_uint32_t irqstat_l, irqstat_h, irq; - void *param; + rt_isr_handler_t isr_func; + rt_uint32_t irqstat_l, irqstat_h, irq; + void *param; - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; - irqstat_l = p->IRQ_FINALSTATUS_L; - irqstat_h = p->IRQ_FINALSTATUS_H; - if (irqstat_l) - { - irq = __rt_ffs(irqstat_l) - 1; - } - else if(irqstat_h) - { - irq = __rt_ffs(irqstat_h) - 1 + 32; - } - else - { - rt_kprintf("No interrupt occur\n"); - return; - } + irqstat_l = p->IRQ_FINALSTATUS_L; + irqstat_h = p->IRQ_FINALSTATUS_H; + if (irqstat_l) + { + irq = __rt_ffs(irqstat_l) - 1; + } + else if(irqstat_h) + { + irq = __rt_ffs(irqstat_h) - 1 + 32; + } + else + { + rt_kprintf("No interrupt occur\n"); + return; + } - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; - /* turn to interrupt service routine */ - if(isr_func){ - isr_func(irq, param); - } + /* turn to interrupt service routine */ + if(isr_func){ + isr_func(irq, param); + } #ifdef RT_USING_INTERRUPT_INFO irq_desc[irq].counter ++; #endif @@ -191,7 +191,7 @@ void rt_hw_trap_irq() void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/bsp/fh8620/drivers/uart.c b/bsp/fh8620/drivers/uart.c index 4b264d9206..89df32d753 100644 --- a/bsp/fh8620/drivers/uart.c +++ b/bsp/fh8620/drivers/uart.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <board.h> #include <rtdevice.h> #include "fh_arch.h" @@ -32,35 +32,35 @@ void rt_fh_uart_handler(int vector, void *param) { - int status; - unsigned int ret; - struct fh_uart *uart; - unsigned int reg_status; - rt_device_t dev = (rt_device_t)param; - uart = (struct fh_uart *)dev->user_data; - status = uart_get_iir_status(uart->uart_port); - if (status & UART_IIR_NOINT) - { - return; - } - if(status & UART_IIR_THREMPTY){ - //first close tx isr - uart_disable_irq(uart->uart_port,UART_IER_ETBEI); + int status; + unsigned int ret; + struct fh_uart *uart; + unsigned int reg_status; + rt_device_t dev = (rt_device_t)param; + uart = (struct fh_uart *)dev->user_data; + status = uart_get_iir_status(uart->uart_port); + if (status & UART_IIR_NOINT) + { + return; + } + if(status & UART_IIR_THREMPTY){ + //first close tx isr + uart_disable_irq(uart->uart_port,UART_IER_ETBEI); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE); - } - else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){ - //bug.... - //if no data in rx fifo - reg_status = uart_get_status(uart->uart_port); - if((reg_status & 1<<3) == 0) - ret = uart_getc(uart->uart_port); - } - else{ - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); - } + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE); + } + else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){ + //bug.... + //if no data in rx fifo + reg_status = uart_get_status(uart->uart_port); + if((reg_status & 1<<3) == 0) + ret = uart_getc(uart->uart_port); + } + else{ + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); + } } /** @@ -69,67 +69,67 @@ void rt_fh_uart_handler(int vector, void *param) static rt_err_t fh_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - enum data_bits data_mode; - enum stop_bits stop_mode; - enum parity parity_mode; - struct fh_uart *uart; + int div; + enum data_bits data_mode; + enum stop_bits stop_mode; + enum parity parity_mode; + struct fh_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct fh_uart *)serial->parent.user_data; + uart = (struct fh_uart *)serial->parent.user_data; - switch (cfg->data_bits) - { - case DATA_BITS_8: - data_mode = UART_DATA_BIT8; - break; - case DATA_BITS_7: - data_mode = UART_DATA_BIT7; - break; - case DATA_BITS_6: - data_mode = UART_DATA_BIT6; - break; - case DATA_BITS_5: - data_mode = UART_DATA_BIT5; - break; - default: - data_mode = UART_DATA_BIT8; - break; - } + switch (cfg->data_bits) + { + case DATA_BITS_8: + data_mode = UART_DATA_BIT8; + break; + case DATA_BITS_7: + data_mode = UART_DATA_BIT7; + break; + case DATA_BITS_6: + data_mode = UART_DATA_BIT6; + break; + case DATA_BITS_5: + data_mode = UART_DATA_BIT5; + break; + default: + data_mode = UART_DATA_BIT8; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - stop_mode = UART_STOP_BIT2; - break; - case STOP_BITS_1: - default: - stop_mode = UART_STOP_BIT1; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + stop_mode = UART_STOP_BIT2; + break; + case STOP_BITS_1: + default: + stop_mode = UART_STOP_BIT1; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - parity_mode = UART_PARITY_ODD; - break; - case PARITY_EVEN: - parity_mode = UART_PARITY_EVEN; - break; - case PARITY_NONE: - default: - parity_mode = UART_PARITY_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + parity_mode = UART_PARITY_ODD; + break; + case PARITY_EVEN: + parity_mode = UART_PARITY_EVEN; + break; + case PARITY_NONE: + default: + parity_mode = UART_PARITY_NONE; + break; + } uart_disable_irq(uart->uart_port, UART_IER_ERBFI); - uart_configure(uart->uart_port, data_mode, - stop_mode, parity_mode, - cfg->baud_rate, UART_CLOCK_FREQ); + uart_configure(uart->uart_port, data_mode, + stop_mode, parity_mode, + cfg->baud_rate, UART_CLOCK_FREQ); - uart_enable_irq(uart->uart_port, UART_IER_ERBFI); + uart_enable_irq(uart->uart_port, UART_IER_ERBFI); return RT_EOK; } @@ -146,13 +146,13 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); - uart_disable_irq(uart->uart_port,UART_IER_ERBFI); + rt_hw_interrupt_mask(uart->irq); + uart_disable_irq(uart->uart_port,UART_IER_ERBFI); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); - uart_enable_irq(uart->uart_port,UART_IER_ERBFI); + rt_hw_interrupt_umask(uart->irq); + uart_enable_irq(uart->uart_port,UART_IER_ERBFI); break; } @@ -161,33 +161,33 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial, static int fh_uart_putc(struct rt_serial_device *serial, char c) { - struct fh_uart *uart = serial->parent.user_data; - unsigned int ret; - ret = uart_get_status(uart->uart_port); - if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){ - //RT_DEVICE_FLAG_INT_TX + struct fh_uart *uart = serial->parent.user_data; + unsigned int ret; + ret = uart_get_status(uart->uart_port); + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){ + //RT_DEVICE_FLAG_INT_TX - if(c == '\n'){ - fh_uart_putc(serial,'\r'); - } - if(ret & UART_USR_TFNF){ - uart_putc(uart->uart_port, c); - return 1; - } - //open tx isr here.. - uart_enable_irq(uart->uart_port,UART_IER_ETBEI); - return -1; - } - //poll mode - else{ + if(c == '\n'){ + fh_uart_putc(serial,'\r'); + } + if(ret & UART_USR_TFNF){ + uart_putc(uart->uart_port, c); + return 1; + } + //open tx isr here.. + uart_enable_irq(uart->uart_port,UART_IER_ETBEI); + return -1; + } + //poll mode + else{ - while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF)) - ; - uart_putc(uart->uart_port, c); - return 1; + while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF)) + ; + uart_putc(uart->uart_port, c); + return 1; - } + } @@ -196,16 +196,16 @@ static int fh_uart_putc(struct rt_serial_device *serial, char c) static int fh_uart_getc(struct rt_serial_device *serial) { int result; - struct fh_uart *uart = serial->parent.user_data; + struct fh_uart *uart = serial->parent.user_data; - if (uart_is_rx_ready(uart->uart_port)) - { - result = uart_getc(uart->uart_port); - } - else - { - result = -1; - } + if (uart_is_rx_ready(uart->uart_port)) + { + result = uart_getc(uart->uart_port); + } + else + { + result = -1; + } return result; } @@ -222,8 +222,8 @@ static const struct rt_uart_ops fh_uart_ops = #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct fh_uart uart0 = { - (uart *)UART0_REG_BASE, - UART0_IRQn + (uart *)UART0_REG_BASE, + UART0_IRQn }; #endif @@ -231,8 +231,8 @@ struct fh_uart uart0 = { #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct fh_uart uart1 = { - (uart *)UART1_REG_BASE, - UART1_IRQn + (uart *)UART1_REG_BASE, + UART1_IRQn }; #endif @@ -245,45 +245,45 @@ struct fh_uart uart1 = { */ void rt_hw_uart_init(void) { - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #if defined(RT_USING_UART0) #if(0) - serial0.ops = &fh_uart_ops; - serial0.config = config; + serial0.ops = &fh_uart_ops; + serial0.config = config; - /* register vcom device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE, - &uart0); - rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, - (void *)&(serial0.parent), "UART0"); - rt_hw_interrupt_umask(uart0.irq); + /* register vcom device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE, + &uart0); + rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, + (void *)&(serial0.parent), "UART0"); + rt_hw_interrupt_umask(uart0.irq); #endif - serial0.ops = &fh_uart_ops; - serial0.config = config; + serial0.ops = &fh_uart_ops; + serial0.config = config; - /* register vcom device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , - &uart0); - rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, - (void *)&(serial0.parent), "UART0"); - rt_hw_interrupt_umask(uart0.irq); + /* register vcom device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , + &uart0); + rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, + (void *)&(serial0.parent), "UART0"); + rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART1) - serial1.ops = &fh_uart_ops; - serial1.config = config; + serial1.ops = &fh_uart_ops; + serial1.config = config; - /* register vcom device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , - &uart1); - rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler, - (void *)&(serial1.parent), "UART1"); - rt_hw_interrupt_umask(uart1.irq); + /* register vcom device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , + &uart1); + rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler, + (void *)&(serial1.parent), "UART1"); + rt_hw_interrupt_umask(uart1.irq); #endif diff --git a/bsp/fh8620/drivers/uart.h b/bsp/fh8620/drivers/uart.h index d4459f02f8..c7af24523b 100644 --- a/bsp/fh8620/drivers/uart.h +++ b/bsp/fh8620/drivers/uart.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef UART_H_ #define UART_H_ diff --git a/bsp/fh8620/drivers/wdt.c b/bsp/fh8620/drivers/wdt.c index 1d67007a6a..f7f292df86 100644 --- a/bsp/fh8620/drivers/wdt.c +++ b/bsp/fh8620/drivers/wdt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "fh_def.h" #include "wdt.h" #include "interrupt.h" diff --git a/bsp/fh8620/drivers/wdt.h b/bsp/fh8620/drivers/wdt.h index 768a2e0739..71673d24aa 100644 --- a/bsp/fh8620/drivers/wdt.h +++ b/bsp/fh8620/drivers/wdt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef WDT_H_ #define WDT_H_ diff --git a/bsp/fh8620/libraries/driverlib/fh_gpio.c b/bsp/fh8620/libraries/driverlib/fh_gpio.c index e3e58f9a1f..7c39386968 100644 --- a/bsp/fh8620/libraries/driverlib/fh_gpio.c +++ b/bsp/fh8620/libraries/driverlib/fh_gpio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,10 +18,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - -
\ No newline at end of file + + diff --git a/bsp/fh8620/libraries/driverlib/fh_i2c.c b/bsp/fh8620/libraries/driverlib/fh_i2c.c index 661703e71c..cc91561b9f 100644 --- a/bsp/fh8620/libraries/driverlib/fh_i2c.c +++ b/bsp/fh8620/libraries/driverlib/fh_i2c.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "inc/fh_driverlib.h" int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj) diff --git a/bsp/fh8620/libraries/driverlib/fh_ictl.c b/bsp/fh8620/libraries/driverlib/fh_ictl.c index a53c8dba34..10edbb27ff 100644 --- a/bsp/fh8620/libraries/driverlib/fh_ictl.c +++ b/bsp/fh8620/libraries/driverlib/fh_ictl.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,25 +18,25 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "inc/fh_driverlib.h" void ictl_close_all_isr(fh_intc *p){ - if(p){ - //enable all interrupts - p->IRQ_EN_L = 0xffffffff; - p->IRQ_EN_H = 0xffffffff; - //mask all interrupts - p->IRQ_MASK_L = 0xffffffff; - p->IRQ_MASK_H = 0xffffffff; - } + if(p){ + //enable all interrupts + p->IRQ_EN_L = 0xffffffff; + p->IRQ_EN_H = 0xffffffff; + //mask all interrupts + p->IRQ_MASK_L = 0xffffffff; + p->IRQ_MASK_H = 0xffffffff; + } } @@ -44,13 +44,13 @@ void ictl_close_all_isr(fh_intc *p){ void ictl_mask_isr(fh_intc *p,int irq){ - if(p){ + if(p){ - if (irq < 32) - p->IRQ_MASK_L |= (1 << irq); - else - p->IRQ_MASK_H |= (1 << (irq - 32)); - } + if (irq < 32) + p->IRQ_MASK_L |= (1 << irq); + else + p->IRQ_MASK_H |= (1 << (irq - 32)); + } } @@ -58,12 +58,12 @@ void ictl_mask_isr(fh_intc *p,int irq){ void ictl_unmask_isr(fh_intc *p,int irq){ - if(p){ - if (irq < 32) - p->IRQ_MASK_L &= ~(1 << irq); - else - p->IRQ_MASK_H &= ~(1 << (irq - 32)); + if(p){ + if (irq < 32) + p->IRQ_MASK_L &= ~(1 << irq); + else + p->IRQ_MASK_H &= ~(1 << (irq - 32)); - } + } } diff --git a/bsp/fh8620/libraries/driverlib/fh_mmc.c b/bsp/fh8620/libraries/driverlib/fh_mmc.c index 5995e634fa..0b644d29e5 100644 --- a/bsp/fh8620/libraries/driverlib/fh_mmc.c +++ b/bsp/fh8620/libraries/driverlib/fh_mmc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_pwm.c b/bsp/fh8620/libraries/driverlib/fh_pwm.c index af19110a46..7b71e78f2b 100644 --- a/bsp/fh8620/libraries/driverlib/fh_pwm.c +++ b/bsp/fh8620/libraries/driverlib/fh_pwm.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_sdio.c b/bsp/fh8620/libraries/driverlib/fh_sdio.c index 8c9e69e07d..edc4151068 100644 --- a/bsp/fh8620/libraries/driverlib/fh_sdio.c +++ b/bsp/fh8620/libraries/driverlib/fh_sdio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -34,15 +34,15 @@ #define SDC_USE_IDMA #define INSTRUCTIONS_PER_USEC 1000 -#define CMD_TIMEOUT_USEC 100000 -#define DATA_READY_TIMEOUT_USEC 200000 +#define CMD_TIMEOUT_USEC 100000 +#define DATA_READY_TIMEOUT_USEC 200000 #define DMA_TRANSFER_TIMEOUT_TICKS 300 #define DATA_TRANSFER_OVER_TIMEOUT_USEC 1000 #define ACMD41_RETRY_COUNT 1000//100000 -#define CIU_CLK 50000//25000//25000 //27MHz -#define MMC_FOD_VALUE 125 /* 125 KHz */ -#define NORM_FOD_VALUE 25000//5000//25000 /* 25 MHz */ +#define CIU_CLK 50000//25000//25000 //27MHz +#define MMC_FOD_VALUE 125 /* 125 KHz */ +#define NORM_FOD_VALUE 25000//5000//25000 /* 25 MHz */ #define MMC_FOD_DIVIDER_VALUE (((CIU_CLK+MMC_FOD_VALUE*2-1)/(MMC_FOD_VALUE*2))) #ifdef SDCARD_CLK_DIVIDER #define ONE_BIT_BUS_FREQ SDCARD_CLK_DIVIDER @@ -56,1118 +56,1118 @@ static sdc_t sdc_array[2]; static void plat_loop(unsigned int macrosecond) { - unsigned int clk; - - while (macrosecond-- > 0) { - for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--); - } + unsigned int clk; + + while (macrosecond-- > 0) { + for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--); + } } static int synopmob_execute_command(unsigned int base, unsigned int cmd_register, unsigned int arg_register) { - unsigned int retries = CMD_TIMEOUT_USEC; + unsigned int retries = CMD_TIMEOUT_USEC; + + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME + synopmob_set_register(base+CMDARG, arg_register); + synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/)); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME - synopmob_set_register(base+CMDARG, arg_register); - synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/)); + while (retries-- > 0) { + if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/)) + return 0; + plat_loop(1); + } - while (retries-- > 0) { - if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/)) - return 0; - plat_loop(1); - } - - return ERRCMDRETRIESOVER; + return ERRCMDRETRIESOVER; } static int synopmob_wait_command_done(unsigned int base, unsigned int* inst, unsigned int flag) { - unsigned int retries = CMD_TIMEOUT_USEC; - unsigned int sts; + unsigned int retries = CMD_TIMEOUT_USEC; + unsigned int sts; - while (retries-- > 0) { - sts = synopmob_read_register(base+RINTSTS); - if (sts && ((sts & flag) == flag) ) { - *inst = sts; - return 0; - } - plat_loop(1); - } - return ERRCMDRETRIESOVER; + while (retries-- > 0) { + sts = synopmob_read_register(base+RINTSTS); + if (sts && ((sts & flag) == flag) ) { + *inst = sts; + return 0; + } + plat_loop(1); + } + return ERRCMDRETRIESOVER; } static int synopmob_wait_data_ready(unsigned int base) { - unsigned int retries = DATA_READY_TIMEOUT_USEC; + unsigned int retries = DATA_READY_TIMEOUT_USEC; + + while (retries-- > 0) { + if (!((synopmob_read_register(base+STATUS)) & 0x00000200)) { + return 0; + } - while (retries-- > 0) { - if (!((synopmob_read_register(base+STATUS)) & 0x00000200)) { - return 0; - } - - plat_loop(1); - } - return ERRDATANOTREADY; + plat_loop(1); + } + return ERRDATANOTREADY; } static int synopmob_handle_standard_rinsts(unsigned int raw_int_stat) { - int error_status = 0; - - if ( raw_int_stat & INTMASK_ERROR) { - if (raw_int_stat & INTMSK_RESP_ERR) { - error_status = ERRRESPRECEP; - } - if (raw_int_stat & INTMSK_RCRC) { - error_status = ERRRESPCRC; - } - if (raw_int_stat & INTMSK_DCRC) { - error_status = ERRDCRC; - } - if (raw_int_stat & INTMSK_RTO) { - error_status = ERRRESPTIMEOUT; - } - if (raw_int_stat & INTMSK_DTO) { - error_status = ERRDRTIMEOUT; - } - if (raw_int_stat & INTMSK_HTO) { - error_status = ERRUNDERWRITE; - } - if (raw_int_stat & INTMSK_FRUN) { - error_status = ERROVERREAD; - } - if (raw_int_stat & INTMSK_HLE) { - error_status = ERRHLE; - } - if (raw_int_stat & INTMSK_SBE) { - error_status = ERRSTARTBIT; - } - if (raw_int_stat & INTMSK_EBE) { - error_status = ERRENDBITERR; - } - } + int error_status = 0; + + if ( raw_int_stat & INTMASK_ERROR) { + if (raw_int_stat & INTMSK_RESP_ERR) { + error_status = ERRRESPRECEP; + } + if (raw_int_stat & INTMSK_RCRC) { + error_status = ERRRESPCRC; + } + if (raw_int_stat & INTMSK_DCRC) { + error_status = ERRDCRC; + } + if (raw_int_stat & INTMSK_RTO) { + error_status = ERRRESPTIMEOUT; + } + if (raw_int_stat & INTMSK_DTO) { + error_status = ERRDRTIMEOUT; + } + if (raw_int_stat & INTMSK_HTO) { + error_status = ERRUNDERWRITE; + } + if (raw_int_stat & INTMSK_FRUN) { + error_status = ERROVERREAD; + } + if (raw_int_stat & INTMSK_HLE) { + error_status = ERRHLE; + } + if (raw_int_stat & INTMSK_SBE) { + error_status = ERRSTARTBIT; + } + if (raw_int_stat & INTMSK_EBE) { + error_status = ERRENDBITERR; + } + } //SDIO_PRINTF("------- %s, line %d raw_int_stat = %08x-------\n", __FUNCTION__, __LINE__, raw_int_stat); - return error_status; + return error_status; } static int synopmob_check_r1_resp(unsigned int the_response) { - int retval = 0; - - if (the_response & R1CS_ERROR_OCCURED_MAP) { - if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) { - retval = ERRADDRESSRANGE; - } else if (the_response & R1CS_ADDRESS_MISALIGN) { - retval = ERRADDRESSMISALIGN; - } else if (the_response & R1CS_BLOCK_LEN_ERR) { - retval = ERRBLOCKLEN; - } else if (the_response & R1CS_ERASE_SEQ_ERR) { - retval = ERRERASESEQERR; - } else if (the_response & R1CS_ERASE_PARAM) { - retval = ERRERASEPARAM; - } else if (the_response & R1CS_WP_VIOLATION) { - retval = ERRPROT; - } else if (the_response & R1CS_CARD_IS_LOCKED) { - retval = ERRCARDLOCKED; - } else if (the_response & R1CS_LCK_UNLCK_FAILED) { - retval = ERRCARDLOCKED; - } else if (the_response & R1CS_COM_CRC_ERROR) { - retval = ERRCRC; - } else if (the_response & R1CS_ILLEGAL_COMMAND) { - retval = ERRILLEGALCOMMAND; - } else if (the_response & R1CS_CARD_ECC_FAILED) { - retval = ERRECCFAILED; - } else if (the_response & R1CS_CC_ERROR) { - retval = ERRCCERR; - } else if (the_response & R1CS_ERROR) { - retval = ERRUNKNOWN; - } else if (the_response & R1CS_UNDERRUN) { - retval = ERRUNDERRUN; - } else if (the_response & R1CS_OVERRUN) { - retval = ERROVERRUN; - } else if (the_response & R1CS_CSD_OVERWRITE) { - retval = ERRCSDOVERWRITE; - } else if (the_response & R1CS_WP_ERASE_SKIP) { - retval = ERRPROT; - } else if (the_response & R1CS_ERASE_RESET) { - retval = ERRERASERESET; - } else if (the_response & R1CS_SWITCH_ERROR) { - retval = ERRFSMSTATE; - } - } - - return retval; + int retval = 0; + + if (the_response & R1CS_ERROR_OCCURED_MAP) { + if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) { + retval = ERRADDRESSRANGE; + } else if (the_response & R1CS_ADDRESS_MISALIGN) { + retval = ERRADDRESSMISALIGN; + } else if (the_response & R1CS_BLOCK_LEN_ERR) { + retval = ERRBLOCKLEN; + } else if (the_response & R1CS_ERASE_SEQ_ERR) { + retval = ERRERASESEQERR; + } else if (the_response & R1CS_ERASE_PARAM) { + retval = ERRERASEPARAM; + } else if (the_response & R1CS_WP_VIOLATION) { + retval = ERRPROT; + } else if (the_response & R1CS_CARD_IS_LOCKED) { + retval = ERRCARDLOCKED; + } else if (the_response & R1CS_LCK_UNLCK_FAILED) { + retval = ERRCARDLOCKED; + } else if (the_response & R1CS_COM_CRC_ERROR) { + retval = ERRCRC; + } else if (the_response & R1CS_ILLEGAL_COMMAND) { + retval = ERRILLEGALCOMMAND; + } else if (the_response & R1CS_CARD_ECC_FAILED) { + retval = ERRECCFAILED; + } else if (the_response & R1CS_CC_ERROR) { + retval = ERRCCERR; + } else if (the_response & R1CS_ERROR) { + retval = ERRUNKNOWN; + } else if (the_response & R1CS_UNDERRUN) { + retval = ERRUNDERRUN; + } else if (the_response & R1CS_OVERRUN) { + retval = ERROVERRUN; + } else if (the_response & R1CS_CSD_OVERWRITE) { + retval = ERRCSDOVERWRITE; + } else if (the_response & R1CS_WP_ERASE_SKIP) { + retval = ERRPROT; + } else if (the_response & R1CS_ERASE_RESET) { + retval = ERRERASERESET; + } else if (the_response & R1CS_SWITCH_ERROR) { + retval = ERRFSMSTATE; + } + } + + return retval; } static int synopmob_check_r5_resp(unsigned int the_resp) { - int ret = 0; - - if (the_resp & R5_IO_ERR_BITS) { - if (the_resp & R5_IO_CRC_ERR) { - ret = ERRDCRC; - } else if (the_resp & R5_IO_BAD_CMD) { - ret = ERRILLEGALCOMMAND; - } else if (the_resp & R5_IO_GEN_ERR) { - ret = ERRUNKNOWN; - } else if (the_resp & R5_IO_FUNC_ERR) { - ret = ERRBADFUNC; - } else if (the_resp & R5_IO_OUT_RANGE) { - ret = ERRADDRESSRANGE; - } - } - - return ret; + int ret = 0; + + if (the_resp & R5_IO_ERR_BITS) { + if (the_resp & R5_IO_CRC_ERR) { + ret = ERRDCRC; + } else if (the_resp & R5_IO_BAD_CMD) { + ret = ERRILLEGALCOMMAND; + } else if (the_resp & R5_IO_GEN_ERR) { + ret = ERRUNKNOWN; + } else if (the_resp & R5_IO_FUNC_ERR) { + ret = ERRBADFUNC; + } else if (the_resp & R5_IO_OUT_RANGE) { + ret = ERRADDRESSRANGE; + } + } + + return ret; } static int sd_send_cmd0(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; - ret = synopmob_execute_command(base, 0x4000, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - return synopmob_handle_standard_rinsts(intst); - } - } + ret = synopmob_execute_command(base, 0x4000, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + return synopmob_handle_standard_rinsts(intst); + } + } - return ret; + return ret; } static int sd_send_cmd2(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; - ret = synopmob_execute_command(base, 0xC2, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - return synopmob_handle_standard_rinsts(intst); - } - } + ret = synopmob_execute_command(base, 0xC2, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + return synopmob_handle_standard_rinsts(intst); + } + } - return ret; + return ret; } static int sd_send_cmd3(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int resp; - unsigned int base = sdc->ip_base; + int ret; + unsigned int intst; + unsigned int resp; + unsigned int base = sdc->ip_base; - ret = synopmob_execute_command(base, 0x43, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - resp = synopmob_read_register(base+RESP0); - sdc->rca = resp >> 16; - resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22); - return synopmob_check_r1_resp(resp); - } - } - } + ret = synopmob_execute_command(base, 0x43, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + resp = synopmob_read_register(base+RESP0); + sdc->rca = resp >> 16; + resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22); + return synopmob_check_r1_resp(resp); + } + } + } - return ret; + return ret; } static int sd_send_cmd_r1(sdc_t* sdc, unsigned int cmd, unsigned int arg, unsigned int buzy) { - int ret; - unsigned int intst; - unsigned int resp; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, cmd, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (buzy && !ret) { - ret = synopmob_wait_data_ready(base); - } - } - } - } + int ret; + unsigned int intst; + unsigned int resp; + unsigned int base = sdc->ip_base; - return ret; + ret = synopmob_execute_command(base, cmd, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (buzy && !ret) { + ret = synopmob_wait_data_ready(base); + } + } + } + } + + return ret; } static int sd_send_cmd7(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1); + return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1); } static int sd_send_uncmd7(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; - ret = synopmob_execute_command(base, 0x7, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - } - } + ret = synopmob_execute_command(base, 0x7, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + } + } - return ret; + return ret; } static int sd_send_cmd16(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x50, 512, 0); + return sd_send_cmd_r1(sdc, 0x50, 512, 0); } static int sd_send_cmd55(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0); + return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0); } static int sd_send_acmd6(sdc_t* sdc, unsigned int bitwidth) { - unsigned int cmd_arg; - int ret; - unsigned int base = sdc->ip_base; + unsigned int cmd_arg; + int ret; + unsigned int base = sdc->ip_base; - ret = sd_send_cmd55(sdc); - if (!ret) { - cmd_arg = 0; //default to 1bit mode - if (bitwidth == 4) { - cmd_arg = 2; // 4bit mode - } - ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0); - if (!ret) { - if (bitwidth == 4) { - synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); - } - else { - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - } - } - } + ret = sd_send_cmd55(sdc); + if (!ret) { + cmd_arg = 0; //default to 1bit mode + if (bitwidth == 4) { + cmd_arg = 2; // 4bit mode + } + ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0); + if (!ret) { + if (bitwidth == 4) { + synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); + } + else { + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + } + } + } - return ret; + return ret; } #ifdef SDC_USE_IDMA static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer) { - sdc_t* sdc = (sdc_t*)handle; - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int cmd; - unsigned int multi = 0; - unsigned int base = sdc->ip_base; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; + sdc_t* sdc = (sdc_t*)handle; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int cmd; + unsigned int multi = 0; + unsigned int base = sdc->ip_base; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + + // valid check + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } + if (!num || num > 16) { + return ERRNOTSUPPORTED; + } + if (blk + num > sdc->sectors) { + return ERRADDRESSRANGE; + } + + if ( rw ) { + flush_dcache_range((unsigned long)buffer, num << 9); + } + else { + // to avoid memset bug? + inv_dcache_range((unsigned long)buffer, num << 9); + } + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } - // valid check - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - if (!num || num > 16) { - return ERRNOTSUPPORTED; - } - if (blk + num > sdc->sectors) { - return ERRADDRESSRANGE; - } + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - if ( rw ) { - flush_dcache_range((unsigned long)buffer, num << 9); - } - else { - // to avoid memset bug? - inv_dcache_range((unsigned long)buffer, num << 9); + cmd = 0x2658; // write + if ( !rw ) { + cmd = 0x2251; //read + } + //if (num > 1) { + if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode. + cmd++; + multi++; + } + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. } + num <<= 9; - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } + pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; + pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); + pDmaDesc->desc2 = (unsigned int)buffer; + flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST + synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + ret = synopmob_execute_command(base, cmd, blk); + if ( !ret ) { + ret = ERRIDMA; + synopmob_set_bits(base+CTRL, INT_ENABLE); + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } - cmd = 0x2658; // write - if ( !rw ) { - cmd = 0x2251; //read - } - //if (num > 1) { - if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode. - cmd++; - multi++; - } - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - } - num <<= 9; - - pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; - pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); - pDmaDesc->desc2 = (unsigned int)buffer; - flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST - synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, blk); - if ( !ret ) { - ret = ERRIDMA; - synopmob_set_bits(base+CTRL, INT_ENABLE); - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } + if (ret) { + char* op = "read"; + if (rw) + op = "write"; - if (ret) { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret); - } + SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret); + } - synopmob_clear_bits(base+CTRL, INT_ENABLE); - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_clear_bits(base+CTRL, INT_ENABLE); + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); - synopmob_set_register(base + RINTSTS, 0xfffe); + synopmob_set_register(base + RINTSTS, 0xfffe); - if ( !ret && rw) { - ret = synopmob_wait_data_ready(base); - } + if ( !ret && rw) { + ret = synopmob_wait_data_ready(base); + } - if (!ret && multi ) { //send STOP_TRANSACTION command - ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); - } + if (!ret && multi ) { //send STOP_TRANSACTION command + ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); + } + + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buffer, num); + } - rt_sem_release(sdc->mutex); - - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buffer, num); - } - - return ret; + return ret; } #else //no IDMA static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer) { - sdc_t* sdc = (sdc_t*)handle; - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int entries; - unsigned int cmd; - unsigned int multi = 0; - unsigned int base = sdc->ip_base; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; + sdc_t* sdc = (sdc_t*)handle; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int entries; + unsigned int cmd; + unsigned int multi = 0; + unsigned int base = sdc->ip_base; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; - // valid check - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - if (!num || num > 16) { - return ERRNOTSUPPORTED; - } - if (blk + num > sdc->sectors) { - return ERRADDRESSRANGE; - } + // valid check + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } + if (!num || num > 16) { + return ERRNOTSUPPORTED; + } + if (blk + num > sdc->sectors) { + return ERRADDRESSRANGE; + } - if ( rw ) { - flush_dcache_range((unsigned long)buffer, num << 9); - } - else { - // to avoid memset bug? - inv_dcache_range((unsigned long)buffer, num << 9); + if ( rw ) { + flush_dcache_range((unsigned long)buffer, num << 9); + } + else { + // to avoid memset bug? + inv_dcache_range((unsigned long)buffer, num << 9); } - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + cmd = 0x2658; // write + if ( !rw ) { + cmd = 0x2251; //read + } + if (num > 1) { + cmd++; + multi++; + } + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. + } + num <<= 9; - cmd = 0x2658; // write - if ( !rw ) { - cmd = 0x2251; //read - } - if (num > 1) { - cmd++; - multi++; - } - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - } - num <<= 9; - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, num); - - ret = synopmob_execute_command(base, cmd, blk); - if ( !ret ) { - while (1) { - ret = synopmob_wait_command_done(base, &intsts, 0); - if (ret) - break; + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, num); - ret = synopmob_handle_standard_rinsts(intsts); - if (ret) - break; + ret = synopmob_execute_command(base, cmd, blk); + if ( !ret ) { + while (1) { + ret = synopmob_wait_command_done(base, &intsts, 0); + if (ret) + break; - if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){ - while (num > 0 ) { - entries = synopmob_read_register(base + STATUS); - if (!GET_FIFO_COUNT(entries)) - break; - *((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT); - buffer += 4; - num -= 4; - } - } - - if (rw && ( intsts & INTMSK_TXDR ) ) { - while (num > 0) { - entries = synopmob_read_register(base+STATUS); - if ( entries & 8 ) { //FIFO is full - break; - } - synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer)); - buffer += 4; - num -= 4; - } - } - - if ( intsts & INTMSK_DAT_OVER ) { - break; - } + ret = synopmob_handle_standard_rinsts(intsts); + if (ret) + break; - if (intsts & INTMSK_CMD_DONE) { - entries = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(entries); - if (ret) { - break; - } - } + if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){ + while (num > 0 ) { + entries = synopmob_read_register(base + STATUS); + if (!GET_FIFO_COUNT(entries)) + break; + *((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT); + buffer += 4; + num -= 4; + } + } - synopmob_set_register(base+RINTSTS, intsts); //write to clear - intsts = 0; - } - - if (intsts) { - synopmob_set_register(base+RINTSTS, intsts); //write to clear - } - } + if (rw && ( intsts & INTMSK_TXDR ) ) { + while (num > 0) { + entries = synopmob_read_register(base+STATUS); + if ( entries & 8 ) { //FIFO is full + break; + } + synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer)); + buffer += 4; + num -= 4; + } + } - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - synopmob_set_register(base + RINTSTS, 0xfffe); + if ( intsts & INTMSK_DAT_OVER ) { + break; + } - if ( !ret && rw) { - ret = synopmob_wait_data_ready(base); - } + if (intsts & INTMSK_CMD_DONE) { + entries = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(entries); + if (ret) { + break; + } + } - if (!ret && multi ) { //send STOP_TRANSACTION command - ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); - } + synopmob_set_register(base+RINTSTS, intsts); //write to clear + intsts = 0; + } + + if (intsts) { + synopmob_set_register(base+RINTSTS, intsts); //write to clear + } + } + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + synopmob_set_register(base + RINTSTS, 0xfffe); + + if ( !ret && rw) { + ret = synopmob_wait_data_ready(base); + } + + if (!ret && multi ) { //send STOP_TRANSACTION command + ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); + } + + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buffer, num); + } - rt_sem_release(sdc->mutex); - - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buffer, num); - } - - return ret; + return ret; } #endif //SDC_USE_IDMA int sdc_write_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer) { - return sdc_read_write_block(handle, 1, blk, num, buffer); + return sdc_read_write_block(handle, 1, blk, num, buffer); } int sdc_read_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer) { - return sdc_read_write_block(handle, 0, blk, num, buffer); + return sdc_read_write_block(handle, 0, blk, num, buffer); } int sdc_erase_block(HSDC handle, unsigned int blk, unsigned int num) { - int ret; - sdc_t* sdc = (sdc_t*)handle; - - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - num = ((num-1)<<9) + blk; - } - else { - num = blk + num - 1; - } - - ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32 - if (!ret) { - ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33 - if (!ret) { - ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38 - } - } + int ret; + sdc_t* sdc = (sdc_t*)handle; - return ret; + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. + num = ((num-1)<<9) + blk; + } + else { + num = blk + num - 1; + } + + ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32 + if (!ret) { + ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33 + if (!ret) { + ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38 + } + } + + return ret; } int sdc_get_sector_num(HSDC handle) { - return ((sdc_t*)handle)->sectors; + return ((sdc_t*)handle)->sectors; } static int sd_send_cmd9(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int resp0; - unsigned int resp1; - unsigned int resp2; - unsigned int resp3; - unsigned int base = sdc->ip_base; - unsigned int C_SIZE; - unsigned int C_SIZE_MULT; - unsigned int READ_BL_LEN; + int ret; + unsigned int intst; + unsigned int resp0; + unsigned int resp1; + unsigned int resp2; + unsigned int resp3; + unsigned int base = sdc->ip_base; + unsigned int C_SIZE; + unsigned int C_SIZE_MULT; + unsigned int READ_BL_LEN; + + ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0); + sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1); + sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2); + sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3); - ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0); - sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1); - sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2); - sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3); - - if ((resp3>>30) == 0) { //CSD version 1.0 - C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2); - C_SIZE_MULT = ((resp1 >> 15) & 0x07); - READ_BL_LEN = ((resp2 >> 16) & 0xf); - sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9); - } - else { //CSD version 2.0 - sdc->sectors = (((resp1 >> 16)+1)<<10); - } - } - } - } + if ((resp3>>30) == 0) { //CSD version 1.0 + C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2); + C_SIZE_MULT = ((resp1 >> 15) & 0x07); + READ_BL_LEN = ((resp2 >> 16) & 0xf); + sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9); + } + else { //CSD version 2.0 + sdc->sectors = (((resp1 >> 16)+1)<<10); + } + } + } + } - return ret; + return ret; } static int sd_send_cmd5(sdc_t* sdc, unsigned int arg, unsigned int* resp) { - unsigned int cmd_reg = 0x45; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; + unsigned int cmd_reg = 0x45; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - } - } - } - - return ret; + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + } + } + } + + return ret; } static int sd_send_cmd8(sdc_t* sdc) { - int ret; - unsigned int cmd_reg = 0x48; - unsigned int intst; - unsigned int err = 0; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, cmd_reg, 0x000001A5); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - err |= synopmob_handle_standard_rinsts(intst); - if (intst & INTMSK_CMD_DONE) { - break; - } - } - } - } + int ret; + unsigned int cmd_reg = 0x48; + unsigned int intst; + unsigned int err = 0; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, cmd_reg, 0x000001A5); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + err |= synopmob_handle_standard_rinsts(intst); + if (intst & INTMSK_CMD_DONE) { + break; + } + } + } + } - return err; + return err; } static int sd_send_acmd41(sdc_t* sdc, int* hcs) { - unsigned int cmd_reg = 0x69; - unsigned int resp; - int ret = 0; - unsigned int count = ACMD41_RETRY_COUNT; - unsigned int cmd_arg = 0xff8000; - unsigned int base = sdc->ip_base; + unsigned int cmd_reg = 0x69; + unsigned int resp; + int ret = 0; + unsigned int count = ACMD41_RETRY_COUNT; + unsigned int cmd_arg = 0xff8000; + unsigned int base = sdc->ip_base; + + if (*hcs) { + cmd_arg |= (1<<30); + } + while ( count > 0) { + SDC_WHERE(); + ret = sd_send_cmd55(sdc); + if (ret) + break; - if (*hcs) { - cmd_arg |= (1<<30); - } - while ( count > 0) { - SDC_WHERE(); - ret = sd_send_cmd55(sdc); - if (ret) - break; + SDC_WHERE(); + ret = synopmob_execute_command(base, cmd_reg, cmd_arg); + if (ret) + break; - SDC_WHERE(); - ret = synopmob_execute_command(base, cmd_reg, cmd_arg); - if (ret) - break; + SDC_WHERE(); + ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE); + if ( ret ) + break; - SDC_WHERE(); - ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE); - if ( ret ) - break; + SDC_WHERE(); + synopmob_set_register(base+RINTSTS, resp); + ret = synopmob_handle_standard_rinsts(resp); + if (!ret) { + SDC_WHERE(); + resp = synopmob_read_register(base+RESP0); + if (resp & 0x80000000) { //card is ready. + SDC_WHERE(); + if ( !(resp & (1<<30)) ) { + SDC_WHERE(); + *hcs = 0; + } + if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage + ret = ERRHARDWARE; + } + break; + } + } - SDC_WHERE(); - synopmob_set_register(base+RINTSTS, resp); - ret = synopmob_handle_standard_rinsts(resp); - if (!ret) { - SDC_WHERE(); - resp = synopmob_read_register(base+RESP0); - if (resp & 0x80000000) { //card is ready. - SDC_WHERE(); - if ( !(resp & (1<<30)) ) { - SDC_WHERE(); - *hcs = 0; - } - if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage - ret = ERRHARDWARE; - } - break; - } - } + --count; + plat_loop(1); + } - --count; - plat_loop(1); - } + if (!count) + ret = ERRACMD41TIMEOUT; - if (!count) - ret = ERRACMD41TIMEOUT; - - return ret; + return ret; } static int sd_send_acmd51(sdc_t* sdc) //Send SCR { - unsigned int cmd_reg = 0x2273; - unsigned int resp; - int ret; - unsigned int intst = 0; - unsigned int entries; - int count = 1; - unsigned int base = sdc->ip_base; + unsigned int cmd_reg = 0x2273; + unsigned int resp; + int ret; + unsigned int intst = 0; + unsigned int entries; + int count = 1; + unsigned int base = sdc->ip_base; - ret = sd_send_cmd55(sdc); - if (!ret) { - synopmob_set_register(base+BLKSIZ, 8); - synopmob_set_register(base+BYTCNT, 8); - ret = synopmob_execute_command(base, cmd_reg, 0); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (ret) { - break; - } + ret = sd_send_cmd55(sdc); + if (!ret) { + synopmob_set_register(base+BLKSIZ, 8); + synopmob_set_register(base+BYTCNT, 8); + ret = synopmob_execute_command(base, cmd_reg, 0); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (ret) { + break; + } - ret = synopmob_handle_standard_rinsts(intst); - if (ret) { - break; - } - - if (intst & INTMSK_CMD_DONE) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (ret) - break; - } + ret = synopmob_handle_standard_rinsts(intst); + if (ret) { + break; + } - if (intst & INTMSK_DAT_OVER) { - entries = synopmob_read_register(base + STATUS); - if (GET_FIFO_COUNT(entries) == 2) { - while (count >= 0) { - entries = synopmob_read_register(base + FIFODAT); - sdc->scr[count--] = BE32_TO_CPU(entries); - } - } - break; - } + if (intst & INTMSK_CMD_DONE) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (ret) + break; + } - synopmob_set_register(base+RINTSTS, intst); - intst = 0; - } + if (intst & INTMSK_DAT_OVER) { + entries = synopmob_read_register(base + STATUS); + if (GET_FIFO_COUNT(entries) == 2) { + while (count >= 0) { + entries = synopmob_read_register(base + FIFODAT); + sdc->scr[count--] = BE32_TO_CPU(entries); + } + } + break; + } - if (intst) { - synopmob_set_register(base+RINTSTS, intst); - } - } + synopmob_set_register(base+RINTSTS, intst); + intst = 0; + } - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } + if (intst) { + synopmob_set_register(base+RINTSTS, intst); + } + } + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } - return ret; + return ret; } -static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff) +static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff) { - unsigned int cmd_reg = 0x2246; - unsigned int resp; - int ret; - unsigned int intst = 0; - unsigned int entries; - int count = 64; - unsigned int base = sdc->ip_base; + unsigned int cmd_reg = 0x2246; + unsigned int resp; + int ret; + unsigned int intst = 0; + unsigned int entries; + int count = 64; + unsigned int base = sdc->ip_base; - synopmob_set_register(base+BLKSIZ, 64); - synopmob_set_register(base+BYTCNT, 64); - ret = synopmob_execute_command(base, cmd_reg, cmd_arg); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (ret) { - break; - } + synopmob_set_register(base+BLKSIZ, 64); + synopmob_set_register(base+BYTCNT, 64); + ret = synopmob_execute_command(base, cmd_reg, cmd_arg); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (ret) { + break; + } - ret = synopmob_handle_standard_rinsts(intst); - if (ret) { - break; - } - - if (intst & INTMSK_CMD_DONE) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (ret) - break; - } + ret = synopmob_handle_standard_rinsts(intst); + if (ret) { + break; + } - while (count > 0) { - entries = synopmob_read_register(base + STATUS); - if ( !GET_FIFO_COUNT(entries) ) { - break; - } - *(data_buff++) = synopmob_read_register(base + FIFODAT); - count -= 4; - } + if (intst & INTMSK_CMD_DONE) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (ret) + break; + } - if (intst & INTMSK_DAT_OVER) { - break; - } + while (count > 0) { + entries = synopmob_read_register(base + STATUS); + if ( !GET_FIFO_COUNT(entries) ) { + break; + } + *(data_buff++) = synopmob_read_register(base + FIFODAT); + count -= 4; + } - synopmob_set_register(base+RINTSTS, intst); //write to clear - intst = 0; - } + if (intst & INTMSK_DAT_OVER) { + break; + } - if (intst) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - } - } + synopmob_set_register(base+RINTSTS, intst); //write to clear + intst = 0; + } - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); + if (intst) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + } + } - return ret; + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + + return ret; } static int synopmob_send_clock_only_cmd(unsigned int base) { - return synopmob_execute_command(base, 0x202000, 0); + return synopmob_execute_command(base, 0x202000, 0); } static int synopmob_disable_all_clocks(unsigned int base) { - synopmob_set_register(base+CLKENA, 0); - return synopmob_send_clock_only_cmd(base); + synopmob_set_register(base+CLKENA, 0); + return synopmob_send_clock_only_cmd(base); } static int synopmob_enable_clocks_with_val(unsigned int base, unsigned int val) { - synopmob_set_register(base+CLKENA, val); - return synopmob_send_clock_only_cmd(base); + synopmob_set_register(base+CLKENA, val); + return synopmob_send_clock_only_cmd(base); } static int synopmob_set_clk_freq(sdc_t* sdc, unsigned int divider) { - #define MAX_DIVIDER_VALUE 0xff - - unsigned int orig_clkena; - int retval; - unsigned int base = sdc->ip_base; + #define MAX_DIVIDER_VALUE 0xff + + unsigned int orig_clkena; + int retval; + unsigned int base = sdc->ip_base; - if (divider > MAX_DIVIDER_VALUE) { - return 0xffffffff; - } + if (divider > MAX_DIVIDER_VALUE) { + return 0xffffffff; + } + + /* To make sure we dont disturb enable/disable settings of the cards*/ + orig_clkena = synopmob_read_register(base+CLKENA); - /* To make sure we dont disturb enable/disable settings of the cards*/ - orig_clkena = synopmob_read_register(base+CLKENA); + /* Disable all clocks before changing frequency the of card clocks */ + if ((retval = synopmob_disable_all_clocks(base)) != 0) { + return retval; + } + /* Program the clock divider in our case it is divider 0 */ + synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE); + synopmob_set_bits(base+CLKDIV, divider); - /* Disable all clocks before changing frequency the of card clocks */ - if ((retval = synopmob_disable_all_clocks(base)) != 0) { - return retval; - } - /* Program the clock divider in our case it is divider 0 */ - synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE); - synopmob_set_bits(base+CLKDIV, divider); - - /*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */ - if ((retval = synopmob_send_clock_only_cmd(base)) != 0) { - synopmob_enable_clocks_with_val(base, orig_clkena); - return retval; - } + /*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */ + if ((retval = synopmob_send_clock_only_cmd(base)) != 0) { + synopmob_enable_clocks_with_val(base, orig_clkena); + return retval; + } - return synopmob_enable_clocks_with_val(base, orig_clkena); + return synopmob_enable_clocks_with_val(base, orig_clkena); } static int enum_sd_card(sdc_t* sdc) { - int ret; - int count = 1000; - int hcs = 0; - unsigned int buffer[16]; - unsigned int base = sdc->ip_base; + int ret; + int count = 1000; + int hcs = 0; + unsigned int buffer[16]; + unsigned int base = sdc->ip_base; - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - - #if 0 - synopmob_set_bits(0x98500004, (1<<24)); //set to output mode - synopmob_set_bits(0x98500000, (1<<24)); //power off - plat_loop(1000000/5); //Lets give some ramp down period - synopmob_clear_bits(0x98500000, (1<<24)); //power on - plat_loop(1000000/5);//Lets give some ramp down period - #endif - - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } - synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ - ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - - if ( !ret ) { - plat_loop(1000); //enough for 74 clock. - SDC_WHERE(); - ret = sd_send_cmd0(sdc); //CMD0 has no response - } - - if ( !ret ) { - SDC_WHERE(); - ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card. - if (!ret) { - hcs = 1; - } - SDC_WHERE(); - ret = sd_send_acmd41(sdc, &hcs); - } + #if 0 + synopmob_set_bits(0x98500004, (1<<24)); //set to output mode + synopmob_set_bits(0x98500000, (1<<24)); //power off + plat_loop(1000000/5); //Lets give some ramp down period + synopmob_clear_bits(0x98500000, (1<<24)); //power on + plat_loop(1000000/5);//Lets give some ramp down period + #endif - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd2(sdc); //CID - } + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd3(sdc); //get RCA - } + synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ + ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd9(sdc); //CSD - } + if ( !ret ) { + plat_loop(1000); //enough for 74 clock. + SDC_WHERE(); + ret = sd_send_cmd0(sdc); //CMD0 has no response + } - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd7(sdc); //select the card - } + if ( !ret ) { + SDC_WHERE(); + ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card. + if (!ret) { + hcs = 1; + } + SDC_WHERE(); + ret = sd_send_acmd41(sdc, &hcs); + } - if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) { - SDC_WHERE(); - ret = sd_send_acmd51(sdc); //SCR - if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported? - ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode - } - } - - if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10. - SDC_WHERE(); - ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode. - if ( !ret && (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode? - SDC_WHERE(); - ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode. - if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) { - //switch to high speed mode sucess. - sd_send_uncmd7(sdc); //deselect the card - sd_send_cmd9(sdc); //CSD - ret = sd_send_cmd7(sdc); //select the card - } - } - } - - if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) { - if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode. - SDC_WHERE(); - ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2)))); - } - else if ( (sdc->csd[3] & 0xff) == 0x32 ) { - SDC_WHERE(); //25MHz standard speed mode. - ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/); - } - } + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd2(sdc); //CID + } - if (!ret) { - sdc->card_type = SD_TYPE; - if (hcs) { - sdc->card_type = SD_2_0_TYPE; - } - } + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd3(sdc); //get RCA + } + + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd9(sdc); //CSD + } - return ret; + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd7(sdc); //select the card + } + + if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) { + SDC_WHERE(); + ret = sd_send_acmd51(sdc); //SCR + if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported? + ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode + } + } + + if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10. + SDC_WHERE(); + ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode. + if ( !ret && (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode? + SDC_WHERE(); + ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode. + if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) { + //switch to high speed mode sucess. + sd_send_uncmd7(sdc); //deselect the card + sd_send_cmd9(sdc); //CSD + ret = sd_send_cmd7(sdc); //select the card + } + } + } + + if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) { + if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode. + SDC_WHERE(); + ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2)))); + } + else if ( (sdc->csd[3] & 0xff) == 0x32 ) { + SDC_WHERE(); //25MHz standard speed mode. + ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/); + } + } + + if (!ret) { + sdc->card_type = SD_TYPE; + if (hcs) { + sdc->card_type = SD_2_0_TYPE; + } + } + + return ret; } int sdio_drv_creg_read(HSDC handle, int addr, int fn, unsigned int *resp) { - sdc_t* sdc = (sdc_t*)handle; - unsigned int arg; - unsigned int cmd_reg = 0x74; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; - rt_err_t err; + sdc_t* sdc = (sdc_t*)handle; + unsigned int arg; + unsigned int cmd_reg = 0x74; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; + rt_err_t err; if(resp) { *resp = 0; } - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - arg = (fn << 28) | (addr << 9); - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r5_resp(*resp); - } - } - } + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } - rt_sem_release(sdc->mutex); - - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret); - } - - return ret; + arg = (fn << 28) | (addr << 9); + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r5_resp(*resp); + } + } + } + + rt_sem_release(sdc->mutex); + + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret); + } + + return ret; } int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data, unsigned int *resp) { - sdc_t* sdc = (sdc_t*)handle; - unsigned int arg; - unsigned int cmd_reg = 0x74; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; - rt_err_t err; + sdc_t* sdc = (sdc_t*)handle; + unsigned int arg; + unsigned int cmd_reg = 0x74; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; + rt_err_t err; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data; + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r5_resp(*resp); + } + } + } - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data; - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r5_resp(*resp); - } - } - } + rt_sem_release(sdc->mutex); + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret); + } - rt_sem_release(sdc->mutex); - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret); - } - - return ret; + return ret; } #define ARC_REG_DC_IVDL 0x4A @@ -1184,153 +1184,153 @@ extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); void inv_dcache_range(unsigned long start, unsigned long len) { - mmu_invalidate_dcache(start, len); + mmu_invalidate_dcache(start, len); } void flush_dcache_range(unsigned long start, unsigned long len) { - mmu_clean_dcache(start, len); + mmu_clean_dcache(start, len); } int g_use_bcm43362 = 0; static int sdio_drv_read_write(sdc_t* sdc, unsigned int rw, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - int loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + int loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; //SDIO_PRINTF("------- %s, line %d buf = %08x size = %d -------\n", __FUNCTION__, __LINE__, buf, bsize); - arg = (fn << 28) | (addr << 9); + arg = (fn << 28) | (addr << 9); - if (g_use_bcm43362) { - arg |= (1 << 26); //OPcode = 1............, for AP6181. - } + if (g_use_bcm43362) { + arg |= (1 << 26); //OPcode = 1............, for AP6181. + } - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; - if ( rw ) { - flush_dcache_range((unsigned long)buf, num); - } - else { - inv_dcache_range((unsigned long)buf, num); + if ( rw ) { + flush_dcache_range((unsigned long)buf, num); + } + else { + inv_dcache_range((unsigned long)buf, num); } - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } //synopmob_set_bits(base+FIFOTH, 0x2 << 28); - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - //pDmaDesc->desc0 = 0; - pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; - pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); - pDmaDesc->desc2 = (unsigned int)buf; - //pDmaDesc->desc3 = 0; - flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc)); - synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc); - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); + //pDmaDesc->desc0 = 0; + pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; + pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); + pDmaDesc->desc2 = (unsigned int)buf; + //pDmaDesc->desc3 = 0; + flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc)); + synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc); + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); //SDIO_PRINTF("pDmaDesc = %08x, %08x / %08x / %08x / %08x\n", pDmaDesc, pDmaDesc->desc0, pDmaDesc->desc1, pDmaDesc->desc2, pDmaDesc->desc3); - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt SDIO_PRINTF("------- %s, line %d idsts = %08x check = %d -------\n", __FUNCTION__, __LINE__, sdc->idsts, loop_for_command_done_check); - ret = ERRIDMA; - } - } - else + ret = ERRIDMA; + } + } + else SDIO_PRINTF("------- %s, line %d intsts = %08x buf = %08x -------\n", __FUNCTION__, __LINE__, intsts, buf); - } - } + } + } + + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - SDIO_PRINTF("sdio_drv_read_write1(%s) fail:, ret = %d\n", op, ret); - } - - if ( rw && !ret ) { //write - ret = synopmob_wait_data_ready(base); - } + } + + if ( rw && !ret ) { //write + ret = synopmob_wait_data_ready(base); + } - rt_sem_release(sdc->mutex); + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buf, num); + } - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buf, num); - } - if (ret) { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret); + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret); } - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } int sdio_drv_read(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf); + return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf); } int sdio_drv_write(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf); + return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf); } static void dumpchain(DmaDesc *pChain) { int i = 0; DmaDesc *tmp_pChain = pChain; - + while(tmp_pChain && i < 10) { SDIO_PRINTF("[%d]: chain =%p, buf = %p, size = %d, csi = %08x, next = %p\n", i, tmp_pChain, (DmaDesc *)tmp_pChain->desc2, tmp_pChain->desc1, tmp_pChain->desc0, (DmaDesc *)tmp_pChain->desc3); @@ -1346,711 +1346,711 @@ static void dumpchain(DmaDesc *pChain) #if 1 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - unsigned int chain_len = 0; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - unsigned int rw = 1; - DmaDesc *tmpDesc = (DmaDesc *)chain; - DmaDesc *lastDesc = (void*)0; + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + unsigned int chain_len = 0; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + unsigned int rw = 1; + DmaDesc *tmpDesc = (DmaDesc *)chain; + DmaDesc *lastDesc = (void*)0; - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - while(tmpDesc != 0) { // make sure size is little than DescBuf1SizMsk if(tmpDesc->desc1 > (DescBuf1SizMsk >> DescBuf1SizeShift)) { - // TBD... fix me + // TBD... fix me rt_sem_release(sdc->mutex); return 0; } // TBD... fix me, we must align tmpDesc->desc2 to 4 ? - + tmpDesc->desc0 = DescOwnByDma | DescSecAddrChained; - + // is it last node? if(tmpDesc->desc3 == 0 || tmpDesc->desc3 == (unsigned int)chain) { - tmpDesc->desc0 |= DescLastDesc; - lastDesc = tmpDesc; + tmpDesc->desc0 |= DescLastDesc; + lastDesc = tmpDesc; } else { - tmpDesc->desc0 |= DescDisInt; //disable interrupt... + tmpDesc->desc0 |= DescDisInt; //disable interrupt... } - + // is it first node? if((char *)tmpDesc == (char *)chain) { - tmpDesc->desc0 |= DescFirstDesc; - } + tmpDesc->desc0 |= DescFirstDesc; + } flush_dcache_range(tmpDesc->desc2, tmpDesc->desc1); - + tmpDesc = (DmaDesc *)tmpDesc->desc3; chain_len += sizeof(buf_chain_t); if((char *)tmpDesc == (char *)chain) { - break; + break; } } lastDesc->desc3 = (unsigned int)chain; - //FIXME, chain must be continuous arrry. - flush_dcache_range((unsigned long)chain, chain_len); + //FIXME, chain must be continuous arrry. + flush_dcache_range((unsigned long)chain, chain_len); + + synopmob_set_register(base+DBADDR, (unsigned int)(chain)); + + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); + + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } - synopmob_set_register(base+DBADDR, (unsigned int)(chain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt); - dumpchain((DmaDesc *)chain); - } + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt); + dumpchain((DmaDesc *)chain); + } - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } - rt_sem_release(sdc->mutex); + rt_sem_release(sdc->mutex); - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret); - } + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret); + } - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #elif 0 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - //static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4]; - volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000; - - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - unsigned int chain_len = 0; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - char err; - unsigned int rw = 1; + //static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4]; + volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000; - buf_chain_t *usrchain; - unsigned int desc0; - unsigned int length = 0; + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + unsigned int chain_len = 0; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + char err; + unsigned int rw = 1; - if (!chain) { - return 0; - } + buf_chain_t *usrchain; + unsigned int desc0; + unsigned int length = 0; - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; + if (!chain) { + return 0; + } + + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; - OSSemPend(sdc->mutex, 0, &err); - if (err != OS_NO_ERR) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + OSSemPend(sdc->mutex, 0, &err); + if (err != OS_NO_ERR) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + usrchain = chain; + while (1) { + if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) { + // TBD... fix me + OSSemPost (sdc->mutex); + return 0; + } + length += usrchain->size; + desc0 = DescOwnByDma | DescSecAddrChained; + if (!usrchain->next || usrchain->next == chain) { + desc0 |= DescLastDesc; + } + else { + desc0 |= DescDisInt; //disable interrupt... + } + + if(usrchain == chain) { + desc0 |= DescFirstDesc; + } + + st_pchain[chain_len].desc0 = desc0; + st_pchain[chain_len].desc1 = (unsigned int)usrchain->size; + st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf; + st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]); + flush_dcache_range((unsigned int)usrchain->buf, usrchain->size); + + usrchain = usrchain->next; + if( !usrchain || usrchain == chain) { + break; + } + if (++chain_len >= 4) { + while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n"); + } + } + st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]); - usrchain = chain; - while (1) { - if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) { - // TBD... fix me - OSSemPost (sdc->mutex); - return 0; - } - length += usrchain->size; - desc0 = DescOwnByDma | DescSecAddrChained; - if (!usrchain->next || usrchain->next == chain) { - desc0 |= DescLastDesc; - } - else { - desc0 |= DescDisInt; //disable interrupt... - } + if (length != num) { + while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); + } - if(usrchain == chain) { - desc0 |= DescFirstDesc; - } + synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain)); - st_pchain[chain_len].desc0 = desc0; - st_pchain[chain_len].desc1 = (unsigned int)usrchain->size; - st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf; - st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]); - flush_dcache_range((unsigned int)usrchain->buf, usrchain->size); - - usrchain = usrchain->next; - if( !usrchain || usrchain == chain) { - break; - } - if (++chain_len >= 4) { - while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n"); - } - } - st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]); + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); - if (length != num) { - while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); - } + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } - synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); - } + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); + } - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } - OSSemPost (sdc->mutex); + OSSemPost (sdc->mutex); - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #else static unsigned char __attribute__ ((aligned(32))) st_net_buf[2*1024]; int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain; - - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - unsigned int rw = 1; + static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain; + + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + unsigned int rw = 1; + + buf_chain_t *usrchain; + unsigned int length = 0; + + if (!chain) { + return 0; + } + + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - buf_chain_t *usrchain; - unsigned int length = 0; + usrchain = chain; + while (1) { + if (length + usrchain->size >= sizeof(st_net_buf)) { + while(1) SDIO_PRINTF("too long net pkt\n"); + } - if (!chain) { - return 0; - } + memcpy(st_net_buf + length, usrchain->buf, usrchain->size); + length += usrchain->size; + usrchain = usrchain->next; + if (!usrchain || usrchain->next == chain) { + break; + } + } - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; + st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc; + st_pchain.desc1 = length; + st_pchain.desc2 = (unsigned int)st_net_buf; + st_pchain.desc3 = (unsigned int)&st_pchain; + flush_dcache_range((unsigned long)st_net_buf, length); - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + if (length != num) { + while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); + } - usrchain = chain; - while (1) { - if (length + usrchain->size >= sizeof(st_net_buf)) { - while(1) SDIO_PRINTF("too long net pkt\n"); - } - - memcpy(st_net_buf + length, usrchain->buf, usrchain->size); - length += usrchain->size; - usrchain = usrchain->next; - if (!usrchain || usrchain->next == chain) { - break; - } - } - - st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc; - st_pchain.desc1 = length; - st_pchain.desc2 = (unsigned int)st_net_buf; - st_pchain.desc3 = (unsigned int)&st_pchain; - flush_dcache_range((unsigned long)st_net_buf, length); - - if (length != num) { - while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); - } + synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain)); - synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); - } + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); + } + + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } - rt_sem_release(sdc->mutex); + rt_sem_release(sdc->mutex); - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #endif #endif static int sdio_card_reset(sdc_t* sdc) { - unsigned int resp; - int ret; + unsigned int resp; + int ret; - /* Soft Reset card */ + /* Soft Reset card */ sdio_drv_creg_write(sdc, 0x6, 0, 0x8, &resp); - return 0; + return 0; } static int enum_sdio_card(sdc_t* sdc) { - int ret; - unsigned int resp; - unsigned int base = sdc->ip_base; + int ret; + unsigned int resp; + unsigned int base = sdc->ip_base; + + #if 0 + synopmob_set_bits(0x98500004, (1<<24)); //set to output mode + synopmob_set_bits(0x98500000, (1<<24)); //power off + plat_loop(1000000/5); //Lets give some ramp down period + synopmob_clear_bits(0x98500000, (1<<24)); //power on + plat_loop(1000000/5);//Lets give some ramp down period + #endif + + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + + synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ + ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - #if 0 - synopmob_set_bits(0x98500004, (1<<24)); //set to output mode - synopmob_set_bits(0x98500000, (1<<24)); //power off - plat_loop(1000000/5); //Lets give some ramp down period - synopmob_clear_bits(0x98500000, (1<<24)); //power on - plat_loop(1000000/5);//Lets give some ramp down period - #endif + if ( !ret ) { + plat_loop(100); //enough for 74 clock. + #if 0 + sdio_card_reset(sdc); + plat_loop(100000); + #endif + ret = sd_send_cmd5(sdc, 0, &resp); + if (!ret) { + resp &= 0x00ffffff; + ret = sd_send_cmd5(sdc, resp, &resp); + } + } - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + if (!ret) { + ret = sd_send_cmd3(sdc); //get RCA + } - synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ - ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - - if ( !ret ) { - plat_loop(100); //enough for 74 clock. - #if 0 - sdio_card_reset(sdc); - plat_loop(100000); - #endif - ret = sd_send_cmd5(sdc, 0, &resp); - if (!ret) { - resp &= 0x00ffffff; - ret = sd_send_cmd5(sdc, resp, &resp); - } - } + if (!ret) { + ret = sd_send_cmd7(sdc); //select the card + } - if (!ret) { - ret = sd_send_cmd3(sdc); //get RCA - } - - if (!ret) { - ret = sd_send_cmd7(sdc); //select the card - } + if (!g_use_bcm43362) + { + sdio_drv_creg_read(sdc, 0x13, 0, &resp); + if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support? + if (sdc->wkmod & SDC_WKMOD_4WIRE) { + sdio_drv_creg_read(sdc, 0x7, 0, &resp); + resp &= 0xfc; + resp |= (1 << 1); + sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode + sdio_drv_creg_read(sdc, 0x7, 0, &resp); + if ((resp & 0x3) != 0x2) { + return ERRCARDINTERNAL; // 4bit mode failed + } + synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); + } + if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) { + ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ); + //ret = synopmob_set_clk_freq(sdc, 0); + } + } - if (!g_use_bcm43362) - { - sdio_drv_creg_read(sdc, 0x13, 0, &resp); - if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support? - if (sdc->wkmod & SDC_WKMOD_4WIRE) { - sdio_drv_creg_read(sdc, 0x7, 0, &resp); - resp &= 0xfc; - resp |= (1 << 1); - sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode - sdio_drv_creg_read(sdc, 0x7, 0, &resp); - if ((resp & 0x3) != 0x2) { - return ERRCARDINTERNAL; // 4bit mode failed - } - synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); - } - if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) { - ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ); - //ret = synopmob_set_clk_freq(sdc, 0); - } - } + sdio_drv_creg_read(sdc, 0x3, 0, &resp); + if (!ret) { + sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version + sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card + sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card + do { + sdio_drv_creg_read(sdc, 0x3, 0, &resp); + } while (!(resp & 2)); + } + } //g_use_bcm43362 - sdio_drv_creg_read(sdc, 0x3, 0, &resp); - if (!ret) { - sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version - sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card - sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card - do { - sdio_drv_creg_read(sdc, 0x3, 0, &resp); - } while (!(resp & 2)); - } - } //g_use_bcm43362 + sdc->card_type = SDIO_TYPE; - sdc->card_type = SDIO_TYPE; + synopmob_set_bits(base+CTRL, INT_ENABLE); - synopmob_set_bits(base+CTRL, INT_ENABLE); - - return ret; + return ret; } int sdio_high_speed_mode(HSDC handle, int bitwidth, int freq) { - int ret; - sdc_t* sdc = (sdc_t*)handle; + int ret; + sdc_t* sdc = (sdc_t*)handle; - if (bitwidth == 4) - { - synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE); - } + if (bitwidth == 4) + { + synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE); + } - ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1); - if (ret != 0) - { - SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret); - } + ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1); + if (ret != 0) + { + SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret); + } - return ret; + return ret; } static int common_init(unsigned int which, unsigned int sdio, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - int ret = ERRNORES; - sdc_t* sdc; - unsigned int base; - unsigned int temp; - unsigned int fifo_thresh; - volatile DmaDesc *pDmaDesc; - rt_sem_t sem; - rt_sem_t mutex; - - base = SDC0_REG_BASE; - temp = PMU_SDC0_RST_BIT; - if (which > 0) { - base = SDC1_REG_BASE; - temp = PMU_SDC1_RST_BIT; - } - + int ret = ERRNORES; + sdc_t* sdc; + unsigned int base; + unsigned int temp; + unsigned int fifo_thresh; + volatile DmaDesc *pDmaDesc; + rt_sem_t sem; + rt_sem_t mutex; + + base = SDC0_REG_BASE; + temp = PMU_SDC0_RST_BIT; + if (which > 0) { + base = SDC1_REG_BASE; + temp = PMU_SDC1_RST_BIT; + } + #if 0 - //PMU_RST_MODULE(temp); plat_loop(1); - temp = synopmob_read_register(PMU_REG_CLK_DIV3); - temp &= (~(0x0f<<8)); - temp |= (0xf<<8); - synopmob_set_register(PMU_REG_CLK_DIV3, temp); + //PMU_RST_MODULE(temp); plat_loop(1); + temp = synopmob_read_register(PMU_REG_CLK_DIV3); + temp &= (~(0x0f<<8)); + temp |= (0xf<<8); + synopmob_set_register(PMU_REG_CLK_DIV3, temp); #endif - *phandle = (HSDC)0; - - sdc = &sdc_array[which]; - sem = sdc->sem; - mutex = sdc->mutex; - memset((void *)sdc, 0, sizeof(*sdc)); - sdc->wkmod = wkmod; - sdc->idma_support = 0; - sdc->ip_base = base; - sdc->rca = 0; - sdc->card_type = NONE_TYPE; - if (!sem) { - sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0); - if ( !sem ) { - return ret; - } - } - sdc->sem = sem; + *phandle = (HSDC)0; + + sdc = &sdc_array[which]; + sem = sdc->sem; + mutex = sdc->mutex; + memset((void *)sdc, 0, sizeof(*sdc)); + sdc->wkmod = wkmod; + sdc->idma_support = 0; + sdc->ip_base = base; + sdc->rca = 0; + sdc->card_type = NONE_TYPE; + if (!sem) { + sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0); + if ( !sem ) { + return ret; + } + } + sdc->sem = sem; + + if (!mutex) { + mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1); + if ( !mutex ) { + return ret; + } + } + sdc->mutex = mutex; - if (!mutex) { - mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1); - if ( !mutex ) { - return ret; - } - } - sdc->mutex = mutex; - - synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller - plat_loop(100); + synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller + plat_loop(100); - synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC); - sdc->idma_support = 1; //fixed to support IDMA + synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC); + sdc->idma_support = 1; //fixed to support IDMA - pDmaDesc = (volatile DmaDesc *)dma_desc; - sdc->pDmaDesc = pDmaDesc; - if (sdc->idma_support) { - synopmob_set_bits(base + CTRL, DMA_RESET); - plat_loop(100); - synopmob_set_bits(base + CTRL, FIFO_RESET); - plat_loop(100); - synopmob_set_bits(base + BMOD, BMOD_SWR); - plat_loop(100); - - //synopmob_set_bits(base + BMOD,BMOD_DE); - pDmaDesc->desc0 = DescSecAddrChained; - pDmaDesc->desc1 = 0; - pDmaDesc->desc2 = 0; - pDmaDesc->desc3 = (unsigned int)(pDmaDesc); - synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); - } + pDmaDesc = (volatile DmaDesc *)dma_desc; + sdc->pDmaDesc = pDmaDesc; + if (sdc->idma_support) { + synopmob_set_bits(base + CTRL, DMA_RESET); + plat_loop(100); + synopmob_set_bits(base + CTRL, FIFO_RESET); + plat_loop(100); + synopmob_set_bits(base + BMOD, BMOD_SWR); + plat_loop(100); - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + //synopmob_set_bits(base + BMOD,BMOD_DE); + pDmaDesc->desc0 = DescSecAddrChained; + pDmaDesc->desc1 = 0; + pDmaDesc->desc2 = 0; + pDmaDesc->desc3 = (unsigned int)(pDmaDesc); + synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); + } - synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt. - synopmob_clear_bits(base+CTRL, INT_ENABLE); - synopmob_set_register(base+INTMSK, 0); // mask all INTR - synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt. + synopmob_clear_bits(base+CTRL, INT_ENABLE); + synopmob_set_register(base+INTMSK, 0); // mask all INTR + synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR - synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/ - /* Set the card Debounce to allow the CDETECT fluctuations to settle down*/ - synopmob_set_register(base+DEBNCE, 0x0FFFFF); + synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/ - fifo_thresh = synopmob_read_register(base+FIFOTH); - //fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2; - fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2; - sdc->fifo_depth = fifo_thresh * 2; - sdc->fifo_threth = fifo_thresh; - /* Tx Watermark */ - synopmob_clear_bits(base+FIFOTH, 0xfff); - synopmob_set_bits(base+FIFOTH, fifo_thresh); - /* Rx Watermark */ - synopmob_clear_bits(base+FIFOTH, 0x0fff0000); - synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16); - //synopmob_set_bits(base+FIFOTH, 2<< 28); + /* Set the card Debounce to allow the CDETECT fluctuations to settle down*/ + synopmob_set_register(base+DEBNCE, 0x0FFFFF); - if (!sdio) { - ret = enum_sd_card(sdc); - } - else { - ret = enum_sdio_card(sdc); - } + fifo_thresh = synopmob_read_register(base+FIFOTH); + //fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2; + fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2; + sdc->fifo_depth = fifo_thresh * 2; + sdc->fifo_threth = fifo_thresh; + /* Tx Watermark */ + synopmob_clear_bits(base+FIFOTH, 0xfff); + synopmob_set_bits(base+FIFOTH, fifo_thresh); + /* Rx Watermark */ + synopmob_clear_bits(base+FIFOTH, 0x0fff0000); + synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16); + //synopmob_set_bits(base+FIFOTH, 2<< 28); - if (!ret) { - *phandle = (HSDC)sdc; - } + if (!sdio) { + ret = enum_sd_card(sdc); + } + else { + ret = enum_sdio_card(sdc); + } - return ret; + if (!ret) { + *phandle = (HSDC)sdc; + } + + return ret; } int sdc_is_connected(unsigned int which) { - unsigned int base = SDC0_REG_BASE; - - if (which > 0) - base = SDC1_REG_BASE; + unsigned int base = SDC0_REG_BASE; + + if (which > 0) + base = SDC1_REG_BASE; - return !(synopmob_read_register(base+CDETECT) & 1); + return !(synopmob_read_register(base+CDETECT) & 1); } int sdc_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - return common_init(which, 0, wkmod, dma_desc, phandle); + return common_init(which, 0, wkmod, dma_desc, phandle); } int sdio_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - return common_init(which, 1, wkmod, dma_desc, phandle); + return common_init(which, 1, wkmod, dma_desc, phandle); } int sdio_enable_card_int(HSDC handle, int enable) { - unsigned int base = ((sdc_t*)handle)->ip_base; + unsigned int base = ((sdc_t*)handle)->ip_base; - if (enable) { - //synopmob_set_register(base+INTMSK, INTMSK_SDIO); - synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO )); - } - else { - //synopmob_set_register(base+INTMSK, 0); - synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO )); - } + if (enable) { + //synopmob_set_register(base+INTMSK, INTMSK_SDIO); + synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO )); + } + else { + //synopmob_set_register(base+INTMSK, 0); + synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO )); + } - return 0; + return 0; } int sdio_set_card_int_cb(HSDC handle, void (*cb)(void)) { - ((sdc_t*)handle)->cb = cb; + ((sdc_t*)handle)->cb = cb; - return 0; + return 0; } static void OSSDCISR(sdc_t* sdc) { - unsigned int sts; - unsigned int base; + unsigned int sts; + unsigned int base; - base = sdc->ip_base; - sts = synopmob_read_register(base+IDSTS); - if ( sts ) { - synopmob_set_register(base+IDSTS, sts); - sdc->idsts = sts; - rt_sem_release(sdc->sem); - } + base = sdc->ip_base; + sts = synopmob_read_register(base+IDSTS); + if ( sts ) { + synopmob_set_register(base+IDSTS, sts); + sdc->idsts = sts; + rt_sem_release(sdc->sem); + } - //sts = synopmob_read_register(base+RINTSTS); - sts = synopmob_read_register(base+MINTSTS); - sts &= INTMSK_SDIO; - if ( sts ) { //interrupt from WIFI card. - //synopmob_set_register(base+INTMSK, 0); //mask all the interrupt - synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt - synopmob_set_register(base+RINTSTS, sts); - synopmob_set_register(base+MINTSTS, sts); - if (sdc->cb) { - sdc->cb(); - } - } + //sts = synopmob_read_register(base+RINTSTS); + sts = synopmob_read_register(base+MINTSTS); + sts &= INTMSK_SDIO; + if ( sts ) { //interrupt from WIFI card. + //synopmob_set_register(base+INTMSK, 0); //mask all the interrupt + synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt + synopmob_set_register(base+RINTSTS, sts); + synopmob_set_register(base+MINTSTS, sts); + if (sdc->cb) { + sdc->cb(); + } + } } void OSSDCINTR_0(int vector, void *param) { - OSSDCISR(&sdc_array[0]); + OSSDCISR(&sdc_array[0]); } void OSSDCINTR_1(int vector, void *param) { - OSSDCISR(&sdc_array[1]); + OSSDCISR(&sdc_array[1]); } void fh_sdio0_init(void) { int sd0_irq = SDC0_IRQn; - + rt_hw_interrupt_install(sd0_irq, OSSDCINTR_0, NULL, NULL); rt_hw_interrupt_umask(sd0_irq); } @@ -2058,7 +2058,7 @@ void fh_sdio0_init(void) void fh_sdio1_init(void) { int sd1_irq = SDC1_IRQn; - + rt_hw_interrupt_install(sd1_irq, OSSDCINTR_1, NULL, NULL); rt_hw_interrupt_umask(sd1_irq); } @@ -2071,14 +2071,14 @@ void fh_sdio_init(void) int sdc_deinit(HSDC handle) { - return -1; // TBD... fix me + return -1; // TBD... fix me } int sdc_set_clk_divider(unsigned int divider) { if(divider > 255) return -1; - + sdc_clk_divider = divider; return 0; } diff --git a/bsp/fh8620/libraries/driverlib/fh_spi.c b/bsp/fh8620/libraries/driverlib/fh_spi.c index 14d8039732..14e47ad73b 100644 --- a/bsp/fh8620/libraries/driverlib/fh_spi.c +++ b/bsp/fh8620/libraries/driverlib/fh_spi.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_timer.c b/bsp/fh8620/libraries/driverlib/fh_timer.c index f3034adeaa..eab30888a5 100644 --- a/bsp/fh8620/libraries/driverlib/fh_timer.c +++ b/bsp/fh8620/libraries/driverlib/fh_timer.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -79,66 +79,66 @@ *****************************************************************************/ int timer_init(timer *tim) { - tim->TIMER_CTRL_REG = 0; + tim->TIMER_CTRL_REG = 0; } int timer_set_mode(timer *tim, enum timer_mode mode) { - switch (mode) - { - case TIMER_MODE_PERIODIC: - tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; - break; - case TIMER_MODE_ONESHOT: - tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; - break; - default: - rt_kprintf("Not support TIMER mode\n"); - return -1; - break; - } + switch (mode) + { + case TIMER_MODE_PERIODIC: + tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; + break; + case TIMER_MODE_ONESHOT: + tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; + break; + default: + rt_kprintf("Not support TIMER mode\n"); + return -1; + break; + } - return 0; + return 0; } void timer_set_period(timer *tim, UINT32 period, UINT32 clock) { - tim->TIMER_LOAD_COUNT = clock/period; + tim->TIMER_LOAD_COUNT = clock/period; } void timer_enable(timer *tim) { - tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE; + tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE; } void timer_disable(timer *tim) { - tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE; + tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE; } void timer_enable_irq(timer *tim) { - tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK; + tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK; } void timer_disable_irq(timer *tim) { - tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK; + tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK; } UINT32 timer_get_status(timer *tim) { - return tim->TIMER_INT_STATUS; + return tim->TIMER_INT_STATUS; } UINT32 timer_get_eoi(timer *tim) { - return tim->TIMER_EOI; + return tim->TIMER_EOI; } UINT32 timer_get_value(timer *tim) { - return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE; + return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE; } diff --git a/bsp/fh8620/libraries/driverlib/fh_uart.c b/bsp/fh8620/libraries/driverlib/fh_uart.c index 0d9ad1f35d..75b453c9fb 100644 --- a/bsp/fh8620/libraries/driverlib/fh_uart.c +++ b/bsp/fh8620/libraries/driverlib/fh_uart.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -79,33 +79,33 @@ int uart_init(uart *port) { - port->UART_IER = 0; - port->UART_LCR = 0; - //port->UART_DLL = 0; - //port->UART_DLH = 0; + port->UART_IER = 0; + port->UART_LCR = 0; + //port->UART_DLL = 0; + //port->UART_DLH = 0; } UINT32 uart_get_status(uart *port) { - return port->UART_USR; + return port->UART_USR; } void uart_configure(uart *port, enum data_bits data_bit, - enum stop_bits stop_bit, enum parity parity, - UINT32 buard_rate, UINT32 uart_clk) + enum stop_bits stop_bit, enum parity parity, + UINT32 buard_rate, UINT32 uart_clk) { - UINT32 divisor; - UINT32 freq; - UINT32 baud_div; - UINT32 lcr_reg = 0; - UINT32 ret; + UINT32 divisor; + UINT32 freq; + UINT32 baud_div; + UINT32 lcr_reg = 0; + UINT32 ret; - /*divisor = DIV(buard_rate); - port->UART_LCR |= UART_LCR_DLAB; - port->UART_DLL = divisor & 0xFF; - port->UART_DLH = (divisor >> 8) & 0xFF; - port->UART_LCR &= ~UART_LCR_DLAB;*/ + /*divisor = DIV(buard_rate); + port->UART_LCR |= UART_LCR_DLAB; + port->UART_DLL = divisor & 0xFF; + port->UART_DLH = (divisor >> 8) & 0xFF; + port->UART_LCR &= ~UART_LCR_DLAB;*/ do{ //clear fifo... @@ -113,141 +113,141 @@ void uart_configure(uart *port, enum data_bits data_bit, //read status.. ret = uart_get_status(port); }while(ret & UART_USR_BUSY); - switch (data_bit) { - case UART_DATA_BIT5: - lcr_reg |= UART_LCR_DLS5; - break; - case UART_DATA_BIT6: - lcr_reg |= UART_LCR_DLS6; - break; - case UART_DATA_BIT7: - lcr_reg |= UART_LCR_DLS7; - break; - case UART_DATA_BIT8: - lcr_reg |= UART_LCR_DLS8; - break; - default: - lcr_reg |= UART_LCR_DLS8; - break; - } + switch (data_bit) { + case UART_DATA_BIT5: + lcr_reg |= UART_LCR_DLS5; + break; + case UART_DATA_BIT6: + lcr_reg |= UART_LCR_DLS6; + break; + case UART_DATA_BIT7: + lcr_reg |= UART_LCR_DLS7; + break; + case UART_DATA_BIT8: + lcr_reg |= UART_LCR_DLS8; + break; + default: + lcr_reg |= UART_LCR_DLS8; + break; + } - switch (stop_bit) { - case UART_STOP_BIT1: - lcr_reg |= UART_LCR_STOP1; - break; - case UART_STOP_BIT2: - lcr_reg |= UART_LCR_STOP2; - break; - default: - lcr_reg |= UART_LCR_STOP1; - break; - } + switch (stop_bit) { + case UART_STOP_BIT1: + lcr_reg |= UART_LCR_STOP1; + break; + case UART_STOP_BIT2: + lcr_reg |= UART_LCR_STOP2; + break; + default: + lcr_reg |= UART_LCR_STOP1; + break; + } - switch (parity) { - case UART_PARITY_EVEN: - lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN; - break; - case UART_PARITY_ODD: - lcr_reg |= UART_LCR_PEN; - break; - case UART_PARITY_ST: - lcr_reg |= UART_LCR_SP; - break; - case UART_PARITY_NONE: - default: - break; - } + switch (parity) { + case UART_PARITY_EVEN: + lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN; + break; + case UART_PARITY_ODD: + lcr_reg |= UART_LCR_PEN; + break; + case UART_PARITY_ST: + lcr_reg |= UART_LCR_SP; + break; + case UART_PARITY_NONE: + default: + break; + } - switch (buard_rate) { - case 115200: - baud_div = BAUDRATE_115200; - break; - case 57600: - baud_div = BAUDRATE_57600; - break; - case 38400: - baud_div = BAUDRATE_38400; - break; - case 19200: - baud_div = BAUDRATE_19200; - break; - case 9600: - baud_div = BAUDRATE_9600; - break; - default: - baud_div = BAUDRATE_115200; - break; - } + switch (buard_rate) { + case 115200: + baud_div = BAUDRATE_115200; + break; + case 57600: + baud_div = BAUDRATE_57600; + break; + case 38400: + baud_div = BAUDRATE_38400; + break; + case 19200: + baud_div = BAUDRATE_19200; + break; + case 9600: + baud_div = BAUDRATE_9600; + break; + default: + baud_div = BAUDRATE_115200; + break; + } - //clear fifo - port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR; + //clear fifo + port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR; - //div - ret = port->UART_LCR; - ret |= UART_LCR_DLAB; - port->UART_LCR = ret; - port->RBRTHRDLL = baud_div & 0x00ff; - port->DLHIER = (baud_div & 0x00ff)>>8; - /* clear DLAB */ - ret = ret & 0x7f; - port->UART_LCR = ret; + //div + ret = port->UART_LCR; + ret |= UART_LCR_DLAB; + port->UART_LCR = ret; + port->RBRTHRDLL = baud_div & 0x00ff; + port->DLHIER = (baud_div & 0x00ff)>>8; + /* clear DLAB */ + ret = ret & 0x7f; + port->UART_LCR = ret; - //line control - port->UART_LCR = lcr_reg; - //fifo control - port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE; + //line control + port->UART_LCR = lcr_reg; + //fifo control + port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE; } int uart_enable_irq(uart *port, UINT32 mode) { - unsigned int ret; - ret = port->UART_IER; - ret |= mode; - port->UART_IER = ret; + unsigned int ret; + ret = port->UART_IER; + ret |= mode; + port->UART_IER = ret; } int uart_disable_irq(uart *port, UINT32 mode) { - unsigned int ret; - ret = port->UART_IER; - ret &= ~mode; + unsigned int ret; + ret = port->UART_IER; + ret &= ~mode; - port->UART_IER = ret; + port->UART_IER = ret; } UINT32 uart_get_iir_status(uart *port) { - return port->UART_IIR; + return port->UART_IIR; } UINT32 uart_get_line_status(uart *port) { - return port->UART_LSR; + return port->UART_LSR; } UINT32 uart_is_rx_ready(uart *port) { - return port->UART_LSR & UART_LSR_DR; + return port->UART_LSR & UART_LSR_DR; } UINT8 uart_getc(uart *port) { - return port->UART_RBR & 0xFF; + return port->UART_RBR & 0xFF; } void uart_putc(uart *port, UINT8 c) { - //while(!(port->UART_USR & UART_USR_TFNF)); - port->UART_THR = c; + //while(!(port->UART_USR & UART_USR_TFNF)); + port->UART_THR = c; } void uart_set_fifo_mode(uart *port, UINT32 fifo_mode) { - port->UART_FCR = fifo_mode; + port->UART_FCR = fifo_mode; } diff --git a/bsp/fh8620/libraries/driverlib/fh_wdt.c b/bsp/fh8620/libraries/driverlib/fh_wdt.c index 002a929bba..33e3defa1e 100644 --- a/bsp/fh8620/libraries/driverlib/fh_wdt.c +++ b/bsp/fh8620/libraries/driverlib/fh_wdt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_driverlib.h b/bsp/fh8620/libraries/inc/fh_driverlib.h index 9bb6b8c75d..9f45eb836f 100644 --- a/bsp/fh8620/libraries/inc/fh_driverlib.h +++ b/bsp/fh8620/libraries/inc/fh_driverlib.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rtthread.h> #include <rthw.h> #include "fh_def.h" diff --git a/bsp/fh8620/libraries/inc/fh_gpio.h b/bsp/fh8620/libraries/inc/fh_gpio.h index 62d1823eba..3d98a44be3 100644 --- a/bsp/fh8620/libraries/inc/fh_gpio.h +++ b/bsp/fh8620/libraries/inc/fh_gpio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_GPIO_H_ #define FH_GPIO_H_ diff --git a/bsp/fh8620/libraries/inc/fh_i2c.h b/bsp/fh8620/libraries/inc/fh_i2c.h index 4debd9926d..069aa8f275 100644 --- a/bsp/fh8620/libraries/inc/fh_i2c.h +++ b/bsp/fh8620/libraries/inc/fh_i2c.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_I2C_H_ #define FH_I2C_H_ diff --git a/bsp/fh8620/libraries/inc/fh_ictl.h b/bsp/fh8620/libraries/inc/fh_ictl.h index 9796c99afc..6959715377 100644 --- a/bsp/fh8620/libraries/inc/fh_ictl.h +++ b/bsp/fh8620/libraries/inc/fh_ictl.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -30,21 +30,21 @@ #include "fh_def.h" typedef struct { - RwReg IRQ_EN_L; - RwReg IRQ_EN_H; - RwReg IRQ_MASK_L; - RwReg IRQ_MASK_H; - RwReg IRQ_FORCE_L; - RwReg IRQ_FORCE_H; - RwReg IRQ_RAWSTARUS_L; - RwReg IRQ_RAWSTARUS_H; - RwReg IRQ_STATUS_L; - RwReg IRQ_STATUS_H; - RwReg IRQ_MASKSTATUS_L; - RwReg IRQ_MASKSTATUS_H; - RwReg IRQ_FINALSTATUS_L; - RwReg IRQ_FINALSTATUS_H; - RwReg IRQ_VECTOR; + RwReg IRQ_EN_L; + RwReg IRQ_EN_H; + RwReg IRQ_MASK_L; + RwReg IRQ_MASK_H; + RwReg IRQ_FORCE_L; + RwReg IRQ_FORCE_H; + RwReg IRQ_RAWSTARUS_L; + RwReg IRQ_RAWSTARUS_H; + RwReg IRQ_STATUS_L; + RwReg IRQ_STATUS_H; + RwReg IRQ_MASKSTATUS_L; + RwReg IRQ_MASKSTATUS_H; + RwReg IRQ_FINALSTATUS_L; + RwReg IRQ_FINALSTATUS_H; + RwReg IRQ_VECTOR; }fh_intc; diff --git a/bsp/fh8620/libraries/inc/fh_mmc.h b/bsp/fh8620/libraries/inc/fh_mmc.h index 4aaf416ce6..d999ecf7dd 100644 --- a/bsp/fh8620/libraries/inc/fh_mmc.h +++ b/bsp/fh8620/libraries/inc/fh_mmc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_pwm.h b/bsp/fh8620/libraries/inc/fh_pwm.h index 011da43905..6281a5f128 100644 --- a/bsp/fh8620/libraries/inc/fh_pwm.h +++ b/bsp/fh8620/libraries/inc/fh_pwm.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_sdio.h b/bsp/fh8620/libraries/inc/fh_sdio.h index b268dbd322..f4791605e1 100644 --- a/bsp/fh8620/libraries/inc/fh_sdio.h +++ b/bsp/fh8620/libraries/inc/fh_sdio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -32,53 +32,53 @@ //#define __ASIC_BRANCH__ enum { - CTRL = 0x0, /** Control */ - PWREN = 0x4, /** Power-enable */ - CLKDIV = 0x8, /** Clock divider */ - CLKSRC = 0xC, /** Clock source */ - CLKENA = 0x10, /** Clock enable */ - TMOUT = 0x14, /** Timeout */ - CTYPE = 0x18, /** Card type */ - BLKSIZ = 0x1C, /** Block Size */ - BYTCNT = 0x20, /** Byte count */ - INTMSK = 0x24, /** Interrupt Mask */ - CMDARG = 0x28, /** Command Argument */ - CMD = 0x2C, /** Command */ - RESP0 = 0x30, /** Response 0 */ - RESP1 = 0x34, /** Response 1 */ - RESP2 = 0x38, /** Response 2 */ - RESP3 = 0x3C, /** Response 3 */ - MINTSTS = 0x40, /** Masked interrupt status */ - RINTSTS = 0x44, /** Raw interrupt status */ - STATUS = 0x48, /** Status */ - FIFOTH = 0x4C, /** FIFO threshold */ - CDETECT = 0x50, /** Card detect */ - WRTPRT = 0x54, /** Write protect */ - GPIO = 0x58, /** General Purpose IO */ - TCBCNT = 0x5C, /** Transferred CIU byte count */ - TBBCNT = 0x60, /** Transferred host/DMA to/from byte count */ - DEBNCE = 0x64, /** Card detect debounce */ - USRID = 0x68, /** User ID */ - VERID = 0x6C, /** Version ID */ - HCON = 0x70, /** Hardware Configuration */ - UHSREG = 0x74, /** Reserved */ - BMOD = 0x80, /** Bus mode Register */ - PLDMND = 0x84, /** Poll Demand */ - DBADDR = 0x88, /** Descriptor Base Address */ - IDSTS = 0x8C, /** Internal DMAC Status */ - IDINTEN = 0x90, /** Internal DMAC Interrupt Enable */ - DSCADDR = 0x94, /** Current Host Descriptor Address */ - BUFADDR = 0x98, /** Current Host Buffer Address */ - FIFODAT = 0x200, /** FIFO data read write */ + CTRL = 0x0, /** Control */ + PWREN = 0x4, /** Power-enable */ + CLKDIV = 0x8, /** Clock divider */ + CLKSRC = 0xC, /** Clock source */ + CLKENA = 0x10, /** Clock enable */ + TMOUT = 0x14, /** Timeout */ + CTYPE = 0x18, /** Card type */ + BLKSIZ = 0x1C, /** Block Size */ + BYTCNT = 0x20, /** Byte count */ + INTMSK = 0x24, /** Interrupt Mask */ + CMDARG = 0x28, /** Command Argument */ + CMD = 0x2C, /** Command */ + RESP0 = 0x30, /** Response 0 */ + RESP1 = 0x34, /** Response 1 */ + RESP2 = 0x38, /** Response 2 */ + RESP3 = 0x3C, /** Response 3 */ + MINTSTS = 0x40, /** Masked interrupt status */ + RINTSTS = 0x44, /** Raw interrupt status */ + STATUS = 0x48, /** Status */ + FIFOTH = 0x4C, /** FIFO threshold */ + CDETECT = 0x50, /** Card detect */ + WRTPRT = 0x54, /** Write protect */ + GPIO = 0x58, /** General Purpose IO */ + TCBCNT = 0x5C, /** Transferred CIU byte count */ + TBBCNT = 0x60, /** Transferred host/DMA to/from byte count */ + DEBNCE = 0x64, /** Card detect debounce */ + USRID = 0x68, /** User ID */ + VERID = 0x6C, /** Version ID */ + HCON = 0x70, /** Hardware Configuration */ + UHSREG = 0x74, /** Reserved */ + BMOD = 0x80, /** Bus mode Register */ + PLDMND = 0x84, /** Poll Demand */ + DBADDR = 0x88, /** Descriptor Base Address */ + IDSTS = 0x8C, /** Internal DMAC Status */ + IDINTEN = 0x90, /** Internal DMAC Interrupt Enable */ + DSCADDR = 0x94, /** Current Host Descriptor Address */ + BUFADDR = 0x98, /** Current Host Buffer Address */ + FIFODAT = 0x200, /** FIFO data read write */ }; /* Control register definitions */ -#define CTRL_RESET 0x00000001 +#define CTRL_RESET 0x00000001 #define FIFO_RESET 0x00000002 -#define DMA_RESET 0x00000004 -#define INT_ENABLE 0x00000010 -#define READ_WAIT 0x00000040 -#define CTRL_USE_IDMAC 0x02000000 +#define DMA_RESET 0x00000004 +#define INT_ENABLE 0x00000010 +#define READ_WAIT 0x00000040 +#define CTRL_USE_IDMAC 0x02000000 /* Interrupt mask defines */ #define INTMSK_CDETECT 0x00000001 @@ -102,11 +102,11 @@ enum { #define INTMASK_ERROR (INTMSK_RESP_ERR|INTMSK_RCRC|INTMSK_DCRC|INTMSK_RTO|INTMSK_DTO|INTMSK_HTO|INTMSK_FRUN|INTMSK_HLE|INTMSK_SBE|INTMSK_EBE) /*BMOD register define */ -#define BMOD_SWR 0x00000001 -#define BMOD_DE 0x00000080 +#define BMOD_SWR 0x00000001 +#define BMOD_DE 0x00000080 /* for STATUS register */ -#define GET_FIFO_COUNT(x) (((x)&0x3ffe0000)>>17) +#define GET_FIFO_COUNT(x) (((x)&0x3ffe0000)>>17) #define GET_FIFO_DEPTH(x) ((((x)&0x0FFF0000)>>16)+1) /* for IDMA intr register */ @@ -122,62 +122,62 @@ enum { /* Define Card status bits (R1 response) */ #define R1CS_ADDRESS_OUT_OF_RANGE 0x80000000 -#define R1CS_ADDRESS_MISALIGN 0x40000000 -#define R1CS_BLOCK_LEN_ERR 0x20000000 -#define R1CS_ERASE_SEQ_ERR 0x10000000 -#define R1CS_ERASE_PARAM 0x08000000 -#define R1CS_WP_VIOLATION 0x04000000 -#define R1CS_CARD_IS_LOCKED 0x02000000 -#define R1CS_LCK_UNLCK_FAILED 0x01000000 -#define R1CS_COM_CRC_ERROR 0x00800000 -#define R1CS_ILLEGAL_COMMAND 0x00400000 -#define R1CS_CARD_ECC_FAILED 0x00200000 -#define R1CS_CC_ERROR 0x00100000 -#define R1CS_ERROR 0x00080000 -#define R1CS_UNDERRUN 0x00040000 -#define R1CS_OVERRUN 0x00020000 -#define R1CS_CSD_OVERWRITE 0x00010000 -#define R1CS_WP_ERASE_SKIP 0x00008000 -#define R1CS_RESERVED_0 0x00004000 -#define R1CS_ERASE_RESET 0x00002000 -#define R1CS_CURRENT_STATE_MASK 0x00001e00 -#define R1CS_READY_FOR_DATA 0x00000100 -#define R1CS_SWITCH_ERROR 0x00000080 -#define R1CS_RESERVED_1 0x00000040 -#define R1CS_APP_CMD 0x00000020 -#define R1CS_RESERVED_2 0x00000010 -#define R1CS_APP_SPECIFIC_MASK 0x0000000c -#define R1CS_MANUFAC_TEST_MASK 0x00000003 -#define R1CS_ERROR_OCCURED_MAP 0xfdffa080 -#define R1CS_CURRENT_STATE(x) (((x)&R1CS_CURRENT_STATE_MASK)>>9) +#define R1CS_ADDRESS_MISALIGN 0x40000000 +#define R1CS_BLOCK_LEN_ERR 0x20000000 +#define R1CS_ERASE_SEQ_ERR 0x10000000 +#define R1CS_ERASE_PARAM 0x08000000 +#define R1CS_WP_VIOLATION 0x04000000 +#define R1CS_CARD_IS_LOCKED 0x02000000 +#define R1CS_LCK_UNLCK_FAILED 0x01000000 +#define R1CS_COM_CRC_ERROR 0x00800000 +#define R1CS_ILLEGAL_COMMAND 0x00400000 +#define R1CS_CARD_ECC_FAILED 0x00200000 +#define R1CS_CC_ERROR 0x00100000 +#define R1CS_ERROR 0x00080000 +#define R1CS_UNDERRUN 0x00040000 +#define R1CS_OVERRUN 0x00020000 +#define R1CS_CSD_OVERWRITE 0x00010000 +#define R1CS_WP_ERASE_SKIP 0x00008000 +#define R1CS_RESERVED_0 0x00004000 +#define R1CS_ERASE_RESET 0x00002000 +#define R1CS_CURRENT_STATE_MASK 0x00001e00 +#define R1CS_READY_FOR_DATA 0x00000100 +#define R1CS_SWITCH_ERROR 0x00000080 +#define R1CS_RESERVED_1 0x00000040 +#define R1CS_APP_CMD 0x00000020 +#define R1CS_RESERVED_2 0x00000010 +#define R1CS_APP_SPECIFIC_MASK 0x0000000c +#define R1CS_MANUFAC_TEST_MASK 0x00000003 +#define R1CS_ERROR_OCCURED_MAP 0xfdffa080 +#define R1CS_CURRENT_STATE(x) (((x)&R1CS_CURRENT_STATE_MASK)>>9) /* R5 response */ -#define R5_IO_CRC_ERR 0x00008000 -#define R5_IO_BAD_CMD 0x00004000 -#define R5_IO_GEN_ERR 0x00000800 -#define R5_IO_FUNC_ERR 0x00000200 +#define R5_IO_CRC_ERR 0x00008000 +#define R5_IO_BAD_CMD 0x00004000 +#define R5_IO_GEN_ERR 0x00000800 +#define R5_IO_FUNC_ERR 0x00000200 #define R5_IO_OUT_RANGE 0x00000100 -#define R5_IO_ERR_BITS 0x0000cb00 +#define R5_IO_ERR_BITS 0x0000cb00 enum { - NONE_TYPE = 0, - SD_TYPE, - SD_2_0_TYPE, - SDIO_TYPE, + NONE_TYPE = 0, + SD_TYPE, + SD_2_0_TYPE, + SDIO_TYPE, }; enum { - CARD_STATE_EMPTY = -1, - CARD_STATE_IDLE = 0, - CARD_STATE_READY = 1, - CARD_STATE_IDENT = 2, - CARD_STATE_STBY = 3, - CARD_STATE_TRAN = 4, - CARD_STATE_DATA = 5, - CARD_STATE_RCV = 6, - CARD_STATE_PRG = 7, - CARD_STATE_DIS = 8, - CARD_STATE_INA = 9 + CARD_STATE_EMPTY = -1, + CARD_STATE_IDLE = 0, + CARD_STATE_READY = 1, + CARD_STATE_IDENT = 2, + CARD_STATE_STBY = 3, + CARD_STATE_TRAN = 4, + CARD_STATE_DATA = 5, + CARD_STATE_RCV = 6, + CARD_STATE_PRG = 7, + CARD_STATE_DIS = 8, + CARD_STATE_INA = 9 }; enum DmaDescriptorDES1 // Buffer's size field of Descriptor @@ -204,28 +204,28 @@ enum DmaDescriptorDES0 // Control and status word of DMA descriptor DES0 }; typedef struct DmaDescStruct { - unsigned int desc0; /* control and status information of descriptor */ - unsigned int desc1; /* buffer sizes */ - unsigned int desc2; /* physical address of the buffer 1 */ - unsigned int desc3; /* physical address of the buffer 2 */ + unsigned int desc0; /* control and status information of descriptor */ + unsigned int desc1; /* buffer sizes */ + unsigned int desc2; /* physical address of the buffer 1 */ + unsigned int desc3; /* physical address of the buffer 2 */ }DmaDesc; typedef struct { - unsigned int wkmod; - volatile DmaDesc *pDmaDesc; - unsigned int idma_support; - unsigned int rca; - unsigned int ip_base; - unsigned int card_type; - unsigned int fifo_depth; - unsigned int fifo_threth; - unsigned int sectors; - unsigned int scr[2]; - unsigned int csd[4]; - unsigned int idsts; - rt_sem_t sem; - rt_sem_t mutex; - void (*cb)(void); + unsigned int wkmod; + volatile DmaDesc *pDmaDesc; + unsigned int idma_support; + unsigned int rca; + unsigned int ip_base; + unsigned int card_type; + unsigned int fifo_depth; + unsigned int fifo_threth; + unsigned int sectors; + unsigned int scr[2]; + unsigned int csd[4]; + unsigned int idsts; + rt_sem_t sem; + rt_sem_t mutex; + void (*cb)(void); } sdc_t; #define ONE_BIT_MODE (0) @@ -244,55 +244,55 @@ typedef struct { enum { - ERRNOERROR = 0, - - // for raw interrupt status error - ERRRESPRECEP, // 1 - ERRRESPCRC, - ERRDCRC, - ERRRESPTIMEOUT, - ERRDRTIMEOUT, - ERRUNDERWRITE, - ERROVERREAD, - ERRHLE, - ERRSTARTBIT, - ERRENDBITERR, // 10 + ERRNOERROR = 0, - // for R1 response - ERRADDRESSRANGE, // 11 - ERRADDRESSMISALIGN, - ERRBLOCKLEN, - ERRERASESEQERR, - ERRERASEPARAM, - ERRPROT, - ERRCARDLOCKED, - ERRCRC, - ERRILLEGALCOMMAND, - ERRECCFAILED, - ERRCCERR, - ERRUNKNOWN, - ERRUNDERRUN, - ERROVERRUN, - ERRCSDOVERWRITE, - ERRERASERESET, - ERRFSMSTATE, // 27 + // for raw interrupt status error + ERRRESPRECEP, // 1 + ERRRESPCRC, + ERRDCRC, + ERRRESPTIMEOUT, + ERRDRTIMEOUT, + ERRUNDERWRITE, + ERROVERREAD, + ERRHLE, + ERRSTARTBIT, + ERRENDBITERR, // 10 - // for R5 response - ERRBADFUNC, // 28 + // for R1 response + ERRADDRESSRANGE, // 11 + ERRADDRESSMISALIGN, + ERRBLOCKLEN, + ERRERASESEQERR, + ERRERASEPARAM, + ERRPROT, + ERRCARDLOCKED, + ERRCRC, + ERRILLEGALCOMMAND, + ERRECCFAILED, + ERRCCERR, + ERRUNKNOWN, + ERRUNDERRUN, + ERROVERRUN, + ERRCSDOVERWRITE, + ERRERASERESET, + ERRFSMSTATE, // 27 - // others - ERRCARDNOTCONN, // 29 - ERRCARDWPROTECT, - ERRCMDRETRIESOVER, - ERRNOTSUPPORTED, - ERRHARDWARE, - ERRDATANOTREADY, - ERRCARDINTERNAL, - ERRACMD41TIMEOUT, - ERRIDMA, - ERRNORES, + // for R5 response + ERRBADFUNC, // 28 - ERRNOTEQUAL, + // others + ERRCARDNOTCONN, // 29 + ERRCARDWPROTECT, + ERRCMDRETRIESOVER, + ERRNOTSUPPORTED, + ERRHARDWARE, + ERRDATANOTREADY, + ERRCARDINTERNAL, + ERRACMD41TIMEOUT, + ERRIDMA, + ERRNORES, + + ERRNOTEQUAL, }; #ifdef __ASIC_BRANCH__ @@ -352,5 +352,5 @@ extern int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data extern void inv_dcache_range(unsigned long start, unsigned long len); extern void flush_dcache_range(unsigned long start, unsigned long len); - + #endif //__sdcard_h__ diff --git a/bsp/fh8620/libraries/inc/fh_spi.h b/bsp/fh8620/libraries/inc/fh_spi.h index d81c2428bc..689a85b3f4 100644 --- a/bsp/fh8620/libraries/inc/fh_spi.h +++ b/bsp/fh8620/libraries/inc/fh_spi.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_SPI_H_ #define FH_SPI_H_ @@ -97,8 +97,8 @@ #define SPI_STATUS_BUSY (1) -#define SPI_TX_DMA (1<<1) -#define SPI_RX_DMA (1<<0) +#define SPI_TX_DMA (1<<1) +#define SPI_RX_DMA (1<<0) struct spi_config diff --git a/bsp/fh8620/libraries/inc/fh_timer.h b/bsp/fh8620/libraries/inc/fh_timer.h index 715a73b252..9f88bff22e 100644 --- a/bsp/fh8620/libraries/inc/fh_timer.h +++ b/bsp/fh8620/libraries/inc/fh_timer.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,7 +29,7 @@ /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ #include "fh_def.h" @@ -38,7 +38,7 @@ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ #define TIMER_CTRL_ENABLE (1u << 0) #define TIMER_CTRL_MODE (1u << 1) @@ -49,19 +49,19 @@ /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef struct { - RwReg TIMER_LOAD_COUNT; - RwReg TIMER_CURRENT_VALUE; - RwReg TIMER_CTRL_REG; - RwReg TIMER_EOI; - RwReg TIMER_INT_STATUS; + RwReg TIMER_LOAD_COUNT; + RwReg TIMER_CURRENT_VALUE; + RwReg TIMER_CTRL_REG; + RwReg TIMER_EOI; + RwReg TIMER_INT_STATUS; }timer; enum timer_mode { - TIMER_MODE_PERIODIC = 0, - TIMER_MODE_ONESHOT = 1, + TIMER_MODE_PERIODIC = 0, + TIMER_MODE_ONESHOT = 1, }; @@ -73,7 +73,7 @@ typedef struct { /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ diff --git a/bsp/fh8620/libraries/inc/fh_uart.h b/bsp/fh8620/libraries/inc/fh_uart.h index 87da9ee2f7..34d2a9bb9a 100644 --- a/bsp/fh8620/libraries/inc/fh_uart.h +++ b/bsp/fh8620/libraries/inc/fh_uart.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,13 +29,13 @@ /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ #include "fh_def.h" /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ #define UART_RBR RBRTHRDLL @@ -120,53 +120,53 @@ #define UART_IIR_FIFOSE (0x03 << 6) //uart baudrate cofig -//#define UART_CLOCK_FREQ (27000000) //27MHZ +//#define UART_CLOCK_FREQ (27000000) //27MHZ // -//#define DIV(n) (((UART_CLOCK_FREQ/(n))+8)/16) +//#define DIV(n) (((UART_CLOCK_FREQ/(n))+8)/16) /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef struct { - RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */ - RwReg DLHIER; /* UART_DLH, UART_IER */ - RwReg IIRFCR; /* UART_IIR, UART_FCR */ - RwReg UART_LCR; /*(0x000c) */ - RwReg UART_MCR; /*(0x0010) */ - RwReg UART_LSR; /*(0x0014) */ - RwReg UART_MSR; /*(0x0018) */ - RwReg UART_SCR; /*(0x001c) */ - RwReg reserved[20]; - RwReg UART_FAR; /* (0x0070) */ - RwReg UART_TFR; /* (0x0074) */ - RwReg UART_RFW; /* (0x0078) */ - RwReg UART_USR; /* (0x007c) */ - RwReg UART_TFL; /* (0x0080) */ - RwReg UART_RFL; /* (0x0084) */ - RwReg UART_SRR; /* (0x0088) */ - RwReg reserved1[3]; - RwReg UART_SFE; /* (0x0098) */ - RwReg UART_SRT; /* (0x009c) */ - RwReg UART_STET; /* (0x00a0) */ - RwReg UART_HTX; /* (0x00a4) */ - RwReg UART_DMASA; /* (0x00a8) */ - RwReg reserved2[18]; - RwReg UART_CPR; /* (0x00f4) */ - RwReg UART_UCV; /* (0x00f8) */ - RwReg UART_CTR; /* (0x00fc) */ + RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */ + RwReg DLHIER; /* UART_DLH, UART_IER */ + RwReg IIRFCR; /* UART_IIR, UART_FCR */ + RwReg UART_LCR; /*(0x000c) */ + RwReg UART_MCR; /*(0x0010) */ + RwReg UART_LSR; /*(0x0014) */ + RwReg UART_MSR; /*(0x0018) */ + RwReg UART_SCR; /*(0x001c) */ + RwReg reserved[20]; + RwReg UART_FAR; /* (0x0070) */ + RwReg UART_TFR; /* (0x0074) */ + RwReg UART_RFW; /* (0x0078) */ + RwReg UART_USR; /* (0x007c) */ + RwReg UART_TFL; /* (0x0080) */ + RwReg UART_RFL; /* (0x0084) */ + RwReg UART_SRR; /* (0x0088) */ + RwReg reserved1[3]; + RwReg UART_SFE; /* (0x0098) */ + RwReg UART_SRT; /* (0x009c) */ + RwReg UART_STET; /* (0x00a0) */ + RwReg UART_HTX; /* (0x00a4) */ + RwReg UART_DMASA; /* (0x00a8) */ + RwReg reserved2[18]; + RwReg UART_CPR; /* (0x00f4) */ + RwReg UART_UCV; /* (0x00f8) */ + RwReg UART_CTR; /* (0x00fc) */ }uart; struct fh_uart { - uart *uart_port; - int irq; + uart *uart_port; + int irq; }; @@ -174,34 +174,34 @@ struct fh_uart { enum data_bits { - UART_DATA_BIT5 = 0, - UART_DATA_BIT6 = 1, - UART_DATA_BIT7 = 2, - UART_DATA_BIT8 = 3 + UART_DATA_BIT5 = 0, + UART_DATA_BIT6 = 1, + UART_DATA_BIT7 = 2, + UART_DATA_BIT8 = 3 }; enum stop_bits { - UART_STOP_BIT1 = 0, - UART_STOP_BIT1_5 = 1, - UART_STOP_BIT2 = 2 + UART_STOP_BIT1 = 0, + UART_STOP_BIT1_5 = 1, + UART_STOP_BIT2 = 2 }; enum parity { - UART_PARITY_NONE = 0, - UART_PARITY_EVEN = 1, - UART_PARITY_ODD = 2, - UART_PARITY_ST = 3 /* Stick Parity */ + UART_PARITY_NONE = 0, + UART_PARITY_EVEN = 1, + UART_PARITY_ODD = 2, + UART_PARITY_ST = 3 /* Stick Parity */ }; -#define UART_CLOCK_FREQ (30000000) //30MHZ +#define UART_CLOCK_FREQ (30000000) //30MHZ typedef enum enum_uart_baudrate{ - BAUDRATE_9600 = (((UART_CLOCK_FREQ/9600)+8)/16), - BAUDRATE_19200 = (((UART_CLOCK_FREQ/19200)+8)/16), - BAUDRATE_38400 = (((UART_CLOCK_FREQ/38400)+8)/16), - BAUDRATE_57600 = (((UART_CLOCK_FREQ/57600)+8)/16), - BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16), - BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16), + BAUDRATE_9600 = (((UART_CLOCK_FREQ/9600)+8)/16), + BAUDRATE_19200 = (((UART_CLOCK_FREQ/19200)+8)/16), + BAUDRATE_38400 = (((UART_CLOCK_FREQ/38400)+8)/16), + BAUDRATE_57600 = (((UART_CLOCK_FREQ/57600)+8)/16), + BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16), + BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16), }uart_baudrate_e; /**************************************************************************** @@ -213,8 +213,8 @@ extern int uart_init(uart *port); extern UINT32 uart_get_status(uart *port); extern void uart_configure(uart *port, enum data_bits data_bit, - enum stop_bits stop_bit, enum parity parity, - UINT32 buard_rate, UINT32 uart_clk); + enum stop_bits stop_bit, enum parity parity, + UINT32 buard_rate, UINT32 uart_clk); extern int uart_enable_irq(uart *port, UINT32 mode); @@ -235,7 +235,7 @@ extern void uart_set_fifo_mode(uart *port, UINT32 fifo_mode); /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ diff --git a/bsp/fh8620/libraries/inc/fh_wdt.h b/bsp/fh8620/libraries/inc/fh_wdt.h index a90331dbd5..7804a3a536 100644 --- a/bsp/fh8620/libraries/inc/fh_wdt.h +++ b/bsp/fh8620/libraries/inc/fh_wdt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_WDT_H_ #define FH_WDT_H_ diff --git a/bsp/fh8620/platform/board.h b/bsp/fh8620/platform/board.h index 46b276b052..ac8708ec9e 100644 --- a/bsp/fh8620/platform/board.h +++ b/bsp/fh8620/platform/board.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef __BOARD_H__ #define __BOARD_H__ #include "platform_def.h" diff --git a/bsp/fh8620/platform/board_info.h b/bsp/fh8620/platform/board_info.h index 71f8d3c19e..d86907621f 100644 --- a/bsp/fh8620/platform/board_info.h +++ b/bsp/fh8620/platform/board_info.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef __BOARD_INFO_H__ #define __BOARD_INFO_H__ @@ -33,32 +33,32 @@ extern "C" { /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef int (*probe_p)(void *); typedef int (*exit_p)(void *); struct fh_board_ops { - //void *ops_data; - probe_p probe; - probe_p exit; + //void *ops_data; + probe_p probe; + probe_p exit; }; struct fh_board_info { - char *name; - void *data; - struct fh_board_ops *ops; + char *name; + void *data; + struct fh_board_ops *ops; }; @@ -73,7 +73,7 @@ void fh_print_all_board_info(void); void fh_free_all_info(void); /**************************************************************************** * section - * add function prototype here if any + * add function prototype here if any ***************************************************************************/ #ifdef __cplusplus diff --git a/bsp/fh8620/platform/common/board_info.c b/bsp/fh8620/platform/common/board_info.c index aa56cbac62..6bb95bfaa9 100644 --- a/bsp/fh8620/platform/common/board_info.c +++ b/bsp/fh8620/platform/common/board_info.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -36,27 +36,27 @@ * add all #define here *****************************************************************************/ struct fh_board_info_list_node { - struct fh_board_info obj; - rt_list_t list; + struct fh_board_info obj; + rt_list_t list; }; -#define CHECK_TEST_LIST_EMPTY \ - if(rt_list_isempty(&board_info_head.list)) \ - rt_kprintf("board info is null...please register first..\n") +#define CHECK_TEST_LIST_EMPTY \ + if(rt_list_isempty(&board_info_head.list)) \ + rt_kprintf("board info is null...please register first..\n") /**************************************************************************** * ADT section * add definition of user defined Data Type that only be used in this file here ***************************************************************************/ -#define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ - n = rt_list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ + n = rt_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) -#define PARA_ERROR (-1) -#define PROBE_FUNC_MISS (-2) +#define PARA_ERROR (-1) +#define PROBE_FUNC_MISS (-2) /****************************************************************************** * Function prototype section @@ -104,45 +104,45 @@ static struct fh_board_info_list_node board_info_head; int fh_board_info_init(void) { - memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node)); - rt_list_init(&board_info_head.list); - board_info_head.obj.name = "NO INFO"; - return 0; + memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node)); + rt_list_init(&board_info_head.list); + board_info_head.obj.name = "NO INFO"; + return 0; } void fh_free_all_info(void) { - rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - CHECK_TEST_LIST_EMPTY; + CHECK_TEST_LIST_EMPTY; - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { - if (info_node->obj.ops->exit) { - info_node->obj.ops->exit(info_node->obj.data); - } - rt_kprintf("soc free list name:(%s)\n", info_node->obj.name); - rt_free(info_node); - } - fh_board_info_init(); + if (info_node->obj.ops->exit) { + info_node->obj.ops->exit(info_node->obj.data); + } + rt_kprintf("soc free list name:(%s)\n", info_node->obj.name); + rt_free(info_node); + } + fh_board_info_init(); } void fh_print_all_board_info(void) { - rt_list_t *p_list; + rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - CHECK_TEST_LIST_EMPTY; + CHECK_TEST_LIST_EMPTY; - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - rt_kprintf("%s\n", info_node->obj.name); - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + rt_kprintf("%s\n", info_node->obj.name); + } } /***************************************************************************** @@ -157,94 +157,94 @@ void fh_print_all_board_info(void) { //register the platform info such as base add,isr no.. //caution:do not free the name and data because of here not copy struct fh_board_info *fh_board_info_register(char *info_name, void *data) { - rt_list_t *p_list; - struct fh_board_info_list_node *new_node; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *new_node; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - if (RT_NULL == info_name || RT_NULL == data) { - rt_kprintf("info name or info data is NULL!\n"); - return RT_NULL; - } + if (RT_NULL == info_name || RT_NULL == data) { + rt_kprintf("info name or info data is NULL!\n"); + return RT_NULL; + } - //check if the func is already in the test list.... + //check if the func is already in the test list.... #if(0) - list_for_each_entry_safe(info_node, _info_node, p_list, list) { - if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) { - rt_kprintf("info_name(%s) is already registered\n", info_name); - return RT_NULL; - } - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) { + if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) { + rt_kprintf("info_name(%s) is already registered\n", info_name); + return RT_NULL; + } + } #endif - new_node = (struct fh_board_info_list_node *) rt_malloc( - sizeof(struct fh_board_info_list_node)); - if (!new_node) { - rt_kprintf("malloc new_list_node failed~\n"); - return RT_NULL; - } + new_node = (struct fh_board_info_list_node *) rt_malloc( + sizeof(struct fh_board_info_list_node)); + if (!new_node) { + rt_kprintf("malloc new_list_node failed~\n"); + return RT_NULL; + } - new_node->obj.name = info_name; - new_node->obj.data = data; - //here insert "before" and test is "after" will make the list like a fifo... - rt_list_insert_before(&board_info_head.list, &new_node->list); - return &new_node->obj; + new_node->obj.name = info_name; + new_node->obj.data = data; + //here insert "before" and test is "after" will make the list like a fifo... + rt_list_insert_before(&board_info_head.list, &new_node->list); + return &new_node->obj; } //back the platform info static void *fh_get_board_info_data(char *info_name) { - rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - //check info name - if (RT_NULL == info_name) { - rt_kprintf("info name is NULL!\n"); - return RT_NULL; - } + //check info name + if (RT_NULL == info_name) { + rt_kprintf("info name is NULL!\n"); + return RT_NULL; + } - CHECK_TEST_LIST_EMPTY; + CHECK_TEST_LIST_EMPTY; - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - if (!strcmp(info_node->obj.name, info_name)) { - return info_node->obj.data; - } - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + if (!strcmp(info_node->obj.name, info_name)) { + return info_node->obj.data; + } + } - rt_kprintf("Can't find the board info name:%s\n", info_name); + rt_kprintf("Can't find the board info name:%s\n", info_name); } int fh_board_driver_register(char *info_name, struct fh_board_ops *ops) { - rt_list_t *p_list; - struct fh_board_info_list_node *new_node; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *new_node; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - if (RT_NULL == info_name || RT_NULL == ops) { - rt_kprintf("info name or ops func is NULL!\n"); - return PARA_ERROR; - } + if (RT_NULL == info_name || RT_NULL == ops) { + rt_kprintf("info name or ops func is NULL!\n"); + return PARA_ERROR; + } - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - if (!strcmp(info_node->obj.name, info_name)) { + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + if (!strcmp(info_node->obj.name, info_name)) { - info_node->obj.ops = ops; - if (info_node->obj.ops->probe) { - info_node->obj.ops->probe(info_node->obj.data); - } + info_node->obj.ops = ops; + if (info_node->obj.ops->probe) { + info_node->obj.ops->probe(info_node->obj.data); + } - //return info_node->obj.data; - } - } + //return info_node->obj.data; + } + } - //rt_kprintf("Can't find the board info name:%s\n",info_name); + //rt_kprintf("Can't find the board info name:%s\n",info_name); - return 0; + return 0; } diff --git a/bsp/fh8620/platform/common/chkenv.c b/bsp/fh8620/platform/common/chkenv.c index 563b5bb55a..e2d8f18b22 100644 --- a/bsp/fh8620/platform/common/chkenv.c +++ b/bsp/fh8620/platform/common/chkenv.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -47,11 +47,11 @@ * * **************************/ -#if RT_NAME_MAX != 16 +#if RT_NAME_MAX != 16 #error "define RT_NAME_MAX 16" #endif -#if RT_TICK_PER_SECOND != 100 +#if RT_TICK_PER_SECOND != 100 #warning "RT_TICK_PER_SECOND = 100" #endif diff --git a/bsp/fh8620/platform/fh8620/arch.h b/bsp/fh8620/platform/fh8620/arch.h index df0e7f1965..306c1239e8 100644 --- a/bsp/fh8620/platform/fh8620/arch.h +++ b/bsp/fh8620/platform/fh8620/arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ARCH_H_ #define ARCH_H_ @@ -31,37 +31,37 @@ /*****************************/ /* BSP CONTROLLER BASE */ /*****************************/ -#define INTC_REG_BASE (0xE0200000) -#define SDC0_REG_BASE (0xE2000000) -#define SDC1_REG_BASE (0xE2100000) -#define TVE_REG_BASE (0xE8000000) -#define VOU_REG_BASE (0xE8100000) -#define AES_REG_BASE (0xE8200000) -#define JPEG_REG_BASE (0xE8300000) -#define ISPB_REG_BASE (0xEA000000) -#define ISPF_REG_BASE (0xEA100000) -#define VPU_REG_BASE (0xEC000000) -#define VCU_REG_BASE (0xEC100000) -#define DDRC_REG_BASE (0xED000000) -#define DMAC_REG_BASE (0xEE000000) -#define GMAC_REG_BASE (0xEF000000) -#define PMU_REG_BASE (0xF0000000) -#define I2C0_REG_BASE (0xF0200000) -#define GPIO0_REG_BASE (0xF0300000) +#define INTC_REG_BASE (0xE0200000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2100000) +#define TVE_REG_BASE (0xE8000000) +#define VOU_REG_BASE (0xE8100000) +#define AES_REG_BASE (0xE8200000) +#define JPEG_REG_BASE (0xE8300000) +#define ISPB_REG_BASE (0xEA000000) +#define ISPF_REG_BASE (0xEA100000) +#define VPU_REG_BASE (0xEC000000) +#define VCU_REG_BASE (0xEC100000) +#define DDRC_REG_BASE (0xED000000) +#define DMAC_REG_BASE (0xEE000000) +#define GMAC_REG_BASE (0xEF000000) +#define PMU_REG_BASE (0xF0000000) +#define I2C0_REG_BASE (0xF0200000) +#define GPIO0_REG_BASE (0xF0300000) #define GPIO1_REG_BASE (0xf4000000) -#define PWM_REG_BASE (0xF0400000) -#define SPI0_REG_BASE (0xF0500000) -#define SPI1_REG_BASE (0xF0600000) -#define UART0_REG_BASE (0xF0700000) -#define UART1_REG_BASE (0xF0800000) -#define I2S_REG_BASE (0xF0900000) -#define ACODEC_REG_BASE (0xF0A00000) -#define I2C1_REG_BASE (0xF0B00000) -#define TMR_REG_BASE (0xF0C00000) -#define WDT_REG_BASE (0xF0D00000) -#define DPHY_REG_BASE (0xF1000000) -#define MIPIC_REG_BASE (0xF1100000) -#define SADC_REG_BASE (0xF1200000) +#define PWM_REG_BASE (0xF0400000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define I2S_REG_BASE (0xF0900000) +#define ACODEC_REG_BASE (0xF0A00000) +#define I2C1_REG_BASE (0xF0B00000) +#define TMR_REG_BASE (0xF0C00000) +#define WDT_REG_BASE (0xF0D00000) +#define DPHY_REG_BASE (0xF1000000) +#define MIPIC_REG_BASE (0xF1100000) +#define SADC_REG_BASE (0xF1200000) diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board.c b/bsp/fh8620/platform/fh8620/iot_cam/board.c index 8e45b9be90..a726ce5efe 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/board.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/board.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -67,15 +67,15 @@ #ifndef HW_SDCARD_POWER_GPIO - #define HW_SDCARD_POWER_GPIO 63 //not used + #define HW_SDCARD_POWER_GPIO 63 //not used #endif /**************************************************************************** * ADT section * add definition of user defined Data Type that only be used in this file here ***************************************************************************/ struct st_platform_info { - char *name; - void *private_data; + char *name; + void *private_data; }; /****************************************************************************** @@ -101,14 +101,14 @@ struct st_platform_info { void fh_mmc_reset(struct fh_mmc_obj *mmc_obj) { - rt_uint32_t value; - if (mmc_obj->id) - fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd); - else - fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb); - do { - fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value); - } while (value != 0xffffffff); + rt_uint32_t value; + if (mmc_obj->id) + fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd); + else + fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb); + do { + fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value); + } while (value != 0xffffffff); } static struct fh_mmc_obj mmc0_obj = @@ -130,8 +130,8 @@ static struct fh_mmc_obj mmc1_obj = }; #ifdef RT_USING_SPI -#define SPI0_CLK_IN (50000000) -#define SPI0_MAX_BAUD (SPI0_CLK_IN/2) +#define SPI0_CLK_IN (50000000) +#define SPI0_MAX_BAUD (SPI0_CLK_IN/2) static struct spi_control_platform_data spi0_platform_data = { @@ -152,8 +152,8 @@ static struct spi_control_platform_data spi0_platform_data = }; -#define SPI1_CLK_IN (50000000) -#define SPI1_MAX_BAUD (SPI1_CLK_IN/2) +#define SPI1_CLK_IN (50000000) +#define SPI1_MAX_BAUD (SPI1_CLK_IN/2) static struct spi_control_platform_data spi1_platform_data = { @@ -217,10 +217,10 @@ static struct fh_wdt_obj wdt_obj = #ifdef RT_USING_SADC static struct wrap_sadc_obj sadc_obj = { - .id = 0, - .regs = (void *)SADC_REG_BASE, - .irq_no = SADC_IRQn, - .sample_mode = ISR_MODE, + .id = 0, + .regs = (void *)SADC_REG_BASE, + .irq_no = SADC_IRQn, + .sample_mode = ISR_MODE, }; #endif @@ -366,8 +366,8 @@ struct st_platform_info plat_sadc = #endif const static struct st_platform_info *platform_info[] = { - &plat_mmc0, - //&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework... + &plat_mmc0, + //&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework... #ifdef RT_USING_SPI &plat_spi0, #endif @@ -400,168 +400,168 @@ const static struct st_platform_info *platform_info[] = { void clock_init(void) { - //UINT32 reg; - //gate enable, spi0, gmac, uart0, timer0, wdt, pts + //UINT32 reg; + //gate enable, spi0, gmac, uart0, timer0, wdt, pts #ifdef YG_TEK - fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000); + fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000); #endif - //SPI0 - fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff); + //SPI0 + fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff); - //GMAC - fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000); + //GMAC + fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000); - //UART0 - fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf); + //UART0 + fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf); - //TIMER0 - fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000); + //TIMER0 + fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000); - //PTS - fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f); + //PTS + fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f); - //WDT - //fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00); - fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00); + //WDT + //fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00); + fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00); - //clock enable - fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080); + //clock enable + fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080); //sd0_drv_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000); + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000); //sd0_sample_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000); + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000); - //sd1_drv_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000); - //sd1_sample_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300); + //sd1_drv_sel + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000); + //sd1_sample_sel + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300); } void fh_platform_info_register(void){ - struct fh_board_info *test_info; - int i; + struct fh_board_info *test_info; + int i; - for(i=0;i<sizeof(platform_info)/sizeof(struct st_platform_info *);i++){ - test_info = fh_board_info_register(platform_info[i]->name,platform_info[i]->private_data); - if(!test_info){ - rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name); - } - } + for(i=0;i<sizeof(platform_info)/sizeof(struct st_platform_info *);i++){ + test_info = fh_board_info_register(platform_info[i]->name,platform_info[i]->private_data); + if(!test_info){ + rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name); + } + } } void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); - //add iomux init 2015-3-11 by yu.zhang for fh81(fullhan) - //iomux_init(); + /* initialize the system clock */ + rt_hw_clock_init(); + //add iomux init 2015-3-11 by yu.zhang for fh81(fullhan) + //iomux_init(); fh_iomux_init(PMU_REG_BASE + 0x5c); - //add clk init 2015-3-11 by yu.zhang for fh81(fullhan) - clock_init(); - /* initialize uart */ - rt_hw_uart_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - /* initialize timer1 */ - rt_hw_timer_init(); - //board data info init... - fh_board_info_init(); - fh_platform_info_register(); + //add clk init 2015-3-11 by yu.zhang for fh81(fullhan) + clock_init(); + /* initialize uart */ + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + /* initialize timer1 */ + rt_hw_timer_init(); + //board data info init... + fh_board_info_init(); + fh_platform_info_register(); } void rt_board_driver_init(){ - //add board init lock here... - /*rt_show_version();*/ - int ret; + //add board init lock here... + /*rt_show_version();*/ + int ret; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); - rt_kprintf("DFS initialized!\n"); + { + /* init the device filesystem */ + dfs_init(); + rt_kprintf("DFS initialized!\n"); #if defined(RT_USING_DFS_ELMFAT) - /* init the elm chan FatFs filesystam*/ - elm_init(); - rt_kprintf("ELM initialized!\n"); + /* init the elm chan FatFs filesystam*/ + elm_init(); + rt_kprintf("ELM initialized!\n"); #endif #if defined(RT_USING_DFS_ROMFS) - dfs_romfs_init(); - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + dfs_romfs_init(); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_DEVFS) - devfs_init(); - if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) - rt_kprintf("Device File System initialized!\n"); - else - rt_kprintf("Device File System initialzation failed!\n"); + devfs_init(); + if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) + rt_kprintf("Device File System initialized!\n"); + else + rt_kprintf("Device File System initialzation failed!\n"); - #ifdef RT_USING_NEWLIB - /* init libc */ - libc_system_init(RT_CONSOLE_DEVICE_NAME); - #endif + #ifdef RT_USING_NEWLIB + /* init libc */ + libc_system_init(RT_CONSOLE_DEVICE_NAME); + #endif #endif #if defined(RT_USING_DFS_UFFS) - { - /* init the uffs filesystem */ - dfs_uffs_init(); + { + /* init the uffs filesystem */ + dfs_uffs_init(); - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_DFS_RAMFS - dfs_ramfs_init(); - { - rt_uint8_t *ramfs_pool = RT_NULL; - struct dfs_ramfs* ramfs; - ramfs_pool = rt_malloc(0x800000); - if(ramfs_pool) - { - ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000); - if (ramfs != RT_NULL) - { - if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0) - { - rt_kprintf("Mount RAMDisk done!\n"); - } - else - { - rt_kprintf("Mount RAMDisk failed.\n"); - } - } - } - else - { - rt_kprintf("alloc ramfs poll failed\n"); - } - } + dfs_ramfs_init(); + { + rt_uint8_t *ramfs_pool = RT_NULL; + struct dfs_ramfs* ramfs; + ramfs_pool = rt_malloc(0x800000); + if(ramfs_pool) + { + ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000); + if (ramfs != RT_NULL) + { + if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0) + { + rt_kprintf("Mount RAMDisk done!\n"); + } + else + { + rt_kprintf("Mount RAMDisk failed.\n"); + } + } + } + else + { + rt_kprintf("alloc ramfs poll failed\n"); + } + } #endif - } + } #endif /* Filesystem Initialization end*/ #ifdef RT_USING_GPIO { rt_hw_gpio_init(); - rt_kprintf("GPIO initialized!\n"); + rt_kprintf("GPIO initialized!\n"); #ifdef RT_USING_SDIO //wifi @@ -572,7 +572,7 @@ void rt_board_driver_init(){ //micro sd gpio_request(HW_SDCARD_POWER_GPIO); gpio_direction_output(HW_SDCARD_POWER_GPIO, 0); - rt_kprintf("SDIO initialized!\n"); + rt_kprintf("SDIO initialized!\n"); #endif //sensor gpio_request(HW_CIS_RST_GPIO); @@ -585,7 +585,7 @@ void rt_board_driver_init(){ #ifdef RT_USING_SDIO #ifndef RT_USING_WIFI_MARVEL rt_hw_mmc_init(); - rt_kprintf("MMC initialized!\n"); + rt_kprintf("MMC initialized!\n"); rt_thread_delay(RT_TICK_PER_SECOND*2); /* mount sd card fat partition 1 as root directory */ #ifdef RT_USING_DFS_ELMFAT @@ -601,56 +601,56 @@ void rt_board_driver_init(){ #ifdef RT_USING_FH_DMA - { + { rt_fh_dma_init(); - rt_kprintf("DMA initialized!\n"); - } + rt_kprintf("DMA initialized!\n"); + } #endif #ifdef RT_USING_FH_ACW - { - fh_audio_init(); - rt_kprintf("AUDIO initialized!\n"); - } + { + fh_audio_init(); + rt_kprintf("AUDIO initialized!\n"); + } #endif #ifdef RT_USING_LWIP - { - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("LWIP SYS initialized!\n"); - eth_system_device_init(); - rt_kprintf("ETH initialized!\n"); - } + { + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("LWIP SYS initialized!\n"); + eth_system_device_init(); + rt_kprintf("ETH initialized!\n"); + } #endif #ifdef RT_USING_GMAC /* register ethernetif device */ rt_app_fh_gmac_init(); - rt_kprintf("GMAC initialized!\n"); + rt_kprintf("GMAC initialized!\n"); #endif #ifdef RT_USING_I2C - { - rt_hw_i2c_init(); - rt_kprintf("I2C initialized!\n"); - } + { + rt_hw_i2c_init(); + rt_kprintf("I2C initialized!\n"); + } #endif #ifdef RT_USING_PWM { rt_hw_pwm_init(); - rt_kprintf("PWM initialized!\n"); + rt_kprintf("PWM initialized!\n"); } #endif #ifdef RT_USING_WDT { rt_hw_wdt_init(); - rt_kprintf("WDT initialized!\n"); + rt_kprintf("WDT initialized!\n"); } #endif @@ -658,7 +658,7 @@ void rt_board_driver_init(){ #ifdef RT_USING_SPI { rt_hw_spi_init(); - rt_kprintf("SPI initialized!\n"); + rt_kprintf("SPI initialized!\n"); } #endif @@ -668,21 +668,21 @@ void rt_board_driver_init(){ rt_kprintf("FLASH initialized!\n"); #endif - rt_kprintf("init done\n"); + rt_kprintf("init done\n"); #ifdef RT_USING_SADC rt_hw_sadc_init(); - rt_kprintf("SADC initialized!\n"); + rt_kprintf("SADC initialized!\n"); #endif #ifdef RT_USING_ENC28J60 - gpio_request(ENC28J60_INT); - gpio_direction_input(ENC28J60_INT); - gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING); - rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL); - gpio_irq_enable(gpio_to_irq(ENC28J60_INT)); - gpio_release(ENC28J60_INT); + gpio_request(ENC28J60_INT); + gpio_direction_input(ENC28J60_INT); + gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING); + rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL); + gpio_irq_enable(gpio_to_irq(ENC28J60_INT)); + gpio_release(ENC28J60_INT); - enc28j60_attach(ENC28J60_SPI_DEV); + enc28j60_attach(ENC28J60_SPI_DEV); #endif } diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h index 48551b7095..902375f429 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h +++ b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,18 +18,18 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef BOARD_DEF_H_ #define BOARD_DEF_H_ /* *********************** - * SECTION: DRIVE + * SECTION: DRIVE * ***********************/ // Basic drive.. #define RT_USING_UART1 @@ -49,22 +49,22 @@ #define CONFIG_PLAT_V2 #ifndef FH_DDR_START -#define FH_DDR_START 0xA0000000 -#define FH_DDR_END 0xA1000000 +#define FH_DDR_START 0xA0000000 +#define FH_DDR_END 0xA1000000 -#define FH_RTT_OS_MEM_SIZE 0x00600000 -#define FH_DMA_MEM_SIZE 0x20000 /* 128k */ +#define FH_RTT_OS_MEM_SIZE 0x00600000 +#define FH_DMA_MEM_SIZE 0x20000 /* 128k */ -#define FH_RTT_OS_MEM_END (FH_DDR_START + FH_RTT_OS_MEM_SIZE) -#define FH_SDK_MEM_START (FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE) -#define FH_RTT_OS_HEAP_END FH_SDK_MEM_START -#define FH_SDK_MEM_SIZE (FH_DDR_END - FH_SDK_MEM_START) +#define FH_RTT_OS_MEM_END (FH_DDR_START + FH_RTT_OS_MEM_SIZE) +#define FH_SDK_MEM_START (FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE) +#define FH_RTT_OS_HEAP_END FH_SDK_MEM_START +#define FH_SDK_MEM_SIZE (FH_DDR_END - FH_SDK_MEM_START) #endif /* end of FH_DDR_START*/ - + /* *********************** - * SECTION: DRIVE COMPONENT + * SECTION: DRIVE COMPONENT * ***********************/ -#define UART_NAME "uart1" +#define UART_NAME "uart1" #define RT_USING_DMA_MEM #define RT_USING_MCI0 diff --git a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c index ee0bb63260..dc699c4450 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,650 +18,650 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdef.h" #include "iomux.h" #include "rtconfig.h" Iomux_Pad fh_iomux_cfg[] = { - { - .func_name = { "RESETN", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "TEST", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "CIS_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "CIS_HSYNC", "GPIO20", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_VSYNC", "GPIO21", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_PCLK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 0, - }, - { - .func_name = { "CIS_D0", "GPIO22", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D1", "GPIO23", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D2", "GPIO24", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D3", "GPIO25", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D4", "GPIO26", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D5", "GPIO27", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D6", "GPIO28", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D7", "GPIO29", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D8", "GPIO30", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D9", "GPIO31", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D10", "GPIO32", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D11", "GPIO33", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_REF_CLK", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 3, - }, - { - .func_name = { "MAC_MDC", "GPIO34", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 0, - }, - { - .func_name = { "MAC_MDIO", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_COL", "GPIO35", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_CRS", "GPIO36", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXCK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "MAC_RXD0", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, + { + .func_name = { "RESETN", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "TEST", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "CIS_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "CIS_HSYNC", "GPIO20", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_VSYNC", "GPIO21", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_PCLK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 0, + }, + { + .func_name = { "CIS_D0", "GPIO22", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D1", "GPIO23", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D2", "GPIO24", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D3", "GPIO25", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D4", "GPIO26", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D5", "GPIO27", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D6", "GPIO28", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D7", "GPIO29", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D8", "GPIO30", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D9", "GPIO31", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D10", "GPIO32", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D11", "GPIO33", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_REF_CLK", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 3, + }, + { + .func_name = { "MAC_MDC", "GPIO34", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 0, + }, + { + .func_name = { "MAC_MDIO", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_COL", "GPIO35", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_CRS", "GPIO36", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXCK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "MAC_RXD0", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, - { - .func_name = { "MAC_RXD1", "GPIO38", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXD2", "GPIO39", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXD3", "GPIO40", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXDV", "GPIO41", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXCK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "MAC_TXD0", "GPIO42", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD1", "GPIO43", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD2", "GPIO44", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD3", "GPIO45", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXEN", "GPIO46", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXER", "GPIO47", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TCK", "GPIO5", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TRSTN", "GPIO6", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TMS", "GPIO7", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TDI", "GPIO8", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TDO", "GPIO9", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO10", "UART1_OUT", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "GPIO11", "UART1_IN", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "GPIO12", "PWM_OUT0", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO13", "PWM_OUT1", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO14", "PWM_OUT2", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", }, - .reg_type = 13, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", }, - .reg_type = 13, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", }, - .reg_type = 21, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SDA1", "GPIO51", "I2S_DO", "", }, - .reg_type = 21, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_TXD", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CSN0", "GPIO54", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CSN1", "GPIO55", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_RXD", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "SD0_CD", "GPIO52", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD0_WP", "GPIO53", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD0_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 3, - }, - { - .func_name = { "SD0_CMD_RSP", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA0", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA1", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 2, - }, - { - .func_name = { "SD0_DATA2", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA3", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_CLK", "SSI1_CLK", "", "", }, - .reg_type = 8, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SD1_CD", "GPIO_58", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD1_WP", "GPIO_59", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD1_DATA0", "SSI1_TXD", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA3", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "CLK_SW0", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW1", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW2", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW3", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "MAC_TXER", "GPIO37", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, + { + .func_name = { "MAC_RXD1", "GPIO38", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXD2", "GPIO39", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXD3", "GPIO40", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXDV", "GPIO41", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXCK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "MAC_TXD0", "GPIO42", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD1", "GPIO43", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD2", "GPIO44", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD3", "GPIO45", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXEN", "GPIO46", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXER", "GPIO47", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TCK", "GPIO5", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TRSTN", "GPIO6", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TMS", "GPIO7", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TDI", "GPIO8", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TDO", "GPIO9", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO10", "UART1_OUT", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "GPIO11", "UART1_IN", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "GPIO12", "PWM_OUT0", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO13", "PWM_OUT1", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO14", "PWM_OUT2", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", }, + .reg_type = 13, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", }, + .reg_type = 13, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", }, + .reg_type = 21, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SDA1", "GPIO51", "I2S_DO", "", }, + .reg_type = 21, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_TXD", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CSN0", "GPIO54", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CSN1", "GPIO55", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_RXD", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "SD0_CD", "GPIO52", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD0_WP", "GPIO53", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD0_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 3, + }, + { + .func_name = { "SD0_CMD_RSP", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA0", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA1", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 2, + }, + { + .func_name = { "SD0_DATA2", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA3", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_CLK", "SSI1_CLK", "", "", }, + .reg_type = 8, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SD1_CD", "GPIO_58", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD1_WP", "GPIO_59", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD1_DATA0", "SSI1_TXD", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA3", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "CLK_SW0", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW1", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW2", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW3", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "MAC_TXER", "GPIO37", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, }; diff --git a/bsp/fh8620/platform/fh8620/iot_cam/startup.c b/bsp/fh8620/platform/fh8620/iot_cam/startup.c index ebadf0677b..6787dc7f37 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/startup.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/startup.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rthw.h> #include <rtthread.h> #include <mmu.h> @@ -50,13 +50,13 @@ extern void rt_system_heap_init(void*, void*); extern void rt_hw_finsh_init(void); extern void rt_application_init(void); -static struct mem_desc fh_mem_desc[] = +static struct mem_desc fh_mem_desc[] = { - { 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED }, - { FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED }, - { 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */ - { 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* io table */ - { 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* GPIO#1 io table */ + { 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED }, + { FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED }, + { 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */ + { 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* io table */ + { 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* GPIO#1 io table */ }; rt_uint8_t _irq_stack_start[1024]; @@ -72,46 +72,46 @@ extern unsigned char __bss_end; */ void rtthread_startup(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize mmu */ - rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0])); - rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END); + rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END); #ifdef RT_USING_DMA_MEM - //just use the last 100KB - fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE); + //just use the last 100KB + fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE); #endif - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* initialize timer system */ - rt_system_timer_init(); + /* initialize timer system */ + rt_system_timer_init(); - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); - /* initialize system timer thread */ - rt_system_timer_thread_init(); + /* initialize system timer thread */ + rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ + /* never reach here */ - return ; + return ; } diff --git a/bsp/fh8620/platform/fh_arch.h b/bsp/fh8620/platform/fh_arch.h index 2cbe36718a..a8360cda54 100644 --- a/bsp/fh8620/platform/fh_arch.h +++ b/bsp/fh8620/platform/fh_arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_ARCH_H_ #define FH_ARCH_H_ diff --git a/bsp/fh8620/platform/fh_def.h b/bsp/fh8620/platform/fh_def.h index 57bedcb9e7..4a97709d54 100644 --- a/bsp/fh8620/platform/fh_def.h +++ b/bsp/fh8620/platform/fh_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_DEF_H_ #define FH_DEF_H_ @@ -32,29 +32,29 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) -typedef char SINT8; -typedef short SINT16; -typedef int SINT32; -typedef long long SINT64; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; +typedef char SINT8; +typedef short SINT16; +typedef int SINT32; +typedef long long SINT64; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; #ifndef TYPE_DEFINED -typedef unsigned char uchar; -typedef signed char int8; -typedef unsigned char uint8; -typedef signed short int16; -typedef unsigned short uint16; -typedef signed int int32; -typedef unsigned int uint32; -typedef signed long long int64; -typedef unsigned long long uint64; -typedef float ieee_single; -typedef double ieee_double; +typedef unsigned char uchar; +typedef signed char int8; +typedef unsigned char uint8; +typedef signed short int16; +typedef unsigned short uint16; +typedef signed int int32; +typedef unsigned int uint32; +typedef signed long long int64; +typedef unsigned long long uint64; +typedef float ieee_single; +typedef double ieee_double; -typedef unsigned long boolean; +typedef unsigned long boolean; #define TYPE_DEFINED diff --git a/bsp/fh8620/platform/plat-v2/arch.h b/bsp/fh8620/platform/plat-v2/arch.h index bb32d96ea4..c8d23c0163 100644 --- a/bsp/fh8620/platform/plat-v2/arch.h +++ b/bsp/fh8620/platform/plat-v2/arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,53 +18,53 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ARCH_H_ #define ARCH_H_ /*****************************/ /* BSP CONTROLLER BASE */ /*****************************/ -#define INTC_REG_BASE (0xE0200000) -#define SDC0_REG_BASE (0xE2000000) -#define SDC1_REG_BASE (0xE2100000) -#define TVE_REG_BASE (0xE8000000) -#define VOU_REG_BASE (0xE8100000) -#define AES_REG_BASE (0xE8200000) +#define INTC_REG_BASE (0xE0200000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2100000) +#define TVE_REG_BASE (0xE8000000) +#define VOU_REG_BASE (0xE8100000) +#define AES_REG_BASE (0xE8200000) /* -#define JPEG_REG_BASE (0xE8300000) -#define ISPB_REG_BASE (0xEA000000) -#define ISPF_REG_BASE (0xEA100000) -#define VPU_REG_BASE (0xEC000000) -#define VCU_REG_BASE (0xEC100000) -#define DDRC_REG_BASE (0xED000000) +#define JPEG_REG_BASE (0xE8300000) +#define ISPB_REG_BASE (0xEA000000) +#define ISPF_REG_BASE (0xEA100000) +#define VPU_REG_BASE (0xEC000000) +#define VCU_REG_BASE (0xEC100000) +#define DDRC_REG_BASE (0xED000000) */ -#define DMAC_REG_BASE (0xEE000000) -#define GMAC_REG_BASE (0xEF000000) -#define PMU_REG_BASE (0xF0000000) -#define I2C0_REG_BASE (0xF0200000) -#define GPIO0_REG_BASE (0xF0300000) +#define DMAC_REG_BASE (0xEE000000) +#define GMAC_REG_BASE (0xEF000000) +#define PMU_REG_BASE (0xF0000000) +#define I2C0_REG_BASE (0xF0200000) +#define GPIO0_REG_BASE (0xF0300000) #define GPIO1_REG_BASE (0xf4000000) -#define PWM_REG_BASE (0xF0400000) -#define SPI0_REG_BASE (0xF0500000) -#define SPI1_REG_BASE (0xF0600000) -#define UART0_REG_BASE (0xF0700000) -#define UART1_REG_BASE (0xF0800000) -/*#define I2S_REG_BASE (0xF0900000)*/ -#define ACODEC_REG_BASE (0xF0A00000) -#define I2C1_REG_BASE (0xF0B00000) -#define TMR_REG_BASE (0xF0C00000) -#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +/*#define I2S_REG_BASE (0xF0900000)*/ +#define ACODEC_REG_BASE (0xF0A00000) +#define I2C1_REG_BASE (0xF0B00000) +#define TMR_REG_BASE (0xF0C00000) +#define WDT_REG_BASE (0xF0D00000) /* -#define DPHY_REG_BASE (0xF1000000) -#define MIPIC_REG_BASE (0xF1100000) +#define DPHY_REG_BASE (0xF1000000) +#define MIPIC_REG_BASE (0xF1100000) */ -#define SADC_REG_BASE (0xF1200000) +#define SADC_REG_BASE (0xF1200000) typedef enum IRQn { diff --git a/bsp/fh8620/platform/plat-v2/clock.c b/bsp/fh8620/platform/plat-v2/clock.c index 1c82348c7f..335b4c3ce9 100644 --- a/bsp/fh8620/platform/plat-v2/clock.c +++ b/bsp/fh8620/platform/plat-v2/clock.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "clock.h" #include <rtdevice.h> #include "fh_arch.h" @@ -40,8 +40,8 @@ //#define FH_DBG_CLK -#define FH_CLK_DIV_DEFAULT_VALUE 0x55aaaa55 -#define FH_CLK_GATE_DEFAULT_VALUE 0xaa5555aa +#define FH_CLK_DIV_DEFAULT_VALUE 0x55aaaa55 +#define FH_CLK_GATE_DEFAULT_VALUE 0xaa5555aa #define CONFIG_PAE_PTS_CLOCK (1000000) #define TICKS_PER_USEC (CONFIG_PAE_PTS_CLOCK / 1000000) @@ -50,15 +50,15 @@ #define fh_clk_err(p,fmt,args...)\ - rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args) + rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args) #ifdef FH_CLK_DEBUG #define fh_clk_debug(p,fmt,args...)\ - rt_kprintf("%s:\t\t"fmt,p->name, ##args) + rt_kprintf("%s:\t\t"fmt,p->name, ##args) #define fh_clk_debug_no_handle(fmt,args...)\ - rt_kprintf(fmt, ##args) + rt_kprintf(fmt, ##args) #else //#define fh_clk_err(p,fmt,args...) #define fh_clk_debug(p,fmt,args...) @@ -77,48 +77,48 @@ static struct fh_clk_tree fh_clk_tree; -#define FH_TIMER_WRITEL(offset,value) __raw_writel(value,(fh_clk_tree.c_base_addr + offset)) -#define FH_TIMER_READL(offset) __raw_readl((fh_clk_tree.c_base_addr + offset)) +#define FH_TIMER_WRITEL(offset,value) __raw_writel(value,(fh_clk_tree.c_base_addr + offset)) +#define FH_TIMER_READL(offset) __raw_readl((fh_clk_tree.c_base_addr + offset)) enum clk_gate_enum{ -#define CLK_GATE (1) -#define CLK_UNGATE (0) - ISP_ACLK_GATE = (1<<0), - HCLK_GATE = (1<<1), - CPU_FCLK0_GATE = (1<<3), - VCU_CLK_GATE = (1<<4), - VOU_CLK_GATE = (1<<5), - MCLK_GATE = (1<<6), - SPI0_CLK_GATE = (1<<7), - SPI1_CLK_GATE = (1<<8), - SDC0_CLK_GATE = (1<<9), - SDC1_CLK_GATE = (1<<10), - AC_MCLK_GATE = (1<<11), ///// - I2C0_CLK_GATE = (1<<12), - UART0_CLK_GATE = (1<<13), - UART1_CLK_GATE = (1<<14), - //can't change - WDT_CLK_GATE = (1<<15), +#define CLK_GATE (1) +#define CLK_UNGATE (0) + ISP_ACLK_GATE = (1<<0), + HCLK_GATE = (1<<1), + CPU_FCLK0_GATE = (1<<3), + VCU_CLK_GATE = (1<<4), + VOU_CLK_GATE = (1<<5), + MCLK_GATE = (1<<6), + SPI0_CLK_GATE = (1<<7), + SPI1_CLK_GATE = (1<<8), + SDC0_CLK_GATE = (1<<9), + SDC1_CLK_GATE = (1<<10), + AC_MCLK_GATE = (1<<11), ///// + I2C0_CLK_GATE = (1<<12), + UART0_CLK_GATE = (1<<13), + UART1_CLK_GATE = (1<<14), + //can't change + WDT_CLK_GATE = (1<<15), - PWM_CLK_GATE = (1<<16), - TMR0_CLK_GATE = (1<<17), - TMR1_CLK_GATE = (1<<18), - PTS_CLK_GATE = (1<<19), - MIPI_DPHY_CLK20M_GATE = (1<<20), - MIPI_P32_CLK_GATE = (1<<21), - PIX_CLK_GATE = (1<<22), //// - CIS_CLK_OUT_GATE = (1<<23), - I2S_SCLK_GATE = (1<<24), ////// - ETH_REF_CLK_GATE = (1<<25), - SADC_CLK_GATE = (1<<26), - I2C1_CLK_GATE = (1<<27), - ETH_RX_CLK_GATE = (1<<28), ///// - ETH_TX_CLK_GATE = (1<<29), ///// - ETH_RMII_CLK_GATE = (1<<30),//// + PWM_CLK_GATE = (1<<16), + TMR0_CLK_GATE = (1<<17), + TMR1_CLK_GATE = (1<<18), + PTS_CLK_GATE = (1<<19), + MIPI_DPHY_CLK20M_GATE = (1<<20), + MIPI_P32_CLK_GATE = (1<<21), + PIX_CLK_GATE = (1<<22), //// + CIS_CLK_OUT_GATE = (1<<23), + I2S_SCLK_GATE = (1<<24), ////// + ETH_REF_CLK_GATE = (1<<25), + SADC_CLK_GATE = (1<<26), + I2C1_CLK_GATE = (1<<27), + ETH_RX_CLK_GATE = (1<<28), ///// + ETH_TX_CLK_GATE = (1<<29), ///// + ETH_RMII_CLK_GATE = (1<<30),//// }; @@ -130,96 +130,96 @@ enum clk_gate_enum{ typedef void (*clk_update)(struct fh_clk* p_clk); //update func... -void clk_in_update(struct fh_clk* p_clk); -void pll1_clk_update(struct fh_clk* p_clk); -void pll0_clk_update(struct fh_clk* p_clk); +void clk_in_update(struct fh_clk* p_clk); +void pll1_clk_update(struct fh_clk* p_clk); +void pll0_clk_update(struct fh_clk* p_clk); void cis_pclk_update(struct fh_clk* p_clk); -void ddr_clk_update(struct fh_clk* p_clk); -void ddr_clk_update(struct fh_clk* p_clk); -void fclk_update(struct fh_clk* p_clk); -void aclk_update(struct fh_clk* p_clk); -void hclk_update(struct fh_clk* p_clk); -void pclk_update(struct fh_clk* p_clk); -void isp_aclk_update(struct fh_clk* p_clk); -void vcu_clk_update(struct fh_clk* p_clk); -void vou_clk_update(struct fh_clk* p_clk); -void mipi_p32_clk_update(struct fh_clk* p_clk); -void cis_clk_out_update(struct fh_clk* p_clk); -void pts_update(struct fh_clk* p_clk); -void mipi_pix_clk_update(struct fh_clk* p_clk); -void spi0_clk_update(struct fh_clk* p_clk); -void spi1_clk_update(struct fh_clk* p_clk); -void mipi_dphy_clk20m_update(struct fh_clk* p_clk); -void i2c0_clk_update(struct fh_clk* p_clk); -void i2c1_clk_update(struct fh_clk* p_clk); -void uart0_clk_update(struct fh_clk* p_clk); -void uart1_clk_update(struct fh_clk* p_clk); -void pwm_clk_update(struct fh_clk* p_clk); -void time0_clk_update(struct fh_clk* p_clk); -void time1_clk_update(struct fh_clk* p_clk); -void sadc_clk_update(struct fh_clk* p_clk); -void sdc0_clk2x_update(struct fh_clk* p_clk); -void sdc0_clk_update(struct fh_clk* p_clk); -void sdc0_clk_out_update(struct fh_clk* p_clk); -void sdc0_clk_sample_update(struct fh_clk* p_clk); -void sdc0_clk_drv_update(struct fh_clk* p_clk); -void sdc1_clk2x_update(struct fh_clk* p_clk); -void sdc1_clk_update(struct fh_clk* p_clk); -void sdc1_clk_out_update(struct fh_clk* p_clkt); -void sdc1_clk_sample_update(struct fh_clk* p_clk); -void sdc1_clk_drv_update(struct fh_clk* p_clk); -void eth_ref_clk_update(struct fh_clk* p_clk); -void wdt_clk_update(struct fh_clk* p_clk); +void ddr_clk_update(struct fh_clk* p_clk); +void ddr_clk_update(struct fh_clk* p_clk); +void fclk_update(struct fh_clk* p_clk); +void aclk_update(struct fh_clk* p_clk); +void hclk_update(struct fh_clk* p_clk); +void pclk_update(struct fh_clk* p_clk); +void isp_aclk_update(struct fh_clk* p_clk); +void vcu_clk_update(struct fh_clk* p_clk); +void vou_clk_update(struct fh_clk* p_clk); +void mipi_p32_clk_update(struct fh_clk* p_clk); +void cis_clk_out_update(struct fh_clk* p_clk); +void pts_update(struct fh_clk* p_clk); +void mipi_pix_clk_update(struct fh_clk* p_clk); +void spi0_clk_update(struct fh_clk* p_clk); +void spi1_clk_update(struct fh_clk* p_clk); +void mipi_dphy_clk20m_update(struct fh_clk* p_clk); +void i2c0_clk_update(struct fh_clk* p_clk); +void i2c1_clk_update(struct fh_clk* p_clk); +void uart0_clk_update(struct fh_clk* p_clk); +void uart1_clk_update(struct fh_clk* p_clk); +void pwm_clk_update(struct fh_clk* p_clk); +void time0_clk_update(struct fh_clk* p_clk); +void time1_clk_update(struct fh_clk* p_clk); +void sadc_clk_update(struct fh_clk* p_clk); +void sdc0_clk2x_update(struct fh_clk* p_clk); +void sdc0_clk_update(struct fh_clk* p_clk); +void sdc0_clk_out_update(struct fh_clk* p_clk); +void sdc0_clk_sample_update(struct fh_clk* p_clk); +void sdc0_clk_drv_update(struct fh_clk* p_clk); +void sdc1_clk2x_update(struct fh_clk* p_clk); +void sdc1_clk_update(struct fh_clk* p_clk); +void sdc1_clk_out_update(struct fh_clk* p_clkt); +void sdc1_clk_sample_update(struct fh_clk* p_clk); +void sdc1_clk_drv_update(struct fh_clk* p_clk); +void eth_ref_clk_update(struct fh_clk* p_clk); +void wdt_clk_update(struct fh_clk* p_clk); rt_int32_t check_pix_clk_source(rt_uint32_t offset,rt_uint32_t mask,rt_uint32_t *value); -void pix_update(struct fh_clk* p_clk); +void pix_update(struct fh_clk* p_clk); struct fh_clk_div{ //some has prediv.... //this two could have or...... -#define PRE_DIV_CAL_ALREADY (0x80000000) -#define PRE_DIV_ENABLE (0x01) -#define DIV_ENABLE (0x10) - rt_uint32_t div_flag; +#define PRE_DIV_CAL_ALREADY (0x80000000) +#define PRE_DIV_ENABLE (0x01) +#define DIV_ENABLE (0x10) + rt_uint32_t div_flag; - rt_uint32_t pdiv_value; + rt_uint32_t pdiv_value; - //rt_uint32_t hw_div_value; - rt_uint32_t sw_div_value; - rt_uint32_t sw_div_multi; - //rt_uint32_t clk_in_hz; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; - //rt_uint32_t rate; + //rt_uint32_t hw_div_value; + rt_uint32_t sw_div_value; + rt_uint32_t sw_div_multi; + //rt_uint32_t clk_in_hz; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; + //rt_uint32_t rate; }; struct fh_clk_mux{ -//#define MUX_LEVEL_1 (1) -//#define MUX_LEVEL_2 (2) -//#define MAX_MUX_LEVEL MUX_LEVEL_2 -// rt_uint32_t lev; -#define HAS_MUX (0) -#define HAS_NO_MUX (1) - rt_uint32_t mux_flag; - rt_uint32_t hw_mux_value; - rt_uint32_t sw_mux_value; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; +//#define MUX_LEVEL_1 (1) +//#define MUX_LEVEL_2 (2) +//#define MAX_MUX_LEVEL MUX_LEVEL_2 +// rt_uint32_t lev; +#define HAS_MUX (0) +#define HAS_NO_MUX (1) + rt_uint32_t mux_flag; + rt_uint32_t hw_mux_value; + rt_uint32_t sw_mux_value; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; struct fh_clk_gate{ -#define HAS_GATE (0) -#define HAS_NO_GATE (1) - rt_uint32_t gate_flag; -#define CLK_UNGATE (0) -#define CLK_GATE (1) - //rt_uint32_t hw_status; - rt_uint32_t sw_status; - //rt_uint32_t value; +#define HAS_GATE (0) +#define HAS_NO_GATE (1) + rt_uint32_t gate_flag; +#define CLK_UNGATE (0) +#define CLK_GATE (1) + //rt_uint32_t hw_status; + rt_uint32_t sw_status; + //rt_uint32_t value; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; @@ -234,7 +234,7 @@ struct fh_clk_gate{ * ***************/ struct fh_clk_level_1{ - rt_uint32_t clk_in_out; + rt_uint32_t clk_in_out; }; @@ -244,7 +244,7 @@ struct fh_clk_level_1{ * ***************/ struct fh_clk_level_2{ - rt_uint32_t clk_in_out; + rt_uint32_t clk_in_out; }; /*************** @@ -253,19 +253,19 @@ struct fh_clk_level_2{ * ***************/ struct fh_clk_level_3_ddr{ - //rt_uint32_t mux_level; + //rt_uint32_t mux_level; - struct fh_clk_mux mux[2]; - struct fh_clk_gate gate; - struct fh_clk_div div; + struct fh_clk_mux mux[2]; + struct fh_clk_gate gate; + struct fh_clk_div div; }; struct fh_clk_level_3_sdc{ -#define DIFF_REFERENCE (0x80000000) +#define DIFF_REFERENCE (0x80000000) - rt_uint32_t phase_diff; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; + rt_uint32_t phase_diff; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; @@ -274,26 +274,26 @@ struct fh_clk_level_3_gmac{ }; struct fh_clk_level_3_normal{ - struct fh_clk_mux mux; - struct fh_clk_gate gate; - struct fh_clk_div div; + struct fh_clk_mux mux; + struct fh_clk_gate gate; + struct fh_clk_div div; }; struct fh_clk_level_3 { -#define LEVEL_PERI_NORMAL (0x301) -#define LEVEL_PERI_DDR (0x302) -#define LEVEL_PERI_SDC (0x303) -#define LEVEL_PERI_GMAC (0x304) - rt_uint32_t peri_flag; - union - { - struct fh_clk_level_3_ddr ddr; - struct fh_clk_level_3_sdc sdc; - struct fh_clk_level_3_gmac gmac; - struct fh_clk_level_3_normal normal; - }obj; +#define LEVEL_PERI_NORMAL (0x301) +#define LEVEL_PERI_DDR (0x302) +#define LEVEL_PERI_SDC (0x303) +#define LEVEL_PERI_GMAC (0x304) + rt_uint32_t peri_flag; + union + { + struct fh_clk_level_3_ddr ddr; + struct fh_clk_level_3_sdc sdc; + struct fh_clk_level_3_gmac gmac; + struct fh_clk_level_3_normal normal; + }obj; }; @@ -301,34 +301,34 @@ struct fh_clk_level_3 { struct fh_clk { - char *name; -#define LEVEL_CRYSTAL (0x100) -#define LEVEL_PLL (0x200) -#define LEVEL_PERIPHERAL (0x300) - rt_uint32_t level; + char *name; +#define LEVEL_CRYSTAL (0x100) +#define LEVEL_PLL (0x200) +#define LEVEL_PERIPHERAL (0x300) + rt_uint32_t level; -#define ROOT_NODE (RT_NULL) - struct fh_clk *parent; +#define ROOT_NODE (RT_NULL) + struct fh_clk *parent; - union - { - struct fh_clk_level_1 crystal; - struct fh_clk_level_2 pll; - struct fh_clk_level_3 peri; - }clk; + union + { + struct fh_clk_level_1 crystal; + struct fh_clk_level_2 pll; + struct fh_clk_level_3 peri; + }clk; - rt_uint32_t clk_out_rate; -#define CLK_HAS_NO_GATE (0x80000000) - rt_uint32_t gate; + rt_uint32_t clk_out_rate; +#define CLK_HAS_NO_GATE (0x80000000) + rt_uint32_t gate; - clk_update update_func; + clk_update update_func; - //struct fh_clk_tree *p_tree; + //struct fh_clk_tree *p_tree; }; struct fh_clk_tree{ - rt_uint32_t c_base_addr; - struct fh_clk **clk_head; + rt_uint32_t c_base_addr; + struct fh_clk **clk_head; }; @@ -340,105 +340,105 @@ struct fh_clk_tree{ * * ********/ -#define CRYSTAL_HZ (24000000) +#define CRYSTAL_HZ (24000000) struct fh_clk clk_in = { - .name = "clk_in", - .level = LEVEL_CRYSTAL, - .parent = ROOT_NODE, - .clk.crystal.clk_in_out = CRYSTAL_HZ, - //.clk_out_rate = clk_in.clk.crystal.clk_in_out, - .clk_out_rate = CRYSTAL_HZ, - .update_func = clk_in_update, + .name = "clk_in", + .level = LEVEL_CRYSTAL, + .parent = ROOT_NODE, + .clk.crystal.clk_in_out = CRYSTAL_HZ, + //.clk_out_rate = clk_in.clk.crystal.clk_in_out, + .clk_out_rate = CRYSTAL_HZ, + .update_func = clk_in_update, }; -#define CIS_PCLK_HZ (108000000) +#define CIS_PCLK_HZ (108000000) struct fh_clk cis_pclk = { - .name = "cis_pclk", - .level = LEVEL_CRYSTAL, - .parent = ROOT_NODE, - .clk.crystal.clk_in_out = CIS_PCLK_HZ, - //.clk_out_rate = clk_in.clk.crystal.clk_in_out, - .clk_out_rate = CIS_PCLK_HZ, - .update_func = cis_pclk_update, + .name = "cis_pclk", + .level = LEVEL_CRYSTAL, + .parent = ROOT_NODE, + .clk.crystal.clk_in_out = CIS_PCLK_HZ, + //.clk_out_rate = clk_in.clk.crystal.clk_in_out, + .clk_out_rate = CIS_PCLK_HZ, + .update_func = cis_pclk_update, }; -#define PLL0_HZ (864000000) +#define PLL0_HZ (864000000) struct fh_clk pll0 = { - .name = "pll0", - .level = LEVEL_PLL, - .parent = &clk_in, - .clk.crystal.clk_in_out = PLL0_HZ, - //.clk_out_rate = pll0.clk.crystal.clk_in_out, - .clk_out_rate = PLL0_HZ, - .update_func = pll0_clk_update, + .name = "pll0", + .level = LEVEL_PLL, + .parent = &clk_in, + .clk.crystal.clk_in_out = PLL0_HZ, + //.clk_out_rate = pll0.clk.crystal.clk_in_out, + .clk_out_rate = PLL0_HZ, + .update_func = pll0_clk_update, }; -#define PLL1_HZ (600000000) +#define PLL1_HZ (600000000) struct fh_clk pll1 = { - .name = "pll1", - .level = LEVEL_PLL, - .parent = &clk_in, - .clk.crystal.clk_in_out = PLL1_HZ, - .clk_out_rate = PLL1_HZ, - .update_func = pll1_clk_update, + .name = "pll1", + .level = LEVEL_PLL, + .parent = &clk_in, + .clk.crystal.clk_in_out = PLL1_HZ, + .clk_out_rate = PLL1_HZ, + .update_func = pll1_clk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk ddr_clk_normal = { - .name = "ddr_normal", - .level = LEVEL_PERIPHERAL, - //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_DDR, - //0:xtal_clk - //1:pll0_clk -#define MUX0_XTAL_CLK (0) -#define MUX0_PLL0_CLK (1) + .name = "ddr_normal", + .level = LEVEL_PERIPHERAL, + //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_DDR, + //0:xtal_clk + //1:pll0_clk +#define MUX0_XTAL_CLK (0) +#define MUX0_PLL0_CLK (1) - .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, + .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, - //0:pll0 clk default 864/2M - //1:pll1 clk default 600M -#define MUX1_PLL0_CLK (0) -#define MUX1_PLL1_CLK (1) - .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, + //0:pll0 clk default 864/2M + //1:pll1 clk default 600M +#define MUX1_PLL0_CLK (0) +#define MUX1_PLL1_CLK (1) + .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, - //gate - //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, + //gate + //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, - .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, + .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, + .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, - //div - //clk in maybe cry or pll - .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE, - //.clk.peri.obj.ddr.div.pdiv_value = 2, + //div + //clk in maybe cry or pll + .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE, + //.clk.peri.obj.ddr.div.pdiv_value = 2, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.div.sw_div_value = 1, + .clk.peri.obj.ddr.div.sw_div_value = 1, #endif - .clk.peri.obj.ddr.div.sw_div_multi =1, - .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, + .clk.peri.obj.ddr.div.sw_div_multi =1, + .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, - .update_func = ddr_clk_update, + .update_func = ddr_clk_update, }; @@ -450,121 +450,121 @@ static struct fh_clk ddr_clk_normal = { //NEED_CAUTION parent not fix... static struct fh_clk ddr_clk_div2 = { - .name = "ddr_div2", - .level = LEVEL_PERIPHERAL, - //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_DDR, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, + .name = "ddr_div2", + .level = LEVEL_PERIPHERAL, + //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_DDR, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, - //0:pll0 clk default 864/2M - //1:pll1 clk default 600M - .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, + //0:pll0 clk default 864/2M + //1:pll1 clk default 600M + .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, - //gate - //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, + //gate + //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, - .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, + .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, + .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, - //div - //clk in maybe cry or pll - .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE, - .clk.peri.obj.ddr.div.pdiv_value = 2, + //div + //clk in maybe cry or pll + .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE, + .clk.peri.obj.ddr.div.pdiv_value = 2, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.div.sw_div_value = 1, + .clk.peri.obj.ddr.div.sw_div_value = 1, #endif - .clk.peri.obj.ddr.div.sw_div_multi =1, - .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, + .clk.peri.obj.ddr.div.sw_div_multi =1, + .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, - .update_func = ddr_clk_update, + .update_func = ddr_clk_update, }; static struct fh_clk cpu_fclk = { - .name = "cpu_fclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_fclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 0, + .clk.peri.obj.normal.div.sw_div_value = 0, #endif - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = fclk_update, + .update_func = fclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk cpu_aclk = { - .name = "cpu_aclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_aclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, -// .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, -// .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, +// .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, +// .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.pdiv_value = 2, -// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.pdiv_value = 2, +// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = aclk_update, + .update_func = aclk_update, }; @@ -572,282 +572,282 @@ static struct fh_clk cpu_aclk = { static struct fh_clk cpu_hclk = { - .name = "cpu_hclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_hclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .update_func = hclk_update, + .update_func = hclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk cpu_pclk = { - .name = "cpu_pclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_pclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE, - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.pdiv_value = 2, -// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.pdiv_value = 2, +// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = pclk_update, + .update_func = pclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk isp_aclk = { - .name = "isp_aclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "isp_aclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE, - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE, + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0x03 << 8, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0x03 << 8, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = isp_aclk_update, + .update_func = isp_aclk_update, }; // ////NEED_CAUTION parent not fix... static struct fh_clk vcu_clk = { - .name = "vcu_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "vcu_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0x03 << 24, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0x03 << 24, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = vcu_clk_update, + .update_func = vcu_clk_update, }; static struct fh_clk vou_clk = { - .name = "vou_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "vou_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = vou_clk_update, + .update_func = vou_clk_update, }; static struct fh_clk mipi_p32_clk = { - .name = "mipi_p32_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_p32_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = mipi_p32_clk_update, + .update_func = mipi_p32_clk_update, }; static struct fh_clk cis_clk_out = { - .name = "cis_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cis_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 3, + .clk.peri.obj.normal.div.sw_div_value = 3, #endif - .update_func = cis_clk_out_update, + .update_func = cis_clk_out_update, }; @@ -855,43 +855,43 @@ static struct fh_clk cis_clk_out = { static struct fh_clk pts_clk = { - .name = "pts_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pts_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 35, + .clk.peri.obj.normal.div.sw_div_value = 35, #endif - .clk.peri.obj.normal.div.pdiv_value = 12, + .clk.peri.obj.normal.div.pdiv_value = 12, - .update_func = pts_update, + .update_func = pts_update, }; @@ -899,31 +899,31 @@ static struct fh_clk pts_clk = { static struct fh_clk mipi_pix_clk = { - .name = "mipi_pix_clk_i", - .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_pix_clk_i", + .level = LEVEL_PERIPHERAL, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 3, + .clk.peri.obj.normal.div.sw_div_value = 3, #endif - .update_func = mipi_pix_clk_update, + .update_func = mipi_pix_clk_update, }; @@ -931,37 +931,37 @@ static struct fh_clk mipi_pix_clk = { static struct fh_clk pix_clk = { - .name = "pix_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pix_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk -#define CIS_PIX_CLK (0) -#define CIS_PIX_CLK_OPPOSITE (1) -#define MIPI_PIX_CLK (2) + //0:xtal_clk + //1:pll0_clk +#define CIS_PIX_CLK (0) +#define CIS_PIX_CLK_OPPOSITE (1) +#define MIPI_PIX_CLK (2) - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.normal.mux.reg_mask = 3<<4, + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.normal.mux.reg_mask = 3<<4, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = 0, + //div + .clk.peri.obj.normal.div.div_flag = 0, - .update_func = pix_update, + .update_func = pix_update, }; @@ -971,41 +971,41 @@ static struct fh_clk pix_clk = { static struct fh_clk spi0_clk = { - .name = "spi0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "spi0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif - .update_func = spi0_clk_update, + .update_func = spi0_clk_update, }; @@ -1013,46 +1013,46 @@ static struct fh_clk spi0_clk = { static struct fh_clk spi1_clk = { - .name = "spi1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "spi1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif #ifdef RT_USING_SPI1 - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif - .update_func = spi1_clk_update, + .update_func = spi1_clk_update, }; @@ -1060,200 +1060,200 @@ static struct fh_clk spi1_clk = { static struct fh_clk mipi_dphy_clk20m = { - .name = "mipi_dphy_clk20m", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_dphy_clk20m", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, -// .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.pdiv_value = 30, -// .clk.peri.obj.normal.div.sw_div_value = 11, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, +// .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.pdiv_value = 30, +// .clk.peri.obj.normal.div.sw_div_value = 11, - .update_func = mipi_dphy_clk20m_update, + .update_func = mipi_dphy_clk20m_update, }; static struct fh_clk i2c0_clk = { - .name = "i2c0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "i2c0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = i2c0_clk_update, + .update_func = i2c0_clk_update, }; static struct fh_clk i2c1_clk = { - .name = "i2c1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "i2c1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = i2c1_clk_update, + .update_func = i2c1_clk_update, }; static struct fh_clk uart0_clk = { - .name = "uart0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "uart0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x1f << 0, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x1f << 0, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 10, + .clk.peri.obj.normal.div.pdiv_value = 10, - .update_func = uart0_clk_update, + .update_func = uart0_clk_update, }; static struct fh_clk uart1_clk = { - .name = "uart1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "uart1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x1f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x1f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 10, + .clk.peri.obj.normal.div.pdiv_value = 10, - .update_func = uart1_clk_update, + .update_func = uart1_clk_update, }; @@ -1261,131 +1261,131 @@ static struct fh_clk uart1_clk = { static struct fh_clk pwm_clk = { - .name = "pwm_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pwm_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 0, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 0, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = pwm_clk_update, + .update_func = pwm_clk_update, }; static struct fh_clk time0_clk = { - .name = "time0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "time0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = time0_clk_update, + .update_func = time0_clk_update, }; static struct fh_clk time1_clk = { - .name = "time1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, + .name = "time1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = time1_clk_update, + .update_func = time1_clk_update, }; @@ -1393,227 +1393,227 @@ static struct fh_clk time1_clk = { static struct fh_clk sadc_clk = { - .name = "sadc_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sadc_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.sw_div_multi = 1, - .clk.peri.obj.normal.div.pdiv_value = 120, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.sw_div_multi = 1, + .clk.peri.obj.normal.div.pdiv_value = 120, - .update_func = sadc_clk_update, + .update_func = sadc_clk_update, }; static struct fh_clk sdc0_clk2x = { - .name = "sdc0_clk2x", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sdc0_clk2x", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = sdc0_clk2x_update, + .update_func = sdc0_clk2x_update, }; static struct fh_clk sdc0_clk = { - .name = "sdc0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, + .name = "sdc0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, - .update_func = sdc0_clk_update, + .update_func = sdc0_clk_update, }; static struct fh_clk sdc0_clk_out = { - .name = "sdc0_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, + .name = "sdc0_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, - .update_func = sdc0_clk_out_update, + .update_func = sdc0_clk_out_update, }; static struct fh_clk sdc0_clk_sample = { - .name = "sdc0_clk_sample", - .level = LEVEL_PERIPHERAL, + .name = "sdc0_clk_sample", + .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<16, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<16, - .update_func = sdc0_clk_sample_update, + .update_func = sdc0_clk_sample_update, }; static struct fh_clk sdc0_clk_drive = { - .name = "sdc0_clk_drive", - .level = LEVEL_PERIPHERAL, + .name = "sdc0_clk_drive", + .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<20, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<20, - .update_func = sdc0_clk_drv_update, + .update_func = sdc0_clk_drv_update, }; static struct fh_clk sdc1_clk2x = { - .name = "sdc1_clk2x", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sdc1_clk2x", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = sdc1_clk2x_update, + .update_func = sdc1_clk2x_update, }; static struct fh_clk sdc1_clk = { - .name = "sdc1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, + .name = "sdc1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, - .update_func = sdc1_clk_update, + .update_func = sdc1_clk_update, }; static struct fh_clk sdc1_clk_out = { - .name = "sdc1_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, + .name = "sdc1_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, - .update_func = sdc1_clk_out_update, + .update_func = sdc1_clk_out_update, }; static struct fh_clk sdc1_clk_sample = { - .name = "sdc1_clk_sample", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<8, + .name = "sdc1_clk_sample", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<8, - .update_func = sdc1_clk_sample_update, + .update_func = sdc1_clk_sample_update, }; static struct fh_clk sdc1_clk_drive = { - .name = "sdc1_clk_drive", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<12, + .name = "sdc1_clk_drive", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<12, - .update_func = sdc1_clk_drv_update, + .update_func = sdc1_clk_drv_update, }; @@ -1621,826 +1621,826 @@ static struct fh_clk sdc1_clk_drive = { static struct fh_clk eth_ref_clk = { - .name = "eth_ref_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "eth_ref_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = eth_ref_clk_update, + .update_func = eth_ref_clk_update, }; static struct fh_clk wdt_clk = { - .name = "wdt_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .name = "wdt_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .update_func = wdt_clk_update, + .update_func = wdt_clk_update, }; struct fh_clk *fh_clk_array[] = { - &clk_in, - &cis_pclk, - &pll0, - &pll1, - &ddr_clk_normal, - &ddr_clk_div2, - &cpu_fclk, - &cpu_aclk, - &cpu_hclk, - &cpu_pclk, - &isp_aclk, - &vcu_clk, - &vou_clk, - &mipi_p32_clk, - &cis_clk_out, - &pts_clk, - &mipi_pix_clk, - &pix_clk, + &clk_in, + &cis_pclk, + &pll0, + &pll1, + &ddr_clk_normal, + &ddr_clk_div2, + &cpu_fclk, + &cpu_aclk, + &cpu_hclk, + &cpu_pclk, + &isp_aclk, + &vcu_clk, + &vou_clk, + &mipi_p32_clk, + &cis_clk_out, + &pts_clk, + &mipi_pix_clk, + &pix_clk, - //pll1 - &sdc0_clk2x, - &sdc0_clk, - &sdc0_clk_out, - &sdc0_clk_sample, - &sdc0_clk_drive, + //pll1 + &sdc0_clk2x, + &sdc0_clk, + &sdc0_clk_out, + &sdc0_clk_sample, + &sdc0_clk_drive, - &sdc1_clk2x, - &sdc1_clk, - &sdc1_clk_out, - &sdc1_clk_sample, - &sdc1_clk_drive, + &sdc1_clk2x, + &sdc1_clk, + &sdc1_clk_out, + &sdc1_clk_sample, + &sdc1_clk_drive, - &spi0_clk, - &spi1_clk, - &mipi_dphy_clk20m, - &i2c0_clk, - &i2c1_clk, - &uart0_clk, - &uart1_clk, - &pwm_clk, - &time0_clk, - &time1_clk, - &sadc_clk, - ð_ref_clk, + &spi0_clk, + &spi1_clk, + &mipi_dphy_clk20m, + &i2c0_clk, + &i2c1_clk, + &uart0_clk, + &uart1_clk, + &pwm_clk, + &time0_clk, + &time1_clk, + &sadc_clk, + ð_ref_clk, - &wdt_clk, + &wdt_clk, }; static inline rt_int32_t wrap_read_reg(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t temp_v, temp_shift; + rt_uint32_t temp_v, temp_shift; - /* if(fh_pmu_status() == PMU_STATUS_CLOSE) - return -1;*/ - temp_v = FH_TIMER_READL(offset); - temp_v &= mask; - temp_shift = __rt_ffs(mask); - temp_v = temp_v >> (temp_shift - 1); - *value = temp_v; - return 0; + /* if(fh_pmu_status() == PMU_STATUS_CLOSE) + return -1;*/ + temp_v = FH_TIMER_READL(offset); + temp_v &= mask; + temp_shift = __rt_ffs(mask); + temp_v = temp_v >> (temp_shift - 1); + *value = temp_v; + return 0; } static inline rt_int32_t wrap_write_reg(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t value) + rt_uint32_t value) { - rt_uint32_t temp_v, temp_shift; + rt_uint32_t temp_v, temp_shift; - /* - if(fh_pmu_status() == PMU_STATUS_CLOSE) - return -1; - */ + /* + if(fh_pmu_status() == PMU_STATUS_CLOSE) + return -1; + */ - temp_v = FH_TIMER_READL(offset); - temp_v &= ~mask; - temp_shift = __rt_ffs(mask); - temp_v |= value << (temp_shift - 1); - FH_TIMER_WRITEL(offset, temp_v); - return 0; + temp_v = FH_TIMER_READL(offset); + temp_v &= ~mask; + temp_shift = __rt_ffs(mask); + temp_v |= value << (temp_shift - 1); + FH_TIMER_WRITEL(offset, temp_v); + return 0; } rt_int32_t check_pix_clk_source(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t mux0; - rt_int32_t ret; - ret = wrap_read_reg(offset, mask, &mux0); + rt_uint32_t mux0; + rt_int32_t ret; + ret = wrap_read_reg(offset, mask, &mux0); - if (ret != 0) { - return ret; - } + if (ret != 0) { + return ret; + } - *value = mux0; - return 0; + *value = mux0; + return 0; } rt_int32_t check_xtal_pll0(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t mux0; - rt_int32_t ret; - ret = wrap_read_reg(offset, mask, &mux0); + rt_uint32_t mux0; + rt_int32_t ret; + ret = wrap_read_reg(offset, mask, &mux0); - if (ret != 0) { - return ret; - } - if (mux0 == MUX0_PLL0_CLK) - *value = MUX0_PLL0_CLK; - else - *value = MUX0_XTAL_CLK; + if (ret != 0) { + return ret; + } + if (mux0 == MUX0_PLL0_CLK) + *value = MUX0_PLL0_CLK; + else + *value = MUX0_XTAL_CLK; - return 0; + return 0; } void cal_pll0_prediv(rt_uint32_t *div_flag, rt_uint32_t *pre_value) { - if (!(*div_flag & PRE_DIV_CAL_ALREADY)) { - //before has got the prediv value.. - if (*div_flag & PRE_DIV_ENABLE) { + if (!(*div_flag & PRE_DIV_CAL_ALREADY)) { + //before has got the prediv value.. + if (*div_flag & PRE_DIV_ENABLE) { - *pre_value *= 2; - } else { - *pre_value = 2; - } - *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY; - } + *pre_value *= 2; + } else { + *pre_value = 2; + } + *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY; + } } rt_int32_t sw_div_process(rt_uint32_t div_flag, rt_uint32_t offset, - rt_uint32_t mask, rt_uint32_t *div_value) + rt_uint32_t mask, rt_uint32_t *div_value) { - //rt_kprintf("----------div go----------\n"); - rt_uint32_t div; - rt_int32_t ret; - if (div_flag & DIV_ENABLE) { - ret = wrap_read_reg(offset, mask, &div); - if (ret != 0) { - return ret; - } + //rt_kprintf("----------div go----------\n"); + rt_uint32_t div; + rt_int32_t ret; + if (div_flag & DIV_ENABLE) { + ret = wrap_read_reg(offset, mask, &div); + if (ret != 0) { + return ret; + } // -// rt_kprintf("hw value is %x\n",div); -// rt_kprintf("sw value is %x\n",div_value); +// rt_kprintf("hw value is %x\n",div); +// rt_kprintf("sw value is %x\n",div_value); // -// rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000)); -// rt_kprintf("mask is %x\n",mask); +// rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000)); +// rt_kprintf("mask is %x\n",mask); - //if use the hw default value.... + //if use the hw default value.... - if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) { - *div_value = div; - return 0; - } + if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) { + *div_value = div; + return 0; + } - if (div != *div_value) { - ret = wrap_write_reg(offset, mask, *div_value); - if (ret != 0) { - return ret; - } - } - } - //rt_kprintf("----------div done----------\n"); - return 0; - //*div_flag |= PRE_DIV_ENABLE; + if (div != *div_value) { + ret = wrap_write_reg(offset, mask, *div_value); + if (ret != 0) { + return ret; + } + } + } + //rt_kprintf("----------div done----------\n"); + return 0; + //*div_flag |= PRE_DIV_ENABLE; } void cal_baud_hz(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div, - rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out) + rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out) { - //div += 1; - if (div_flag & PRE_DIV_ENABLE) { - *baud_out = (clk_in / pre_div); - } else { - *baud_out = clk_in; - } + //div += 1; + if (div_flag & PRE_DIV_ENABLE) { + *baud_out = (clk_in / pre_div); + } else { + *baud_out = clk_in; + } - if (div_flag & DIV_ENABLE) { - *baud_out /= ((div + 1) * div_multi); - } + if (div_flag & DIV_ENABLE) { + *baud_out /= ((div + 1) * div_multi); + } } void cal_baud_div(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div, - rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out) + rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out) { - //div += 1; - rt_uint32_t temp_baud_hz, temp_baud_div; + //div += 1; + rt_uint32_t temp_baud_hz, temp_baud_div; - if (div_flag & DIV_ENABLE) { - if (div_flag & PRE_DIV_ENABLE) { - temp_baud_hz = (clk_in / pre_div); - } else { - temp_baud_hz = clk_in; - } - temp_baud_div = temp_baud_hz / baud_out; - *div = temp_baud_div - 1; - } + if (div_flag & DIV_ENABLE) { + if (div_flag & PRE_DIV_ENABLE) { + temp_baud_hz = (clk_in / pre_div); + } else { + temp_baud_hz = clk_in; + } + temp_baud_div = temp_baud_hz / baud_out; + *div = temp_baud_div - 1; + } } rt_int32_t process_gate(rt_uint32_t gate_flag, rt_uint32_t reg_offset, - rt_uint32_t reg_mask, rt_uint32_t *sw_status, - rt_uint32_t *pclk_status) + rt_uint32_t reg_mask, rt_uint32_t *sw_status, + rt_uint32_t *pclk_status) { - //rt_kprintf("----------gate go----------\n"); - rt_uint32_t hw_gate; - rt_int32_t ret; - if (gate_flag == HAS_GATE) { - ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate); - if (ret != 0) { - return ret; - } + //rt_kprintf("----------gate go----------\n"); + rt_uint32_t hw_gate; + rt_int32_t ret; + if (gate_flag == HAS_GATE) { + ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate); + if (ret != 0) { + return ret; + } - if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) { - *sw_status = hw_gate; - *pclk_status = *sw_status; - return 0; - } + if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) { + *sw_status = hw_gate; + *pclk_status = *sw_status; + return 0; + } -// rt_kprintf("gate hw is :%x\n",hw_gate); -// rt_kprintf("gate sw is :%x\n",sw_status); - if (hw_gate != *sw_status) { - //update the gate.. -// rt_kprintf("gate reg offset is :%x\n",reg_offset); -// rt_kprintf("gate reg mask is :%x\n",reg_mask); -// rt_kprintf("gate reg write is :%x\n",sw_status); - ret = wrap_write_reg(reg_offset, reg_mask, *sw_status); - if (ret != 0) { - return ret; - } - } +// rt_kprintf("gate hw is :%x\n",hw_gate); +// rt_kprintf("gate sw is :%x\n",sw_status); + if (hw_gate != *sw_status) { + //update the gate.. +// rt_kprintf("gate reg offset is :%x\n",reg_offset); +// rt_kprintf("gate reg mask is :%x\n",reg_mask); +// rt_kprintf("gate reg write is :%x\n",sw_status); + ret = wrap_write_reg(reg_offset, reg_mask, *sw_status); + if (ret != 0) { + return ret; + } + } - *pclk_status = *sw_status; - } + *pclk_status = *sw_status; + } - else { - *pclk_status |= CLK_HAS_NO_GATE; - } - //rt_kprintf("---------gate done---------\n"); - return 0; + else { + *pclk_status |= CLK_HAS_NO_GATE; + } + //rt_kprintf("---------gate done---------\n"); + return 0; } void clk_handle(struct fh_clk* p_clk, struct fh_clk *parent) { - //rt_uint32_t div; - //rt_uint32_t sw_gate; - rt_uint32_t phase; - rt_int32_t ret; - p_clk->parent = parent; -// switch - //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n "); - if (p_clk->parent) - //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority); - fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name); - else - fh_clk_debug(p_clk, "'root node'\n"); + //rt_uint32_t div; + //rt_uint32_t sw_gate; + rt_uint32_t phase; + rt_int32_t ret; + p_clk->parent = parent; +// switch + //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n "); + if (p_clk->parent) + //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority); + fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name); + else + fh_clk_debug(p_clk, "'root node'\n"); - switch (p_clk->level) { + switch (p_clk->level) { - case LEVEL_CRYSTAL: - //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate); - break; - case LEVEL_PLL: - //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate); - break; - case LEVEL_PERIPHERAL: + case LEVEL_CRYSTAL: + //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate); + break; + case LEVEL_PLL: + //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate); + break; + case LEVEL_PERIPHERAL: - switch (p_clk->clk.peri.peri_flag) { + switch (p_clk->clk.peri.peri_flag) { - case LEVEL_PERI_NORMAL: - //div = p_clk->clk.peri.obj.normal.div.sw_div_value; - ret = - sw_div_process( - p_clk->clk.peri.obj.normal.div.div_flag, - p_clk->clk.peri.obj.normal.div.reg_offset, - p_clk->clk.peri.obj.normal.div.reg_mask, - &p_clk->clk.peri.obj.normal.div.sw_div_value); + case LEVEL_PERI_NORMAL: + //div = p_clk->clk.peri.obj.normal.div.sw_div_value; + ret = + sw_div_process( + p_clk->clk.peri.obj.normal.div.div_flag, + p_clk->clk.peri.obj.normal.div.reg_offset, + p_clk->clk.peri.obj.normal.div.reg_mask, + &p_clk->clk.peri.obj.normal.div.sw_div_value); - if (ret != 0) { - fh_clk_err(p_clk, - "div process failed.error no:%x\n", - ret); - break; - } + if (ret != 0) { + fh_clk_err(p_clk, + "div process failed.error no:%x\n", + ret); + break; + } - //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value); -// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value); -// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value); -// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); -// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag); - //hw will self add 1.. + //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value); +// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value); +// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value); +// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); +// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag); + //hw will self add 1.. - cal_baud_hz(p_clk->parent->clk_out_rate, - p_clk->clk.peri.obj.normal.div.div_flag, - p_clk->clk.peri.obj.normal.div.pdiv_value, - p_clk->clk.peri.obj.normal.div.sw_div_value, - p_clk->clk.peri.obj.normal.div.sw_div_multi, - &p_clk->clk_out_rate); + cal_baud_hz(p_clk->parent->clk_out_rate, + p_clk->clk.peri.obj.normal.div.div_flag, + p_clk->clk.peri.obj.normal.div.pdiv_value, + p_clk->clk.peri.obj.normal.div.sw_div_value, + p_clk->clk.peri.obj.normal.div.sw_div_multi, + &p_clk->clk_out_rate); - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //fix the gate.. - //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status; - ret = - process_gate( - p_clk->clk.peri.obj.normal.gate.gate_flag, - p_clk->clk.peri.obj.normal.gate.reg_offset, - p_clk->clk.peri.obj.normal.gate.reg_mask, - &p_clk->clk.peri.obj.normal.gate.sw_status, - &p_clk->gate); + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //fix the gate.. + //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status; + ret = + process_gate( + p_clk->clk.peri.obj.normal.gate.gate_flag, + p_clk->clk.peri.obj.normal.gate.reg_offset, + p_clk->clk.peri.obj.normal.gate.reg_mask, + &p_clk->clk.peri.obj.normal.gate.sw_status, + &p_clk->gate); - if (ret != 0) { - fh_clk_err(p_clk, - "gate process failed.error no:%x\n", - ret); - break; - } + if (ret != 0) { + fh_clk_err(p_clk, + "gate process failed.error no:%x\n", + ret); + break; + } - break; - case LEVEL_PERI_DDR: - //rt_uint32_t mux0,mux1; - //div = p_clk->clk.peri.obj.ddr.div.sw_div_value; + break; + case LEVEL_PERI_DDR: + //rt_uint32_t mux0,mux1; + //div = p_clk->clk.peri.obj.ddr.div.sw_div_value; - ret = - sw_div_process( - p_clk->clk.peri.obj.ddr.div.div_flag, - p_clk->clk.peri.obj.ddr.div.reg_offset, - p_clk->clk.peri.obj.ddr.div.reg_mask, - &p_clk->clk.peri.obj.ddr.div.sw_div_value); + ret = + sw_div_process( + p_clk->clk.peri.obj.ddr.div.div_flag, + p_clk->clk.peri.obj.ddr.div.reg_offset, + p_clk->clk.peri.obj.ddr.div.reg_mask, + &p_clk->clk.peri.obj.ddr.div.sw_div_value); - if (ret != 0) { - fh_clk_err(p_clk, - "div process failed.error no:%x\n", - ret); - break; - } + if (ret != 0) { + fh_clk_err(p_clk, + "div process failed.error no:%x\n", + ret); + break; + } -// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value); -// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value); -// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); -// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag); +// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value); +// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value); +// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); +// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag); - cal_baud_hz(p_clk->parent->clk_out_rate, - p_clk->clk.peri.obj.ddr.div.div_flag, - p_clk->clk.peri.obj.ddr.div.pdiv_value, - p_clk->clk.peri.obj.ddr.div.sw_div_value, - p_clk->clk.peri.obj.ddr.div.sw_div_multi, - &p_clk->clk_out_rate); + cal_baud_hz(p_clk->parent->clk_out_rate, + p_clk->clk.peri.obj.ddr.div.div_flag, + p_clk->clk.peri.obj.ddr.div.pdiv_value, + p_clk->clk.peri.obj.ddr.div.sw_div_value, + p_clk->clk.peri.obj.ddr.div.sw_div_multi, + &p_clk->clk_out_rate); - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //fix the gate.. - //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask); - //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status; + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //fix the gate.. + //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask); + //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status; - ret = process_gate( - p_clk->clk.peri.obj.ddr.gate.gate_flag, - p_clk->clk.peri.obj.ddr.gate.reg_offset, - p_clk->clk.peri.obj.ddr.gate.reg_mask, - &p_clk->clk.peri.obj.ddr.gate.sw_status, - &p_clk->gate); + ret = process_gate( + p_clk->clk.peri.obj.ddr.gate.gate_flag, + p_clk->clk.peri.obj.ddr.gate.reg_offset, + p_clk->clk.peri.obj.ddr.gate.reg_mask, + &p_clk->clk.peri.obj.ddr.gate.sw_status, + &p_clk->gate); - if (ret != 0) { - fh_clk_err(p_clk, - "gate process failed.error no:%x\n", - ret); - break; - } + if (ret != 0) { + fh_clk_err(p_clk, + "gate process failed.error no:%x\n", + ret); + break; + } - break; - case LEVEL_PERI_SDC: - //just need to handle the phase.... - p_clk->clk_out_rate = p_clk->parent->clk_out_rate; - if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) { - //fh_clk_debug(p_clk,"this is the reference..no need to process..\n"); - break; - } + break; + case LEVEL_PERI_SDC: + //just need to handle the phase.... + p_clk->clk_out_rate = p_clk->parent->clk_out_rate; + if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) { + //fh_clk_debug(p_clk,"this is the reference..no need to process..\n"); + break; + } - //baud ... + //baud ... - //phase.. - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //hw status.. - ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset, - p_clk->clk.peri.obj.sdc.reg_mask, - &phase); + //phase.. + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //hw status.. + ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset, + p_clk->clk.peri.obj.sdc.reg_mask, + &phase); - if (ret != 0) { - fh_clk_err(p_clk, - "read pmu failed.error no:%x\n", - ret); - break; - } + if (ret != 0) { + fh_clk_err(p_clk, + "read pmu failed.error no:%x\n", + ret); + break; + } -// fh_clk_debug(p_clk,"hw phase is :%x\n",phase); -// fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff); - if (phase != p_clk->clk.peri.obj.sdc.phase_diff) { - //update the hw para.. - ret = - wrap_write_reg( - p_clk->clk.peri.obj.sdc.reg_offset, - p_clk->clk.peri.obj.sdc.reg_mask, - p_clk->clk.peri.obj.sdc.phase_diff); - if (ret != 0) { - fh_clk_err(p_clk, - "write pmu failed.error no:%x\n", - ret); - break; - } - } +// fh_clk_debug(p_clk,"hw phase is :%x\n",phase); +// fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff); + if (phase != p_clk->clk.peri.obj.sdc.phase_diff) { + //update the hw para.. + ret = + wrap_write_reg( + p_clk->clk.peri.obj.sdc.reg_offset, + p_clk->clk.peri.obj.sdc.reg_mask, + p_clk->clk.peri.obj.sdc.phase_diff); + if (ret != 0) { + fh_clk_err(p_clk, + "write pmu failed.error no:%x\n", + ret); + break; + } + } - break; - case LEVEL_PERI_GMAC: - break; - default: - break; + break; + case LEVEL_PERI_GMAC: + break; + default: + break; - } - } + } + } - fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate); + fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate); } // void clk_in_update(struct fh_clk* p_clk) { - clk_handle(p_clk, RT_NULL); + clk_handle(p_clk, RT_NULL); } void cis_pclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, RT_NULL); + clk_handle(p_clk, RT_NULL); } void pll1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &clk_in); + clk_handle(p_clk, &clk_in); } void pll0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &clk_in); + clk_handle(p_clk, &clk_in); } void ddr_clk_update(struct fh_clk* p_clk) { - //check if pll0 or pll1 - rt_uint32_t mux0, mux1; - rt_int32_t ret; - struct fh_clk* parent; - //1 step: fix the parent.. - ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset, - p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } + //check if pll0 or pll1 + rt_uint32_t mux0, mux1; + rt_int32_t ret; + struct fh_clk* parent; + //1 step: fix the parent.. + ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset, + p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } - if (mux1 == MUX1_PLL0_CLK) { - ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset, - p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } - if (mux0 == MUX0_PLL0_CLK) { - //ddr normal parent is pll0 - parent = &pll0; - } else { - //ddr normal parent is xtal - parent = &clk_in; - } - } else { - //ddr normal parent is pll1 - parent = &pll1; - } - p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX; - p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX; - clk_handle(p_clk, parent); + if (mux1 == MUX1_PLL0_CLK) { + ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset, + p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } + if (mux0 == MUX0_PLL0_CLK) { + //ddr normal parent is pll0 + parent = &pll0; + } else { + //ddr normal parent is xtal + parent = &clk_in; + } + } else { + //ddr normal parent is pll1 + parent = &pll1; + } + p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX; + p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX; + clk_handle(p_clk, parent); } void fclk_update(struct fh_clk* p_clk) { - //check if pll0 or xtal - rt_uint32_t mux0; - rt_int32_t ret; - struct fh_clk* parent; //1 step: fix the parent.. + //check if pll0 or xtal + rt_uint32_t mux0; + rt_int32_t ret; + struct fh_clk* parent; //1 step: fix the parent.. - //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); - ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset, - p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } + //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); + ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset, + p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } - //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); - if (mux0 == MUX0_PLL0_CLK) { - //ddr normal parent is pll0 - parent = &pll0; - } else { - //ddr normal parent is xtal - parent = &clk_in; - } - p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; - //2 step:fix the div... - if (mux0 == MUX0_PLL0_CLK) { - //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value); - cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag, - &p_clk->clk.peri.obj.normal.div.pdiv_value); - } - clk_handle(p_clk, parent); + //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); + if (mux0 == MUX0_PLL0_CLK) { + //ddr normal parent is pll0 + parent = &pll0; + } else { + //ddr normal parent is xtal + parent = &clk_in; + } + p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; + //2 step:fix the div... + if (mux0 == MUX0_PLL0_CLK) { + //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value); + cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag, + &p_clk->clk.peri.obj.normal.div.pdiv_value); + } + clk_handle(p_clk, parent); } void pix_update(struct fh_clk* p_clk) { - //check if pll0 or xtal - rt_uint32_t mux0; - rt_int32_t ret; - struct fh_clk* parent; //1 step: fix the parent.. + //check if pll0 or xtal + rt_uint32_t mux0; + rt_int32_t ret; + struct fh_clk* parent; //1 step: fix the parent.. #if(1) - //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); - ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset, - p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } -//#define CIS_PIX_CLK (0) -//#define CIS_PIX_CLK_OPPOSITE (1) -//#define MIPI_PIX_CLK (2) + //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); + ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset, + p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } +//#define CIS_PIX_CLK (0) +//#define CIS_PIX_CLK_OPPOSITE (1) +//#define MIPI_PIX_CLK (2) - //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); - if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) { - //ddr normal parent is pll0 - parent = &cis_pclk; - } else { - parent = &mipi_pix_clk; - } - p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; + //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); + if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) { + //ddr normal parent is pll0 + parent = &cis_pclk; + } else { + parent = &mipi_pix_clk; + } + p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; #endif - clk_handle(p_clk, parent); + clk_handle(p_clk, parent); } void aclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_fclk); + clk_handle(p_clk, &cpu_fclk); } void hclk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void pclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_hclk); + clk_handle(p_clk, &cpu_hclk); } void isp_aclk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void vcu_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void vou_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void mipi_p32_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void cis_clk_out_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void pts_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void mipi_pix_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void spi0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void spi1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void mipi_dphy_clk20m_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void i2c0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void i2c1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void uart0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void pwm_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void time0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void time1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void uart1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sadc_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } //sdc0... void sdc0_clk2x_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sdc0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc0_clk_out_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk); + clk_handle(p_clk, &sdc0_clk); } void sdc0_clk_sample_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc0_clk_drv_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc1_clk2x_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sdc1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void sdc1_clk_out_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk); + clk_handle(p_clk, &sdc1_clk); } void sdc1_clk_sample_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void sdc1_clk_drv_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void eth_ref_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void wdt_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_pclk); + clk_handle(p_clk, &cpu_pclk); } /** * @brief System Clock Configuration */ -#define CLK_CONTROL_BASE PMU_REG_BASE +#define CLK_CONTROL_BASE PMU_REG_BASE void rt_hw_clock_init(void) { - struct fh_clk *p; - int i; - fh_clk_tree.c_base_addr = CLK_CONTROL_BASE; - fh_clk_tree.clk_head = fh_clk_array; + struct fh_clk *p; + int i; + fh_clk_tree.c_base_addr = CLK_CONTROL_BASE; + fh_clk_tree.clk_head = fh_clk_array; - //first open all the clock.. - FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0); - for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { - p = fh_clk_tree.clk_head[i]; - if (p->update_func) - p->update_func(p); - } + //first open all the clock.. + FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0); + for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { + p = fh_clk_tree.clk_head[i]; + if (p->update_func) + p->update_func(p); + } } /*************** @@ -2453,196 +2453,196 @@ void rt_hw_clock_init(void) struct fh_clk *clk_get(const char *name) { - struct fh_clk *p; - int i; + struct fh_clk *p; + int i; - for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { - p = fh_clk_tree.clk_head[i]; - if (!strcmp(p->name, name)) { - return p; - } - } + for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { + p = fh_clk_tree.clk_head[i]; + if (!strcmp(p->name, name)) { + return p; + } + } - return RT_NULL; + return RT_NULL; } // -//#define HAS_GATE (0) -//#define HAS_NO_GATE (1) -// rt_uint32_t gate_flag; -//#define CLK_UNGATE (0) -//#define CLK_GATE (1) +//#define HAS_GATE (0) +//#define HAS_NO_GATE (1) +// rt_uint32_t gate_flag; +//#define CLK_UNGATE (0) +//#define CLK_GATE (1) void clk_gate_control(struct fh_clk *p_clk, rt_uint32_t status) { - if (status > CLK_GATE) - return; + if (status > CLK_GATE) + return; - if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->level == LEVEL_PERIPHERAL) { - switch (p_clk->clk.peri.peri_flag) { - case LEVEL_PERI_NORMAL: + switch (p_clk->clk.peri.peri_flag) { + case LEVEL_PERI_NORMAL: - if (p_clk->clk.peri.obj.normal.gate.gate_flag - == HAS_GATE) { - p_clk->clk.peri.obj.normal.gate.sw_status = - status; - } else { - rt_kprintf("[%-16.15s]: no gate...\t\n", - p_clk->name); - } + if (p_clk->clk.peri.obj.normal.gate.gate_flag + == HAS_GATE) { + p_clk->clk.peri.obj.normal.gate.sw_status = + status; + } else { + rt_kprintf("[%-16.15s]: no gate...\t\n", + p_clk->name); + } - break; - case LEVEL_PERI_DDR: - if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) { - p_clk->clk.peri.obj.ddr.gate.sw_status = status; - } else { - rt_kprintf("[%-16.15s]: no gate...\t\n", - p_clk->name); - } + break; + case LEVEL_PERI_DDR: + if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) { + p_clk->clk.peri.obj.ddr.gate.sw_status = status; + } else { + rt_kprintf("[%-16.15s]: no gate...\t\n", + p_clk->name); + } - break; + break; - default: - break; - } + default: + break; + } - p_clk->update_func(p_clk); + p_clk->update_func(p_clk); - } + } } void clk_gate(struct fh_clk *p_clk) { - clk_gate_control(p_clk, CLK_GATE); + clk_gate_control(p_clk, CLK_GATE); } void clk_ungate(struct fh_clk *p_clk) { - clk_gate_control(p_clk, CLK_UNGATE); + clk_gate_control(p_clk, CLK_UNGATE); } rt_uint32_t clk_get_rate(struct fh_clk *p_clk) { - rt_uint32_t rate; - //first update the status - p_clk->update_func(p_clk); - rate = p_clk->clk_out_rate; - return rate; + rt_uint32_t rate; + //first update the status + p_clk->update_func(p_clk); + rate = p_clk->clk_out_rate; + return rate; } void clk_set_rate(struct fh_clk *p_clk, rt_uint32_t rate_value) { - rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out; + rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out; - if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->level == LEVEL_PERIPHERAL) { - switch (p_clk->clk.peri.peri_flag) { - case LEVEL_PERI_NORMAL: + switch (p_clk->clk.peri.peri_flag) { + case LEVEL_PERI_NORMAL: - clk_in = p_clk->parent->clk_out_rate; - div_flag = p_clk->clk.peri.obj.normal.div.div_flag; - pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value; - div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi; - baud_out = rate_value; + clk_in = p_clk->parent->clk_out_rate; + div_flag = p_clk->clk.peri.obj.normal.div.div_flag; + pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value; + div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi; + baud_out = rate_value; - cal_baud_div(clk_in, div_flag, pre_div, - &p_clk->clk.peri.obj.normal.div.sw_div_value, - div_multi, baud_out); + cal_baud_div(clk_in, div_flag, pre_div, + &p_clk->clk.peri.obj.normal.div.sw_div_value, + div_multi, baud_out); - break; - case LEVEL_PERI_DDR: - //rt_uint32_t mux0,mux1; - clk_in = p_clk->parent->clk_out_rate; - div_flag = p_clk->clk.peri.obj.ddr.div.div_flag; - pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value; - div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi; - baud_out = rate_value; + break; + case LEVEL_PERI_DDR: + //rt_uint32_t mux0,mux1; + clk_in = p_clk->parent->clk_out_rate; + div_flag = p_clk->clk.peri.obj.ddr.div.div_flag; + pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value; + div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi; + baud_out = rate_value; - cal_baud_div(clk_in, div_flag, pre_div, - &p_clk->clk.peri.obj.ddr.div.sw_div_value, - div_multi, baud_out); - break; - case LEVEL_PERI_SDC: - fh_clk_debug(p_clk, - "sdc can't set baud,please set the 'sdcx_clk2x'\n"); - break; - case LEVEL_PERI_GMAC: - fh_clk_debug(p_clk, "gmac not support set baud\n"); - break; - default: - break; - } - p_clk->update_func(p_clk); + cal_baud_div(clk_in, div_flag, pre_div, + &p_clk->clk.peri.obj.ddr.div.sw_div_value, + div_multi, baud_out); + break; + case LEVEL_PERI_SDC: + fh_clk_debug(p_clk, + "sdc can't set baud,please set the 'sdcx_clk2x'\n"); + break; + case LEVEL_PERI_GMAC: + fh_clk_debug(p_clk, "gmac not support set baud\n"); + break; + default: + break; + } + p_clk->update_func(p_clk); - } + } } rt_uint32_t sdc_get_phase(struct fh_clk *p_clk) { - if (p_clk->level == LEVEL_PERIPHERAL) { - if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { + if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { - p_clk->update_func(p_clk); - return p_clk->clk.peri.obj.sdc.phase_diff; - } - } - return SDC_CLK_PARA_ERROR; + p_clk->update_func(p_clk); + return p_clk->clk.peri.obj.sdc.phase_diff; + } + } + return SDC_CLK_PARA_ERROR; } rt_uint32_t sdc_set_phase(struct fh_clk *p_clk, rt_uint32_t phase) { - if (phase > DIFF_SDC_REFCLK_270) - return SDC_CLK_PARA_ERROR; + if (phase > DIFF_SDC_REFCLK_270) + return SDC_CLK_PARA_ERROR; - if (p_clk->level == LEVEL_PERIPHERAL) { - if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { - p_clk->clk.peri.obj.sdc.phase_diff = phase; - p_clk->update_func(p_clk); - return SDC_CLK_PARA_OK; - } - } - return SDC_CLK_PARA_ERROR; + if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { + p_clk->clk.peri.obj.sdc.phase_diff = phase; + p_clk->update_func(p_clk); + return SDC_CLK_PARA_OK; + } + } + return SDC_CLK_PARA_ERROR; } #ifdef FH_DBG_CLK int fh_clk_nlist() { - struct fh_clk *p; - int i; + struct fh_clk *p; + int i; - for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) { - p = fh_clk_tree.clk_head[i]; - //p->update_func(p); - rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate); - } + for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) { + p = fh_clk_tree.clk_head[i]; + //p->update_func(p); + rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate); + } - return 0; + return 0; } int fh_clk_glist() { - struct fh_clk *p; - int i; - rt_kprintf("first bit set means has no gate..\n"); - for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) { - p = fh_clk_tree.clk_head[i]; - //p->update_func(p); - if(!(p->gate & CLK_HAS_NO_GATE)) - rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate); - else - rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name); - } + struct fh_clk *p; + int i; + rt_kprintf("first bit set means has no gate..\n"); + for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) { + p = fh_clk_tree.clk_head[i]; + //p->update_func(p); + if(!(p->gate & CLK_HAS_NO_GATE)) + rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate); + else + rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name); + } - return 0; + return 0; } #endif diff --git a/bsp/fh8620/platform/plat-v2/clock.h b/bsp/fh8620/platform/plat-v2/clock.h index 60b0ed6538..cdf94b017a 100644 --- a/bsp/fh8620/platform/plat-v2/clock.h +++ b/bsp/fh8620/platform/plat-v2/clock.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef TIMER_H_ #define TIMER_H_ @@ -43,12 +43,12 @@ void fh_pmu_open(void); void fh_pmu_close(void); */ -#define DIFF_SDC_REFCLK_0 (0) -#define DIFF_SDC_REFCLK_90 (1) -#define DIFF_SDC_REFCLK_180 (2) -#define DIFF_SDC_REFCLK_270 (3) -#define SDC_CLK_PARA_ERROR (0xffff0000) -#define SDC_CLK_PARA_OK (0) +#define DIFF_SDC_REFCLK_0 (0) +#define DIFF_SDC_REFCLK_90 (1) +#define DIFF_SDC_REFCLK_180 (2) +#define DIFF_SDC_REFCLK_270 (3) +#define SDC_CLK_PARA_ERROR (0xffff0000) +#define SDC_CLK_PARA_OK (0) void clk_gate(struct fh_clk *p_clk); diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.c b/bsp/fh8620/platform/plat-v2/fh_pmu.c index 8f518efd94..d17f215a17 100644 --- a/bsp/fh8620/platform/plat-v2/fh_pmu.c +++ b/bsp/fh8620/platform/plat-v2/fh_pmu.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,45 +18,45 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdebug.h" #include "arch.h" #include "fh_pmu.h" #include "fh_def.h" -#define FH_PMU_WRITEL(offset,value) SET_REG((PMU_REG_BASE + offset),value) -#define FH_PMU_WRITEL_MASK(offset,value, mask) SET_REG_M((PMU_REG_BASE + offset), value, mask) -#define FH_PMU_READL(offset) GET_REG((PMU_REG_BASE + offset)) +#define FH_PMU_WRITEL(offset,value) SET_REG((PMU_REG_BASE + offset),value) +#define FH_PMU_WRITEL_MASK(offset,value, mask) SET_REG_M((PMU_REG_BASE + offset), value, mask) +#define FH_PMU_READL(offset) GET_REG((PMU_REG_BASE + offset)) -#define PMU_OFFSET_MAX 0x1d0 +#define PMU_OFFSET_MAX 0x1d0 int fh_pmu_read(rt_uint32_t offset, rt_uint32_t *value) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - *value = FH_PMU_READL(offset); - return 0; + *value = FH_PMU_READL(offset); + return 0; } int fh_pmu_write(rt_uint32_t offset, const rt_uint32_t value) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - FH_PMU_WRITEL(offset, value); - return 0; + FH_PMU_WRITEL(offset, value); + return 0; } int fh_pmu_write_mask(rt_uint32_t offset, const rt_uint32_t value, - const rt_uint32_t mask) + const rt_uint32_t mask) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - FH_PMU_WRITEL_MASK(offset, value, mask); - return 0; + FH_PMU_WRITEL_MASK(offset, value, mask); + return 0; } diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.h b/bsp/fh8620/platform/plat-v2/fh_pmu.h index 19a6279d1a..4ecedd2fd4 100644 --- a/bsp/fh8620/platform/plat-v2/fh_pmu.h +++ b/bsp/fh8620/platform/plat-v2/fh_pmu.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_PMU_H_ #define FH_PMU_H_ @@ -36,7 +36,7 @@ #define REG_PMU_PLL0_CTRL (0x010) #define REG_PMU_PLL1_CTRL (0x014) #define REG_PMU_ARC_CLK_GATE (0x018) -#define REG_PMU_CLK_GATE (0x01c) +#define REG_PMU_CLK_GATE (0x01c) #define REG_PMU_CLK_SEL (0x020) #define REG_PMU_CLK_DIV0 (0x024) #define REG_PMU_CLK_DIV1 (0x028) diff --git a/bsp/fh8620/platform/plat-v2/iomux.c b/bsp/fh8620/platform/plat-v2/iomux.c index 67acf6ca75..51b14f5937 100644 --- a/bsp/fh8620/platform/plat-v2/iomux.c +++ b/bsp/fh8620/platform/plat-v2/iomux.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,34 +18,34 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdebug.h" #include "iomux.h" static void fh_iomux_setmfs(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel; - break; - default: - break; - } + switch (pad->reg_type) { + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel; + break; + default: + break; + } } @@ -53,50 +53,50 @@ static void fh_iomux_setmfs(Iomux_Pad *pad) static int fh_iomux_getmfs(Iomux_Pad *pad) { - int mfs; + int mfs; - switch (pad->reg_type) { - case 8: - mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs; - break; - case 13: - mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs; - break; - case 20: - mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs; - break; - case 21: - mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs; - break; - default: - mfs = -1; - break; + switch (pad->reg_type) { + case 8: + mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs; + break; + case 13: + mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs; + break; + case 20: + mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs; + break; + case 21: + mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs; + break; + default: + mfs = -1; + break; - } - return mfs; + } + return mfs; } static void fh_iomux_print() { - int i; - UINT32 reg; + int i; + UINT32 reg; - for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) { - int curr_func; + for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) { + int curr_func; - curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]); - reg = readl((UINT32)iomux_obj.pads[i].reg); + curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]); + reg = readl((UINT32)iomux_obj.pads[i].reg); - if (curr_func < 0) - rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0], - reg); - else - rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func], - reg); + if (curr_func < 0) + rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0], + reg); + else + rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func], + reg); - } + } } @@ -105,90 +105,90 @@ static void fh_iomux_print() static void fh_iomux_setcur(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 5: - (IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - default: - break; - } + switch (pad->reg_type) { + case 5: + (IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + default: + break; + } } static void fh_iomux_setpupd(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 9: - (IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd; - break; - default: - break; - } + switch (pad->reg_type) { + case 9: + (IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd; + break; + default: + break; + } } static void fh_iomux_setrest(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 5: - (IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0; - break; - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0; - break; - case 9: - (IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(17)pad->reg)->bit.e = 1; - (IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1; - break; - default: - break; - } + switch (pad->reg_type) { + case 5: + (IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0; + break; + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0; + break; + case 9: + (IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(17)pad->reg)->bit.e = 1; + (IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1; + break; + default: + break; + } } @@ -198,13 +198,13 @@ extern const int fh_iomux_cfg_count; void __fh_setiomux(Iomux_Pad *pad, void *iobase) { - UINT32 regvalue = 0; - pad->reg = ®value; - fh_iomux_setmfs(pad); - fh_iomux_setcur(pad); - fh_iomux_setpupd(pad); - fh_iomux_setrest(pad); - SET_REG(iobase, regvalue); + UINT32 regvalue = 0; + pad->reg = ®value; + fh_iomux_setmfs(pad); + fh_iomux_setcur(pad); + fh_iomux_setpupd(pad); + fh_iomux_setrest(pad); + SET_REG(iobase, regvalue); } static UINT32 g_iomux_base; @@ -212,73 +212,73 @@ static UINT32 g_iomux_base; void fh_iomux_init(UINT32 base) { -// return; - int i; -// int test_cnt = 0; - UINT32 reg; - g_iomux_base = base; +// return; + int i; +// int test_cnt = 0; + UINT32 reg; + g_iomux_base = base; - iomux_obj.pbase = (void *)base; + iomux_obj.pbase = (void *)base; -// iomux_obj.vbase = (UINT32 *)rt_malloc(1024); - iomux_obj.pads = fh_iomux_cfg; +// iomux_obj.vbase = (UINT32 *)rt_malloc(1024); + iomux_obj.pads = fh_iomux_cfg; - for (i = 0; i < fh_iomux_cfg_count; i++) { + for (i = 0; i < fh_iomux_cfg_count; i++) { #if (1) - iomux_obj.pads[i].id = i; - iomux_obj.pads[i].reg_offset = i * 4; - iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset); - fh_iomux_setmfs(&fh_iomux_cfg[i]); - fh_iomux_setcur(&fh_iomux_cfg[i]); - fh_iomux_setpupd(&fh_iomux_cfg[i]); - fh_iomux_setrest(&fh_iomux_cfg[i]); - SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg); -// *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset))); - //rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset)); -// test_cnt++; + iomux_obj.pads[i].id = i; + iomux_obj.pads[i].reg_offset = i * 4; + iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset); + fh_iomux_setmfs(&fh_iomux_cfg[i]); + fh_iomux_setcur(&fh_iomux_cfg[i]); + fh_iomux_setpupd(&fh_iomux_cfg[i]); + fh_iomux_setrest(&fh_iomux_cfg[i]); + SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg); +// *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset))); + //rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset)); +// test_cnt++; #else #ifdef FH_USING_JTAG - if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0) - continue; + if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0) + continue; #endif /* - if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0) - break; + if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0) + break; */ - __fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4); + __fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4); #endif - } + } #ifdef CONFIG_RMII - //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1; - reg = GET_REG(0xf00000a4); - reg |= (1 << 13); - SET_REG(0xf00000a4, reg); + //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1; + reg = GET_REG(0xf00000a4); + reg |= (1 << 13); + SET_REG(0xf00000a4, reg); #else - //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0; - reg = GET_REG(0xf00000a4); - reg &= ~(1 << 13); - SET_REG(0xf00000a4, reg); + //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0; + reg = GET_REG(0xf00000a4); + reg &= ~(1 << 13); + SET_REG(0xf00000a4, reg); #endif #ifdef IOMUX_DEBUG - fh_iomux_print(iomux_obj); + fh_iomux_print(iomux_obj); #endif - //rt_free(iomux_obj.vbase); - //iomux_obj.vbase = 0; + //rt_free(iomux_obj.vbase); + //iomux_obj.vbase = 0; } void fh_iomux_pin_switch(int pin_num, int func_num) { - RT_ASSERT(pin_num < fh_iomux_cfg_count); - __fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4); - /* - fh_iomux_cfg[pin_num].func_sel = func_num; - fh_iomux_setmfs(&fh_iomux_cfg[pin_num]); - SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset))); - */ + RT_ASSERT(pin_num < fh_iomux_cfg_count); + __fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4); + /* + fh_iomux_cfg[pin_num].func_sel = func_num; + fh_iomux_setmfs(&fh_iomux_cfg[pin_num]); + SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset))); + */ } diff --git a/bsp/fh8620/platform/plat-v2/iomux.h b/bsp/fh8620/platform/plat-v2/iomux.h index e03273b2b8..a0aa8d338e 100644 --- a/bsp/fh8620/platform/plat-v2/iomux.h +++ b/bsp/fh8620/platform/plat-v2/iomux.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef IOMUX_H_ #define IOMUX_H_ @@ -126,179 +126,179 @@ #define PMU_PAD_MAC_TXER (92) -#define IOMUX_PADTYPE(n) (Iomux_PadType##n *) -#define IOMUX_PUPD_NONE 0 -#define IOMUX_PUPD_DOWN 1 -#define IOMUX_PUPD_UP 2 -#define IOMUX_PUPD_KEEPER 3 +#define IOMUX_PADTYPE(n) (Iomux_PadType##n *) +#define IOMUX_PUPD_NONE 0 +#define IOMUX_PUPD_DOWN 1 +#define IOMUX_PUPD_UP 2 +#define IOMUX_PUPD_KEEPER 3 //#define IOMUX_DEBUG typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_31_6 :24; + UINT32 e8_e4 :2; + UINT32 reserved_31_6 :24; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType5; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_7_6 :2; + UINT32 e8_e4 :2; + UINT32 reserved_7_6 :2; - UINT32 mfs :1; - UINT32 reserved_31_9 :23; + UINT32 mfs :1; + UINT32 reserved_31_9 :23; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType8; typedef union { - struct - { - UINT32 smt :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 smt :1; + UINT32 reserved_3_1 :3; - UINT32 ie :1; - UINT32 reserved_7_5 :3; + UINT32 ie :1; + UINT32 reserved_7_5 :3; - UINT32 pu_pd :2; - UINT32 reserved_31_10 :22; + UINT32 pu_pd :2; + UINT32 reserved_31_10 :22; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType9; typedef union { - struct - { - UINT32 e4_e2 :2; - UINT32 reserved_3_2 :2; + struct + { + UINT32 e4_e2 :2; + UINT32 reserved_3_2 :2; - UINT32 smt :1; - UINT32 reserved_7_5 :3; + UINT32 smt :1; + UINT32 reserved_7_5 :3; - UINT32 ie :1; - UINT32 reserved_11_9 :3; + UINT32 ie :1; + UINT32 reserved_11_9 :3; - UINT32 mfs :2; - UINT32 reserved_31_14 :18; + UINT32 mfs :2; + UINT32 reserved_31_14 :18; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType13; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_7_6 :2; + UINT32 e8_e4 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 e :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4) - UINT32 reserved_15_12 :2; + UINT32 ie :1; + UINT32 e :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4) + UINT32 reserved_15_12 :2; - UINT32 pu_pd :2; - UINT32 reserved_31_18 :14; + UINT32 pu_pd :2; + UINT32 reserved_31_18 :14; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType17; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e4_e2 :2; - UINT32 reserved_7_6 :2; + UINT32 e4_e2 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 reserved_15_13 :3; + UINT32 ie :1; + UINT32 reserved_15_13 :3; - UINT32 pu_pd :2; - UINT32 reserved_19_18 :2; + UINT32 pu_pd :2; + UINT32 reserved_19_18 :2; - UINT32 mfs :1; - UINT32 reserved_31_21 :11; + UINT32 mfs :1; + UINT32 reserved_31_21 :11; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType20; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e4_e2 :2; - UINT32 reserved_7_6 :2; + UINT32 e4_e2 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 reserved_15_13 :3; + UINT32 ie :1; + UINT32 reserved_15_13 :3; - UINT32 pu_pd :2; - UINT32 reserved_19_18 :2; + UINT32 pu_pd :2; + UINT32 reserved_19_18 :2; - UINT32 mfs :2; - UINT32 reserved_31_21 :10; + UINT32 mfs :2; + UINT32 reserved_31_21 :10; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType21; typedef struct { int id; - UINT32* reg; - UINT32 reg_offset; - char* func_name[4]; - int reg_type; - int func_sel; - int drv_cur; - int pupd; - //UINT32 value; + UINT32* reg; + UINT32 reg_offset; + char* func_name[4]; + int reg_type; + int func_sel; + int drv_cur; + int pupd; + //UINT32 value; }Iomux_Pad; typedef struct { - void *vbase; - void *pbase; - Iomux_Pad *pads; + void *vbase; + void *pbase; + Iomux_Pad *pads; }Iomux_Object; diff --git a/bsp/fh8620/platform/plat-v2/reset.c b/bsp/fh8620/platform/plat-v2/reset.c index 654a0745e9..aa7024169f 100644 --- a/bsp/fh8620/platform/plat-v2/reset.c +++ b/bsp/fh8620/platform/plat-v2/reset.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include <rthw.h> #include <rtthread.h> #include "fh_pmu.h" @@ -32,13 +32,13 @@ void machine_reset(void) { - fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff); + fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff); } void machine_shutdown(void) { - while(1) - ; + while(1) + ; } diff --git a/bsp/fh8620/platform/plat-v2/timer.c b/bsp/fh8620/platform/plat-v2/timer.c index de831db3c6..96bcc6f39d 100644 --- a/bsp/fh8620/platform/plat-v2/timer.c +++ b/bsp/fh8620/platform/plat-v2/timer.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -43,48 +43,48 @@ static unsigned long long timestamp; rt_uint32_t read_pts(void) { - return GET_REG(REG_PAE_PTS_REG); + return GET_REG(REG_PAE_PTS_REG); } unsigned long long get_ticks(void) { - rt_uint32_t now = read_pts(); - if (now >= lastdec) { - /* normal mode */ - timestamp += now - lastdec; - } else { - now = read_pts(); - if (now >= lastdec) - timestamp += now - lastdec; - else { - /* we have an overflow ... */ - timestamp += now + 0xffffffff - lastdec; - } - } - lastdec = now; - return timestamp / (TICKS_PER_USEC * 10); + rt_uint32_t now = read_pts(); + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + now = read_pts(); + if (now >= lastdec) + timestamp += now - lastdec; + else { + /* we have an overflow ... */ + timestamp += now + 0xffffffff - lastdec; + } + } + lastdec = now; + return timestamp / (TICKS_PER_USEC * 10); } void udelay(unsigned long usec) { - unsigned long long tmp; - rt_uint32_t tmo; - tmo = (usec + 9) / 10; - tmp = get_ticks() + tmo; /* get current timestamp */ + unsigned long long tmp; + rt_uint32_t tmo; + tmo = (usec + 9) / 10; + tmp = get_ticks() + tmo; /* get current timestamp */ - while (get_ticks() < tmp) - /* loop till event */ - /*NOP*/; + while (get_ticks() < tmp) + /* loop till event */ + /*NOP*/; } void rt_timer_handler(int vector, void *param) { - timer *tim = param; + timer *tim = param; - rt_interrupt_enter(); - timer_get_eoi(tim); - rt_tick_increase(); - rt_interrupt_leave(); + rt_interrupt_enter(); + timer_get_eoi(tim); + rt_tick_increase(); + rt_interrupt_leave(); } /** @@ -92,18 +92,18 @@ void rt_timer_handler(int vector, void *param) */ void rt_hw_timer_init() { - timer *tim = (timer *) TMR_REG_BASE; - timer_init(tim); - /* install interrupt handler */ - rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim, - "sys_tick"); - rt_hw_interrupt_umask(TMR0_IRQn); + timer *tim = (timer *) TMR_REG_BASE; + timer_init(tim); + /* install interrupt handler */ + rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim, + "sys_tick"); + rt_hw_interrupt_umask(TMR0_IRQn); - timer_set_mode(tim, TIMER_MODE_PERIODIC); - timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK); - //timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK); - timer_enable_irq(tim); - timer_enable(tim); + timer_set_mode(tim, TIMER_MODE_PERIODIC); + timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK); + //timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK); + timer_enable_irq(tim); + timer_enable(tim); } diff --git a/bsp/fh8620/platform/plat-v2/timer.h b/bsp/fh8620/platform/plat-v2/timer.h index 5ee024a094..bbccdfa826 100644 --- a/bsp/fh8620/platform/plat-v2/timer.h +++ b/bsp/fh8620/platform/plat-v2/timer.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef TIMER_H_ #define TIMER_H_ diff --git a/bsp/fh8620/platform/platform_def.h b/bsp/fh8620/platform/platform_def.h index b511863981..a576220f3e 100644 --- a/bsp/fh8620/platform/platform_def.h +++ b/bsp/fh8620/platform/platform_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef PLATFORM_DEF_H_ #define PLATFORM_DEF_H_ diff --git a/bsp/fh8620/rtconfig.h b/bsp/fh8620/rtconfig.h index 8b7ce31be1..78749abdfa 100644 --- a/bsp/fh8620/rtconfig.h +++ b/bsp/fh8620/rtconfig.h @@ -5,19 +5,19 @@ // <RDTConfigurator URL="http://www.rt-thread.com/eclipse"> // <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" /> -#define RT_NAME_MAX 16 +#define RT_NAME_MAX 16 // <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" /> -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32"> // <item description="8">8</item> // <item description="32">32</item> // <item description="256">256</item> // </integer> -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 // <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" /> -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 // <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" /> -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 // <bool name="RT_USING_MODULE" description="Using Application Module" default="true" /> // #define RT_USING_MODULE // <bool name="RT_USING_CPU_FFS" description="Using CPU instructions for ffs function" default="true" /> @@ -36,11 +36,11 @@ // <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" > // #define RT_USING_TIMER_SOFT // <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" /> -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" /> -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" /> -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_TICK_PER_SECOND 100 // </section> // <section name="IPC" description="Inter-Thread communication" default="always" > @@ -86,13 +86,13 @@ // <bool name="RT_USING_RTC" description="Using RTC Device Driver Framework" default="true" /> //#define RT_USING_RTC // <integer name="RT_MMCSD_THREAD_PREORITY" description="The prority of mmcsd thread" default="15" /> -#define RT_MMCSD_THREAD_PREORITY 15 +#define RT_MMCSD_THREAD_PREORITY 15 // <section name="RT_USING_CONSOLE" description="Using console" default="true" > #define RT_USING_CONSOLE // <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" /> -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" /> -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart1" // </section> // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" /> @@ -105,7 +105,7 @@ // <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" /> #define FINSH_USING_DESCRIPTION // <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" /> -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 // </section> // <section name="LIBC" description="C Runtime library setting" default="always" > @@ -124,9 +124,9 @@ // <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" /> #define DFS_USING_WORKDIR // <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" /> -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" /> -#define DFS_FD_MAX 16 +#define DFS_FD_MAX 16 // <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" /> #define RT_USING_DFS_ELMFAT // <integer name="RT_DFS_ELM_DRIVES" description="The maximal number of drives of FatFs" default="4" /> @@ -138,13 +138,13 @@ // <item description="LFN with dynamic LFN working buffer on the stack">2</item> // <item description="LFN with dynamic LFN working buffer on the heap">3</item> // </integer> -#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_USE_LFN 3 // <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936"> -#define RT_DFS_ELM_CODE_PAGE 936 +#define RT_DFS_ELM_CODE_PAGE 936 // <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" /> #define RT_DFS_ELM_CODE_PAGE_FILE // <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" /> -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_MAX_LFN 255 // <integer name="RT_DFS_ELM_MAX_SECTOR_SIZE" description="Maximal size of sector" default="512" /> #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 // <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" /> @@ -174,19 +174,19 @@ // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" /> #define RT_LWIP_DHCP // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" /> -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" /> -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" /> -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" /> -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" /> -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" /> -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" /> -#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_IPADDR "192.168.1.30" // <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" /> #define RT_LWIP_GWADDR "192.168.1.1" // <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" /> diff --git a/bsp/rx/ReadMe.txt b/bsp/rx/README.md index 956e2e00a1..956e2e00a1 100644 --- a/bsp/rx/ReadMe.txt +++ b/bsp/rx/README.md diff --git a/bsp/rx/applications/application.c b/bsp/rx/applications/application.c index 4a6e250429..2013a3c69a 100644 --- a/bsp/rx/applications/application.c +++ b/bsp/rx/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -14,7 +10,7 @@ */ /** - * @addtogroup STM32 + * @addtogroup */ /*@{*/ diff --git a/bsp/rx/applications/startup.c b/bsp/rx/applications/startup.c index 4b195492f6..92d415c620 100644 --- a/bsp/rx/applications/startup.c +++ b/bsp/rx/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -90,7 +86,7 @@ int main(void) { rt_hw_system_freq_init(); - + __enable_interrupt(); /* disable interrupt first */ rt_hw_interrupt_disable(); diff --git a/bsp/rx/drivers/Uart.h b/bsp/rx/drivers/Uart.h index 9354861ca3..cc8aeaf5df 100644 --- a/bsp/rx/drivers/Uart.h +++ b/bsp/rx/drivers/Uart.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __UART_H__ #define __UART_H__ diff --git a/bsp/rx/drivers/board.c b/bsp/rx/drivers/board.c index 4e02325325..aa80014066 100644 --- a/bsp/rx/drivers/board.c +++ b/bsp/rx/drivers/board.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include <rthw.h> #include <rtthread.h> #include "board.h" @@ -17,7 +26,7 @@ * */ #pragma vector = VECT_CMT0_CMI0 -__interrupt +__interrupt void SysTick_Handler(void) { // __enable_interrupt(); @@ -56,7 +65,7 @@ void rt_hw_systick_init(void) } void rt_hw_system_freq_init(void) -{ +{ /* Declare error flag */ bool err = true; @@ -69,15 +78,15 @@ void rt_hw_system_freq_init(void) 24E6, PDL_NO_DATA ); - /* + /* Clock Description Frequency ---------------------------------------- Input Clock Frequency..............12MHz - Internal Clock Frequency...........96MHz + Internal Clock Frequency...........96MHz Peripheral Clock Frequency.........48MHz External Bus Clock Frequency.......24MHz */ - /* Halt in while loop when RPDL errors detected */ + /* Halt in while loop when RPDL errors detected */ while (!err); } @@ -86,8 +95,8 @@ void rt_hw_system_freq_init(void) */ void rt_hw_board_init() { - - rt_hw_system_freq_init(); + + rt_hw_system_freq_init(); rt_hw_systick_init(); rt_hw_uart_init(); #ifdef RT_USING_CONSOLE diff --git a/bsp/rx/drivers/board.h b/bsp/rx/drivers/board.h index 870e805a99..117521d033 100644 --- a/bsp/rx/drivers/board.h +++ b/bsp/rx/drivers/board.h @@ -1,11 +1,21 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + + #ifndef __BOARD_H__ #define __BOARD_H__ -#define XTAL_FREQUENCY (12000000L) -#define ICLK_MUL (8) -#define PCLK_MUL (4) -#define BCLK_MUL (2) +#define XTAL_FREQUENCY (12000000L) +#define ICLK_MUL (8) +#define PCLK_MUL (4) +#define BCLK_MUL (2) #define RX62N_SRAM_END 0x0000ffff diff --git a/bsp/rx/drivers/uart.c b/bsp/rx/drivers/uart.c index 9e304ac95c..37d65ba8c0 100644 --- a/bsp/rx/drivers/uart.c +++ b/bsp/rx/drivers/uart.c @@ -1,9 +1,11 @@ /* -********************************************************************************************************* -* Filename : uart.c -********************************************************************************************************* -*/ - + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include <rthw.h> #include <rtthread.h> @@ -22,18 +24,18 @@ /* Clock selection control */ -#define SCI_CKS_MIN 0 -#define SCI_CKS_MAX 3 -#define SCI_CKS_STEP 1 +#define SCI_CKS_MIN 0 +#define SCI_CKS_MAX 3 +#define SCI_CKS_STEP 1 -#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a]) +#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a]) //#define IER_ADDRESS(a) ((volatile unsigned char *)&(ICU.IER[IER_SCI0_ERI0 + a])/sizeof(unsigned char)) -#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) -#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) -#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) ) -#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) ) -#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) ) +#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) +#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) ) +#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) ) +#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) ) +#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) ) #define RXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_RXI0]+ ((4*a)/sizeof(unsigned char))) #define TXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_TXI0]+ ((4*a) / sizeof(unsigned char))) //#define SCI1_USE_B @@ -44,8 +46,8 @@ #define SourceClk 12000000 #define rpdl_CGC_f_pclk SourceClk * 4 /* Idle output options */ -#define SPACE 0 -#define MARK 1 +#define SPACE 0 +#define MARK 1 typedef int UART_ID_Type; typedef int IRQn_Type; @@ -55,14 +57,14 @@ typedef int IRQn_Type; struct rx_uart { UART_ID_Type UART; - volatile struct st_sci __sfr * sci; + volatile struct st_sci __sfr * sci; }; static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { #if 1 struct rx_uart *uart; - + unsigned char smr_copy; unsigned char semr_copy; unsigned char scr_copy; @@ -81,7 +83,7 @@ static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_conf semr_copy = 0x00u; scmr_copy = 0x72u; brr_divider = 0; - + switch (uart->UART) { case 0: SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; @@ -257,11 +259,11 @@ case 0: } /*parity*/ - if (cfg->parity == PARITY_ODD) + if (cfg->parity == PARITY_ODD) smr_copy |= BIT_5; - else if (cfg->parity == PARITY_EVEN) + else if (cfg->parity == PARITY_EVEN) smr_copy |= BIT_4 | BIT_5; - + brr_divider = rpdl_CGC_f_pclk / cfg->baud_rate; @@ -304,13 +306,13 @@ case 0: }while (bit_interval_counter != 0); scr_copy = 0x00u; - + /*enable rx an tx*/ scr_copy |= BIT_5 | BIT_4 ; uart->sci->SCR.BYTE &= 0x5B; uart->sci->SCR.BYTE |= scr_copy; - + *(IPR_ADDRESS(uart->UART)) = 5; uart->sci->SSR.BYTE = 0xC0; uart->sci->SSR.BYTE &= INV_BIT_5; @@ -363,9 +365,9 @@ case 0: break; } - flag |= PDL_SCI_ASYNC | - PDL_SCI_TX_CONNECTED | - PDL_SCI_RX_CONNECTED | + flag |= PDL_SCI_ASYNC | + PDL_SCI_TX_CONNECTED | + PDL_SCI_RX_CONNECTED | PDL_SCI_CLK_INT_IO ; /* Configure the RS232 port */ err &= R_SCI_Create( @@ -373,12 +375,12 @@ case 0: flag, cfg->baud_rate, 5); - + uart->sci->SCR.BYTE |= BIT_4|BIT_5; __enable_interrupt(); #endif - + switch (uart->UART) { case 0: @@ -430,7 +432,7 @@ case 0: break; } - + return RT_EOK; } @@ -464,7 +466,7 @@ static int rx_putc(struct rt_serial_device *serial, char c) uart = (struct rx_uart *)serial->parent.user_data; while (uart->sci->SSR.BIT.TDRE == 0); uart->sci->TDR = c; - return 1; + return 1; } static int rx_getc(struct rt_serial_device *serial) @@ -528,15 +530,15 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &rx_uart_ops; serial2.config = config; /* register UART1 device */ rt_hw_serial_register(&serial2, "uart2", - RT_DEVICE_FLAG_RDWR | - RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); #endif diff --git a/bsp/rx/rtconfig.h b/bsp/rx/rtconfig.h index 6f055dce1a..57524271da 100644 --- a/bsp/rx/rtconfig.h +++ b/bsp/rx/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -27,9 +27,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -72,9 +72,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" /> -#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_CONSOLE_DEVICE_NAME "uart2" /* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH @@ -89,17 +89,17 @@ /* Reentrancy (thread safe) of the FatFs module. */ #define RT_DFS_ELM_REENTRANT /* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -/* #define RT_DFS_ELM_CODE_PAGE 936 */ -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +/* #define RT_DFS_ELM_USE_LFN 1 */ +/* #define RT_DFS_ELM_CODE_PAGE 936 */ +#define RT_DFS_ELM_MAX_LFN 255 /* Maximum sector size to be handled. */ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* #define RT_USING_LWIP */ @@ -113,49 +113,49 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 /* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 +#define RT_LWIP_TCP_SND_BUF 8192 /* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +#define RT_LWIP_TCP_WND 8192 /* SECTION: RT-Thread/GUI */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -171,7 +171,7 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 /* image support */ /* #define RTGUI_IMAGE_XPM */ diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript index e4fe5d3259..75372b529e 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript @@ -24,6 +24,7 @@ STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c ''') if GetDepend(['RT_USING_SERIAL']): diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/main.c b/bsp/stm32/stm32f072-st-nucleo/applications/main.c index 486ed61283..1d48ded64d 100644 --- a/bsp/stm32/stm32f072-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f072-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f091-st-nucleo/applications/main.c b/bsp/stm32/stm32f091-st-nucleo/applications/main.c index 9783d01e55..61981d49b0 100644 --- a/bsp/stm32/stm32f091-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f091-st-nucleo/applications/main.c @@ -17,19 +17,16 @@ int main(void) { - int count = 1; - /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c index be493624c1..8569ce27bd 100644 --- a/bsp/stm32/stm32f103-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c index 55c2b62023..8de9bd81e9 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c @@ -19,13 +19,12 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_pin_write(LED1_PIN, PIN_HIGH); @@ -34,6 +33,4 @@ int main(void) rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-blue-pill/applications/main.c b/bsp/stm32/stm32f103-blue-pill/applications/main.c index 9be4cd59b1..1fcf936a48 100644 --- a/bsp/stm32/stm32f103-blue-pill/applications/main.c +++ b/bsp/stm32/stm32f103-blue-pill/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c index 0ec4930664..3101374062 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c index dc4e9cbb7e..ce702bb417 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c index 7ddaa5ee96..e3078f4e82 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c index bf9e60aae9..a2ffe21b45 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED4_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED4_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c index 096b4df406..5ba5873b52 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c index be493624c1..8569ce27bd 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c +++ b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f103-yf-ufun/applications/main.c b/bsp/stm32/stm32f103-yf-ufun/applications/main.c index ffe4955e19..8f9c5c7a07 100644 --- a/bsp/stm32/stm32f103-yf-ufun/applications/main.c +++ b/bsp/stm32/stm32f103-yf-ufun/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED3_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED3_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED3_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f107-uc-eval/applications/main.c b/bsp/stm32/stm32f107-uc-eval/applications/main.c index 9dca242b10..9f1a27444d 100644 --- a/bsp/stm32/stm32f107-uc-eval/applications/main.c +++ b/bsp/stm32/stm32f107-uc-eval/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/main.c b/bsp/stm32/stm32f401-st-nucleo/applications/main.c index 48009f1c78..d4200202ed 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f401-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c index 47358c8a61..9f52445b11 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c index 2fc9307caf..9fb7ebf153 100644 --- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f407-st-discovery/applications/main.c b/bsp/stm32/stm32f407-st-discovery/applications/main.c index 2651a75073..ecc3464e69 100644 --- a/bsp/stm32/stm32f407-st-discovery/applications/main.c +++ b/bsp/stm32/stm32f407-st-discovery/applications/main.c @@ -17,11 +17,10 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); diff --git a/bsp/stm32/stm32f410-st-nucleo/applications/main.c b/bsp/stm32/stm32f410-st-nucleo/applications/main.c index 05ab0e2504..0de22d3ffd 100644 --- a/bsp/stm32/stm32f410-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f410-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f411-atk-nano/applications/main.c b/bsp/stm32/stm32f411-atk-nano/applications/main.c index df457f4760..351b59dc19 100644 --- a/bsp/stm32/stm32f411-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f411-atk-nano/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c index 0e109663ae..9f36615507 100644 --- a/bsp/stm32/stm32f411-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c index be6a8af867..f28cc62dd2 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c +++ b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/main.c b/bsp/stm32/stm32f412-st-nucleo/applications/main.c index 2cf35c5bc6..3bc5104ea7 100644 --- a/bsp/stm32/stm32f412-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f412-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f413-st-nucleo/applications/main.c b/bsp/stm32/stm32f413-st-nucleo/applications/main.c index 799dc6797d..ddd672e739 100644 --- a/bsp/stm32/stm32f413-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f413-st-nucleo/applications/main.c @@ -23,16 +23,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/main.c b/bsp/stm32/stm32f427-robomaster-a/applications/main.c index 6cef3cbb34..f63f29396c 100644 --- a/bsp/stm32/stm32f427-robomaster-a/applications/main.c +++ b/bsp/stm32/stm32f427-robomaster-a/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f429-armfly-v6/applications/main.c b/bsp/stm32/stm32f429-armfly-v6/applications/main.c index 21b7c14ec0..152a11bab1 100644 --- a/bsp/stm32/stm32f429-armfly-v6/applications/main.c +++ b/bsp/stm32/stm32f429-armfly-v6/applications/main.c @@ -15,20 +15,16 @@ int main(void) { - int count = 1; - HC574_SetPin(LED1,0); HC574_SetPin(LED2,0); HC574_SetPin(LED3,0); HC574_SetPin(LED4,0); - while (count++) + while (1) { HC574_SetPin(LED1,1); rt_thread_mdelay(500); HC574_SetPin(LED1,0); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c index 6d19a46edb..609b4e63b4 100644 --- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c index 64e40b75c8..27c28e0cb2 100644 --- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f429-st-disco/applications/main.c b/bsp/stm32/stm32f429-st-disco/applications/main.c index 992f2b5d74..48f43fd6fa 100644 --- a/bsp/stm32/stm32f429-st-disco/applications/main.c +++ b/bsp/stm32/stm32f429-st-disco/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f446-st-nucleo/applications/main.c b/bsp/stm32/stm32f446-st-nucleo/applications/main.c index 897c6eec1c..b419a79449 100644 --- a/bsp/stm32/stm32f446-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f446-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f469-st-disco/applications/main.c b/bsp/stm32/stm32f469-st-disco/applications/main.c index 759572d376..e5a331ad8c 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/main.c +++ b/bsp/stm32/stm32f469-st-disco/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f746-st-disco/applications/main.c b/bsp/stm32/stm32f746-st-disco/applications/main.c index 0024ce1c0a..d98649e9c6 100644 --- a/bsp/stm32/stm32f746-st-disco/applications/main.c +++ b/bsp/stm32/stm32f746-st-disco/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f767-atk-apollo/applications/main.c b/bsp/stm32/stm32f767-atk-apollo/applications/main.c index 71e6132ea2..bec589c403 100644 --- a/bsp/stm32/stm32f767-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f767-atk-apollo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c index 4cf67f2e9e..3570c667c9 100644 --- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f767-fire-challenger/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f767-st-nucleo/applications/main.c b/bsp/stm32/stm32f767-st-nucleo/applications/main.c index a0967c1326..e270c27a91 100644 --- a/bsp/stm32/stm32f767-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f767-st-nucleo/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32f769-st-disco/applications/main.c b/bsp/stm32/stm32f769-st-disco/applications/main.c index d61afe14c3..396afa994a 100644 --- a/bsp/stm32/stm32f769-st-disco/applications/main.c +++ b/bsp/stm32/stm32f769-st-disco/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED1 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/main.c b/bsp/stm32/stm32g070-st-nucleo/applications/main.c index 5f22fcae65..a438b9e67d 100644 --- a/bsp/stm32/stm32g070-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g070-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32g071-st-nucleo/applications/main.c b/bsp/stm32/stm32g071-st-nucleo/applications/main.c index 5f22fcae65..a438b9e67d 100644 --- a/bsp/stm32/stm32g071-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g071-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32g431-st-nucleo/applications/main.c b/bsp/stm32/stm32g431-st-nucleo/applications/main.c index fa4fd35a6e..5524d24935 100644 --- a/bsp/stm32/stm32g431-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g431-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32h743-atk-apollo/applications/main.c b/bsp/stm32/stm32h743-atk-apollo/applications/main.c index 376d3c78ff..c52580b1b1 100644 --- a/bsp/stm32/stm32h743-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32h743-atk-apollo/applications/main.c @@ -17,16 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32h743-st-nucleo/applications/main.c b/bsp/stm32/stm32h743-st-nucleo/applications/main.c index 9a8ac51bb5..ef1884d3bc 100644 --- a/bsp/stm32/stm32h743-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32h743-st-nucleo/applications/main.c @@ -17,16 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32h747-st-discovery/applications/main.c b/bsp/stm32/stm32h747-st-discovery/applications/main.c index 3904f7b3bc..2a91e93091 100644 --- a/bsp/stm32/stm32h747-st-discovery/applications/main.c +++ b/bsp/stm32/stm32h747-st-discovery/applications/main.c @@ -17,16 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c index b19e338dc5..90a52049e4 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c @@ -17,16 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32h750-artpi-h750/applications/main.c b/bsp/stm32/stm32h750-artpi-h750/applications/main.c index 6ab088b624..d4b0bb98a6 100644 --- a/bsp/stm32/stm32h750-artpi-h750/applications/main.c +++ b/bsp/stm32/stm32h750-artpi-h750/applications/main.c @@ -17,16 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - return RT_EOK; } diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/main.c b/bsp/stm32/stm32l010-st-nucleo/applications/main.c index 5f22fcae65..a438b9e67d 100644 --- a/bsp/stm32/stm32l010-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l010-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l053-st-nucleo/applications/main.c b/bsp/stm32/stm32l053-st-nucleo/applications/main.c index 5f22fcae65..a438b9e67d 100644 --- a/bsp/stm32/stm32l053-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l053-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/main.c b/bsp/stm32/stm32l412-st-nucleo/applications/main.c index b22a9d1ba3..296c33d352 100644 --- a/bsp/stm32/stm32l412-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l412-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LD4 pin mode to output */ rt_pin_mode(LD4_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LD4_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LD4_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l431-BearPi/applications/main.c b/bsp/stm32/stm32l431-BearPi/applications/main.c index 9222b842fc..b5409814f6 100644 --- a/bsp/stm32/stm32l431-BearPi/applications/main.c +++ b/bsp/stm32/stm32l431-BearPi/applications/main.c @@ -17,19 +17,15 @@ int main(void) { - int count = 1; + rt_kprintf("---Welcome use BearPi---\n"); + /* set LED pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_kprintf("---Welcome use BearPi---\n"); - /* set LED pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED0_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED0_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - - return RT_EOK; + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } } diff --git a/bsp/stm32/stm32l432-st-nucleo/applications/main.c b/bsp/stm32/stm32l432-st-nucleo/applications/main.c index 336347c11e..d3654159d8 100644 --- a/bsp/stm32/stm32l432-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l432-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l433-st-nucleo/applications/main.c b/bsp/stm32/stm32l433-st-nucleo/applications/main.c index 056bad6689..93992725f1 100644 --- a/bsp/stm32/stm32l433-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l433-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l452-st-nucleo/applications/main.c b/bsp/stm32/stm32l452-st-nucleo/applications/main.c index fa4fd35a6e..5524d24935 100644 --- a/bsp/stm32/stm32l452-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l452-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c index dfad8c68c1..7410e0463e 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l475-st-discovery/applications/main.c b/bsp/stm32/stm32l475-st-discovery/applications/main.c index bddb8abe63..c0c25b6705 100644 --- a/bsp/stm32/stm32l475-st-discovery/applications/main.c +++ b/bsp/stm32/stm32l475-st-discovery/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/main.c b/bsp/stm32/stm32l476-st-nucleo/applications/main.c index b22a8b8e8d..2c204ae916 100644 --- a/bsp/stm32/stm32l476-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l476-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l496-ali-developer/applications/main.c b/bsp/stm32/stm32l496-ali-developer/applications/main.c index 86d1cf72dd..1d40627d3c 100644 --- a/bsp/stm32/stm32l496-ali-developer/applications/main.c +++ b/bsp/stm32/stm32l496-ali-developer/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l496-st-nucleo/applications/main.c b/bsp/stm32/stm32l496-st-nucleo/applications/main.c index efe91875b9..6c19612f99 100644 --- a/bsp/stm32/stm32l496-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l496-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c index 2dbb2b2c81..845e68f25f 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c @@ -23,17 +23,13 @@ int main(void) { - int count = 1; - rt_pin_mode(LED_RUN_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED_RUN_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED_RUN_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32l4r9-st-eval/applications/main.c b/bsp/stm32/stm32l4r9-st-eval/applications/main.c index c53f70fb97..ea49f25f87 100644 --- a/bsp/stm32/stm32l4r9-st-eval/applications/main.c +++ b/bsp/stm32/stm32l4r9-st-eval/applications/main.c @@ -18,17 +18,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED0_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c index 85d9d3ba89..b5425e474b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c +++ b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LD7 pin mode to output */ rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED7_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED7_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h index bcceba61a0..5220e13b97 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h @@ -18,18 +18,21 @@ #include <stdlib.h> +extern void *rt_malloc(unsigned long nbytes); +extern void rt_free(void *ptr); + #ifdef __cplusplus extern "C" { #endif static inline void *metal_allocate_memory(unsigned int size) { - return (malloc(size)); + return (rt_malloc(size)); } static inline void metal_free_memory(void *ptr) { - free(ptr); + rt_free(ptr); } #ifdef __cplusplus diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h index bcceba61a0..5220e13b97 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h @@ -18,18 +18,21 @@ #include <stdlib.h> +extern void *rt_malloc(unsigned long nbytes); +extern void rt_free(void *ptr); + #ifdef __cplusplus extern "C" { #endif static inline void *metal_allocate_memory(unsigned int size) { - return (malloc(size)); + return (rt_malloc(size)); } static inline void metal_free_memory(void *ptr) { - free(ptr); + rt_free(ptr); } #ifdef __cplusplus diff --git a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c index 6e70b83927..71f2ba733a 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c +++ b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LD8 pin mode to output */ rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED4_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED4_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h index bcceba61a0..5220e13b97 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h @@ -18,18 +18,21 @@ #include <stdlib.h> +extern void *rt_malloc(unsigned long nbytes); +extern void rt_free(void *ptr); + #ifdef __cplusplus extern "C" { #endif static inline void *metal_allocate_memory(unsigned int size) { - return (malloc(size)); + return (rt_malloc(size)); } static inline void metal_free_memory(void *ptr) { - free(ptr); + rt_free(ptr); } #ifdef __cplusplus diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h index bcceba61a0..5220e13b97 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h @@ -18,18 +18,21 @@ #include <stdlib.h> +extern void *rt_malloc(unsigned long nbytes); +extern void rt_free(void *ptr); + #ifdef __cplusplus extern "C" { #endif static inline void *metal_allocate_memory(unsigned int size) { - return (malloc(size)); + return (rt_malloc(size)); } static inline void metal_free_memory(void *ptr) { - free(ptr); + rt_free(ptr); } #ifdef __cplusplus diff --git a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c index f6e244c12c..b4a71ebc08 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c @@ -17,17 +17,14 @@ int main(void) { - int count = 1; /* set LED0 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED1_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/board.c b/bsp/stm32/stm32wb55-st-nucleo/board/board.c index 13796c442c..11c7c8cf2b 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/board.c +++ b/bsp/stm32/stm32wb55-st-nucleo/board/board.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version + * 2021-03-27 xph open rtc clk to support ble stack */ #include "board.h" @@ -26,9 +27,7 @@ void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1 - |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE - |RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -50,9 +49,7 @@ void SystemClock_Config(void) } /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2 - |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -64,22 +61,12 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clocks - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RTC - |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_LPUART1 - |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC; - PeriphClkInitStruct.PLLSAI1.PLLN = 24; - PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2; - PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK|RCC_PLLSAI1_ADCCLK; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1; PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; - PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { diff --git a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c index 57385ad74c..9d38020849 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c @@ -19,17 +19,14 @@ int main(void) { - int count = 1; /* set LED_BLUE pin mode to output */ rt_pin_mode(LED_BLUE_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED_BLUE_PIN, PIN_HIGH); rt_thread_mdelay(500); rt_pin_write(LED_BLUE_PIN, PIN_LOW); rt_thread_mdelay(500); } - - return RT_EOK; } diff --git a/bsp/stm32f20x/.config b/bsp/stm32f20x/.config index a568b7e0ae..5f3bc12590 100644 --- a/bsp/stm32f20x/.config +++ b/bsp/stm32f20x/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -20,18 +21,7 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +# CONFIG_RT_DEBUG is not set # # Inter-Thread communication @@ -51,6 +41,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -63,8 +54,9 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -73,6 +65,7 @@ CONFIG_ARCH_ARM_CORTEX_M3=y # RT-Thread Components # # CONFIG_RT_USING_COMPONENTS_INIT is not set +# CONFIG_RT_USING_USER_MAIN is not set # # C++ features @@ -101,51 +94,34 @@ CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=4 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -CONFIG_RT_DFS_ELM_USE_LFN_0=y +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set # CONFIG_RT_DFS_ELM_USE_LFN_1 is not set # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set # CONFIG_RT_DFS_ELM_USE_LFN_3 is not set -CONFIG_RT_DFS_ELM_USE_LFN=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=1 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set # CONFIG_RT_USING_SERIAL is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set @@ -155,10 +131,10 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -170,13 +146,9 @@ CONFIG_RT_USING_RTC=y # # POSIX layer and C standard library # -CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_USING_POSIX=y -# CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -188,14 +160,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -210,16 +182,9 @@ CONFIG_RT_USING_POSIX=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set - -# -# ARM CMSIS -# -# CONFIG_RT_USING_CMSIS_OS is not set -# CONFIG_RT_USING_RTT_CMSIS is not set # CONFIG_RT_USING_LWP is not set # @@ -229,14 +194,20 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -258,7 +229,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # @@ -268,9 +242,34 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set # # security packages @@ -278,6 +277,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -292,6 +293,11 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -303,7 +309,31 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -314,12 +344,40 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set # # peripheral libraries and drivers @@ -327,17 +385,61 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set # # miscellaneous packages @@ -347,12 +449,17 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -363,7 +470,29 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set CONFIG_SOC_STM32F2=y CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART6 is not set +CONFIG_SOC_STM32F20X=y diff --git a/bsp/stm32f20x/Drivers/24LCxx.c b/bsp/stm32f20x/Drivers/24LCxx.c index 1903a85b82..1fdbc9b8d1 100644 --- a/bsp/stm32f20x/Drivers/24LCxx.c +++ b/bsp/stm32f20x/Drivers/24LCxx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,171 +16,171 @@ #define EE24LC024H /* - Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes + Note: If eeprom size lager then EE_MEM_SIZE byte, you must define EE_ADDR_SIZE == I2C_MEM_2Bytes */ #ifdef EE24LC024H #define EE_ADDR_SIZE I2C_MEM_1Byte -#define EE_MEM_SIZE 256 -#define EE_PageSize 16 +#define EE_MEM_SIZE 256 +#define EE_PageSize 16 #endif static struct rt_device ee_dev; uint32_t EE_ReadBuffer(void *pBuffer, rt_off_t ReadAddr, rt_size_t NumByteToRead) { - return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte ); + return I2C_IORW(I2C1, (uint8_t *)pBuffer, (uint16_t)NumByteToRead, (uint16_t)ReadAddr, EE_Address | 0x01, I2C_MEM_1Byte ); } uint32_t EE_WritePage(void *pBuffer, uint16_t WriteAddr) -{ - I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE ); +{ + I2C_IORW(I2C1, (uint8_t *)pBuffer, EE_PageSize , WriteAddr, EE_Address , EE_ADDR_SIZE ); - /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) - rt_kprintf("EE ACK failed\n");*/ - rt_thread_delay(50); + /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) + rt_kprintf("EE ACK failed\n");*/ + rt_thread_delay(50); - return 0; + return 0; } uint32_t EE_WriteByte(void *pBuffer, uint16_t WriteAddr) { - I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE ); + I2C_IORW(I2C1, (uint8_t *)pBuffer, 1 , WriteAddr, EE_Address, EE_ADDR_SIZE ); - /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) - rt_kprintf("EE ACK failed\n");*/ - rt_thread_delay(50); + /*if( I2C_AcknowledgePolling(I2C1 , EE_Address) == Error ) + rt_kprintf("EE ACK failed\n");*/ + rt_thread_delay(50); - return 0; + return 0; } Status EE_WriteBuffer(const void *pBuffer, rt_off_t WriteAddr, rt_size_t NumByteToWrite) { - uint8_t NumOfPage = 0, NumOfSingle = 0; - uint16_t Addr = 0,count = 0; - uint8_t *ptr = (uint8_t *)pBuffer; - - Addr = (uint16_t)(WriteAddr&0xFFFF); + uint8_t NumOfPage = 0, NumOfSingle = 0; + uint16_t Addr = 0,count = 0; + uint8_t *ptr = (uint8_t *)pBuffer; + + Addr = (uint16_t)(WriteAddr&0xFFFF); + + count = (uint16_t)(NumByteToWrite&0xFFFF); + + if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE) + return Error; + + while (count >= EE_PageSize) + { + EE_WritePage(ptr, Addr); + Addr += EE_PageSize; + count -= EE_PageSize; + ptr += EE_PageSize; + } - count = (uint16_t)(NumByteToWrite&0xFFFF); - - if ((WriteAddr + NumByteToWrite) > EE_MEM_SIZE) - return Error; + while (count) + { + EE_WriteByte(ptr++, Addr++); + count--; + } - while (count >= EE_PageSize) - { - EE_WritePage(ptr, Addr); - Addr += EE_PageSize; - count -= EE_PageSize; - ptr += EE_PageSize; - } - - while (count) - { - EE_WriteByte(ptr++, Addr++); - count--; - } - - return Success; + return Success; } static rt_err_t ee24LCxx_init(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t ee24LCxx_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) { - if (EE_ReadBuffer(buf, pos, size) == Success) - return size; - else - return -1; + if (EE_ReadBuffer(buf, pos, size) == Success) + return size; + else + return -1; } static rt_size_t ee24LCxx_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size) { - if (EE_WriteBuffer(buf, pos, size) == Success) - return size; - else - return -1; + if (EE_WriteBuffer(buf, pos, size) == Success) + return size; + else + return -1; } static rt_err_t ee24LCxx_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t ee24LCxx_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t ee24LCxx_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } void ee24LCxx_hw_init(void) { - uint32_t delay, i; - I2C1_INIT(); + uint32_t delay, i; + I2C1_INIT(); - for (i =0; i < 4; i++) - { - delay = 0xFFFFF; - while (delay--); - } + for (i =0; i < 4; i++) + { + delay = 0xFFFFF; + while (delay--); + } - ee_dev.init = ee24LCxx_init; - ee_dev.open = ee24LCxx_open; - ee_dev.close = ee24LCxx_close; - ee_dev.read = ee24LCxx_read; - ee_dev.write = ee24LCxx_write; - ee_dev.control = ee24LCxx_control; - ee_dev.type = RT_Device_Class_Unknown; + ee_dev.init = ee24LCxx_init; + ee_dev.open = ee24LCxx_open; + ee_dev.close = ee24LCxx_close; + ee_dev.read = ee24LCxx_read; + ee_dev.write = ee24LCxx_write; + ee_dev.control = ee24LCxx_control; + ee_dev.type = RT_Device_Class_Unknown; - rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR); + rt_device_register(&ee_dev, "eeprom", RT_DEVICE_FLAG_RDWR); } void dump_ee(void) { - rt_device_t dev; - char buf[EE_MEM_SIZE]; - int i, j; + rt_device_t dev; + char buf[EE_MEM_SIZE]; + int i, j; - dev = rt_device_find("eeprom"); - rt_device_read(dev, 0, buf, EE_MEM_SIZE ); + dev = rt_device_find("eeprom"); + rt_device_read(dev, 0, buf, EE_MEM_SIZE ); - for (i = 0; i < 16; i++) - { - for (j = 0; j < 16; j++) - { - rt_kprintf("0x%02X ", buf[ i*16+ j]); - } - rt_kprintf("\n"); - } + for (i = 0; i < 16; i++) + { + for (j = 0; j < 16; j++) + { + rt_kprintf("0x%02X ", buf[ i*16+ j]); + } + rt_kprintf("\n"); + } } void ee_reset(void) { - char buf[EE_MEM_SIZE], read[EE_MEM_SIZE]; - int i; - rt_device_t dev = rt_device_find("eeprom"); + char buf[EE_MEM_SIZE], read[EE_MEM_SIZE]; + int i; + rt_device_t dev = rt_device_find("eeprom"); - for (i = 0; i < EE_MEM_SIZE; i++) - { - buf[i] = 0xFF; - read[i] = 0; - } - if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE) - rt_kprintf("Write Success\n"); + for (i = 0; i < EE_MEM_SIZE; i++) + { + buf[i] = 0xFF; + read[i] = 0; + } + if (rt_device_write(dev, 0, buf, EE_MEM_SIZE ) == EE_MEM_SIZE) + rt_kprintf("Write Success\n"); - rt_device_read(dev, 0, read, EE_MEM_SIZE ); + rt_device_read(dev, 0, read, EE_MEM_SIZE ); - for (i = 0; i < EE_MEM_SIZE; i++) - { - if (buf[i] != read[i]) - rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i); - } + for (i = 0; i < EE_MEM_SIZE; i++) + { + if (buf[i] != read[i]) + rt_kprintf("EE Failed %X != %X at %d\n", buf[i], read[i], i); + } } #ifdef RT_USING_FINSH diff --git a/bsp/stm32f20x/Drivers/FM25Lx.c b/bsp/stm32f20x/Drivers/FM25Lx.c index b1437d7707..e59af25fd4 100644 --- a/bsp/stm32f20x/Drivers/FM25Lx.c +++ b/bsp/stm32f20x/Drivers/FM25Lx.c @@ -26,7 +26,7 @@ void rt_hw_spi2_baud_rate(uint16_t SPI_BaudRatePrescaler) /* FM25L256 using SPI2 */ void fm25_spi_cfg() { - GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; SPI_InitTypeDef SPI_InitStructure; /* Enable SPI Periph clock */ @@ -36,24 +36,24 @@ void fm25_spi_cfg() //Setup GPIO GPIO_InitStructure.GPIO_Pin = FM25_SPI_SCK | FM25_SPI_MISO | FM25_SPI_MOSI; - /*Connect Pin to AF*/ - GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3); - GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3); - GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3); + /*Connect Pin to AF*/ + GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource3, GPIO_AF_SPI3); + GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource4, GPIO_AF_SPI3); + GPIO_PinAFConfig(FM25_SPI_GPIO, GPIO_PinSource5, GPIO_AF_SPI3); - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(FM25_SPI_GPIO, &GPIO_InitStructure); - /* CS pin: PB12 */ + /* CS pin: PB12 */ GPIO_InitStructure.GPIO_Pin = FM25_SPI_NSS_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_Init(FM25_SPI_NSS_GPIO, &GPIO_InitStructure); - CS_HIGH(); + CS_HIGH(); - SPI_Cmd(FM25_SPI, DISABLE); + SPI_Cmd(FM25_SPI, DISABLE); /*------------------------ SPI configuration ------------------------*/ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx; SPI_InitStructure.SPI_Mode = SPI_Mode_Master; @@ -72,23 +72,23 @@ void fm25_spi_cfg() SPI_Cmd(FM25_SPI, ENABLE); //SPI_CalculateCRC(FM25_SPI, DISABLE); - fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO); + fram_lock = rt_sem_create("framlock", 1, RT_IPC_FLAG_FIFO); } static uint8_t spi_readwrite(uint8_t data) { int32_t timeout = 0xFFFFF; - //rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE)); - //Wait until the transmit buffer is empty + //rt_kprintf("State 0x%X\n", SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE)); + //Wait until the transmit buffer is empty while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_TXE) == RESET && --timeout >0); - if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} + if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} // Send the byte SPI_I2S_SendData(FM25_SPI, data); - timeout = 0xFFFFF; + timeout = 0xFFFFF; //Wait until a data is received while (SPI_I2S_GetFlagStatus(FM25_SPI, SPI_I2S_FLAG_RXNE) == RESET && --timeout >0); - if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} + if( timeout <= 0 ){ spi_timeout_cnt++; return 0;} // Get the received data data = SPI_I2S_ReceiveData(FM25_SPI); @@ -110,29 +110,29 @@ rt_size_t fm25_read(rt_device_t dev, rt_off_t offset, void * buf, rt_size_t size { uint32_t index; - uint8_t *buffer = (uint8_t*) buf; + uint8_t *buffer = (uint8_t*) buf; fram_lock(); //spi_config(); - //rt_kprintf("READ: %d, size=%d\n", offset, size); + //rt_kprintf("READ: %d, size=%d\n", offset, size); CS_LOW(); - spi_readwrite( FM25_READ); - spi_readwrite( (offset >> 8)&0xFF ); - spi_readwrite( offset & 0xFF ); + spi_readwrite( FM25_READ); + spi_readwrite( (offset >> 8)&0xFF ); + spi_readwrite( offset & 0xFF ); for(index=0; index<size; index++) { - *buffer++ = spi_readwrite(0xFF); + *buffer++ = spi_readwrite(0xFF); - if( spi_timeout_cnt > 0 ) - { - fram_unlock(); - spi_timeout_cnt = 0; - rt_kprintf("Read time out\n"); - return -1; - } + if( spi_timeout_cnt > 0 ) + { + fram_unlock(); + spi_timeout_cnt = 0; + rt_kprintf("Read time out\n"); + return -1; + } - offset++; + offset++; } CS_HIGH(); @@ -145,33 +145,33 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size { uint32_t index = size; - uint8_t *buffer = (uint8_t*) buf; + uint8_t *buffer = (uint8_t*) buf; fram_lock(); //spi_config(); - //rt_kprintf("WRITE: %d, size=%d\n", offset, size); - CS_LOW(); + //rt_kprintf("WRITE: %d, size=%d\n", offset, size); + CS_LOW(); spi_readwrite( FM25_WREN ); - CS_HIGH(); - CS_LOW(); + CS_HIGH(); + CS_LOW(); spi_readwrite( FM25_WRITE); - spi_readwrite( (offset >> 8)&0xFF ); - spi_readwrite( offset & 0xFF ); - while( index > 0 ) - { - spi_readwrite( *buffer++ ); + spi_readwrite( (offset >> 8)&0xFF ); + spi_readwrite( offset & 0xFF ); + while( index > 0 ) + { + spi_readwrite( *buffer++ ); - if( spi_timeout_cnt > 0 ) - { - fram_unlock(); - rt_kprintf("Write time out\n"); - spi_timeout_cnt = 0; - return -1; - } - index--; - offset++; - } + if( spi_timeout_cnt > 0 ) + { + fram_unlock(); + rt_kprintf("Write time out\n"); + spi_timeout_cnt = 0; + return -1; + } + index--; + offset++; + } CS_HIGH(); - //rt_thread_delay(100); + //rt_thread_delay(100); fram_unlock(); @@ -179,36 +179,36 @@ rt_size_t fm25_write(rt_device_t dev, rt_off_t offset, const void * buf, rt_size } static rt_err_t fm25_init(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t fm25_open(rt_device_t dev, rt_uint16_t oflag) { - char i; - SPI_Cmd(FM25_SPI, ENABLE); + char i; + SPI_Cmd(FM25_SPI, ENABLE); - if( oflag != RT_DEVICE_FLAG_RDONLY ) - { - CS_LOW(); - spi_readwrite( FM25_WRSR ); - spi_readwrite( FM25_WPEN ); - CS_HIGH(); - //rt_kprintf("RDSR=0x%X\n", fm25_read_status()); + if( oflag != RT_DEVICE_FLAG_RDONLY ) + { + CS_LOW(); + spi_readwrite( FM25_WRSR ); + spi_readwrite( FM25_WPEN ); + CS_HIGH(); + //rt_kprintf("RDSR=0x%X\n", fm25_read_status()); - } - return RT_EOK; + } + return RT_EOK; } static rt_err_t fm25_close(rt_device_t dev) { - CS_LOW(); + CS_LOW(); spi_readwrite( FM25_WRDI ); CS_HIGH(); - SPI_Cmd(FM25_SPI, DISABLE); + SPI_Cmd(FM25_SPI, DISABLE); - return RT_EOK; + return RT_EOK; } static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) { @@ -219,30 +219,30 @@ static rt_err_t fm25_control(rt_device_t dev, int cmd, void *args) geometry->bytes_per_sector = 1; geometry->block_size = 1; - geometry->sector_count = 8192; - + geometry->sector_count = 8192; + } - return RT_EOK; + return RT_EOK; } -static struct rt_device spi_flash_device; +static struct rt_device spi_flash_device; void fm25_hw_init() { - int i = 0xFFFFF; - fm25_spi_cfg(); + int i = 0xFFFFF; + fm25_spi_cfg(); - while(i--); - //spi_config(); - CS_LOW(); + while(i--); + //spi_config(); + CS_LOW(); spi_readwrite( FM25_WRDI ); CS_HIGH(); - spi_flash_device.type = RT_Device_Class_Block; + spi_flash_device.type = RT_Device_Class_Block; spi_flash_device.init = fm25_init; spi_flash_device.open = fm25_open; spi_flash_device.close = fm25_close; - spi_flash_device.read = fm25_read; + spi_flash_device.read = fm25_read; spi_flash_device.write = fm25_write; spi_flash_device.control = fm25_control; /* no private */ @@ -255,17 +255,17 @@ void fm25_hw_init() int fram_test(int x) { - //rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2); - rt_device_t device = RT_NULL; - char buf[256]; - char read[256]; - int i, j; + //rt_kprintf("SR=0x%X\nCR1=0x%X\nCR2=0x%X\n", FM25_SPI->SR, FM25_SPI->CR1,FM25_SPI->CR2); + rt_device_t device = RT_NULL; + char buf[256]; + char read[256]; + int i, j; - for(i =0; i< 256; i++ ) - { - buf[i] = i; - read[i] = 0; - } + for(i =0; i< 256; i++ ) + { + buf[i] = i; + read[i] = 0; + } // step 1:find device device = rt_device_find("fram0"); if( device == RT_NULL) @@ -273,22 +273,22 @@ int fram_test(int x) rt_kprintf("device %s: not found!\r\n"); return RT_ERROR; } - device->open(device,RT_DEVICE_FLAG_RDWR); + device->open(device,RT_DEVICE_FLAG_RDWR); - for( j = 0; j < FM25_MAXSIZE; j+= 256 ) - //j = 256*x; - { - //rt_kprintf("RDSR=0x%X\n", fm25_read_status()); - device->write(device,j, buf,256); - device->read(device,j, read,256); - for(i =0; i< 256; i++ ) - { - if( buf[i] != read[i] ) - rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]); - } - } - device->close(device); - rt_kprintf("Finsh test\n"); + for( j = 0; j < FM25_MAXSIZE; j+= 256 ) + //j = 256*x; + { + //rt_kprintf("RDSR=0x%X\n", fm25_read_status()); + device->write(device,j, buf,256); + device->read(device,j, read,256); + for(i =0; i< 256; i++ ) + { + if( buf[i] != read[i] ) + rt_kprintf("error at %d: %d!=%d\n", i, buf[i], read[i]); + } + } + device->close(device); + rt_kprintf("Finsh test\n"); } #ifdef RT_USING_FINSH #include <finsh.h> diff --git a/bsp/stm32f20x/Drivers/FM25Lx.h b/bsp/stm32f20x/Drivers/FM25Lx.h index 3f714ac8da..6d7e9ec08a 100644 --- a/bsp/stm32f20x/Drivers/FM25Lx.h +++ b/bsp/stm32f20x/Drivers/FM25Lx.h @@ -1,14 +1,14 @@ #ifndef FM25LX_H #define FM25LX_H -#define FM25_WREN 0x06 -#define FM25_WRDI 0x04 -#define FM25_RDSR 0x05 -#define FM25_WRSR 0x01 -#define FM25_READ 0x03 -#define FM25_WRITE 0x02 -#define FM25_WEL 0x02 -#define FM25_WPEN 0x80 +#define FM25_WREN 0x06 +#define FM25_WRDI 0x04 +#define FM25_RDSR 0x05 +#define FM25_WRSR 0x01 +#define FM25_READ 0x03 +#define FM25_WRITE 0x02 +#define FM25_WEL 0x02 +#define FM25_WPEN 0x80 #define FM25CL64B //#define FM25LC256 @@ -19,25 +19,25 @@ #define FM25_MAXSIZE 32768 #endif -#define FM25_SPI SPI3 -#define FM25_SPI_GPIO GPIOB -#define FM25_SPI_MOSI GPIO_Pin_5 -#define FM25_SPI_MISO GPIO_Pin_4 -#define FM25_SPI_SCK GPIO_Pin_3 -#define FM25_SPI_NSS_GPIO GPIOD -#define FM25_SPI_NSS_PIN GPIO_Pin_10 -#define FM25_SPI_CLK RCC_APB1Periph_SPI3 -#define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB -#define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD +#define FM25_SPI SPI3 +#define FM25_SPI_GPIO GPIOB +#define FM25_SPI_MOSI GPIO_Pin_5 +#define FM25_SPI_MISO GPIO_Pin_4 +#define FM25_SPI_SCK GPIO_Pin_3 +#define FM25_SPI_NSS_GPIO GPIOD +#define FM25_SPI_NSS_PIN GPIO_Pin_10 +#define FM25_SPI_CLK RCC_APB1Periph_SPI3 +#define FM25_SPI_GPIO_CLK RCC_AHB1Periph_GPIOB +#define FM25_SPI_NSS_GPIO_CLK RCC_AHB1Periph_GPIOD -#define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1 -#define FM25_SPI_DMA_Channel DMA_Channel_0 -#define FM25_SPI_RX_DMA_Stream DMA1_Stream0 -#define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn +#define FM25_SPI_DMA_CLK RCC_AHB1Periph_DMA1 +#define FM25_SPI_DMA_Channel DMA_Channel_0 +#define FM25_SPI_RX_DMA_Stream DMA1_Stream0 +#define FM25_SPI_RX_DMA_IRQ DMA1_Stream0_IRQn #define FM25_SPI_RX_DMA_FLAG DMA_IT_TCIF0 -#define FM25_SPI_TX_DMA_Stream DMA1_Stream5 -#define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn +#define FM25_SPI_TX_DMA_Stream DMA1_Stream5 +#define FM25_SPI_TX_DMA_IRQ DMA1_Stream5_IRQn #define FM25_SPI_TX_DMA_FLAG DMA_IT_TCIF5 -#define FM25_SPI_DR_Base 0x4003C00C +#define FM25_SPI_DR_Base 0x4003C00C -#endif
\ No newline at end of file +#endif diff --git a/bsp/stm32f20x/Drivers/board.c b/bsp/stm32f20x/Drivers/board.c index e3cfdbbc12..0b2d214540 100644 --- a/bsp/stm32f20x/Drivers/board.c +++ b/bsp/stm32f20x/Drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,16 +30,16 @@ void SD_LowLevel_DeInit(void) { GPIO_InitTypeDef GPIO_InitStructure; - + /*!< Disable SDIO Clock */ SDIO_ClockCmd(DISABLE); - + /*!< Set Power State to OFF */ SDIO_SetPowerState(SDIO_PowerState_OFF); /*!< DeInitializes the SDIO peripheral */ SDIO_DeInit(); - + /* Disable the SDIO APB2 Clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); @@ -66,7 +66,7 @@ void SD_LowLevel_DeInit(void) } /** - * @brief Initializes the SD Card and put it into StandBy State (Ready for + * @brief Initializes the SD Card and put it into StandBy State (Ready for * data transfer). * @param None * @retval None @@ -101,7 +101,7 @@ void SD_LowLevel_Init(void) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOC, &GPIO_InitStructure); - + /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; @@ -154,7 +154,7 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) /* DMA2 Stream3 or Stream6 enable */ DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); - + } /** @@ -219,11 +219,11 @@ uint32_t SD_DMAEndOfTransferStatus(void) void NVIC_Configuration(void) { #ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x20000000 */ - NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); + /* Set the Vector Table base location at 0x20000000 */ + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); #else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); + /* Set the Vector Table base location at 0x08000000 */ + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); #endif } @@ -236,15 +236,15 @@ void NVIC_Configuration(void) *******************************************************************************/ void SysTick_Configuration(void) { - RCC_ClocksTypeDef rcc_clocks; - rt_uint32_t cnts; + RCC_ClocksTypeDef rcc_clocks; + rt_uint32_t cnts; - RCC_GetClocksFreq(&rcc_clocks); + RCC_GetClocksFreq(&rcc_clocks); - cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND; + cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND; - SysTick_Config(cnts); - SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); } /** @@ -253,13 +253,13 @@ void SysTick_Configuration(void) */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** @@ -267,15 +267,15 @@ void SysTick_Handler(void) */ void rt_hw_board_init() { - /* NVIC Configuration */ - NVIC_Configuration(); + /* NVIC Configuration */ + NVIC_Configuration(); - /* Configure the SysTick */ - SysTick_Configuration(); + /* Configure the SysTick */ + SysTick_Configuration(); - rt_hw_usart_init(); + rt_hw_usart_init(); #ifdef RT_USING_CONSOLE - rt_console_set_device(CONSOLE_DEVICE); + rt_console_set_device(CONSOLE_DEVICE); #endif } diff --git a/bsp/stm32f20x/Drivers/board.h b/bsp/stm32f20x/Drivers/board.h index 63a97b6b1c..9b58dd81c7 100644 --- a/bsp/stm32f20x/Drivers/board.h +++ b/bsp/stm32f20x/Drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,32 +16,32 @@ /* board configuration */ // <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card -// <i>Default: 1 -#define STM32_USE_SDIO 1 +// <i>Default: 1 +#define STM32_USE_SDIO 1 /* whether use board external SRAM memory */ // <e>Use external SRAM memory on the board -// <i>Enable External SRAM memory +// <i>Enable External SRAM memory #define STM32_EXT_SRAM 0 -// <o>Begin Address of External SRAM -// <i>Default: 0x68000000 +// <o>Begin Address of External SRAM +// <i>Default: 0x68000000 #define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */ -// <o>End Address of External SRAM -// <i>Default: 0x68080000 +// <o>End Address of External SRAM +// <i>Default: 0x68080000 #define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */ // </e> // <o> Internal SRAM memory size[Kbytes] <8-128> -// <i>Default: 64 +// <i>Default: 64 #define STM32_SRAM_SIZE 128 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) // <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3 -// <i>Default: 1 -#define STM32_CONSOLE_USART 1 +// <i>Default: 1 +#define STM32_CONSOLE_USART 1 // <o> Ethernet Interface: <0=> Microchip ENC28J60 -#define STM32_ETH_IF 0 +#define STM32_ETH_IF 0 void rt_hw_board_led_on(int n); void rt_hw_board_led_off(int n); @@ -64,21 +64,21 @@ void rt_hw_board_init(void); #define SD_DETECT_PIN GPIO_Pin_0 /* PB.0 */ #define SD_DETECT_GPIO_PORT GPIOB /* GPIOB */ #define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOB - + #define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) -/** +/** * @brief SDIO Intialization Frequency (400KHz max) */ #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) -/** - * @brief SDIO Data Transfer Frequency (25MHz max) +/** + * @brief SDIO Data Transfer Frequency (25MHz max) */ -#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) +#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) #define SD_SDIO_DMA DMA2 #define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2 - -#define SD_SDIO_DMA_STREAM3 3 + +#define SD_SDIO_DMA_STREAM3 3 //#define SD_SDIO_DMA_STREAM6 6 #ifdef SD_SDIO_DMA_STREAM3 @@ -88,7 +88,7 @@ void rt_hw_board_init(void); #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3 #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3 - #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 + #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 #elif defined SD_SDIO_DMA_STREAM6 #define SD_SDIO_DMA_STREAM DMA2_Stream6 #define SD_SDIO_DMA_CHANNEL DMA_Channel_4 @@ -96,11 +96,11 @@ void rt_hw_board_init(void); #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6 #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6 #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6 - #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6 + #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6 #endif /* SD_SDIO_DMA_STREAM3 */ void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); +void SD_LowLevel_Init(void); void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize); void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize); diff --git a/bsp/stm32f20x/Drivers/drv_rtc.c b/bsp/stm32f20x/Drivers/drv_rtc.c index 6078a15249..4e5093ee53 100644 --- a/bsp/stm32f20x/Drivers/drv_rtc.c +++ b/bsp/stm32f20x/Drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -43,20 +43,20 @@ static struct rt_device rtc; static time_t rt_mktime(struct tm *tm) { - long res; - int year; - year = tm->tm_year - 70; + long res; + int year; + year = tm->tm_year - 70; - res = YEAR * year + DAY * ((year + 1) / 4); - res += month[tm->tm_mon]; + res = YEAR * year + DAY * ((year + 1) / 4); + res += month[tm->tm_mon]; - if (tm->tm_mon > 1 && ((year + 2) % 4)) - res -= DAY; - res += DAY * (tm->tm_mday - 1); - res += HOUR * tm->tm_hour; - res += MINUTE * tm->tm_min; - res += tm->tm_sec; - return res; + if (tm->tm_mon > 1 && ((year + 2) % 4)) + res -= DAY; + res += DAY * (tm->tm_mday - 1); + res += HOUR * tm->tm_hour; + res += MINUTE * tm->tm_min; + res += tm->tm_sec; + return res; } static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) { @@ -76,7 +76,7 @@ static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_siz static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) { time_t *time; - struct tm ti,*to; + struct tm ti,*to; RT_ASSERT(dev != RT_NULL); switch (cmd) @@ -84,17 +84,17 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_GET_TIME: time = (time_t *)args; /* read device */ - //RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure); - RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); - RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure); - ti.tm_sec = RTC_TimeStructure.RTC_Seconds; - ti.tm_min = RTC_TimeStructure.RTC_Minutes; - ti.tm_hour = RTC_TimeStructure.RTC_Hours; - //ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay; - ti.tm_mon = RTC_DateStructure.RTC_Month -1; - ti.tm_mday = RTC_DateStructure.RTC_Date; - ti.tm_year = RTC_DateStructure.RTC_Year + 70; - *time = rt_mktime(&ti); + //RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStructure, &RTC_DateStructure); + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); + RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure); + ti.tm_sec = RTC_TimeStructure.RTC_Seconds; + ti.tm_min = RTC_TimeStructure.RTC_Minutes; + ti.tm_hour = RTC_TimeStructure.RTC_Hours; + //ti.tm_wday = (RTC_DateStructure.RTC_WeekDay==7)?0:RTC_DateStructure.RTC_WeekDay; + ti.tm_mon = RTC_DateStructure.RTC_Month -1; + ti.tm_mday = RTC_DateStructure.RTC_Date; + ti.tm_year = RTC_DateStructure.RTC_Year + 70; + *time = rt_mktime(&ti); //*time = RTC_GetCounter(); break; @@ -104,10 +104,10 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) time = (time_t *)args; /* Enable the PWR clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - /* Allow access to RTC */ - PWR_BackupAccessCmd(ENABLE); + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); /* Wait until last write operation on RTC registers has finished */ //RTC_WaitForLastTask(); @@ -115,22 +115,22 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) /* Change the current time */ //RTC_SetCounter(*time); - to = gmtime(time); - RTC_TimeStructure.RTC_Seconds = to->tm_sec; - RTC_TimeStructure.RTC_Minutes = to->tm_min; - RTC_TimeStructure.RTC_Hours = to->tm_hour; - //RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday; - RTC_DateStructure.RTC_Month = to->tm_mon + 1; - RTC_DateStructure.RTC_Date = to->tm_mday; - RTC_DateStructure.RTC_Year = to->tm_year - 70; - RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure); - RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure); + to = gmtime(time); + RTC_TimeStructure.RTC_Seconds = to->tm_sec; + RTC_TimeStructure.RTC_Minutes = to->tm_min; + RTC_TimeStructure.RTC_Hours = to->tm_hour; + //RTC_DateStructure.RTC_WeekDay =(ti->tm_wday==0)?7:ti->tm_wday; + RTC_DateStructure.RTC_Month = to->tm_mon + 1; + RTC_DateStructure.RTC_Date = to->tm_mday; + RTC_DateStructure.RTC_Year = to->tm_year - 70; + RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure); + RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure); /* Wait until last write operation on RTC registers has finished */ //RTC_WaitForLastTask(); RTC_WriteBackupRegister(RTC_BKP_DR1, 0xA5A5); - //BKP_WriteBackupRegister(BKP_DR1, 0xA5A5); + //BKP_WriteBackupRegister(BKP_DR1, 0xA5A5); } break; } @@ -147,75 +147,75 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) *******************************************************************************/ int RTC_Config(void) { - u32 count=0x200000; - /* Enable the PWR clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + u32 count=0x200000; + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - /* Allow access to RTC */ - PWR_BackupAccessCmd(ENABLE); + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); - RCC_LSEConfig(RCC_LSE_ON); + RCC_LSEConfig(RCC_LSE_ON); - /* Wait till LSE is ready */ - while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) ); + /* Wait till LSE is ready */ + while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) ); if ( count == 0 ) { return -1; } - /* Select the RTC Clock Source */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - SynchPrediv = 0xFF; - AsynchPrediv = 0x7F; + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; - /* Enable the RTC Clock */ - RCC_RTCCLKCmd(ENABLE); + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); - /* Wait for RTC APB registers synchronisation */ - RTC_WaitForSynchro(); + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); - /* Enable The TimeStamp */ - //RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE); + /* Enable The TimeStamp */ + //RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE); - return 0; + return 0; } int RTC_Configuration(void) { - if(RTC_Config() < 0 ) - return -1; + if(RTC_Config() < 0 ) + return -1; - /* Set the Time */ - RTC_TimeStructure.RTC_Hours = 0; - RTC_TimeStructure.RTC_Minutes = 0; - RTC_TimeStructure.RTC_Seconds = 0; + /* Set the Time */ + RTC_TimeStructure.RTC_Hours = 0; + RTC_TimeStructure.RTC_Minutes = 0; + RTC_TimeStructure.RTC_Seconds = 0; - /* Set the Date */ - RTC_DateStructure.RTC_Month = 1; - RTC_DateStructure.RTC_Date = 1; - RTC_DateStructure.RTC_Year = 0; - RTC_DateStructure.RTC_WeekDay = 4; + /* Set the Date */ + RTC_DateStructure.RTC_Month = 1; + RTC_DateStructure.RTC_Date = 1; + RTC_DateStructure.RTC_Year = 0; + RTC_DateStructure.RTC_WeekDay = 4; - /* Calendar Configuration */ - RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; - RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; - RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStructure); + /* Calendar Configuration */ + RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); - /* Set Current Time and Date */ - RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure); - RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure); - if (RTC_Init(&RTC_InitStructure) == ERROR) - return -1; + /* Set Current Time and Date */ + RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure); + RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure); + if (RTC_Init(&RTC_InitStructure) == ERROR) + return -1; return 0; } void rt_hw_rtc_init(void) { - rtc.type = RT_Device_Class_RTC; + rtc.type = RT_Device_Class_RTC; if (RTC_ReadBackupRegister(RTC_BKP_DR1) != 0xA5A5) { @@ -234,11 +234,11 @@ void rt_hw_rtc_init(void) } /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rt_rtc_open; - rtc.close = RT_NULL; - rtc.read = rt_rtc_read; - rtc.write = RT_NULL; + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; rtc.control = rt_rtc_control; /* no private */ diff --git a/bsp/stm32f20x/Drivers/drv_rtc.h b/bsp/stm32f20x/Drivers/drv_rtc.h index 8f6c9a00a0..0d0ad288fc 100644 --- a/bsp/stm32f20x/Drivers/drv_rtc.h +++ b/bsp/stm32f20x/Drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32f20x/Drivers/i2c.c b/bsp/stm32f20x/Drivers/i2c.c index e1b4b02ffa..9b2f4ed866 100644 --- a/bsp/stm32f20x/Drivers/i2c.c +++ b/bsp/stm32f20x/Drivers/i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,15 +14,15 @@ #include "stm32f2xx_i2c.h" #include "stm32f2xx_dma.h" -#define EV_SB 1 -#define EV_ADDR (1<<1) -#define EV_STOPF (1<<2) -#define EV_BTF (1<<3) -#define ERR_ARLO (1<<4) -#define ERR_AF (1<<5) -#define ERR_OVR (1<<6) -#define ERR_PECERR (1<<7) -#define ERR_BERR (1<<8) +#define EV_SB 1 +#define EV_ADDR (1<<1) +#define EV_STOPF (1<<2) +#define EV_BTF (1<<3) +#define ERR_ARLO (1<<4) +#define ERR_AF (1<<5) +#define ERR_OVR (1<<6) +#define ERR_PECERR (1<<7) +#define ERR_BERR (1<<8) #define I2C_COMPLETE (1<<9) #define I2C_BUSY 1 @@ -66,7 +66,7 @@ void dump_i2c_register(I2C_TypeDef* I2Cx) else I2C_TRACE("======I2C2======\n"); I2C_TRACE("CR1: 0x%x\tCR2: 0x%x\n", I2Cx->CR1, I2Cx->CR2); - I2C_TRACE("SR1: 0x%x\tSR2: 0x%x\n", I2Cx->SR1, I2Cx->SR2); + I2C_TRACE("SR1: 0x%x\tSR2: 0x%x\n", I2Cx->SR1, I2Cx->SR2); } @@ -75,532 +75,532 @@ Status I2C_AcknowledgePolling(I2C_TypeDef* I2Cx ,uint8_t Addr) { uint32_t timeout = 0xFFFF, ret; uint16_t tmp; - ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER ); - - if( ret == RT_EOK ) - { - do{ - if( timeout-- <= 0 ) - { - I2C_ClearFlag(I2Cx,I2C_FLAG_AF); - I2Cx->CR1 |= CR1_STOP_Set; - rt_mutex_release(i2c_mux); - return Error; - } - - I2Cx->CR1 |= CR1_START_Set; - tmp = I2Cx->SR1;//MSB - I2Cx->DR = Addr; - - }while((I2Cx->SR1&0x0002) != 0x0002); - - I2C_ClearFlag(I2Cx,I2C_FLAG_AF); - I2Cx->CR1 |= CR1_STOP_Set; - while ((I2Cx->CR1&0x200) == 0x200); - rt_kprintf( "AcknowledgePolling OK\n"); - rt_mutex_release(i2c_mux); - return Success; - } - else - return Error; -} + ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER ); -/* - Only 1 byte READ using Interrupt or Polling otherwise using DMA + if( ret == RT_EOK ) + { + do{ + if( timeout-- <= 0 ) + { + I2C_ClearFlag(I2Cx,I2C_FLAG_AF); + I2Cx->CR1 |= CR1_STOP_Set; + rt_mutex_release(i2c_mux); + return Error; + } + + I2Cx->CR1 |= CR1_START_Set; + tmp = I2Cx->SR1;//MSB + I2Cx->DR = Addr; + + }while((I2Cx->SR1&0x0002) != 0x0002); + + I2C_ClearFlag(I2Cx,I2C_FLAG_AF); + I2Cx->CR1 |= CR1_STOP_Set; + while ((I2Cx->CR1&0x200) == 0x200); + rt_kprintf( "AcknowledgePolling OK\n"); + rt_mutex_release(i2c_mux); + return Success; + } + else + return Error; +} + +/* + Only 1 byte READ using Interrupt or Polling otherwise using DMA */ void I2C1_EV_IRQHandler() { - __IO uint16_t regSR1, regSR2; - __IO uint32_t regSR; - int i=10; + __IO uint16_t regSR1, regSR2; + __IO uint32_t regSR; + int i=10; - rt_interrupt_enter(); - //rt_hw_led_on(10); - regSR1 = I2C1->SR1; - regSR2 = I2C1->SR2; - regSR = (regSR2 << 16) | regSR1; - //rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus); - - if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5 - { + rt_interrupt_enter(); + //rt_hw_led_on(10); + regSR1 = I2C1->SR1; + regSR2 = I2C1->SR2; + regSR = (regSR2 << 16) | regSR1; + //rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus); - if( i2cStatus == S1 ) //Send TX Command - { - I2C1->DR = DevAddr & 0xFE; - i2cStatus = S2; - } - else if( i2cStatus == S4 ) //Send RX Command - { - I2C1->DR = DevAddr | 0x01; - i2cStatus = S5; - } + if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5 + { + if( i2cStatus == S1 ) //Send TX Command + { + I2C1->DR = DevAddr & 0xFE; + i2cStatus = S2; + } + else if( i2cStatus == S4 ) //Send RX Command + { + I2C1->DR = DevAddr | 0x01; + i2cStatus = S5; + } - regSR1 = 0; - regSR2 = 0; - } - if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6 - { - switch( i2cStatus ) - { - case S2: //Send 1st memory address phase - { - //I2C_DMACmd(I2C1, ENABLE); - I2C1->DR = MemAddr[0]; - if( memtype == I2C_MEM_1Byte ) - i2cStatus = S2_2; - else if( memtype == I2C_MEM_2Bytes ) - i2cStatus = S2_1; - } - break; - case S5: //Set RX buffer phase - { - if( i2cFlag == I2C_READ_DMA ) - { - I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX); - I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set; - DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE); - } - else if( i2cFlag == I2C_READ_INTERRUPT ) - { - I2C1->CR2 |= I2C_IT_BUF; - I2C1->CR1 &= CR1_ACK_Reset; - /* Program the STOP */ - I2C1->CR1 |= CR1_STOP_Set; - } - i2cStatus = S6; - } - break; - } - - regSR1 = 0; - regSR2 = 0; - //dump_i2c_register(I2C1); - } - if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7 - { - //Interrupt RX complete phase - if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT ) - { - *i2c_buf = I2C1->DR; - i2cStatus = S_STOP; - rt_event_send(&i2c_event, I2C_COMPLETE); - } - } - if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2 - { - //Start TX/RX phase - if(i2cStatus == S3) - { - DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 ); - DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); - switch (i2cFlag) - { - case I2C_WRITE: - i2cStatus = S_STOP; - I2C1->CR1 |= CR1_STOP_Set; - rt_event_send(&i2c_event, I2C_COMPLETE); - break; + regSR1 = 0; + regSR2 = 0; - case I2C_READ_DMA: - i2cStatus = S4; - I2C1->CR1 |= CR1_START_Set; - break; + } + if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6 + { + switch( i2cStatus ) + { + case S2: //Send 1st memory address phase + { + //I2C_DMACmd(I2C1, ENABLE); + I2C1->DR = MemAddr[0]; + if( memtype == I2C_MEM_1Byte ) + i2cStatus = S2_2; + else if( memtype == I2C_MEM_2Bytes ) + i2cStatus = S2_1; + } + break; + case S5: //Set RX buffer phase + { + if( i2cFlag == I2C_READ_DMA ) + { + I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX); + I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set; + DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE); + } + else if( i2cFlag == I2C_READ_INTERRUPT ) + { + I2C1->CR2 |= I2C_IT_BUF; + I2C1->CR1 &= CR1_ACK_Reset; + /* Program the STOP */ + I2C1->CR1 |= CR1_STOP_Set; + } + i2cStatus = S6; + } + break; + } - case I2C_READ_POLLING: - i2cStatus = S_STOP; - rt_event_send(&i2c_event, I2C_COMPLETE); - I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set); - I2C1->CR1 |= CR1_START_Set; - break; + regSR1 = 0; + regSR2 = 0; + //dump_i2c_register(I2C1); + } + if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7 + { + //Interrupt RX complete phase + if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT ) + { + *i2c_buf = I2C1->DR; + i2cStatus = S_STOP; + rt_event_send(&i2c_event, I2C_COMPLETE); + } + } + if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2 + { + //Start TX/RX phase + if(i2cStatus == S3) + { + DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 ); + DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); + switch (i2cFlag) + { + case I2C_WRITE: + i2cStatus = S_STOP; + I2C1->CR1 |= CR1_STOP_Set; + rt_event_send(&i2c_event, I2C_COMPLETE); + break; - case I2C_READ_INTERRUPT: - i2cStatus = S4; - I2C1->CR1 |= CR1_START_Set; - break; - } - } - if( i2cStatus == S2_1 ) //Send 2nd memory address - { - if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes - { - I2C1->DR = MemAddr[1]; - i2cStatus = S2_2; - } - if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT) - { - i2cStatus = S3; - } - } - if( i2cStatus == S2_2 ) //Set TX DAM phase - { - I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX); - I2C1->CR2 |= CR2_DMAEN_Set; - i2cStatus = S3; - } - } + case I2C_READ_DMA: + i2cStatus = S4; + I2C1->CR1 |= CR1_START_Set; + break; - rt_interrupt_leave(); + case I2C_READ_POLLING: + i2cStatus = S_STOP; + rt_event_send(&i2c_event, I2C_COMPLETE); + I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set); + I2C1->CR1 |= CR1_START_Set; + break; + + case I2C_READ_INTERRUPT: + i2cStatus = S4; + I2C1->CR1 |= CR1_START_Set; + break; + } + } + if( i2cStatus == S2_1 ) //Send 2nd memory address + { + if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes + { + I2C1->DR = MemAddr[1]; + i2cStatus = S2_2; + } + if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT) + { + i2cStatus = S3; + } + } + if( i2cStatus == S2_2 ) //Set TX DAM phase + { + I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX); + I2C1->CR2 |= CR2_DMAEN_Set; + i2cStatus = S3; + } + } + + rt_interrupt_leave(); } void DMA1_Stream6_IRQHandler(void) //I2C1 TX { - rt_interrupt_enter(); - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_TX, DMA_IT_TCIF6)) + rt_interrupt_enter(); + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_TX, DMA_IT_TCIF6)) { - I2C_TRACE("TXTC\n"); - DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 ); - + I2C_TRACE("TXTC\n"); + DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 ); + } - rt_interrupt_leave(); + rt_interrupt_leave(); } void DMA1_Stream0_IRQHandler(void) //I2C1 RX { - rt_interrupt_enter(); + rt_interrupt_enter(); - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TCIF0)) + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TCIF0)) + { + I2C_TRACE("RXTC\n"); + /* clear DMA flag */ + DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TCIF0 ); + DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, DISABLE); + DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); + if( i2cStatus == S6 ) + { + i2cStatus = S_STOP; + I2C1->CR1 |= CR1_STOP_Set; + rt_event_send(&i2c_event, I2C_COMPLETE); + } + } + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_HTIF0)) + { + I2C_TRACE("RXHT\n"); + DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_HTIF0 ); + } + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TEIF0)) + { + I2C_TRACE("RXTE\n"); + DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TEIF0 ); + } + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_FEIF0)) + { + I2C_TRACE("RXFE\n"); + DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_FEIF0 ); + } + if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_DMEIF0)) { - I2C_TRACE("RXTC\n"); - /* clear DMA flag */ - DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TCIF0 ); - DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, DISABLE); - DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); - if( i2cStatus == S6 ) - { - i2cStatus = S_STOP; - I2C1->CR1 |= CR1_STOP_Set; - rt_event_send(&i2c_event, I2C_COMPLETE); - } + I2C_TRACE("RXDME\n"); + DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_DMEIF0 ); } - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_HTIF0)) - { - I2C_TRACE("RXHT\n"); - DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_HTIF0 ); - } - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_TEIF0)) - { - I2C_TRACE("RXTE\n"); - DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_TEIF0 ); - } - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_FEIF0)) - { - I2C_TRACE("RXFE\n"); - DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_FEIF0 ); - } - if (DMA_GetITStatus(I2C1_DMA_CHANNEL_RX, DMA_IT_DMEIF0)) - { - I2C_TRACE("RXDME\n"); - DMA_ClearFlag(I2C1_DMA_CHANNEL_RX, DMA_FLAG_DMEIF0 ); - } - rt_interrupt_leave(); + rt_interrupt_leave(); } void I2C1_ER_IRQHandler() { - __IO uint16_t regSR1, regSR2; - - i2cErrorNo = 0; - regSR1 = I2C1->SR1; - I2C_TRACE("I2C Error SR1= 0x%X CR1 = 0x%X\n" , regSR1, I2C1->CR1); - if( (regSR1 & SR1_AF_Set) == SR1_AF_Set) - { - I2C1->SR1 &= ~SR1_AF_Set; - i2cErrorNo |= ERR_AF; - I2C_TRACE("ACK failure\n"); - } - if( (regSR1 & SR1_BERR_Set) == SR1_BERR_Set) - { - I2C1->SR1 &= ~SR1_BERR_Set; - i2cErrorNo |= ERR_BERR; - I2C_TRACE("Bus Error\n"); - } - if( (regSR1 & SR1_ARLO_Set) == SR1_ARLO_Set) - { - I2C1->SR1 &= ~SR1_ARLO_Set; - i2cErrorNo |= ERR_ARLO; - I2C_TRACE("Arblitation lost\n"); - } - //dump_i2c_register(I2C1); + __IO uint16_t regSR1, regSR2; + + i2cErrorNo = 0; + regSR1 = I2C1->SR1; + I2C_TRACE("I2C Error SR1= 0x%X CR1 = 0x%X\n" , regSR1, I2C1->CR1); + if( (regSR1 & SR1_AF_Set) == SR1_AF_Set) + { + I2C1->SR1 &= ~SR1_AF_Set; + i2cErrorNo |= ERR_AF; + I2C_TRACE("ACK failure\n"); + } + if( (regSR1 & SR1_BERR_Set) == SR1_BERR_Set) + { + I2C1->SR1 &= ~SR1_BERR_Set; + i2cErrorNo |= ERR_BERR; + I2C_TRACE("Bus Error\n"); + } + if( (regSR1 & SR1_ARLO_Set) == SR1_ARLO_Set) + { + I2C1->SR1 &= ~SR1_ARLO_Set; + i2cErrorNo |= ERR_ARLO; + I2C_TRACE("Arblitation lost\n"); + } + //dump_i2c_register(I2C1); } Status I2C_Free_Bus(I2C_TypeDef* I2Cx, u32 timeout ) { - /*u32 i = 0; - u16 tmp = 0; - GPIO_InitTypeDef GPIO_InitStructure; + /*u32 i = 0; + u16 tmp = 0; + GPIO_InitTypeDef GPIO_InitStructure; - tmp = I2Cx->SR2; + tmp = I2Cx->SR2; + + while( tmp & SR2_BUSY ) + { + if( i++ < timeout ) + { + if( I2Cx == I2C1 ) + { + //rt_kprintf("Free Bus!\n"); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + GPIO_Init(GPIOB, &GPIO_InitStructure); - while( tmp & SR2_BUSY ) - { - if( i++ < timeout ) - { - if( I2Cx == I2C1 ) - { - //rt_kprintf("Free Bus!\n"); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; - GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_SetBits(GPIOB, GPIO_Pin_6); + GPIO_SetBits(GPIOB, GPIO_Pin_7); - GPIO_SetBits(GPIOB, GPIO_Pin_6); - GPIO_SetBits(GPIOB, GPIO_Pin_7); - - } - else if( I2Cx == I2C2 ) - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; - GPIO_Init(GPIOB, &GPIO_InitStructure); + } + else if( I2Cx == I2C2 ) + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_ResetBits(GPIOB, GPIO_Pin_10); - } - rt_thread_delay(10); - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - I2C_Cmd(I2Cx, DISABLE); - I2C_Cmd(I2Cx, ENABLE); - } - else - return Error; - tmp = I2Cx->SR2; - } */ - return Success; + GPIO_ResetBits(GPIOB, GPIO_Pin_10); + } + rt_thread_delay(10); + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + I2C_Cmd(I2Cx, DISABLE); + I2C_Cmd(I2Cx, ENABLE); + } + else + return Error; + tmp = I2Cx->SR2; + } */ + return Success; } /* - I2Cx: I2C1 or I2C2 (Now it only support I2C1) - pBuffer: Buffer point - NumByteToRW: Number of bytes read/write + I2Cx: I2C1 or I2C2 (Now it only support I2C1) + pBuffer: Buffer point + NumByteToRW: Number of bytes read/write memAddr: 1-2 bytes memory address - SlaveAddress: device address - MemType: 1 = memory address size 1 bytes, 2 = memory address size 2 bytes + SlaveAddress: device address + MemType: 1 = memory address size 1 bytes, 2 = memory address size 2 bytes */ Status I2C_IORW(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToRW, uint16_t memAddr, uint8_t SlaveAddress, uint8_t MemType ) { - uint32_t ev, Timeout=0xFFFF; + uint32_t ev, Timeout=0xFFFF; uint16_t temp, temp2; - static uint32_t call_cnt = 0, i; - Status ret; + static uint32_t call_cnt = 0, i; + Status ret; + + ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER ); + if( ret == RT_EOK ) + { + ret = Success; + DevAddr = SlaveAddress; + BufSize = NumByteToRW; + i2c_buf = pBuffer; + memtype = MemType; + + MemAddr = (uint8_t*)&memAddr; + I2CDirection = I2C_DIRECTION_TX; - ret = rt_mutex_take(i2c_mux, RT_WAITING_FOREVER ); - if( ret == RT_EOK ) - { - ret = Success; - DevAddr = SlaveAddress; - BufSize = NumByteToRW; - i2c_buf = pBuffer; - memtype = MemType; + I2CMode = DMA; - MemAddr = (uint8_t*)&memAddr; - I2CDirection = I2C_DIRECTION_TX; - - I2CMode = DMA; - - i2cStatus = S1; - if( SlaveAddress & 0x01 ) - { - if( BufSize == 1 ) - i2cFlag = I2C_READ_INTERRUPT; //I2C_READ_POLLING; - else - i2cFlag = I2C_READ_DMA; - } - else - i2cFlag = I2C_WRITE; - I2Cx->CR2 |= I2C_IT_ERR | I2C_IT_EVT;// | CR2_DMAEN_Set; - - I2Cx->CR1 |= CR1_START_Set; + i2cStatus = S1; + if( SlaveAddress & 0x01 ) + { + if( BufSize == 1 ) + i2cFlag = I2C_READ_INTERRUPT; //I2C_READ_POLLING; + else + i2cFlag = I2C_READ_DMA; + } + else + i2cFlag = I2C_WRITE; + I2Cx->CR2 |= I2C_IT_ERR | I2C_IT_EVT;// | CR2_DMAEN_Set; + + I2Cx->CR1 |= CR1_START_Set; - Timeout = 0xFFFF; - if( rt_event_recv( &i2c_event, I2C_COMPLETE, RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &ev ) != RT_EOK ) {ret = Error; goto i2cError;} - - if( i2cFlag == I2C_READ_POLLING ) - { - while ((I2Cx->SR1&0x0001) != 0x0001) - if (Timeout-- == 0) {ret = Error; goto i2cError;} - Timeout = 0xFFFF; - I2Cx->DR = DevAddr; - /* Wait until ADDR is set: EV6 */ - while ((I2Cx->SR1&0x0002) != 0x0002) - { - if (Timeout-- == 0){ret = Error; goto i2cError;} - } - /* Clear ACK bit */ - I2Cx->CR1 &= CR1_ACK_Reset; - /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 - software sequence must complete before the current byte end of transfer */ - __disable_irq(); - /* Clear ADDR flag */ - temp = I2Cx->SR2; - /* Program the STOP */ - I2Cx->CR1 |= CR1_STOP_Set; - /* Re-enable IRQs */ - __enable_irq(); - /* Wait until a data is received in DR register (RXNE = 1) EV7 */ - while ((I2Cx->SR1 & 0x00040) != 0x000040)if (Timeout-- == 0){ret = Error; goto i2cError;} - /* Read the data */ - *i2c_buf = I2Cx->DR; - /* Make sure that the STOP bit is cleared by Hardware before CR1 write access */ - while ((I2Cx->CR1&0x200) == 0x200)if (Timeout-- == 0){ret = Error; goto i2cError;} - /* Enable Acknowledgement to be ready for another reception */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - while ((I2Cx->CR1&0x200) == 0x200) - { - if (Timeout-- == 0) {ret = Error; break;} - } - if( i2cFlag == I2C_READ_INTERRUPT ) - I2Cx->CR1 |= CR1_ACK_Set; - } - i2cError: - if( ret == Error ) - { - /* TODO: i2c error handler */ - /* Need check i2cErrorNo and Reset I2C bus */ - } - I2Cx->CR2 &= ~CR2_FREQ_Reset; - //dump_i2c_register(I2C1); - rt_mutex_release(i2c_mux); - return ret; - } - else - return Error; + Timeout = 0xFFFF; + if( rt_event_recv( &i2c_event, I2C_COMPLETE, RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &ev ) != RT_EOK ) {ret = Error; goto i2cError;} + + if( i2cFlag == I2C_READ_POLLING ) + { + while ((I2Cx->SR1&0x0001) != 0x0001) + if (Timeout-- == 0) {ret = Error; goto i2cError;} + Timeout = 0xFFFF; + I2Cx->DR = DevAddr; + /* Wait until ADDR is set: EV6 */ + while ((I2Cx->SR1&0x0002) != 0x0002) + { + if (Timeout-- == 0){ret = Error; goto i2cError;} + } + /* Clear ACK bit */ + I2Cx->CR1 &= CR1_ACK_Reset; + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + /* Clear ADDR flag */ + temp = I2Cx->SR2; + /* Program the STOP */ + I2Cx->CR1 |= CR1_STOP_Set; + /* Re-enable IRQs */ + __enable_irq(); + /* Wait until a data is received in DR register (RXNE = 1) EV7 */ + while ((I2Cx->SR1 & 0x00040) != 0x000040)if (Timeout-- == 0){ret = Error; goto i2cError;} + /* Read the data */ + *i2c_buf = I2Cx->DR; + /* Make sure that the STOP bit is cleared by Hardware before CR1 write access */ + while ((I2Cx->CR1&0x200) == 0x200)if (Timeout-- == 0){ret = Error; goto i2cError;} + /* Enable Acknowledgement to be ready for another reception */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + while ((I2Cx->CR1&0x200) == 0x200) + { + if (Timeout-- == 0) {ret = Error; break;} + } + if( i2cFlag == I2C_READ_INTERRUPT ) + I2Cx->CR1 |= CR1_ACK_Set; + } + i2cError: + if( ret == Error ) + { + /* TODO: i2c error handler */ + /* Need check i2cErrorNo and Reset I2C bus */ + } + I2Cx->CR2 &= ~CR2_FREQ_Reset; + //dump_i2c_register(I2C1); + rt_mutex_release(i2c_mux); + return ret; + } + else + return Error; } void I2C1_INIT() { - GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; I2C_InitTypeDef I2C_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + if( i2c1_init_flag == 0 ) + { + /* Enable the I2C clock */ + RCC_APB1PeriphClockCmd(I2C1_CLK, ENABLE); + /* GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(I2C1_GPIO_CLK, ENABLE); + /* Enable the DMA1 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); - if( i2c1_init_flag == 0 ) - { - /* Enable the I2C clock */ - RCC_APB1PeriphClockCmd(I2C1_CLK, ENABLE); - /* GPIOB clock enable */ - RCC_AHB1PeriphClockCmd(I2C1_GPIO_CLK, ENABLE); - /* Enable the DMA1 clock */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); - - //Reset GPIO - GPIO_InitStructure.GPIO_Pin = I2C1_SDA_PIN | I2C1_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(I2C1_GPIO_PORT, &GPIO_InitStructure); - - /* Connect PXx to I2C_SCL*/ - GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SDA_SOURCE, GPIO_AF_I2C1); - - /* Connect PXx to I2C_SDA*/ - GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SCL_SOURCE, GPIO_AF_I2C1); - - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(I2C1_CLK, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(I2C1_CLK, DISABLE); - - I2C_DeInit(I2C1); - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = OwnAddress1; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = ClockSpeed; - I2C_Init(I2C1, &I2C_InitStructure); - - I2C_Cmd(I2C1, ENABLE); - - /* Configure and enable I2C1 event interrupt -------------------------------*/ - NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C1 DMA interrupt -------------------------------*/ - NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_TX_IRQn; - NVIC_Init(&NVIC_InitStructure); - - NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_RX_IRQn; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C1 error interrupt -------------------------------*/ - NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; - NVIC_Init(&NVIC_InitStructure); - - /* I2C1 TX DMA Channel configuration */ - DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); - DMA_DeInit(I2C1_DMA_CHANNEL_TX); - I2CDMA_InitStructure.DMA_Channel = DMA_Channel_1; - I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address; - I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */ - I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; /* This parameter will be configured durig communication */ - I2CDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ - I2CDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - I2CDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - I2CDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - I2CDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - I2CDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - I2CDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - //I2CDMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - I2CDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - I2CDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; - I2CDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - I2CDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure); - - /* I2C1 RX DMA Channel configuration */ - DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); - DMA_DeInit(I2C1_DMA_CHANNEL_RX); - DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure); - - //I2C_AcknowledgePolling(I2C1, 0x70); - - rt_event_init(&i2c_event, "i2c_event", RT_IPC_FLAG_FIFO ); - i2c_mux = rt_mutex_create("i2c_mux", RT_IPC_FLAG_FIFO ); - i2c1_init_flag = 1; - } + //Reset GPIO + GPIO_InitStructure.GPIO_Pin = I2C1_SDA_PIN | I2C1_SCL_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2C1_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to I2C_SCL*/ + GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SDA_SOURCE, GPIO_AF_I2C1); + + /* Connect PXx to I2C_SDA*/ + GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SCL_SOURCE, GPIO_AF_I2C1); + + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(I2C1_CLK, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(I2C1_CLK, DISABLE); + + I2C_DeInit(I2C1); + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = OwnAddress1; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = ClockSpeed; + I2C_Init(I2C1, &I2C_InitStructure); + + I2C_Cmd(I2C1, ENABLE); + + /* Configure and enable I2C1 event interrupt -------------------------------*/ + NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure and enable I2C1 DMA interrupt -------------------------------*/ + NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_TX_IRQn; + NVIC_Init(&NVIC_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = I2C1_DMA_RX_IRQn; + NVIC_Init(&NVIC_InitStructure); + + /* Configure and enable I2C1 error interrupt -------------------------------*/ + NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_Init(&NVIC_InitStructure); + + /* I2C1 TX DMA Channel configuration */ + DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); + DMA_DeInit(I2C1_DMA_CHANNEL_TX); + I2CDMA_InitStructure.DMA_Channel = DMA_Channel_1; + I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address; + I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */ + I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; /* This parameter will be configured durig communication */ + I2CDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ + I2CDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + I2CDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + I2CDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + I2CDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + I2CDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + I2CDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + //I2CDMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + I2CDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + I2CDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + I2CDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + I2CDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure); + + /* I2C1 RX DMA Channel configuration */ + DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); + DMA_DeInit(I2C1_DMA_CHANNEL_RX); + DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure); + + //I2C_AcknowledgePolling(I2C1, 0x70); + + rt_event_init(&i2c_event, "i2c_event", RT_IPC_FLAG_FIFO ); + i2c_mux = rt_mutex_create("i2c_mux", RT_IPC_FLAG_FIFO ); + i2c1_init_flag = 1; + } } void I2C_DMAConfig(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t BufferSize, uint32_t Direction) { - - I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer; - I2CDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - /* Initialize the DMA with the new parameters */ + + I2CDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer; + I2CDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; + /* Initialize the DMA with the new parameters */ if (Direction == I2C_DIRECTION_TX) { /* Configure the DMA Tx Channel with the buffer address and the buffer size */ I2CDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; if (I2Cx == I2C1) - { + { I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address; - //DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); - DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure); - DMA_Cmd(I2C1_DMA_CHANNEL_TX, ENABLE); - } + //DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE); + DMA_Init(I2C1_DMA_CHANNEL_TX, &I2CDMA_InitStructure); + DMA_Cmd(I2C1_DMA_CHANNEL_TX, ENABLE); + } else - { + { I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address; - //DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE); - DMA_Init(I2C2_DMA_CHANNEL_TX, &I2CDMA_InitStructure); - DMA_Cmd(I2C2_DMA_CHANNEL_TX, ENABLE); - } + //DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE); + DMA_Init(I2C2_DMA_CHANNEL_TX, &I2CDMA_InitStructure); + DMA_Cmd(I2C2_DMA_CHANNEL_TX, ENABLE); + } } else /* Reception */ @@ -609,19 +609,19 @@ void I2C_DMAConfig(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t BufferSize, uin I2CDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; if (I2Cx == I2C1) - { + { I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address; - //DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); - DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure); - DMA_Cmd(I2C1_DMA_CHANNEL_RX, ENABLE); - } - else - { + //DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE); + DMA_Init(I2C1_DMA_CHANNEL_RX, &I2CDMA_InitStructure); + DMA_Cmd(I2C1_DMA_CHANNEL_RX, ENABLE); + } + else + { I2CDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address; - // DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE); - DMA_Init(I2C2_DMA_CHANNEL_RX, &I2CDMA_InitStructure); - DMA_Cmd(I2C2_DMA_CHANNEL_RX, ENABLE); - } + // DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE); + DMA_Init(I2C2_DMA_CHANNEL_RX, &I2CDMA_InitStructure); + DMA_Cmd(I2C2_DMA_CHANNEL_RX, ENABLE); + } } } diff --git a/bsp/stm32f20x/Drivers/i2c.h b/bsp/stm32f20x/Drivers/i2c.h index 3d2c9d871f..e1a6b57427 100644 --- a/bsp/stm32f20x/Drivers/i2c.h +++ b/bsp/stm32f20x/Drivers/i2c.h @@ -5,17 +5,17 @@ /* Exported constants --------------------------------------------------------*/ -#define SR1_AF_Set ((uint16_t)0x0400) -#define SR1_ARLO_Set ((uint16_t)0x0200) -#define SR1_BERR_Set ((uint16_t)0x0100) -#define SR1_ADDR_Set ((uint16_t)0x0002) -#define SR1_SB_Set ((uint16_t)0x0001) +#define SR1_AF_Set ((uint16_t)0x0400) +#define SR1_ARLO_Set ((uint16_t)0x0200) +#define SR1_BERR_Set ((uint16_t)0x0100) +#define SR1_ADDR_Set ((uint16_t)0x0002) +#define SR1_SB_Set ((uint16_t)0x0001) -#define SR2_BUSY ((uint16_t)0x0002) -#define SR2_MSL ((uint16_t)0x0001) +#define SR2_BUSY ((uint16_t)0x0002) +#define SR2_MSL ((uint16_t)0x0001) -#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Set ((uint16_t)0x8000) /* I2C SPE mask */ #define CR1_PE_Set ((uint16_t)0x0001) #define CR1_PE_Reset ((uint16_t)0xFFFE) @@ -97,12 +97,12 @@ #define I2C1_DMA_CHANNEL_TX DMA1_Stream6 #define I2C1_DMA_CHANNEL_RX DMA1_Stream0 -#define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn +#define I2C1_DMA_TX_IRQn DMA1_Stream6_IRQn #define I2C1_DMA_RX_IRQn DMA1_Stream0_IRQn - + #define I2C2_DMA_CHANNEL_TX DMA1_Stream2 #define I2C2_DMA_CHANNEL_RX DMA1_Stream7 -#define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn +#define I2C2_DMA_TX_IRQn DMA1_Stream2_IRQn #define I2C2_DMA_RX_IRQn DMA1_Stream7_IRQn #define I2C1_DR_Address 0x40005410 @@ -112,20 +112,20 @@ #define I2C1_SCL_PIN GPIO_Pin_6 #define I2C1_SDA_SOURCE GPIO_PinSource7 #define I2C1_SCL_SOURCE GPIO_PinSource6 -#define I2C1_GPIO_PORT GPIOB -#define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2C1_GPIO_PORT GPIOB +#define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB #define I2C1_CLK RCC_APB1Periph_I2C1 #define I2C2_SDA_PIN GPIO_Pin_11 #define I2C2_SCL_PIN GPIO_Pin_10 #define I2C2_SDA_SOURCE GPIO_PinSource11 #define I2C2_SCL_SOURCE GPIO_PinSource10 -#define I2C2_GPIO_PORT GPIOB -#define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2C2_GPIO_PORT GPIOB +#define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB #define I2C2_CLK RCC_APB1Periph_I2C1 -#define I2C_MEM_1Byte 1 -#define I2C_MEM_2Bytes 2 +#define I2C_MEM_1Byte 1 +#define I2C_MEM_2Bytes 2 typedef enum { @@ -144,4 +144,4 @@ void I2C1_INIT(); Status I2C_AcknowledgePolling(I2C_TypeDef* I2Cx ,uint8_t Addr); Status I2C_IORW(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToRead, uint16_t memAddr, uint8_t SlaveAddress , uint8_t MemType ); -#endif
\ No newline at end of file +#endif diff --git a/bsp/stm32f20x/Drivers/sdio_sd.c b/bsp/stm32f20x/Drivers/sdio_sd.c index 4c0689768b..9eab300e0f 100644 --- a/bsp/stm32f20x/Drivers/sdio_sd.c +++ b/bsp/stm32f20x/Drivers/sdio_sd.c @@ -4,160 +4,160 @@ * @author MCD Application Team * @version V4.6.1 * @date 18-April-2011 - * @brief This file provides a set of functions needed to manage the SDIO SD + * @brief This file provides a set of functions needed to manage the SDIO SD * Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this memory). - * - * + * to know about the boards supporting this memory). + * + * * @verbatim * * =================================================================== * How to use this driver * =================================================================== - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (SDIO and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c + * It implements a high level communication layer for read and write + * from/to this memory. The needed STM32 hardware resources (SDIO and + * GPIO) are defined in stm32xx_eval.h file, and the initialization is + * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and + * You can easily tailor this driver to any other development board, + * by just adapting the defines for hardware resources and * SD_LowLevel_Init() function. - * + * * A - SD Card Initialization and configuration - * ============================================ - * - To initialize the SD Card, use the SD_Init() function. It - * Initializes the SD Card and put it into StandBy State (Ready + * ============================================ + * - To initialize the SD Card, use the SD_Init() function. It + * Initializes the SD Card and put it into StandBy State (Ready * for data transfer). This function provide the following operations: - * + * * 1 - Apply the SD Card initialization process at 400KHz and check - * the SD Card type (Standard Capacity or High Capacity). You - * can change or adapt this frequency by adjusting the - * "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file. + * the SD Card type (Standard Capacity or High Capacity). You + * can change or adapt this frequency by adjusting the + * "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file. * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ + * + * +---------------------------------------------+ * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In initialization mode and according to the SD Card standard, - * make sure that the SDIO_CK frequency don't exceed 400KHz. - * + * +---------------------------------------------+ + * + * In initialization mode and according to the SD Card standard, + * make sure that the SDIO_CK frequency don't exceed 400KHz. + * * 2 - Get the SD CID and CSD data. All these information are * managed by the SDCardInfo structure. This structure provide - * also ready computed SD Card capacity and Block size. + * also ready computed SD Card capacity and Block size. * * 3 - Configure the SD Card Data transfer frequency. By Default, * the card transfer frequency is set to 24MHz. You can change - * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" + * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" * define inside the stm32xx_eval.h file. * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ + * + * +---------------------------------------------+ * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In transfer mode and according to the SD Card standard, + * +---------------------------------------------+ + * + * In transfer mode and according to the SD Card standard, * make sure that the SDIO_CK frequency don't exceed 25MHz * and 50MHz in High-speed mode switch. * To be able to use a frequency higher than 24MHz, you should - * use the SDIO peripheral in bypass mode. Refer to the + * use the SDIO peripheral in bypass mode. Refer to the * corresponding reference manual for more details. - * + * * 4 - Select the corresponding SD Card according to the address * read with the step 2. - * - * 5 - Configure the SD Card in wide bus mode: 4-bits data. + * + * 5 - Configure the SD Card in wide bus mode: 4-bits data. * * B - SD Card Read operation - * ========================== + * ========================== * - You can read SD card by using two function: SD_ReadBlock() and * SD_ReadMultiBlocks() functions. These functions support only * 512-byte block length. * - The SD_ReadBlock() function read only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to + * function can transfer the data using DMA controller or using + * polling mode. To select between DMA or polling mode refer to * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple - * of 512-byte). + * mode is selected + * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple + * of 512-byte). * - Any read operation should be followed by two functions to check * if the DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the + * - SD_GetStatus(): to check that the SD Card has finished the * data transfer and it is ready for data. - * + * * - The DMA transfer is finished by the SDIO Data End interrupt. User * has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler(). - * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. - * + * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. + * * C - SD Card Write operation - * =========================== + * =========================== * - You can write SD card by using two function: SD_WriteBlock() and * SD_WriteMultiBlocks() functions. These functions support only - * 512-byte block length. + * 512-byte block length. * - The SD_WriteBlock() function write only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to + * function can transfer the data using DMA controller or using + * polling mode. To select between DMA or polling mode refer to * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple - * of 512-byte). + * mode is selected + * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple + * of 512-byte). * - Any write operation should be followed by two functions to check * if the DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * * - The DMA transfer is finished by the SDIO Data End interrupt. User * has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler(). - * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. - - * + * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. + + * * D - SD card status - * ================== + * ================== * - At any time, you can check the SD Card status and get the SD card * state by using the SD_GetStatus() function. This function checks * first if the SD card is still connected and then get the internal - * SD Card transfer state. - * - You can also get the SD card SD Status register by using the - * SD_SendSDStatus() function. - * + * SD Card transfer state. + * - You can also get the SD card SD Status register by using the + * SD_SendSDStatus() function. + * * E - Programming Model - * ===================== + * ===================== * Status = SD_Init(); // Initialization Step as described in section A - * + * * // SDIO Interrupt ENABLE * NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; * NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; * NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; * NVIC_Init(&NVIC_InitStructure); - * + * * // Write operation as described in Section C * Status = SD_WriteBlock(buffer, address, 512); * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * + * while(SD_GetStatus() != SD_TRANSFER_OK); + * * Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * + * while(SD_GetStatus() != SD_TRANSFER_OK); + * * // Read operation as described in Section B * Status = SD_ReadBlock(buffer, address, 512); * Status = SD_WaitReadOperation(); * while(SD_GetStatus() != SD_TRANSFER_OK); - * + * * Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); * Status = SD_WaitReadOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * + * while(SD_GetStatus() != SD_TRANSFER_OK); + * + * * STM32 SDIO Pin assignment - * ========================= + * ========================= * +-----------------------------------------------------------+ * | Pin assignment | * +-----------------------------+---------------+-------------+ @@ -170,11 +170,11 @@ * | SDIO CLK | CLK | 5 | * | | GND | 6 (0 V) | * | SDIO D0 | D0 | 7 | - * | SDIO D1 | D1 | 8 | - * +-----------------------------+---------------+-------------+ - * - * @endverbatim - * + * | SDIO D1 | D1 | 8 | + * +-----------------------------+---------------+-------------+ + * + * @endverbatim + * ****************************************************************************** * @attention * @@ -186,8 +186,8 @@ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "sdio_sd.h" @@ -195,40 +195,40 @@ /** @addtogroup Utilities * @{ */ - + /** @addtogroup STM32_EVAL * @{ - */ + */ /** @addtogroup Common * @{ */ - + /** @addtogroup STM32_EVAL_SDIO_SD * @brief This file provides all the SD Card driver firmware functions. * @{ - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Private_Types * @{ - */ + */ /** * @} - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Private_Defines * @{ - */ -/** - * @brief SDIO Static flags, TimeOut, FIFO Address + */ +/** + * @brief SDIO Static flags, TimeOut, FIFO Address */ #define NULL 0 #define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) #define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) -/** - * @brief Mask for errors Card Status R1 (OCR Register) +/** + * @brief Mask for errors Card Status R1 (OCR Register) */ #define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) #define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) @@ -251,8 +251,8 @@ #define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) #define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) -/** - * @brief Masks for R6 Response +/** + * @brief Masks for R6 Response */ #define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) #define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) @@ -280,22 +280,22 @@ #define SD_HALFFIFO ((uint32_t)0x00000008) #define SD_HALFFIFOBYTES ((uint32_t)0x00000020) -/** - * @brief Command Class Supported +/** + * @brief Command Class Supported */ #define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) #define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) #define SD_CCCC_ERASE ((uint32_t)0x00000020) -/** +/** * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. + * SDIO_APP_CMD should be sent before sending these commands. */ #define SDIO_SEND_IF_COND ((uint32_t)0x00000008) /** * @} - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Private_Macros @@ -303,8 +303,8 @@ */ /** * @} - */ - + */ + /** @defgroup STM32_EVAL_SDIO_SD_Private_Variables * @{ @@ -319,10 +319,10 @@ SD_CardInfo SDCardInfo; SDIO_InitTypeDef SDIO_InitStructure; SDIO_CmdInitTypeDef SDIO_CmdInitStructure; -SDIO_DataInitTypeDef SDIO_DataInitStructure; +SDIO_DataInitTypeDef SDIO_DataInitStructure; /** - * @} - */ + * @} + */ /** @defgroup STM32_EVAL_SDIO_SD_Private_Function_Prototypes @@ -338,15 +338,15 @@ static SD_Error SDEnWideBus(FunctionalState NewState); static SD_Error IsCardProgramming(uint8_t *pstatus); static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); - + /** * @} - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Private_Functions * @{ - */ + */ /** * @brief DeInitializes the SDIO interface. @@ -354,12 +354,12 @@ uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); * @retval None */ void SD_DeInit(void) -{ +{ SD_LowLevel_DeInit(); } /** - * @brief Initializes the SD Card and put it into StandBy State (Ready for data + * @brief Initializes the SD Card and put it into StandBy State (Ready for data * transfer). * @param None * @retval SD_Error: SD Card Error code. @@ -367,7 +367,7 @@ void SD_DeInit(void) SD_Error SD_Init(void) { __IO SD_Error errorstatus = SD_OK; - + /* SDIO Peripheral Low Level Init */ SD_LowLevel_Init(); @@ -391,15 +391,15 @@ SD_Error SD_Init(void) /*!< Configure the SDIO peripheral */ /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */ - /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; SDIO_Init(&SDIO_InitStructure); - + /*----------------- Read CSD/CID MSD registers ------------------*/ errorstatus = SD_GetCardInfo(&SDCardInfo); @@ -412,7 +412,7 @@ SD_Error SD_Init(void) if (errorstatus == SD_OK) { errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); - } + } return(errorstatus); } @@ -421,7 +421,7 @@ SD_Error SD_Init(void) * @brief Gets the cuurent sd card data transfer status. * @param None * @retval SDTransferState: Data Transfer state. - * This value can be: + * This value can be: * - SD_TRANSFER_OK: No data transfer is acting * - SD_TRANSFER_BUSY: Data transfer is acting */ @@ -430,7 +430,7 @@ SDTransferState SD_GetStatus(void) SDCardState cardstate = SD_CARD_TRANSFER; cardstate = SD_GetState(); - + if (cardstate == SD_CARD_TRANSFER) { return(SD_TRANSFER_OK); @@ -453,7 +453,7 @@ SDTransferState SD_GetStatus(void) SDCardState SD_GetState(void) { uint32_t resp1 = 0; - + if(SD_Detect()== SD_PRESENT) { if (SD_SendStatus(&resp1) != SD_OK) @@ -484,12 +484,12 @@ uint8_t SD_Detect(void) /*if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) { status = SD_NOT_PRESENT; - } */ + } */ return status; } /** - * @brief Enquires cards about their operating voltage and configures + * @brief Enquires cards about their operating voltage and configures * clock controls. * @param None * @retval SD_Error: SD Card Error code. @@ -504,7 +504,7 @@ SD_Error SD_PowerON(void) /*!< Configure the SDIO peripheral */ /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV) */ /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ - /*!< SDIO_CK for initialization should not exceed 400 KHz */ + /*!< SDIO_CK for initialization should not exceed 400 KHz */ SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV; SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; @@ -649,7 +649,7 @@ SD_Error SD_PowerOFF(void) } /** - * @brief Intialises all cards or single card as the case may be Card(s) come + * @brief Intialises all cards or single card as the case may be Card(s) come * into standby state. * @param None * @retval SD_Error: SD Card Error code. @@ -739,7 +739,7 @@ SD_Error SD_InitializeCards(void) /** * @brief Returns information about specific card. - * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card + * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card * information. * @retval SD_Error: SD Card Error code. */ @@ -809,7 +809,7 @@ SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) /*!< Byte 10 */ tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); @@ -833,9 +833,9 @@ SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) /*!< Byte 10 */ tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; - cardinfo->CardBlockSize = 512; + cardinfo->CardBlockSize = 512; } @@ -941,14 +941,14 @@ SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; cardinfo->SD_cid.Reserved2 = 1; - + return(errorstatus); } /** - * @brief Enables wide bus opeartion for the requeseted card if supported by + * @brief Enables wide bus opeartion for the requeseted card if supported by * card. - * @param WideMode: Specifies the SD card wide bus mode. + * @param WideMode: Specifies the SD card wide bus mode. * This parameter can be one of the following values: * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) * @arg SDIO_BusWide_4b: 4-bit data transfer @@ -1026,14 +1026,14 @@ SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) /*!< Byte 13 */ tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); cardstatus->ERASE_OFFSET = tmp; - + return(errorstatus); } /** - * @brief Enables wide bus opeartion for the requeseted card if supported by + * @brief Enables wide bus opeartion for the requeseted card if supported by * card. - * @param WideMode: Specifies the SD card wide bus mode. + * @param WideMode: Specifies the SD card wide bus mode. * This parameter can be one of the following values: * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) * @arg SDIO_BusWide_4b: 4-bit data transfer @@ -1064,7 +1064,7 @@ SD_Error SD_EnableWideBusOperation(uint32_t WideMode) if (SD_OK == errorstatus) { /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; @@ -1080,7 +1080,7 @@ SD_Error SD_EnableWideBusOperation(uint32_t WideMode) if (SD_OK == errorstatus) { /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; @@ -1118,32 +1118,32 @@ SD_Error SD_SelectDeselect(uint32_t addr) /** * @brief Allows to read one block from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the * DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. * @param readbuff: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data are to be read. + * @param ReadAddr: Address from where data are to be read. * @param BlockSize: the SD card Data block size. The Block size should be 512. * @retval SD_Error: SD Card Error code. */ SD_Error SD_ReadBlock(uint32_t ReadAddr, uint8_t *readbuff, uint16_t BlockSize) { SD_Error errorstatus = SD_OK; -#if defined (SD_POLLING_MODE) +#if defined (SD_POLLING_MODE) uint32_t count = 0, *tempbuff = (uint32_t *)readbuff; #endif TransferError = SD_OK; TransferEnd = 0; StopCondition = 0; - + SDIO->DCTRL = 0x0; - + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) { BlockSize = 512; @@ -1173,7 +1173,7 @@ SD_Error SD_ReadBlock(uint32_t ReadAddr, uint8_t *readbuff, uint16_t BlockSize) return(errorstatus); } -#if defined (SD_POLLING_MODE) +#if defined (SD_POLLING_MODE) /*!< In case of single block transfer, no need of stop transfer at all.*/ /*!< Polling mode */ while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) @@ -1217,7 +1217,7 @@ SD_Error SD_ReadBlock(uint32_t ReadAddr, uint8_t *readbuff, uint16_t BlockSize) *tempbuff = SDIO_ReadData(); tempbuff++; } - + /*!< Clear all the static flags */ SDIO_ClearFlag(SDIO_STATIC_FLAGS); @@ -1232,13 +1232,13 @@ SD_Error SD_ReadBlock(uint32_t ReadAddr, uint8_t *readbuff, uint16_t BlockSize) /** * @brief Allows to read blocks from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the * DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. * @param readbuff: pointer to the buffer that will contain the received data. * @param ReadAddr: Address from where data are to be read. * @param BlockSize: the SD card Data block size. The Block size should be 512. @@ -1251,7 +1251,7 @@ SD_Error SD_ReadMultiBlocks(uint32_t ReadAddr, uint8_t *readbuff, uint16_t Block TransferError = SD_OK; TransferEnd = 0; StopCondition = 1; - + SDIO->DCTRL = 0x0; if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) @@ -1274,7 +1274,7 @@ SD_Error SD_ReadMultiBlocks(uint32_t ReadAddr, uint8_t *readbuff, uint16_t Block { return(errorstatus); } - + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; @@ -1306,10 +1306,10 @@ SD_Error SD_ReadMultiBlocks(uint32_t ReadAddr, uint8_t *readbuff, uint16_t Block } /** - * @brief This function waits until the SDIO DMA data transfer is finished. + * @brief This function waits until the SDIO DMA data transfer is finished. * This function should be called after SDIO_ReadMultiBlocks() function - * to insure that all data sent by the card are already transferred by - * the DMA controller. + * to insure that all data sent by the card are already transferred by + * the DMA controller. * @param None. * @retval SD_Error: SD Card Error code. */ @@ -1331,14 +1331,14 @@ SD_Error SD_WaitReadOperation(void) /** * @brief Allows to write one block starting from a specified address in a card. * The Data transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the + * @note This operation should be followed by two functions to check if the * DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param WriteAddr: Address from where data are to be read. + * @param WriteAddr: Address from where data are to be read. * @param BlockSize: the SD card Data block size. The Block size should be 512. * @retval SD_Error: SD Card Error code. */ @@ -1354,7 +1354,7 @@ SD_Error SD_WriteBlock(uint32_t WriteAddr, uint8_t *writebuff, uint16_t BlockSiz TransferError = SD_OK; TransferEnd = 0; StopCondition = 0; - + SDIO->DCTRL = 0x0; @@ -1363,7 +1363,7 @@ SD_Error SD_WriteBlock(uint32_t WriteAddr, uint8_t *writebuff, uint16_t BlockSiz BlockSize = 512; //WriteAddr /= 512; } - + /*!< Send CMD24 WRITE_SINGLE_BLOCK */ SDIO_CmdInitStructure.SDIO_Argument = WriteAddr; SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; @@ -1388,7 +1388,7 @@ SD_Error SD_WriteBlock(uint32_t WriteAddr, uint8_t *writebuff, uint16_t BlockSiz SDIO_DataConfig(&SDIO_DataInitStructure); /*!< In case of single data block transfer no need of stop command at all */ -#if defined (SD_POLLING_MODE) +#if defined (SD_POLLING_MODE) while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) { if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) @@ -1447,13 +1447,13 @@ SD_Error SD_WriteBlock(uint32_t WriteAddr, uint8_t *writebuff, uint16_t BlockSiz /** * @brief Allows to write blocks starting from a specified address in a card. - * The Data transfer can be managed by DMA mode only. - * @note This operation should be followed by two functions to check if the + * The Data transfer can be managed by DMA mode only. + * @note This operation should be followed by two functions to check if the * DMA Controller and SD Card status. * - SD_ReadWaitOperation(): this function insure that the DMA * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. * @param WriteAddr: Address from where data are to be read. * @param writebuff: pointer to the buffer that contain the data to be transferred. * @param BlockSize: the SD card Data block size. The Block size should be 512. @@ -1467,7 +1467,7 @@ SD_Error SD_WriteMultiBlocks(uint32_t WriteAddr, uint8_t *writebuff, uint16_t Bl TransferError = SD_OK; TransferEnd = 0; StopCondition = 1; - + SDIO->DCTRL = 0x0; if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) @@ -1531,17 +1531,17 @@ SD_Error SD_WriteMultiBlocks(uint32_t WriteAddr, uint8_t *writebuff, uint16_t Bl SDIO_DataConfig(&SDIO_DataInitStructure); SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE); - SDIO_DMACmd(ENABLE); + SDIO_DMACmd(ENABLE); SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); return(errorstatus); } /** - * @brief This function waits until the SDIO DMA data transfer is finished. + * @brief This function waits until the SDIO DMA data transfer is finished. * This function should be called after SDIO_WriteBlock() and - * SDIO_WriteMultiBlocks() function to insure that all data sent by the - * card are already transferred by the DMA controller. + * SDIO_WriteMultiBlocks() function to insure that all data sent by the + * card are already transferred by the DMA controller. * @param None. * @retval SD_Error: SD Card Error code. */ @@ -1567,7 +1567,7 @@ SD_Error SD_WaitWriteOperation(void) * @brief Gets the cuurent data transfer state. * @param None * @retval SDTransferState: Data Transfer state. - * This value can be: + * This value can be: * - SD_TRANSFER_OK: No data transfer is acting * - SD_TRANSFER_BUSY: Data transfer is acting */ @@ -1633,7 +1633,7 @@ SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) startaddr /= 512; endaddr /= 512; } - + /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) { @@ -1697,7 +1697,7 @@ SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) /** * @brief Returns the current card's status. - * @param pcardstatus: pointer to the buffer that will contain the SD card + * @param pcardstatus: pointer to the buffer that will contain the SD card * status (Card Status register). * @retval SD_Error: SD Card Error code. */ @@ -1707,7 +1707,7 @@ SD_Error SD_SendStatus(uint32_t *pcardstatus) SDIO->ARG = (uint32_t) RCA << 16; SDIO->CMD = 0x44D; - + errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); if (errorstatus != SD_OK) @@ -1721,7 +1721,7 @@ SD_Error SD_SendStatus(uint32_t *pcardstatus) /** * @brief Returns the current SD card's status. - * @param psdstatus: pointer to the buffer that will contain the SD card status + * @param psdstatus: pointer to the buffer that will contain the SD card status * (SD Status register). * @retval SD_Error: SD Card Error code. */ @@ -2008,8 +2008,8 @@ static SD_Error CmdResp2Error(void) /** * @brief Checks for error conditions for R6 (RCA) response. * @param cmd: The sent command index. - * @param prca: pointer to the variable that will contain the SD card relative - * address RCA. + * @param prca: pointer to the variable that will contain the SD card relative + * address RCA. * @retval SD_Error: SD Card Error code. */ static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) @@ -2493,7 +2493,7 @@ uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) /** * @} - */ + */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ @@ -2506,7 +2506,7 @@ uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) #include <dfs_fs.h> /* set sector size to 512 */ -#define SECTOR_SIZE 512 +#define SECTOR_SIZE 512 static struct rt_device sdcard_device; //static SD_CardInfo SDCardInfo; @@ -2516,44 +2516,44 @@ static rt_uint8_t _sdcard_buffer[SECTOR_SIZE]; /* RT-Thread Device Driver Interface */ static rt_err_t rt_sdcard_init(rt_device_t dev) { -/* NVIC_InitTypeDef NVIC_InitStructure; +/* NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); */ + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); */ - if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) - { - rt_kprintf("init sd lock semaphore failed\n"); - } - else - rt_kprintf("SD Card init OK\n"); + if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("init sd lock semaphore failed\n"); + } + else + rt_kprintf("SD Card init OK\n"); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_sdcard_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - SD_Error status; - rt_uint32_t retry; - rt_uint32_t factor; + SD_Error status; + rt_uint32_t retry; + rt_uint32_t factor; - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; - else factor = SECTOR_SIZE; - //rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size); - rt_sem_take(&sd_lock, RT_WAITING_FOREVER); + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; + else factor = SECTOR_SIZE; + //rt_kprintf("sd: read 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer ,pos, size); + rt_sem_take(&sd_lock, RT_WAITING_FOREVER); retry = 3; while(retry) @@ -2571,8 +2571,8 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_ (uint8_t*)_sdcard_buffer, SECTOR_SIZE); status = SD_WaitReadOperation(); - while(SD_GetStatus() != SD_TRANSFER_OK); - if (status != SD_OK) break; + while(SD_GetStatus() != SD_TRANSFER_OK); + if (status != SD_OK) break; /* copy to the buffer */ rt_memcpy(((rt_uint8_t*)buffer + index * SECTOR_SIZE), _sdcard_buffer, SECTOR_SIZE); @@ -2590,49 +2590,49 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_ status = SD_ReadMultiBlocks((part.offset + pos) * factor, (uint8_t*)buffer, SECTOR_SIZE, size); } - status = SD_WaitReadOperation(); - while(SD_GetStatus() != SD_TRANSFER_OK); - /*rt_kprintf("===DUMP SECTOR %d===\n",pos); - { - int i, j; - char* tmp = (char*)buffer; - for(i =0; i < 32;i++) - { - rt_kprintf("%2d: ",i); - for(j= 0; j < 16;j++) - rt_kprintf("%02X ",tmp[i*16+j]); - rt_kprintf("\n"); - } - } */ + status = SD_WaitReadOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); + /*rt_kprintf("===DUMP SECTOR %d===\n",pos); + { + int i, j; + char* tmp = (char*)buffer; + for(i =0; i < 32;i++) + { + rt_kprintf("%2d: ",i); + for(j= 0; j < 16;j++) + rt_kprintf("%02X ",tmp[i*16+j]); + rt_kprintf("\n"); + } + } */ } if (status == SD_OK) break; retry --; } - rt_sem_release(&sd_lock); - if (status == SD_OK) return size; + rt_sem_release(&sd_lock); + if (status == SD_OK) return size; - rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer); - return 0; + rt_kprintf("read failed: %d, buffer 0x%08x\n", status, buffer); + return 0; } static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - SD_Error status; - rt_uint32_t factor; + SD_Error status; + rt_uint32_t factor; + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; + else factor = SECTOR_SIZE; - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) factor = 1; - else factor = SECTOR_SIZE; + //rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size); + rt_sem_take(&sd_lock, RT_WAITING_FOREVER); - //rt_kprintf("sd: write 0x%X, sector 0x%X, 0x%X\n", (uint32_t)buffer , pos, size); - rt_sem_take(&sd_lock, RT_WAITING_FOREVER); - - /* read all sectors */ - if (((rt_uint32_t)buffer % 4 != 0) || + /* read all sectors */ + if (((rt_uint32_t)buffer % 4 != 0) || ((rt_uint32_t)buffer > 0x20080000)) - { - rt_uint32_t index; + { + rt_uint32_t index; /* which is not alignment with 4 or not chip SRAM */ for (index = 0; index < size; index ++) @@ -2643,14 +2643,14 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf status = SD_WriteBlock((part.offset + index + pos) * factor, (uint8_t*)_sdcard_buffer, SECTOR_SIZE); - status = SD_WaitWriteOperation(); - while(SD_GetStatus() != SD_TRANSFER_OK); + status = SD_WaitWriteOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); if (status != SD_OK) break; } - } - else - { + } + else + { if (size == 1) { status = SD_WriteBlock((part.offset + pos) * factor, @@ -2662,15 +2662,15 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf (uint8_t*)buffer, SECTOR_SIZE, size); } - status = SD_WaitWriteOperation(); + status = SD_WaitWriteOperation(); while(SD_GetStatus() != SD_TRANSFER_OK); - } - rt_sem_release(&sd_lock); + } + rt_sem_release(&sd_lock); - if (status == SD_OK) return size; + if (status == SD_OK) return size; - rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer); - return 0; + rt_kprintf("write failed: %d, buffer 0x%08x\n", status, buffer); + return 0; } static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) @@ -2686,89 +2686,89 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) geometry->bytes_per_sector = 512; geometry->block_size = SDCardInfo.CardBlockSize; - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024; - else - geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize; + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + geometry->sector_count = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024; + else + geometry->sector_count = SDCardInfo.CardCapacity/SDCardInfo.CardBlockSize; } - return RT_EOK; + return RT_EOK; } void rt_hw_sdcard_init() { NVIC_InitTypeDef NVIC_InitStructure; - if (SD_Init() == SD_OK) - { - SD_Error status; - rt_uint8_t *sector; + if (SD_Init() == SD_OK) + { + SD_Error status; + rt_uint8_t *sector; - /*status = SD_GetCardInfo(&SDCardInfo); - if (status != SD_OK) goto __return; + /*status = SD_GetCardInfo(&SDCardInfo); + if (status != SD_OK) goto __return; - status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16)); - if (status != SD_OK) goto __return; + status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16)); + if (status != SD_OK) goto __return; - SD_EnableWideBusOperation(SDIO_BusWide_4b); - SD_SetDeviceMode(SD_DMA_MODE); */ + SD_EnableWideBusOperation(SDIO_BusWide_4b); + SD_SetDeviceMode(SD_DMA_MODE); */ - // SDIO Interrupt ENABLE - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + // SDIO Interrupt ENABLE + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - return; - } - status = SD_ReadBlock(0, (uint8_t*)sector, 512); - status = SD_WaitReadOperation(); + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + status = SD_ReadBlock(0, (uint8_t*)sector, 512); + status = SD_WaitReadOperation(); while(SD_GetStatus() != SD_TRANSFER_OK); - if (status == SD_OK) - { - /* get the first partition */ - if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + if (status == SD_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) { /* there is no partition */ part.offset = 0; part.size = 0; } - } - else - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } - /* release sector buffer */ - rt_free(sector); + /* release sector buffer */ + rt_free(sector); - /* register sdcard device */ - sdcard_device.type = RT_Device_Class_Block; - sdcard_device.init = rt_sdcard_init; - sdcard_device.open = rt_sdcard_open; - sdcard_device.close = rt_sdcard_close; - sdcard_device.read = rt_sdcard_read; - sdcard_device.write = rt_sdcard_write; - sdcard_device.control = rt_sdcard_control; + /* register sdcard device */ + sdcard_device.type = RT_Device_Class_Block; + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; - /* no private */ - sdcard_device.user_data = &SDCardInfo; + /* no private */ + sdcard_device.user_data = &SDCardInfo; - rt_device_register(&sdcard_device, "sd0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + rt_device_register(&sdcard_device, "sd0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - return; - } + return; + } __return: - rt_kprintf("sdcard init failed\n"); + rt_kprintf("sdcard init failed\n"); } diff --git a/bsp/stm32f20x/Drivers/sdio_sd.h b/bsp/stm32f20x/Drivers/sdio_sd.h index c4ee35eb07..6a732a5e52 100644 --- a/bsp/stm32f20x/Drivers/sdio_sd.h +++ b/bsp/stm32f20x/Drivers/sdio_sd.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V4.6.1 * @date 18-April-2011 - * @brief This file contains all the functions prototypes for the SD Card + * @brief This file contains all the functions prototypes for the SD Card * stm32_eval_sdio_sd driver firmware library. ****************************************************************************** * @attention @@ -17,8 +17,8 @@ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_EVAL_SDIO_SD_H @@ -34,27 +34,27 @@ /** @addtogroup Utilities * @{ */ - + /** @addtogroup STM32_EVAL * @{ - */ + */ /** @addtogroup Common * @{ */ - + /** @addtogroup STM32_EVAL_SDIO_SD * @{ - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Exported_Types * @{ - */ + */ typedef enum { -/** - * @brief SDIO specific error defines - */ +/** + * @brief SDIO specific error defines + */ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ @@ -89,23 +89,23 @@ typedef enum SD_SDIO_FUNCTION_FAILED = (32), SD_SDIO_UNKNOWN_FUNCTION = (33), -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR, +/** + * @brief Standard error defines + */ + SD_INTERNAL_ERROR, SD_NOT_CONFIGURED, - SD_REQUEST_PENDING, - SD_REQUEST_NOT_APPLICABLE, - SD_INVALID_PARAMETER, - SD_UNSUPPORTED_FEATURE, - SD_UNSUPPORTED_HW, - SD_ERROR, - SD_OK = 0 + SD_REQUEST_PENDING, + SD_REQUEST_NOT_APPLICABLE, + SD_INVALID_PARAMETER, + SD_UNSUPPORTED_FEATURE, + SD_UNSUPPORTED_HW, + SD_ERROR, + SD_OK = 0 } SD_Error; -/** - * @brief SDIO Transfer state - */ +/** + * @brief SDIO Transfer state + */ typedef enum { SD_TRANSFER_OK = 0, @@ -113,9 +113,9 @@ typedef enum SD_TRANSFER_ERROR } SDTransferState; -/** - * @brief SD Card States - */ +/** + * @brief SD Card States + */ typedef enum { SD_CARD_READY = ((uint32_t)0x00000001), @@ -130,9 +130,9 @@ typedef enum }SDCardState; -/** - * @brief Card Specific Data: CSD Register - */ +/** + * @brief Card Specific Data: CSD Register + */ typedef struct { __IO uint8_t CSDStruct; /*!< CSD structure */ @@ -174,8 +174,8 @@ typedef struct __IO uint8_t Reserved4; /*!< always 1*/ } SD_CSD; -/** - * @brief Card Identification Data: CID Register +/** + * @brief Card Identification Data: CID Register */ typedef struct { @@ -191,8 +191,8 @@ typedef struct __IO uint8_t Reserved2; /*!< always 1 */ } SD_CID; -/** - * @brief SD Card Status +/** + * @brief SD Card Status */ typedef struct { @@ -209,8 +209,8 @@ typedef struct } SD_CardStatus; -/** - * @brief SD Card information +/** + * @brief SD Card information */ typedef struct { @@ -225,13 +225,13 @@ typedef struct /** * @} */ - + /** @defgroup STM32_EVAL_SDIO_SD_Exported_Constants * @{ - */ + */ -/** - * @brief SDIO Commands Index +/** + * @brief SDIO Commands Index */ #define SD_CMD_GO_IDLE_STATE ((uint8_t)0) #define SD_CMD_SEND_OP_COND ((uint8_t)1) @@ -280,9 +280,9 @@ typedef struct #define SD_CMD_GEN_CMD ((uint8_t)56) #define SD_CMD_NO_CMD ((uint8_t)64) -/** +/** * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. + * SDIO_APP_CMD should be sent before sending these commands. */ #define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ #define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ @@ -293,9 +293,9 @@ typedef struct #define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ #define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ -/** +/** * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. + * SDIO_APP_CMD should be sent before sending these commands. */ #define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ #define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ @@ -308,8 +308,8 @@ typedef struct #define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ #define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ #define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/* Uncomment the following line to select the SDIO Data transfer mode */ + +/* Uncomment the following line to select the SDIO Data transfer mode */ #define SD_DMA_MODE ((uint32_t)0x00000000) /*#define SD_POLLING_MODE ((uint32_t)0x00000002)*/ @@ -319,8 +319,8 @@ typedef struct #define SD_PRESENT ((uint8_t)0x01) #define SD_NOT_PRESENT ((uint8_t)0x00) -/** - * @brief Supported SD Memory Cards +/** + * @brief Supported SD Memory Cards */ #define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) #define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) @@ -333,18 +333,18 @@ typedef struct /** * @} - */ - + */ + /** @defgroup STM32_EVAL_SDIO_SD_Exported_Macros * @{ - */ + */ /** * @} - */ + */ /** @defgroup STM32_EVAL_SDIO_SD_Exported_Functions * @{ - */ + */ void SD_DeInit(void); SD_Error SD_Init(void); SDTransferState SD_GetStatus(void); @@ -388,10 +388,10 @@ SD_Error SD_WaitWriteOperation(void); /** * @} - */ + */ /** * @} - */ + */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f20x/Drivers/serial.c b/bsp/stm32f20x/Drivers/serial.c index 4ccc041689..cafde1a3e1 100644 --- a/bsp/stm32f20x/Drivers/serial.c +++ b/bsp/stm32f20x/Drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #include <stm32f2xx_usart.h> static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel, - rt_uint32_t address, rt_uint32_t size); + rt_uint32_t address, rt_uint32_t size); /** * @addtogroup STM32 @@ -26,252 +26,252 @@ static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel, /* RT-Thread Device Interface */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data; + struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = 0; - uart->int_rx->save_index = 0; - } + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } - if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL); - uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL; + if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL); + uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL; - /* init data node memory pool */ - rt_mp_init(&(uart->dma_tx->data_node_mp), "dn", - uart->dma_tx->data_node_mem_pool, - sizeof(uart->dma_tx->data_node_mem_pool), - sizeof(struct stm32_serial_data_node)); - } + /* init data node memory pool */ + rt_mp_init(&(uart->dma_tx->data_node_mp), "dn", + uart->dma_tx->data_node_mem_pool, + sizeof(uart->dma_tx->data_node_mem_pool), + sizeof(struct stm32_serial_data_node)); + } - /* Enable USART */ - USART_Cmd(uart->uart_device, ENABLE); + /* Enable USART */ + USART_Cmd(uart->uart_device, ENABLE); - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct stm32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct stm32_serial_device* uart; - ptr = buffer; - err_code = RT_EOK; - uart = (struct stm32_serial_device*)dev->user_data; + ptr = buffer; + err_code = RT_EOK; + uart = (struct stm32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - /* read a character */ - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size--; + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; - /* move to next position */ - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->SR & USART_FLAG_RXNE) - { - *ptr = uart->uart_device->DR & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->SR & USART_FLAG_RXNE) + { + *ptr = uart->uart_device->DR & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel, - rt_uint32_t address, rt_uint32_t size) + rt_uint32_t address, rt_uint32_t size) { - RT_ASSERT(dma_channel != RT_NULL); + RT_ASSERT(dma_channel != RT_NULL); - /* disable DMA */ - DMA_Cmd(dma_channel, DISABLE); + /* disable DMA */ + DMA_Cmd(dma_channel, DISABLE); - /* set buffer address */ - dma_channel->M0AR = address; - /* set size */ - dma_channel->NDTR = size; + /* set buffer address */ + dma_channel->M0AR = address; + /* set size */ + dma_channel->NDTR = size; - /* enable DMA */ - DMA_Cmd(dma_channel, ENABLE); + /* enable DMA */ + DMA_Cmd(dma_channel, ENABLE); } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct stm32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct stm32_serial_device* uart; - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct stm32_serial_device*)dev->user_data; + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct stm32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx, does not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* DMA mode Tx */ + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* DMA mode Tx */ - /* allocate a data node */ - struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*) - rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER); - if (data_node == RT_NULL) - { - /* set error code */ - err_code = -RT_ENOMEM; - } - else - { - rt_uint32_t level; + /* allocate a data node */ + struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*) + rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER); + if (data_node == RT_NULL) + { + /* set error code */ + err_code = -RT_ENOMEM; + } + else + { + rt_uint32_t level; - /* fill data node */ - data_node->data_ptr = ptr; - data_node->data_size = size; + /* fill data node */ + data_node->data_ptr = ptr; + data_node->data_size = size; - /* insert to data link */ - data_node->next = RT_NULL; + /* insert to data link */ + data_node->next = RT_NULL; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - data_node->prev = uart->dma_tx->list_tail; - if (uart->dma_tx->list_tail != RT_NULL) - uart->dma_tx->list_tail->next = data_node; - uart->dma_tx->list_tail = data_node; + data_node->prev = uart->dma_tx->list_tail; + if (uart->dma_tx->list_tail != RT_NULL) + uart->dma_tx->list_tail->next = data_node; + uart->dma_tx->list_tail = data_node; - if (uart->dma_tx->list_head == RT_NULL) - { - /* start DMA to transmit data */ - uart->dma_tx->list_head = data_node; + if (uart->dma_tx->list_head == RT_NULL) + { + /* start DMA to transmit data */ + uart->dma_tx->list_head = data_node; - /* Enable DMA Channel */ - rt_serial_enable_dma(uart->dma_tx->dma_channel, - (rt_uint32_t)uart->dma_tx->list_head->data_ptr, - uart->dma_tx->list_head->data_size); - } + /* Enable DMA Channel */ + rt_serial_enable_dma(uart->dma_tx->dma_channel, + (rt_uint32_t)uart->dma_tx->list_head->data_ptr, + uart->dma_tx->list_head->data_size); + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(uart->uart_device->SR & USART_FLAG_TXE)); - uart->uart_device->DR = '\r'; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(uart->uart_device->SR & USART_FLAG_TXE)); + uart->uart_device->DR = '\r'; + } - while (!(uart->uart_device->SR & USART_FLAG_TXE)); - uart->uart_device->DR = (*ptr & 0x1FF); + while (!(uart->uart_device->SR & USART_FLAG_TXE)); + uart->uart_device->DR = (*ptr & 0x1FF); - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - while (!(uart->uart_device->SR & USART_FLAG_TXE)); - uart->uart_device->DR = (*ptr & 0x1FF); + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + while (!(uart->uart_device->SR & USART_FLAG_TXE)); + uart->uart_device->DR = (*ptr & 0x1FF); - ++ptr; --size; - } - } - } + ++ptr; --size; + } + } + } - /* set error code */ - rt_set_errno(err_code); + /* set error code */ + rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - struct stm32_serial_device* uart; + struct stm32_serial_device* uart; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - uart = (struct stm32_serial_device*)dev->user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - USART_Cmd(uart->uart_device, DISABLE); - break; + uart = (struct stm32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + USART_Cmd(uart->uart_device, DISABLE); + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - USART_Cmd(uart->uart_device, ENABLE); - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + USART_Cmd(uart->uart_device, ENABLE); + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -280,87 +280,87 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; + struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; - if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) - { - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* save on rx buffer */ - while (uart->uart_device->SR & USART_FLAG_RXNE) - { - rt_base_t level; + /* save on rx buffer */ + while (uart->uart_device->SR & USART_FLAG_RXNE) + { + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* save character */ - uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } - } + device->rx_indicate(device, rx_length); + } + } - if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) - { - /* clear interrupt */ - USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); - } + if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) + { + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); + } } /* @@ -368,47 +368,47 @@ void rt_hw_serial_isr(rt_device_t device) */ void rt_hw_serial_dma_tx_isr(rt_device_t device) { - rt_uint32_t level; - struct stm32_serial_data_node* data_node; - struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; + rt_uint32_t level; + struct stm32_serial_data_node* data_node; + struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data; - /* DMA mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX); + /* DMA mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX); - /* get the first data node */ - data_node = uart->dma_tx->list_head; - RT_ASSERT(data_node != RT_NULL); + /* get the first data node */ + data_node = uart->dma_tx->list_head; + RT_ASSERT(data_node != RT_NULL); - /* invoke call to notify tx complete */ - if (device->tx_complete != RT_NULL) - device->tx_complete(device, data_node->data_ptr); + /* invoke call to notify tx complete */ + if (device->tx_complete != RT_NULL) + device->tx_complete(device, data_node->data_ptr); - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* remove list head */ - uart->dma_tx->list_head = data_node->next; - if (uart->dma_tx->list_head == RT_NULL) /* data link empty */ - uart->dma_tx->list_tail = RT_NULL; + /* remove list head */ + uart->dma_tx->list_head = data_node->next; + if (uart->dma_tx->list_head == RT_NULL) /* data link empty */ + uart->dma_tx->list_tail = RT_NULL; - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* release data node memory */ - rt_mp_free(data_node); + /* release data node memory */ + rt_mp_free(data_node); - if (uart->dma_tx->list_head != RT_NULL) - { - /* transmit next data node */ - rt_serial_enable_dma(uart->dma_tx->dma_channel, - (rt_uint32_t)uart->dma_tx->list_head->data_ptr, - uart->dma_tx->list_head->data_size); - } - else - { - /* no data to be transmitted, disable DMA */ - DMA_Cmd(uart->dma_tx->dma_channel, DISABLE); - } + if (uart->dma_tx->list_head != RT_NULL) + { + /* transmit next data node */ + rt_serial_enable_dma(uart->dma_tx->dma_channel, + (rt_uint32_t)uart->dma_tx->list_head->data_ptr, + uart->dma_tx->list_head->data_size); + } + else + { + /* no data to be transmitted, disable DMA */ + DMA_Cmd(uart->dma_tx->dma_channel, DISABLE); + } } /*@}*/ diff --git a/bsp/stm32f20x/Drivers/serial.h b/bsp/stm32f20x/Drivers/serial.h index 8ab56b4839..4df341a0e3 100644 --- a/bsp/stm32f20x/Drivers/serial.h +++ b/bsp/stm32f20x/Drivers/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,45 +17,45 @@ /* STM32F10x library definitions */ #include <stm32f2xx.h> -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_DMA_NODE_SIZE 4 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 /* data node for Tx Mode */ struct stm32_serial_data_node { - rt_uint8_t *data_ptr; - rt_size_t data_size; - struct stm32_serial_data_node *next, *prev; + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct stm32_serial_data_node *next, *prev; }; struct stm32_serial_dma_tx { - /* DMA Channel */ - DMA_Stream_TypeDef* dma_channel; + /* DMA Channel */ + DMA_Stream_TypeDef* dma_channel; - /* data list head and tail */ - struct stm32_serial_data_node *list_head, *list_tail; + /* data list head and tail */ + struct stm32_serial_data_node *list_head, *list_tail; - /* data node memory pool */ - struct rt_mempool data_node_mp; - rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE * - (sizeof(struct stm32_serial_data_node) + sizeof(void*))]; + /* data node memory pool */ + struct rt_mempool data_node_mp; + rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE * + (sizeof(struct stm32_serial_data_node) + sizeof(void*))]; }; struct stm32_serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct stm32_serial_device { - USART_TypeDef* uart_device; + USART_TypeDef* uart_device; - /* rx structure */ - struct stm32_serial_int_rx* int_rx; + /* rx structure */ + struct stm32_serial_int_rx* int_rx; - /* tx structure */ - struct stm32_serial_dma_tx* dma_tx; + /* tx structure */ + struct stm32_serial_dma_tx* dma_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial); diff --git a/bsp/stm32f20x/Drivers/stm32f2_eth.c b/bsp/stm32f20x/Drivers/stm32f2_eth.c index 1876c5bcaa..c774e16ed2 100644 --- a/bsp/stm32f20x/Drivers/stm32f2_eth.c +++ b/bsp/stm32f20x/Drivers/stm32f2_eth.c @@ -10,14 +10,14 @@ #include "stm32f2x7_eth.h" #include "stm32f2x7_eth_conf.h" -#define STM32_ETH_DEBUG 0 +#define STM32_ETH_DEBUG 0 //#define CHECKSUM_BY_HARDWARE /* don't ues hardware checksum. */ /* MII and RMII mode selection, for STM322xG-EVAL Board(MB786) RevB ***********/ -//#define MII_MODE +//#define MII_MODE #define RMII_MODE // In this case the System clock frequency is configured - // to 100 MHz, for more details refer to system_stm32f2xx.c + // to 100 MHz, for more details refer to system_stm32f2xx.c #define DP83848_PHY_ADDRESS 0x01 /* Relative to STM322xG-EVAL Board */ @@ -27,10 +27,10 @@ extern ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; /* Ethernet Receive buffers */ -extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; +extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Transmit buffers */ -extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; +extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Global pointers to track current transmit and receive descriptors */ extern ETH_DMADESCTypeDef *DMATxDescToSet; @@ -42,11 +42,11 @@ extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos; #define MAX_ADDR_LEN 6 struct rt_stm32_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_stm32_eth stm32_eth_device; static struct rt_semaphore tx_wait; @@ -61,29 +61,29 @@ void ETH_IRQHandler(void) { rt_uint32_t status; - status = ETH->DMASR; + status = ETH->DMASR; - /* Frame received */ - if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET) - { - rt_err_t result; - //rt_kprintf("Frame comming\n"); - /* Clear the interrupt flags. */ - /* Clear the Eth DMA Rx IT pending bits */ - ETH_DMAClearITPendingBit(ETH_DMA_IT_R); + /* Frame received */ + if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET) + { + rt_err_t result; + //rt_kprintf("Frame comming\n"); + /* Clear the interrupt flags. */ + /* Clear the Eth DMA Rx IT pending bits */ + ETH_DMAClearITPendingBit(ETH_DMA_IT_R); - /* a frame has been received */ - result = eth_device_ready(&(stm32_eth_device.parent)); - if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result ); - //RT_ASSERT(result == RT_EOK); - } - if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */ - { - ETH_DMAClearITPendingBit(ETH_DMA_IT_T); - } - - ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS); -// + /* a frame has been received */ + result = eth_device_ready(&(stm32_eth_device.parent)); + if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result ); + //RT_ASSERT(result == RT_EOK); + } + if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */ + { + ETH_DMAClearITPendingBit(ETH_DMA_IT_T); + } + + ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS); +// } @@ -91,244 +91,244 @@ void ETH_IRQHandler(void) /* initialize the interface */ static rt_err_t rt_stm32_eth_init(rt_device_t dev) { - int i; + int i; + + /* MAC address configuration */ + ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); + + /* Initialize Tx Descriptors list: Chain Mode */ + ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + /* Initialize Rx Descriptors list: Chain Mode */ + ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); - /* MAC address configuration */ - ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); - - /* Initialize Tx Descriptors list: Chain Mode */ - ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); - /* Initialize Rx Descriptors list: Chain Mode */ - ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); + /* Enable Ethernet Rx interrrupt */ + { + for(i=0; i<ETH_RXBUFNB; i++) + { + ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE); + } + } - /* Enable Ethernet Rx interrrupt */ - { - for(i=0; i<ETH_RXBUFNB; i++) - { - ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE); - } - } - - #ifdef CHECKSUM_BY_HARDWARE - /* Enable the checksum insertion for the Tx frames */ - { - for(i=0; i<ETH_TXBUFNB; i++) - { - ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull); - } - } - #endif + #ifdef CHECKSUM_BY_HARDWARE + /* Enable the checksum insertion for the Tx frames */ + { + for(i=0; i<ETH_TXBUFNB; i++) + { + ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull); + } + } + #endif - { - uint16_t tmp, i=10000; + { + uint16_t tmp, i=10000; - tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); - ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE ); - ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START + tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); + ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE ); + ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START - while(i--); + while(i--); - //tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); + //tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); - if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS ) - { - rt_kprintf("BIST pass\n"); - } - else - { - uint16_t ctrl; + if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS ) + { + rt_kprintf("BIST pass\n"); + } + else + { + uint16_t ctrl; - ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1); - rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) ); - } - tmp &= ~BIST_START; //Stop BIST - ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp); + ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1); + rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) ); + } + tmp &= ~BIST_START; //Stop BIST + ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp); - } + } - /* Enable MAC and DMA transmission and reception */ - ETH_Start(); + /* Enable MAC and DMA transmission and reception */ + ETH_Start(); - //rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); -// rt_kprintf("ETH Init\n"); + //rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); +// rt_kprintf("ETH Init\n"); return RT_EOK; } static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_stm32_eth_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } void show_frame(struct pbuf *q) { - int i = 0; - int j = 0; - char *ptr = q->payload; + int i = 0; + int j = 0; + char *ptr = q->payload; - for( i = 0; i < q->len; i++ ) - rt_kprintf("0x%02X ", *(ptr++)); - rt_kprintf("\n"); + for( i = 0; i < q->len; i++ ) + rt_kprintf("0x%02X ", *(ptr++)); + rt_kprintf("\n"); } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) { - rt_err_t ret; - struct pbuf *q; - uint32_t l = 0; - u8 *buffer ; - - if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK) - { - buffer = (u8 *)(DMATxDescToSet->Buffer1Addr); - for(q = p; q != NULL; q = q->next) - { - //show_frame(q); - rt_memcpy((u8_t*)&buffer[l], q->payload, q->len); - l = l + q->len; - } - if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR ) - rt_kprintf("Tx Error\n"); - //rt_sem_release(xTxSemaphore); - rt_sem_release(&tx_wait); - //rt_kprintf("Tx packet, len = %d\n", l); - } - else - { - rt_kprintf("Tx Timeout\n"); - return ret; - } + rt_err_t ret; + struct pbuf *q; + uint32_t l = 0; + u8 *buffer ; - /* Return SUCCESS */ - return RT_EOK; + if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK) + { + buffer = (u8 *)(DMATxDescToSet->Buffer1Addr); + for(q = p; q != NULL; q = q->next) + { + //show_frame(q); + rt_memcpy((u8_t*)&buffer[l], q->payload, q->len); + l = l + q->len; + } + if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR ) + rt_kprintf("Tx Error\n"); + //rt_sem_release(xTxSemaphore); + rt_sem_release(&tx_wait); + //rt_kprintf("Tx packet, len = %d\n", l); + } + else + { + rt_kprintf("Tx Timeout\n"); + return ret; + } + + /* Return SUCCESS */ + return RT_EOK; } /* reception packet. */ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) { - struct pbuf *p, *q; - u16_t len; - uint32_t l=0,i =0; - FrameTypeDef frame; - static framecnt = 1; - u8 *buffer; - __IO ETH_DMADESCTypeDef *DMARxNextDesc; - - p = RT_NULL; - -// rt_kprintf("ETH rx\n"); - /* Get received frame */ - frame = ETH_Get_Received_Frame_interrupt(); - - if( frame.length > 0 ) - { - /* check that frame has no error */ - if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) - { - //rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length); - /* Obtain the size of the packet and put it into the "len" variable. */ - len = frame.length; - buffer = (u8 *)frame.buffer; - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - //p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + struct pbuf *p, *q; + u16_t len; + uint32_t l=0,i =0; + FrameTypeDef frame; + static framecnt = 1; + u8 *buffer; + __IO ETH_DMADESCTypeDef *DMARxNextDesc; + + p = RT_NULL; + +// rt_kprintf("ETH rx\n"); + /* Get received frame */ + frame = ETH_Get_Received_Frame_interrupt(); + + if( frame.length > 0 ) + { + /* check that frame has no error */ + if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) + { + //rt_kprintf("Get a frame %d buf = 0x%X, len= %d\n", framecnt++, frame.buffer, frame.length); + /* Obtain the size of the packet and put it into the "len" variable. */ + len = frame.length; + buffer = (u8 *)frame.buffer; + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + //p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + + /* Copy received frame from ethernet driver buffer to stack buffer */ + if (p != NULL) + { + for (q = p; q != NULL; q = q->next) + { + rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len); + l = l + q->len; + } + } + } - /* Copy received frame from ethernet driver buffer to stack buffer */ - if (p != NULL) - { - for (q = p; q != NULL; q = q->next) - { - rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len); - l = l + q->len; - } - } - } - - /* Release descriptors to DMA */ - /* Check if received frame with multiple DMA buffer segments */ - if (DMA_RX_FRAME_infos->Seg_Count > 1) - { - DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc; - } - else - { - DMARxNextDesc = frame.descriptor; - } - - /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ - for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++) - { - DMARxNextDesc->Status = ETH_DMARxDesc_OWN; - DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr); - } - - /* Clear Segment_Count */ - DMA_RX_FRAME_infos->Seg_Count =0; - - - /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_RBUS; - - /* Resume DMA reception */ - ETH->DMARPDR = 0; - } - } - return p; + /* Release descriptors to DMA */ + /* Check if received frame with multiple DMA buffer segments */ + if (DMA_RX_FRAME_infos->Seg_Count > 1) + { + DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc; + } + else + { + DMARxNextDesc = frame.descriptor; + } + + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++) + { + DMARxNextDesc->Status = ETH_DMARxDesc_OWN; + DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr); + } + + /* Clear Segment_Count */ + DMA_RX_FRAME_infos->Seg_Count =0; + + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + } + return p; } static void NVIC_Configuration(void) { - NVIC_InitTypeDef NVIC_InitStructure; - - /* 2 bit for pre-emption priority, 2 bits for subpriority */ - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); - /* Enable the Ethernet global Interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + NVIC_InitTypeDef NVIC_InitStructure; + + /* 2 bit for pre-emption priority, 2 bits for subpriority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + /* Enable the Ethernet global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); } /* @@ -383,15 +383,15 @@ static void GPIO_Configuration(void) ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12 ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13 - **** Just for MII Mode **** - ETH_MII_CRS ----------------------> PA0 - ETH_MII_COL ----------------------> PA3 - ETH_MII_TX_CLK -------------------> PC3 - ETH_MII_RX_ER --------------------> PB10 - ETH_MII_RXD2 ---------------------> PB0 - ETH_MII_RXD3 ---------------------> PB1 - ETH_MII_TXD2 ---------------------> PC2 - ETH_MII_TXD3 ---------------------> PB8 + **** Just for MII Mode **** + ETH_MII_CRS ----------------------> PA0 + ETH_MII_COL ----------------------> PA3 + ETH_MII_TX_CLK -------------------> PC3 + ETH_MII_RX_ER --------------------> PB10 + ETH_MII_RXD2 ---------------------> PB0 + ETH_MII_RXD3 ---------------------> PB1 + ETH_MII_TXD2 ---------------------> PC2 + ETH_MII_TXD3 ---------------------> PB8 */ /* Configure PC1, PC4 and PC5 */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5; @@ -450,7 +450,7 @@ static void ETH_MACDMA_Config(void) /* Enable ETHERNET clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | - RCC_AHB1Periph_ETH_MAC_Rx, ENABLE); + RCC_AHB1Periph_ETH_MAC_Rx, ENABLE); /* Reset ETHERNET on AHB Bus */ ETH_DeInit(); @@ -468,9 +468,9 @@ static void ETH_MACDMA_Config(void) /* Fill ETH_InitStructure parametrs */ /*------------------------ MAC -----------------------------------*/ ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; - //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; // ETH_InitStructure.ETH_Speed = ETH_Speed_10M; - // ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + // ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; @@ -484,95 +484,95 @@ static void ETH_MACDMA_Config(void) ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif - /*------------------------ DMA -----------------------------------*/ - - /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: - the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + /*------------------------ DMA -----------------------------------*/ + + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ - ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - - ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; - ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; - ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; /* Configure Ethernet */ if( ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS) == ETH_ERROR ) - rt_kprintf("ETH init error, may be no link\n"); + rt_kprintf("ETH init error, may be no link\n"); /* Enable the Ethernet Rx Interrupt */ ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R , ENABLE); } -#define DevID_SNo0 (*((rt_uint32_t *)0x1FFF7A10)); -#define DevID_SNo1 (*((rt_uint32_t *)0x1FFF7A10+32)); +#define DevID_SNo0 (*((rt_uint32_t *)0x1FFF7A10)); +#define DevID_SNo1 (*((rt_uint32_t *)0x1FFF7A10+32)); #define DevID_SNo2 (*((rt_uint32_t *)0x1FFF7A10+64)); void rt_hw_stm32_eth_init(void) { - GPIO_Configuration(); - NVIC_Configuration(); - ETH_MACDMA_Config(); + GPIO_Configuration(); + NVIC_Configuration(); + ETH_MACDMA_Config(); stm32_eth_device.dev_addr[0] = 0x00; stm32_eth_device.dev_addr[1] = 0x60; stm32_eth_device.dev_addr[2] = 0x6e; - { - uint32_t cpu_id[3] = {0}; - cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0; - - // generate MAC addr from 96bit unique ID (only for test) - stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF); - stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF); - stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF); + { + uint32_t cpu_id[3] = {0}; + cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0; + + // generate MAC addr from 96bit unique ID (only for test) + stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF); + stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF); + stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF); -// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7); -// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8); -// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9); - } +// stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7); +// stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8); +// stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9); + } - stm32_eth_device.parent.parent.init = rt_stm32_eth_init; - stm32_eth_device.parent.parent.open = rt_stm32_eth_open; - stm32_eth_device.parent.parent.close = rt_stm32_eth_close; - stm32_eth_device.parent.parent.read = rt_stm32_eth_read; - stm32_eth_device.parent.parent.write = rt_stm32_eth_write; - stm32_eth_device.parent.parent.control = rt_stm32_eth_control; - stm32_eth_device.parent.parent.user_data = RT_NULL; + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; - stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; - stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; - /* init tx semaphore */ - rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO); + /* init tx semaphore */ + rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO); - /* register eth device */ - eth_device_init(&(stm32_eth_device.parent), "e0"); + /* register eth device */ + eth_device_init(&(stm32_eth_device.parent), "e0"); } static char led = 0; void dp83483() { - uint16_t bsr,sts, bcr, phycr; + uint16_t bsr,sts, bcr, phycr; - bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR); - sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR); - bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR); - phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); + bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR); + sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR); + bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR); + phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR); - rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr); + rt_kprintf("BCR = 0x%X\tBSR = 0x%X\tPHY_STS = 0x%X\tPHY_CR = 0x%X\n", bcr,bsr,sts, phycr); - rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) ); - rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) ); + rt_kprintf("PHY_FCSCR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR ) ); + rt_kprintf("PHY_MISR = 0x%X\n", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) ); - rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); + rt_kprintf("DMASR = 0x%X\n", ETH->DMASR ); - //ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led)); - led = (led==7)?0:7; + //ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led)); + led = (led==7)?0:7; } #ifdef RT_USING_FINSH diff --git a/bsp/stm32f20x/Drivers/stm32f2xx_it.c b/bsp/stm32f20x/Drivers/stm32f2xx_it.c index 6126d7173d..3a482fa747 100644 --- a/bsp/stm32f20x/Drivers/stm32f2xx_it.c +++ b/bsp/stm32f20x/Drivers/stm32f2xx_it.c @@ -1,11 +1,11 @@ /** ****************************************************************************** - * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c + * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c * @author MCD Application Team * @version V1.0.0 * @date 18-April-2011 * @brief Main Interrupt Service Routines. - * This file provides template for all exceptions handler and + * This file provides template for all exceptions handler and * peripherals interrupt service routine. ****************************************************************************** * @attention @@ -19,7 +19,7 @@ * * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f2xx.h" @@ -126,7 +126,7 @@ void DebugMon_Handler(void) /** * @} - */ + */ #if defined(RT_USING_DFS) && STM32_USE_SDIO /******************************************************************************* @@ -145,7 +145,7 @@ void SDIO_IRQHandler(void) /* Process All SDIO Interrupt Sources */ if( SD_ProcessIRQSrc() == 2) - rt_kprintf("SD Error\n"); + rt_kprintf("SD Error\n"); /* leave interrupt */ rt_interrupt_leave(); diff --git a/bsp/stm32f20x/Drivers/usart.c b/bsp/stm32f20x/Drivers/usart.c index ff82ab9f8a..876b187940 100644 --- a/bsp/stm32f20x/Drivers/usart.c +++ b/bsp/stm32f20x/Drivers/usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,9 +34,9 @@ struct stm32_serial_int_rx uart1_int_rx; struct stm32_serial_device uart1 = { - USART1, - &uart1_int_rx, - RT_NULL + USART1, + &uart1_int_rx, + RT_NULL }; struct rt_device uart1_device; #endif @@ -45,9 +45,9 @@ struct rt_device uart1_device; struct stm32_serial_int_rx uart6_int_rx; struct stm32_serial_device uart6 = { - USART6, - &uart6_int_rx, - RT_NULL + USART6, + &uart6_int_rx, + RT_NULL }; struct rt_device uart6_device; #endif @@ -56,9 +56,9 @@ struct rt_device uart6_device; struct stm32_serial_int_rx uart2_int_rx; struct stm32_serial_device uart2 = { - USART2, - &uart2_int_rx, - RT_NULL + USART2, + &uart2_int_rx, + RT_NULL }; struct rt_device uart2_device; #endif @@ -68,9 +68,9 @@ struct stm32_serial_int_rx uart3_int_rx; struct stm32_serial_dma_tx uart3_dma_tx; struct stm32_serial_device uart3 = { - USART3, - &uart3_int_rx, - &uart3_dma_tx + USART3, + &uart3_int_rx, + &uart3_dma_tx }; struct rt_device uart3_device; #endif @@ -80,110 +80,110 @@ struct rt_device uart3_device; #define USART3_DR_Base 0x40004804 /* USART1_REMAP = 0 */ -#define UART1_GPIO_TX GPIO_Pin_9 -#define UART1_GPIO_RX GPIO_Pin_10 -#define UART1_GPIO GPIOA -#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 -#define UART1_TX_DMA DMA1_Channel4 -#define UART1_RX_DMA DMA1_Channel5 +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_GPIO GPIOA +#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 +#define UART1_TX_DMA DMA1_Channel4 +#define UART1_RX_DMA DMA1_Channel5 #if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL) -#define UART2_GPIO_TX GPIO_Pin_5 -#define UART2_GPIO_RX GPIO_Pin_6 -#define UART2_GPIO GPIOD -#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 +#define UART2_GPIO_TX GPIO_Pin_5 +#define UART2_GPIO_RX GPIO_Pin_6 +#define UART2_GPIO GPIOD +#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 #else /* for STM32F10X_HD */ /* USART2_REMAP = 0 */ -#define UART2_GPIO_TX GPIO_Pin_2 -#define UART2_GPIO_RX GPIO_Pin_3 -#define UART2_GPIO GPIOA -#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 -#define UART2_TX_DMA DMA1_Channel7 -#define UART2_RX_DMA DMA1_Channel6 +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_GPIO GPIOA +#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 +#define UART2_TX_DMA DMA1_Channel7 +#define UART2_RX_DMA DMA1_Channel6 #endif /* USART3_REMAP[1:0] = 00 */ -#define UART3_GPIO_RX GPIO_Pin_11 -#define UART3_GPIO_TX GPIO_Pin_10 -#define UART3_GPIO GPIOB -#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 -#define UART3_TX_DMA DMA1_Channel2 -#define UART3_RX_DMA DMA1_Channel3 +#define UART3_GPIO_RX GPIO_Pin_11 +#define UART3_GPIO_TX GPIO_Pin_10 +#define UART3_GPIO GPIOB +#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 +#define UART3_TX_DMA DMA1_Channel2 +#define UART3_RX_DMA DMA1_Channel3 /* USART6_REMAP = 0 */ -#define UART6_GPIO_TX GPIO_Pin_6 -#define UART6_GPIO_RX GPIO_Pin_7 -#define UART6_GPIO GPIOC -#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6 -//#define UART1_TX_DMA DMA1_Channel? -//#define UART1_RX_DMA DMA1_Channel? +#define UART6_GPIO_TX GPIO_Pin_6 +#define UART6_GPIO_RX GPIO_Pin_7 +#define UART6_GPIO GPIOC +#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6 +//#define UART1_TX_DMA DMA1_Channel? +//#define UART1_RX_DMA DMA1_Channel? static void RCC_Configuration(void) { #ifdef RT_USING_UART1 - /* Enable USART1 and GPIOA clocks */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); + /* Enable USART1 and GPIOA clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); #endif #ifdef RT_USING_UART6 - /* Enable USART6 and GPIOC clocks */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + /* Enable USART6 and GPIOC clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); #endif } static void GPIO_Configuration(void) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct; #ifdef RT_USING_UART1 - GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; - GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; + GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; + GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; + GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10; - GPIO_Init(GPIOA,&GPIO_InitStruct); + GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10; + GPIO_Init(GPIOA,&GPIO_InitStruct); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1); #endif #ifdef RT_USING_UART6 - GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; - GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; + GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; + GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; + GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX; - GPIO_Init(UART6_GPIO,&GPIO_InitStruct); + GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX; + GPIO_Init(UART6_GPIO,&GPIO_InitStruct); - GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6); - GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6); + GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6); + GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6); #endif } static void NVIC_Configuration(void) { - NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; #ifdef RT_USING_UART1 - /* Enable the USART1 Interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); #endif #ifdef RT_USING_UART6 - /* Enable the USART1 Interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); #endif } @@ -193,60 +193,60 @@ static void NVIC_Configuration(void) */ void rt_hw_usart_init() { - USART_InitTypeDef USART_InitStructure; + USART_InitTypeDef USART_InitStructure; - RCC_Configuration(); + RCC_Configuration(); - GPIO_Configuration(); + GPIO_Configuration(); - NVIC_Configuration(); + NVIC_Configuration(); - /* uart init */ + /* uart init */ #ifdef RT_USING_UART1 - USART_DeInit(USART1); - USART_InitStructure.USART_BaudRate = 115200; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No ; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_DeInit(USART1); + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART1, &USART_InitStructure); + USART_Init(USART1, &USART_InitStructure); - /* register uart1 */ - rt_hw_serial_register(&uart1_device, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart1); + /* register uart1 */ + rt_hw_serial_register(&uart1_device, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); - /* enable interrupt */ - USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); - /* Enable USART1 */ - USART_Cmd(USART1, ENABLE); - USART_ClearFlag(USART1,USART_FLAG_TXE); + /* enable interrupt */ + USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); + /* Enable USART1 */ + USART_Cmd(USART1, ENABLE); + USART_ClearFlag(USART1,USART_FLAG_TXE); #endif - /* uart init */ + /* uart init */ #ifdef RT_USING_UART6 - USART_DeInit(USART6); - USART_InitStructure.USART_BaudRate = 115200; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No ; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_DeInit(USART6); + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART6, &USART_InitStructure); + USART_Init(USART6, &USART_InitStructure); - /* register uart1 */ - rt_hw_serial_register(&uart6_device, "uart6", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart6); + /* register uart1 */ + rt_hw_serial_register(&uart6_device, "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); - /* enable interrupt */ - USART_ITConfig(USART6, USART_IT_RXNE, ENABLE); - /* Enable USART6 */ - USART_Cmd(USART6, ENABLE); - USART_ClearFlag(USART6,USART_FLAG_TXE); + /* enable interrupt */ + USART_ITConfig(USART6, USART_IT_RXNE, ENABLE); + /* Enable USART6 */ + USART_Cmd(USART6, ENABLE); + USART_ClearFlag(USART6,USART_FLAG_TXE); #endif } diff --git a/bsp/stm32f20x/Drivers/usart.h b/bsp/stm32f20x/Drivers/usart.h index 176c179e5b..76b64f96f8 100644 --- a/bsp/stm32f20x/Drivers/usart.h +++ b/bsp/stm32f20x/Drivers/usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32f20x/applications/application.c b/bsp/stm32f20x/applications/application.c index 4f37de7b30..04258d0ffd 100644 --- a/bsp/stm32f20x/applications/application.c +++ b/bsp/stm32f20x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32f20x/applications/startup.c b/bsp/stm32f20x/applications/startup.c index 92be9bd2ce..709a4bfb6d 100644 --- a/bsp/stm32f20x/applications/startup.c +++ b/bsp/stm32f20x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,11 +42,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(u8* file, u32 line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -55,58 +55,58 @@ void assert_failed(u8* file, u32 line) */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP #if STM32_EXT_SRAM - rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END); + rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END); #else - #if defined(__CC_ARM) || defined(__CLANG_ARM) - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END); - #endif + #if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END); + #endif #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/stm32f20x/project.ewp b/bsp/stm32f20x/project.ewp index 9bdc55d5c8..930a998d2b 100644 --- a/bsp/stm32f20x/project.ewp +++ b/bsp/stm32f20x/project.ewp @@ -145,10 +145,8 @@ <option>
<name>CCDefines</name>
<state />
+ <state>__RTTHREAD__</state>
<state>USE_STDPERIPH_DRIVER</state>
- <state>RT_USING_DLIBC</state>
- <state>_DLIB_FILE_DESCRIPTOR</state>
- <state>_DLIB_THREAD_SUPPORT</state>
</option>
<option>
<name>CCPreprocFile</name>
@@ -279,22 +277,18 @@ <name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
- <state>$PROJ_DIR$\applications</state>
- <state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
- <state>$PROJ_DIR$\..\..\components\finsh</state>
+ <state>$PROJ_DIR$\..\..\include</state>
+ <state>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx</state>
<state>$PROJ_DIR$\Drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\common</state>
- <state>$PROJ_DIR$\..\..\components\drivers\include</state>
+ <state>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc</state>
<state>$PROJ_DIR$\.</state>
- <state>$PROJ_DIR$\..\..\include</state>
+ <state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\Libraries\CMSIS\CM3\CoreSupport</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3</state>
+ <state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
- <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
- <state>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc</state>
- <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx</state>
- <state>$PROJ_DIR$\..\..\components\dfs\include</state>
+ <state>$PROJ_DIR$\..\..\components\finsh</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -1022,10 +1016,8 @@ <option>
<name>CCDefines</name>
<state>NDEBUG</state>
+ <state>__RTTHREAD__</state>
<state>USE_STDPERIPH_DRIVER</state>
- <state>RT_USING_DLIBC</state>
- <state>_DLIB_FILE_DESCRIPTOR</state>
- <state>_DLIB_THREAD_SUPPORT</state>
</option>
<option>
<name>CCPreprocFile</name>
@@ -1156,22 +1148,18 @@ <name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
- <state>$PROJ_DIR$\applications</state>
- <state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
- <state>$PROJ_DIR$\..\..\components\finsh</state>
+ <state>$PROJ_DIR$\..\..\include</state>
+ <state>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx</state>
<state>$PROJ_DIR$\Drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\common</state>
- <state>$PROJ_DIR$\..\..\components\drivers\include</state>
+ <state>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc</state>
<state>$PROJ_DIR$\.</state>
- <state>$PROJ_DIR$\..\..\include</state>
+ <state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\Libraries\CMSIS\CM3\CoreSupport</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3</state>
+ <state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
- <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
- <state>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\inc</state>
- <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx</state>
- <state>$PROJ_DIR$\..\..\components\dfs\include</state>
+ <state>$PROJ_DIR$\..\..\components\finsh</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -1755,363 +1743,279 @@ </settings>
</configuration>
<group>
- <name>Kernel</name>
+ <name>Applications</name>
<file>
- <name>$PROJ_DIR$\..\..\src\clock.c</name>
+ <name>$PROJ_DIR$\applications\startup.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\cpu.c</name>
+ <name>$PROJ_DIR$\applications\application.c</name>
</file>
+ </group>
+ <group>
+ <name>CPU</name>
<file>
- <name>$PROJ_DIR$\..\..\src\device.c</name>
+ <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\idle.c</name>
+ <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\ipc.c</name>
+ <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\irq.c</name>
+ <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\kservice.c</name>
+ <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
</file>
+ </group>
+ <group>
+ <name>DeviceDrivers</name>
<file>
- <name>$PROJ_DIR$\..\..\src\mem.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\misc\pin.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\mempool.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\rtc\rtc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\object.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\signal.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\thread.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\src\timer.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
</file>
- </group>
- <group>
- <name>Applications</name>
<file>
- <name>$PROJ_DIR$\applications\application.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\applications\startup.c</name>
+ <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name>
</file>
</group>
<group>
<name>Drivers</name>
<file>
- <name>$PROJ_DIR$\Drivers\24LCxx.c</name>
+ <name>$PROJ_DIR$\Drivers\stm32f2xx_it.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\FM25Lx.c</name>
+ <name>$PROJ_DIR$\Drivers\serial.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\board.c</name>
+ <name>$PROJ_DIR$\Drivers\24LCxx.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\drv_rtc.c</name>
+ <name>$PROJ_DIR$\Drivers\board.c</name>
</file>
<file>
<name>$PROJ_DIR$\Drivers\i2c.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\sdio_sd.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Drivers\serial.c</name>
+ <name>$PROJ_DIR$\Drivers\FM25Lx.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\stm32f2xx_it.c</name>
+ <name>$PROJ_DIR$\Drivers\usart.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Drivers\usart.c</name>
+ <name>$PROJ_DIR$\Drivers\drv_rtc.c</name>
</file>
</group>
<group>
- <name>STM32_StdPeriph</name>
- <file>
- <name>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c</name>
- </file>
+ <name>finsh</name>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\msh.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
</file>
<file>
- <name>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\iar\startup_stm32f2xx.s</name>
+ <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
</file>
</group>
<group>
- <name>cpu</name>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name>
- </file>
+ <name>Kernel</name>
<file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name>
+ <name>$PROJ_DIR$\..\..\src\timer.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name>
+ <name>$PROJ_DIR$\..\..\src\idle.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
+ <name>$PROJ_DIR$\..\..\src\ipc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
+ <name>$PROJ_DIR$\..\..\src\irq.c</name>
</file>
- </group>
- <group>
- <name>Filesystem</name>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\dfs.c</name>
+ <name>$PROJ_DIR$\..\..\src\kservice.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_file.c</name>
+ <name>$PROJ_DIR$\..\..\src\mempool.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c</name>
+ <name>$PROJ_DIR$\..\..\src\device.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name>
+ <name>$PROJ_DIR$\..\..\src\thread.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\poll.c</name>
+ <name>$PROJ_DIR$\..\..\src\components.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\src\select.c</name>
+ <name>$PROJ_DIR$\..\..\src\object.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c</name>
+ <name>$PROJ_DIR$\..\..\src\mem.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
+ <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name>
+ <name>$PROJ_DIR$\..\..\src\clock.c</name>
</file>
</group>
<group>
- <name>DeviceDrivers</name>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\misc\pin.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\rtc\rtc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
- </file>
+ <name>libc</name>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name>
+ <name>$PROJ_DIR$\..\..\components\libc\compilers\common\time.c</name>
</file>
+ </group>
+ <group>
+ <name>Libraries</name>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name>
- </file>
- </group>
- <group>
- <name>finsh</name>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\msh.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\msh_cmd.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\msh_file.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
+ <name>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c</name>
</file>
- </group>
- <group>
- <name>libc</name>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\common\gmtime_r.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c</name>
</file>
- </group>
- <group>
- <name>dlib</name>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c</name>
+ <name>$PROJ_DIR$\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\iar\startup_stm32f2xx.s</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\rmtx.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\components\libc\compilers\dlib\time.c</name>
+ <name>$PROJ_DIR$\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</name>
</file>
</group>
</project>
diff --git a/bsp/stm32f20x/project.uvproj b/bsp/stm32f20x/project.uvproj index 5424b2e029..debdfbaadd 100644 --- a/bsp/stm32f20x/project.uvproj +++ b/bsp/stm32f20x/project.uvproj @@ -7,6 +7,7 @@ <TargetName>RT-Thread STM32</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>STM32F207VG</Device> @@ -27,6 +28,7 @@ <SLE66AMisc /> <SLE66LinkerMisc /> <SFDFile>SFD\ST\STM32F2xx\STM32F2xx.sfr</SFDFile> + <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> <BinPath /> <IncludePath /> @@ -58,6 +60,8 @@ <UserProg2Name /> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> @@ -66,6 +70,8 @@ <UserProg2Name /> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> </BeforeMake> <AfterMake> <RunUserProg1>1</RunUserProg1> @@ -74,6 +80,8 @@ <UserProg2Name /> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> <SVCSIdString /> @@ -92,6 +100,7 @@ <StopOnExitCode>3</StopOnExitCode> <CustomArgument /> <IncludeLibraryModules /> + <ComprImg>1</ComprImg> </CommonProperty> <DllOption> <SimDllName>SARMCM3.DLL</SimDllName> @@ -121,6 +130,7 @@ <RestoreFunctions>1</RestoreFunctions> <RestoreToolbox>1</RestoreToolbox> <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + <RestoreSysVw>1</RestoreSysVw> </Simulator> <Target> <UseTarget>1</UseTarget> @@ -131,9 +141,11 @@ <RestoreMemoryDisplay>1</RestoreMemoryDisplay> <RestoreFunctions>0</RestoreFunctions> <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + <RestoreSysVw>1</RestoreSysVw> </Target> <RunDebugAfterBuild>0</RunDebugAfterBuild> - <TargetSelection>7</TargetSelection> + <TargetSelection>4</TargetSelection> <SimDlls> <CpuDll /> <CpuDllArguments /> @@ -159,9 +171,14 @@ <Capability>1</Capability> <DriverSelection>4099</DriverSelection> </Flash1> + <bUseTDR>0</bUseTDR> <Flash2>Segger\JL2CM3.dll</Flash2> <Flash3>"" ()</Flash3> <Flash4 /> + <pFcarmOut /> + <pFcarmGrp /> + <pFcArmRoot /> + <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> <ArmAdsMisc> @@ -208,6 +225,7 @@ <useUlib>0</useUlib> <EndSel>0</EndSel> <uLtcg>0</uLtcg> + <nSecure>0</nSecure> <RoSelD>3</RoSelD> <RwSelD>3</RwSelD> <CodeSel>0</CodeSel> @@ -331,7 +349,7 @@ <Optim>1</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> @@ -339,11 +357,22 @@ <Rwpi>0</Rwpi> <wLevel>0</wLevel> <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls /> - <Define>RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER</Define> + <Define>USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define> <Undefine /> - <IncludePath>.;..\..\include;applications;.;Drivers;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common</IncludePath> + <IncludePath>applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;Drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include</IncludePath> </VariousControls> </Cads> <Aads> @@ -354,6 +383,9 @@ <SplitLS>0</SplitLS> <SwStkChk>0</SwStkChk> <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> <VariousControls> <MiscControls /> <Define /> @@ -370,6 +402,7 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase /> <ScatterFile /> <IncludeLibs /> <IncludeLibsPath /> @@ -381,127 +414,123 @@ </TargetOption> <Groups> <Group> - <GroupName>Kernel</GroupName> - <Files> - <File> - <FileName>clock.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\clock.c</FilePath> - </File> - </Files> + <GroupName>Applications</GroupName> <Files> <File> - <FileName>components.c</FileName> + <FileName>application.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\components.c</FilePath> + <FilePath>applications\application.c</FilePath> </File> </Files> <Files> <File> - <FileName>cpu.c</FileName> + <FileName>startup.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\cpu.c</FilePath> + <FilePath>applications\startup.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> <Files> <File> - <FileName>device.c</FileName> + <FileName>div0.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\device.c</FilePath> + <FilePath>..\..\libcpu\arm\common\div0.c</FilePath> </File> </Files> <Files> <File> - <FileName>idle.c</FileName> + <FileName>showmem.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\idle.c</FilePath> + <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath> </File> </Files> <Files> <File> - <FileName>ipc.c</FileName> + <FileName>backtrace.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\ipc.c</FilePath> + <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> </File> </Files> <Files> <File> - <FileName>irq.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\irq.c</FilePath> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> </File> </Files> <Files> <File> - <FileName>kservice.c</FileName> + <FileName>cpuport.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\kservice.c</FilePath> + <FilePath>..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>DeviceDrivers</GroupName> <Files> <File> - <FileName>mem.c</FileName> + <FileName>pin.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mem.c</FilePath> + <FilePath>..\..\components\drivers\misc\pin.c</FilePath> </File> </Files> <Files> <File> - <FileName>mempool.c</FileName> + <FileName>rtc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mempool.c</FilePath> + <FilePath>..\..\components\drivers\rtc\rtc.c</FilePath> </File> </Files> <Files> <File> - <FileName>object.c</FileName> + <FileName>waitqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\object.c</FilePath> + <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath> </File> </Files> <Files> <File> - <FileName>scheduler.c</FileName> + <FileName>pipe.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\scheduler.c</FilePath> + <FilePath>..\..\components\drivers\src\pipe.c</FilePath> </File> </Files> <Files> <File> - <FileName>signal.c</FileName> + <FileName>dataqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\signal.c</FilePath> + <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath> </File> </Files> <Files> <File> - <FileName>thread.c</FileName> + <FileName>completion.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\thread.c</FilePath> + <FilePath>..\..\components\drivers\src\completion.c</FilePath> </File> </Files> <Files> <File> - <FileName>timer.c</FileName> + <FileName>ringbuffer.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\timer.c</FilePath> + <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> </File> </Files> - </Group> - <Group> - <GroupName>Applications</GroupName> <Files> <File> - <FileName>application.c</FileName> + <FileName>ringblk_buf.c</FileName> <FileType>1</FileType> - <FilePath>applications\application.c</FilePath> + <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> </File> </Files> <Files> <File> - <FileName>startup.c</FileName> + <FileName>workqueue.c</FileName> <FileType>1</FileType> - <FilePath>applications\startup.c</FilePath> + <FilePath>..\..\components\drivers\src\workqueue.c</FilePath> </File> </Files> </Group> @@ -509,16 +538,9 @@ <GroupName>Drivers</GroupName> <Files> <File> - <FileName>24LCxx.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\24LCxx.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>FM25Lx.c</FileName> + <FileName>serial.c</FileName> <FileType>1</FileType> - <FilePath>Drivers\FM25Lx.c</FilePath> + <FilePath>Drivers\serial.c</FilePath> </File> </Files> <Files> @@ -530,9 +552,9 @@ </Files> <Files> <File> - <FileName>drv_rtc.c</FileName> + <FileName>usart.c</FileName> <FileType>1</FileType> - <FilePath>Drivers\drv_rtc.c</FilePath> + <FilePath>Drivers\usart.c</FilePath> </File> </Files> <Files> @@ -544,16 +566,9 @@ </Files> <Files> <File> - <FileName>sdio_sd.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\sdio_sd.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>serial.c</FileName> + <FileName>FM25Lx.c</FileName> <FileType>1</FileType> - <FilePath>Drivers\serial.c</FilePath> + <FilePath>Drivers\FM25Lx.c</FilePath> </File> </Files> <Files> @@ -565,552 +580,448 @@ </Files> <Files> <File> - <FileName>usart.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\usart.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>STM32_StdPeriph</GroupName> - <Files> - <File> - <FileName>system_stm32f2xx.c</FileName> - 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<FileName>finsh_vm.c</FileName> + <FileName>stm32f2xx_sdio.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_vm.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c</FilePath> </File> </Files> <Files> <File> - <FileName>finsh_token.c</FileName> + <FileName>stm32f2xx_cryp_aes.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_token.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</FilePath> </File> </Files> - </Group> - <Group> - <GroupName>libc</GroupName> <Files> <File> - <FileName>libc.c</FileName> + <FileName>stm32f2xx_dbgmcu.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c</FilePath> </File> </Files> <Files> <File> - <FileName>mem_std.c</FileName> + <FileName>stm32f2xx_syscfg.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c</FilePath> </File> </Files> <Files> <File> - <FileName>stdio.c</FileName> + <FileName>stm32f2xx_iwdg.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stdio.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c</FilePath> </File> </Files> <Files> <File> - <FileName>stubs.c</FileName> + <FileName>stm32f2xx_i2c.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stubs.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c</FilePath> </File> </Files> <Files> <File> - <FileName>time.c</FileName> + <FileName>stm32f2xx_adc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\common\time.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</FilePath> </File> </Files> </Group> diff --git a/bsp/stm32f20x/project.uvprojx b/bsp/stm32f20x/project.uvprojx index 95caac5140..548fd7a663 100644 --- a/bsp/stm32f20x/project.uvprojx +++ b/bsp/stm32f20x/project.uvprojx @@ -1,39 +1,44 @@ <?xml version="1.0" encoding="UTF-8" standalone="no" ?> <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + <SchemaVersion>2.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> <Target> <TargetName>RT-Thread STM32</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>STM32F207VG</Device> <Vendor>STMicroelectronics</Vendor> - <PackID>Keil.STM32F2xx_DFP.2.0.0</PackID> + <PackID>Keil.STM32F2xx_DFP.2.9.0</PackID> <PackURL>http://www.keil.com/pack</PackURL> <Cpu>IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu> - <FlashUtilSpec /> - <StartupFile /> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207VGTx$CMSIS\Flash\STM32F2xx_1024.FLM))</FlashDriverDll> <DeviceId>0</DeviceId> <RegisterFile>$$Device:STM32F207VGTx$Drivers\CMSIS\Device\ST\STM32F2xx\Include\stm32f2xx.h</RegisterFile> - <MemoryEnv /> - <Cmp /> - <Asm /> - <Linker /> - <OHString /> - <InfinionOptionDll /> - <SLE66CMisc /> - <SLE66AMisc /> - <SLE66LinkerMisc /> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> <SFDFile>$$Device:STM32F207VGTx$CMSIS\SVD\STM32F20x.svd</SFDFile> <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> - <BinPath /> - <IncludePath /> - <LibPath /> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> <RegisterFilePath>ST\STM32F2xx\</RegisterFilePath> <DBRegisterFilePath>ST\STM32F2xx\</DBRegisterFilePath> <TargetStatus> @@ -49,7 +54,7 @@ <CreateLib>0</CreateLib> <CreateHexFile>0</CreateHexFile> <DebugInformation>1</DebugInformation> - <BrowseInformation>0</BrowseInformation> + <BrowseInformation>1</BrowseInformation> <ListingPath>.\build\</ListingPath> <HexFormatSelection>1</HexFormatSelection> <Merge32K>0</Merge32K> @@ -57,29 +62,35 @@ <BeforeCompile> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> </BeforeMake> <AfterMake> <RunUserProg1>1</RunUserProg1> <RunUserProg2>0</RunUserProg2> <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> - <UserProg2Name /> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString /> + <SVCSIdString></SVCSIdString> </TargetCommonOption> <CommonProperty> <UseCPPCompiler>0</UseCPPCompiler> @@ -93,8 +104,9 @@ <AssembleAssemblyFile>0</AssembleAssemblyFile> <PublicsOnly>0</PublicsOnly> <StopOnExitCode>3</StopOnExitCode> - <CustomArgument /> - <IncludeLibraryModules /> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> </CommonProperty> <DllOption> <SimDllName>SARMCM3.DLL</SimDllName> @@ -114,57 +126,24 @@ <HexOffset>0</HexOffset> <Oh166RecLen>16</Oh166RecLen> </OPTHX> - <Simulator> - <UseSimulator>0</UseSimulator> - <LoadApplicationAtStartup>1</LoadApplicationAtStartup> - <RunToMain>0</RunToMain> - <RestoreBreakpoints>1</RestoreBreakpoints> - <RestoreWatchpoints>1</RestoreWatchpoints> - <RestoreMemoryDisplay>1</RestoreMemoryDisplay> - <RestoreFunctions>1</RestoreFunctions> - <RestoreToolbox>1</RestoreToolbox> - <LimitSpeedToRealTime>0</LimitSpeedToRealTime> - </Simulator> - <Target> - <UseTarget>1</UseTarget> - <LoadApplicationAtStartup>1</LoadApplicationAtStartup> - <RunToMain>1</RunToMain> - <RestoreBreakpoints>1</RestoreBreakpoints> - <RestoreWatchpoints>1</RestoreWatchpoints> - <RestoreMemoryDisplay>1</RestoreMemoryDisplay> - <RestoreFunctions>0</RestoreFunctions> - <RestoreToolbox>1</RestoreToolbox> - </Target> - <RunDebugAfterBuild>0</RunDebugAfterBuild> - <TargetSelection>7</TargetSelection> - <SimDlls> - <CpuDll /> - <CpuDllArguments /> - <PeripheralDll /> - <PeripheralDllArguments /> - <InitializationFile /> - </SimDlls> - <TargetDlls> - <CpuDll /> - <CpuDllArguments /> - <PeripheralDll /> - <PeripheralDllArguments /> - <InitializationFile /> - <Driver>Segger\JL2CM3.dll</Driver> - </TargetDlls> </DebugOption> <Utilities> <Flash1> <UseTargetDll>1</UseTargetDll> <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> - <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> <Capability>1</Capability> <DriverSelection>4099</DriverSelection> </Flash1> + <bUseTDR>1</bUseTDR> <Flash2>Segger\JL2CM3.dll</Flash2> <Flash3>"" ()</Flash3> - <Flash4 /> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> <ArmAdsMisc> @@ -196,7 +175,7 @@ <RvctClst>0</RvctClst> <GenPPlst>0</GenPPlst> <AdsCpuType>"Cortex-M3"</AdsCpuType> - <RvctDeviceName /> + <RvctDeviceName></RvctDeviceName> <mOS>0</mOS> <uocRom>0</uocRom> <uocRam>0</uocRam> @@ -211,6 +190,7 @@ <useUlib>0</useUlib> <EndSel>0</EndSel> <uLtcg>0</uLtcg> + <nSecure>0</nSecure> <RoSelD>3</RoSelD> <RwSelD>3</RwSelD> <CodeSel>0</CodeSel> @@ -327,14 +307,14 @@ <Size>0x0</Size> </OCR_RVCT10> </OnChipMemories> - <RvctStartVector /> + <RvctStartVector></RvctStartVector> </ArmAdsMisc> <Cads> <interw>1</interw> <Optim>1</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> @@ -342,11 +322,22 @@ <Rwpi>0</Rwpi> <wLevel>0</wLevel> <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls /> - <Define>RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER</Define> - <Undefine /> - <IncludePath>.;..\..\include;applications;.;Drivers;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common</IncludePath> + <MiscControls></MiscControls> + <Define>USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define> + <Undefine></Undefine> + <IncludePath>applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;Drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;Libraries\STM32F2xx_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\CMSIS\CM3\CoreSupport;Libraries\CMSIS\Include</IncludePath> </VariousControls> </Cads> <Aads> @@ -357,11 +348,14 @@ <SplitLS>0</SplitLS> <SwStkChk>0</SwStkChk> <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> <VariousControls> - <MiscControls /> - <Define /> - <Undefine /> - <IncludePath /> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> </VariousControls> </Aads> <LDads> @@ -373,138 +367,109 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> - <ScatterFile /> - <IncludeLibs /> - <IncludeLibsPath /> - <Misc /> - <LinkerInputFile /> - <DisabledWarnings /> + <pXoBase></pXoBase> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> </LDads> </TargetArmAds> </TargetOption> <Groups> <Group> - <GroupName>Kernel</GroupName> + <GroupName>Applications</GroupName> <Files> <File> - <FileName>clock.c</FileName> + <FileName>startup.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\clock.c</FilePath> + <FilePath>applications\startup.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>components.c</FileName> + <FileName>application.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\components.c</FilePath> + <FilePath>applications\application.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> <Files> <File> - <FileName>cpu.c</FileName> + <FileName>div0.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\cpu.c</FilePath> + <FilePath>..\..\libcpu\arm\common\div0.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>device.c</FileName> + <FileName>backtrace.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\device.c</FilePath> + <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>idle.c</FileName> + <FileName>showmem.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\idle.c</FilePath> + <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>ipc.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\ipc.c</FilePath> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> </File> - </Files> - <Files> <File> - <FileName>irq.c</FileName> + <FileName>cpuport.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\irq.c</FilePath> + <FilePath>..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>DeviceDrivers</GroupName> <Files> <File> - <FileName>kservice.c</FileName> + <FileName>pin.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\kservice.c</FilePath> + <FilePath>..\..\components\drivers\misc\pin.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>mem.c</FileName> + <FileName>rtc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mem.c</FilePath> + <FilePath>..\..\components\drivers\rtc\rtc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>mempool.c</FileName> + <FileName>waitqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mempool.c</FilePath> + <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>object.c</FileName> + <FileName>dataqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\object.c</FilePath> + <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>scheduler.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\scheduler.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>signal.c</FileName> + <FileName>pipe.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\signal.c</FilePath> + <FilePath>..\..\components\drivers\src\pipe.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>thread.c</FileName> + <FileName>ringbuffer.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\thread.c</FilePath> + <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>timer.c</FileName> + <FileName>ringblk_buf.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\timer.c</FilePath> + <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> </File> - </Files> - </Group> - <Group> - <GroupName>Applications</GroupName> - <Files> <File> - <FileName>application.c</FileName> + <FileName>workqueue.c</FileName> <FileType>1</FileType> - <FilePath>applications\application.c</FilePath> + <FilePath>..\..\components\drivers\src\workqueue.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>startup.c</FileName> + <FileName>completion.c</FileName> <FileType>1</FileType> - <FilePath>applications\startup.c</FilePath> + <FilePath>..\..\components\drivers\src\completion.c</FilePath> </File> </Files> </Group> @@ -512,612 +477,375 @@ <GroupName>Drivers</GroupName> <Files> <File> - <FileName>24LCxx.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\24LCxx.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>FM25Lx.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\FM25Lx.c</FilePath> - </File> - </Files> - <Files> - <File> <FileName>board.c</FileName> <FileType>1</FileType> <FilePath>Drivers\board.c</FilePath> </File> - </Files> - <Files> - <File> - <FileName>drv_rtc.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\drv_rtc.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>i2c.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\i2c.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>sdio_sd.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\sdio_sd.c</FilePath> - </File> - </Files> - <Files> <File> <FileName>serial.c</FileName> <FileType>1</FileType> <FilePath>Drivers\serial.c</FilePath> </File> - </Files> - <Files> <File> <FileName>stm32f2xx_it.c</FileName> <FileType>1</FileType> <FilePath>Drivers\stm32f2xx_it.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>usart.c</FileName> - <FileType>1</FileType> - <FilePath>Drivers\usart.c</FilePath> - </File> - </Files> - </Group> - <Group> - <GroupName>STM32_StdPeriph</GroupName> - <Files> - <File> - <FileName>system_stm32f2xx.c</FileName> - <FileType>1</FileType> - <FilePath>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>misc.c</FileName> + <FileName>drv_rtc.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c</FilePath> + <FilePath>Drivers\drv_rtc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stm32f2xx_adc.c</FileName> + <FileName>FM25Lx.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</FilePath> + <FilePath>Drivers\FM25Lx.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stm32f2xx_can.c</FileName> + <FileName>usart.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c</FilePath> + <FilePath>Drivers\usart.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stm32f2xx_crc.c</FileName> + <FileName>i2c.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c</FilePath> + <FilePath>Drivers\i2c.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stm32f2xx_cryp.c</FileName> + <FileName>24LCxx.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c</FilePath> + <FilePath>Drivers\24LCxx.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>finsh</GroupName> <Files> <File> - <FileName>stm32f2xx_cryp_aes.c</FileName> + <FileName>finsh_node.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</FilePath> + <FilePath>..\..\components\finsh\finsh_node.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stm32f2xx_cryp_des.c</FileName> + <FileName>finsh_parser.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c</FilePath> + <FilePath>..\..\components\finsh\finsh_parser.c</FilePath> </File> - </Files> - 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<FilePath>..\..\components\finsh\finsh_token.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</FilePath> </File> - </Files> - </Group> - <Group> - <GroupName>libc</GroupName> - <Files> <File> - <FileName>libc.c</FileName> + <FileName>stm32f2xx_dbgmcu.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>mem_std.c</FileName> + <FileName>stm32f2xx_syscfg.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stdio.c</FileName> + <FileName>stm32f2xx_iwdg.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stdio.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>stubs.c</FileName> + <FileName>stm32f2xx_i2c.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\armlibc\stubs.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>time.c</FileName> + <FileName>stm32f2xx_adc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\libc\compilers\common\time.c</FilePath> + <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</FilePath> </File> </Files> </Group> </Groups> </Target> </Targets> + + <RTE> + <apis/> + <components/> + <files/> + </RTE> + </Project> diff --git a/bsp/stm32f20x/rtconfig.h b/bsp/stm32f20x/rtconfig.h index 8a2f3e4b6a..3790d931e7 100644 --- a/bsp/stm32f20x/rtconfig.h +++ b/bsp/stm32f20x/rtconfig.h @@ -16,8 +16,6 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG -#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -39,8 +37,9 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 #define ARCH_ARM +#define RT_USING_CPU_FFS #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 @@ -67,24 +66,6 @@ /* Device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 4 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_0 -#define RT_DFS_ELM_USE_LFN 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 1 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_DFS_ELM_REENTRANT -#define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -93,26 +74,22 @@ #define RT_USING_PIN #define RT_USING_RTC -/* Using WiFi */ - - /* Using USB */ /* POSIX layer and C standard library */ -#define RT_USING_LIBC -#define RT_USING_POSIX +#define RT_LIBC_USING_TIME /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -124,9 +101,6 @@ /* Utilities */ -/* ARM CMSIS */ - - /* RT-Thread online packages */ /* IoT - internet of things */ @@ -158,6 +132,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ @@ -166,7 +143,11 @@ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + #define SOC_STM32F2 #define RT_USING_UART1 +#define SOC_STM32F20X #endif diff --git a/bsp/stm32f20x/template.uvproj b/bsp/stm32f20x/template.uvproj index 79c48c556f..9458edbfa3 100644 --- a/bsp/stm32f20x/template.uvproj +++ b/bsp/stm32f20x/template.uvproj @@ -10,6 +10,7 @@ <TargetName>RT-Thread STM32</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>STM32F207VG</Device> @@ -30,6 +31,7 @@ <SLE66AMisc></SLE66AMisc> <SLE66LinkerMisc></SLE66LinkerMisc> <SFDFile>SFD\ST\STM32F2xx\STM32F2xx.sfr</SFDFile> + <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> <BinPath></BinPath> <IncludePath></IncludePath> @@ -61,6 +63,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> @@ -69,6 +73,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> </BeforeMake> <AfterMake> <RunUserProg1>1</RunUserProg1> @@ -77,6 +83,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> <SVCSIdString></SVCSIdString> @@ -95,6 +103,7 @@ <StopOnExitCode>3</StopOnExitCode> <CustomArgument></CustomArgument> <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> </CommonProperty> <DllOption> <SimDllName>SARMCM3.DLL</SimDllName> @@ -124,6 +133,7 @@ <RestoreFunctions>1</RestoreFunctions> <RestoreToolbox>1</RestoreToolbox> <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + <RestoreSysVw>1</RestoreSysVw> </Simulator> <Target> <UseTarget>1</UseTarget> @@ -134,9 +144,11 @@ <RestoreMemoryDisplay>1</RestoreMemoryDisplay> <RestoreFunctions>0</RestoreFunctions> <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + <RestoreSysVw>1</RestoreSysVw> </Target> <RunDebugAfterBuild>0</RunDebugAfterBuild> - <TargetSelection>7</TargetSelection> + <TargetSelection>4</TargetSelection> <SimDlls> <CpuDll></CpuDll> <CpuDllArguments></CpuDllArguments> @@ -162,9 +174,14 @@ <Capability>1</Capability> <DriverSelection>4099</DriverSelection> </Flash1> + <bUseTDR>0</bUseTDR> <Flash2>Segger\JL2CM3.dll</Flash2> <Flash3>"" ()</Flash3> <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> <ArmAdsMisc> @@ -211,6 +228,7 @@ <useUlib>0</useUlib> <EndSel>0</EndSel> <uLtcg>0</uLtcg> + <nSecure>0</nSecure> <RoSelD>3</RoSelD> <RwSelD>3</RwSelD> <CodeSel>0</CodeSel> @@ -334,7 +352,7 @@ <Optim>1</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> @@ -342,6 +360,17 @@ <Rwpi>0</Rwpi> <wLevel>0</wLevel> <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -357,6 +386,9 @@ <SplitLS>0</SplitLS> <SwStkChk>0</SwStkChk> <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -373,6 +405,7 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> <ScatterFile></ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> diff --git a/bsp/stm32f20x/template.uvprojx b/bsp/stm32f20x/template.uvprojx index 5f9e741955..fef2f8964c 100644 --- a/bsp/stm32f20x/template.uvprojx +++ b/bsp/stm32f20x/template.uvprojx @@ -10,11 +10,12 @@ <TargetName>RT-Thread STM32</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> + <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>STM32F207VG</Device> <Vendor>STMicroelectronics</Vendor> - <PackID>Keil.STM32F2xx_DFP.2.0.0</PackID> + <PackID>Keil.STM32F2xx_DFP.2.9.0</PackID> <PackURL>http://www.keil.com/pack</PackURL> <Cpu>IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -64,6 +65,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> @@ -72,6 +75,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> </BeforeMake> <AfterMake> <RunUserProg1>1</RunUserProg1> @@ -80,6 +85,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> <SVCSIdString></SVCSIdString> @@ -98,6 +105,7 @@ <StopOnExitCode>3</StopOnExitCode> <CustomArgument></CustomArgument> <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> </CommonProperty> <DllOption> <SimDllName>SARMCM3.DLL</SimDllName> @@ -117,57 +125,24 @@ <HexOffset>0</HexOffset> <Oh166RecLen>16</Oh166RecLen> </OPTHX> - <Simulator> - <UseSimulator>0</UseSimulator> - <LoadApplicationAtStartup>1</LoadApplicationAtStartup> - <RunToMain>0</RunToMain> - <RestoreBreakpoints>1</RestoreBreakpoints> - <RestoreWatchpoints>1</RestoreWatchpoints> - <RestoreMemoryDisplay>1</RestoreMemoryDisplay> - <RestoreFunctions>1</RestoreFunctions> - <RestoreToolbox>1</RestoreToolbox> - <LimitSpeedToRealTime>0</LimitSpeedToRealTime> - </Simulator> - <Target> - <UseTarget>1</UseTarget> - <LoadApplicationAtStartup>1</LoadApplicationAtStartup> - <RunToMain>1</RunToMain> - <RestoreBreakpoints>1</RestoreBreakpoints> - <RestoreWatchpoints>1</RestoreWatchpoints> - <RestoreMemoryDisplay>1</RestoreMemoryDisplay> - <RestoreFunctions>0</RestoreFunctions> - <RestoreToolbox>1</RestoreToolbox> - </Target> - <RunDebugAfterBuild>0</RunDebugAfterBuild> - <TargetSelection>7</TargetSelection> - <SimDlls> - <CpuDll></CpuDll> - <CpuDllArguments></CpuDllArguments> - <PeripheralDll></PeripheralDll> - <PeripheralDllArguments></PeripheralDllArguments> - <InitializationFile></InitializationFile> - </SimDlls> - <TargetDlls> - <CpuDll></CpuDll> - <CpuDllArguments></CpuDllArguments> - <PeripheralDll></PeripheralDll> - <PeripheralDllArguments></PeripheralDllArguments> - <InitializationFile></InitializationFile> - <Driver>Segger\JL2CM3.dll</Driver> - </TargetDlls> </DebugOption> <Utilities> <Flash1> <UseTargetDll>1</UseTargetDll> <UseExternalTool>0</UseExternalTool> <RunIndependent>0</RunIndependent> - <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> <Capability>1</Capability> <DriverSelection>4099</DriverSelection> </Flash1> + <bUseTDR>1</bUseTDR> <Flash2>Segger\JL2CM3.dll</Flash2> <Flash3>"" ()</Flash3> <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> <ArmAdsMisc> @@ -214,6 +189,7 @@ <useUlib>0</useUlib> <EndSel>0</EndSel> <uLtcg>0</uLtcg> + <nSecure>0</nSecure> <RoSelD>3</RoSelD> <RwSelD>3</RwSelD> <CodeSel>0</CodeSel> @@ -337,7 +313,7 @@ <Optim>1</Optim> <oTime>0</oTime> <SplitLS>0</SplitLS> - <OneElfS>0</OneElfS> + <OneElfS>1</OneElfS> <Strict>0</Strict> <EnumInt>0</EnumInt> <PlainCh>0</PlainCh> @@ -345,6 +321,17 @@ <Rwpi>0</Rwpi> <wLevel>0</wLevel> <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -360,6 +347,9 @@ <SplitLS>0</SplitLS> <SwStkChk>0</SwStkChk> <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -376,6 +366,7 @@ <useFile>0</useFile> <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> <ScatterFile></ScatterFile> <IncludeLibs></IncludeLibs> <IncludeLibsPath></IncludeLibsPath> @@ -388,4 +379,10 @@ </Target> </Targets> + <RTE> + <apis/> + <components/> + <files/> + </RTE> + </Project> diff --git a/bsp/taihu/applications/application.c b/bsp/taihu/applications/application.c index fde951b663..ed1f5aceb9 100644 --- a/bsp/taihu/applications/application.c +++ b/bsp/taihu/applications/application.c @@ -1,20 +1,16 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-04-16 first version + * 2011-04-16 first version */ #include <rtthread.h> -#define THREAD_STACK_SIZE 1024 +#define THREAD_STACK_SIZE 1024 #if 0 struct rt_semaphore sem1, sem2; @@ -27,44 +23,44 @@ static rt_uint8_t thread2_stack[THREAD_STACK_SIZE]; static void thread1_entry(void* parameter) { - while (1) - { - rt_sem_release(&sem2); - rt_kprintf("thread1..: %s\n", rt_thread_self()->name); - rt_sem_take(&sem1, RT_WAITING_FOREVER); - rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name); - } + while (1) + { + rt_sem_release(&sem2); + rt_kprintf("thread1..: %s\n", rt_thread_self()->name); + rt_sem_take(&sem1, RT_WAITING_FOREVER); + rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name); + } } static void thread2_entry(void* parameter) { - while (1) - { - rt_sem_take(&sem2, RT_WAITING_FOREVER); - rt_kprintf("thread2--->: %s\n", rt_thread_self()->name); - rt_sem_release(&sem1); - } + while (1) + { + rt_sem_take(&sem2, RT_WAITING_FOREVER); + rt_kprintf("thread2--->: %s\n", rt_thread_self()->name); + rt_sem_release(&sem1); + } } /* user application */ int rt_application_init() { - rt_err_t result; + rt_err_t result; - rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO); - result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), 10, 10); - if (result == RT_EOK) - rt_thread_startup(&thread1); + result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), 10, 10); + if (result == RT_EOK) + rt_thread_startup(&thread1); - result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL, - &thread2_stack[0], sizeof(thread2_stack), 18, 10); - if (result == RT_EOK) - rt_thread_startup(&thread2); + result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL, + &thread2_stack[0], sizeof(thread2_stack), 18, 10); + if (result == RT_EOK) + rt_thread_startup(&thread2); - return 0; + return 0; } #else static struct rt_thread thread1; @@ -74,27 +70,27 @@ rt_timer_t ttimer; static void thread1_entry(void* parameter) { - rt_uint32_t count = 0; - while (1) - { - rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++); + rt_uint32_t count = 0; + while (1) + { + rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++); - rt_thread_delay(10); - } + rt_thread_delay(10); + } } /* user application */ int rt_application_init() { - rt_err_t result; + rt_err_t result; - result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, - &thread1_stack[0], sizeof(thread1_stack), 10, 10); + result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), 10, 10); - ttimer = &(thread1.thread_timer); - if (result == RT_EOK) - rt_thread_startup(&thread1); + ttimer = &(thread1.thread_timer); + if (result == RT_EOK) + rt_thread_startup(&thread1); - return 0; + return 0; } #endif diff --git a/bsp/taihu/applications/board.c b/bsp/taihu/applications/board.c index 507cc0ae22..83febe6e72 100644 --- a/bsp/taihu/applications/board.c +++ b/bsp/taihu/applications/board.c @@ -1,15 +1,11 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-04-16 first version + * 2011-04-16 first version */ #include <rtthread.h> @@ -19,6 +15,6 @@ void rt_hw_board_init() { - rt_hw_serial_init(); - rt_console_set_device("uart1"); + rt_hw_serial_init(); + rt_console_set_device("uart1"); } diff --git a/bsp/taihu/applications/board.h b/bsp/taihu/applications/board.h index 518084aca6..88c30a854c 100644 --- a/bsp/taihu/applications/board.h +++ b/bsp/taihu/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/taihu/applications/startup.c b/bsp/taihu/applications/startup.c index 9f7d9415b5..299a2867e6 100644 --- a/bsp/taihu/applications/startup.c +++ b/bsp/taihu/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,42 +29,42 @@ extern int __heap_end; */ void rtthread_startup(void) { - /* init hardware interrupt */ - rt_hw_interrupt_init(); + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* init board */ - rt_hw_board_init(); - rt_show_version(); + /* init board */ + rt_hw_board_init(); + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); - /* init memory system */ + /* init memory system */ #ifdef RT_USING_HEAP - rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end); + rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end); #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); #ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("uart1"); + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); #endif - /* init soft timer thread */ - rt_system_timer_thread_init(); + /* init soft timer thread */ + rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } diff --git a/bsp/taihu/rtconfig.h b/bsp/taihu/rtconfig.h index 0ca8b43a19..4878a6858f 100644 --- a/bsp/taihu/rtconfig.h +++ b/bsp/taihu/rtconfig.h @@ -3,19 +3,19 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 -#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_THREAD_PRIORITY_MAX 32 +#define IDLE_THREAD_STACK_SIZE 1024 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* CPU Frequency 200MHz */ -#define RT_CPU_FREQ 200 +#define RT_CPU_FREQ 200 /* SECTION: RT_DEBUG */ /* open debug for system assert */ @@ -59,12 +59,12 @@ /* Using Device System*/ #define RT_USING_DEVICE #define RT_USING_UART1 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -85,34 +85,34 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/components/drivers/spi/sfud/src/sfud.c b/components/drivers/spi/sfud/src/sfud.c index e5b03131ff..4078179262 100644 --- a/components/drivers/spi/sfud/src/sfud.c +++ b/components/drivers/spi/sfud/src/sfud.c @@ -218,7 +218,7 @@ sfud_err sfud_qspi_fast_read_enable(sfud_flash *flash, uint8_t data_line_width) break; case 2: if (read_mode & DUAL_IO) { - qspi_set_read_cmd_format(flash, SFUD_CMD_DUAL_IO_READ_DATA, 1, 2, 8, 2); + qspi_set_read_cmd_format(flash, SFUD_CMD_DUAL_IO_READ_DATA, 1, 2, 4, 2); } else if (read_mode & DUAL_OUTPUT) { qspi_set_read_cmd_format(flash, SFUD_CMD_DUAL_OUTPUT_READ_DATA, 1, 1, 8, 2); } else { diff --git a/components/libc/compilers/common/time.c b/components/libc/compilers/common/time.c index 286a173347..83b6ed5672 100644 --- a/components/libc/compilers/common/time.c +++ b/components/libc/compilers/common/time.c @@ -21,11 +21,15 @@ #include <sys/time.h> #include <rtthread.h> -#include <rtdbg.h> + #ifdef RT_USING_DEVICE #include <rtdevice.h> #endif +#define DBG_TAG "TIME" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + /* seconds per day */ #define SPD 24*60*60 diff --git a/components/libc/pthreads/pthread.c b/components/libc/pthreads/pthread.c index 8a728c4e99..79104d1fd5 100644 --- a/components/libc/pthreads/pthread.c +++ b/components/libc/pthreads/pthread.c @@ -209,6 +209,8 @@ int pthread_create(pthread_t *pid, /* get pthread data */ ptd = _pthread_get_data(pth_id); + RT_ASSERT(ptd != RT_NULL); + if (attr != RT_NULL) { ptd->attr = *attr; @@ -299,6 +301,12 @@ int pthread_detach(pthread_t thread) { int ret = 0; _pthread_data_t *ptd = _pthread_get_data(thread); + if (ptd == RT_NULL) + { + /* invalid pthread id */ + ret = EINVAL; + goto __exit; + } rt_enter_critical(); if (ptd->attr.detachstate == PTHREAD_CREATE_DETACHED) @@ -360,6 +368,12 @@ int pthread_join(pthread_t thread, void **value_ptr) rt_err_t result; ptd = _pthread_get_data(thread); + + if (ptd == RT_NULL) + { + return EINVAL; /* invalid pthread id */ + } + if (ptd && ptd->tid == rt_thread_self()) { /* join self */ @@ -367,7 +381,9 @@ int pthread_join(pthread_t thread, void **value_ptr) } if (ptd->attr.detachstate == PTHREAD_CREATE_DETACHED) + { return EINVAL; /* join on a detached pthread */ + } result = rt_sem_take(ptd->joinable_sem, RT_WAITING_FOREVER); if (result == RT_EOK) @@ -662,7 +678,10 @@ int pthread_cancel(pthread_t thread) /* get posix thread data */ ptd = _pthread_get_data(thread); - RT_ASSERT(ptd != RT_NULL); + if (ptd == RT_NULL) + { + return EINVAL; + } /* cancel self */ if (ptd->tid == rt_thread_self()) diff --git a/components/net/lwip-2.0.2/src/apps/tftp/tftp_port.c b/components/net/lwip-2.0.2/src/apps/tftp/tftp_port.c index 129cc7da17..e14e34cfec 100644 --- a/components/net/lwip-2.0.2/src/apps/tftp/tftp_port.c +++ b/components/net/lwip-2.0.2/src/apps/tftp/tftp_port.c @@ -1,21 +1,7 @@ /* - * File : tftp_port.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/net/lwip-2.1.2/src/apps/tftp/tftp_port.c b/components/net/lwip-2.1.2/src/apps/tftp/tftp_port.c index 129cc7da17..e14e34cfec 100644 --- a/components/net/lwip-2.1.2/src/apps/tftp/tftp_port.c +++ b/components/net/lwip-2.1.2/src/apps/tftp/tftp_port.c @@ -1,21 +1,7 @@ /* - * File : tftp_port.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h index 4350890544..77fb4de8a2 100644 --- a/libcpu/aarch64/common/armv8.h +++ b/libcpu/aarch64/common/armv8.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,47 +14,47 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long long pc; - unsigned long long spsr; - unsigned long long x30; - unsigned long long xz; - unsigned long long x28; - unsigned long long x29; - unsigned long long x26; - unsigned long long x27; - unsigned long long x24; - unsigned long long x25; - unsigned long long x22; - unsigned long long x23; - unsigned long long x20; - unsigned long long x21; - unsigned long long x18; - unsigned long long x19; - unsigned long long x16; - unsigned long long x17; - unsigned long long x14; - unsigned long long x15; - unsigned long long x12; - unsigned long long x13; - unsigned long long x10; - unsigned long long x11; - unsigned long long x8; - unsigned long long x9; - unsigned long long x6; - unsigned long long x7; - unsigned long long x4; - unsigned long long x5; - unsigned long long x2; - unsigned long long x3; - unsigned long long x0; - unsigned long long x1; + unsigned long long pc; + unsigned long long spsr; + unsigned long long x30; + unsigned long long xz; + unsigned long long x28; + unsigned long long x29; + unsigned long long x26; + unsigned long long x27; + unsigned long long x24; + unsigned long long x25; + unsigned long long x22; + unsigned long long x23; + unsigned long long x20; + unsigned long long x21; + unsigned long long x18; + unsigned long long x19; + unsigned long long x16; + unsigned long long x17; + unsigned long long x14; + unsigned long long x15; + unsigned long long x12; + unsigned long long x13; + unsigned long long x10; + unsigned long long x11; + unsigned long long x8; + unsigned long long x9; + unsigned long long x6; + unsigned long long x7; + unsigned long long x4; + unsigned long long x5; + unsigned long long x2; + unsigned long long x3; + unsigned long long x0; + unsigned long long x1; }; -#define SP_ELx ( ( unsigned long long ) 0x01 ) -#define SP_EL0 ( ( unsigned long long ) 0x00 ) -#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) -#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) -#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) +#define SP_ELx ( ( unsigned long long ) 0x01 ) +#define SP_EL0 ( ( unsigned long long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) rt_ubase_t rt_hw_get_current_el(void); void rt_hw_set_elx_env(void); diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h index f3ffd6f857..e6d8626ab9 100644 --- a/libcpu/aarch64/common/cp15.h +++ b/libcpu/aarch64/common/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector) static inline void setup_bootstrap_addr(int cpu, int addr) { - CORE_MAILBOX3_SET(cpu) = addr; + CORE_MAILBOX3_SET(cpu) = addr; } static inline void enable_cpu_ipi_intr(int cpu) @@ -65,7 +65,7 @@ static inline void enable_cpu_ipi_intr(int cpu) static inline void enable_cpu_timer_intr(int cpu) { - CORETIMER_INTCTL(cpu) = 0x8; + CORETIMER_INTCTL(cpu) = 0x8; } static inline void enable_cntv(void) diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c index 84d3df2e8a..66b540a5e5 100644 --- a/libcpu/aarch64/common/cpu.c +++ b/libcpu/aarch64/common/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c index 1f4d868636..ec690a1cc6 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.c +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h index fa20846ea2..9ca4835b9a 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.h +++ b/libcpu/aarch64/common/gic/gic_pl400.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c index b799143084..2a41c4f813 100644 --- a/libcpu/aarch64/common/mmu.c +++ b/libcpu/aarch64/common/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -52,7 +52,7 @@ void mmu_memset(char *dst, char v, size_t len) } static unsigned long __page_off = 0; -static unsigned long get_free_page(void) +static unsigned long get_free_page(void) { __page_off += 512; return (unsigned long)(main_tbl + __page_off); @@ -128,7 +128,7 @@ void mmu_enable(void) } -static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) +static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { int level; unsigned long* cur_lv_tbl = lv0_tbl; @@ -136,22 +136,22 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned unsigned long off; int level_shift = 39; - if (va & (0x200000UL - 1)) + if (va & (0x200000UL - 1)) { return MMU_MAP_ERROR_VANOTALIGN; } - if (pa & (0x200000UL - 1)) + if (pa & (0x200000UL - 1)) { return MMU_MAP_ERROR_PANOTALIGN; } - for (level = 0; level < 2; level++) + for (level = 0; level < 2; level++) { off = (va >> level_shift); off &= MMU_LEVEL_MASK; - if ((cur_lv_tbl[off] & 1) == 0) + if ((cur_lv_tbl[off] & 1) == 0) { page = get_free_page(); - if (!page) + if (!page) { return MMU_MAP_ERROR_NOPAGE; } @@ -159,7 +159,7 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned cur_lv_tbl[off] = page | 0x3UL; } page = cur_lv_tbl[off]; - if (!(page & 0x2)) + if (!(page & 0x2)) { //is block! error! return MMU_MAP_ERROR_CONFLICT; @@ -239,8 +239,8 @@ static int level2shift(int level) static uint64_t *get_level_table(uint64_t *pte) { uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK); - - if (pte_type(pte) != PMD_TYPE_TABLE) + + if (pte_type(pte) != PMD_TYPE_TABLE) { table = create_table(); set_table(pte, table); @@ -259,10 +259,10 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att int level = 0; addr = virt; - while (size) + while (size) { table = &main_tbl[0]; - for (level = 0; level < 4; level++) + for (level = 0; level < 4; level++) { block_shift = level2shift(level); idx = addr >> block_shift; @@ -270,7 +270,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att block_size = (uint64_t)(1L << block_shift); pte = table + idx; - if (size >= block_size && IS_ALIGNED(addr, block_size)) + if (size >= block_size && IS_ALIGNED(addr, block_size)) { attr &= 0xfff0000000000ffcUL; if(level != 3) @@ -298,7 +298,7 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned void rt_hw_dcache_enable(void) { - if (!(get_sctlr() & CR_M)) + if (!(get_sctlr() & CR_M)) { rt_kprintf("please init mmu!\n"); } @@ -364,4 +364,4 @@ void rt_hw_icache_invalidate_all(void) void rt_hw_icache_disable(void) { set_sctlr(get_sctlr() & ~CR_I); -}
\ No newline at end of file +} diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h index 6a66472c79..f3261c3a1d 100644 --- a/libcpu/aarch64/common/mmu.h +++ b/libcpu/aarch64/common/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c index a412ca1953..4a5d502a3c 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.c +++ b/libcpu/aarch64/cortex-a53/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018/5/3 Bernard first version * 2019-07-28 zdzn add smp support - * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi */ @@ -160,15 +160,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) } if(cpu_mask & 0x2) { - send_ipi_msg(1, ipi_vector); + send_ipi_msg(1, ipi_vector); } if(cpu_mask & 0x4) { - send_ipi_msg(2, ipi_vector); + send_ipi_msg(2, ipi_vector); } if(cpu_mask & 0x8) { - send_ipi_msg(3, ipi_vector); + send_ipi_msg(3, ipi_vector); } __DSB(); } diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h index 8e741ed4e6..94a455550d 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.h +++ b/libcpu/aarch64/cortex-a53/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c index 68222c2c67..751793d7a3 100644 --- a/libcpu/aarch64/cortex-a53/stack.c +++ b/libcpu/aarch64/cortex-a53/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,70 +21,70 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_ubase_t *stk; - rt_ubase_t current_el; + rt_ubase_t *stk; + rt_ubase_t current_el; - stk = (rt_ubase_t*)stack_addr; + stk = (rt_ubase_t*)stack_addr; - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ - *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ - *(--stk) = ( rt_ubase_t ) 11; /* X11 */ - *(--stk) = ( rt_ubase_t ) 10; /* X10 */ - *(--stk) = ( rt_ubase_t ) 13; /* X13 */ - *(--stk) = ( rt_ubase_t ) 12; /* X12 */ - *(--stk) = ( rt_ubase_t ) 15; /* X15 */ - *(--stk) = ( rt_ubase_t ) 14; /* X14 */ - *(--stk) = ( rt_ubase_t ) 17; /* X17 */ - *(--stk) = ( rt_ubase_t ) 16; /* X16 */ - *(--stk) = ( rt_ubase_t ) 19; /* X19 */ - *(--stk) = ( rt_ubase_t ) 18; /* X18 */ - *(--stk) = ( rt_ubase_t ) 21; /* X21 */ - *(--stk) = ( rt_ubase_t ) 20; /* X20 */ - *(--stk) = ( rt_ubase_t ) 23; /* X23 */ - *(--stk) = ( rt_ubase_t ) 22; /* X22 */ - *(--stk) = ( rt_ubase_t ) 25; /* X25 */ - *(--stk) = ( rt_ubase_t ) 24; /* X24 */ - *(--stk) = ( rt_ubase_t ) 27; /* X27 */ - *(--stk) = ( rt_ubase_t ) 26; /* X26 */ - *(--stk) = ( rt_ubase_t ) 29; /* X29 */ - *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ - *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ - current_el = rt_hw_get_current_el(); + current_el = rt_hw_get_current_el(); - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } - *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c index 41d4d620f6..d43e0e4d6a 100644 --- a/libcpu/aarch64/cortex-a53/trap.c +++ b/libcpu/aarch64/cortex-a53/trap.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Date Author Notes * 2018-10-06 ZhaoXiaowei the first version */ @@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("Execption:\n"); rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); } /** @@ -57,7 +57,7 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs) } #define GIC_ACK_INTID_MASK (0x000003ff) -#define CORE0_IRQ_SOURCE (0x40000060) +#define CORE0_IRQ_SOURCE (0x40000060) void rt_hw_trap_irq(void) { diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c index 3b689dceb3..3ecb7750ad 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.c +++ b/libcpu/aarch64/cortex-a72/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h index 0d2d4867c7..72e69bd808 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.h +++ b/libcpu/aarch64/cortex-a72/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c index 68222c2c67..751793d7a3 100644 --- a/libcpu/aarch64/cortex-a72/stack.c +++ b/libcpu/aarch64/cortex-a72/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,70 +21,70 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_ubase_t *stk; - rt_ubase_t current_el; + rt_ubase_t *stk; + rt_ubase_t current_el; - stk = (rt_ubase_t*)stack_addr; + stk = (rt_ubase_t*)stack_addr; - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ - *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ - *(--stk) = ( rt_ubase_t ) 11; /* X11 */ - *(--stk) = ( rt_ubase_t ) 10; /* X10 */ - *(--stk) = ( rt_ubase_t ) 13; /* X13 */ - *(--stk) = ( rt_ubase_t ) 12; /* X12 */ - *(--stk) = ( rt_ubase_t ) 15; /* X15 */ - *(--stk) = ( rt_ubase_t ) 14; /* X14 */ - *(--stk) = ( rt_ubase_t ) 17; /* X17 */ - *(--stk) = ( rt_ubase_t ) 16; /* X16 */ - *(--stk) = ( rt_ubase_t ) 19; /* X19 */ - *(--stk) = ( rt_ubase_t ) 18; /* X18 */ - *(--stk) = ( rt_ubase_t ) 21; /* X21 */ - *(--stk) = ( rt_ubase_t ) 20; /* X20 */ - *(--stk) = ( rt_ubase_t ) 23; /* X23 */ - *(--stk) = ( rt_ubase_t ) 22; /* X22 */ - *(--stk) = ( rt_ubase_t ) 25; /* X25 */ - *(--stk) = ( rt_ubase_t ) 24; /* X24 */ - *(--stk) = ( rt_ubase_t ) 27; /* X27 */ - *(--stk) = ( rt_ubase_t ) 26; /* X26 */ - *(--stk) = ( rt_ubase_t ) 29; /* X29 */ - *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ - *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ - current_el = rt_hw_get_current_el(); + current_el = rt_hw_get_current_el(); - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } - *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c index d93aa18fd6..bd76f7717b 100644 --- a/libcpu/aarch64/cortex-a72/trap.c +++ b/libcpu/aarch64/cortex-a72/trap.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Date Author Notes * 2018-10-06 ZhaoXiaowei the first version */ @@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("Execption:\n"); rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); } /** @@ -64,7 +64,7 @@ void rt_hw_interrupt_ack(int fiq_irq); void rt_hw_trap_irq(void) { void *param; - int ir; + int ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c index 1a2593644a..d3bd8af6fe 100644 --- a/libcpu/arc/em/cpuport.c +++ b/libcpu/arc/em/cpuport.c @@ -22,11 +22,11 @@ rt_uint32_t rt_interrupt_to_thread; rt_uint32_t exc_nest_count; struct init_stack_frame { - rt_uint32_t pc; - rt_uint32_t blink; - rt_uint32_t task; - rt_uint32_t status32; - rt_uint32_t r0; + rt_uint32_t pc; + rt_uint32_t blink; + rt_uint32_t task; + rt_uint32_t status32; + rt_uint32_t r0; }; /** @@ -55,7 +55,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stack_frame->blink = (rt_uint32_t)texit; stack_frame->task = (rt_uint32_t)tentry; stack_frame->status32 = ARC_INIT_STATUS; - stack_frame->r0 = (rt_uint32_t)parameter; + stack_frame->r0 = (rt_uint32_t)parameter; return stk; } @@ -74,14 +74,14 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to) { struct rt_thread *rt_thread_to; - if (to != NULL) { + if (to != NULL) { rt_thread_to = rt_container_of(to, struct rt_thread, sp); #if ARC_FEATURE_SEC_PRESENT - arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); - arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); + arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); #else - arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); - arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); + arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); #endif - } + } } diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 130f9074d1..91b57053da 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,276 +15,276 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ /******************************************************************************/ /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ /******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c index b24ab5644b..18d8d6208a 100644 --- a/libcpu/arm/AT91SAM7S/cpu.c +++ b/libcpu/arm/AT91SAM7S/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index db9d31fe28..e4aa8643f1 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include <rtthread.h> #include "AT91SAM7S.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -53,11 +53,11 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_AIC_ICCR = 1 << vector; } /** @@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_AIC_IECR = 1 << vector; + AT91C_AIC_IECR = 1 << vector; } /** @@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); - if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); + if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; + } } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index adbe8609d6..583443f4cb 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,46 +22,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -72,312 +72,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; - if (irqno == AT91C_ID_US0) - { + if (irqno == AT91C_ID_US0) + { #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - } - else if (irqno == AT91C_ID_US1) - { + } + else if (irqno == AT91C_ID_US1) + { #ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; + /* serial 2 */ + serial = &serial2; #endif - } - RT_ASSERT(serial != RT_NULL); + } + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; + device = (rt_device_t) &serial2; - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 0937e92f6c..7766053a7f 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,48 +17,48 @@ #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address #endif -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ #endif diff --git a/libcpu/arm/AT91SAM7S/stack.c b/libcpu/arm/AT91SAM7S/stack.c index 6f8bd13bf9..23fce8e6e2 100644 --- a/libcpu/arm/AT91SAM7S/stack.c +++ b/libcpu/arm/AT91SAM7S/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7S/trap.c b/libcpu/arm/AT91SAM7S/trap.c index 208e568950..aa9df7c74b 100644 --- a/libcpu/arm/AT91SAM7S/trap.c +++ b/libcpu/arm/AT91SAM7S/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ void rt_hw_trap_irq() { - rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; + rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; - hander(AT91C_AIC_ISR); + hander(AT91C_AIC_ISR); - /* end of interrupt */ - AT91C_AIC_EOICR = 0; + /* end of interrupt */ + AT91C_AIC_EOICR = 0; } void rt_hw_trap_fiq() diff --git a/libcpu/arm/AT91SAM7X/cpu.c b/libcpu/arm/AT91SAM7X/cpu.c index 046f7e8ced..ffa4092900 100644 --- a/libcpu/arm/AT91SAM7X/cpu.c +++ b/libcpu/arm/AT91SAM7X/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/interrupt.c b/libcpu/arm/AT91SAM7X/interrupt.c index 0c37f63ada..3a28f507ca 100644 --- a/libcpu/arm/AT91SAM7X/interrupt.c +++ b/libcpu/arm/AT91SAM7X/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "AT91SAM7X256.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; + rt_base_t index; /* init exceptions table */ for(index=0; index < MAX_HANDLERS; index++) @@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void) irq_desc[index].param = RT_NULL; } - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_BASE_AIC->AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_BASE_AIC->AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_BASE_AIC->AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_BASE_AIC->AIC_ICCR = 1 << vector; } /** @@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_BASE_AIC->AIC_IECR = 1 << vector; + AT91C_BASE_AIC->AIC_IECR = 1 << vector; } /** @@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - } - } + rt_isr_handler_t old_handler = RT_NULL; + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/stack.c b/libcpu/arm/AT91SAM7X/stack.c index ef60b1a760..caa4826014 100644 --- a/libcpu/arm/AT91SAM7X/stack.c +++ b/libcpu/arm/AT91SAM7X/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 1c1c351ff8..3c012dd85e 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,17 +20,17 @@ void rt_hw_trap_irq(void) { - int irqno; - extern struct rt_irq_desc irq_desc[]; + int irqno; + extern struct rt_irq_desc irq_desc[]; - /* get interrupt number */ - irqno = AT91C_BASE_AIC->AIC_ISR; + /* get interrupt number */ + irqno = AT91C_BASE_AIC->AIC_ISR; - /* invoke isr with parameters */ - irq_desc[irqno].handler(irqno, irq_desc[irqno].param); + /* invoke isr with parameters */ + irq_desc[irqno].handler(irqno, irq_desc[irqno].param); - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; } void rt_hw_trap_fiq(void) @@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void) extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); - rt_schedule(); + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); + rt_schedule(); } /*@}*/ diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 99a65ac915..3112a8ac15 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,8 +9,8 @@ #ifndef __AM33XX_H__ #define __AM33XX_H__ -#define REG32(x) (*((volatile unsigned int *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned int *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) /** Cache Line size in ARM Cortex-A8. */ #define AM33XX_CACHELINE_SIZE (64) @@ -198,22 +198,22 @@ #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) /* timer registers */ -#define DMTIMER_TIDR(base) REG32(base + 0x0) -#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) -#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) -#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) -#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) -#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) -#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) -#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) -#define DMTIMER_TCLR(base) REG32(base + 0x38) -#define DMTIMER_TCRR(base) REG32(base + 0x3C) -#define DMTIMER_TLDR(base) REG32(base + 0x40) -#define DMTIMER_TTGR(base) REG32(base + 0x44) -#define DMTIMER_TWPS(base) REG32(base + 0x48) -#define DMTIMER_TMAR(base) REG32(base + 0x4C) -#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) -#define DMTIMER_TSICR(base) REG32(base + 0x54) +#define DMTIMER_TIDR(base) REG32(base + 0x0) +#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) +#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) +#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) +#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) +#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) +#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) +#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) +#define DMTIMER_TCLR(base) REG32(base + 0x38) +#define DMTIMER_TCRR(base) REG32(base + 0x3C) +#define DMTIMER_TLDR(base) REG32(base + 0x40) +#define DMTIMER_TTGR(base) REG32(base + 0x44) +#define DMTIMER_TWPS(base) REG32(base + 0x48) +#define DMTIMER_TMAR(base) REG32(base + 0x4C) +#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) +#define DMTIMER_TSICR(base) REG32(base + 0x54) #define EMU_INT 0 #define COMMTX_INT 1 @@ -317,33 +317,33 @@ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #endif diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c index 469276466b..19161a1817 100644 --- a/libcpu/arm/am335x/cpu.c +++ b/libcpu/arm/am335x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,74 +17,74 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #if defined(__CC_ARM) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #elif defined(__GNUC__) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } #endif @@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c index 3acd868496..c4c5e8d7eb 100644 --- a/libcpu/arm/am335x/interrupt.c +++ b/libcpu/arm/am335x/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #define AINTC_BASE AM33XX_AINTC_REGS -#define MAX_HANDLERS 128 +#define MAX_HANDLERS 128 extern volatile rt_uint8_t rt_interrupt_nest; @@ -59,13 +59,13 @@ extern int system_vectors; static void rt_hw_vector_init(void) { unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE; - + #ifdef __ICCARM__ unsigned int *src = (unsigned int *)&__vector; #else unsigned int *src = (unsigned int *)&system_vectors; #endif - + rt_memcpy(dest, src, 16 * 4); rt_cpu_vector_set_base(AM335X_VECTOR_BASE); } diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/am335x/interrupt.h +++ b/libcpu/arm/am335x/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c index babe825298..fbd886d0e6 100644 --- a/libcpu/arm/am335x/mmu.c +++ b/libcpu/arm/am335x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i); void mmu_disable_dcache() { - rt_cpu_dcache_disable(); + rt_cpu_dcache_disable(); } void mmu_enable_dcache() { - rt_hw_cpu_dcache_enable(); + rt_hw_cpu_dcache_enable(); } void mmu_disable_icache() { - rt_cpu_icache_disable(); + rt_cpu_icache_disable(); } void mmu_enable_icache() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } void mmu_disable() { - rt_cpu_mmu_disable(); + rt_cpu_mmu_disable(); } void mmu_enable() { - rt_cpu_mmu_enable(); + rt_cpu_mmu_enable(); } void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - rt_cpu_tlb_set(i); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + + rt_cpu_tlb_set(i); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } /* level1 page table */ @@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } @@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void) mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */ mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */ - mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ + mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ } void rt_hw_mmu_init(void) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); mmu_setmtts(); - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); /* enables MMU */ mmu_enable(); diff --git a/libcpu/arm/am335x/mmu.h b/libcpu/arm/am335x/mmu.h index 73635d3a0e..706d669844 100644 --- a/libcpu/arm/am335x/mmu.h +++ b/libcpu/arm/am335x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,27 +13,27 @@ #include <rtthread.h> -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ void rt_hw_mmu_init(void); diff --git a/libcpu/arm/am335x/stack.c b/libcpu/arm/am335x/stack.c index 1dad930818..db3cb37e73 100644 --- a/libcpu/arm/am335x/stack.c +++ b/libcpu/arm/am335x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/am335x/trap.c b/libcpu/arm/am335x/trap.c index b77543da64..7c73ce93d3 100644 --- a/libcpu/arm/am335x/trap.c +++ b/libcpu/arm/am335x/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,13 +36,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) return; #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) #ifdef RT_USING_GDB if (gdb_mem_fault_handler) { - regs->pc = (unsigned long)gdb_mem_fault_handler; + regs->pc = (unsigned long)gdb_mem_fault_handler; return; } #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } void rt_hw_trap_irq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_IRQ); + ir = rt_hw_interrupt_get_active(INT_IRQ); if (ir == 127) { /* new IRQ generation */ @@ -169,18 +169,18 @@ void rt_hw_trap_irq() if (isr_func != RT_NULL) isr_func(ir, param); - /* new IRQ generation */ + /* new IRQ generation */ rt_hw_interrupt_ack(INT_IRQ); } void rt_hw_trap_fiq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_FIQ); + ir = rt_hw_interrupt_get_active(INT_FIQ); /* get interrupt service routine */ isr_func = isr_table[ir].handler; @@ -189,7 +189,7 @@ void rt_hw_trap_fiq() /* turn to interrupt service routine */ isr_func(ir, param); - /* new FIQ generation */ + /* new FIQ generation */ rt_hw_interrupt_ack(INT_FIQ); } diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index dc93f42ed6..9148afa401 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c index aa26d10ec6..19baa4d9fe 100644 --- a/libcpu/arm/arm926/machine.c +++ b/libcpu/arm/arm926/machine.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c index 19d70b9b0b..50ada17f22 100644 --- a/libcpu/arm/arm926/mmu.c +++ b/libcpu/arm/arm926/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h index 36fdbeacd8..ecd39d4edf 100644 --- a/libcpu/arm/arm926/mmu.h +++ b/libcpu/arm/arm926/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c index f90bfa8c22..caf16c41bc 100644 --- a/libcpu/arm/arm926/stack.c +++ b/libcpu/arm/arm926/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index 9e7ba48037..c364b2addd 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/armv6.h b/libcpu/arm/armv6/armv6.h index 659ce90721..522c35845f 100644 --- a/libcpu/arm/armv6/armv6.h +++ b/libcpu/arm/armv6/armv6.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ - + #ifndef __ARMV6_H__ #define __ARMV6_H__ @@ -26,7 +26,7 @@ #ifndef __ASSEMBLY__ struct rt_hw_register { - rt_uint32_t cpsr; + rt_uint32_t cpsr; rt_uint32_t r0; rt_uint32_t r1; rt_uint32_t r2; @@ -46,24 +46,24 @@ struct rt_hw_register }; #if(0) struct rt_hw_register{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #endif #endif diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c index f886e7e164..6e82539c6e 100644 --- a/libcpu/arm/armv6/cpuport.c +++ b/libcpu/arm/armv6/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,32 +20,32 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } @@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit) #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -164,67 +164,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c index ae3cf73559..deb2f8365f 100644 --- a/libcpu/arm/armv6/mmu.c +++ b/libcpu/arm/armv6/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,411 +12,411 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } + value = 0x55555555; + __asm volatile + { + mcr p15, 0, value, c3, c0, 0 + mcr p15, 0, i, c2, c0, 0 + } } void mmu_set_domain(rt_uint32_t i) { - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } + __asm volatile + { + mcr p15,0, i, c3, c0, 0 + } } void mmu_enable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_clean_invalidated_cache_index(int index) { - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } + __asm volatile + { + mcr p15, 0, index, c7, c14, 2 + } } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } } void mmu_invalidate_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c5, 0 + } } void mmu_invalidate_dcache_all() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c6, 0 + } } #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - /* Enables the extended page tables to be configured for - the hardware page translation mechanism, Subpage AP bits disabled */ - i |= (1 << 23); /* support for ARMv6 MMU features */ - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + i |= 0x1; + /* Enables the extended page tables to be configured for + the hardware page translation mechanism, Subpage AP bits disabled */ + i |= (1 << 23); /* support for ARMv6 MMU features */ + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() { - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); } #endif @@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); * level2 page table * RT_MMU_PTE_SIZE must be 1024*n */ -#define RT_MMU_PTE_SIZE 4096 +#define RT_MMU_PTE_SIZE 4096 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); void mmu_create_pgd(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); + nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); + pTT++; + } } void mmu_create_pte(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; + volatile rt_uint32_t *pTT; + volatile rt_uint32_t *p_pteentry; + int i; + rt_uint32_t vaddr; + rt_uint32_t total_page = 0; + rt_uint32_t pte_offset = 0; + rt_uint32_t sect_attr = 0; - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; + total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; + pte_offset = mdesc->sect_attr & 0xfffffc00; + sect_attr = mdesc->sect_attr & 0x3ff; + vaddr = mdesc->vaddr_start; - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } + for(i = 0; i < total_page; i++) + { + pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); + if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ + { + *pTT = pte_offset | sect_attr; + p_pteentry = (rt_uint32_t *)pte_offset + + ((vaddr & 0x000ff000) >> 12); + pte_offset += 1024; + } + else /* using old Level 1 page table item */ + { + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + ((vaddr & 0x000ff000) >> 12); + } - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } + *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); + vaddr += 0x1000; + } } static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) { - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } + rt_uint32_t pte_offset = 0; + rt_uint32_t nsec = 0; + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == PAGE_MAPPED) + { + nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; + mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; + pte_offset += nsec << 10; + } + if (pte_offset >= RT_MMU_PTE_SIZE) + { + rt_kprintf("PTE table size too little\n"); + RT_ASSERT(0); + } - mdesc++; - } + mdesc++; + } } void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } + /* clear pgd and pte table */ + rt_memset((void *)_pgd_table, 0, 16*1024); + rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); + build_pte_mem_desc(mdesc, size); + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == SECT_MAPPED) + { + mmu_create_pgd(mdesc); + } + else + { + mmu_create_pte(mdesc); + } - mdesc++; - } + mdesc++; + } - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_pgd_table); - /* enables MMU */ - mmu_enable(); + /* enables MMU */ + mmu_enable(); - /* enable Instruction Cache */ - mmu_enable_icache(); + /* enable Instruction Cache */ + mmu_enable_icache(); - /* enable Data Cache */ - mmu_enable_dcache(); + /* enable Data Cache */ + mmu_enable_dcache(); - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); } diff --git a/libcpu/arm/armv6/mmu.h b/libcpu/arm/armv6/mmu.h index 4df61ac21d..18355378bd 100644 --- a/libcpu/arm/armv6/mmu.h +++ b/libcpu/arm/armv6/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -155,35 +155,35 @@ #define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; #define SECT_MAPPED 0 #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/armv6/stack.c b/libcpu/arm/armv6/stack.c index 52de999fc2..33a8d96d48 100644 --- a/libcpu/arm/armv6/stack.c +++ b/libcpu/arm/armv6/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.c b/libcpu/arm/armv6/vfp.c index 9aa8d34fcc..fc07f5a309 100644 --- a/libcpu/arm/armv6/vfp.c +++ b/libcpu/arm/armv6/vfp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.h b/libcpu/arm/armv6/vfp.h index c347dbe0a6..fd084f3aef 100644 --- a/libcpu/arm/armv6/vfp.h +++ b/libcpu/arm/armv6/vfp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -87,7 +87,7 @@ }) #define vmsr(vfp, var) \ - asm("vmsr "#vfp", %0" \ + asm("vmsr "#vfp", %0" \ : : "r" (var) : "cc") diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 4fc87b20d1..388a409d88 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/common/div0.c b/libcpu/arm/common/div0.c index 0cb3e09b54..113778b43f 100644 --- a/libcpu/arm/common/div0.c +++ b/libcpu/arm/common/div0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,5 +8,5 @@ */ void __div0 (void) { - while (1) ; + while (1) ; } diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index b770e4ce17..1a94ff1d9f 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,27 +12,27 @@ void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) { - int i = 0, j =0; + int i = 0, j =0; - RT_ASSERT(addr); + RT_ASSERT(addr); - addr = addr & ~0xF; - size = 4*((size + 3)/4); + addr = addr & ~0xF; + size = 4*((size + 3)/4); - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - addr += 4; - i++; - } + addr += 4; + i++; + } - rt_kprintf("\n"); - } + rt_kprintf("\n"); + } - return; + return; } diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 30af86baa1..0a7e702dbb 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-03-29 quanzhao the first version + * 2019-03-29 quanzhao the first version */ #include <rthw.h> #include <rtdef.h> diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 97c5b93ad2..687199e573 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 6775b781bc..9555e01e9c 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2e94b88277..faad418b2d 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index a16d0467fb..e48f9f854d 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index b7a70719a9..0d440d1d0e 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 442187edee..a8a9afb95c 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 1260f41fe5..243fe19a0a 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index fbce6df935..5cc60a774d 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/cortex-a/pmu.h +++ b/libcpu/arm/cortex-a/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 07d795ab5b..e68b324867 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index dc232a46ee..a213e776c7 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index 19aec42230..49e15bf339 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c index 842802c866..d8f9b12c2c 100644 --- a/libcpu/arm/cortex-m23/cpuport.c +++ b/libcpu/arm/cortex-m23/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index b6c4c9743c..19c33bd7c9 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index 41325105d7..928689d9c8 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -457,7 +457,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c index 5f37ddbb8f..f49f0c24f8 100644 --- a/libcpu/arm/cortex-m33/trustzone.c +++ b/libcpu/arm/cortex-m33/trustzone.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); rt_ubase_t rt_trustzone_current_context; -#if defined(__CC_ARM) +#if defined(__CC_ARM) static __inline rt_uint32_t __get_IPSR(void) { register rt_uint32_t result __asm("ipsr"); @@ -78,7 +78,7 @@ rt_err_t rt_trustzone_enter(rt_ubase_t module) rt_trustzone_init(); if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0)) { - return RT_EOK; + return RT_EOK; } return -RT_ERROR; } diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index 2e47832259..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 350b819c00..417558e285 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rtdef.h> #include <board.h> -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) void rt_hw_cpu_icache_enable(void) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index aeb9f14ac5..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/armv7.h b/libcpu/arm/cortex-r4/armv7.h index 3adcb92c5d..d29b41a213 100644 --- a/libcpu/arm/cortex-r4/armv7.h +++ b/libcpu/arm/cortex-r4/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,23 +16,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index 23c16e383c..dd82ef1cf4 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,22 +30,22 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } #ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __asm(" rsb r1, r0, #0"); - __asm(" and r1, r1, r0"); - __asm(" clz r1, r1"); - __asm(" rsb r0, r1, #32"); + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); } #endif diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 30e14f5a2d..14a9023921 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include "armv7.h" -#define MAX_HANDLERS 96 +#define MAX_HANDLERS 96 /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_int_not_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } #define vimRAM (0xFFF82000U) void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr; + rt_uint32_t *vect_addr; /* the initialization is done in sys_startup.c */ @@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_int_not_handle; - vect_addr = (rt_uint32_t *)(vimRAM + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; + vect_addr = (rt_uint32_t *)(vimRAM + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) @@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector) * @return the old handler */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 612cde3bfb..539b47d3d2 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/trap.c b/libcpu/arm/cortex-r4/trap.c index d50ad06538..e6c62390c1 100644 --- a/libcpu/arm/cortex-r4/trap.c +++ b/libcpu/arm/cortex-r4/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,13 +28,13 @@ */ void rt_hw_show_register (struct rt_hw_exp_stack *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) rt_kprintf("Data Abort "); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_kprintf("Reserved trap\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) vimREG->IRQVECREG; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) vimREG->IRQVECREG; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c index 99edb96260..435ca2f15f 100644 --- a/libcpu/arm/dm36x/cpuport.c +++ b/libcpu/arm/dm36x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,70 +20,70 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -162,67 +162,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c index abb2c1cd9e..bec2e6a71c 100644 --- a/libcpu/arm/dm36x/mmu.c +++ b/libcpu/arm/dm36x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,22 +12,22 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; + value = 0; __asm volatile { mcr p15, 0, value, c8, c7, 0 - } + } - value = 0x55555555; - __asm volatile - { + value = 0x55555555; + __asm volatile + { mcr p15, 0, value, c3, c0, 0 mcr p15, 0, i, c2, c0, 0 } @@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } ptr += CACHE_LINE_SIZE; } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() @@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all() #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* S R bit=1 0 for system protection */ - i |= (1 << 8); - i &= ~(1 << 9); + i |= 0x1; + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + /* S R bit=1 0 for system protection */ + i |= (1 << 8); + i &= ~(1 << 9); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); ptr += CACHE_LINE_SIZE; } } @@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() @@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc) if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ { *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + + p_pteentry = (rt_uint32_t *)pte_offset + ((vaddr & 0x000ff000) >> 12); pte_offset += 1024; } else /* using old Level 1 page table item */ { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + ((vaddr & 0x000ff000) >> 12); } @@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ + /* clear pgd and pte table */ rt_memset((void *)_pgd_table, 0, 16*1024); rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); build_pte_mem_desc(mdesc, size); diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h index 3410b881ac..60a4e3c6e9 100644 --- a/libcpu/arm/dm36x/mmu.h +++ b/libcpu/arm/dm36x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -133,14 +133,14 @@ #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; + #define SECT_MAPPED 0 + #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/dm36x/stack.c b/libcpu/arm/dm36x/stack.c index 9d7385b9c8..e725d060c1 100644 --- a/libcpu/arm/dm36x/stack.c +++ b/libcpu/arm/dm36x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 54e7e9b0c8..a1f594dcb9 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ #include <rthw.h> #include "lpc214x.h" -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 +#define MAX_HANDLERS 32 +#define SVCMODE 0x13 extern rt_uint32_t rt_interrupt_nest; /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; /** * @addtogroup LPC214x @@ -37,35 +37,35 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)tentry; /* entry point */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)tentry; /* entry point */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /* exception and interrupt handler table */ @@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -82,32 +82,32 @@ void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; + rt_base_t index; + rt_uint32_t *vect_addr, *vect_ctl; - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for (index = 0; index < MAX_HANDLERS; index ++) - { + for (index = 0; index < MAX_HANDLERS; index ++) + { irq_desc[index].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - *vect_addr = (rt_uint32_t)&irq_desc[index]; - *vect_ctl = 0xF; - } + *vect_addr = (rt_uint32_t)&irq_desc[index]; + *vect_ctl = 0xF; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -116,7 +116,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } /** @@ -125,7 +125,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -143,17 +143,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if(vector >= 0 && vector < MAX_HANDLERS) { - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); /* assign IRQ slot and enable this slot */ *vect_ctl = 0x20 | (vector & 0x1F); old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } } return old_handler; @@ -173,22 +173,22 @@ RT_WEAK void rt_hw_cpu_reset(void) */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } void rt_hw_trap_irq(void) { int irqno; - struct rt_irq_desc* irq; + struct rt_irq_desc* irq; extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); /* acknowledge Interrupt */ // VICVectAddr = 0; diff --git a/libcpu/arm/lpc214x/lpc214x.h b/libcpu/arm/lpc214x/lpc214x.h index 1805bc6c03..21691f85ad 100644 --- a/libcpu/arm/lpc214x/lpc214x.h +++ b/libcpu/arm/lpc214x/lpc214x.h @@ -361,33 +361,33 @@ #define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) #define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 enum LPC214x_INT { - WDT_INT = 0, - SW_INT_reserved, - DbgCommRx_INT, - DbgCommTx_INT, - TIMER0_INT, - TIMER1_INT, - UART0_INT, - UART1_INT, - PWM0_INT, - I2C0_INT, - SP0_INT, - SP1_INT, - PLL_INT, - RTC_INT, - EINT0_INT, - EINT1_INT, - EINT2_INT, - EINT3_INT, - ADC0_INT, - I2C1_INT, - BOD_INT, - ADC1_INT, - USB_INT + WDT_INT = 0, + SW_INT_reserved, + DbgCommRx_INT, + DbgCommTx_INT, + TIMER0_INT, + TIMER1_INT, + UART0_INT, + UART1_INT, + PWM0_INT, + I2C0_INT, + SP0_INT, + SP1_INT, + PLL_INT, + RTC_INT, + EINT0_INT, + EINT1_INT, + EINT2_INT, + EINT3_INT, + ADC0_INT, + I2C1_INT, + BOD_INT, + ADC1_INT, + USB_INT }; #endif // __LPC214x_H diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 5cb9730854..827310ca67 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #ifdef __cplusplus extern "C" { #endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + /* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) @@ -111,7 +111,7 @@ these registers are known as "VICVectPriority(x)". */ /* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL_BASE_ADDR 0xE002C000 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) @@ -137,7 +137,7 @@ these registers are known as "VICVectPriority(x)". */ #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) /* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 +#define GPIO_BASE_ADDR 0xE0028000 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) @@ -148,13 +148,13 @@ these registers are known as "VICVectPriority(x)". */ #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) /* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) @@ -162,227 +162,227 @@ these registers are known as "VICVectPriority(x)". */ #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) /* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 +#define SCB_BASE_ADDR 0xE01FC000 /* Memory Accelerator Module (MAM) */ #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) @@ -405,7 +405,7 @@ Reset, and Code Security/Debugging */ #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - + /* External Interrupts */ #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) @@ -423,22 +423,22 @@ Reset, and Code Security/Debugging */ #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) /* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 /* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_BASE_ADDR 0xFFE08000 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) @@ -503,9 +503,9 @@ are for LPC24xx only. */ #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - + /* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 +#define TMR0_BASE_ADDR 0xE0004000 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) @@ -525,7 +525,7 @@ are for LPC24xx only. */ #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) /* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 +#define TMR1_BASE_ADDR 0xE0008000 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) @@ -545,7 +545,7 @@ are for LPC24xx only. */ #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) /* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 +#define TMR2_BASE_ADDR 0xE0070000 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) @@ -565,7 +565,7 @@ are for LPC24xx only. */ #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) /* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 +#define TMR3_BASE_ADDR 0xE0074000 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) @@ -586,7 +586,7 @@ are for LPC24xx only. */ /* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0_BASE_ADDR 0xE0014000 #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) @@ -610,7 +610,7 @@ are for LPC24xx only. */ #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) -#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1_BASE_ADDR 0xE0018000 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) @@ -636,7 +636,7 @@ are for LPC24xx only. */ /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 +#define UART0_BASE_ADDR 0xE000C000 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) @@ -653,7 +653,7 @@ are for LPC24xx only. */ #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 +#define UART1_BASE_ADDR 0xE0010000 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) @@ -671,7 +671,7 @@ are for LPC24xx only. */ #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 +#define UART2_BASE_ADDR 0xE0078000 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) @@ -688,7 +688,7 @@ are for LPC24xx only. */ #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 +#define UART3_BASE_ADDR 0xE007C000 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) @@ -705,7 +705,7 @@ are for LPC24xx only. */ #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) /* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 +#define I2C0_BASE_ADDR 0xE001C000 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) @@ -715,7 +715,7 @@ are for LPC24xx only. */ #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) /* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 +#define I2C1_BASE_ADDR 0xE005C000 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) @@ -725,7 +725,7 @@ are for LPC24xx only. */ #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) /* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 +#define I2C2_BASE_ADDR 0xE0080000 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) @@ -735,7 +735,7 @@ are for LPC24xx only. */ #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) /* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 +#define SPI0_BASE_ADDR 0xE0020000 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) @@ -743,7 +743,7 @@ are for LPC24xx only. */ #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) /* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0_BASE_ADDR 0xE0068000 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) @@ -756,7 +756,7 @@ are for LPC24xx only. */ #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) /* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1_BASE_ADDR 0xE0030000 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) @@ -770,7 +770,7 @@ are for LPC24xx only. */ /* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 +#define RTC_BASE_ADDR 0xE0024000 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) @@ -801,7 +801,7 @@ are for LPC24xx only. */ /* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 +#define AD0_BASE_ADDR 0xE0034000 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) @@ -817,12 +817,12 @@ are for LPC24xx only. */ /* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 +#define DAC_BASE_ADDR 0xE006C000 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) /* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 +#define WDG_BASE_ADDR 0xE0000000 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) @@ -830,78 +830,78 @@ are for LPC24xx only. */ #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) /* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 +#define MCI_BASE_ADDR 0xE008C000 #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) @@ -924,7 +924,7 @@ are for LPC24xx only. */ /* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 +#define I2S_BASE_ADDR 0xE0088000 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) @@ -938,7 +938,7 @@ are for LPC24xx only. */ /* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 +#define DMA_BASE_ADDR 0xFFE04000 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) @@ -970,8 +970,8 @@ are for LPC24xx only. */ /* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) @@ -1027,7 +1027,7 @@ are for LPC24xx only. */ /* USB Host and OTG registers are for LPC24xx only */ /* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 +#define USBHC_BASE_ADDR 0xFFE0C000 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) @@ -1053,16 +1053,16 @@ are for LPC24xx only. */ #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) /* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 +#define USBOTG_BASE_ADDR 0xFFE0C100 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) @@ -1070,20 +1070,20 @@ are for LPC24xx only. */ #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ +with the spec. update in USB Device Section. */ #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ @@ -1139,7 +1139,7 @@ with the spec. update in USB Device Section. */ #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ /* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ #define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) #define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) #define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) @@ -1169,24 +1169,24 @@ with the spec. update in USB Device Section. */ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/lpc24xx/cpu.c b/libcpu/arm/lpc24xx/cpu.c index 0453722d1d..d9c74020bb 100644 --- a/libcpu/arm/lpc24xx/cpu.c +++ b/libcpu/arm/lpc24xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/lpc24xx/interrupt.c b/libcpu/arm/lpc24xx/interrupt.c index a855de1e11..87bb86b879 100644 --- a/libcpu/arm/lpc24xx/interrupt.c +++ b/libcpu/arm/lpc24xx/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "LPC24xx.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,19 +30,19 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /*@{*/ void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr, *vect_cntl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - VICIntSelect = 0; + rt_uint32_t *vect_addr, *vect_cntl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + VICIntSelect = 0; /* init exceptions table */ rt_memset(irq_desc, 0x00, sizeof(irq_desc)); @@ -50,27 +50,27 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); - vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - *vect_cntl = 0xF; + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); + vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; + *vect_cntl = 0xF; } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -82,22 +82,22 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index 0378a5f658..a7bce755b3 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc24xx/trap.c b/libcpu/arm/lpc24xx/trap.c index d296bfdbfe..7ad7328a93 100644 --- a/libcpu/arm/lpc24xx/trap.c +++ b/libcpu/arm/lpc24xx/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,13 +27,13 @@ */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -48,8 +48,8 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -66,8 +66,8 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) { rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -83,8 +83,8 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) { rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -97,11 +97,11 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) * @note never invoke this function in application */ void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ +{ rt_kprintf("Data Abort "); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -116,27 +116,27 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) { rt_kprintf("not used\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) -{ +{ rt_kprintf("fast interrupt request\n"); } diff --git a/libcpu/arm/realview-a8-vmm/armv7.h b/libcpu/arm/realview-a8-vmm/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/realview-a8-vmm/armv7.h +++ b/libcpu/arm/realview-a8-vmm/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/realview-a8-vmm/cp15.h b/libcpu/arm/realview-a8-vmm/cp15.h index 486f38200d..b18331af92 100644 --- a/libcpu/arm/realview-a8-vmm/cp15.h +++ b/libcpu/arm/realview-a8-vmm/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/cpu.c b/libcpu/arm/realview-a8-vmm/cpu.c index dbdb4ac515..8c5a6d16dd 100644 --- a/libcpu/arm/realview-a8-vmm/cpu.c +++ b/libcpu/arm/realview-a8-vmm/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ /** shutdown CPU */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/realview-a8-vmm/gic.c b/libcpu/arm/realview-a8-vmm/gic.c index 82f87b7e8f..962317821a 100644 --- a/libcpu/arm/realview-a8-vmm/gic.c +++ b/libcpu/arm/realview-a8-vmm/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/gic.h b/libcpu/arm/realview-a8-vmm/gic.h index 8fcdf05f6f..7c781ad4d9 100644 --- a/libcpu/arm/realview-a8-vmm/gic.h +++ b/libcpu/arm/realview-a8-vmm/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.c b/libcpu/arm/realview-a8-vmm/interrupt.c index 5fffb4ba36..23ff062a8b 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.c +++ b/libcpu/arm/realview-a8-vmm/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.h b/libcpu/arm/realview-a8-vmm/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.h +++ b/libcpu/arm/realview-a8-vmm/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/realview-a8-vmm/mmu.c b/libcpu/arm/realview-a8-vmm/mmu.c index 58acdd8145..f4d6068099 100644 --- a/libcpu/arm/realview-a8-vmm/mmu.c +++ b/libcpu/arm/realview-a8-vmm/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.c b/libcpu/arm/realview-a8-vmm/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.c +++ b/libcpu/arm/realview-a8-vmm/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.h b/libcpu/arm/realview-a8-vmm/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.h +++ b/libcpu/arm/realview-a8-vmm/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/stack.c b/libcpu/arm/realview-a8-vmm/stack.c index 619a16c446..8cf73ac05c 100644 --- a/libcpu/arm/realview-a8-vmm/stack.c +++ b/libcpu/arm/realview-a8-vmm/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/trap.c b/libcpu/arm/realview-a8-vmm/trap.c index 4a522f5126..c6ca45aee7 100644 --- a/libcpu/arm/realview-a8-vmm/trap.c +++ b/libcpu/arm/realview-a8-vmm/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 2adf526a5c..3a72782ae4 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,76 +17,76 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); - /* Disable watchdog */ - WTCON = 0x0000; + /* Disable watchdog */ + WTCON = 0x0000; - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -173,14 +173,14 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c index 8c7aebeb25..c985fc7c86 100644 --- a/libcpu/arm/s3c24x0/interrupt.c +++ b/libcpu/arm/s3c24x0/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include "s3c24x0.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -86,15 +86,15 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector == INTNOTUSED6) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - // while(1); - } - else if (vector == INTGLOBAL) - INTMSK = 0x0; - else - INTMSK &= ~(1 << vector); + if (vector == INTNOTUSED6) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + // while(1); + } + else if (vector == INTGLOBAL) + INTMSK = 0x0; + else + INTMSK &= ~(1 << vector); } /** @@ -115,9 +115,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; + isr_table[vector].handler = handler; isr_table[vector].param = param; } } diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index dc993ec9a3..4e5ef8d3c6 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,158 +12,158 @@ #include <rtthread.h> #include "s3c24x0.h" -#define _MMUTT_STARTADDRESS 0x33FF0000 +#define _MMUTT_STARTADDRESS 0x33FF0000 -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) #ifdef __GNUC__ void mmu_setttbase(register rt_uint32_t i) { - asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; + i |= 0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } #endif @@ -320,71 +320,71 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } void rt_hw_mmu_init(void) { - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== - mmu_disable_dcache(); - mmu_disable_icache(); + mmu_disable_dcache(); + mmu_disable_icache(); - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - mmu_invalidate_icache(); + mmu_invalidate_icache(); - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + mmu_disable(); + mmu_invalidate_tlb(); - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - mmu_setttbase(_MMUTT_STARTADDRESS); + mmu_setttbase(_MMUTT_STARTADDRESS); - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - mmu_enable_alignfault(); + mmu_enable_alignfault(); - mmu_enable(); + mmu_enable(); - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); } diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 73de840b37..0f9484405c 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up */ #include <rtthread.h> @@ -17,50 +17,50 @@ // #define RTC_DEBUG -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) /** * This function get rtc time */ void rt_hw_rtc_get(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; } while (sec != BCDSEC); #ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); #endif - /* disable access to RTC registers */ - RTC_DISABLE + /* disable access to RTC registers */ + RTC_DISABLE - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; } /** @@ -68,32 +68,32 @@ void rt_hw_rtc_get(struct tm *ti) */ void rt_hw_rtc_set(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); + /* enable access to RTC registers */ + RTC_ENABLE - /* enable access to RTC registers */ - RTC_ENABLE + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE + /* disable access to RTC registers */ + RTC_DISABLE } /** @@ -101,26 +101,26 @@ void rt_hw_rtc_set(struct tm *ti) */ void rt_hw_rtc_reset (void) { - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); } static struct rt_device rtc; static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) { - RTC_ENABLE - return RT_EOK; + RTC_ENABLE + return RT_EOK; } static rt_err_t rtc_close(rt_device_t dev) { - RTC_DISABLE - return RT_EOK; + RTC_DISABLE + return RT_EOK; } static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - return RT_EOK; + return RT_EOK; } static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) @@ -150,36 +150,36 @@ static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) void rt_hw_rtc_init(void) { - rtc.type = RT_Device_Class_RTC; + rtc.type = RT_Device_Class_RTC; - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); } #ifdef RT_USING_FINSH #include <finsh.h> void list_date() { - time_t time; - rt_device_t device; + time_t time; + rt_device_t device; - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - rt_kprintf("%d, %s\n", time, ctime(&time)); - } + rt_kprintf("%d, %s\n", time, ctime(&time)); + } } FINSH_FUNCTION_EXPORT(list_date, list date); #endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index aafa714b0e..78219325a5 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index 03749c5227..75e1eb0119 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { */ /*@{*/ -// Memory control +// Memory control #define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control @@ -101,7 +101,7 @@ extern "C" { #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control // LCD CONTROLLER @@ -114,7 +114,7 @@ extern "C" { #define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 #define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set #define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table #define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table #define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode #define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette @@ -223,10 +223,10 @@ extern "C" { #define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 // Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register // USB DEVICE @@ -388,9 +388,9 @@ extern "C" { #define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control @@ -495,7 +495,7 @@ extern "C" { #ifdef __BIG_ENDIAN /* edited for 2440A */ #define SDIDAT (*(volatile unsigned *)0x5a00004c) #else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) +#define SDIDAT (*(volatile unsigned *)0x5a000040) #endif //SD Interface // PENDING BIT @@ -562,40 +562,40 @@ extern "C" { #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} //Wait until INTPND is changed for the case that the ISR is very short. -#define INTGLOBAL 32 +#define INTGLOBAL 32 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c index 82607c3590..99938e2317 100644 --- a/libcpu/arm/s3c24x0/stack.c +++ b/libcpu/arm/s3c24x0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index 833b193cce..235c5e5e5c 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,21 +11,21 @@ #include <rtthread.h> #include "s3c24x0.h" -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz #if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ #endif rt_uint32_t PCLK; @@ -35,60 +35,60 @@ rt_uint32_t UCLK; void rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t m, p, s; + rt_uint32_t val; + rt_uint8_t m, p, s; - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; + FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; - val = CLKDIVN; - m = (val>>1)&3; - p = val&1; + val = CLKDIVN; + m = (val>>1)&3; + p = val&1; - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; } - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; } void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); } void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; } void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) { - CLKDIVN = (hdivn<<1) | pdivn; + CLKDIVN = (hdivn<<1) | pdivn; } /** @@ -96,9 +96,9 @@ void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) */ void rt_hw_clock_init(void) { - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); } diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index f2f389c6b0..f0e8a7097a 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,13 +34,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -53,15 +53,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -75,10 +75,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -91,15 +91,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -112,15 +112,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -132,9 +132,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -161,13 +161,13 @@ void rt_hw_trap_irq(void) ClearPending(1 << irq); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c index 9d60b09688..d80ca054e2 100644 --- a/libcpu/arm/s3c44b0/cpu.c +++ b/libcpu/arm/s3c44b0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,29 +22,29 @@ */ void rt_hw_cpu_icache_enable() { - rt_base_t reg; + rt_base_t reg; - volatile int i; - /* flush cycle */ - for(i = 0x10002000; i < 0x10004800; i+=16) - { - *((int *)i)=0x0; - } + volatile int i; + /* flush cycle */ + for(i = 0x10002000; i < 0x10004800; i+=16) + { + *((int *)i)=0x0; + } - /* - * Init cache - * Non-cacheable area (everything outside RAM) - * 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; + /* + * Init cache + * Non-cacheable area (everything outside RAM) + * 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -53,11 +53,11 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - rt_base_t reg; + rt_base_t reg; - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -66,7 +66,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return 0; + return 0; } /** @@ -75,7 +75,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } /** @@ -84,7 +84,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - rt_hw_cpu_icache_disable(); + rt_hw_cpu_icache_disable(); } /** @@ -93,7 +93,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return rt_hw_cpu_icache_status(); + return rt_hw_cpu_icache_status(); } /** @@ -110,9 +110,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c index 6b3eed4a39..5464011dd2 100644 --- a/libcpu/arm/s3c44b0/interrupt.c +++ b/libcpu/arm/s3c44b0/interrupt.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard add interrupt bank 0..3 for more effective + * 2006-09-15 Bernard add interrupt bank 0..3 for more effective * in irq trap */ #include <rtthread.h> #include "s3c44b0.h" -#define MAX_HANDLERS 26 +#define MAX_HANDLERS 26 extern rt_uint32_t rt_interrupt_nest; @@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256]; void rt_hw_interrupt_handle(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -42,70 +42,70 @@ void rt_hw_interrupt_handle(int vector) */ void rt_hw_interrupt_init() { - register int i; + register int i; - /* all interrupt disabled include global bit */ - INTMSK = 0x07ffffff; - - /* clear pending register */ - I_ISPC = 0x03ffffff; - - /* non-vector mode IRQ enable */ - INTCON = 0x5; - - /* all IRQ mode */ - INTMOD = 0x0; + /* all interrupt disabled include global bit */ + INTMSK = 0x07ffffff; - /* init exceptions table */ - for(i=0; i<MAX_HANDLERS; i++) - { - isr_table[i] = rt_hw_interrupt_handle; - } + /* clear pending register */ + I_ISPC = 0x03ffffff; - for ( i = 0; i < 256; i++) - { - interrupt_bank0[i] = 0; - interrupt_bank1[i] = 0; - interrupt_bank2[i] = 0; - interrupt_bank3[i] = 0; - } + /* non-vector mode IRQ enable */ + INTCON = 0x5; - /* setup interrupt bank table */ - interrupt_bank0[1] = 0; - interrupt_bank0[2] = 1; - interrupt_bank0[4] = 2; - interrupt_bank0[8] = 3; - interrupt_bank0[16] = 4; - interrupt_bank0[32] = 5; - interrupt_bank0[64] = 6; - interrupt_bank0[128]= 7; + /* all IRQ mode */ + INTMOD = 0x0; - interrupt_bank1[1] = 8; - interrupt_bank1[2] = 9; - interrupt_bank1[4] = 10; - interrupt_bank1[8] = 11; - interrupt_bank1[16] = 12; - interrupt_bank1[32] = 13; - interrupt_bank1[64] = 14; - interrupt_bank1[128]= 15; + /* init exceptions table */ + for(i=0; i<MAX_HANDLERS; i++) + { + isr_table[i] = rt_hw_interrupt_handle; + } - interrupt_bank2[1] = 16; - interrupt_bank2[2] = 17; - interrupt_bank2[4] = 18; - interrupt_bank2[8] = 19; - interrupt_bank2[16] = 20; - interrupt_bank2[32] = 21; - interrupt_bank2[64] = 22; - interrupt_bank2[128]= 23; + for ( i = 0; i < 256; i++) + { + interrupt_bank0[i] = 0; + interrupt_bank1[i] = 0; + interrupt_bank2[i] = 0; + interrupt_bank3[i] = 0; + } - interrupt_bank3[1] = 24; - interrupt_bank3[2] = 25; + /* setup interrupt bank table */ + interrupt_bank0[1] = 0; + interrupt_bank0[2] = 1; + interrupt_bank0[4] = 2; + interrupt_bank0[8] = 3; + interrupt_bank0[16] = 4; + interrupt_bank0[32] = 5; + interrupt_bank0[64] = 6; + interrupt_bank0[128]= 7; - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + interrupt_bank1[1] = 8; + interrupt_bank1[2] = 9; + interrupt_bank1[4] = 10; + interrupt_bank1[8] = 11; + interrupt_bank1[16] = 12; + interrupt_bank1[32] = 13; + interrupt_bank1[64] = 14; + interrupt_bank1[128]= 15; + + interrupt_bank2[1] = 16; + interrupt_bank2[2] = 17; + interrupt_bank2[4] = 18; + interrupt_bank2[8] = 19; + interrupt_bank2[16] = 20; + interrupt_bank2[32] = 21; + interrupt_bank2[64] = 22; + interrupt_bank2[128]= 23; + + interrupt_bank3[1] = 24; + interrupt_bank3[2] = 25; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -114,7 +114,7 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -123,7 +123,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - INTMSK &= ~(1 << vector); + INTMSK &= ~(1 << vector); } /** @@ -134,11 +134,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector < MAX_HANDLERS) - { - if (old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) isr_table[vector] = new_handler; - } + if(vector < MAX_HANDLERS) + { + if (old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } } /*@}*/ diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h index 7b854b718a..a40946b573 100644 --- a/libcpu/arm/s3c44b0/s3c44b0.h +++ b/libcpu/arm/s3c44b0/s3c44b0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,315 +22,315 @@ extern "C" { /*@{*/ /*------------------------------------------------------------------------ - * ASIC Address Definition + * ASIC Address Definition *----------------------------------------------------------------------*/ -#define S3C_REG *(volatile unsigned int *) -#define S3C_REGW *(volatile unsigned short *) -#define S3C_REGB *(volatile unsigned char *) +#define S3C_REG *(volatile unsigned int *) +#define S3C_REGW *(volatile unsigned short *) +#define S3C_REGB *(volatile unsigned char *) /* System */ -#define SYSCFG (S3C_REG(0x1c00000)) +#define SYSCFG (S3C_REG(0x1c00000)) /* Cache */ -#define NCACHBE0 (S3C_REG(0x1c00004)) -#define NCACHBE1 (S3C_REG(0x1c00008)) +#define NCACHBE0 (S3C_REG(0x1c00004)) +#define NCACHBE1 (S3C_REG(0x1c00008)) /* Bus control */ -#define SBUSCON (S3C_REG(0x1c40000)) +#define SBUSCON (S3C_REG(0x1c40000)) /* Memory control */ -#define BWSCON (S3C_REG(0x1c80000)) -#define BANKCON0 (S3C_REG(0x1c80004)) -#define BANKCON1 (S3C_REG(0x1c80008)) -#define BANKCON2 (S3C_REG(0x1c8000c)) -#define BANKCON3 (S3C_REG(0x1c80010)) -#define BANKCON4 (S3C_REG(0x1c80014)) -#define BANKCON5 (S3C_REG(0x1c80018)) -#define BANKCON6 (S3C_REG(0x1c8001c)) -#define BANKCON7 (S3C_REG(0x1c80020)) -#define REFRESH (S3C_REG(0x1c80024)) -#define BANKSIZE (S3C_REG(0x1c80028)) -#define MRSRB6 (S3C_REG(0x1c8002c)) -#define MRSRB7 (S3C_REG(0x1c80030)) +#define BWSCON (S3C_REG(0x1c80000)) +#define BANKCON0 (S3C_REG(0x1c80004)) +#define BANKCON1 (S3C_REG(0x1c80008)) +#define BANKCON2 (S3C_REG(0x1c8000c)) +#define BANKCON3 (S3C_REG(0x1c80010)) +#define BANKCON4 (S3C_REG(0x1c80014)) +#define BANKCON5 (S3C_REG(0x1c80018)) +#define BANKCON6 (S3C_REG(0x1c8001c)) +#define BANKCON7 (S3C_REG(0x1c80020)) +#define REFRESH (S3C_REG(0x1c80024)) +#define BANKSIZE (S3C_REG(0x1c80028)) +#define MRSRB6 (S3C_REG(0x1c8002c)) +#define MRSRB7 (S3C_REG(0x1c80030)) /* UART */ -#define ULCON0 (S3C_REG(0x1d00000)) -#define ULCON1 (S3C_REG(0x1d04000)) -#define UCON0 (S3C_REG(0x1d00004)) -#define UCON1 (S3C_REG(0x1d04004)) -#define UFCON0 (S3C_REG(0x1d00008)) -#define UFCON1 (S3C_REG(0x1d04008)) -#define UMCON0 (S3C_REG(0x1d0000c)) -#define UMCON1 (S3C_REG(0x1d0400c)) -#define UTRSTAT0 (S3C_REG(0x1d00010)) -#define UTRSTAT1 (S3C_REG(0x1d04010)) -#define UERSTAT0 (S3C_REG(0x1d00014)) -#define UERSTAT1 (S3C_REG(0x1d04014)) -#define UFSTAT0 (S3C_REG(0x1d00018)) -#define UFSTAT1 (S3C_REG(0x1d04018)) -#define UMSTAT0 (S3C_REG(0x1d0001c)) -#define UMSTAT1 (S3C_REG(0x1d0401c)) -#define UBRDIV0 (S3C_REG(0x1d00028)) -#define UBRDIV1 (S3C_REG(0x1d04028)) +#define ULCON0 (S3C_REG(0x1d00000)) +#define ULCON1 (S3C_REG(0x1d04000)) +#define UCON0 (S3C_REG(0x1d00004)) +#define UCON1 (S3C_REG(0x1d04004)) +#define UFCON0 (S3C_REG(0x1d00008)) +#define UFCON1 (S3C_REG(0x1d04008)) +#define UMCON0 (S3C_REG(0x1d0000c)) +#define UMCON1 (S3C_REG(0x1d0400c)) +#define UTRSTAT0 (S3C_REG(0x1d00010)) +#define UTRSTAT1 (S3C_REG(0x1d04010)) +#define UERSTAT0 (S3C_REG(0x1d00014)) +#define UERSTAT1 (S3C_REG(0x1d04014)) +#define UFSTAT0 (S3C_REG(0x1d00018)) +#define UFSTAT1 (S3C_REG(0x1d04018)) +#define UMSTAT0 (S3C_REG(0x1d0001c)) +#define UMSTAT1 (S3C_REG(0x1d0401c)) +#define UBRDIV0 (S3C_REG(0x1d00028)) +#define UBRDIV1 (S3C_REG(0x1d04028)) -#define UTXH0 (S3C_REGB(0x1d00020)) -#define UTXH1 (S3C_REGB(0x1d04020)) -#define URXH0 (S3C_REGB(0x1d00024)) -#define URXH1 (S3C_REGB(0x1d04024)) +#define UTXH0 (S3C_REGB(0x1d00020)) +#define UTXH1 (S3C_REGB(0x1d04020)) +#define URXH0 (S3C_REGB(0x1d00024)) +#define URXH1 (S3C_REGB(0x1d04024)) /* SIO */ -#define SIOCON (S3C_REG(0x1d14000)) -#define SIODAT (S3C_REG(0x1d14004)) -#define SBRDR (S3C_REG(0x1d14008)) -#define IVTCNT (S3C_REG(0x1d1400c)) -#define DCNTZ (S3C_REG(0x1d14010)) +#define SIOCON (S3C_REG(0x1d14000)) +#define SIODAT (S3C_REG(0x1d14004)) +#define SBRDR (S3C_REG(0x1d14008)) +#define IVTCNT (S3C_REG(0x1d1400c)) +#define DCNTZ (S3C_REG(0x1d14010)) /* IIS */ -#define IISCON (S3C_REG(0x1d18000)) -#define IISMOD (S3C_REG(0x1d18004)) -#define IISPSR (S3C_REG(0x1d18008)) -#define IISFCON (S3C_REG(0x1d1800c)) +#define IISCON (S3C_REG(0x1d18000)) +#define IISMOD (S3C_REG(0x1d18004)) +#define IISPSR (S3C_REG(0x1d18008)) +#define IISFCON (S3C_REG(0x1d1800c)) -#define IISFIF (S3C_REQW(0x1d18010)) +#define IISFIF (S3C_REQW(0x1d18010)) /* I/O Port */ -#define PCONA (S3C_REG(0x1d20000)) -#define PDATA (S3C_REG(0x1d20004)) +#define PCONA (S3C_REG(0x1d20000)) +#define PDATA (S3C_REG(0x1d20004)) -#define PCONB (S3C_REG(0x1d20008)) -#define PDATB (S3C_REG(0x1d2000c)) +#define PCONB (S3C_REG(0x1d20008)) +#define PDATB (S3C_REG(0x1d2000c)) -#define PCONC (S3C_REG(0x1d20010)) -#define PDATC (S3C_REG(0x1d20014)) -#define PUPC (S3C_REG(0x1d20018)) +#define PCONC (S3C_REG(0x1d20010)) +#define PDATC (S3C_REG(0x1d20014)) +#define PUPC (S3C_REG(0x1d20018)) -#define PCOND (S3C_REG(0x1d2001c)) -#define PDATD (S3C_REG(0x1d20020)) -#define PUPD (S3C_REG(0x1d20024)) +#define PCOND (S3C_REG(0x1d2001c)) +#define PDATD (S3C_REG(0x1d20020)) +#define PUPD (S3C_REG(0x1d20024)) -#define PCONE (S3C_REG(0x1d20028)) -#define PDATE (S3C_REG(0x1d2002c)) -#define PUPE (S3C_REG(0x1d20030)) +#define PCONE (S3C_REG(0x1d20028)) +#define PDATE (S3C_REG(0x1d2002c)) +#define PUPE (S3C_REG(0x1d20030)) -#define PCONF (S3C_REG(0x1d20034)) -#define PDATF (S3C_REG(0x1d20038)) -#define PUPF (S3C_REG(0x1d2003c)) +#define PCONF (S3C_REG(0x1d20034)) +#define PDATF (S3C_REG(0x1d20038)) +#define PUPF (S3C_REG(0x1d2003c)) -#define PCONG (S3C_REG(0x1d20040)) -#define PDATG (S3C_REG(0x1d20044)) -#define PUPG (S3C_REG(0x1d20048)) +#define PCONG (S3C_REG(0x1d20040)) +#define PDATG (S3C_REG(0x1d20044)) +#define PUPG (S3C_REG(0x1d20048)) -#define SPUCR (S3C_REG(0x1d2004c)) -#define EXTINT (S3C_REG(0x1d20050)) -#define EXTINTPND (S3C_REG(0x1d20054)) +#define SPUCR (S3C_REG(0x1d2004c)) +#define EXTINT (S3C_REG(0x1d20050)) +#define EXTINTPND (S3C_REG(0x1d20054)) /* Watchdog */ -#define WTCON (S3C_REG(0x1d30000)) -#define WTDAT (S3C_REG(0x1d30004)) -#define WTCNT (S3C_REG(0x1d30008)) +#define WTCON (S3C_REG(0x1d30000)) +#define WTDAT (S3C_REG(0x1d30004)) +#define WTCNT (S3C_REG(0x1d30008)) /* ADC */ -#define ADCCON (S3C_REG(0x1d40000)) -#define ADCPSR (S3C_REG(0x1d40004)) -#define ADCDAT (S3C_REG(0x1d40008)) +#define ADCCON (S3C_REG(0x1d40000)) +#define ADCPSR (S3C_REG(0x1d40004)) +#define ADCDAT (S3C_REG(0x1d40008)) /* Timer */ -#define TCFG0 (S3C_REG(0x1d50000)) -#define TCFG1 (S3C_REG(0x1d50004)) -#define TCON (S3C_REG(0x1d50008)) +#define TCFG0 (S3C_REG(0x1d50000)) +#define TCFG1 (S3C_REG(0x1d50004)) +#define TCON (S3C_REG(0x1d50008)) -#define TCNTB0 (S3C_REG(0x1d5000c)) -#define TCMPB0 (S3C_REG(0x1d50010)) -#define TCNTO0 (S3C_REG(0x1d50014)) +#define TCNTB0 (S3C_REG(0x1d5000c)) +#define TCMPB0 (S3C_REG(0x1d50010)) +#define TCNTO0 (S3C_REG(0x1d50014)) -#define TCNTB1 (S3C_REG(0x1d50018)) -#define TCMPB1 (S3C_REG(0x1d5001c)) -#define TCNTO1 (S3C_REG(0x1d50020)) +#define TCNTB1 (S3C_REG(0x1d50018)) +#define TCMPB1 (S3C_REG(0x1d5001c)) +#define TCNTO1 (S3C_REG(0x1d50020)) -#define TCNTB2 (S3C_REG(0x1d50024)) -#define TCMPB2 (S3C_REG(0x1d50028)) -#define TCNTO2 (S3C_REG(0x1d5002c)) +#define TCNTB2 (S3C_REG(0x1d50024)) +#define TCMPB2 (S3C_REG(0x1d50028)) +#define TCNTO2 (S3C_REG(0x1d5002c)) -#define TCNTB3 (S3C_REG(0x1d50030)) -#define TCMPB3 (S3C_REG(0x1d50034)) -#define TCNTO3 (S3C_REG(0x1d50038)) +#define TCNTB3 (S3C_REG(0x1d50030)) +#define TCMPB3 (S3C_REG(0x1d50034)) +#define TCNTO3 (S3C_REG(0x1d50038)) -#define TCNTB4 (S3C_REG(0x1d5003c)) -#define TCMPB4 (S3C_REG(0x1d50040)) -#define TCNTO4 (S3C_REG(0x1d50044)) +#define TCNTB4 (S3C_REG(0x1d5003c)) +#define TCMPB4 (S3C_REG(0x1d50040)) +#define TCNTO4 (S3C_REG(0x1d50044)) -#define TCNTB5 (S3C_REG(0x1d50048)) -#define TCNTO5 (S3C_REG(0x1d5004c)) +#define TCNTB5 (S3C_REG(0x1d50048)) +#define TCNTO5 (S3C_REG(0x1d5004c)) /* IIC */ -#define IICCON (S3C_REG(0x1d60000)) -#define IICSTAT (S3C_REG(0x1d60004)) -#define IICADD (S3C_REG(0x1d60008)) -#define IICDS (S3C_REG(0x1d6000c)) +#define IICCON (S3C_REG(0x1d60000)) +#define IICSTAT (S3C_REG(0x1d60004)) +#define IICADD (S3C_REG(0x1d60008)) +#define IICDS (S3C_REG(0x1d6000c)) /* RTC */ -#define RTCCON (S3C_REGB(0x1d70040) -#define RTCALM (S3C_REGB(0x1d70050) -#define ALMSEC (S3C_REGB(0x1d70054) -#define ALMMIN (S3C_REGB(0x1d70058) -#define ALMHOUR (S3C_REGB(0x1d7005c) -#define ALMDAY (S3C_REGB(0x1d70060) -#define ALMMON (S3C_REGB(0x1d70064) -#define ALMYEAR (S3C_REGB(0x1d70068) -#define RTCRST (S3C_REGB(0x1d7006c) -#define BCDSEC (S3C_REGB(0x1d70070) -#define BCDMIN (S3C_REGB(0x1d70074) -#define BCDHOUR (S3C_REGB(0x1d70078) -#define BCDDAY (S3C_REGB(0x1d7007c) -#define BCDDATE (S3C_REGB(0x1d70080) -#define BCDMON (S3C_REGB(0x1d70084) -#define BCDYEAR (S3C_REGB(0x1d70088) -#define TICINT (S3C_REGB(0x1d7008c) +#define RTCCON (S3C_REGB(0x1d70040) +#define RTCALM (S3C_REGB(0x1d70050) +#define ALMSEC (S3C_REGB(0x1d70054) +#define ALMMIN (S3C_REGB(0x1d70058) +#define ALMHOUR (S3C_REGB(0x1d7005c) +#define ALMDAY (S3C_REGB(0x1d70060) +#define ALMMON (S3C_REGB(0x1d70064) +#define ALMYEAR (S3C_REGB(0x1d70068) +#define RTCRST (S3C_REGB(0x1d7006c) +#define BCDSEC (S3C_REGB(0x1d70070) +#define BCDMIN (S3C_REGB(0x1d70074) +#define BCDHOUR (S3C_REGB(0x1d70078) +#define BCDDAY (S3C_REGB(0x1d7007c) +#define BCDDATE (S3C_REGB(0x1d70080) +#define BCDMON (S3C_REGB(0x1d70084) +#define BCDYEAR (S3C_REGB(0x1d70088) +#define TICINT (S3C_REGB(0x1d7008c) /* Clock & Power management */ -#define PLLCON (S3C_REG(0x1d80000)) -#define CLKCON (S3C_REG(0x1d80004)) -#define CLKSLOW (S3C_REG(0x1d80008)) -#define LOCKTIME (S3C_REG(0x1d8000c)) +#define PLLCON (S3C_REG(0x1d80000)) +#define CLKCON (S3C_REG(0x1d80004)) +#define CLKSLOW (S3C_REG(0x1d80008)) +#define LOCKTIME (S3C_REG(0x1d8000c)) /* Interrupt */ -#define INTCON (S3C_REG(0x1e00000)) -#define INTPND (S3C_REG(0x1e00004)) -#define INTMOD (S3C_REG(0x1e00008)) -#define INTMSK (S3C_REG(0x1e0000c)) +#define INTCON (S3C_REG(0x1e00000)) +#define INTPND (S3C_REG(0x1e00004)) +#define INTMOD (S3C_REG(0x1e00008)) +#define INTMSK (S3C_REG(0x1e0000c)) -#define I_PSLV (S3C_REG(0x1e00010)) -#define I_PMST (S3C_REG(0x1e00014)) -#define I_CSLV (S3C_REG(0x1e00018)) -#define I_CMST (S3C_REG(0x1e0001c)) -#define I_ISPR (S3C_REG(0x1e00020)) -#define I_ISPC (S3C_REG(0x1e00024)) +#define I_PSLV (S3C_REG(0x1e00010)) +#define I_PMST (S3C_REG(0x1e00014)) +#define I_CSLV (S3C_REG(0x1e00018)) +#define I_CMST (S3C_REG(0x1e0001c)) +#define I_ISPR (S3C_REG(0x1e00020)) +#define I_ISPC (S3C_REG(0x1e00024)) -#define F_ISPR (S3C_REG(0x1e00038)) -#define F_ISPC (S3C_REG(0x1e0003c)) +#define F_ISPR (S3C_REG(0x1e00038)) +#define F_ISPC (S3C_REG(0x1e0003c)) /********************************/ /* LCD Controller Registers */ /********************************/ -#define LCDCON1 (S3C_REG(0x300000)) -#define LCDCON2 (S3C_REG(0x300004)) -#define LCDSADDR1 (S3C_REG(0x300008)) -#define LCDSADDR2 (S3C_REG(0x30000c)) -#define LCDSADDR3 (S3C_REG(0x300010)) -#define REDLUT (S3C_REG(0x300014)) -#define GREENLUT (S3C_REG(0x300018)) -#define BLUELUT (S3C_REG(0x30001c)) -#define DP1_2 (S3C_REG(0x300020)) -#define DP4_7 (S3C_REG(0x300024)) -#define DP3_5 (S3C_REG(0x300028)) -#define DP2_3 (S3C_REG(0x30002c)) -#define DP5_7 (S3C_REG(0x300030)) -#define DP3_4 (S3C_REG(0x300034)) -#define DP4_5 (S3C_REG(0x300038)) -#define DP6_7 (S3C_REG(0x30003c)) -#define LCDCON3 (S3C_REG(0x300040)) -#define DITHMODE (S3C_REG(0x300044)) +#define LCDCON1 (S3C_REG(0x300000)) +#define LCDCON2 (S3C_REG(0x300004)) +#define LCDSADDR1 (S3C_REG(0x300008)) +#define LCDSADDR2 (S3C_REG(0x30000c)) +#define LCDSADDR3 (S3C_REG(0x300010)) +#define REDLUT (S3C_REG(0x300014)) +#define GREENLUT (S3C_REG(0x300018)) +#define BLUELUT (S3C_REG(0x30001c)) +#define DP1_2 (S3C_REG(0x300020)) +#define DP4_7 (S3C_REG(0x300024)) +#define DP3_5 (S3C_REG(0x300028)) +#define DP2_3 (S3C_REG(0x30002c)) +#define DP5_7 (S3C_REG(0x300030)) +#define DP3_4 (S3C_REG(0x300034)) +#define DP4_5 (S3C_REG(0x300038)) +#define DP6_7 (S3C_REG(0x30003c)) +#define LCDCON3 (S3C_REG(0x300040)) +#define DITHMODE (S3C_REG(0x300044)) /* ZDMA0 */ -#define ZDCON0 (S3C_REG(0x1e80000)) -#define ZDISRC0 (S3C_REG(0x1e80004)) -#define ZDIDES0 (S3C_REG(0x1e80008)) -#define ZDICNT0 (S3C_REG(0x1e8000c)) -#define ZDCSRC0 (S3C_REG(0x1e80010)) -#define ZDCDES0 (S3C_REG(0x1e80014)) -#define ZDCCNT0 (S3C_REG(0x1e80018)) +#define ZDCON0 (S3C_REG(0x1e80000)) +#define ZDISRC0 (S3C_REG(0x1e80004)) +#define ZDIDES0 (S3C_REG(0x1e80008)) +#define ZDICNT0 (S3C_REG(0x1e8000c)) +#define ZDCSRC0 (S3C_REG(0x1e80010)) +#define ZDCDES0 (S3C_REG(0x1e80014)) +#define ZDCCNT0 (S3C_REG(0x1e80018)) /* ZDMA1 */ -#define ZDCON1 (S3C_REG(0x1e80020)) -#define ZDISRC1 (S3C_REG(0x1e80024)) -#define ZDIDES1 (S3C_REG(0x1e80028)) -#define ZDICNT1 (S3C_REG(0x1e8002c)) -#define ZDCSRC1 (S3C_REG(0x1e80030)) -#define ZDCDES1 (S3C_REG(0x1e80034)) -#define ZDCCNT1 (S3C_REG(0x1e80038)) +#define ZDCON1 (S3C_REG(0x1e80020)) +#define ZDISRC1 (S3C_REG(0x1e80024)) +#define ZDIDES1 (S3C_REG(0x1e80028)) +#define ZDICNT1 (S3C_REG(0x1e8002c)) +#define ZDCSRC1 (S3C_REG(0x1e80030)) +#define ZDCDES1 (S3C_REG(0x1e80034)) +#define ZDCCNT1 (S3C_REG(0x1e80038)) /* BDMA0 */ -#define BDCON0 (S3C_REG(0x1f80000)) -#define BDISRC0 (S3C_REG(0x1f80004)) -#define BDIDES0 (S3C_REG(0x1f80008)) -#define BDICNT0 (S3C_REG(0x1f8000c)) -#define BDCSRC0 (S3C_REG(0x1f80010)) -#define BDCDES0 (S3C_REG(0x1f80014)) -#define BDCCNT0 (S3C_REG(0x1f80018)) +#define BDCON0 (S3C_REG(0x1f80000)) +#define BDISRC0 (S3C_REG(0x1f80004)) +#define BDIDES0 (S3C_REG(0x1f80008)) +#define BDICNT0 (S3C_REG(0x1f8000c)) +#define BDCSRC0 (S3C_REG(0x1f80010)) +#define BDCDES0 (S3C_REG(0x1f80014)) +#define BDCCNT0 (S3C_REG(0x1f80018)) /* BDMA1 */ -#define BDCON1 (S3C_REG(0x1f80020)) -#define BDISRC1 (S3C_REG(0x1f80024)) -#define BDIDES1 (S3C_REG(0x1f80028)) -#define BDICNT1 (S3C_REG(0x1f8002c)) -#define BDCSRC1 (S3C_REG(0x1f80030)) -#define BDCDES1 (S3C_REG(0x1f80034)) -#define BDCCNT1 (S3C_REG(0x1f80038)) +#define BDCON1 (S3C_REG(0x1f80020)) +#define BDISRC1 (S3C_REG(0x1f80024)) +#define BDIDES1 (S3C_REG(0x1f80028)) +#define BDICNT1 (S3C_REG(0x1f8002c)) +#define BDCSRC1 (S3C_REG(0x1f80030)) +#define BDCDES1 (S3C_REG(0x1f80034)) +#define BDCCNT1 (S3C_REG(0x1f80038)) /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 /* User Mode(USR) */ -#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ -#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ -#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ -#define ABORTMODE 0x17 /* Abort Mode(ABT) */ -#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ -#define MODEMASK 0x1f /* Processor Mode Mask */ -#define NOINT 0xc0 +#define USERMODE 0x10 /* User Mode(USR) */ +#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ +#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ +#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ +#define ABORTMODE 0x17 /* Abort Mode(ABT) */ +#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ +#define MODEMASK 0x1f /* Processor Mode Mask */ +#define NOINT 0xc0 /*****************************/ /* INT Define */ /*****************************/ -#define INT_ADC 0x00 -#define INT_RTC 0x01 -#define INT_UTXD1 0x02 -#define INT_UTXD0 0x03 -#define INT_SIO 0x04 -#define INT_IIC 0x05 -#define INT_URXD1 0x06 -#define INT_URXD0 0x07 -#define INT_TIMER5 0x08 -#define INT_TIMER4 0x09 -#define INT_TIMER3 0x0A -#define INT_TIMER2 0x0B -#define INT_TIMER1 0x0C -#define INT_TIMER0 0x0D -#define INT_UERR01 0x0E -#define INT_WDT 0x1F -#define INT_BDMA1 0x10 -#define INT_BDMA0 0x11 -#define INT_ZDMA1 0x12 -#define INT_ZDMA0 0x13 -#define INT_TICK 0x14 -#define INT_EINT4567 0x15 -#define INT_EINT3 0x16 -#define INT_EINT2 0x17 -#define INT_EINT1 0x18 -#define INT_EINT0 0x19 +#define INT_ADC 0x00 +#define INT_RTC 0x01 +#define INT_UTXD1 0x02 +#define INT_UTXD0 0x03 +#define INT_SIO 0x04 +#define INT_IIC 0x05 +#define INT_URXD1 0x06 +#define INT_URXD0 0x07 +#define INT_TIMER5 0x08 +#define INT_TIMER4 0x09 +#define INT_TIMER3 0x0A +#define INT_TIMER2 0x0B +#define INT_TIMER1 0x0C +#define INT_TIMER0 0x0D +#define INT_UERR01 0x0E +#define INT_WDT 0x1F +#define INT_BDMA1 0x10 +#define INT_BDMA0 0x11 +#define INT_ZDMA1 0x12 +#define INT_ZDMA0 0x13 +#define INT_TICK 0x14 +#define INT_EINT4567 0x15 +#define INT_EINT3 0x16 +#define INT_EINT2 0x17 +#define INT_EINT1 0x18 +#define INT_EINT0 0x19 -#define INT_GLOBAL 26 +#define INT_GLOBAL 26 struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; /*@}*/ diff --git a/libcpu/arm/s3c44b0/serial.c b/libcpu/arm/s3c44b0/serial.c index 6af515b027..95f8cb3487 100644 --- a/libcpu/arm/s3c44b0/serial.c +++ b/libcpu/arm/s3c44b0/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,21 +18,21 @@ void rt_serial_init(void); void rt_console_puts(const char* str); void rt_serial_putc(const char c); -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ rt_inline void serial_flush_input(void) { - volatile unsigned int tmp; + volatile unsigned int tmp; - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; + /* keep on reading as long as the receiver is not empty */ + while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; } rt_inline void serial_flush_output(void) { - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; + /* wait until the transmitter is no longer busy */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; } /** @@ -48,10 +48,10 @@ rt_inline void serial_flush_output(void) */ void rt_console_puts(const char* str) { - while (*str) - { - rt_serial_putc (*str++); - } + while (*str) + { + rt_serial_putc (*str++); + } } /** @@ -59,25 +59,25 @@ void rt_console_puts(const char* str) */ void rt_serial_init() { - rt_uint32_t divisor = 0; + rt_uint32_t divisor = 0; - divisor = 0x20; + divisor = 0x20; - serial_flush_output(); - serial_flush_input(); + serial_flush_output(); + serial_flush_input(); - /* UART interrupt off */ - UCON0 = 0; - /* FIFO disable */ - UFCON0 =0x0; - UMCON0 =0x0; - /* set baudrate */ - UBRDIV0 = divisor; + /* UART interrupt off */ + UCON0 = 0; + /* FIFO disable */ + UFCON0 =0x0; + UMCON0 =0x0; + /* set baudrate */ + UBRDIV0 = divisor; - /* word length=8bit, stop bit = 1, no parity, use external clock */ - ULCON0 = 0x03|0x00|0x00; + /* word length=8bit, stop bit = 1, no parity, use external clock */ + ULCON0 = 0x03|0x00|0x00; - UCON0 = 0x5; + UCON0 = 0x5; } /** @@ -87,9 +87,9 @@ void rt_serial_init() */ char rt_serial_getc() { - while ((UTRSTAT0 & USTAT_RCV_READY) == 0); + while ((UTRSTAT0 & USTAT_RCV_READY) == 0); - return URXH0; + return URXH0; } /** @@ -99,16 +99,16 @@ char rt_serial_getc() */ void rt_serial_putc(const char c) { - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n')rt_serial_putc('\r'); + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n')rt_serial_putc('\r'); - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); + /* wait for room in the transmit FIFO */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); - UTXH0 = (rt_uint8_t)c; + UTXH0 = (rt_uint8_t)c; } /*@}*/ diff --git a/libcpu/arm/s3c44b0/stack.c b/libcpu/arm/s3c44b0/stack.c index 12da611d5a..4ed4693994 100644 --- a/libcpu/arm/s3c44b0/stack.c +++ b/libcpu/arm/s3c44b0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c44b0/trap.c b/libcpu/arm/s3c44b0/trap.c index 3b93d5457e..106a990262 100644 --- a/libcpu/arm/s3c44b0/trap.c +++ b/libcpu/arm/s3c44b0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,13 +33,13 @@ extern struct rt_thread *rt_current_thread; */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -52,10 +52,10 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("undefined instruction\n"); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("prefetch abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,10 +100,10 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("data abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -123,50 +123,50 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - register unsigned long ispr, intstat; - register rt_isr_handler_t isr_func; + register unsigned long ispr, intstat; + register rt_isr_handler_t isr_func; #ifdef BSP_INT_DEBUG - rt_kprintf("irq coming, "); + rt_kprintf("irq coming, "); #endif - intstat = I_ISPR & 0x7ffffff; + intstat = I_ISPR & 0x7ffffff; #ifdef BSP_INT_DEBUG - rt_kprintf("I_ISPR: %d\n", intstat); + rt_kprintf("I_ISPR: %d\n", intstat); #endif - ispr = intstat; + ispr = intstat; - /* to find interrupt */ - if ( intstat & 0xff ) /* lowest 8bits */ - { - intstat = interrupt_bank0[intstat & 0xff]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff00 ) /* low 8bits */ - { - intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff0000 ) /* high 8bits */ - { - intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff000000 ) /* highest 8bits */ - { - intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else return; + /* to find interrupt */ + if ( intstat & 0xff ) /* lowest 8bits */ + { + intstat = interrupt_bank0[intstat & 0xff]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff00 ) /* low 8bits */ + { + intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff0000 ) /* high 8bits */ + { + intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff000000 ) /* highest 8bits */ + { + intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else return; #ifdef BSP_INT_DEBUG - rt_kprintf("irq: %d happen\n", intstat); + rt_kprintf("irq: %d happen\n", intstat); #endif - /* turn to interrupt service routine */ - isr_func(intstat); + /* turn to interrupt service routine */ + isr_func(intstat); - I_ISPC = ispr; /* clear interrupt */ + I_ISPC = ispr; /* clear interrupt */ } void rt_hw_trap_fiq() diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index da69e25b6d..031d310fcf 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,46 +11,46 @@ #include <rtthread.h> #include "sep4020.h" -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 static void rt_hw_set_system_clock(void) { - rt_uint8_t pv; + rt_uint8_t pv; - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; } static void rt_hw_set_usb_clock(void) { - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; } @@ -59,10 +59,10 @@ static void rt_hw_set_usb_clock(void) */ void rt_hw_clock_init(void) { - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); } /** @@ -70,22 +70,22 @@ void rt_hw_clock_init(void) */ rt_uint32_t rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t pv, pd, npd; + rt_uint32_t val; + rt_uint8_t pv, pd, npd; - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); return(val); } diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index 92ba2cf86a..256ede56e9 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,76 +21,76 @@ extern rt_uint32_t rt_hw_interrupt_disable(void); */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -100,7 +100,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -109,7 +109,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -118,7 +118,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -127,7 +127,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -136,7 +136,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -145,7 +145,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -155,18 +155,18 @@ rt_base_t rt_hw_cpu_dcache_status() RT_WEAK void rt_hw_cpu_reset() { - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -175,12 +175,12 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t UNUSED level; - rt_kprintf("shutdown...\n"); + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - RT_ASSERT(RT_NULL); + RT_ASSERT(RT_NULL); } /*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index ebc9c9625b..24907c139f 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include <sep4020.h> -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -45,7 +45,7 @@ void rt_hw_interrupt_init(void) *(RP)(INTC_IMR) = 0xFFFFFFFF; /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; + *(RP)(INTC_IER) = 0XFFFFFFFF; /*Dont use any forced irq*/ *(RP)(INTC_IFR) = 0x0; @@ -82,7 +82,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - *(RP)(INTC_IMR) |= 1 << vector; + *(RP)(INTC_IMR) |= 1 << vector; } /** @@ -91,12 +91,12 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else - *(RP)(INTC_IMR) &= ~(1 << vector); + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else + *(RP)(INTC_IMR) &= ~(1 << vector); } @@ -118,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index 4ae09d0275..bb8effbff0 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ /*Core definations*/ #define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F @@ -106,7 +106,7 @@ #define RTC_INT_STS (RTC_BASE+0X014) /* 中断状态寄存器 */ #define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */ #define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ #define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* 配置时间确认寄存器 (在配置时间之前先写0xaaaaaaaa) */ #define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */ @@ -325,18 +325,18 @@ * SD模块 * 基址: 0x1000B000 */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ #define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO数据块长度寄存器 */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ #define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */ #define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状态寄存器 */ #define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状态屏蔽寄存器 */ @@ -650,15 +650,15 @@ #define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */ #define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */ #define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) /* ************************************** * Error Codes: * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, + * parameter error return (-33)/E_PAR, * hardware error reture (-99)/E_HA ************************************** */ @@ -680,7 +680,7 @@ #define E_QOVR (-73) /* Queuing or nesting overflow */ #define E_DLT (-81) /* Object being waited for was deleted */ #define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ #define E_HA (-99) /* HARD WARE ERROR */ @@ -692,7 +692,7 @@ */ #define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) +#define CLK_SI2S (1 << 15) #define CLK_SSMC (1 << 14) #define CLK_SMAC (1 << 13) #define CLK_SUSB (1 << 12) @@ -713,8 +713,8 @@ /*Interrupt Sources*/ -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 #define INTSRC_EMI 29 #define INTSRC_MAC 28 #define INTSRC_TIMER1 27 @@ -732,17 +732,17 @@ #define INTSRC_USB 15 #define INTSRC_SMC0 14 #define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 #define INTSRC_EXINT0 1 #define INTSRC_NULL 0 @@ -752,7 +752,7 @@ #define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //置1后，软件强制该位对应的中断源发出中断信号 #define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //置1后，允许中断源的IRQ 中断信号 #define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //置0后，不允许中断源的IRQ 中断信号 -#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 +#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 #define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //置0后，通过对应的IRQ 中断信号 #define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //屏蔽对应的IRQ 中断信号 #define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ 中断信号 @@ -765,7 +765,7 @@ * 所有程序中用到的Typedef ************************************** */ - + typedef char S8; /* signed 8-bit integer */ typedef short S16; /* signed 16-bit integer */ typedef long S32; /* signed 32-bit integer */ @@ -782,8 +782,8 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif typedef int ER; /* Error code. A signed integer. */ @@ -802,71 +802,71 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index 713959238a..9bf1546c08 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #include <rtthread.h> #include <rthw.h> @@ -24,204 +24,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - return RT_EOK; + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; + /* move to next position */ + uart->int_tx->save_index ++; - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } - ++ptr; --size; - } - } + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + return RT_EOK; } /* @@ -229,49 +229,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index 69e7df248c..26ec0f6cec 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #ifndef __SERIAL_H__ @@ -15,67 +15,67 @@ #include <sep4020.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep4020's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/arm/sep4020/stack.c b/libcpu/arm/sep4020/stack.c index b2205c76d2..3a7b5fd87c 100644 --- a/libcpu/arm/sep4020/stack.c +++ b/libcpu/arm/sep4020/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index c551b2246c..441a55bd6d 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,13 +31,13 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -155,13 +155,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/zynqmp-r5/armv7.h b/libcpu/arm/zynqmp-r5/armv7.h index 59c97546ec..c70d210709 100644 --- a/libcpu/arm/zynqmp-r5/armv7.h +++ b/libcpu/arm/zynqmp-r5/armv7.h @@ -14,23 +14,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c index aa8517e254..d6e7cd2d6d 100644 --- a/libcpu/arm/zynqmp-r5/cache.c +++ b/libcpu/arm/zynqmp-r5/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> #include <rtdef.h> @@ -13,154 +13,154 @@ #include "xpseudo_asm_gcc.h" #include "xreg_cortexr5.h" -#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ typedef intptr_t INTPTR; typedef rt_uint32_t u32; #if defined (__GNUC__) #define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #elif defined (__ICCARM__) #define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #endif void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr = LocalAddr & ~(cacheline - 1U); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - while (LocalAddr < end) { + while (LocalAddr < end) { - /* Invalidate L1 I-cache line */ - asm_inval_ic_line_mva_pou(LocalAddr); + /* Invalidate L1 I-cache line */ + asm_inval_ic_line_mva_pou(LocalAddr); - LocalAddr += cacheline; - } - } + LocalAddr += cacheline; + } + } - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushLine(INTPTR adr) { - u32 currmask; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - /* Wait for flush to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { - const u32 cacheline = 32U; - u32 end; - u32 tempadr = adr; - u32 tempend; - u32 currmask; + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0U) { - end = tempadr + len; - tempend = end; - /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - if ((tempadr & (cacheline-1U)) != 0U) { - tempadr &= (~(cacheline - 1U)); + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempadr); - } - if ((tempend & (cacheline-1U)) != 0U) { - tempend &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempend); - } + Xil_DCacheFlushLine(tempend); + } - while (tempadr < tempend) { + while (tempadr < tempend) { - /* Invalidate Data cache line */ - asm_inval_dc_line_mva_poc(tempadr); + /* Invalidate Data cache line */ + asm_inval_dc_line_mva_poc(tempadr); - tempadr += cacheline; - } - } + tempadr += cacheline; + } + } - dsb(); - mtcpsr(currmask); + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr &= ~(cacheline - 1U); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); - while (LocalAddr < end) { - /* Flush Data cache line */ - asm_clean_inval_dc_line_mva_poc(LocalAddr); + while (LocalAddr < end) { + /* Flush Data cache line */ + asm_clean_inval_dc_line_mva_poc(LocalAddr); - LocalAddr += cacheline; - } - } - dsb(); - mtcpsr(currmask); + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); } void rt_hw_cpu_icache_ops(int ops, void *addr, int size) @@ -179,22 +179,22 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) rt_base_t rt_hw_cpu_icache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_I_BIT; + return CtrlReg & XREG_CP15_CONTROL_I_BIT; } rt_base_t rt_hw_cpu_dcache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_C_BIT; + return CtrlReg & XREG_CP15_CONTROL_C_BIT; } diff --git a/libcpu/arm/zynqmp-r5/cpu.c b/libcpu/arm/zynqmp-r5/cpu.c index a2e3b85dc7..d0f1b0204c 100644 --- a/libcpu/arm/zynqmp-r5/cpu.c +++ b/libcpu/arm/zynqmp-r5/cpu.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> diff --git a/libcpu/arm/zynqmp-r5/gic.c b/libcpu/arm/zynqmp-r5/gic.c index 3acefbc9bf..67360d93ce 100644 --- a/libcpu/arm/zynqmp-r5/gic.c +++ b/libcpu/arm/zynqmp-r5/gic.c @@ -1,18 +1,18 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rtthread.h> #include "board.h" #include "gic.h" -/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is +/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is * compliant to the GICv1 architecture specification. */ struct arm_gic @@ -39,12 +39,12 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) static unsigned int _gic_max_irq; @@ -206,4 +206,4 @@ void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/gic.h b/libcpu/arm/zynqmp-r5/gic.h index 7cffec3f88..3f591c0652 100644 --- a/libcpu/arm/zynqmp-r5/gic.h +++ b/libcpu/arm/zynqmp-r5/gic.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __GIC_H__ diff --git a/libcpu/arm/zynqmp-r5/interrupt.c b/libcpu/arm/zynqmp-r5/interrupt.c index 12ba638345..fa37674761 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.c +++ b/libcpu/arm/zynqmp-r5/interrupt.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> @@ -130,4 +130,4 @@ void rt_hw_interrupt_trigger(int vector) void rt_hw_interrupt_clear(int vector) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/interrupt.h b/libcpu/arm/zynqmp-r5/interrupt.h index 71459fa0a9..35490a047b 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.h +++ b/libcpu/arm/zynqmp-r5/interrupt.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __INTERRUPT_H__ diff --git a/libcpu/arm/zynqmp-r5/mpu.c b/libcpu/arm/zynqmp-r5/mpu.c index dc33a5fe65..fc2ae7dc44 100644 --- a/libcpu/arm/zynqmp-r5/mpu.c +++ b/libcpu/arm/zynqmp-r5/mpu.c @@ -14,8 +14,8 @@ * * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- -* 5.00 pkp 02/20/14 First release -* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map +* 5.00 pkp 02/20/14 First release +* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a * part of processor boot process * 6.2 mus 01/27/17 Updated to support IAR compiler @@ -46,37 +46,37 @@ typedef rt_uint32_t u32; /************************** Variable Definitions *****************************/ static const struct { - u64 size; - unsigned int encoding; + u64 size; + unsigned int encoding; }region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, }; /************************** Function Prototypes ******************************/ @@ -96,129 +96,129 @@ static void Xil_DisableMPURegions(void); * MPU with default memory attributes for rest of address range for Cortex R5 * processor. * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ void Init_MPU(void) { - u32 Addr; - u32 RegSize = 0U; - u32 Attrib; - u32 RegNum = 0, i, Offset = 0; - u64 size; + u32 Addr; + u32 RegSize = 0U; + u32 Attrib; + u32 RegNum = 0, i, Offset = 0; + u64 size; - Xil_DisableMPURegions(); + Xil_DisableMPURegions(); - Addr = 0x00000000U; -#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR - /* If the DDR is present, configure region as per DDR size */ - size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; - if (size < 0x80000000) { - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - RegSize = region_size[i].encoding; + Addr = 0x00000000U; +#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR + /* If the DDR is present, configure region as per DDR size */ + size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; + if (size < 0x80000000) { + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + RegSize = region_size[i].encoding; - /* Check if DDR size is in power of 2*/ - if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) - Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; - if (region_size[i].size > (size + Offset + 1)) { - rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ - in power of 2. As processor allocates MPU regions size \ - in power of 2, address range %llx to %x has been \ - incorrectly mapped as normal memory \n", \ - region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); - } - break; - } - } - } else { - /* if the DDR size is > 2GB, truncate it to 2GB */ - RegSize = REGION_2G; - } + /* Check if DDR size is in power of 2*/ + if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) + Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; + if (region_size[i].size > (size + Offset + 1)) { + rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ + in power of 2. As processor allocates MPU regions size \ + in power of 2, address range %llx to %x has been \ + incorrectly mapped as normal memory \n", \ + region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); + } + break; + } + } + } else { + /* if the DDR size is > 2GB, truncate it to 2GB */ + RegSize = REGION_2G; + } #else - /* For DDRless system, configure region for TCM */ - RegSize = REGION_256K; + /* For DDRless system, configure region for TCM */ + RegSize = REGION_256K; #endif - Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. - * 512 MB - LPD-PL interface - * 256 MB - FPD-PL (HPM0) interface - * 256 MB - FPD-PL (HPM1) interface - */ - Addr = 0x80000000; - RegSize = REGION_1G; - Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. + * 512 MB - LPD-PL interface + * 256 MB - FPD-PL (HPM0) interface + * 256 MB - FPD-PL (HPM1) interface + */ + Addr = 0x80000000; + RegSize = REGION_1G; + Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ - Addr = 0xC0000000U; - RegSize = REGION_512M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ + Addr = 0xC0000000U; + RegSize = REGION_512M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ - Addr = 0xE0000000U; - RegSize = REGION_256M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ + Addr = 0xE0000000U; + RegSize = REGION_256M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ - Addr = 0xF8000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ + Addr = 0xF8000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ - Addr = 0xF9000000U; - RegSize = REGION_1M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ + Addr = 0xF9000000U; + RegSize = REGION_1M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ - Addr = 0xFD000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ + Addr = 0xFD000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ - Addr = 0xFE000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ + Addr = 0xFE000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, - * CSU, PMU, TCM, OCM - */ - Addr = 0xFF000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, + * CSU, PMU, TCM, OCM + */ + Addr = 0xFF000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ - Addr = 0xFFFC0000U; - RegSize = REGION_256K; - Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ + Addr = 0xFFFC0000U; + RegSize = REGION_256K; + Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - /* A total of 10 MPU regions are allocated with another 6 being free for users */ + /* A total of 10 MPU regions are allocated with another 6 being free for users */ } @@ -228,28 +228,28 @@ void Init_MPU(void) * of the region size defined by reg_size having attributes attrib of region number * reg_num * -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @param reg_size specifies the size for that memory region. -* @param reg_num specifies the number for that memory region. -* @return None. +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. * * ******************************************************************************/ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) { - u32 Local_reg_size = reg_size; + u32 Local_reg_size = reg_size; - Local_reg_size = Local_reg_size<<1U; - Local_reg_size |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); - isb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ - dsb(); - isb(); /* synchronize context on this processor */ + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); + isb(); /* synchronize context on this processor */ } @@ -257,29 +257,29 @@ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) * * Disable all the MPU regions if any of them is enabled * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ static void Xil_DisableMPURegions(void) { - u32 Temp = 0U; - u32 Index = 0U; - for (Index = 0; Index <= 15; Index++) { - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); + u32 Temp = 0U; + u32 Index = 0U; + for (Index = 0; Index <= 15; Index++) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); #if defined (__GNUC__) - Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); #elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); #endif - Temp &= (~REGION_EN); - dsb(); - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); - dsb(); - isb(); - } + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + } } diff --git a/libcpu/arm/zynqmp-r5/stack.c b/libcpu/arm/zynqmp-r5/stack.c index c8ba712c49..20a6e23987 100644 --- a/libcpu/arm/zynqmp-r5/stack.c +++ b/libcpu/arm/zynqmp-r5/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/trap.c b/libcpu/arm/zynqmp-r5/trap.c index 7a48a3c190..64d4cbf5e8 100644 --- a/libcpu/arm/zynqmp-r5/trap.c +++ b/libcpu/arm/zynqmp-r5/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h index f3f978d9eb..7a65ef6ece 100644 --- a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h +++ b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h @@ -36,7 +36,7 @@ * * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- -* 5.00 pkp 05/21/14 First release +* 5.00 pkp 05/21/14 First release * 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors * </pre> * @@ -59,38 +59,38 @@ extern "C" { /***************** Macros (Inline Functions) Definitions ********************/ /* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s +#define stringify(s) tostring(s) +#define tostring(s) #s #if defined (__aarch64__) /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) -#define cpsiei() //__asm__ __volatile__("cpsie i\n") -#define cpsidi() //__asm__ __volatile__("cpsid i\n") +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") -#define cpsief() //__asm__ __volatile__("cpsie f\n") -#define cpsidf() //__asm__ __volatile__("cpsid f\n") +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) /*__asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - )*/ +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ -#define mfgpr(rn) /*({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - })*/ +#define mfgpr(rn) /*({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ /* memory synchronization operations */ @@ -105,13 +105,13 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #define mfelrel3() ({u64 rval = 0U; \ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ @@ -123,39 +123,39 @@ extern "C" { #else /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) -#define mfgpr(rn) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfgpr(rn) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) /* memory synchronization operations */ @@ -170,72 +170,72 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #endif -#define ldrb(adr) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldrb(adr) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) /* Count leading zeroes (clz) */ -#define clz(arg) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) +#define clz(arg) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) #if defined (__aarch64__) -#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) -#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) -#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) -#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) -#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ -#define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) -#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) #else /* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); -#define mfcp(rn) ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcp(rn) ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #endif /************************** Variable Definitions ****************************/ diff --git a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h index 263f213567..9c0ae2b440 100644 --- a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h +++ b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h @@ -23,86 +23,86 @@ * </pre> * ******************************************************************************/ -#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ -#define XREG_CORTEXR5_H /* by using protection macros */ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr /* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 /* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 /* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20U -#define XREG_CPSR_MODE_BITS 0x1FU -#define XREG_CPSR_SYSTEM_MODE 0x1FU -#define XREG_CPSR_UNDEFINED_MODE 0x1BU -#define XREG_CPSR_DATA_ABORT_MODE 0x17U -#define XREG_CPSR_SVC_MODE 0x13U -#define XREG_CPSR_IRQ_MODE 0x12U -#define XREG_CPSR_FIQ_MODE 0x11U -#define XREG_CPSR_USER_MODE 0x10U +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U -#define XREG_CPSR_IRQ_ENABLE 0x80U -#define XREG_CPSR_FIQ_ENABLE 0x40U +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U -#define XREG_CPSR_N_BIT 0x80000000U -#define XREG_CPSR_Z_BIT 0x40000000U -#define XREG_CPSR_C_BIT 0x20000000U -#define XREG_CPSR_V_BIT 0x10000000U +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U /*MPU region definitions*/ #define REGION_32B 0x00000004U @@ -138,99 +138,99 @@ extern "C" { -#define SHAREABLE 0x00000004U /*shareable */ -#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ -#define DEVICE_SHARED 0x00000001U /*device, shareable*/ -#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ -#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ -#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ -#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ -#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ -#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ -#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ -#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ -#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ /* inner and outer cache policies can be combined for different combinations */ -#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ -#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ -#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ -#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ -#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ -#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ -#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ -#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ -#define NO_ACCESS (0x00000000U<<8U) /*No access*/ -#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ -#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ -#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ -#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ -#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ -#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ /* CP15 defines */ /* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" -#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" /* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" /* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000U -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U -#define XREG_CP15_CONTROL_EE_BIT 0x02000000U -#define XREG_CP15_CONTROL_HA_BIT 0x00020000U -#define XREG_CP15_CONTROL_RR_BIT 0x00004000U -#define XREG_CP15_CONTROL_V_BIT 0x00002000U -#define XREG_CP15_CONTROL_I_BIT 0x00001000U -#define XREG_CP15_CONTROL_Z_BIT 0x00000800U -#define XREG_CP15_CONTROL_SW_BIT 0x00000400U -#define XREG_CP15_CONTROL_B_BIT 0x00000080U -#define XREG_CP15_CONTROL_C_BIT 0x00000004U -#define XREG_CP15_CONTROL_A_BIT 0x00000002U -#define XREG_CP15_CONTROL_M_BIT 0x00000001U +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U /* C2 Register Defines */ /* Not Used */ @@ -241,55 +241,55 @@ extern "C" { /* Not Used */ /* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" /* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" -#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" -#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" -#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" -#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" /* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" /* The CP15 register access below has been deprecated in favor of the new * isb instruction in Cortex R5. */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" -#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" -#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" /* The next two CP15 register accesses below have been deprecated in favor * of the new dsb and dmb instructions in Cortex R5. */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" /* C8 Register Defines */ /* Not Used */ @@ -297,24 +297,24 @@ extern "C" { /* C9 Register Defines */ -#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" -#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" -#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" /* C10 Register Defines */ /* Not used */ @@ -326,90 +326,90 @@ extern "C" { /* Not used */ /* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" /* C14 Register Defines */ /* not used */ /* C15 Register Defines */ -#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" /* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 /* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24U) -#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) -#define XREG_FPSID_ARCH_BIT (16U) -#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8U) -#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4U) -#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0U) -#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) /* FPSCR bits */ -#define XREG_FPSCR_N_BIT (0X00000001U << 31U) -#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) -#define XREG_FPSCR_C_BIT (0X00000001U << 29U) -#define XREG_FPSCR_V_BIT (0X00000001U << 28U) -#define XREG_FPSCR_QC (0X00000001U << 27U) -#define XREG_FPSCR_AHP (0X00000001U << 26U) -#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) -#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) -#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) -#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) -#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) -#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) -#define XREG_FPSCR_RMODE_BIT (22U) -#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20U) -#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16U) -#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (0X00000001U << 7U) -#define XREG_FPSCR_IXC (0X00000001U << 4U) -#define XREG_FPSCR_UFC (0X00000001U << 3U) -#define XREG_FPSCR_OFC (0X00000001U << 2U) -#define XREG_FPSCR_DZC (0X00000001U << 1U) -#define XREG_FPSCR_IOC (0X00000001U << 0U) +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) /* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28U) -#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24U) -#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20U) -#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16U) -#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12U) -#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8U) -#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4U) -#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0U) -#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) /* FPEXC bits */ -#define XREG_FPEXC_EX (0X00000001U << 31U) -#define XREG_FPEXC_EN (0X00000001U << 30U) -#define XREG_FPEXC_DEX (0X00000001U << 29U) +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) #ifdef __cplusplus diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index fdd8a4d56c..1d4ea5adfa 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -25,7 +25,7 @@ */ RT_WEAK void rt_hw_cpu_reset() { - /*NOTREACHED*/ + /*NOTREACHED*/ } /** @@ -34,9 +34,9 @@ RT_WEAK void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - RT_ASSERT(0); + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c index 14ef865448..66fb6ca8b9 100644 --- a/libcpu/avr32/uc3/serial.c +++ b/libcpu/avr32/uc3/serial.c @@ -24,8 +24,8 @@ struct rt_device _rt_usart_device; struct avr32_serial_int_rx _rt_usart_rx; struct avr32_serial_device uart = { - .uart_device = (avr32_usart_t *) &AVR32_USART1, - .int_rx = &_rt_usart_rx + .uart_device = (avr32_usart_t *) &AVR32_USART1, + .int_rx = &_rt_usart_rx }; /** @@ -36,163 +36,163 @@ struct avr32_serial_device uart = /* RT-Thread Device Interface */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; + struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = 0; - uart->int_rx->save_index = 0; - } + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; - ptr = buffer; - err_code = RT_EOK; - uart = (struct avr32_serial_device*)dev->user_data; + ptr = buffer; + err_code = RT_EOK; + uart = (struct avr32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - /* read a character */ - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size--; + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; - /* move to next position */ - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (usart_test_hit(uart->uart_device)) - { - *ptr = uart->uart_device->rhr & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (usart_test_hit(uart->uart_device)) + { + *ptr = uart->uart_device->rhr & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct avr32_serial_device*)dev->user_data; + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct avr32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx, does not support */ - RT_ASSERT(0); - } - else - { - /* polling mode */ - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - usart_putchar(uart->uart_device, (int) *ptr); + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + usart_putchar(uart->uart_device, (int) *ptr); - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - usart_bw_write_char(uart->uart_device, (int) *ptr); + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + usart_bw_write_char(uart->uart_device, (int) *ptr); - ++ptr; --size; - } - } - } + ++ptr; --size; + } + } + } - /* set error code */ - rt_set_errno(err_code); + /* set error code */ + rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - struct avr32_serial_device* uart; + struct avr32_serial_device* uart; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - uart = (struct avr32_serial_device*)dev->user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; + uart = (struct avr32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -201,77 +201,77 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(void) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; - rt_base_t level; + struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; + rt_base_t level; - if (usart_test_hit(uart->uart_device)) - { - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + if (usart_test_hit(uart->uart_device)) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* save character */ - uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* invoke callback */ - if (_rt_usart_device.rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (_rt_usart_device.rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); - } - } - else - { - usart_reset_status(uart->uart_device); - } + _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); + } + } + else + { + usart_reset_status(uart->uart_device); + } } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h index a17338701b..fef65a12be 100644 --- a/libcpu/avr32/uc3/serial.h +++ b/libcpu/avr32/uc3/serial.h @@ -21,29 +21,29 @@ #include "compiler.h" #include "usart.h" -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_DMA_NODE_SIZE 4 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 /* data node for Tx Mode */ struct avr32_serial_data_node { - rt_uint8_t *data_ptr; - rt_size_t data_size; - struct avr32_serial_data_node *next, *prev; + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct avr32_serial_data_node *next, *prev; }; struct avr32_serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct avr32_serial_device { - avr32_usart_t *uart_device; + avr32_usart_t *uart_device; - /* rx structure */ - struct avr32_serial_int_rx* int_rx; + /* rx structure */ + struct avr32_serial_int_rx* int_rx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c index dd43b5edbc..dee1161c12 100644 --- a/libcpu/avr32/uc3/stack.c +++ b/libcpu/avr32/uc3/stack.c @@ -30,28 +30,28 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0; /* r8 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r12 */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = (unsigned long)tentry; /* entry point, pc */ - *(--stk) = 0x00600000; /* sr */ - *(--stk) = 0; /* r0 */ - *(--stk) = 0; /* r1 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r7 */ + stk = (unsigned long *)stack_addr; + *(stk) = 0; /* r8 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r12 */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = 0x00600000; /* sr */ + *(--stk) = 0; /* r0 */ + *(--stk) = 0; /* r1 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r7 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/blackfin/bf53x/cpuport.c b/libcpu/blackfin/bf53x/cpuport.c index 91cfaeb403..2d69ccc99a 100644 --- a/libcpu/blackfin/bf53x/cpuport.c +++ b/libcpu/blackfin/bf53x/cpuport.c @@ -8,8 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes - * 2012-02-13 mojingxian first version + * Date Author Notes + * 2012-02-13 mojingxian first version */ #include <rtthread.h> @@ -23,10 +23,10 @@ rt_uint32_t rt_thread_switch_interrupt_flag; * initializes stack of thread */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { unsigned char i; - unsigned long *stk; + unsigned long *stk; stk = (unsigned long *)stack_addr; /* Load stack pointer */ diff --git a/libcpu/blackfin/bf53x/serial.c b/libcpu/blackfin/bf53x/serial.c index b8a4c52570..4a6484a647 100644 --- a/libcpu/blackfin/bf53x/serial.c +++ b/libcpu/blackfin/bf53x/serial.c @@ -29,206 +29,206 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - return RT_EOK; + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - - return RT_EOK; +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); +{ + RT_ASSERT(dev != RT_NULL); - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - *ptr = uart->uart_device->rbr_thr & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + *ptr = uart->uart_device->rbr_thr & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; + -- size; - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = '\r'; - } + /* move to next position */ + uart->int_tx->save_index ++; - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = (*ptr & 0xFF); + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - ++ptr; --size; - } - } + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = '\r'; + } - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = (*ptr & 0xFF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; } /* @@ -236,49 +236,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); + } - /* save on rx buffer */ - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); - } + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h index 8d85193634..7969c5514e 100644 --- a/libcpu/blackfin/bf53x/serial.h +++ b/libcpu/blackfin/bf53x/serial.h @@ -4,49 +4,49 @@ #include <rthw.h> #include <rtthread.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register - volatile rt_uint16_t reserved0; - volatile rt_uint16_t reserved1; - volatile rt_uint16_t reserved2; - volatile rt_uint16_t reserved3; - volatile rt_uint16_t reserved4; - volatile rt_uint16_t reserved5; - volatile rt_uint16_t reserved6; - volatile rt_uint16_t reserved7; - volatile rt_uint16_t reserved8; - volatile rt_uint16_t lsr; //line status register + volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register + volatile rt_uint16_t reserved0; + volatile rt_uint16_t reserved1; + volatile rt_uint16_t reserved2; + volatile rt_uint16_t reserved3; + volatile rt_uint16_t reserved4; + volatile rt_uint16_t reserved5; + volatile rt_uint16_t reserved6; + volatile rt_uint16_t reserved7; + volatile rt_uint16_t reserved8; + volatile rt_uint16_t lsr; //line status register }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/c-sky/ck802/core_ck802.h b/libcpu/c-sky/ck802/core_ck802.h index badae8c0ff..e7185131e4 100644 --- a/libcpu/c-sky/ck802/core_ck802.h +++ b/libcpu/c-sky/ck802/core_ck802.h @@ -133,24 +133,24 @@ extern "C" { */ /** - \brief ���ʴ�����״̬�Ĵ���(PSR)�������嶨��. + \brief 访问处理器状态寄存器(PSR)的联合体定义. */ typedef union { struct { - uint32_t C: 1; /*!< bit: 0 �����룯��λλ */ - uint32_t _reserved0: 5; /*!< bit: 2.. 5 ���� */ - uint32_t IE: 1; /*!< bit: 6 �ж���Ч����λ */ - uint32_t IC: 1; /*!< bit: 7 �жϿ���λ */ - uint32_t EE: 1; /*!< bit: 8 �쳣��Ч����λ */ - uint32_t MM: 1; /*!< bit: 9 �������쳣�ڸ�λ */ - uint32_t _reserved1: 6; /*!< bit: 10..15 ���� */ - uint32_t VEC: 8; /*!< bit: 16..23 �쳣�¼�����ֵ */ - uint32_t _reserved2: 7; /*!< bit: 24..30 ���� */ - uint32_t S: 1; /*!< bit: 31 �����û�ģʽ����λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t C: 1; /*!< bit: 0 条件码／进位位 */ + uint32_t _reserved0: 5; /*!< bit: 2.. 5 保留 */ + uint32_t IE: 1; /*!< bit: 6 中断有效控制位 */ + uint32_t IC: 1; /*!< bit: 7 中断控制位 */ + uint32_t EE: 1; /*!< bit: 8 异常有效控制位 */ + uint32_t MM: 1; /*!< bit: 9 不对齐异常掩盖位 */ + uint32_t _reserved1: 6; /*!< bit: 10..15 保留 */ + uint32_t VEC: 8; /*!< bit: 16..23 异常事件向量值 */ + uint32_t _reserved2: 7; /*!< bit: 24..30 保留 */ + uint32_t S: 1; /*!< bit: 31 超级用户模式设置位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PSR_Type; /* PSR Register Definitions */ @@ -176,21 +176,21 @@ typedef union #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */ /** - \brief ���ʸ��ٻ������üĴ���(CCR, CR<18, 0>)�������嶨��. + \brief 访问高速缓存配置寄存器(CCR, CR<18, 0>)的联合体定义. */ typedef union { struct { - uint32_t MP: 1; /*!< bit: 0 �ڴ汣������λ */ - uint32_t _reserved0: 6; /*!< bit: 1.. 6 ���� */ - uint32_t BE: 1; /*!< bit: 7 Endianģʽ */ - uint32_t SCK: 3; /*!< bit: 8..10 ϵͳ�ʹ�������ʱ�ӱ� */ - uint32_t _reserved1: 2; /*!< bit: 11..12 ���� */ - uint32_t BE_V2: 1; /*!< bit: 13 V2�汾��С�� */ - uint32_t _reserved2: 18; /*!< bit: 14..31 ���� */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t MP: 1; /*!< bit: 0 内存保护设置位 */ + uint32_t _reserved0: 6; /*!< bit: 1.. 6 保留 */ + uint32_t BE: 1; /*!< bit: 7 Endian模式 */ + uint32_t SCK: 3; /*!< bit: 8..10 系统和处理器的时钟比 */ + uint32_t _reserved1: 2; /*!< bit: 11..12 保留 */ + uint32_t BE_V2: 1; /*!< bit: 13 V2版本大小端 */ + uint32_t _reserved2: 18; /*!< bit: 14..31 保留 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } CCR_Type; /* CCR Register Definitions */ @@ -207,38 +207,38 @@ typedef union #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */ /** - \brief ���ʿɸ��ͷ���Ȩ�����üĴ���(CAPR, CR<19,0>)�������嶨��.. + \brief 访问可高缓和访问权限配置寄存器(CAPR, CR<19,0>)的联合体定义.. */ typedef union { struct { - uint32_t X0: 1; /*!< bit: 0 ����ִ����������λ */ - uint32_t X1: 1; /*!< bit: 1 ����ִ����������λ */ - uint32_t X2: 1; /*!< bit: 2 ����ִ����������λ */ - uint32_t X3: 1; /*!< bit: 3 ����ִ����������λ */ - uint32_t X4: 1; /*!< bit: 4 ����ִ����������λ */ - uint32_t X5: 1; /*!< bit: 5 ����ִ����������λ */ - uint32_t X6: 1; /*!< bit: 6 ����ִ����������λ */ - uint32_t X7: 1; /*!< bit: 7 ����ִ����������λ */ - uint32_t AP0: 2; /*!< bit: 8.. 9 ����Ȩ������λ */ - uint32_t AP1: 2; /*!< bit: 10..11 ����Ȩ������λ */ - uint32_t AP2: 2; /*!< bit: 12..13 ����Ȩ������λ */ - uint32_t AP3: 2; /*!< bit: 14..15 ����Ȩ������λ */ - uint32_t AP4: 2; /*!< bit: 16..17 ����Ȩ������λ */ - uint32_t AP5: 2; /*!< bit: 18..19 ����Ȩ������λ */ - uint32_t AP6: 2; /*!< bit: 20..21 ����Ȩ������λ */ - uint32_t AP7: 2; /*!< bit: 22..23 ����Ȩ������λ */ - uint32_t S0: 1; /*!< bit: 24 ��ȫ��������λ */ - uint32_t S1: 1; /*!< bit: 25 ��ȫ��������λ */ - uint32_t S2: 1; /*!< bit: 26 ��ȫ��������λ */ - uint32_t S3: 1; /*!< bit: 27 ��ȫ��������λ */ - uint32_t S4: 1; /*!< bit: 28 ��ȫ��������λ */ - uint32_t S5: 1; /*!< bit: 29 ��ȫ��������λ */ - uint32_t S6: 1; /*!< bit: 30 ��ȫ��������λ */ - uint32_t S7: 1; /*!< bit: 31 ��ȫ��������λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t X0: 1; /*!< bit: 0 不可执行属性设置位 */ + uint32_t X1: 1; /*!< bit: 1 不可执行属性设置位 */ + uint32_t X2: 1; /*!< bit: 2 不可执行属性设置位 */ + uint32_t X3: 1; /*!< bit: 3 不可执行属性设置位 */ + uint32_t X4: 1; /*!< bit: 4 不可执行属性设置位 */ + uint32_t X5: 1; /*!< bit: 5 不可执行属性设置位 */ + uint32_t X6: 1; /*!< bit: 6 不可执行属性设置位 */ + uint32_t X7: 1; /*!< bit: 7 不可执行属性设置位 */ + uint32_t AP0: 2; /*!< bit: 8.. 9 访问权限设置位 */ + uint32_t AP1: 2; /*!< bit: 10..11 访问权限设置位 */ + uint32_t AP2: 2; /*!< bit: 12..13 访问权限设置位 */ + uint32_t AP3: 2; /*!< bit: 14..15 访问权限设置位 */ + uint32_t AP4: 2; /*!< bit: 16..17 访问权限设置位 */ + uint32_t AP5: 2; /*!< bit: 18..19 访问权限设置位 */ + uint32_t AP6: 2; /*!< bit: 20..21 访问权限设置位 */ + uint32_t AP7: 2; /*!< bit: 22..23 访问权限设置位 */ + uint32_t S0: 1; /*!< bit: 24 安全属性设置位 */ + uint32_t S1: 1; /*!< bit: 25 安全属性设置位 */ + uint32_t S2: 1; /*!< bit: 26 安全属性设置位 */ + uint32_t S3: 1; /*!< bit: 27 安全属性设置位 */ + uint32_t S4: 1; /*!< bit: 28 安全属性设置位 */ + uint32_t S5: 1; /*!< bit: 29 安全属性设置位 */ + uint32_t S6: 1; /*!< bit: 30 安全属性设置位 */ + uint32_t S7: 1; /*!< bit: 31 安全属性设置位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } CAPR_Type; /* CAPR Register Definitions */ @@ -315,18 +315,18 @@ typedef union #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */ /** - \brief ���ʱ��������ƼĴ���(PACR, CR<20,0>)�������嶨��. + \brief 访问保护区控制寄存器(PACR, CR<20,0>)的联合体定义. */ typedef union { struct { - uint32_t E: 1; /*!< bit: 0 ��������Ч���� */ - uint32_t Size: 5; /*!< bit: 1.. 5 ��������С */ - uint32_t _reserved0: 4; /*!< bit: 6.. 9 ���� */ - uint32_t base_addr: 22; /*!< bit: 10..31 ��������ַ�ĸ�λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t E: 1; /*!< bit: 0 保护区有效设置 */ + uint32_t Size: 5; /*!< bit: 1.. 5 保护区大小 */ + uint32_t _reserved0: 4; /*!< bit: 6.. 9 保留 */ + uint32_t base_addr: 22; /*!< bit: 10..31 保护区地址的高位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PACR_Type; /* PACR Register Definitions */ @@ -340,16 +340,16 @@ typedef union #define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */ /** - \brief ���ʱ�����ѡ��Ĵ���(PRSR,CR<21,0>)�������嶨��. + \brief 访问保护区选择寄存器(PRSR,CR<21,0>)的联合体定义. */ typedef union { struct { - uint32_t RID: 3; /*!< bit: 0.. 2 ����������ֵ */ - uint32_t _reserved0: 30; /*!< bit: 3..31 ���� */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t RID: 3; /*!< bit: 0.. 2 保护区索引值 */ + uint32_t _reserved0: 30; /*!< bit: 3..31 保留 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PRSR_Type; /* PRSR Register Definitions */ @@ -367,30 +367,30 @@ typedef union */ /** - \brief ����ʸ���жϿ������Ľṹ��. + \brief 访问矢量中断控制器的结构体. */ typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) �ж�ʹ�����üĴ��� */ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) 中断使能设置寄存器 */ uint32_t RESERVED0[15U]; - __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) �жϵ��Ļ������üĴ��� */ + __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) 中断低功耗唤醒设置寄存器 */ uint32_t RESERVED1[15U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) �ж�ʹ������Ĵ��� */ + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) 中断使能清除寄存器 */ uint32_t RESERVED2[15U]; - __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) �жϵ��Ļ�������Ĵ��� */ + __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) 中断低功耗唤醒清除寄存器 */ uint32_t RESERVED3[15U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) �жϵȴ����üĴ��� */ + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) 中断等待设置寄存器 */ uint32_t RESERVED4[15U]; - __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) ��ȫ�ж�ʹ�����üĴ��� */ + __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) 安全中断使能设置寄存器 */ uint32_t RESERVED5[15U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) �жϵȴ�����Ĵ��� */ + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) 中断等待清除寄存器 */ uint32_t RESERVED6[31U]; - __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) �ж���Ӧ״̬�Ĵ��� */ + __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) 中断响应状态寄存器 */ uint32_t RESERVED7[63U]; - __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) �ж����ȼ����üĴ��� */ + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) 中断优先级设置寄存器 */ uint32_t RESERVED8[504U]; - __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) �ж�״̬�Ĵ��� */ - __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) �ж����ȼ���ֵ�Ĵ��� */ + __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) 中断状态寄存器 */ + __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) 中断优先级阈值寄存器 */ } NVIC_Type; /*@} end of group CSI_NVIC */ @@ -403,14 +403,14 @@ typedef struct */ /** - \brief ����ϵͳ��ʱ�������ݽṹ. + \brief 访问系统计时器的数据结构. */ typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) ����״̬�Ĵ��� */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) ����ֵ�Ĵ��� */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) ��ǰֵ�Ĵ��� */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) У�Ĵ��� */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) 控制状态寄存器 */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) 回填值寄存器 */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) 当前值寄存器 */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) 校准寄存器 */ } CORET_Type; /* CORET Control / Status Register Definitions */ @@ -454,7 +454,7 @@ typedef struct */ /** - \brief ����DCC�����ݽṹ. + \brief 访问DCC的数据结构. */ typedef struct { @@ -464,8 +464,8 @@ typedef struct uint32_t RESERVED1[6U]; union { - __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) ���ݽ����Ĵ��� CPU��*/ - __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) ���ݽ����Ĵ��� CPUд*/ + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) 数据交换寄存器 CPU读*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) 数据交换寄存器 CPU写*/ }; } DCC_Type; diff --git a/libcpu/ia32/__udivsi3.c b/libcpu/ia32/__udivsi3.c index 5a5622f883..ced90b5aba 100644 --- a/libcpu/ia32/__udivsi3.c +++ b/libcpu/ia32/__udivsi3.c @@ -12,31 +12,31 @@ uint32_t __udivsi3(uint32_t num, uint32_t den) { - uint32_t quot = 0, qbit = 1; + uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* If trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* If trap returns... */ + } - /* Left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* Left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return quot; + return quot; } diff --git a/libcpu/ia32/__umodsi3.c b/libcpu/ia32/__umodsi3.c index d47fe3d295..ddc5db5488 100644 --- a/libcpu/ia32/__umodsi3.c +++ b/libcpu/ia32/__umodsi3.c @@ -12,31 +12,31 @@ uint32_t __umodsi3(uint32_t num, uint32_t den) { - register uint32_t quot = 0, qbit = 1; + register uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* if trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* if trap returns... */ + } - /* left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return num; + return num; } diff --git a/libcpu/ia32/cpuport.c b/libcpu/ia32/cpuport.c index 69032c2f87..2e0380d9f8 100644 --- a/libcpu/ia32/cpuport.c +++ b/libcpu/ia32/cpuport.c @@ -7,7 +7,7 @@ * Date Author Notes * 2021/02/19 Bernard Implement rt_hw_context_switch_interrupt in C */ - + #include <rthw.h> #include <rtthread.h> @@ -43,35 +43,35 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(--stk) = (unsigned long)parameter; - *(--stk) = (unsigned long)texit; - *(--stk) = 0x200; /*flags*/ - *(--stk) = 0x08; /*cs*/ - *(--stk) = (unsigned long)tentry; /*eip*/ - *(--stk) = 0; /*irqno*/ - *(--stk) = 0x10; /*ds*/ - *(--stk) = 0x10; /*es*/ - *(--stk) = 0; /*eax*/ - *(--stk) = 0; /*ecx*/ - *(--stk) = 0; /*edx*/ - *(--stk) = 0; /*ebx*/ - *(--stk) = 0; /*esp*/ - *(--stk) = 0; /*ebp*/ - *(--stk) = 0; /*esi*/ - *(--stk) = 0; /*edi*/ + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index d597848c52..473bf7714a 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -7,7 +7,7 @@ * Date Author Notes * 2015/9/15 Bernard Update to new interrupt framework. */ - + #include <rthw.h> #include <rtthread.h> @@ -74,7 +74,7 @@ void rt_hw_isr(int vector) void rt_hw_interrupt_init(void) { int idx; - + rt_hw_idt_init(); rt_hw_pic_init(); diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 172a078273..c77a20c890 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes */ - + #include <rthw.h> #include <rtthread.h> @@ -18,7 +18,7 @@ struct Gatedesc idt[256] = { {0}, }; struct Pseudodesc idt_pd = { - 0, sizeof(idt) - 1, (unsigned long) idt, + 0, sizeof(idt) - 1, (unsigned long) idt, }; /* exception and interrupt handler table */ @@ -37,36 +37,36 @@ extern void rt_hw_interrupt_handle(int vector, void* param); * */ void rt_hw_idt_init(void) -{ - extern void Xdefault(void); - int i, j, func; +{ + extern void Xdefault(void); + int i, j, func; + + // install a default handler + for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) + SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + + /*install trap handler*/ + for(i = 0; i < 16; i++) + { + func = (int)trap_func[i]; + SETGATE(idt[i], 0, GD_KT, func, 0); + } - // install a default handler - for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) - SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + func = (int)trap_func[3]; + SETGATE(idt[3], 0, GD_KT, func, 3); - /*install trap handler*/ - for(i = 0; i < 16; i++) - { - func = (int)trap_func[i]; - SETGATE(idt[i], 0, GD_KT, func, 0); - } + i = 0; - func = (int)trap_func[3]; - SETGATE(idt[3], 0, GD_KT, func, 3); + /*install exteral interrupt handler*/ + for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) + { + func = (int)hdinterrupt_func[i]; + SETGATE(idt[j], 0, GD_KT, func, 0); + i++; + } - i = 0; - - /*install exteral interrupt handler*/ - for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) - { - func = (int)hdinterrupt_func[i]; - SETGATE(idt[j], 0, GD_KT, func, 0); - i++; - } - - // Load the IDT - asm volatile("lidt idt_pd + 2"); + // Load the IDT + asm volatile("lidt idt_pd + 2"); } /** @@ -77,24 +77,24 @@ void rt_hw_idt_init(void) */ void rt_hw_trap_irq(int trapno) { - switch(trapno) - { - case T_DIVIDE: - rt_kprintf("Divide error interrupt\n"); - RT_ASSERT(0); - case T_PGFLT: - rt_kprintf("Page fault interrupt\n"); - RT_ASSERT(0); - case T_GPFLT: - rt_kprintf("General protection interrupt\n"); - RT_ASSERT(0); - case T_DEFAULT: - rt_hw_interrupt_handle(T_DEFAULT, RT_NULL); - return; - } + switch(trapno) + { + case T_DIVIDE: + rt_kprintf("Divide error interrupt\n"); + RT_ASSERT(0); + case T_PGFLT: + rt_kprintf("Page fault interrupt\n"); + RT_ASSERT(0); + case T_GPFLT: + rt_kprintf("General protection interrupt\n"); + RT_ASSERT(0); + case T_DEFAULT: + rt_hw_interrupt_handle(T_DEFAULT, RT_NULL); + return; + } - /*kernel bug if run here*/ - RT_ASSERT(0); + /*kernel bug if run here*/ + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index c66f73b727..8f9a50d89a 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -113,4 +113,4 @@ void rt_hw_interrupt_enable(rt_base_t level) temp = level & 0xffff; asm("LDC %0, FLG": :"r" (temp)); } -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 1b39eea05a..355c05ab39 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,7 +1,7 @@ /* * Assembly Macros For MIPS * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,101 +18,101 @@ /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp, framesize, rpc +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ - .size function,.-function +#define END(function) \ + .end function; \ + .size function,.-function /* * EXPORT - export definition of symbol */ -#define EXPORT(symbol) \ - .globl symbol; \ +#define EXPORT(symbol) \ + .globl symbol; \ symbol: /* * FEXPORT - export definition of a function symbol */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol,@function; \ symbol: /* * Global data declaration with size. */ -#define EXPORTS(name,sz) \ - .globl name; \ - .type name,@object; \ - .size name,sz; \ +#define EXPORTS(name,sz) \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Weak data declaration with size. */ -#define WEXPORT(name,sz) \ - .weakext name; \ - .type name,@object; \ - .size name,sz; \ +#define WEXPORT(name,sz) \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Global data reference with size. */ -#define IMPORT(name, size) \ - .extern name,size +#define IMPORT(name, size) \ + .extern name,size /* * Global zeroed data. */ -#define BSS(name,size) \ - .type name,@object; \ - .comm name,size +#define BSS(name,size) \ + .type name,@object; \ + .comm name,size /* * Local zeroed data. */ -#define LBSS(name,size) \ - .lcomm name,size +#define LBSS(name,size) \ + .lcomm name,size /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ .popsection; -#define ENTRY(name) \ - .globl name; \ - .align 2; \ - .ent name,0; \ +#define ENTRY(name) \ + .globl name; \ + .align 2; \ + .ent name,0; \ name##: /* @@ -122,185 +122,185 @@ symbol = value /* * Size of a register */ -#define SZREG 8 +#define SZREG 8 /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define REG_S sd -#define REG_L ld -#define REG_SUBU dsubu -#define REG_ADDU daddu +#define REG_S sd +#define REG_L ld +#define REG_SUBU dsubu +#define REG_ADDU daddu /* * How to add/sub/load/store/shift C int variables. */ -#define INT_ADD dadd -#define INT_ADDU daddu -#define INT_ADDI daddi -#define INT_ADDIU daddiu -#define INT_SUB dsub -#define INT_SUBU dsubu -#define INT_L ld -#define INT_S sd -#define INT_SLL dsll -#define INT_SLLV dsllv -#define INT_SRL dsrl -#define INT_SRLV dsrlv -#define INT_SRA dsra -#define INT_SRAV dsrav +#define INT_ADD dadd +#define INT_ADDU daddu +#define INT_ADDI daddi +#define INT_ADDIU daddiu +#define INT_SUB dsub +#define INT_SUBU dsubu +#define INT_L ld +#define INT_S sd +#define INT_SLL dsll +#define INT_SLLV dsllv +#define INT_SRL dsrl +#define INT_SRLV dsrlv +#define INT_SRA dsra +#define INT_SRAV dsrav /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define LONG_ADD dadd -#define LONG_ADDU daddu -#define LONG_ADDI daddi -#define LONG_ADDIU daddiu -#define LONG_SUB dsub -#define LONG_SUBU dsubu -#define LONG_L ld -#define LONG_S sd -#define LONG_SP sdp -#define LONG_SLL dsll -#define LONG_SLLV dsllv -#define LONG_SRL dsrl -#define LONG_SRLV dsrlv -#define LONG_SRA dsra -#define LONG_SRAV dsrav +#define LONG_ADD dadd +#define LONG_ADDU daddu +#define LONG_ADDI daddi +#define LONG_ADDIU daddiu +#define LONG_SUB dsub +#define LONG_SUBU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SP sdp +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav -#define LONG .dword -#define LONGSIZE 8 -#define LONGMASK 7 -#define LONGLOG 3 +#define LONG .dword +#define LONGSIZE 8 +#define LONGMASK 7 +#define LONGLOG 3 /* * How to add/sub/load/store/shift pointers. */ -#define PTR_ADD dadd -#define PTR_ADDU daddu -#define PTR_ADDI daddi -#define PTR_ADDIU daddiu -#define PTR_SUB dsub -#define PTR_SUBU dsubu -#define PTR_L ld -#define PTR_S sd -#define PTR_LA dla -#define PTR_LI dli -#define PTR_SLL dsll -#define PTR_SLLV dsllv -#define PTR_SRL dsrl -#define PTR_SRLV dsrlv -#define PTR_SRA dsra -#define PTR_SRAV dsrav +#define PTR_ADD dadd +#define PTR_ADDU daddu +#define PTR_ADDI daddi +#define PTR_ADDIU daddiu +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_LA dla +#define PTR_LI dli +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav -#define PTR_SCALESHIFT 3 +#define PTR_SCALESHIFT 3 -#define PTR .dword -#define PTRSIZE 8 -#define PTRLOG 3 +#define PTR .dword +#define PTRSIZE 8 +#define PTRLOG 3 -#define MFC0 dmfc0 -#define MTC0 dmtc0 +#define MFC0 dmfc0 +#define MTC0 dmtc0 #else /* * Size of a register */ -#define SZREG 4 +#define SZREG 4 /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu /* * How to add/sub/load/store/shift C int variables. */ -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav /* * How to add/sub/load/store/shift C long variables. */ -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 /* * How to add/sub/load/store/shift pointers. */ -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav -#define PTR_SCALESHIFT 2 +#define PTR_SCALESHIFT 2 -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 /* * Some cp0 registers were extended to 64bit for MIPS III. */ -#define MFC0 mfc0 -#define MTC0 mtc0 +#define MFC0 mfc0 +#define MTC0 mtc0 #endif -#define SSNOP sll zero, zero, 1 +#define SSNOP sll zero, zero, 1 #endif /* end of __ASM_H__ */ diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 3da8ecead6..9c9858f5e1 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -164,7 +164,7 @@ void rt_general_exc_dispatch(struct pt_regs *regs) { rt_ubase_t cause, exccode; cause = read_c0_cause(); - exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; + exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; if (exccode == 0) { diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 68107f6235..af9312b5bc 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index 94f664308c..abe3b73945 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index f3bb60662e..0bc6a5f181 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,15 +19,15 @@ #define _ATYPE_ #define _ATYPE32_ #define _ATYPE64_ -#define _CONST64_(x) x +#define _CONST64_(x) x #else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 #ifdef ARCH_MIPS64 -#define _CONST64_(x) x ## L +#define _CONST64_(x) x ## L #else -#define _CONST64_(x) x ## LL +#define _CONST64_(x) x ## LL #endif #endif @@ -38,21 +38,21 @@ #define _ACAST32_ #define _ACAST64_ #else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ #endif /* * Returns the kernel segment base of a given address */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) /* * Returns the physical address of a CKSEGx / XKPHYS address */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) #ifdef ARCH_MIPS64 @@ -61,56 +61,56 @@ * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) -#define KUSEGBASE 0xffffffff00000000 -#define KSEG0BASE 0xffffffff80000000 -#define KSEG1BASE 0xffffffffa0000000 -#define KSEG2BASE 0xffffffffc0000000 -#define KSEG3BASE 0xffffffffe0000000 +#define KUSEGBASE 0xffffffff00000000 +#define KSEG0BASE 0xffffffff80000000 +#define KSEG1BASE 0xffffffffa0000000 +#define KSEG2BASE 0xffffffffc0000000 +#define KSEG3BASE 0xffffffffe0000000 #else -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Map an address to a certain kernel segment */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 /* * Memory segments (32bit kernel mode addresses) * These are the traditional names used in the 32-bit universe. */ -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xa0000000 -#define KSEG2BASE 0xc0000000 -#define KSEG3BASE 0xe0000000 +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xa0000000 +#define KSEG2BASE 0xc0000000 +#define KSEG3BASE 0xe0000000 #endif @@ -118,23 +118,23 @@ /* * Cache modes for XKPHYS address conversion macros */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address @@ -146,20 +146,20 @@ * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #endif #ifndef __ASSEMBLY__ -#define REG8( addr ) (*(volatile u8 *) (addr)) -#define REG16( addr ) (*(volatile u16 *)(addr)) -#define REG32( addr ) (*(volatile u32 *)(addr)) -#define REG64( addr ) (*(volatile u64 *)(addr)) +#define REG8( addr ) (*(volatile u8 *) (addr)) +#define REG16( addr ) (*(volatile u16 *)(addr)) +#define REG32( addr ) (*(volatile u32 *)(addr)) +#define REG64( addr ) (*(volatile u64 *)(addr)) #endif #endif /* _MIPS_ADDRSPACE_H_ */ diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index eb60efaab6..a969f5c751 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -14,7 +14,7 @@ extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); void r4k_cache_init(void) { -// cache_init(dcache_size, cpu_dcache_line_size); +// cache_init(dcache_size, cpu_dcache_line_size); } void r4k_cache_flush_all(void) @@ -31,7 +31,7 @@ void r4k_icache_flush_all(void) void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size > g_mips_core.icache_size) { @@ -39,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -55,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t end, a; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -71,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); @@ -87,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size >= g_mips_core.dcache_size) { @@ -95,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); end = ((addr + size) - 1) & ~(dc_lsize - 1); diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index b57380ac8e..4a459b1ae4 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -102,7 +102,7 @@ enum dma_data_direction #define INDEX_STORE_DATA_D 0x1d #define INDEX_STORE_DATA_S 0x1f -#define cache_op(op, addr) \ +#define cache_op(op, addr) \ __asm__ __volatile__( \ ".set push\n" \ ".set noreorder\n" \ @@ -112,95 +112,95 @@ enum dma_data_direction : \ : "i" (op), "R" (*(unsigned char *)(addr))) -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); static inline void flush_icache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_INVALIDATE_I, addr); + cache_op(INDEX_INVALIDATE_I, addr); } static inline void flush_dcache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_WRITEBACK_INV_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } static inline void flush_icache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_I, addr); + cache_op(HIT_INVALIDATE_I, addr); } static inline void lock_icache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_I, addr); + cache_op(FETCH_AND_LOCK_I, addr); } static inline void lock_dcache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_D, addr); + cache_op(FETCH_AND_LOCK_D, addr); } static inline void flush_dcache_line(rt_ubase_t addr) { - cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } static inline void invalidate_dcache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } static inline void blast_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); } static inline void inv_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, HIT_INVALIDATE_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, HIT_INVALIDATE_D); } static inline void blast_icache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.icache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.icache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.icache_line_size) - cache16_unroll32(addr, INDEX_INVALIDATE_I); + for (addr = start; addr < end; addr += g_mips_core.icache_line_size) + cache16_unroll32(addr, INDEX_INVALIDATE_I); } void r4k_cache_init(void); diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index 8ffeddb277..d5531e35fb 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -24,7 +24,7 @@ typedef struct mips32_core_cfg uint16_t dcache_ways; uint16_t dcache_size; - uint16_t max_tlb_entries; /* number of tlb entry */ + uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h index 50df3746a5..85aa125fa3 100644 --- a/libcpu/mips/common/mips_fpu.h +++ b/libcpu/mips/common/mips_fpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index a13e24b539..a2f6053cf5 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,129 +11,129 @@ #ifndef _MIPS_REGS_H_ #define _MIPS_REGS_H_ #include <rtconfig.h> -#define REG_A0 4 -#define REG_SP 29 -#define REG_GP 28 -#define REG_FP 30 -#define REG_RA 31 +#define REG_A0 4 +#define REG_SP 29 +#define REG_GP 28 +#define REG_FP 30 +#define REG_RA 31 #ifndef ARCH_MIPS64 -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define ta0 $12 -#define t5 $13 -#define ta1 $13 -#define t6 $14 -#define ta2 $14 -#define t7 $15 -#define ta3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define ta0 $12 +#define t5 $13 +#define ta1 $13 +#define t6 $14 +#define ta2 $14 +#define t7 $15 +#define ta3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ #else -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ #endif -#define fv0 $f0 /* return value */ -#define fv0f $f1 -#define fv1 $f2 -#define fv1f $f3 -#define fa0 $f12 /* argument registers */ -#define fa0f $f13 -#define fa1 $f14 -#define fa1f $f15 -#define ft0 $f4 /* caller saved */ -#define ft0f $f5 -#define ft1 $f6 -#define ft1f $f7 -#define ft2 $f8 -#define ft2f $f9 -#define ft3 $f10 -#define ft3f $f11 -#define ft4 $f16 -#define ft4f $f17 -#define ft5 $f18 -#define ft5f $f19 -#define fs0 $f20 /* callee saved */ -#define fs0f $f21 -#define fs1 $f22 -#define fs1f $f23 -#define fs2 $f24 -#define fs2f $f25 -#define fs3 $f26 -#define fs3f $f27 -#define fs4 $f28 -#define fs4f $f29 -#define fs5 $f30 -#define fs5f $f31 +#define fv0 $f0 /* return value */ +#define fv0f $f1 +#define fv1 $f2 +#define fv1f $f3 +#define fa0 $f12 /* argument registers */ +#define fa0f $f13 +#define fa1 $f14 +#define fa1f $f15 +#define ft0 $f4 /* caller saved */ +#define ft0f $f5 +#define ft1 $f6 +#define ft1f $f7 +#define ft2 $f8 +#define ft2f $f9 +#define ft3 $f10 +#define ft3f $f11 +#define ft4 $f16 +#define ft4f $f17 +#define ft5 $f18 +#define ft5f $f19 +#define fs0 $f20 /* callee saved */ +#define fs0f $f21 +#define fs1 $f22 +#define fs1f $f23 +#define fs2 $f24 +#define fs2f $f25 +#define fs3 $f26 +#define fs3f $f27 +#define fs4 $f28 +#define fs4f $f29 +#define fs5 $f30 +#define fs5f $f31 -#define fcr31 $31 /* FPU status register */ +#define fcr31 $31 /* FPU status register */ /* @@ -217,157 +217,157 @@ /* * TX39 Series */ -#define CP0_TX39_CACHE $7 +#define CP0_TX39_CACHE $7 /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_UFR $1 -#define CP1_UNFR $4 -#define CP1_FCCR $25 -#define CP1_FEXR $26 -#define CP1_FENR $28 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) -#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) -#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) -#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) /* * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. */ -#define MIPS_FCCR_CONDX_S 0 -#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) -#define MIPS_FCCR_COND0_S 0 -#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) -#define MIPS_FCCR_COND1_S 1 -#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) -#define MIPS_FCCR_COND2_S 2 -#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) -#define MIPS_FCCR_COND3_S 3 -#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) -#define MIPS_FCCR_COND4_S 4 -#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) -#define MIPS_FCCR_COND5_S 5 -#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) -#define MIPS_FCCR_COND6_S 6 -#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) -#define MIPS_FCCR_COND7_S 7 -#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) /* * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. */ -#define MIPS_FENR_FS_S 2 -#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) /* * FPU Status Register Values */ -#define FPU_CSR_COND_S 23 /* $fcc0 */ -#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) -#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ -#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) #define FPU_CSR_FO 0x00400000 #define FPU_CSR_FN 0x00200000 -#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ -#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) -#define FPU_CSR_COND1_S 25 /* $fcc1 */ -#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) -#define FPU_CSR_COND2_S 26 /* $fcc2 */ -#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) -#define FPU_CSR_COND3_S 27 /* $fcc3 */ -#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) -#define FPU_CSR_COND4_S 28 /* $fcc4 */ -#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) -#define FPU_CSR_COND5_S 29 /* $fcc5 */ -#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) -#define FPU_CSR_COND6_S 30 /* $fcc6 */ -#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) -#define FPU_CSR_COND7_S 31 /* $fcc7 */ -#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) /* * Bits 22:20 of the FPU Status Register will be read as 0, * and should be written as zero. */ -#define FPU_CSR_RSVD (_ULCAST_(7) << 20) +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) -#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) -#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ -#define FPU_CSR_RM 0x00000003 -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 /* * R4x00 interrupt enable / cause bits @@ -396,202 +396,202 @@ /* * Bitfields in the R4xx0 cp0 status register */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 /* * Bitfields in the R[23]000 cp0 status register. */ #define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 /* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) /* * Status register bits available in all MIPS CPUs. */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU1_SHIFT 29 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU1_SHIFT 29 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ /* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) /* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) /* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) /* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) /* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) /* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) /* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) /* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) /* * R10000 performance counter definitions. @@ -604,50 +604,50 @@ /* * Events counted by counter #0 */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 /* * Events counted by counter #1 */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 /* * These flags define in which priviledge mode the counters count events */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ #ifndef __ASSEMBLY__ @@ -685,275 +685,275 @@ * Macros to access the system control coprocessor */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ __read_64bit_c0_register(reg, sel)) -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* * These versions are only needed for systems with more than 38 bits of * physical address space running the 32-bit kernel. That's none atm :-) */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long val; \ - unsigned long flags; \ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ \ - val; \ + val; \ }) -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long flags; \ +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -#define read_c0_info() __read_32bit_c0_register($7, 0) +#define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) -#define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_prid() __read_32bit_c0_register($15, 0) -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) /* * The WatchLo register. There may be upto 8 of them. */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* * The WatchHi register. There may be upto 8 of them. */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) #if 1 /* @@ -962,20 +962,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -993,14 +993,14 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,$"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1018,9 +1018,9 @@ do { \ __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ ".word\t0x40018001\n\t" \ "move\t%0,$1\n\t" \ ".set\tat\n\t" \ @@ -1035,17 +1035,17 @@ do { \ #define read_32bit_cp1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc1\t%0,$"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define write_32bit_cp1_register(register,value) \ __asm__ __volatile__( \ - "ctc1\t%0,$"STR(register)"\n\t" \ - "nop" \ + "ctc1\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); /* TLB operations. */ @@ -1084,62 +1084,62 @@ static inline void tlb_write_random(void) /* * Manipulate bits in a c0 register. */ -#define __BUILD_SET_C0(name,register) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ \ - return res; \ -} \ + return res; \ +} \ \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ \ - return res; \ -} \ + return res; \ +} \ \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ \ - return res; \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) __BUILD_SET_C0(cause,CP0_CAUSE) __BUILD_SET_C0(config,CP0_CONFIG) -#define set_cp0_status(x) set_c0_status(x) -#define set_cp0_cause(x) set_c0_cause(x) -#define set_cp0_config(x) set_c0_config(x) +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) -#define read_c1_status() read_32bit_cp1_register(31) -#define write_c1_status(x) write_32bit_cp1_register(31, x) +#define read_c1_status() read_32bit_cp1_register(31) +#define write_c1_status(x) write_32bit_cp1_register(31, x) -#define readb(reg) (*((volatile unsigned char *) (reg))) -#define readw(reg) (*((volatile unsigned short *) (reg))) -#define readl(reg) (*((volatile unsigned int *) (reg))) +#define readb(reg) (*((volatile unsigned char *) (reg))) +#define readw(reg) (*((volatile unsigned short *) (reg))) +#define readl(reg) (*((volatile unsigned int *) (reg))) -#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) -#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) -#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) +#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) +#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) +#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) #endif /* !__ASSEMBLY__ */ diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h index 00ce58a085..8b82cca5d6 100644 --- a/libcpu/mips/common/ptrace.h +++ b/libcpu/mips/common/ptrace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,9 @@ #include <rtthread.h> struct mips_fpu_struct { - rt_uint64_t fpr[NUM_FPU_REGS]; - rt_uint32_t fcr31; - rt_uint32_t pad; + rt_uint64_t fpr[NUM_FPU_REGS]; + rt_uint32_t fcr31; + rt_uint32_t pad; }; struct pt_regs { @@ -68,53 +68,53 @@ struct pt_regs { /* Note: For call stack o32 ABI has 0x8 shadowsoace Here */ #ifdef ARCH_MIPS64 -#define PT_R0 (0x0 * LONGSIZE) /* 0 */ +#define PT_R0 (0x0 * LONGSIZE) /* 0 */ #else -#define PT_R0 (0x8 * LONGSIZE) /* 0 */ +#define PT_R0 (0x8 * LONGSIZE) /* 0 */ #endif -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ /* * Saved special registers */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ -#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ +#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ -#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ +#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ #ifdef RT_USING_FPU #define PT_FPU_R0 (PT_REG_END) @@ -136,10 +136,10 @@ struct pt_regs { #define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE) #define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4) -#define PT_FPU_END ((PT_FPU_PAD0) + 4) -#define PT_SIZE PT_FPU_END +#define PT_FPU_END ((PT_FPU_PAD0) + 4) +#define PT_SIZE PT_FPU_END #else -#define PT_SIZE PT_REG_END +#define PT_SIZE PT_REG_END #endif -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c index b933b184e7..3f9010837a 100644 --- a/libcpu/mips/common/stack.c +++ b/libcpu/mips/common/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,15 +47,15 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad pt->regs[REG_FP] = (rt_ubase_t)0x0; pt->regs[REG_RA] = (rt_ubase_t)texit; - pt->hi = 0x0; - pt->lo = 0x0; + pt->hi = 0x0; + pt->lo = 0x0; pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM); #ifdef RT_USING_FPU pt->cp0_status |= (ST0_CU1 | ST0_FR); #endif - pt->cp0_cause = read_c0_cause(); - pt->cp0_epc = (rt_ubase_t)tentry; - pt->cp0_badvaddr = 0x0; + pt->cp0_cause = read_c0_cause(); + pt->cp0_epc = (rt_ubase_t)tentry; + pt->cp0_badvaddr = 0x0; return stk; } diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index bb92a18c9c..ba361acd99 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -51,69 +51,69 @@ .set pop .endm - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop .endm - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - sw v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - sw v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + sw v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + sw v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) .endm - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) .endm - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp - move k0, sp + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp + move k0, sp PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - MFC0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - MFC0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + MFC0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + MFC0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop .endm - .macro SAVE_ALL + .macro SAVE_ALL SAVE_SOME SAVE_AT SAVE_TEMP @@ -155,86 +155,86 @@ .set pop .endm - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop .endm - .macro RESTORE_TEMP - lw $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - lw $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) + .macro RESTORE_TEMP + lw $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + lw $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) .endm - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) .endm #define STATMASK 0x1f - .macro RESTORE_SOME - .set push - .set reorder - .set noat - mfc0 a0, CP0_STATUS - ori a0, STATMASK - xori a0, STATMASK - mtc0 a0, CP0_STATUS - li v1, (ST0_CU1 | ST0_FR | ST0_IM) - and a0, v1, a0 - LONG_L v0, PT_STATUS(sp) - li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) - and v0, v1 - or v0, a0 + .macro RESTORE_SOME + .set push + .set reorder + .set noat + mfc0 a0, CP0_STATUS + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS + li v1, (ST0_CU1 | ST0_FR | ST0_IM) + and a0, v1, a0 + LONG_L v0, PT_STATUS(sp) + li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) + and v0, v1 + or v0, a0 li v1, (ST0_KX | ST0_SX | ST0_UX) or v0, v1 - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop .endm - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) eret nop .endm - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) .endm - .macro RESTORE_ALL + .macro RESTORE_ALL RESTORE_TEMP RESTORE_FPU RESTORE_STATIC @@ -243,7 +243,7 @@ RESTORE_SP .endm - .macro RESTORE_ALL_AND_RET + .macro RESTORE_ALL_AND_RET RESTORE_TEMP RESTORE_FPU RESTORE_STATIC diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c index 484d3816f4..bcbf2aba49 100644 --- a/libcpu/mips/gs232/cache.c +++ b/libcpu/mips/gs232/cache.c @@ -1,7 +1,7 @@ /* * Cache Ops For Loongson GS232 * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include <rtthread.h> #include <mips.h> -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1c(unsigned int); @@ -27,10 +27,10 @@ extern void enable_cpu_cache(void); typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; typedef struct cacheop_t @@ -183,12 +183,12 @@ void rt_hw_cache_init(void) end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); /* - * 3. invalidate instruction cache; + * 3. invalidate instruction cache; */ while (start < end) { @@ -197,7 +197,7 @@ void rt_hw_cache_init(void) } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); diff --git a/libcpu/mips/gs232/cache.h b/libcpu/mips/gs232/cache.h index 381298e4df..b47db90814 100644 --- a/libcpu/mips/gs232/cache.h +++ b/libcpu/mips/gs232/cache.h @@ -1,8 +1,8 @@ /* * Cache Ops For Loongson GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,8 +12,8 @@ * 2015-07-08 chinesebear modified for loongson 1c */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations */ @@ -21,31 +21,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c index e3c078241f..e22d9bc14d 100644 --- a/libcpu/mips/gs232/cpuport.c +++ b/libcpu/mips/gs232/cpuport.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2010-07-09 Bernard first version @@ -26,9 +26,9 @@ RT_WEAK void rt_hw_cpu_reset(void) { /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ rt_kprintf("reboot system...\n"); while (1); diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h index 95c81cf93e..cbc660c874 100644 --- a/libcpu/mips/gs232/gs232.h +++ b/libcpu/mips/gs232/gs232.h @@ -1,8 +1,8 @@ /* * Misc define for GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -15,47 +15,47 @@ #include <mips.h> -#define INTC_BASE 0xBFD01040 +#define INTC_BASE 0xBFD01040 #ifdef SOC_LS1B -#define GS232_INTC_CELLS 4 +#define GS232_INTC_CELLS 4 #endif #ifdef SOC_LS1C300 -#define GS232_INTC_CELLS 5 +#define GS232_INTC_CELLS 5 #endif -#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) +#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 #ifndef __ASSEMBLY__ #include <rthw.h> /* Watch Dog registers */ -#define WDT_EN HWREG32(WDT_BASE + 0x00) -#define WDT_SET HWREG32(WDT_BASE + 0x04) -#define WDT_TIMER HWREG32(WDT_BASE + 0x08) +#define WDT_EN HWREG32(WDT_BASE + 0x00) +#define WDT_SET HWREG32(WDT_BASE + 0x04) +#define WDT_TIMER HWREG32(WDT_BASE + 0x08) -#define PLL_FREQ HWREG32(0xbfe78030) -#define PLL_DIV_PARAM HWREG32(0xbfe78034) +#define PLL_FREQ HWREG32(0xbfe78030) +#define PLL_DIV_PARAM HWREG32(0xbfe78034) struct gs232_intc_regs { @@ -65,7 +65,7 @@ struct gs232_intc_regs volatile unsigned int int_clr; /* offset 0x10*/ volatile unsigned int int_pol; volatile unsigned int int_edge; /* offset 0 */ -}; +}; extern void rt_hw_timer_init(void); diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c index 66abea379d..fb80a8c1ec 100644 --- a/libcpu/mips/gs232/interrupt.c +++ b/libcpu/mips/gs232/interrupt.c @@ -1,17 +1,17 @@ /* * Interrupt handle for GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B + * 2010-10-15 lgnq modified for LS1B * 2013-03-29 aozima Modify the interrupt interface implementations. - * 2015-07-06 chinesebear modified for loongson 1c - * 2019-12-04 Jiaxun Yang Generialize + * 2015-07-06 chinesebear modified for loongson 1c + * 2019-12-04 Jiaxun Yang Generialize */ #include <rtthread.h> @@ -52,7 +52,7 @@ void rt_hw_interrupt_init(void) /* Disable */ (gs232_hw0_icregs+i)->int_en = 0x0; /* Trigger active low */ - (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ + (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ /* Make all interrupts level triggered */ (gs232_hw0_icregs+i)->int_edge = 0x00000000; /* Mask all interrupts */ @@ -113,7 +113,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, /** - * ִ Call ISR + * Call ISR * @IRQn ID of IRQ */ void gs232_do_IRQ(int IRQn) diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h index a6f244ef4f..cf32bd5f02 100644 --- a/libcpu/mips/gs232/ls1b.h +++ b/libcpu/mips/gs232/ls1b.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -13,44 +13,44 @@ #include <gs232.h> -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_UART4_IRQ 29 -#define LS1B_UART5_IRQ 30 -#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ -#define LS1B_UART7_IRQ 2 -#define LS1B_UART8_IRQ 2 -#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ -#define LS1B_UART10_IRQ 3 -#define LS1B_UART11_IRQ 3 +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_UART4_IRQ 29 +#define LS1B_UART5_IRQ 30 +#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ +#define LS1B_UART7_IRQ 2 +#define LS1B_UART8_IRQ 2 +#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ +#define LS1B_UART10_IRQ 3 +#define LS1B_UART11_IRQ 3 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 #define LS1B_PCI_INTA_IRQ 38 #define LS1B_PCI_INTB_IRQ 39 #define LS1B_PCI_INTC_IRQ 40 @@ -61,13 +61,13 @@ #define LS1B_GPIO_IRQ_COUNT 64 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) #define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 +#define MIPS_CPU_TIMER_IRQ 167 #define LS1B_INTREG_BASE 0xbfd01040 #define LS1B_DMA_IRQ_BASE 168 diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h index 54c7e36e99..6b8e3fc512 100644 --- a/libcpu/mips/gs232/ls1c.h +++ b/libcpu/mips/gs232/ls1c.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c index 85e0e633ea..6b37abb895 100644 --- a/libcpu/mips/gs232/mipscfg.c +++ b/libcpu/mips/gs232/mipscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,13 +12,13 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c index 8879b82ccf..4df02a1b62 100644 --- a/libcpu/mips/gs232/timer.c +++ b/libcpu/mips/gs232/timer.c @@ -1,7 +1,7 @@ /* * Assembly Macros For MIPS * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ */ void rt_hw_timer_handler(void) { - unsigned int count; + unsigned int count; - count = read_c0_compare(); - write_c0_compare(count); - write_c0_count(0); + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); - /* increase a OS tick */ - rt_tick_increase(); + /* increase a OS tick */ + rt_tick_increase(); } /** @@ -35,7 +35,7 @@ void rt_hw_timer_handler(void) */ void rt_hw_timer_init(void) { - write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); - write_c0_count(0); - mips_unmask_cpu_irq(7); -}
\ No newline at end of file + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); + mips_unmask_cpu_irq(7); +} diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c index 54d38d0d3f..50976f2e4f 100644 --- a/libcpu/mips/gs264/cache.c +++ b/libcpu/mips/gs264/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h index 10a4afd899..1e1bc52737 100644 --- a/libcpu/mips/gs264/cache.h +++ b/libcpu/mips/gs264/cache.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c index 7bed69596a..eae9b007de 100644 --- a/libcpu/mips/gs264/mips_mmu.c +++ b/libcpu/mips/gs264/mips_mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ void mmu_init() uint32_t status = read_c0_status(); status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 write_c0_status(status); - + mmu_clear_tlb(); mmu_clear_itlb(); } @@ -154,7 +154,7 @@ void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t a uint64_t even_vpn = vpn & (~lb); uint32_t index; tlb_item_t tlb_item,tlb2_item; - + mmu_tlb_item_init(&tlb_item); mmu_tlb_item_init(&tlb2_item); tlb_item.page_mask.mask = page_mask; diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h index fcbcef3621..4c7af117d9 100644 --- a/libcpu/mips/gs264/mips_mmu.h +++ b/libcpu/mips/gs264/mips_mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -96,4 +96,4 @@ uint64_t mmu_tlb_get_bad_vaddr(); void tlb_dump(); -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c index b2aed120ae..0ce7000581 100644 --- a/libcpu/mips/gs264/mipscfg.c +++ b/libcpu/mips/gs264/mipscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index b5bedace50..cab73f37bd 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -387,7 +387,7 @@ static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages return; } - if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) { *(mmu_l2 + l2_off) = 0; /* cache maintain */ @@ -691,7 +691,7 @@ void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) //pa --> va void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) -{ +{ void *v_addr = 0; #ifdef RT_USING_USERSPACE diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index 2472bf975f..22a749af64 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 3f08d57167..089f652bce 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -45,51 +45,51 @@ rt_uint32_t __attribute__((nomips16)) _get_gp(void) */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ - *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) 0; /* lo */ - *(--stk) = (rt_uint32_t) 0; /* hi */ - *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ - *(--stk) = (rt_uint32_t) texit; /* 31 ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ - *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ - *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/mips/pic32/exceptions.c b/libcpu/mips/pic32/exceptions.c index de5f70b7e1..d9f457a707 100644 --- a/libcpu/mips/pic32/exceptions.c +++ b/libcpu/mips/pic32/exceptions.c @@ -11,13 +11,13 @@ * Complier: MPLAB C32 * MPLAB IDE * Company: Microchip Technology, Inc. - * Author: Darren Wenn + * Author: Darren Wenn * * Software License Agreement * * The software supplied herewith by Microchip Technology Incorporated - * (the �Company�) for its PIC32/PIC24 Microcontroller is intended - * and supplied to you, the Company�s customer, for use solely and + * (the “Company”) for its PIC32/PIC24 Microcontroller is intended + * and supplied to you, the Company’s customer, for use solely and * exclusively on Microchip PIC32/PIC24 Microcontroller products. * The software is owned by the Company and/or its supplier, and is * protected under applicable copyright laws. All rights are reserved. @@ -26,7 +26,7 @@ * civil liability for the breach of the terms and conditions of this * license. * - * THIS SOFTWARE IS PROVIDED IN AN �AS IS� CONDITION. NO WARRANTIES, + * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, @@ -42,20 +42,20 @@ // declared static in case exception condition would prevent // auto variable being created static enum { - EXCEP_IRQ = 0, // interrupt - EXCEP_AdEL = 4, // address error exception (load or ifetch) - EXCEP_AdES, // address error exception (store) - EXCEP_IBE, // bus error (ifetch) - EXCEP_DBE, // bus error (load/store) - EXCEP_Sys, // syscall - EXCEP_Bp, // breakpoint - EXCEP_RI, // reserved instruction - EXCEP_CpU, // coprocessor unusable - EXCEP_Overflow, // arithmetic overflow - EXCEP_Trap, // trap (possible divide by zero) - EXCEP_IS1 = 16, // implementation specfic 1 - EXCEP_CEU, // CorExtend Unuseable - EXCEP_C2E // coprocessor 2 + EXCEP_IRQ = 0, // interrupt + EXCEP_AdEL = 4, // address error exception (load or ifetch) + EXCEP_AdES, // address error exception (store) + EXCEP_IBE, // bus error (ifetch) + EXCEP_DBE, // bus error (load/store) + EXCEP_Sys, // syscall + EXCEP_Bp, // breakpoint + EXCEP_RI, // reserved instruction + EXCEP_CpU, // coprocessor unusable + EXCEP_Overflow, // arithmetic overflow + EXCEP_Trap, // trap (possible divide by zero) + EXCEP_IS1 = 16, // implementation specfic 1 + EXCEP_CEU, // CorExtend Unuseable + EXCEP_C2E // coprocessor 2 } _excep_code; static unsigned int _epc_code; @@ -65,34 +65,34 @@ static unsigned int _excep_addr; // this function overrides the normal _weak_ generic handler void _general_exception_handler(void) { - asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); - asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); + asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); + asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); - _excep_code = (_excep_code & 0x0000007C) >> 2; + _excep_code = (_excep_code & 0x0000007C) >> 2; - rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); - rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); - switch(_excep_code) - { - case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; - case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; - case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; - case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; - case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; - case EXCEP_Sys:rt_kprintf("syscall\r\n");break; - case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; - case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; - case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; - case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; - case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; - case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; - case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; - case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; - default : rt_kprintf("unkown exception\r\n");break; - } + rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); + rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); + switch(_excep_code) + { + case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; + case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; + case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; + case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; + case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; + case EXCEP_Sys:rt_kprintf("syscall\r\n");break; + case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; + case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; + case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; + case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; + case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; + case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; + case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; + case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; + default : rt_kprintf("unkown exception\r\n");break; + } - while (1) { - // Examine _excep_code to identify the type of exception - // Examine _excep_addr to find the address that caused the exception - } + while (1) { + // Examine _excep_code to identify the type of exception + // Examine _excep_addr to find the address that caused the exception + } } diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c index 125bf2c578..463ba0df96 100644 --- a/libcpu/nios/nios_ii/stack.c +++ b/libcpu/nios/nios_ii/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -30,43 +30,43 @@ * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0x01; /* status */ - *(--stk) = (unsigned long)texit; /* ra */ - *(--stk) = 0xdeadbeef; /* fp */ - *(--stk) = 0xdeadbeef; /* r23 */ - *(--stk) = 0xdeadbeef; /* r22 */ - *(--stk) = 0xdeadbeef; /* r21 */ - *(--stk) = 0xdeadbeef; /* r20 */ - *(--stk) = 0xdeadbeef; /* r19 */ - *(--stk) = 0xdeadbeef; /* r18 */ - *(--stk) = 0xdeadbeef; /* r17 */ - *(--stk) = 0xdeadbeef; /* r16 */ -// *(--stk) = 0xdeadbeef; /* r15 */ -// *(--stk) = 0xdeadbeef; /* r14 */ -// *(--stk) = 0xdeadbeef; /* r13 */ -// *(--stk) = 0xdeadbeef; /* r12 */ -// *(--stk) = 0xdeadbeef; /* r11 */ -// *(--stk) = 0xdeadbeef; /* r10 */ -// *(--stk) = 0xdeadbeef; /* r9 */ -// *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = (unsigned long)parameter; /* r4 argument */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = (unsigned long)tentry; /* pc */ + stk = (unsigned long *)stack_addr; + *(stk) = 0x01; /* status */ + *(--stk) = (unsigned long)texit; /* ra */ + *(--stk) = 0xdeadbeef; /* fp */ + *(--stk) = 0xdeadbeef; /* r23 */ + *(--stk) = 0xdeadbeef; /* r22 */ + *(--stk) = 0xdeadbeef; /* r21 */ + *(--stk) = 0xdeadbeef; /* r20 */ + *(--stk) = 0xdeadbeef; /* r19 */ + *(--stk) = 0xdeadbeef; /* r18 */ + *(--stk) = 0xdeadbeef; /* r17 */ + *(--stk) = 0xdeadbeef; /* r16 */ +// *(--stk) = 0xdeadbeef; /* r15 */ +// *(--stk) = 0xdeadbeef; /* r14 */ +// *(--stk) = 0xdeadbeef; /* r13 */ +// *(--stk) = 0xdeadbeef; /* r12 */ +// *(--stk) = 0xdeadbeef; /* r11 */ +// *(--stk) = 0xdeadbeef; /* r10 */ +// *(--stk) = 0xdeadbeef; /* r9 */ +// *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = (unsigned long)parameter; /* r4 argument */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = (unsigned long)tentry; /* pc */ -// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ -// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ +// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ +// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index 72ef31bfbc..8d06ed00ca 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -24,24 +24,24 @@ struct pt_regs { PPC_REG gpr[32]; PPC_REG nip; PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG orig_gpr3; /* Used for restarting system calls */ PPC_REG ctr; PPC_REG link; PPC_REG xer; PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ + PPC_REG mq; /* 601 only (not used at present) */ /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG result; /* Result of a system call */ }__attribute__((packed)) CELL_STACK_FRAME_t; #endif -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ /* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 +#define __SIGNAL_FRAMESIZE 64 #define instruction_pointer(regs) ((regs)->nip) #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) @@ -51,49 +51,49 @@ struct pt_regs { * These can't be changed without breaking binary compatibility * with MkLinux, etc. */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 -#define PT_NIP 32 -#define PT_MSR 33 +#define PT_NIP 32 +#define PT_MSR 33 #define PT_ORIG_R3 34 -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ #define PT_FPR31 (PT_FPR0 + 2*31) #define PT_FPSCR (PT_FPR0 + 2*32 + 1) diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 570e9ba046..de9d7d2016 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2011-02-14 Fred first implementation for + * 2011-02-14 Fred first implementation for */ #include <rtthread.h> diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h index 8b4d55d698..cb12df845c 100644 --- a/libcpu/ppc/ppc405/context.h +++ b/libcpu/ppc/ppc405/context.h @@ -1,9 +1,9 @@ #ifndef __CONTEXT_H__ #define __CONTEXT_H__ -#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ #define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ #define GPR0 0 #define GPR2 4 diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h index c2562047cb..5e96fa782a 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc405.h +++ b/libcpu/ppc/ppc405/include/asm/ppc405.h @@ -1,30 +1,30 @@ /*----------------------------------------------------------------------------+ | -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. | -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. | -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. | -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ -#ifndef __PPC405_H__ +#ifndef __PPC405_H__ #define __PPC405_H__ /* Define bits and masks for real-mode storage attribute control registers */ -#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) -#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) /****************************************************************************** * Special for PPC405GP @@ -34,29 +34,29 @@ * DMA ******************************************************************************/ #define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ #ifndef CONFIG_405EP /****************************************************************************** @@ -66,22 +66,22 @@ #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ #define kaddr0 0x04 /* address decode definition regsiter 0 */ #define kaddr1 0x05 /* address decode definition regsiter 1 */ #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ #endif /****************************************************************************** @@ -92,23 +92,23 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ #endif #define pb0ap 0x10 /* periph bank 0 access parameters */ #define pb1ap 0x11 /* periph bank 1 access parameters */ @@ -120,221 +120,221 @@ #define pb6ap 0x16 /* periph bank 6 access parameters */ #define pb7ap 0x17 /* periph bank 7 access parameters */ #endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP /****************************************************************************** * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ /* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 /* Defines for CPC0_PCI Register */ -#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ -#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ -#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ /* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ /* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ /* Defines for CPC0_PLLMR0 Register fields */ /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 /* *------------------------------------------------------------------------------- @@ -343,48 +343,48 @@ *------------------------------------------------------------------------------- */ #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -393,57 +393,57 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 -#define SDR_NAND0_NDEN 0x80000000 -#define SDR_NAND0_NDBTEN 0x40000000 -#define SDR_NAND0_NDBADR_MASK 0x30000000 -#define SDR_NAND0_NDBPG_MASK 0x0f000000 -#define SDR_NAND0_NDAREN 0x00800000 -#define SDR_NAND0_NDRBEN 0x00400000 +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 -#define SDR_ULTRA0_NDGPIOBP 0x80000000 -#define SDR_ULTRA0_CSN_MASK 0x78000000 -#define SDR_ULTRA0_CSNSEL0 0x40000000 -#define SDR_ULTRA0_CSNSEL1 0x20000000 -#define SDR_ULTRA0_CSNSEL2 0x10000000 -#define SDR_ULTRA0_CSNSEL3 0x08000000 -#define SDR_ULTRA0_EBCRDYEN 0x04000000 -#define SDR_ULTRA0_SPISSINEN 0x02000000 -#define SDR_ULTRA0_NFSRSTEN 0x01000000 +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 -#define SDR_ULTRA1_LEDNENABLE 0x40000000 +#define SDR_ULTRA1_LEDNENABLE 0x40000000 -#define SDR_ICRX_STAT 0x80000000 -#define SDR_ICTX0_STAT 0x40000000 -#define SDR_ICTX1_STAT 0x20000000 +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 -#define SDR_PINSTP 0x40 +#define SDR_PINSTP 0x40 /****************************************************************************** * Control ******************************************************************************/ /* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ -#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ @@ -462,77 +462,77 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ -#define ecr (0xaa) /* edge conditioner register (405gpr) */ +#define ecr (0xaa) /* edge conditioner register (405gpr) */ /* Bit definitions */ -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ -#define PLLMR_FWD_DIV_BYPASS 0xE0000000 -#define PLLMR_FWD_DIV_3 0xA0000000 -#define PLLMR_FWD_DIV_4 0x80000000 -#define PLLMR_FWD_DIV_6 0x40000000 +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ -#define PLLMR_FB_DIV_1 0x02000000 -#define PLLMR_FB_DIV_2 0x04000000 -#define PLLMR_FB_DIV_3 0x06000000 -#define PLLMR_FB_DIV_4 0x08000000 +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 -#define PLLMR_TUNING_MASK 0x01F80000 +#define PLLMR_TUNING_MASK 0x01F80000 -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ -#define PLLMR_CPU_PLB_DIV_1 0x00000000 -#define PLLMR_CPU_PLB_DIV_2 0x00020000 -#define PLLMR_CPU_PLB_DIV_3 0x00040000 -#define PLLMR_CPU_PLB_DIV_4 0x00060000 +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ -#define PLLMR_OPB_PLB_DIV_1 0x00000000 -#define PLLMR_OPB_PLB_DIV_2 0x00008000 -#define PLLMR_OPB_PLB_DIV_3 0x00010000 -#define PLLMR_OPB_PLB_DIV_4 0x00018000 +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ -#define PLLMR_PCI_PLB_DIV_1 0x00000000 -#define PLLMR_PCI_PLB_DIV_2 0x00002000 -#define PLLMR_PCI_PLB_DIV_3 0x00004000 -#define PLLMR_PCI_PLB_DIV_4 0x00006000 +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ -#define PLLMR_EXB_PLB_DIV_2 0x00000000 -#define PLLMR_EXB_PLB_DIV_3 0x00000800 -#define PLLMR_EXB_PLB_DIV_4 0x00001000 -#define PLLMR_EXB_PLB_DIV_5 0x00001800 +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 /* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ -#define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ #ifndef CONFIG_IOP480 /* @@ -548,201 +548,201 @@ * Memory Access Layer ******************************************************************************/ #if defined(CONFIG_405EZ) -#define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ #else /* !defined(CONFIG_405EZ) */ #define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ #endif /* defined(CONFIG_405EZ) */ /*----------------------------------------------------------------------------- | IIC Register Offsets '----------------------------------------------------------------------------*/ -#define IICMDBUF 0x00 -#define IICSDBUF 0x02 -#define IICLMADR 0x04 -#define IICHMADR 0x05 -#define IICCNTL 0x06 -#define IICMDCNTL 0x07 -#define IICSTS 0x08 -#define IICEXTSTS 0x09 -#define IICLSADR 0x0A -#define IICHSADR 0x0B -#define IICCLKDIV 0x0C -#define IICINTRMSK 0x0D -#define IICXFRCNT 0x0E -#define IICXTCNTLSS 0x0F +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F #define IICDIRECTCNTL 0x10 /*----------------------------------------------------------------------------- | UART Register Offsets '----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 /****************************************************************************** * On Chip Memory ******************************************************************************/ #if defined(CONFIG_405EZ) #define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ #else #define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ #endif /* CONFIG_405EZ */ /****************************************************************************** @@ -751,154 +751,154 @@ #if defined(CONFIG_405EZ) /* Only the 405EZ has 2 GPIOs */ #define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_RR3 (GPIO_BASE+0x28) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) #define GPIO1_BASE 0xEF600800 -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) #elif defined(CONFIG_405EX) #define GPIO_BASE 0xEF600800 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) -#else /* !405EZ */ +#else /* !405EZ */ #define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRH (GPIO_BASE+0x8) -#define GPIO0_OSRL (GPIO_BASE+0xC) -#define GPIO0_TSRH (GPIO_BASE+0x10) -#define GPIO0_TSRL (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1H (GPIO_BASE+0x30) -#define GPIO0_ISR1L (GPIO_BASE+0x34) -#define GPIO0_ISR2H (GPIO_BASE+0x38) -#define GPIO0_ISR2L (GPIO_BASE+0x3C) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) #endif /* CONFIG_405EZ */ -#define GPIO0_BASE GPIO_BASE +#define GPIO0_BASE GPIO_BASE #if defined(CONFIG_405EX) -#define SDR0_SRST 0x0200 +#define SDR0_SRST 0x0200 /* * Software Reset Register */ -#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) -#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) -#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) -#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) -#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) -#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) -#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) -#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) -#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) -#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) -#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) -#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) -#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) -#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) -#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) -#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) -#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) -#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) -#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) -#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) -#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) -#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) -#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) -#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) -#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) -#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) -#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) -#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) -#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) -#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) -#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) -#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 -#define SDR0_SDCS_SDD (0x80000000 >> 31) +#define SDR0_SDCS_SDD (0x80000000 >> 31) /* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 +#define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ @@ -924,9 +924,9 @@ #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) @@ -940,41 +940,41 @@ #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ -#define SDR0_PFC0 0x4100 -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME 0x02000000 -#define SDR0_PFC1_U0ME 0x00080000 -#define SDR0_PFC1_U0IM 0x00040000 -#define SDR0_PFC1_SIS 0x00020000 -#define SDR0_PFC1_DMAAEN 0x00010000 -#define SDR0_PFC1_DMADEN 0x00008000 -#define SDR0_PFC1_USBEN 0x00004000 -#define SDR0_PFC1_AHBSWAP 0x00000020 -#define SDR0_PFC1_USBBIGEN 0x00000010 -#define SDR0_PFC1_GPT_FREQ 0x0000000f +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f #endif /* General Purpose Timer (GPT) Register Offsets */ -#define GPT0_TBC 0x00000000 -#define GPT0_IM 0x00000018 -#define GPT0_ISS 0x0000001C -#define GPT0_ISC 0x00000020 -#define GPT0_IE 0x00000024 -#define GPT0_COMP0 0x00000080 -#define GPT0_COMP1 0x00000084 -#define GPT0_COMP2 0x00000088 -#define GPT0_COMP3 0x0000008C -#define GPT0_COMP4 0x00000090 -#define GPT0_COMP5 0x00000094 -#define GPT0_COMP6 0x00000098 -#define GPT0_MASK0 0x000000C0 -#define GPT0_MASK1 0x000000C4 -#define GPT0_MASK2 0x000000C8 -#define GPT0_MASK3 0x000000CC -#define GPT0_MASK4 0x000000D0 -#define GPT0_MASK5 0x000000D4 -#define GPT0_MASK6 0x000000D8 -#define GPT0_DCT0 0x00000110 -#define GPT0_DCIS 0x0000011C +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C -#endif /* __PPC405_H__ */ +#endif /* __PPC405_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h index cdb542c2da..83b55e5e64 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h @@ -4,8 +4,8 @@ /* * Define the number of UIC's */ -#define UIC_MAX 1 -#define IRQ_MAX UIC_MAX * 32 +#define UIC_MAX 1 +#define IRQ_MAX UIC_MAX * 32 /* UIC0 dcr base address */ #define UIC0_DCR_BASE 0xc0 @@ -13,49 +13,49 @@ /* * UIC register */ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ /* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr /* the interrupt vector definitions */ -#define VECNUM_MAL_SERR 10 -#define VECNUM_MAL_TXEOB 11 -#define VECNUM_MAL_RXEOB 12 -#define VECNUM_MAL_TXDE 13 -#define VECNUM_MAL_RXDE 14 -#define VECNUM_ETH0 15 -#define VECNUM_ETH1_OFFS 2 -#define VECNUM_EIRQ6 29 +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 /* * Mask definitions (used for example in 4xx_enet.c) */ -#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ -#define UIC_NR(vec) ((vec) >> 5) +#define UIC_NR(vec) ((vec) >> 5) #endif /* _PPC4xx_UIC_H_ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h index 57fe7ab221..2bfef123d6 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h @@ -19,13 +19,13 @@ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ -#ifndef __PPC4XX_H__ +#ifndef __PPC4XX_H__ #define __PPC4XX_H__ /* * Configure which SDRAM/DDR/DDR2 controller is equipped */ -#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ #include <asm/ppc405.h> #include <asm/ppc4xx-uic.h> @@ -33,102 +33,102 @@ /* * Macro for generating register field mnemonics */ -#define PPC_REG_BITS 32 -#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) /* * Elide casts when assembling register mnemonics */ #ifndef __ASSEMBLY__ -#define static_cast(type, val) (type)(val) +#define static_cast(type, val) (type)(val) #else -#define static_cast(type, val) (val) +#define static_cast(type, val) (val) #endif /* * Common stuff for 4xx (405 and 440) */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) #ifndef __ASSEMBLY__ typedef struct { - unsigned long freqDDR; - unsigned long freqEBC; - unsigned long freqOPB; - unsigned long freqPCI; - unsigned long freqPLB; - unsigned long freqTmrClk; - unsigned long freqUART; - unsigned long freqProcessor; - unsigned long freqVCOHz; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pllExtBusDiv; - unsigned long pllFbkDiv; - unsigned long pllFwdDiv; - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllPlbDiv; + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; } PPC4xx_SYS_INFO; static inline rt_uint32_t get_mcsr(void) { - rt_uint32_t val; + rt_uint32_t val; - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; } static inline void set_mcsr(rt_uint32_t val) { - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ /* for multi-cpu support */ -#define NA_OR_UNKNOWN_CPU -1 +#define NA_OR_UNKNOWN_CPU -1 -#endif /* __PPC4XX_H__ */ +#endif /* __PPC4XX_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h index 88aed26009..0b6d06deae 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h +++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h @@ -24,50 +24,50 @@ /* * WARNING! This file is automatically generated - DO NOT EDIT! */ -#define STACK_FRAME_OVERHEAD 16 -#define INT_FRAME_SIZE 192 -#define GPR0 16 -#define GPR1 20 -#define GPR2 24 -#define GPR3 28 -#define GPR4 32 -#define GPR5 36 -#define GPR6 40 -#define GPR7 44 -#define GPR8 48 -#define GPR9 52 -#define GPR10 56 -#define GPR11 60 -#define GPR12 64 -#define GPR13 68 -#define GPR14 72 -#define GPR15 76 -#define GPR16 80 -#define GPR17 84 -#define GPR18 88 -#define GPR19 92 -#define GPR20 96 -#define GPR21 100 -#define GPR22 104 -#define GPR23 108 -#define GPR24 112 -#define GPR25 116 -#define GPR26 120 -#define GPR27 124 -#define GPR28 128 -#define GPR29 132 -#define GPR30 136 -#define GPR31 140 -#define _NIP 144 -#define _MSR 148 -#define ORIG_GPR3 152 -#define _CTR 156 -#define _LINK 160 -#define _XER 164 -#define _CCR 168 -#define _MQ 172 -#define TRAP 176 -#define _DAR 180 -#define _DSISR 184 -#define RESULT 188 +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define ORIG_GPR3 152 +#define _CTR 156 +#define _LINK 160 +#define _XER 164 +#define _CCR 168 +#define _MQ 172 +#define TRAP 176 +#define _DAR 180 +#define _DSISR 184 +#define RESULT 188 diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h index 7aeeb01dc5..827de2186b 100644 --- a/libcpu/ppc/ppc405/include/asm/processor.h +++ b/libcpu/ppc/ppc405/include/asm/processor.h @@ -15,80 +15,80 @@ /* Machine State Register (MSR) Fields */ #ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) #endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI +#define MSR_ MSR_ME|MSR_IP|MSR_RI #else -#define MSR_ MSR_ME|MSR_RI +#define MSR_ MSR_ME|MSR_RI #endif #ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else -#define MSR_KERNEL MSR_ME +#define MSR_KERNEL MSR_ME #endif /* Floating Point Status and Control Register (FPSCR) Fields */ -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ /* Special Purpose Registers (SPRNs)*/ @@ -97,618 +97,618 @@ #define CONFIG_BOOKE #endif -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ #ifdef CONFIG_BOOKE -#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ #endif -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ #endif /* CONFIG_BOOKE */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ #ifdef CONFIG_BOOKE -#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ #endif -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ #endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ #ifndef CONFIG_BOOKE -#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ -#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ #endif -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ #ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ #ifdef CONFIG_BOOKE -#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ -#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ -#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ -#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ #endif -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ #ifdef CONFIG_BOOKE -#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ -#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ -#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ -#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ -#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ #endif -#define SPRN_EAR 0x11A /* External Address Register */ +#define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ #endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ -#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ -#define HID0_TBEN (1<<14) /* Time Base Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ -#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ -#define HID0_DCI HID0_DCFI -#define HID0_SPD (1<<9) /* Speculative disable */ -#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ -#define HID0_SGE (1<<7) /* Store Gathering Enable */ -#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ -#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ -#define HID0_ABE (1<<3) /* Address Broadcast Enable */ -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ -#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ -#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ -#define HID1_ASTME (1<<13) /* Address bus streaming mode */ -#define HID1_ABE (1<<12) /* Address broadcast enable */ -#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ +#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI +#define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ +#define HID0_SGE (1<<7) /* Store Gathering Enable */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ #else -#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ -#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ +#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ #endif /* CONFIG_BOOKE */ -#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ -#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ -#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ -#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ -#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ -#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ -#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ -#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ -#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ -#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ -#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ -#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ -#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ -#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ -#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ -#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ #ifdef CONFIG_BOOKE -#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ -#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ #endif -#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ -#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ -#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #ifdef CONFIG_BOOKE -#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ -#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ -#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ -#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ -#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ -#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ -#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ -#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ -#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ #endif -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ -#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ -#define SPRN_LR 0x008 /* Link Register */ -#define SPRN_MBAR 0x137 /* System memory base address */ -#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ -#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ #ifdef CONFIG_BOOKE -#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ #endif -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ #ifndef CONFIG_BOOKE -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_PIR 0x3FF /* Processor Identification Register */ #else -#define SPRN_PID 0x030 /* Book E Process ID */ -#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ +#define SPRN_PID 0x030 /* Book E Process ID */ +#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ -#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ -#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ -#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ -#define SPRN_PVR 0x11F /* Processor Version Register */ -#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #ifdef CONFIG_BOOKE -#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ #endif -#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ -#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SGR_NORMAL 0 -#define SGR_GUARDED 1 -#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ -#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ -#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ -#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ -#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ -#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ -#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ -#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ -#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ -#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ -#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SGR_NORMAL 0 +#define SGR_GUARDED 1 +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ #ifdef CONFIG_BOOKE -#define SPRN_SVR 0x3FF /* System Version Register */ +#define SPRN_SVR 0x3FF /* System Version Register */ #else -#define SPRN_SVR 0x11E /* System Version Register */ +#define SPRN_SVR 0x11E /* System Version Register */ #endif -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ -#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ -#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ -#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ +#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ +#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ +#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ #ifndef CONFIG_BOOKE -#define SPRN_TCR 0x3DA /* Timer Control Register */ +#define SPRN_TCR 0x3DA /* Timer Control Register */ #else -#define SPRN_TCR 0x154 /* Book E Timer Control Register */ +#define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ -#define THRM1_TIN (1<<0) -#define THRM1_TIV (1<<1) -#define THRM1_THRES (0x7f<<2) -#define THRM1_TID (1<<29) -#define THRM1_TIE (1<<30) -#define THRM1_V (1<<31) -#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ -#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ -#define THRM3_E (1<<31) -#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define THRM1_TIN (1<<0) +#define THRM1_TIV (1<<1) +#define THRM1_THRES (0x7f<<2) +#define THRM1_TID (1<<29) +#define THRM1_TIE (1<<30) +#define THRM1_V (1<<31) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<31) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ #ifndef CONFIG_BOOKE -#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#define SPRN_TSR 0x3D8 /* Timer Status Register */ #else -#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ #endif /* CONFIG_BOOKE */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ -#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ -#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ -#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ -#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ -#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ -#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ -#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ -#define SPRN_XER 0x001 /* Fixed Point Exception Register */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ /* Book E definitions */ -#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ -#define SPRN_CSRR0 0x03A /* Critical SRR0 */ -#define SPRN_CSRR1 0x03B /* Critical SRR0 */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ -#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ -#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ -#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ -#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ -#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ -#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ -#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ -#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ -#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ -#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ -#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ -#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ -#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ -#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ -#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ -#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ -#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ -#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ -#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ -#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_CSRR0 0x03A /* Critical SRR0 */ +#define SPRN_CSRR1 0x03B /* Critical SRR0 */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ +#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ -#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ -#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ -#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ -#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ -#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ -#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ -#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ -#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ -#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ -#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ -#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ -#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ -#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ -#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ -#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ -#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ -#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ -#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ -#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ -#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ -#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ -#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ -#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ +#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ +#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ -#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ -#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ -#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ -#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ -#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ -#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ -#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ -#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ +#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ +#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ +#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ +#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ +#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ -#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ -#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ -#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ -#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ -#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ +#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ +#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ +#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ +#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ -#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ -#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ -#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ -#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ -#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ -#define SPRN_PID1 0x279 /* Process ID Register 1 */ -#define SPRN_PID2 0x27a /* Process ID Register 2 */ -#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ -#define SPRN_MCAR 0x23d /* Machine Check Address register */ -#define MCSR_MCS 0x80000000 /* Machine Check Summary */ -#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ +#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ +#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_PID1 0x279 /* Process ID Register 1 */ +#define SPRN_PID2 0x27a /* Process ID Register 2 */ +#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ #if defined(CONFIG_440) -#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ -#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ #else -#define MCSR_DB 0x20000000 /* Data PLB Error */ +#define MCSR_DB 0x20000000 /* Data PLB Error */ #endif /* defined(CONFIG_440) */ -#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ -#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ -#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ -#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ -#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#define ESR_ST 0x00800000 /* Store Operation */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCR0 0x3f6 -#define SPRN_MSSSR0 0x3f7 +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 #endif /* Short-hand versions for a number of the above SPRNs */ -#define CTR SPRN_CTR /* Counter Register */ -#define DAR SPRN_DAR /* Data Address Register */ -#define DABR SPRN_DABR /* Data Address Breakpoint Register */ -#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ -#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ -#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ -#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ -#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ -#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ -#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ -#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ -#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ -#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ -#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ -#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ -#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ -#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ -#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ -#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ -#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ -#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ -#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ -#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ -#define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ -#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ -#define ESR SPRN_ESR /* Exception Syndrome Register */ -#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ -#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ -#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ -#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ -#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ -#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ -#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ -#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ -#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ -#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ -#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ -#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ -#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ -#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ -#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ -#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ -#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ -#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ -#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ -#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ -#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ -#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ -#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ -#define LR SPRN_LR -#define MBAR SPRN_MBAR /* System memory base address */ +#define CTR SPRN_CTR /* Counter Register */ +#define DAR SPRN_DAR /* Data Address Register */ +#define DABR SPRN_DABR /* Data Address Breakpoint Register */ +#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ +#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ +#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ +#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ +#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ +#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ +#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ +#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ +#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ +#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ +#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ +#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ +#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ +#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ +#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ +#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ +#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ +#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ +#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ +#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ +#define DBSR SPRN_DBSR /* Debug Status Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ +#define EAR SPRN_EAR /* External Address Register */ +#define ESR SPRN_ESR /* Exception Syndrome Register */ +#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ +#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ +#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ +#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ +#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ +#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ +#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ +#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ +#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ +#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ +#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ +#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ +#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ +#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ +#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ +#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ +#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ +#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ +#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ +#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ +#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCR0 +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define PIR SPRN_PIR +#define PIR SPRN_PIR #endif -#define SVR SPRN_SVR /* System-On-Chip Version Register */ -#define PVR SPRN_PVR /* Processor Version */ -#define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ -#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ -#define SPR1 SPRN_SPRG1 -#define SPR2 SPRN_SPRG2 -#define SPR3 SPRN_SPRG3 -#define SPRG0 SPRN_SPRG0 -#define SPRG1 SPRN_SPRG1 -#define SPRG2 SPRN_SPRG2 -#define SPRG3 SPRN_SPRG3 -#define SPRG4 SPRN_SPRG4 -#define SPRG5 SPRN_SPRG5 -#define SPRG6 SPRN_SPRG6 -#define SPRG7 SPRN_SPRG7 -#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ -#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ -#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ -#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ -#define SVR SPRN_SVR /* System Version Register */ -#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ -#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ -#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ -#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ -#define TCR SPRN_TCR /* Timer Control Register */ -#define TSR SPRN_TSR /* Timer Status Register */ -#define ICTC 1019 -#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ -#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ -#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ -#define XER SPRN_XER +#define SVR SPRN_SVR /* System-On-Chip Version Register */ +#define PVR SPRN_PVR /* Processor Version */ +#define RPA SPRN_RPA /* Required Physical Address Register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ +#define SPR1 SPRN_SPRG1 +#define SPR2 SPRN_SPRG2 +#define SPR3 SPRN_SPRG3 +#define SPRG0 SPRN_SPRG0 +#define SPRG1 SPRN_SPRG1 +#define SPRG2 SPRN_SPRG2 +#define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 +#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ +#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ +#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ +#define SVR SPRN_SVR /* System Version Register */ +#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ +#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ +#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ +#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ +#define TCR SPRN_TCR /* Timer Control Register */ +#define TSR SPRN_TSR /* Timer Status Register */ +#define ICTC 1019 +#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ +#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ +#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ +#define XER SPRN_XER -#define DECAR SPRN_DECAR -#define CSRR0 SPRN_CSRR0 -#define CSRR1 SPRN_CSRR1 -#define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG -#define SPRG4R SPRN_SPRG4R -#define SPRG5R SPRN_SPRG5R -#define SPRG6R SPRN_SPRG6R -#define SPRG7R SPRN_SPRG7R -#define SPRG4W SPRN_SPRG4W -#define SPRG5W SPRN_SPRG5W -#define SPRG6W SPRN_SPRG6W -#define SPRG7W SPRN_SPRG7W -#define DEAR SPRN_DEAR -#define DBCR2 SPRN_DBCR2 -#define IAC3 SPRN_IAC3 -#define IAC4 SPRN_IAC4 -#define DVC1 SPRN_DVC1 -#define DVC2 SPRN_DVC2 -#define IVOR0 SPRN_IVOR0 -#define IVOR1 SPRN_IVOR1 -#define IVOR2 SPRN_IVOR2 -#define IVOR3 SPRN_IVOR3 -#define IVOR4 SPRN_IVOR4 -#define IVOR5 SPRN_IVOR5 -#define IVOR6 SPRN_IVOR6 -#define IVOR7 SPRN_IVOR7 -#define IVOR8 SPRN_IVOR8 -#define IVOR9 SPRN_IVOR9 -#define IVOR10 SPRN_IVOR10 -#define IVOR11 SPRN_IVOR11 -#define IVOR12 SPRN_IVOR12 -#define IVOR13 SPRN_IVOR13 -#define IVOR14 SPRN_IVOR14 -#define IVOR15 SPRN_IVOR15 -#define IVOR32 SPRN_IVOR32 -#define IVOR33 SPRN_IVOR33 -#define IVOR34 SPRN_IVOR34 -#define IVOR35 SPRN_IVOR35 -#define MCSRR0 SPRN_MCSRR0 -#define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 -#define L1CSR1 SPRN_L1CSR1 -#define L1CSR2 SPRN_L1CSR2 -#define L1CFG0 SPRN_L1CFG0 -#define L1CFG1 SPRN_L1CFG1 -#define L2CFG0 SPRN_L2CFG0 -#define L2CSR0 SPRN_L2CSR0 -#define L2CSR1 SPRN_L2CSR1 -#define MCSR SPRN_MCSR -#define MMUCSR0 SPRN_MMUCSR0 -#define BUCSR SPRN_BUCSR -#define PID0 SPRN_PID -#define PID1 SPRN_PID1 -#define PID2 SPRN_PID2 -#define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 -#define MAS2 SPRN_MAS2 -#define MAS3 SPRN_MAS3 -#define MAS4 SPRN_MAS4 -#define MAS5 SPRN_MAS5 -#define MAS6 SPRN_MAS6 -#define MAS7 SPRN_MAS7 +#define DECAR SPRN_DECAR +#define CSRR0 SPRN_CSRR0 +#define CSRR1 SPRN_CSRR1 +#define IVPR SPRN_IVPR +#define USPRG0 SPRN_USPRG +#define SPRG4R SPRN_SPRG4R +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W +#define DEAR SPRN_DEAR +#define DBCR2 SPRN_DBCR2 +#define IAC3 SPRN_IAC3 +#define IAC4 SPRN_IAC4 +#define DVC1 SPRN_DVC1 +#define DVC2 SPRN_DVC2 +#define IVOR0 SPRN_IVOR0 +#define IVOR1 SPRN_IVOR1 +#define IVOR2 SPRN_IVOR2 +#define IVOR3 SPRN_IVOR3 +#define IVOR4 SPRN_IVOR4 +#define IVOR5 SPRN_IVOR5 +#define IVOR6 SPRN_IVOR6 +#define IVOR7 SPRN_IVOR7 +#define IVOR8 SPRN_IVOR8 +#define IVOR9 SPRN_IVOR9 +#define IVOR10 SPRN_IVOR10 +#define IVOR11 SPRN_IVOR11 +#define IVOR12 SPRN_IVOR12 +#define IVOR13 SPRN_IVOR13 +#define IVOR14 SPRN_IVOR14 +#define IVOR15 SPRN_IVOR15 +#define IVOR32 SPRN_IVOR32 +#define IVOR33 SPRN_IVOR33 +#define IVOR34 SPRN_IVOR34 +#define IVOR35 SPRN_IVOR35 +#define MCSRR0 SPRN_MCSRR0 +#define MCSRR1 SPRN_MCSRR1 +#define L1CSR0 SPRN_L1CSR0 +#define L1CSR1 SPRN_L1CSR1 +#define L1CSR2 SPRN_L1CSR2 +#define L1CFG0 SPRN_L1CFG0 +#define L1CFG1 SPRN_L1CFG1 +#define L2CFG0 SPRN_L2CFG0 +#define L2CSR0 SPRN_L2CSR0 +#define L2CSR1 SPRN_L2CSR1 +#define MCSR SPRN_MCSR +#define MMUCSR0 SPRN_MMUCSR0 +#define BUCSR SPRN_BUCSR +#define PID0 SPRN_PID +#define PID1 SPRN_PID1 +#define PID2 SPRN_PID2 +#define MAS0 SPRN_MAS0 +#define MAS1 SPRN_MAS1 +#define MAS2 SPRN_MAS2 +#define MAS3 SPRN_MAS3 +#define MAS4 SPRN_MAS4 +#define MAS5 SPRN_MAS5 +#define MAS6 SPRN_MAS6 +#define MAS7 SPRN_MAS7 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR @@ -718,201 +718,201 @@ /* Device Control Registers */ -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ -#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ -#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ -#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ -#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ -#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ -#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ -#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ -#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ -#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ -#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ -#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ -#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ -#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ -#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ -#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ -#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ -#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ -#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ -#define DCRN_DMASR 0x0E0 /* DMA Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 +#define DCRN_BEAR 0x090 /* Bus Error Address Register */ +#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 +#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ +#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ +#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ +#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ +#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ +#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ +#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ +#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ +#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ +#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ +#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ +#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ +#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ +#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ +#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ +#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ +#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ +#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ +#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ +#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ +#define DCRN_DMASR 0x0E0 /* DMA Status Register */ +#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ +#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ +#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 /* System-On-Chip Version Register */ /* System-On-Chip Version Register (SVR) field extraction */ -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ /* Processor Version Register */ /* Processor Version Register (PVR) field extraction */ -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ /* * AMCC has further subdivided the standard PowerPC 16-bit version and * revision subfields of the PVR for the PowerPC 403s into the following: */ -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ /* e600 core PVR fields */ -#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ -#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ -#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ -#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ /* Processor Version Numbers */ -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) -#define PVR_86xx 0x80040000 +#define PVR_86xx 0x80040000 #define PVR_VIRTEX5 0x7ff21912 @@ -922,29 +922,29 @@ * differentiated by the version number in the Communication Processor * Module (CPM). */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 /* * PowerQUICC II family processors report different PVR values depending * on silicon process (HiP3, HiP4, HiP7, etc.) */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 #define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 +#define PVR_8260_HIP7RA 0x80822014 /* * MPC 52xx */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 /* * System Version Register @@ -952,26 +952,26 @@ /* System Version Register (SVR) field extraction */ -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ /* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) #else #if defined(CONFIG_MPC83xx) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) #endif #endif @@ -979,98 +979,98 @@ * SVR_SOC_VER() Version Values */ -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 -#define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 #define _GLOBAL(n)\ - .globl n;\ + .globl n;\ n: /* Macros for setting and retrieving special purpose registers */ -#define stringify(s) tostring(s) -#define tostring(s) #s +#define stringify(s) tostring(s) +#define tostring(s) #s -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) /* Segment Registers */ -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 #ifndef __ASSEMBLY__ struct cpu_type { - char name[15]; - u32 soc_ver; + char name[15]; + u32 soc_ver; }; struct cpu_type *identify_cpu(u32 ver); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } + { .name = #n, .soc_ver = SVR_##v, } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} @@ -1120,65 +1120,65 @@ extern struct task_struct *last_task_used_altivec; * as soon as I get around to remapping the io areas with the BATs * to match the mac we can raise this. -- Cort */ -#define TASK_SIZE (0x80000000UL) +#define TASK_SIZE (0x80000000UL) /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) typedef struct { - unsigned long seg; + unsigned long seg; } mm_segment_t; struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ #ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; #endif /* CONFIG_ALTIVEC */ }; -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) #define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ } /* * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) + * be in kernel space. (Could vm_end == vm_start perhaps?) */ #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } /* * Return saved PC of a blocked thread. For now, this is the "user" PC */ static inline unsigned long thread_saved_pc(struct thread_struct *t) { - return (t->regs) ? t->regs->nip : 0; + return (t->regs) ? t->regs->nip : 0; } -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) unsigned long get_wchan(struct task_struct *p); @@ -1190,16 +1190,16 @@ unsigned long get_wchan(struct task_struct *p); */ #define THREAD_SIZE (2*PAGE_SIZE) #define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) /* in process.c - for early bootup debug -- Cort */ int ll_printk(const char *, ...); void ll_puts(const char *); -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) /* In misc.c */ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); @@ -1212,7 +1212,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #define have_of 0 #elif defined(CONFIG_OAK) #define _machine _MACH_oak -#define have_of 0 +#define have_of 0 #elif defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h index d531de889b..d450803f96 100644 --- a/libcpu/ppc/ppc405/include/asm/ptrace.h +++ b/libcpu/ppc/ppc405/include/asm/ptrace.h @@ -26,27 +26,27 @@ #define PPC_REG unsigned long #endif struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ }__attribute__((packed)) CELL_STACK_FRAME_t; #endif -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ /* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 +#define __SIGNAL_FRAMESIZE 64 #define instruction_pointer(regs) ((regs)->nip) #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) @@ -56,51 +56,51 @@ struct pt_regs { * These can't be changed without breaking binary compatibility * with MkLinux, etc. */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 -#define PT_NIP 32 -#define PT_MSR 33 +#define PT_NIP 32 +#define PT_MSR 33 #ifdef __KERNEL__ #define PT_ORIG_R3 34 #endif -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ #define PT_FPR31 (PT_FPR0 + 2*31) #define PT_FPSCR (PT_FPR0 + 2*32 + 1) diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h index 6413895325..88c38e62cc 100644 --- a/libcpu/ppc/ppc405/include/asm/types.h +++ b/libcpu/ppc/ppc405/include/asm/types.h @@ -27,7 +27,7 @@ __extension__ typedef unsigned long long __u64; #endif typedef struct { - __u32 u[4]; + __u32 u[4]; } __attribute__((aligned(16))) vector128; #ifdef __KERNEL__ diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h index dc01549b01..d464a3e371 100644 --- a/libcpu/ppc/ppc405/include/config.h +++ b/libcpu/ppc/ppc405/include/config.h @@ -1,25 +1,25 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ -#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ +#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ #define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ #define CONFIG_SYS_HZ 100 -#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) +#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) /* * UART */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} @@ -33,26 +33,26 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE 1 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) */ -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_ADDR0 0x555 #define CONFIG_SYS_FLASH_ADDR1 0x2aa #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 27a528e2f0..f072dd07e1 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -28,18 +28,18 @@ rt_uint32_t rt_thread_switch_interrput_flag; rt_isr_handler_t rt_hw_interrupt_handler(rt_uint32_t vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } void uic_irq_ack(unsigned int vec) { - mtdcr(uic0sr, UIC_MASK(vec)); + mtdcr(uic0sr, UIC_MASK(vec)); } void uic_int_handler (unsigned int vec) { - rt_interrupt_enter(); + rt_interrupt_enter(); /* Allow external interrupts to the CPU. */ if (isr_table [vec].handler != 0) @@ -47,91 +47,91 @@ void uic_int_handler (unsigned int vec) (*isr_table[vec].handler)(vec, isr_table[vec].param); } uic_irq_ack(vec); - + rt_interrupt_leave(); } /* handler for UIC interrupt */ void uic_interrupt(rt_uint32_t uic_base, int vec_base) { - int vec; - rt_uint32_t uic_msr; - rt_uint32_t msr_shift; + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = get_dcr(uic_base + UIC_MSR); - msr_shift = uic_msr; - vec = vec_base; + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; - while (msr_shift != 0) - { - if (msr_shift & 0x80000000) - uic_int_handler(vec); + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } } -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, void* param, const char* name) { - int intVal; + int intVal; rt_isr_handler_t old_handler; - if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) - { + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { return RT_NULL; /* out of range */ - } - + } + /* install the handler in the system interrupt table */ intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ old_handler = isr_table[vector].handler; isr_table[vector].handler = new_handler; isr_table[vector].param = param; - + rt_hw_interrupt_enable (intVal); } void rt_hw_interrupt_mask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); } void rt_hw_interrupt_unmask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); } void rt_hw_interrupt_init() { - int vector; + int vector; rt_uint32_t pit_value; pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); /* enable pit */ - mtspr(SPRN_PIT, pit_value); - mtspr(SPRN_TCR, 0x4400000); + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); - /* set default interrupt handler */ + /* set default interrupt handler */ for (vector = 0; vector < MAX_HANDLERS; vector++) { - isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; + isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; isr_table [vector].param = RT_NULL; } - /* initialize interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrput_flag = 0; + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; } /*@}*/ diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h index 32fcd56307..28341ead64 100644 --- a/libcpu/ppc/ppc405/io.h +++ b/libcpu/ppc/ppc405/io.h @@ -12,82 +12,82 @@ */ static inline int in_8(const volatile unsigned char __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } static inline void out_8(volatile unsigned char __iomem *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } extern inline int in_le16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } extern inline int in_be16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } extern inline void out_le16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } extern inline void out_be16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } extern inline unsigned in_le32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } extern inline unsigned in_be32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } extern inline void out_le32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } extern inline void out_be32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } #endif diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c index ac68a13748..1fc9039769 100644 --- a/libcpu/ppc/ppc405/serial.c +++ b/libcpu/ppc/ppc405/serial.c @@ -12,18 +12,18 @@ #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 /*-----------------------------------------------------------------------------+ | Line Status Register. @@ -40,280 +40,280 @@ /* PPC405 serial device */ struct rt_ppc405_serial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; struct rt_ppc405_serial ppc405_serial; /* serial character device */ static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable "RX Data Available" Interrupt on UART */ - out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; - /* init UART rx interrupt */ - rt_hw_interrupt_unmask(device->irqno); - } + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable "RX Data Available" Interrupt on UART */ + out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); - return RT_EOK; + /* init UART rx interrupt */ + rt_hw_interrupt_unmask(device->irqno); + } + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* mask UART rx interrupt */ - rt_hw_interrupt_mask(device->irqno); - } + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* mask UART rx interrupt */ + rt_hw_interrupt_mask(device->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_ppc405_serial* device; + rt_uint8_t* ptr; + struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (device->read_index != device->save_index) - { - *ptr = device->rx_buffer[device->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (device->read_index != device->save_index) + { + *ptr = device->rx_buffer[device->read_index]; - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } - else - { - /* no data in rx buffer */ + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } - /* polling mode */ - RT_ASSERT(0); + /* polling mode */ + RT_ASSERT(0); - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - char *ptr; - struct rt_ppc405_serial* device; + char *ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); + /* polling write */ + ptr = (char *)buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); + } - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); - } + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + ptr ++; + size --; + } + } + else + { + while (size) + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - ptr ++; - size --; - } - } - else - { - while (size) - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_serial_set_baudrate(struct rt_ppc405_serial* device) { - rt_uint32_t bdiv; + rt_uint32_t bdiv; - bdiv = 115200; - out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ - out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + bdiv = 115200; + out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ } void rt_serial_isr(int irqno, void* param) { - unsigned char status; - struct rt_ppc405_serial *device; + unsigned char status; + struct rt_ppc405_serial *device; + + device = (struct rt_ppc405_serial*) param; + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - device = (struct rt_ppc405_serial*) param; - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + if (status & 0x01) + { + rt_base_t level; - if (status & 0x01) - { - rt_base_t level; + while (status & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - while (status & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* read character */ + device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); + device->save_index ++; + if (device->save_index >= RT_UART_RX_BUFFER_SIZE) + device->save_index = 0; - /* read character */ - device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); - device->save_index ++; - if (device->save_index >= RT_UART_RX_BUFFER_SIZE) - device->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (device->save_index == device->read_index) - { - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (device->save_index == device->read_index) + { + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* check error */ - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) - { - out_8((rt_uint8_t *)device->hw_base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } + /* check error */ + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) + { + out_8((rt_uint8_t *)device->hw_base + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - } + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + } - /* invoke callback */ - if(device->parent.rx_indicate != RT_NULL) - { - device->parent.rx_indicate(&device->parent, 1); - } - } + /* invoke callback */ + if(device->parent.rx_indicate != RT_NULL) + { + device->parent.rx_indicate(&device->parent, 1); + } + } } void rt_hw_serial_init(void) { - volatile rt_uint8_t val; - struct rt_ppc405_serial* device; + volatile rt_uint8_t val; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + device->parent.type = RT_Device_Class_Char; - device = (struct rt_ppc405_serial*) &ppc405_serial; - device->parent.type = RT_Device_Class_Char; - - device->hw_base = UART0_BASE; - device->baudrate = 115200; - device->irqno = VECNUM_U0; - rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */ + device->hw_base = UART0_BASE; + device->baudrate = 115200; + device->irqno = VECNUM_U0; + rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */ - rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); - device->read_index = device->save_index = 0; + rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); + device->read_index = device->save_index = 0; - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ - /* setup baudrate */ - rt_serial_set_baudrate(device); - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ - out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ - val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ - out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ - out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ + /* setup baudrate */ + rt_serial_set_baudrate(device); + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ + out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ + val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ + out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ + out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ - device->parent.type = RT_Device_Class_Char; - device->parent.init = rt_serial_init; - device->parent.open = rt_serial_open; - device->parent.close = rt_serial_close; - device->parent.read = rt_serial_read; - device->parent.write = rt_serial_write; - device->parent.control = rt_serial_control; - device->parent.user_data = RT_NULL; + device->parent.type = RT_Device_Class_Char; + device->parent.init = rt_serial_init; + device->parent.open = rt_serial_open; + device->parent.close = rt_serial_close; + device->parent.read = rt_serial_read; + device->parent.write = rt_serial_write; + device->parent.control = rt_serial_control; + device->parent.user_data = RT_NULL; - rt_device_register(&device->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + rt_device_register(&device->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); } diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c index 1deecbc92b..3ee754da23 100644 --- a/libcpu/ppc/ppc405/traps.c +++ b/libcpu/ppc/ppc405/traps.c @@ -7,8 +7,8 @@ extern unsigned long search_exception_table(unsigned long); /* THIS NEEDS CHANGING to use the board info structure. */ -#define END_OF_MEM 0x800000 -#define UICB0_ALL 0 +#define END_OF_MEM 0x800000 +#define UICB0_ALL 0 #define ESR_MCI 0x80000000 #define ESR_PIL 0x08000000 diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c index 6cb8aaf3e7..622e1bd321 100644 --- a/libcpu/risc-v/common/cpuport.c +++ b/libcpu/risc-v/common/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h index d6cec2f0cf..e625d9f91f 100644 --- a/libcpu/risc-v/common/cpuport.h +++ b/libcpu/risc-v/common/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,13 +30,13 @@ #define FSTORE fsd #define FLOAD fld #define FREGBYTES 8 -#define rv_floatreg_t rt_int64_t +#define rv_floatreg_t rt_int64_t #endif #ifdef ARCH_RISCV_FPU_S #define FSTORE fsw #define FLOAD flw #define FREGBYTES 4 -#define rv_floatreg_t rt_int32_t +#define rv_floatreg_t rt_int32_t #endif #endif diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h index 0b321c6de4..35d009ad53 100644 --- a/libcpu/risc-v/common/riscv-ops.h +++ b/libcpu/risc-v/common/riscv-ops.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h index 1da14b2e45..53e19d2962 100644 --- a/libcpu/risc-v/common/riscv-plic.h +++ b/libcpu/risc-v/common/riscv-plic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c index 8c57dfeafc..113df9b3e2 100644 --- a/libcpu/risc-v/k210/cpuport_smp.c +++ b/libcpu/risc-v/k210/cpuport_smp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c index b582599daf..934acbdbf8 100644 --- a/libcpu/risc-v/k210/interrupt.c +++ b/libcpu/risc-v/k210/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c index 144f7f1fff..2a76b50b6d 100644 --- a/libcpu/risc-v/k210/tick.c +++ b/libcpu/risc-v/k210/tick.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h index 0821004263..0bfd6f62e8 100644 --- a/libcpu/risc-v/k210/tick.h +++ b/libcpu/risc-v/k210/tick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c index 717e9bb1c7..e74d174a54 100644 --- a/libcpu/risc-v/nuclei/cpuport.c +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -26,23 +26,23 @@ /** * @brief from thread used interrupt context switch - * + * */ volatile rt_ubase_t rt_interrupt_from_thread = 0; /** * @brief to thread used interrupt context switch - * + * */ volatile rt_ubase_t rt_interrupt_to_thread = 0; /** * @brief flag to indicate context switch in interrupt or not - * + * */ volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; /** * @brief thread stack frame of saved context - * + * */ struct rt_hw_stack_frame { @@ -121,7 +121,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, /** * @brief Do rt-thread context switch in interrupt context - * + * * @param from thread sp of from thread * @param to thread sp of to thread */ @@ -137,7 +137,7 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) /** * @brief Do rt-thread context switch in task context - * + * * @param from thread sp of from thread * @param to thread sp of to thread */ @@ -150,7 +150,7 @@ void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) /** * @brief shutdown CPU - * + * */ RT_WEAK void rt_hw_cpu_shutdown() { @@ -166,9 +166,9 @@ RT_WEAK void rt_hw_cpu_shutdown() /** * @brief Do extra task switch code - * + * * @details - * + * * - Clear software timer interrupt request flag * - clear rt_thread_switch_interrupt_flag to 0 */ @@ -181,9 +181,9 @@ void rt_hw_taskswitch(void) /** * @brief Setup systimer and software timer interrupt - * - * @details - * + * + * @details + * * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level * - Enable these two interrupts @@ -216,7 +216,7 @@ void rt_hw_ticksetup(void) /** * @brief This is the timer interrupt service routine. - * + * */ void SysTick_Handler(void) { @@ -235,13 +235,13 @@ void SysTick_Handler(void) /** * @brief Disable cpu interrupt - * + * * @details - * + * * - Disable cpu interrupt by clear MIE bit in MSTATUS * - Return the previous value in MSTATUS before clear MIE bit - * - * @return the previous value in MSTATUS before clear MIE bit + * + * @return the previous value in MSTATUS before clear MIE bit */ rt_base_t rt_hw_interrupt_disable(void) { @@ -250,7 +250,7 @@ rt_base_t rt_hw_interrupt_disable(void) /** * @brief Restore previous saved interrupt status - * + * * @param level previous saved MSTATUS value */ void rt_hw_interrupt_enable(rt_base_t level) diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h index 3736f0078a..1f9634d4b1 100644 --- a/libcpu/risc-v/nuclei/cpuport.h +++ b/libcpu/risc-v/nuclei/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 diff --git a/libcpu/risc-v/rv32m1/interrupt.c b/libcpu/risc-v/rv32m1/interrupt.c index 72cb344ff7..8da0dcfda6 100644 --- a/libcpu/risc-v/rv32m1/interrupt.c +++ b/libcpu/risc-v/rv32m1/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c index 998bfdc340..0eaf5ffbce 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.c +++ b/libcpu/risc-v/t-head/e906/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, /** - * This function will disable global interrupt + * This function will disable global interrupt * * @param none * @@ -145,7 +145,7 @@ rt_base_t rt_hw_interrupt_disable(void) } /** - * This function will ennable global interrupt + * This function will ennable global interrupt * * @param level not used * diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h index 90efc07653..20302f44aa 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.h +++ b/libcpu/risc-v/t-head/e906/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,13 +42,13 @@ #define FSTORE fsd #define FLOAD fld #define FREGBYTES 8 -#define rv_floatreg_t rt_int64_t +#define rv_floatreg_t rt_int64_t #endif #ifdef ARCH_RISCV_FPU_S #define FSTORE fsw #define FLOAD flw #define FREGBYTES 4 -#define rv_floatreg_t rt_int32_t +#define rv_floatreg_t rt_int32_t #endif #endif diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index a01f598e99..00f9e26ba9 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -34,9 +34,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /* stack frame*/ struct stack_frame { - rt_uint32_t ACCLO; + rt_uint32_t ACCLO; rt_uint32_t ACCHI; - rt_uint32_t FPSW; + rt_uint32_t FPSW; rt_uint32_t R1; rt_uint32_t R2; rt_uint32_t R3; @@ -53,21 +53,21 @@ struct stack_frame rt_uint32_t R14; rt_uint32_t R15; //there is not R0 register,it is special for stack pointer - rt_uint32_t PC; - rt_uint32_t PSW; + rt_uint32_t PC; + rt_uint32_t PSW; }; /** * Initilial the thread stack. - * + * * @author LXZ (2014/11/8) - * - * @param void* tentry - * @param void* parameter - * @param rt_uint8_t* stack_addr - * @param void* texit - * - * @return rt_uint8_t* + * + * @param void* tentry + * @param void* parameter + * @param rt_uint8_t* stack_addr + * @param void* texit + * + * @return rt_uint8_t* */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) @@ -77,7 +77,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, unsigned long i; stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)texit; + *(stk) = (unsigned long)texit; stack_frame = (struct stack_frame *)(stack_addr - sizeof(struct stack_frame)) ; //Initilial all register @@ -85,12 +85,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; } - + stack_frame->PSW = (unsigned long)0x00030000 ; /* psw */ stack_frame->PC = (unsigned long)tentry; /* thread entery*/ stack_frame->R1 = (unsigned long )parameter; /* r1 : parameter */ stack_frame->FPSW = 0x00000100; /* fpsw */ - + return(rt_uint8_t *)stack_frame; } @@ -99,16 +99,16 @@ extern void list_thread(void); #endif extern rt_thread_t rt_current_thread; /** - * deal exception - * + * deal exception + * * @author LXZ (2014/11/8) - * - * @param struct stack_frame* exception_contex + * + * @param struct stack_frame* exception_contex */ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) { if (exception_contex != RT_NULL) { - rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); + rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); rt_kprintf("pc: 0x%08x\n", exception_contex->PC); rt_kprintf("r0: 0x%08x\n", exception_contex->R1); rt_kprintf("r0: 0x%08x\n", exception_contex->R2); @@ -134,17 +134,17 @@ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) list_thread(); #endif while (1); - + } /** * switch thread in interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) { @@ -159,11 +159,11 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) } /** * switch thread out the interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) { @@ -179,7 +179,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) /** * shut down the chip - * + * * @author LXZ (2014/11/8) */ RT_WEAK void rt_hw_cpu_shutdown(void) @@ -190,10 +190,10 @@ RT_WEAK void rt_hw_cpu_shutdown(void) } /** * switch to the first thread,it just call one time - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t to + * + * @param rt_uint32_t to */ void rt_hw_context_switch_to(rt_uint32_t to) { diff --git a/libcpu/sim/posix/cpu_port.c b/libcpu/sim/posix/cpu_port.c index eb1ae4865c..dc3e9379dd 100644 --- a/libcpu/sim/posix/cpu_port.c +++ b/libcpu/sim/posix/cpu_port.c @@ -173,8 +173,8 @@ static void *thread_run(void *parameter) /*TODO: * 最后一行的pthread_exit永远没有机会执行，这是因为在threead->exit函数中 * 会发生线程切换，并永久将此pthread线程挂起，所以更完美的解决方案是在这 - * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。 - */ + * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。 + */ //sem_destroy(&thread->sem); pthread_exit(NULL); diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index cc8ad9a25c..621420e7bf 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -5,7 +5,7 @@ * Version : V1.00.00 * * By : prife -* Version : V1.00.01 +* Version : V1.00.01 ************************************************************************************************************************ */ @@ -47,10 +47,10 @@ const DWORD MS_VC_EXCEPTION=0x406D1388; #pragma pack(push,8) typedef struct tagTHREADNAME_INFO { - DWORD dwType; // Must be 0x1000. - LPCSTR szName; // Pointer to name (in user addr space). - DWORD dwThreadID; // Thread ID (-1=caller thread). - DWORD dwFlags; // Reserved for future use, must be zero. + DWORD dwType; // Must be 0x1000. + LPCSTR szName; // Pointer to name (in user addr space). + DWORD dwThreadID; // Thread ID (-1=caller thread). + DWORD dwFlags; // Reserved for future use, must be zero. } THREADNAME_INFO; #pragma pack(pop) @@ -115,19 +115,19 @@ static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam); static void SetThreadName(DWORD dwThreadID, char* threadName) { #if defined(_MSC_VER) - THREADNAME_INFO info; - info.dwType = 0x1000; - info.szName = threadName; - info.dwThreadID = dwThreadID; - info.dwFlags = 0; + THREADNAME_INFO info; + info.dwType = 0x1000; + info.szName = threadName; + info.dwThreadID = dwThreadID; + info.dwFlags = 0; - __try - { - RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); - } - __except(EXCEPTION_EXECUTE_HANDLER) - { - } + __try + { + RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); + } + __except(EXCEPTION_EXECUTE_HANDLER) + { + } #endif } @@ -144,15 +144,15 @@ static void SetThreadName(DWORD dwThreadID, char* threadName) static DWORD WINAPI thread_run( LPVOID lpThreadParameter ) { - rt_thread_t tid = rt_thread_self(); - win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; + rt_thread_t tid = rt_thread_self(); + win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; - SetThreadName(GetCurrentThreadId(), tid->name); + SetThreadName(GetCurrentThreadId(), tid->name); - pWinThread->Entry(pWinThread->Param); + pWinThread->Entry(pWinThread->Param); - pWinThread->Exit(); - return 0; + pWinThread->Exit(); + return 0; } rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit) @@ -261,7 +261,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_interrupt_to_thread = *((rt_uint32_t *)(to)); - //trigger YIELD exception(cause context switch) + //trigger YIELD exception(cause context switch) TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); } /*** rt_hw_context_switch_interrupt ***/ @@ -312,7 +312,7 @@ void rt_hw_context_switch(rt_uint32_t from, */ void rt_hw_context_switch_to(rt_uint32_t to) { - //set to thread + //set to thread rt_interrupt_to_thread = *((rt_uint32_t *)(to)); //clear from thread diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 15041fc846..44876a5af5 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c index a4e07da061..966277295d 100644 --- a/libcpu/unicore32/sep6200/cpu.c +++ b/libcpu/unicore32/sep6200/cpu.c @@ -20,23 +20,23 @@ #ifdef __GNUC__ rt_inline void cache_invalid(void) { - __asm__ volatile ("movc p0.c5, r1, #28\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"memory", "cc" - ); + __asm__ volatile ("movc p0.c5, r1, #28\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"memory", "cc" + ); } rt_inline void cache_enable(void) { - __asm__ volatile ( "movc r1, p0.c1, #0\n" - "or r1, r1, #0xc\n" - "movc p0.c1, r1, #0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"r0", "memory", "cc"); + __asm__ volatile ( "movc r1, p0.c1, #0\n" + "or r1, r1, #0xc\n" + "movc p0.c1, r1, #0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"r0", "memory", "cc"); } rt_inline void clean_dcache(void) @@ -45,8 +45,8 @@ rt_inline void clean_dcache(void) "movc p0.c5, ip, #10\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : - : - :"ip", "memory", "cc"); + : + :"ip", "memory", "cc"); } rt_inline rt_uint32_t icache_status(void) @@ -77,7 +77,7 @@ rt_inline rt_uint32_t dcache_status(void) rt_inline void dcache_flush(void) { - __asm__ volatile ( "mov ip, #0\n" + __asm__ volatile ( "mov ip, #0\n" "movc p0.c5, ip, #14\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -87,7 +87,7 @@ rt_inline void dcache_flush(void) rt_inline void icache_invalid(void) { - __asm__ volatile ( "mov r0, #0\n" + __asm__ volatile ( "mov r0, #0\n" "movc p0.c5, r0, #20\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -107,8 +107,8 @@ rt_inline void dcache_invalid(void) rt_inline void icache_disable(void) { - icache_invalid(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + icache_invalid(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #8\n" "movc p0.c1, r0, #0\n" : @@ -118,8 +118,8 @@ rt_inline void icache_disable(void) rt_inline void dcache_disable(void) { - dcache_flush(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + dcache_flush(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #20\n" "movc p0.c1, r0, #0\n" : @@ -170,7 +170,7 @@ rt_inline void dcache_enable(void) */ void rt_hw_cpu_icache_enable() { - icache_enable(); + icache_enable(); } /** @@ -179,7 +179,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - icache_disable(); + icache_disable(); } /** @@ -188,7 +188,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return icache_status(); + return icache_status(); } /** @@ -197,7 +197,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - dcache_enable(); + dcache_enable(); } /** @@ -206,7 +206,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - dcache_disable(); + dcache_disable(); } /** @@ -215,29 +215,29 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return dcache_status(); + return dcache_status(); } static void sep6200_reset(rt_uint32_t addr) { __asm__ volatile ( "mov ip, #0\n" - "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ - "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - "movc ip, p0.c1, #0\n" /*ctrl register*/ - "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ - "movc p0.c1, ip, #0\n" - "nop\n" - "mov pc, %0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : "=&r" (addr) - : - :"memory", "cc"); + "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ + "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + "movc ip, p0.c1, #0\n" /*ctrl register*/ + "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ + "movc p0.c1, ip, #0\n" + "nop\n" + "mov pc, %0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : "=&r" (addr) + : + :"memory", "cc"); } static void sep6200_poweroff(void) { - rt_kprintf("sep6200 power off not implemented\n"); + rt_kprintf("sep6200 power off not implemented\n"); while(1); } @@ -248,12 +248,12 @@ static void sep6200_poweroff(void) RT_WEAK void rt_hw_cpu_reset() { - rt_kprintf("Soft reset, Restarting system...\n"); - sep6200_reset(0); + rt_kprintf("Soft reset, Restarting system...\n"); + sep6200_reset(0); - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -262,15 +262,15 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - sep6200_poweroff(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + sep6200_poweroff(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c index 2737849903..b34e648630 100644 --- a/libcpu/unicore32/sep6200/interrupt.c +++ b/libcpu/unicore32/sep6200/interrupt.c @@ -12,38 +12,38 @@ #include <rthw.h> #include <sep6200.h> -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 #define SEP6200_IRQ_TYPE 0 #define SEP6200_FIQ_TYPE 1 -#define int_enable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ - }while(0) -#define int_disable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ - }while(0) -#define mask_all_int(int_type) \ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ - }\ - }while(0) +#define int_enable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ + }while(0) +#define int_disable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ + }while(0) +#define mask_all_int(int_type) \ + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ + }\ + }while(0) #define unmask_all_int(int_type)\ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ - }\ - }while(0) + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ + }\ + }while(0) #define SEP6200_INT_SET(intnum) \ do{ \ @@ -99,27 +99,27 @@ void rt_hw_interrupt_umask(int irq); rt_inline void sep6200_irq_enable(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_disable(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_inline void sep6200_irq_unmask(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_mask(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -127,26 +127,26 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) */ void rt_hw_interrupt_init(void) { - rt_int32_t i; - register rt_uint32_t idx; + rt_int32_t i; + register rt_uint32_t idx; - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - } - int_disable_all(); - mask_all_int(SEP6200_FIQ_TYPE); + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { + isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + int_disable_all(); + mask_all_int(SEP6200_FIQ_TYPE); - //int_enable_all(); - unmask_all_int(SEP6200_IRQ_TYPE); + //int_enable_all(); + unmask_all_int(SEP6200_IRQ_TYPE); - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } @@ -157,11 +157,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to mask\n"); - } else { - sep6200_irq_mask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to mask\n"); + } else { + sep6200_irq_mask(irq); + } } @@ -171,11 +171,11 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to unmask\n"); - } else { - sep6200_irq_unmask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to unmask\n"); + } else { + sep6200_irq_unmask(irq); + } } /** @@ -196,7 +196,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/unicore32/sep6200/sep6200.h b/libcpu/unicore32/sep6200/sep6200.h index 9aced7fbbb..773b505a02 100644 --- a/libcpu/unicore32/sep6200/sep6200.h +++ b/libcpu/unicore32/sep6200/sep6200.h @@ -15,58 +15,58 @@ /*Core definations*/ #define PRIVMODE 0x13 -#define Mode_USR 0x10 -#define Mode_REAL 0x11 -#define Mode_IRQ 0x12 -#define Mode_PRIV 0x13 -#define Mode_TRAP 0x17 -#define Mode_EXT 0x1B -#define Mode_SUSR 0x1F +#define Mode_USR 0x10 +#define Mode_REAL 0x11 +#define Mode_IRQ 0x12 +#define Mode_PRIV 0x13 +#define Mode_TRAP 0x17 +#define Mode_EXT 0x1B +#define Mode_SUSR 0x1F /* * Address */ -#define SEP6200_VIC_BASE 0xb0000000 -#define SEP6200_PMU_BASE 0xb0001000 -#define SEP6200_RTC_BASE 0xb0002000 -#define SEP6200_TIMER_BASE 0xb0003000 -#define SEP6200_PWM_BASE 0xb0004000 -#define SEP6200_GPIO_BASE 0xb0006000 -#define SEP6200_TOUCH_ADC 0xb0007000 -#define SEP6200_SYSCTL_BASE 0xb0008000 -#define SEP6200_UART0_BASE 0xb1000000 -#define SEP6200_UART1_BASE 0xb1001000 -#define SEP6200_UART2_BASE 0xb1002000 -#define SEP6200_UART3_BASE 0xb1003000 -#define SEP6200_SSI1_BASE 0xb1004000 -#define SEP6200_SSI2_BASE 0xb1005000 -#define SEP6200_SSI3_BASE 0xb1006000 -#define SEP6200_I2C_BASE 0xb1007000 -#define SEP6200_I2S_BASE 0xb1008000 +#define SEP6200_VIC_BASE 0xb0000000 +#define SEP6200_PMU_BASE 0xb0001000 +#define SEP6200_RTC_BASE 0xb0002000 +#define SEP6200_TIMER_BASE 0xb0003000 +#define SEP6200_PWM_BASE 0xb0004000 +#define SEP6200_GPIO_BASE 0xb0006000 +#define SEP6200_TOUCH_ADC 0xb0007000 +#define SEP6200_SYSCTL_BASE 0xb0008000 +#define SEP6200_UART0_BASE 0xb1000000 +#define SEP6200_UART1_BASE 0xb1001000 +#define SEP6200_UART2_BASE 0xb1002000 +#define SEP6200_UART3_BASE 0xb1003000 +#define SEP6200_SSI1_BASE 0xb1004000 +#define SEP6200_SSI2_BASE 0xb1005000 +#define SEP6200_SSI3_BASE 0xb1006000 +#define SEP6200_I2C_BASE 0xb1007000 +#define SEP6200_I2S_BASE 0xb1008000 #define SEP6200_USB_BASE 0xb1010000 #define SEP6200_DMAC2_BASE 0xb1011000 #define SEP6200_ESRAM_BASE 0xb2000000 -#define SEP6200_NORREG_BASE0xb2020000 -#define SEP6200_SDIO1_BASE 0xb2022000 -#define SEP6200_SDIO2_BASE 0xb2023000 -#define SEP6200_LCDC_BASE 0xb2025000 -#define SEP6200_VPU_BASE 0xb2026000 -#define SEP6200_DMAC1_BASE 0xb2027000 -#define SEP6200_DDR2_REG 0xb3000000 -#define SEP6200_DDR_MEM 0x40000000 +#define SEP6200_NORREG_BASE0xb2020000 +#define SEP6200_SDIO1_BASE 0xb2022000 +#define SEP6200_SDIO2_BASE 0xb2023000 +#define SEP6200_LCDC_BASE 0xb2025000 +#define SEP6200_VPU_BASE 0xb2026000 +#define SEP6200_DMAC1_BASE 0xb2027000 +#define SEP6200_DDR2_REG 0xb3000000 +#define SEP6200_DDR_MEM 0x40000000 -#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) -#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) -#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) -#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) +#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) +#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) +#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) +#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) #define SEP6200_TIMER_T1LCR (SEP6200_TIMER_BASE + 0X000) @@ -348,7 +348,7 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ #endif typedef int ER; /* Error code. A signed integer. */ @@ -368,88 +368,88 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - rt_uint32_t r12; - rt_uint32_t r13; - rt_uint32_t r14; - rt_uint32_t r15; - rt_uint32_t r16; - rt_uint32_t r17; - rt_uint32_t r18; - rt_uint32_t r19; - rt_uint32_t r20; - rt_uint32_t r21; - rt_uint32_t r22; - rt_uint32_t r23; - rt_uint32_t r24; - rt_uint32_t sb; - rt_uint32_t sl; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t asr; - rt_uint32_t bsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + rt_uint32_t r12; + rt_uint32_t r13; + rt_uint32_t r14; + rt_uint32_t r15; + rt_uint32_t r16; + rt_uint32_t r17; + rt_uint32_t r18; + rt_uint32_t r19; + rt_uint32_t r20; + rt_uint32_t r21; + rt_uint32_t r22; + rt_uint32_t r23; + rt_uint32_t r24; + rt_uint32_t sb; + rt_uint32_t sl; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t asr; + rt_uint32_t bsr; + rt_uint32_t ORIG_r0; }; /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.c b/libcpu/unicore32/sep6200/serial.c index 9b594d87be..f91834b6a7 100644 --- a/libcpu/unicore32/sep6200/serial.c +++ b/libcpu/unicore32/sep6200/serial.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2013-03-16 Peng Fan Modified from sep4020 + * 2013-03-16 Peng Fan Modified from sep4020 */ #include <rtthread.h> #include <rthw.h> @@ -22,204 +22,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - -- size; + -- size; - /* move to next position */ - uart->int_tx->save_index ++; + /* move to next position */ + uart->int_tx->save_index ++; - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - ++ptr; --size; - } - } + ++ptr; --size; + } + } - /* set error code */ - rt_set_errno(err_code); + /* set error code */ + rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -227,49 +227,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; + struct serial_device* uart = (struct serial_device*) device->user_data; - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.h b/libcpu/unicore32/sep6200/serial.h index beeceb6165..dcfdc517d4 100644 --- a/libcpu/unicore32/sep6200/serial.h +++ b/libcpu/unicore32/sep6200/serial.h @@ -16,73 +16,73 @@ #include <sep6200.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_OVERRUN 0x02 /* overrun */ -#define USTAT_PARITY_ERR 0x04 /* parity error */ -#define USTAT_FRAME_ERROR 0x08 /* frame error */ -#define USTAT_BREAK 0x10 /* break */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define USTAT_RCV_ERR 0x80 /* receive error */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_OVERRUN 0x02 /* overrun */ +#define USTAT_PARITY_ERR 0x04 /* parity error */ +#define USTAT_FRAME_ERROR 0x08 /* frame error */ +#define USTAT_BREAK 0x10 /* break */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define USTAT_RCV_ERR 0x80 /* receive error */ -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep6200's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; + uartport* uart_device; - /* rx structure */ - struct serial_int_rx* int_rx; + /* rx structure */ + struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/unicore32/sep6200/stack.c b/libcpu/unicore32/sep6200/stack.c index 71b917c214..049b075f6c 100644 --- a/libcpu/unicore32/sep6200/stack.c +++ b/libcpu/unicore32/sep6200/stack.c @@ -28,47 +28,47 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r28 */ - *(--stk) = 0; /* r27 */ - *(--stk) = 0; /* r26 */ - *(--stk) = 0; /* r25 */ - *(--stk) = 0; /* r24 */ - *(--stk) = 0; /* r23 */ - *(--stk) = 0; /* r22 */ - *(--stk) = 0; /* r21 */ - *(--stk) = 0; /* r20 */ - *(--stk) = 0; /* r19 */ - *(--stk) = 0; /* r18 */ - *(--stk) = 0; /* r17 */ - *(--stk) = 0; /* r16 */ - *(--stk) = 0; /* r15 */ - *(--stk) = 0; /* r14 */ - *(--stk) = 0; /* r13 */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = Mode_PRIV; /* asr */ - *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r28 */ + *(--stk) = 0; /* r27 */ + *(--stk) = 0; /* r26 */ + *(--stk) = 0; /* r25 */ + *(--stk) = 0; /* r24 */ + *(--stk) = 0; /* r23 */ + *(--stk) = 0; /* r22 */ + *(--stk) = 0; /* r21 */ + *(--stk) = 0; /* r20 */ + *(--stk) = 0; /* r19 */ + *(--stk) = 0; /* r18 */ + *(--stk) = 0; /* r17 */ + *(--stk) = 0; /* r16 */ + *(--stk) = 0; /* r15 */ + *(--stk) = 0; /* r14 */ + *(--stk) = 0; /* r13 */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + *(--stk) = Mode_PRIV; /* asr */ + *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/unicore32/sep6200/trap.c b/libcpu/unicore32/sep6200/trap.c index b7d564aa57..f2f342cfbe 100644 --- a/libcpu/unicore32/sep6200/trap.c +++ b/libcpu/unicore32/sep6200/trap.c @@ -28,16 +28,16 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); - rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); - rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); - rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); - rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); + rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); + rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); + rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); + rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_extn(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("extn instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("extn instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_extn(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -138,7 +138,7 @@ void rt_hw_trap_irq(void) void *param; /* get the interrupt number */ - irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); + irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); /* get interrupt service routine */ isr_func = isr_table[irq].handler; @@ -148,13 +148,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/xilinx/microblaze/cpu.c b/libcpu/xilinx/microblaze/cpu.c index d37dcda350..37da5fd7c5 100755 --- a/libcpu/xilinx/microblaze/cpu.c +++ b/libcpu/xilinx/microblaze/cpu.c @@ -28,8 +28,8 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } diff --git a/libcpu/xilinx/microblaze/serial.c b/libcpu/xilinx/microblaze/serial.c index 17cca9f84d..1902f11710 100755 --- a/libcpu/xilinx/microblaze/serial.c +++ b/libcpu/xilinx/microblaze/serial.c @@ -12,7 +12,7 @@ * 2006-08-23 Bernard first version * 2009-05-14 Bernard add RT-THread device interface * - * 2011-12-17 nl1031 MicroBlaze + * 2011-12-17 nl1031 MicroBlaze */ #include <rthw.h> @@ -22,23 +22,23 @@ typedef volatile rt_uint32_t REG32; struct rt_mb_uart_lite_hw { - REG32 Rx_FIFO; // Receiver Holding Register - REG32 Tx_FIFO; // Transmitter Holding Register - REG32 STAT_REG; // Channel Status Register - REG32 CTRL_REG; // Control Register + REG32 Rx_FIFO; // Receiver Holding Register + REG32 Tx_FIFO; // Transmitter Holding Register + REG32 STAT_REG; // Channel Status Register + REG32 CTRL_REG; // Control Register }; struct rt_mb_uart_lite { - struct rt_device parent; + struct rt_device parent; - struct rt_mb_uart_lite_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_mb_uart_lite_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_mb_uart_lite serial1; @@ -46,271 +46,271 @@ struct rt_mb_uart_lite serial1; static void rt_hw_serial_isr(void) { - unsigned int status; - rt_base_t level; - struct rt_device* device; - struct rt_mb_uart_lite* serial = RT_NULL; + unsigned int status; + rt_base_t level; + struct rt_device* device; + struct rt_mb_uart_lite* serial = RT_NULL; #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get uart status register */ - status = serial->hw_base->STAT_REG; - while (status & XUL_SR_RX_FIFO_VALID_DATA) - { - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; + /* get uart status register */ + status = serial->hw_base->STAT_REG; + while (status & XUL_SR_RX_FIFO_VALID_DATA) + { + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - status = serial->hw_base->STAT_REG; - } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + status = serial->hw_base->STAT_REG; + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); } static rt_err_t rt_serial_init (rt_device_t dev) { - struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; + struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); + RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); - /* Read Character */ - *ptr = serial->hw_base->Rx_FIFO; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->Rx_FIFO; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - serial->hw_base->Tx_FIFO = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + serial->hw_base->Tx_FIFO = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - } + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifndef RT_USING_CONSOLE - int Status; + int Status; - /* - * Initialize the UartLite driver so that it is ready to use. - */ - Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); - if (Status != XST_SUCCESS) - { - return; - } + /* + * Initialize the UartLite driver so that it is ready to use. + */ + Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return; + } #endif #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; - serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; + serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } diff --git a/libcpu/xilinx/microblaze/stack.c b/libcpu/xilinx/microblaze/stack.c index 686fc078a3..87f1dfa014 100755 --- a/libcpu/xilinx/microblaze/stack.c +++ b/libcpu/xilinx/microblaze/stack.c @@ -29,43 +29,43 @@ extern void *_SDA2_BASE_; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - stk--; - stk--; - *stk-- = 0; /* r31 */ - *stk-- = 0; /* r30 */ - *stk-- = 0; /* r29 */ - *stk-- = 0; /* r28 */ - *stk-- = 0; /* r27 */ - *stk-- = 0; /* r26 */ - *stk-- = 0; /* r25 */ - *stk-- = 0; /* r24 */ - *stk-- = 0; /* r23 */ - *stk-- = 0; /* r22 */ - *stk-- = 0; /* r21 */ - *stk-- = 0; /* r20 */ - *stk-- = 0; /* r19 */ - *stk-- = 0; /* r18 */ - *stk-- = 0; /* r17 */ - *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ - *stk-- = (unsigned long)tentry; /* r14 = entry address*/ - *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ - *stk-- = 0; /* r12 */ - *stk-- = 0; /* r11 */ - *stk-- = 0; /* r10 */ - *stk-- = 0; /* r09 */ - *stk-- = 0; /* r08 */ - *stk-- = 0; /* r07 */ - *stk-- = 0; /* r06 */ - *stk-- = (unsigned long) parameter; /* r05 */ - *stk-- = 0; /* r04 */ - *stk-- = 0; /* r03 */ - *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ - *stk = 2; /* enable interrupt */ - return (rt_uint8_t *)stk; + stk = (unsigned long *)stack_addr; + stk--; + stk--; + *stk-- = 0; /* r31 */ + *stk-- = 0; /* r30 */ + *stk-- = 0; /* r29 */ + *stk-- = 0; /* r28 */ + *stk-- = 0; /* r27 */ + *stk-- = 0; /* r26 */ + *stk-- = 0; /* r25 */ + *stk-- = 0; /* r24 */ + *stk-- = 0; /* r23 */ + *stk-- = 0; /* r22 */ + *stk-- = 0; /* r21 */ + *stk-- = 0; /* r20 */ + *stk-- = 0; /* r19 */ + *stk-- = 0; /* r18 */ + *stk-- = 0; /* r17 */ + *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ + *stk-- = (unsigned long)tentry; /* r14 = entry address*/ + *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ + *stk-- = 0; /* r12 */ + *stk-- = 0; /* r11 */ + *stk-- = 0; /* r10 */ + *stk-- = 0; /* r09 */ + *stk-- = 0; /* r08 */ + *stk-- = 0; /* r07 */ + *stk-- = 0; /* r06 */ + *stk-- = (unsigned long) parameter; /* r05 */ + *stk-- = 0; /* r04 */ + *stk-- = 0; /* r03 */ + *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ + *stk = 2; /* enable interrupt */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c index 3b3f98d105..bcfb3cc492 100755 --- a/libcpu/xilinx/microblaze/trap.c +++ b/libcpu/xilinx/microblaze/trap.c @@ -10,13 +10,13 @@ * Change Logs: * Date Author Notes * 2006-08-23 Bernard first version - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze * */ -#include <rtthread.h> -#include "xparameters.h" -#include "xintc.h" +#include <rtthread.h> +#include "xparameters.h" +#include "xintc.h" #include "xintc_i.h" #include "xintc_l.h" @@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -41,24 +41,24 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - for (index = 0; index < MAX_HANDLERS; index ++) - { - CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -67,8 +67,8 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - XIntc_Disable(&int_ctl,vector); + /* disable interrupt */ + XIntc_Disable(&int_ctl,vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - XIntc_Enable(&int_ctl,vector); + XIntc_Enable(&int_ctl,vector); } /** @@ -88,15 +88,15 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; - if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; + if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; + } } /*****************************************************************************/ @@ -117,7 +117,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha * calling an interrupt handler. * * -* @return None. +* @return None. * * @note * @@ -131,81 +131,81 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha void rt_hw_trap_irq(void ) { - u32 intr_status; - u32 intr_mask = 1; - int intr_number; - volatile u32 reg; /* used as bit bucket */ - XIntc_Config *cfg_ptr; + u32 intr_status; + u32 intr_mask = 1; + int intr_number; + volatile u32 reg; /* used as bit bucket */ + XIntc_Config *cfg_ptr; - /* Get the configuration data using the device ID */ - cfg_ptr = &XIntc_ConfigTable[0]; + /* Get the configuration data using the device ID */ + cfg_ptr = &XIntc_ConfigTable[0]; - /* Get the interrupts that are waiting to be serviced */ - intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); + /* Get the interrupts that are waiting to be serviced */ + intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); - /* Service each interrupt that is active and enabled by checking each - * bit in the register from LSB to MSB which corresponds to an interrupt - * intput signal - */ - for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) - { - if (intr_status & 1) - { - XIntc_VectorTableEntry *table_ptr; + /* Service each interrupt that is active and enabled by checking each + * bit in the register from LSB to MSB which corresponds to an interrupt + * intput signal + */ + for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) + { + if (intr_status & 1) + { + XIntc_VectorTableEntry *table_ptr; - /* If the interrupt has been setup to acknowledge it - * before servicing the interrupt, then ack it - */ - if (cfg_ptr->AckBeforeService & intr_mask) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * before servicing the interrupt, then ack it + */ + if (cfg_ptr->AckBeforeService & intr_mask) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* The interrupt is active and enabled, call the - * interrupt handler that was setup with the specified - * parameter - */ - table_ptr = &(cfg_ptr->HandlerTable[intr_number]); - table_ptr->Handler(table_ptr->CallBackRef); + /* The interrupt is active and enabled, call the + * interrupt handler that was setup with the specified + * parameter + */ + table_ptr = &(cfg_ptr->HandlerTable[intr_number]); + table_ptr->Handler(table_ptr->CallBackRef); - /* If the interrupt has been setup to acknowledge it - * after it has been serviced then ack it - */ - if ((cfg_ptr->AckBeforeService & intr_mask) == 0) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * after it has been serviced then ack it + */ + if ((cfg_ptr->AckBeforeService & intr_mask) == 0) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* - * Read the ISR again to handle architectures with posted write - * bus access issues. - */ - reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); + /* + * Read the ISR again to handle architectures with posted write + * bus access issues. + */ + reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); - /* - * If only the highest priority interrupt is to be - * serviced, exit loop and return after servicing - * the interrupt - */ - if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) - { - return; - } - } + /* + * If only the highest priority interrupt is to be + * serviced, exit loop and return after servicing + * the interrupt + */ + if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) + { + return; + } + } - /* Move to the next interrupt to check */ - intr_mask <<= 1; - intr_status >>= 1; + /* Move to the next interrupt to check */ + intr_mask <<= 1; + intr_status >>= 1; - /* If there are no other bits set indicating that all interrupts - * have been serviced, then exit the loop - */ - if (intr_status == 0) - { - break; - } - } + /* If there are no other bits set indicating that all interrupts + * have been serviced, then exit the loop + */ + if (intr_status == 0) + { + break; + } + } } |