diff options
| author | wdfk-prog <[email protected]> | 2026-08-29 10:24:53 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2026-09-01 09:39:10 +0800 |
| commit | ef413759d4f20435fa7d0471e9be7b867566cc59 (patch) | |
| tree | c043df9098d83c0c4bcdff32f8c53654a9da5b87 | |
| parent | 5a9d4d77e32c0665afe1c0950125f98be97e2a4e (diff) | |
fix[arm][cortex-m4]: clarify MPU permission expressions
| -rw-r--r-- | libcpu/arm/cortex-m4/mpu.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/libcpu/arm/cortex-m4/mpu.h b/libcpu/arm/cortex-m4/mpu.h index d2cfd1ac2f..e2ca85e6d1 100644 --- a/libcpu/arm/cortex-m4/mpu.h +++ b/libcpu/arm/cortex-m4/mpu.h @@ -22,17 +22,17 @@ * These are identical to Cortex-M7 because both cores implement the * ARMv7-M MPU with the same AP/XN bit layout in the RASR register. */ /* Privileged No Access, Unprivileged No Access */ -#define P_NA_U_NA ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_NA_U_NA (((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* Privileged Read Write, Unprivileged No Access */ -#define P_RW_U_NA ((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_RW_U_NA (((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* Privileged Read Write, Unprivileged Read Only */ -#define P_RW_U_RO ((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_RW_U_RO (((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* Privileged Read Write, Unprivileged Read Write */ -#define P_RW_U_RW ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_RW_U_RW (((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* Privileged Read Only, Unprivileged No Access */ -#define P_RO_U_NA ((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_RO_U_NA (((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* Privileged Read Only, Unprivileged Read Only */ -#define P_RO_U_RO ((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk) +#define P_RO_U_RO (((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | MPU_RASR_XN_Msk) /* MPU attributes for configuring code region permission */ /* Privileged Read Write Execute, Unprivileged Read Write Execute */ |