diff options
| author | Jasontek <[email protected]> | 2026-07-16 15:13:49 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-07-16 15:13:49 +0800 |
| commit | f42337ba03a7b39d089e561bf68f28378f93c46e (patch) | |
| tree | 27ab62e155adda5f680a18efbb708a9e4732716e | |
| parent | 2835e956e87195a25f83e57de54362bd8e537775 (diff) | |
[bsp/nxp]imxrt1180 nxp evk lpadc&hyperflash#11529
49 files changed, 14586 insertions, 72 deletions
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml index 8648a70a2c..3313131adb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.ci/attachconfig/ci.attachconfig.yml @@ -8,4 +8,18 @@ scons.args: &scons Peripheral.flash_fs: <<: *scons kconfig: - - CONFIG_BSP_USING_QSPI_FLASH_FS=y
\ No newline at end of file + - CONFIG_BSP_USING_QSPI_FLASH_FS=y +Peripheral.lpadc1_dma: + <<: *scons + kconfig: + - CONFIG_RT_USING_ADC=y + - CONFIG_BSP_USING_DMA=y + - CONFIG_BSP_USING_LPADC=y + - CONFIG_BSP_USING_LPADC1=y + - CONFIG_BSP_LPADC1_USING_DMA=y +Peripheral.lpadc1: + <<: *scons + kconfig: + - CONFIG_RT_USING_ADC=y + - CONFIG_BSP_USING_LPADC=y + - CONFIG_BSP_USING_LPADC1=y
\ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config index af50c62b1e..9a55fe3218 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -248,7 +248,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set +CONFIG_RT_USING_ADC=y # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -269,8 +269,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set -# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -584,6 +586,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -730,6 +734,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -813,7 +819,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -878,9 +898,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -906,6 +924,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers # end of HAL & SDK Drivers # @@ -1086,6 +1110,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set @@ -1441,6 +1466,9 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_LPADC=y +CONFIG_BSP_USING_LPADC1=y +CONFIG_BSP_LPADC1_USING_DMA=y # CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig index c149a795c1..f3ca407aa7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -26,6 +26,25 @@ menu "On-chip Peripheral Drivers" bool "Enable DMA" default n + menuconfig BSP_USING_LPADC + bool "Enable ADC" + select RT_USING_ADC + default n + + if BSP_USING_LPADC + + config BSP_USING_LPADC1 + bool "Enable LPADC1" + default n + + config BSP_LPADC1_USING_DMA + bool "Enable LPADC1 DMA" + depends on BSP_USING_LPADC1 + depends on BSP_USING_DMA + default n + + endif + config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex new file mode 100644 index 0000000000..fee765231f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex @@ -0,0 +1,9092 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1180-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="f5ef75b4-32d7-412b-bc8b-eec904787d52" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1189xxxxx</processor> + <package>MIMXRT1189CVM8C</package> + <board>MIMXRT1180-EVK</board> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33"> + <core name="Cortex-M33" id="cm33" description=""/> + <core name="Cortex-M7F" id="cm7" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>26.03.10</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description></description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="ADC1" description="Peripheral ADC1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.rgpio" description="Pins initialization requires the RGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TXD" pin_num="B1" pin_signal="GPIO_AON_08"/> + <pin peripheral="LPUART1" signal="RXD" pin_num="A5" pin_signal="GPIO_AON_09"/> + <pin peripheral="RGPIO4" signal="gpio_io, 27" pin_num="M16" pin_signal="GPIO_AD_27"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="drive_strength" value="Normal"/> + </pin_features> + </pin> + <pin peripheral="ADC1" signal="A, 1_7" pin_num="R13" pin_signal="GPIO_AD_02"/> + <pin peripheral="ADC1" signal="B, 1_5" pin_num="T17" pin_signal="GPIO_AD_07"/> + <pin peripheral="ADC1" signal="A, 1_4" pin_num="T14" pin_signal="GPIO_AD_08"/> + <pin peripheral="ADC1" signal="B, 1_7" pin_num="R15" pin_signal="GPIO_AD_03"/> + <pin peripheral="ADC1" signal="A, 1_6" pin_num="P15" pin_signal="GPIO_AD_04"/> + <pin peripheral="ADC1" signal="B, 1_6" pin_num="P13" pin_signal="GPIO_AD_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="20.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>26.03.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ECAT.ecat_pt0_tx_clk" description="'ECAT_PORT0_REF_CLK' (Pins tool id: ECAT.ecat_pt0_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ECAT.ecat_pt1_tx_clk" description="'ECAT_PORT1_REF_CLK' (Pins tool id: ECAT.ecat_pt1_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ETH.eth_tx_clk" description="'NETC_PORT0_REF_CLK' (Pins tool id: ETH.eth_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ETH.eth_tx_clk" description="'NETC_PORT1_REF_CLK' (Pins tool id: ETH.eth_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ETH.eth_tx_clk" description="'NETC_PORT2_REF_CLK' (Pins tool id: ETH.eth_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ETH.eth_tx_clk" description="'NETC_PORT3_REF_CLK' (Pins tool id: ETH.eth_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ETH.eth_tx_clk" description="'NETC_PORT4_REF_CLK' (Pins tool id: ETH.eth_tx_clk, Clocks tool id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ENETC.enetc_clk_in" description="'TMR_1588_REF_CLK' (Pins tool id: ENETC.enetc_clk_in, Clocks tool id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT_PIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.misc" description="Clocks initialization requires the MISC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.misc" description="Clocks initialization requires the MISC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.ele_base_api" description="Clocks initialization requires the ELE_BASE_API Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.ele_base_api" description="Clocks initialization requires the ELE_BASE_API Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq" value="100 kHz" locked="false" enabled="false"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq" value="200 kHz" locked="false" enabled="false"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq" value="300 kHz" locked="false" enabled="false"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq" value="400 kHz" locked="false" enabled="false"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq" value="2 MHz" locked="false" enabled="false"/> + <clock_source id="BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq" value="50 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="ACMP_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="ADC1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="ADC2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="ARM_PLL_CLK.outFreq" value="792 MHz" locked="false" accuracy=""/> + <clock_output id="ASRC_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="BUS_AON_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="BUS_WAKEUP_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="CAN1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CAN2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CAN3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CCM_CKO1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CCM_CKO2_CLK_ROOT.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="ECAT_CLK_ROOT.outFreq" value="100 MHz" locked="false" accuracy=""/> + <clock_output id="ECAT_PORT0_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="ECAT_PORT1_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="EDGELOCK_CLK_ROOT.outFreq" value="200 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_REFCLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="120 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI1_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_SLV_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="I3C1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="I3C2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0102_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0304_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0506_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPIT3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0102_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0304_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0506_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0102_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0304_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0506_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0708_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0910_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART1112_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="M33_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="M33_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/> + <clock_output id="M7_CLK_ROOT.outFreq" value="792 MHz" locked="false" accuracy=""/> + <clock_output id="M7_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/> + <clock_output id="MAC0_CLK_ROOT.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="MAC1_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="MAC2_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="MAC3_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="MAC4_CLK_ROOT.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="MIC_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_PORT0_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_PORT1_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_PORT2_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_PORT3_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_PORT4_REF_CLK.outFreq" value="50 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_32K.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="OSC_RC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_RC_400M.outFreq" value="400 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="200 MHz" locked="false" accuracy=""/> + <clock_output id="SWO_TRACE_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL1_CLK.outFreq" value="1 GHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL1_DIV2_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL1_DIV5_CLK.outFreq" value="200 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_CLK.outFreq" value="528 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD0_CLK.outFreq" value="352 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD1_CLK.outFreq" value="594 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD2_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD3_CLK.outFreq" value="297 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_DIV2_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD0_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD1_CLK.outFreq" value="2880/11 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD2_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="TMR_1588_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="TMR_1588_REF_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="TPM2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM4_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM5_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM6_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="396 MHz" locked="false" accuracy=""/> + <clock_output id="WAKEUP_AXI_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="AONDomainVoltage" value="OD" locked="false"/> + <setting id="CoreClockRootsInitializationConfig" value="selectedCore" locked="false"/> + <setting id="SOCDomainVoltage" value="OD" locked="false"/> + <setting id="ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG" value="Low" locked="false"/> + <setting id="ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL.ARM_PLL_POST_DIV.scale" value="2" locked="true"/> + <setting id="ANADIG_PLL.ARM_PLL_PREDIV.scale" value="1" locked="true"/> + <setting id="ANADIG_PLL.ARM_PLL_VDIV.scale" value="132" locked="true"/> + <setting id="ANADIG_PLL.PLL_AUDIO_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2.denom" value="268435455" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL2.div" value="22" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2.num" value="0" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2_SS_DIV.scale" value="268435455" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale" value="22" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale" value="33" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale" value="18" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale" value="22" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale" value="18" locked="false"/> + <setting id="ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG" value="Disabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG" value="Enabled" locked="false"/> + <setting id="CCM.CLOCK_ROOT0.DIV.scale" value="1" locked="true"/> + <setting id="CCM.CLOCK_ROOT0.MUX.sel" value="ANADIG_PLL.ARM_PLL_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT1.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT1.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT10.DIV.scale" value="5" locked="true"/> + <setting id="CCM.CLOCK_ROOT10.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT11.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT11.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT12.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT12.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT13.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT13.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT14.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT14.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT15.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT15.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT16.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT16.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT17.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT17.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT18.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT18.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT19.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT2.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT2.MUX.sel" value="ANADIG_OSC.OSC_RC_400M" locked="false"/> + <setting id="CCM.CLOCK_ROOT20.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT21.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT21.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT22.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT22.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT23.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT23.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT24.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT24.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT25.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT25.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT26.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT26.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT27.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT27.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT28.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT28.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT29.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT29.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT3.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT3.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT30.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT30.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT31.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT31.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT32.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT32.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT33.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT33.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT34.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT34.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT35.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT35.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT36.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT36.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD1_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT37.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT37.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD1_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT38.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT38.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD1_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT39.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT39.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT4.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT4.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT40.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT40.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT41.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT41.MUX.sel" value="ANADIG_PLL.SYS_PLL2_PFD2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT42.MUX.sel" value="ANADIG_PLL.SYS_PLL2_PFD2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT43.DIV.scale" value="5" locked="true"/> + <setting id="CCM.CLOCK_ROOT43.MUX.sel" value="ANADIG_PLL.SYS_PLL1_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT44.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT44.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT45.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT45.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT46.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT46.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT47.DIV.scale" value="5" locked="true"/> + <setting id="CCM.CLOCK_ROOT47.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT48.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT48.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT49.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT49.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT5.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT5.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT50.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT50.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT51.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT51.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT52.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT52.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT53.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT53.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT54.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT54.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT55.DIV.scale" value="10" locked="true"/> + <setting id="CCM.CLOCK_ROOT55.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT6.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT6.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT65.DIV.scale" value="12" locked="true"/> + <setting id="CCM.CLOCK_ROOT65.MUX.sel" value="ANADIG_PLL.PLL_AUDIO_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT66.DIV.scale" value="12" locked="true"/> + <setting id="CCM.CLOCK_ROOT66.MUX.sel" value="ANADIG_PLL.PLL_AUDIO_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT67.DIV.scale" value="12" locked="true"/> + <setting id="CCM.CLOCK_ROOT67.MUX.sel" value="ANADIG_PLL.PLL_AUDIO_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT68.DIV.scale" value="12" locked="true"/> + <setting id="CCM.CLOCK_ROOT68.MUX.sel" value="ANADIG_PLL.PLL_AUDIO_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT69.DIV.scale" value="12" locked="true"/> + <setting id="CCM.CLOCK_ROOT69.MUX.sel" value="ANADIG_PLL.PLL_AUDIO_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT7.DIV.scale" value="240" locked="true"/> + <setting id="CCM.CLOCK_ROOT7.MUX.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="CCM.CLOCK_ROOT70.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT70.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT71.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT71.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT72.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT72.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT73.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT73.MUX.sel" value="ANADIG_PLL.SYS_PLL1_DIV5_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT8.DIV.scale" value="240" locked="true"/> + <setting id="CCM.CLOCK_ROOT8.MUX.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="CCM.CLOCK_ROOT9.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT9.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>N/A</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="工具链/IDE工程中未找到LPUART Driver。工程不会被编译！" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="工具链/IDE工程不支持LPUART Driver版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.11.0</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.rgpio" description="工具链/IDE工程中未找到RGPIO Driver。工程不会被编译！" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.rgpio" description="工具链/IDE工程不支持RGPIO Driver版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals"> + <feature name="version" evaluation="greaterOrEqual"> + <data type="Version" maxValue="2.2.9">2.1.0</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpadc" description="工具链/IDE工程中未找到LPADC Driver。工程不会被编译！" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpadc" description="工具链/IDE工程不支持LPADC Driver版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals"> + <feature name="version" evaluation="greaterOrEqual"> + <data type="Version" maxValue="2.9.9">2.8.1</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.edma4" description="工具链/IDE工程中未找到EDMA Driver。工程不会被编译！" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.edma4" description="工具链/IDE工程不支持EDMA Driver版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals"> + <feature name="version" evaluation="greaterOrEqual"> + <data type="Version" maxValue="2.10.99">2.9.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Pins" description="外围设备工具需要 Pins 工具，但它已被禁用。" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="外围设备工具需要 Clocks 工具，但它已被禁用。" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>26.03.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="e05a8704-a0aa-436e-89f3-59a6570dd2ff" called_from_default_init="true" id_prefix="" core="cm33"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="LPUART0102_CLK_ROOT" description="LPUART0102 root clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="ClockOutput" resourceId="ADC1_CLK_ROOT" description="ADC1 root clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ADC1.adc_se.1A" description="Signal channel 1A is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ADC1.adc_se.1B" description="Signal channel 1B is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="CM33_NVIC" uuid="c8e1acc8-1046-45d3-bac2-6b81b016b153" type="nvic" type_id="nvic" mode="general" peripheral="CM33_NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"> + <struct name="0"/> + </array> + <array name="interrupts"/> + </config_set> + </instance> + <instance name="LPUART1" uuid="4422a7a9-2880-4c74-aa20-6bae3ad3c1c6" type="lpuart" type_id="lpuart_2.11.0" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="txRtsPolarity" value="kLPUART_RtsPolarityLow"/> + <setting name="rtsWatermark" value="0"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + <setting name="inverseTxd" value="false"/> + </struct> + </config_set> + </instance> + <instance name="RGPIO4" uuid="62e079ad-d053-4886-b2f0-e633a526c432" type="rgpio" type_id="rgpio_2.1.0" mode="GPIO" peripheral="RGPIO4" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="fsl_gpio"> + <array name="interrupts"> + <struct name="0"> + <setting name="enable_irq" value="false"/> + <struct name="gpio_interrupt"> + <setting name="IRQn" value="GPIO4_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="ADC1" uuid="1d0878d1-2537-450e-ad60-e0188d99682c" type="lpadc" type_id="lpadc_2.8.1" mode="LPADC" peripheral="ADC1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="fsl_lpadc"> + <struct name="lpadcConfig"> + <setting name="clockSource" value="AsynchronousFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="enableJustifiedLeft" value="false"/> + <setting name="enableInDozeMode" value="true"/> + <setting name="conversionAverageMode" value="kLPADC_ConversionAverage2"/> + <setting name="offsetCalibration" value="yes"/> + <setting name="autoCalibrate" value="true"/> + <setting name="enableAnalogPreliminary" value="false"/> + <setting name="powerUpDelay" value="0x80"/> + <setting name="referenceVoltageSource" value="kLPADC_ReferenceVoltageAlt2"/> + <setting name="triggerPriorityPolicy" value="kLPADC_ConvPreemptImmediatelyNotAutoResumed"/> + <setting name="enableConvPause" value="false"/> + <setting name="convPauseDelay" value="0"/> + <setting name="FIFO0Watermark" value="0"/> + <setting name="FIFO1Watermark" value="0"/> + <setting name="FIFO0WatermarkDMA" value="true"/> + <setting name="FIFO1WatermarkDMA" value="false"/> + </struct> + <array name="lpadcConvCommandConfig"> + <struct name="0"> + <setting name="user_commandId" value="GRPA"/> + <setting name="commandId" value="1"/> + <setting name="chainedNextCommandNumber" value="2"/> + <setting name="sampleChannelMode" value="kLPADC_SampleChannelSingleEndSideA"/> + <setting name="sampleScaleMode" value="kLPADC_SampleFullScale"/> + <setting name="channelNumber" value="A.1_4"/> + <setting name="enableChannelB_b" value="false"/> + <setting name="channelBScaleMode_e" value="kLPADC_SampleFullScale"/> + <setting name="channelBNumber" value="B.1_0"/> + <setting name="enableAutoChannelIncrement" value="true"/> + <setting name="loopCount" value="3"/> + <setting name="hardwareAverageMode" value="kLPADC_HardwareAverageCount1"/> + <setting name="sampleTimeMode" value="kLPADC_SampleTimeADCK3"/> + <setting name="hardwareCompareMode" value="kLPADC_HardwareCompareDisabled"/> + <setting name="hardwareCompareValueHigh" value="0"/> + <setting name="hardwareCompareValueLow" value="0"/> + <setting name="conversionResoultuionMode" value="kLPADC_ConversionResolutionHigh"/> + <setting name="enableWaitTrigger" value="true"/> + </struct> + <struct name="1"> + <setting name="user_commandId" value="GRPB"/> + <setting name="commandId" value="2"/> + <setting name="chainedNextCommandNumber" value="0"/> + <setting name="sampleChannelMode" value="kLPADC_SampleChannelSingleEndSideB"/> + <setting name="sampleScaleMode" value="kLPADC_SampleFullScale"/> + <setting name="channelNumber" value="B.1_5"/> + <setting name="enableChannelB_b" value="false"/> + <setting name="channelBScaleMode_e" value="kLPADC_SampleFullScale"/> + <setting name="channelBNumber" value="B.1_0"/> + <setting name="enableAutoChannelIncrement" value="true"/> + <setting name="loopCount" value="2"/> + <setting name="hardwareAverageMode" value="kLPADC_HardwareAverageCount1"/> + <setting name="sampleTimeMode" value="kLPADC_SampleTimeADCK3"/> + <setting name="hardwareCompareMode" value="kLPADC_HardwareCompareDisabled"/> + <setting name="hardwareCompareValueHigh" value="0"/> + <setting name="hardwareCompareValueLow" value="0"/> + <setting name="conversionResoultuionMode" value="kLPADC_ConversionResolutionHigh"/> + <setting name="enableWaitTrigger" value="false"/> + </struct> + </array> + <array name="lpadcConvTriggerConfig"> + <struct name="0"> + <setting name="user_triggerId" value="TRIG"/> + <setting name="triggerId" value="0"/> + <setting name="targetCommandId" value="1"/> + <setting name="delayPower" value="0"/> + <setting name="priority" value="false"/> + <setting name="channelAFIFOSelect" value="0"/> + <setting name="channelBFIFOSelect" value="0"/> + <setting name="enableHardwareTrigger" value="false"/> + </struct> + </array> + <struct name="IRQ_cfg"> + <set name="interrupt_type"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="adc_interrupt"> + <setting name="IRQn" value="ADC1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="true"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="DMA4" uuid="e77f5248-6191-4aa7-85d3-5e9a00d14329" type="edma4" type_id="edma4_2.9.0" mode="general" peripheral="DMA4" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="fsl_edma"> + <array name="dmamux_devices"/> + <struct name="common_settings"> + <struct name="vars"/> + <setting name="enableHaltOnError" value="true"/> + <setting name="enableDebugMode" value="false"/> + <setting name="enableRoundRobinArbitration" value="fixedPriority"/> + <setting name="enableGlobalChannelLink" value="true"/> + <setting name="enableMasterIdReplication" value="false"/> + </struct> + <array name="dma_table"> + <struct name="0"/> + </array> + <array name="edma_channels"> + <struct name="0"> + <setting name="apiMode" value="trans"/> + <struct name="edma_channel"> + <setting name="channel_prefix_id" value="CH0"/> + <setting name="uid" value="1780195171347"/> + <setting name="eDMAn" value="0"/> + <setting name="eDMA_source" value="kDma4RequestMuxADC1Request0"/> + <setting name="init_channel_priority" value="false"/> + <struct name="edma_channel_Preemption"> + <setting name="enableChannelPreemption" value="false"/> + <setting name="enablePreemptAbility" value="false"/> + <setting name="channelPriority" value="0"/> + </struct> + <setting name="initMemoryAttributes" value="false"/> + <struct name="memAttributes"> + <set name="writeCache"> + <selected> + <id>buffer</id> + </selected> + </set> + <set name="readCache"> + <selected> + <id>buffer</id> + </selected> + </set> + </struct> + <setting name="setChannelSwapSize" value="noInit"/> + <setting name="signExtension" value="noInit"/> + <setting name="setChannelAccessType" value="noInit"/> + <setting name="masterIdReplicationEnable" value="noInit"/> + <setting name="securityLevel" value="noInit"/> + <setting name="protectionLevel" value="noInit"/> + <setting name="enable_custom_name" value="false"/> + </struct> + <setting name="resetChannel" value="false"/> + <setting name="enableChannelRequest" value="true"/> + <setting name="enableAsyncRequest" value="false"/> + <setting name="enableAutoStop" value="false"/> + <setting name="tcd_pool_enable" value="false"/> + <struct name="tcd_settings"> + <setting name="tcd_size" value="1"/> + <setting name="tcd_memory_ptr_id" value="default"/> + </struct> + <array name="transfer_config"> + <struct name="0"> + <setting name="uid" value="1780716022754"/> + <setting name="tcdID" value="CH0_TRANSFER0"/> + <setting name="ssize" value="kEDMA_TransferSize4Bytes"/> + <setting name="saddr_expr" value="&ADC1->RESFIFO[0]"/> + <setting name="saddr_def" value=""/> + <setting name="soff" value="0"/> + <setting name="soff_def" value=""/> + <setting name="smod" value="kEDMA_ModuloDisable"/> + <setting name="dsize" value="kEDMA_TransferSize4Bytes"/> + <setting name="daddr_expr" value="&adc_result[0]"/> + <setting name="daddr_def" value="AT_NONCACHEABLE_SECTION_ALIGN_INIT(extern uint32_t adc_result[], sizeof(uint32_t));"/> + <setting name="doff" value="sizeof(uint32_t)"/> + <setting name="doff_def" value=""/> + <setting name="dmod" value="kEDMA_ModuloDisable"/> + <setting name="nbytes" value="4"/> + <struct name="MLconfig"> + <setting name="offsetType" value="disabled"/> + <setting name="mloff" value="0"/> + </struct> + <setting name="enableChannelLinkMinor" value="false"/> + <setting name="linkedChannelMinor" value="1780195171347"/> + <setting name="citer" value="7"/> + <setting name="slast" value="0"/> + <setting name="dlast" value="-28"/> + <setting name="enableChannelLinkMajor" value="false"/> + <setting name="linkedChannelMajor" value="1780195171347"/> + <setting name="submitTransfer" value="true"/> + </struct> + </array> + <setting name="loopTransfer" value="false"/> + <setting name="no_init_uid" value="1780195171376"/> + <setting name="init_callback" value="true"/> + <setting name="callback_function" value="DMA_Callback"/> + <setting name="callback_user_data" value=""/> + <set name="channel_enabled_interrupts"> + <selected/> + </set> + <struct name="interrupt_channel"> + <setting name="IRQn" value="DMA4_CH0_CH1_CH32_CH33_IRQn"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + </struct> + </struct> + </array> + <struct name="errInterruptConfig"> + <setting name="enableErrInterrupt" value="false"/> + <struct name="errorInterrupt"> + <setting name="IRQn" value="DMA4_ERROR_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="3116fdbe-0295-4b57-ad42-022f9122c966" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="uart_cmsis_common" uuid="d0c12268-f367-447c-a66c-3e03f1cd1127" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="msg" uuid="8e008aca-d3e8-40c6-b889-8d6339030b41" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="fcde5aa7-2918-464f-b71e-31ed2eb243c1" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="6c250459-db04-46ae-93bf-a2743f8fb8a4" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="5826f4a1-e11a-4dbc-a573-82f543d3a662" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="generic_can" uuid="fc02c632-ea4e-477c-8403-77fa8189b39a" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + </components> + </periphs> + <tee name="TEE" version="12.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>26.03.10</processor_version> + <tool_options> + <option id="_legacy_source_names_" value="no"/> + <option id="_resilient_code_reg_writes_" value="no"/> + <option id="_release_ele_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTEE" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <root> + <ports> + <port id="RGPIO1"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_security id="22" security="s_priv"/> + <pin_security id="23" security="s_priv"/> + <pin_security id="24" security="s_priv"/> + <pin_security id="25" security="s_priv"/> + <pin_security id="26" security="s_priv"/> + <pin_security id="27" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + <port id="RGPIO2"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_security id="22" security="s_priv"/> + <pin_security id="23" security="s_priv"/> + <pin_security id="24" security="s_priv"/> + <pin_security id="25" security="s_priv"/> + <pin_security id="26" security="s_priv"/> + <pin_security id="27" security="s_priv"/> + <pin_security id="28" security="s_priv"/> + <pin_security id="29" security="s_priv"/> + <pin_security id="30" security="s_priv"/> + <pin_security id="31" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + <port id="RGPIO3"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_security id="22" security="s_priv"/> + <pin_security id="23" security="s_priv"/> + <pin_security id="24" security="s_priv"/> + <pin_security id="25" security="s_priv"/> + <pin_security id="26" security="s_priv"/> + <pin_security id="27" security="s_priv"/> + <pin_security id="28" security="s_priv"/> + <pin_security id="29" security="s_priv"/> + <pin_security id="30" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + <port id="RGPIO4"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_security id="22" security="s_priv"/> + <pin_security id="23" security="s_priv"/> + <pin_security id="24" security="s_priv"/> + <pin_security id="25" security="s_priv"/> + <pin_security id="26" security="s_priv"/> + <pin_security id="27" security="s_priv"/> + <pin_security id="28" security="s_priv"/> + <pin_security id="29" security="s_priv"/> + <pin_security id="30" security="s_priv"/> + <pin_security id="31" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + <port id="RGPIO5"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + <port id="RGPIO6"> + <pin_security id="00" security="s_priv"/> + <pin_security id="01" security="s_priv"/> + <pin_security id="02" security="s_priv"/> + <pin_security id="03" security="s_priv"/> + <pin_security id="04" security="s_priv"/> + <pin_security id="05" security="s_priv"/> + <pin_security id="06" security="s_priv"/> + <pin_security id="07" security="s_priv"/> + <pin_security id="08" security="s_priv"/> + <pin_security id="09" security="s_priv"/> + <pin_security id="10" security="s_priv"/> + <pin_security id="11" security="s_priv"/> + <pin_security id="12" security="s_priv"/> + <pin_security id="13" security="s_priv"/> + <pin_security id="14" security="s_priv"/> + <pin_security id="15" security="s_priv"/> + <pin_security id="16" security="s_priv"/> + <pin_security id="17" security="s_priv"/> + <pin_security id="18" security="s_priv"/> + <pin_security id="19" security="s_priv"/> + <pin_security id="20" security="s_priv"/> + <pin_security id="21" security="s_priv"/> + <pin_security id="22" security="s_priv"/> + <pin_security id="23" security="s_priv"/> + <pin_security id="24" security="s_priv"/> + <pin_security id="25" security="s_priv"/> + <pin_security id="26" security="s_priv"/> + <pin_security id="27" security="s_priv"/> + <pin_interrupt_security id="00" security="s_priv"/> + <pin_interrupt_security id="01" security="s_priv"/> + </port> + </ports> + <trdc id="0"> + <masters> + <master id="cm33"> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + </master> + <master id="edma1"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + </masters> + <mbcs> + <mbc checker_id="MBC_A0" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <slaves> + <slave id="GPT1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="OTFAD2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CAN3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART12"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART7"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DCDC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="AXBS"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BLK_CTRL_S_AONMIX"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ANADIG_TEMPSENSOR"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPC_CPU_CTRL"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SRC_GENERAL_REG"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CCM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BBNSM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CP_CM33_IMX9RTC__CM33_TCM_MCM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BLK_CTRL_BBSMMIX"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="XCACHE_PC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="M33_PSF1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="M33_PCF1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="IOMUXC_AON"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SAI1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CAN1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="I3C1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPTMR1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPIT1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="RTWDOG2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="RTWDOG1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TSTMR1_TSTMRA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SYS_CTR_READ"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SYS_CTR_COMPARE"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SYS_CTR_CONTROL"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SEMA1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MU1_MUB"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MU1_MUA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BLK_CTRL_NS_AONMIX"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ROM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BASIC_TROUT1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MTR_DCA1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MTR_MSTR1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="IPC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC_MC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC1_ALIAS"> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS0"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS7"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS8"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS9"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS10"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS11"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS12"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS13"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS14"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS15"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS16"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS17"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS18"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS19"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS20"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS21"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS22"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS23"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS24"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS25"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS26"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS27"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS28"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS29"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS30"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_TEE_ALIAS31"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA3_MP"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPIO1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="EdgeLock"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="524288"/> + </slave> + </slaves> + </mbc> + <mbc checker_id="MBC_A1" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <slaves> + <slave id="SRAM_ITC_cm33"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="131072"/> + </slave> + <slave id="SRAM_DTC_cm33"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="131072"/> + </slave> + </slaves> + </mbc> + </mbcs> + <mrcs> + <mrc checker_id="MRC_A0" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="131072" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_A1" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="67108864" size="67108864" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + </domains> + </mrc> + </mrcs> + </trdc> + <trdc id="1"> + <masters> + <master id="cm7_ahb"> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + </master> + <master id="cm7_axi"> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + </master> + <master id="ahb_ap_sys"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="coresight_etr"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="edma2"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="netc_ace_lite"> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + <domain_assignment secure="ns" enabled="false" locked="false" domain_id="0" domain_input="mda"/> + </master> + </masters> + <mbcs> + <mbc checker_id="MBC_W0" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <slaves> + <slave id="AOI4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="AOI3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EWM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="AOI2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="AOI1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="XBAR3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="XBAR2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="XBAR1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EQDC4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EQDC3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EQDC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EQDC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR8"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR7"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TMR1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="PWM4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="PWM3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="PWM2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="PWM1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ADC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="FLEXSPI1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="FLEXIO2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="FLEXIO1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CAN2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="I3C2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TPM3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPTMR2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPIT2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="RTWDOG5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="RTWDOG4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="RTWDOG3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TSTMR2_TSTMRA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SEMA2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MU2_MUB"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MU2_MUA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BLK_CTRL_WAKEUPMIX"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BASIC_TROUT2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MTR_DCA2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC_MC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC2_ALIAS"> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS0"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS7"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS8"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS9"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS10"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS11"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS12"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS13"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS14"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS15"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS16"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS17"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS18"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS19"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS20"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS21"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS22"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS23"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS24"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS25"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS26"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS27"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS28"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS29"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS30"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS31"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS32"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS33"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS34"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS35"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS36"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS37"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS38"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS39"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS40"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS41"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS42"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS43"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS44"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS45"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS46"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS47"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS48"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS49"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS50"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS51"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS52"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS53"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS54"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS55"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS56"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS57"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS58"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS59"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS60"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS61"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS62"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_TEE_ALIAS63"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DMA4_MP"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPIO2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="GPIO3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="GPIO4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="GPIO5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="GPIO6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="DebugDAP"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="17825792"/> + </slave> + </slaves> + </mbc> + <mbc checker_id="MBC_W1" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <slaves> + <slave id="PROCESS_MONITOR"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPT2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="IEE"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="VREF"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="DAC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ADC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CMP4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CMP3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CMP2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="CMP1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART8"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART11"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART10"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPUART9"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPSPI5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPI2C5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPTMR3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="LPIT3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USBPHY2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USBPHY1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USB_OTG2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USB_OTG1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SINC3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SINC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SINC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="PDM"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SAI4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SAI3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SAI2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SPDIF"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ECAT"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="IOMUXC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="KPP"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="ASRC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MECC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MECC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SEMC"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="FLEXSPI_SLV"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR5"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MSGINTR1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USDHC2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USDHC1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="SFA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TCU6"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="USB_PL301"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MTR_DCA4"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="BASIC_TROUT3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="MTR_DCA3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPV_MEGA2"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="GPV_MEGA1"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC_MC3"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="TRDC3_ALIAS"> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + <domain security="ns" template="NO_ACCESS"/> + </slave> + <slave id="BLK_CTRL_MEGA"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + </slave> + <slave id="EdgeLock_ISP_AP"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="65536"/> + </slave> + <slave id="NIC_MAIN_GPV"> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <domain security="s" template="NO_ACCESS"/> + <base_region start="0" size="1048576"/> + </slave> + </slaves> + </mbc> + </mbcs> + <mrcs> + <mrc checker_id="MRC_W1" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="671088640" size="134217728" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_W2" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + <domain> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="0" size="4194304" security="s" template="NO_ACCESS" enabled="false" index="7"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_W3" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="541589504" size="524288" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_W4" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="542113792" size="262144" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_W5" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="2147483648" size="1610612736" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + </domains> + </mrc> + <mrc checker_id="MRC_W6" using_global_templates="false"> + <access_templates> + <template id="NO_ACCESS" name="No access"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + <domains> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + <domain> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="0"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="1"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="2"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="3"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="4"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="5"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="6"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="7"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="8"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="9"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="10"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="11"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="12"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="13"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="14"/> + <region start="1610612736" size="268435456" security="s" template="NO_ACCESS" enabled="false" index="15"/> + </domain> + </domains> + </mrc> + </mrcs> + </trdc> + <trdc id="2"> + <masters> + <master id="usdhc1"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="usdhc2"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="usb"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + <master id="flexspi_flr"> + <domain_assignment secure="ns" privileged="user" enabled="false" locked="false" domain_id="0" domain_bypass="false"/> + </master> + </masters> + <mbcs/> + <mrcs/> + </trdc> + </root> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="0"/> + <option id="CPACR_CP1" value="0"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="0"/> + <option id="CPACR_CP11" value="0"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="GPIO1_PCNS" value="no"/> + <option id="GPIO1_ICNS" value="no"/> + <option id="GPIO1_PCNP" value="no"/> + <option id="GPIO1_ICNP" value="no"/> + <option id="GPIO2_PCNS" value="no"/> + <option id="GPIO2_ICNS" value="no"/> + <option id="GPIO2_PCNP" value="no"/> + <option id="GPIO2_ICNP" value="no"/> + <option id="GPIO3_PCNS" value="no"/> + <option id="GPIO3_ICNS" value="no"/> + <option id="GPIO3_PCNP" value="no"/> + <option id="GPIO3_ICNP" value="no"/> + <option id="GPIO4_PCNS" value="no"/> + <option id="GPIO4_ICNS" value="no"/> + <option id="GPIO4_PCNP" value="no"/> + <option id="GPIO4_ICNP" value="no"/> + <option id="GPIO5_PCNS" value="no"/> + <option id="GPIO5_ICNS" value="no"/> + <option id="GPIO5_PCNP" value="no"/> + <option id="GPIO5_ICNP" value="no"/> + <option id="GPIO6_PCNS" value="no"/> + <option id="GPIO6_ICNS" value="no"/> + <option id="GPIO6_PCNP" value="no"/> + <option id="GPIO6_ICNP" value="no"/> + <option id="TRDC1_CR_GVLDM" value="yes"/> + <option id="TRDC1_CR_GVLDB" value="no"/> + <option id="TRDC1_CR_GVLDR" value="no"/> + <option id="TRDC1_IDAU_CR_VLD" value="no"/> + <option id="TRDC1_IDAU_CR_LKSAU" value="no"/> + <option id="TRDC1_IDAU_CR_LKNSMPU" value="no"/> + <option id="TRDC1_IDAU_CR_LKSMPU" value="no"/> + <option id="TRDC1_IDAU_CR_LKNSVTOR" value="no"/> + <option id="TRDC1_IDAU_CR_LKSVTAIRCR" value="no"/> + <option id="TRDC2_CR_GVLDM" value="yes"/> + <option id="TRDC2_CR_GVLDB" value="no"/> + <option id="TRDC2_CR_GVLDR" value="no"/> + <option id="TRDC2_IDAU_CR_VLD" value="no"/> + <option id="TRDC2_IDAU_CR_LKSAU" value="no"/> + <option id="TRDC2_IDAU_CR_LKNSMPU" value="no"/> + <option id="TRDC2_IDAU_CR_LKSMPU" value="no"/> + <option id="TRDC2_IDAU_CR_LKNSVTOR" value="no"/> + <option id="TRDC2_IDAU_CR_LKSVTAIRCR" value="no"/> + <option id="TRDC3_CR_GVLDM" value="yes"/> + <option id="TRDC3_CR_GVLDB" value="no"/> + <option id="TRDC3_CR_GVLDR" value="no"/> + <option id="TRDC3_IDAU_CR_VLD" value="no"/> + <option id="TRDC3_IDAU_CR_LKSAU" value="no"/> + <option id="TRDC3_IDAU_CR_LKNSMPU" value="no"/> + <option id="TRDC3_IDAU_CR_LKSMPU" value="no"/> + <option id="TRDC3_IDAU_CR_LKNSVTOR" value="no"/> + <option id="TRDC3_IDAU_CR_LKSVTAIRCR" value="no"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false" masters="cm33"> + <attributes> + <group index="0" id="0" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="1" id="1" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="2" id="2" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="3" id="3" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="4" id="4" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="5" id="5" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="6" id="6" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="7" id="7" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="8" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="9" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="10" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="11" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="12" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="13" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="14" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="15" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false" masters="cm33"> + <attributes> + <group index="0" id="0" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="1" id="1" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="2" id="2" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="3" id="3" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="4" id="4" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="5" id="5" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="6" id="6" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + <group index="7" id="7" memory_type="device" device="nGnRE"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + <region_properties id="outer" cacheable="false" write_back="false" read_allocation="false" write_allocation="false" transientness="false"/> + </regions_properties> + </group> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="8" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="9" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="10" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="11" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="12" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="13" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="14" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="15" executable="false" read_only="false" shareability="non_shareable" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" generate_code_for_disabled_regions="false" masters="cm7_ahb cm7_axi"> + <attributes> + <group index="0" id="0" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="1" id="1" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="2" id="2" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="3" id="3" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="4" id="4" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="5" id="5" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="6" id="6" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="7" id="7" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="8" id="8" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="9" id="9" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="10" id="10" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="11" id="11" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="12" id="12" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="13" id="13" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="14" id="14" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + <group index="15" id="15" memory_type="device"> + <regions_properties> + <region_properties id="inner" cacheable="false" write_back="false" write_allocation="false"/> + <region_properties id="outer" cacheable="false" write_back="false" write_allocation="false"/> + </regions_properties> + </group> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" shareability="non_shareable" attributes_index="0" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" shareability="non_shareable" attributes_index="1" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" shareability="non_shareable" attributes_index="2" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" shareability="non_shareable" attributes_index="3" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" shareability="non_shareable" attributes_index="4" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" shareability="non_shareable" attributes_index="5" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" shareability="non_shareable" attributes_index="6" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" shareability="non_shareable" attributes_index="7" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="8" executable="false" read_only="false" shareability="non_shareable" attributes_index="8" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="9" executable="false" read_only="false" shareability="non_shareable" attributes_index="9" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="10" executable="false" read_only="false" shareability="non_shareable" attributes_index="10" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="11" executable="false" read_only="false" shareability="non_shareable" attributes_index="11" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="12" executable="false" read_only="false" shareability="non_shareable" attributes_index="12" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="13" executable="false" read_only="false" shareability="non_shareable" attributes_index="13" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="14" executable="false" read_only="false" shareability="non_shareable" attributes_index="14" srd="0"/> + <region start="0" size="32" security="priv" enabled="false" index="15" executable="false" read_only="false" shareability="non_shareable" attributes_index="15" srd="0"/> + </regions> + </mpu> + </mpus> + <access_templates> + <template id="NO_ACCESS" name="No access" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="R_s" name="R for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s_priv" name="RW for S-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s" name="RW for S" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns_priv" name="RW for S, R for NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__R_ns" name="RW for S, R for NS" locked="true"> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="BLOCK" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="RW_s__RW_ns_priv" name="RW for S and NS-Priv" locked="true"> + <access read="BLOCK" write="BLOCK" execute="BLOCK" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="BLOCK" security_level="s_priv"/> + </template> + <template id="ALL" locked="true"> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="ns_priv"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_user"/> + <access read="ALLOW" write="ALLOW" execute="ALLOW" security_level="s_priv"/> + </template> + </access_templates> + </functional_group> + </tee> + </tools> +</configuration>
\ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c new file mode 100644 index 0000000000..edd739e507 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c @@ -0,0 +1,836 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v20.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 26.03.10 +board: MIMXRT1180-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz} +- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz} +- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} +- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK} +- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK} +- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +sources: +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz} +- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ + .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Init Sys Pll1. */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using SYS_PLL1_CLK */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using SYS_PLL1_DIV5_CLK */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h new file mode 100644 index 0000000000..c93b94e2bf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h @@ -0,0 +1,184 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config1.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config1.png Binary files differnew file mode 100644 index 0000000000..073647bfed --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config1.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config2.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config2.png Binary files differnew file mode 100644 index 0000000000..54d19c6c4c --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/RTT_Config2.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_adc test.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_adc test.png Binary files differnew file mode 100644 index 0000000000..2c5bf8d024 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_adc test.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_lpadc1_multich_test.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_lpadc1_multich_test.png Binary files differnew file mode 100644 index 0000000000..d02473bbb0 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/drv_lpadc1_multich_test.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0.png Binary files differnew file mode 100644 index 0000000000..5853e7d178 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0_transfer.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0_transfer.png Binary files differnew file mode 100644 index 0000000000..aacbc2cba0 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/edma4_ch0_transfer.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/imxrt1180_sdk_SConscript-change.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/imxrt1180_sdk_SConscript-change.png Binary files differnew file mode 100644 index 0000000000..07fac667ac --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/imxrt1180_sdk_SConscript-change.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPA_command.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPA_command.png Binary files differnew file mode 100644 index 0000000000..5c80ce3598 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPA_command.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPB_command.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPB_command.png Binary files differnew file mode 100644 index 0000000000..5a9125e66b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_GRPB_command.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_TRIG_config.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_TRIG_config.png Binary files differnew file mode 100644 index 0000000000..4bbc272898 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_TRIG_config.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_periph_config.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_periph_config.png Binary files differnew file mode 100644 index 0000000000..295df721d7 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_periph_config.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_pin_mux.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_pin_mux.png Binary files differnew file mode 100644 index 0000000000..dbae147bbe --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc1_pin_mux.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc_edma4_config.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc_edma4_config.png Binary files differnew file mode 100644 index 0000000000..634bf625c8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/figures/lpadc_edma4_config.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c new file mode 100644 index 0000000000..e15d4f9f14 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c @@ -0,0 +1,533 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 26.03.10 +board: MIMXRT1180-EVK +functionalGroups: +- name: BOARD_InitPeripherals + UUID: e05a8704-a0aa-436e-89f3-59a6570dd2ff + called_from_default_init: true + selectedCore: cm33 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +#ifdef BSP_LPADC1_USING_DMA +/*********************************************************************************************************************** + * DMA4 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DMA4' +- type: 'edma4' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'edma4_2.9.0' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'DMA4' +- config_sets: + - fsl_edma: + - dmamux_devices: [] + - common_settings: + - vars: [] + - enableHaltOnError: 'true' + - enableDebugMode: 'false' + - enableRoundRobinArbitration: 'fixedPriority' + - enableGlobalChannelLink: 'true' + - enableMasterIdReplication: 'false' + - dma_table: + - 0: [] + - edma_channels: + - 0: + - apiMode: 'trans' + - edma_channel: + - channel_prefix_id: 'CH0' + - uid: '1780195171347' + - eDMAn: '0' + - eDMA_source: 'kDma4RequestMuxADC1Request0' + - init_channel_priority: 'false' + - edma_channel_Preemption: + - enableChannelPreemption: 'false' + - enablePreemptAbility: 'false' + - channelPriority: '0' + - initMemoryAttributes: 'false' + - memAttributes: + - writeCache: 'buffer' + - readCache: 'buffer' + - setChannelSwapSize: 'noInit' + - signExtension: 'noInit' + - setChannelAccessType: 'noInit' + - masterIdReplicationEnable: 'noInit' + - securityLevel: 'noInit' + - protectionLevel: 'noInit' + - enable_custom_name: 'false' + - resetChannel: 'false' + - enableChannelRequest: 'true' + - enableAsyncRequest: 'false' + - enableAutoStop: 'false' + - tcd_pool_enable: 'false' + - tcd_settings: + - tcd_size: '1' + - tcd_memory_ptr_id: 'default' + - transfer_config: + - 0: + - uid: '1780716022754' + - tcdID: 'CH0_TRANSFER0' + - ssize: 'kEDMA_TransferSize4Bytes' + - saddr_expr: '&ADC1->RESFIFO[0]' + - saddr_def: '' + - soff: '0' + - soff_def: '' + - smod: 'kEDMA_ModuloDisable' + - dsize: 'kEDMA_TransferSize4Bytes' + - daddr_expr: '&adc_result[0]' + - daddr_def: 'AT_NONCACHEABLE_SECTION_ALIGN_INIT(extern uint32_t adc_result[], sizeof(uint32_t));' + - doff: 'sizeof(uint32_t)' + - doff_def: '' + - dmod: 'kEDMA_ModuloDisable' + - nbytes: '4' + - MLconfig: + - offsetType: 'disabled' + - mloff: '0' + - enableChannelLinkMinor: 'false' + - linkedChannelMinor: '1780195171347' + - citer: '7' + - slast: '0' + - dlast: '-28' + - enableChannelLinkMajor: 'false' + - linkedChannelMajor: '1780195171347' + - submitTransfer: 'true' + - loopTransfer: 'false' + - no_init_uid: '1780195171376' + - init_callback: 'true' + - callback_function: 'DMA_Callback' + - callback_user_data: '' + - channel_enabled_interrupts: '' + - interrupt_channel: + - IRQn: 'DMA4_CH0_CH1_CH32_CH33_IRQn' + - enable_priority: 'false' + - priority: '0' + - errInterruptConfig: + - enableErrInterrupt: 'false' + - errorInterrupt: + - IRQn: 'DMA4_ERROR_IRQn' + - enable_interrrupt: 'enabled' + - enable_priority: 'false' + - priority: '0' + - enable_custom_name: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +edma_config_t DMA4_config = { + .enableMasterIdReplication = false, + .enableGlobalChannelLink = true, + .enableHaltOnError = true, + .enableDebugMode = false, + .enableRoundRobinArbitration = false +}; +/* Tansactional transfer configurations */ +edma_transfer_config_t DMA4_CH0_Transfers_config[1]; +edma_handle_t DMA4_CH0_Handle; + +static void DMA4_init(void) +{ + status_t status; + (void)status; + + /* Channel CH0 initialization */ + /* Set the kDma4RequestMuxADC1Request0 request */ + EDMA_SetChannelMux(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL, DMA4_CH0_DMA_REQUEST); + /* Create the eDMA DMA4_CH0_Handle handle */ + EDMA_CreateHandle(&DMA4_CH0_Handle, DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL); + /* DMA callback initialization */ + EDMA_SetCallback(&DMA4_CH0_Handle, DMA_Callback, NULL); + /* DMA4 transfer CH0_TRANSFER0 configuration */ + EDMA_PrepareTransferConfig(&DMA4_CH0_TRANSFER0_CONFIG, (void *) &ADC1->RESFIFO[0], 1 << kEDMA_TransferSize4Bytes, 0, (void *) &adc_result[0], 1 << kEDMA_TransferSize4Bytes, sizeof(uint32_t), 4U, 28U); + DMA4_CH0_TRANSFER0_CONFIG.dstMajorLoopOffset = -28; + /* DMA4 transfer CH0_TRANSFER0 submit */ + status = EDMA_SubmitTransfer(&DMA4_CH0_Handle, &DMA4_CH0_TRANSFER0_CONFIG); + assert(status == kStatus_Success); + /* DMA4 hardware channel 0 request auto stop */ + EDMA_EnableAutoStopRequest(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL, false); + /* DMA4 channel 0 peripheral request */ + EDMA_EnableChannelRequest(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL); +} +#endif +/*********************************************************************************************************************** + * CM33_NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'CM33_NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'CM33_NVIC' +- config_sets: + - nvic: + - interrupt_table: + - 0: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void CM33_NVIC_init(void) +{ +} */ + +/*********************************************************************************************************************** + * LPUART1 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'LPUART1' +- type: 'lpuart' +- mode: 'polling' +- custom_name_enabled: 'false' +- type_id: 'lpuart_2.11.0' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'LPUART1' +- config_sets: + - lpuartConfig_t: + - lpuartConfig: + - clockSource: 'LpuartClock' + - lpuartSrcClkFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - parityMode: 'kLPUART_ParityDisabled' + - dataBitsCount: 'kLPUART_EightDataBits' + - isMsb: 'false' + - stopBitCount: 'kLPUART_OneStopBit' + - enableMatchAddress1: 'false' + - matchAddress1: '0' + - enableMatchAddress2: 'false' + - matchAddress2: '0' + - txFifoWatermark: '0' + - rxFifoWatermark: '1' + - enableRxRTS: 'false' + - enableTxRTS: 'false' + - enableTxCTS: 'false' + - txCtsSource: 'kLPUART_CtsSourcePin' + - txCtsConfig: 'kLPUART_CtsSampleAtStart' + - txRtsPolarity: 'kLPUART_RtsPolarityLow' + - rtsWatermark: '0' + - rxIdleType: 'kLPUART_IdleTypeStartBit' + - rxIdleConfig: 'kLPUART_IdleCharacter1' + - enableTx: 'true' + - enableRx: 'true' + - inverseTxd: 'false' + - quick_selection: 'QuickSelection1' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const lpuart_config_t LPUART1_config = { + .baudRate_Bps = 115200UL, + .parityMode = kLPUART_ParityDisabled, + .dataBitsCount = kLPUART_EightDataBits, + .isMsb = false, + .stopBitCount = kLPUART_OneStopBit, + .txFifoWatermark = 0U, + .rxFifoWatermark = 1U, + .enableRxRTS = false, + .enableTxRTS = false, + .enableTxCTS = false, + .txCtsSource = kLPUART_CtsSourcePin, + .txCtsConfig = kLPUART_CtsSampleAtStart, + .txRtsPolarity = kLPUART_RtsPolarityLow, + .rtsWatermark = 0U, + .rxIdleType = kLPUART_IdleTypeStartBit, + .rxIdleConfig = kLPUART_IdleCharacter1, + .enableTx = true, + .enableRx = true, + .inverseTxd = false +}; + +static void LPUART1_init(void) +{ + LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * RGPIO4 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'RGPIO4' +- type: 'rgpio' +- mode: 'GPIO' +- custom_name_enabled: 'false' +- type_id: 'rgpio_2.1.0' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'RGPIO4' +- config_sets: + - fsl_gpio: + - interrupts: + - 0: + - enable_irq: 'false' + - gpio_interrupt: + - IRQn: 'GPIO4_IRQn' + - enable_interrrupt: 'enabled' + - enable_priority: 'false' + - priority: '0' + - enable_custom_name: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void RGPIO4_init(void) +{ +} */ + +#ifdef BSP_USING_LPADC +/*********************************************************************************************************************** + * ADC1 initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'ADC1' +- type: 'lpadc' +- mode: 'LPADC' +- custom_name_enabled: 'false' +- type_id: 'lpadc_2.8.1' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'ADC1' +- config_sets: + - fsl_lpadc: + - lpadcConfig: + - clockSource: 'AsynchronousFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - enableJustifiedLeft: 'false' + - enableInDozeMode: 'true' + - conversionAverageMode: 'kLPADC_ConversionAverage2' + - offsetCalibration: 'yes' + - autoCalibrate: 'true' + - enableAnalogPreliminary: 'false' + - powerUpDelay: '0x80' + - referenceVoltageSource: 'kLPADC_ReferenceVoltageAlt2' + - triggerPriorityPolicy: 'kLPADC_ConvPreemptImmediatelyNotAutoResumed' + - enableConvPause: 'false' + - convPauseDelay: '0' + - FIFO0Watermark: '0' + - FIFO1Watermark: '0' + - FIFO0WatermarkDMA: 'true' + - FIFO1WatermarkDMA: 'false' + - lpadcConvCommandConfig: + - 0: + - user_commandId: 'GRPA' + - commandId: '1' + - chainedNextCommandNumber: '2' + - sampleChannelMode: 'kLPADC_SampleChannelSingleEndSideA' + - sampleScaleMode: 'kLPADC_SampleFullScale' + - channelNumber: 'A.1_4' + - enableChannelB_b: 'false' + - channelBScaleMode_e: 'kLPADC_SampleFullScale' + - channelBNumber: 'B.1_0' + - enableAutoChannelIncrement: 'true' + - loopCount: '3' + - hardwareAverageMode: 'kLPADC_HardwareAverageCount1' + - sampleTimeMode: 'kLPADC_SampleTimeADCK3' + - hardwareCompareMode: 'kLPADC_HardwareCompareDisabled' + - hardwareCompareValueHigh: '0' + - hardwareCompareValueLow: '0' + - conversionResoultuionMode: 'kLPADC_ConversionResolutionHigh' + - enableWaitTrigger: 'true' + - 1: + - user_commandId: 'GRPB' + - commandId: '2' + - chainedNextCommandNumber: '0' + - sampleChannelMode: 'kLPADC_SampleChannelSingleEndSideB' + - sampleScaleMode: 'kLPADC_SampleFullScale' + - channelNumber: 'B.1_5' + - enableChannelB_b: 'false' + - channelBScaleMode_e: 'kLPADC_SampleFullScale' + - channelBNumber: 'B.1_0' + - enableAutoChannelIncrement: 'true' + - loopCount: '2' + - hardwareAverageMode: 'kLPADC_HardwareAverageCount1' + - sampleTimeMode: 'kLPADC_SampleTimeADCK3' + - hardwareCompareMode: 'kLPADC_HardwareCompareDisabled' + - hardwareCompareValueHigh: '0' + - hardwareCompareValueLow: '0' + - conversionResoultuionMode: 'kLPADC_ConversionResolutionHigh' + - enableWaitTrigger: 'false' + - lpadcConvTriggerConfig: + - 0: + - user_triggerId: 'TRIG' + - triggerId: '0' + - targetCommandId: '1' + - delayPower: '0' + - priority: 'false' + - channelAFIFOSelect: '0' + - channelBFIFOSelect: '0' + - enableHardwareTrigger: 'false' + - IRQ_cfg: + - interrupt_type: '' + - enable_irq: 'false' + - adc_interrupt: + - IRQn: 'ADC1_IRQn' + - enable_interrrupt: 'enabled' + - enable_priority: 'false' + - priority: '0' + - enable_custom_name: 'true' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const lpadc_config_t ADC1_config = { + .enableInDozeMode = true, + .conversionAverageMode = kLPADC_ConversionAverage2, + .enableAnalogPreliminary = false, + .powerUpDelay = 0x80UL, + .referenceVoltageSource = kLPADC_ReferenceVoltageAlt2, + .triggerPriorityPolicy = kLPADC_ConvPreemptImmediatelyNotAutoResumed, + .enableConvPause = false, + .convPauseDelay = 0UL, + .FIFO0Watermark = 0UL, + .FIFO1Watermark = 0UL +}; +lpadc_conv_command_config_t ADC1_commandsConfig[2] = { + { + .sampleScaleMode = kLPADC_SampleFullScale, + .channelBScaleMode = kLPADC_SampleFullScale, + .sampleChannelMode = kLPADC_SampleChannelSingleEndSideA, + .channelNumber = 4U, + .channelBNumber = 0U, + .chainedNextCommandNumber = 2, + .enableChannelB = false, + .enableAutoChannelIncrement = true, + .loopCount = 3UL, + .hardwareAverageMode = kLPADC_HardwareAverageCount1, + .sampleTimeMode = kLPADC_SampleTimeADCK3, + .hardwareCompareMode = kLPADC_HardwareCompareDisabled, + .hardwareCompareValueHigh = 0UL, + .hardwareCompareValueLow = 0UL, + .conversionResolutionMode = kLPADC_ConversionResolutionHigh, + .enableWaitTrigger = true + }, + { + .sampleScaleMode = kLPADC_SampleFullScale, + .channelBScaleMode = kLPADC_SampleFullScale, + .sampleChannelMode = kLPADC_SampleChannelSingleEndSideB, + .channelNumber = 5U, + .channelBNumber = 0U, + .chainedNextCommandNumber = 0, + .enableChannelB = false, + .enableAutoChannelIncrement = true, + .loopCount = 2UL, + .hardwareAverageMode = kLPADC_HardwareAverageCount1, + .sampleTimeMode = kLPADC_SampleTimeADCK3, + .hardwareCompareMode = kLPADC_HardwareCompareDisabled, + .hardwareCompareValueHigh = 0UL, + .hardwareCompareValueLow = 0UL, + .conversionResolutionMode = kLPADC_ConversionResolutionHigh, + .enableWaitTrigger = false + } +}; +lpadc_conv_trigger_config_t ADC1_triggersConfig[1] = { + { + .targetCommandId = 1, + .delayPower = 0UL, + .channelAFIFOSelect = 0, + .channelBFIFOSelect = 0, + .priority = 1, + .enableHardwareTrigger = false + } +}; + +static void ADC1_init(void) +{ + /* Initialize LPADC converter */ + LPADC_Init(ADC1_PERIPHERAL, &ADC1_config); + /* Perform offset calibration */ + LPADC_DoOffsetCalibration(ADC1_PERIPHERAL); + /* Perform auto calibration */ + LPADC_DoAutoCalibration(ADC1_PERIPHERAL); + /* Enable DMA request on FIFO 0 watermark event */ + LPADC_EnableFIFO0WatermarkDMA(ADC1_PERIPHERAL, true); + /* Configure conversion command 1. */ + LPADC_SetConvCommandConfig(ADC1_PERIPHERAL, ADC1_GRPA, &ADC1_commandsConfig[0]); + /* Configure conversion command 2. */ + LPADC_SetConvCommandConfig(ADC1_PERIPHERAL, ADC1_GRPB, &ADC1_commandsConfig[1]); + /* Configure trigger 0. */ + LPADC_SetConvTriggerConfig(ADC1_PERIPHERAL, ADC1_TRIG, &ADC1_triggersConfig[0]); +} +#endif +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ +#ifdef BSP_USING_LPADC + ADC1_init(); +#ifdef BSP_LPADC1_USING_DMA + /* Global initialization */ + (void)memset(DMA4_config.channelConfig, 0, FSL_FEATURE_EDMA_INSTANCE_CHANNELn(DMA4_DMA_BASEADDR) * sizeof(edma_channel_config_t *)); + EDMA_Init(DMA4_DMA_BASEADDR, &DMA4_config); + /* Initialize components */ + DMA4_init(); +#endif +#endif + LPUART1_init(); + +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h new file mode 100644 index 0000000000..f01e594674 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h @@ -0,0 +1,100 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_edma.h" +#include <stdlib.h> +#include "fsl_memory.h" +#include "fsl_common.h" +#include "fsl_lpuart.h" +#include "fsl_clock.h" +#include "fsl_rgpio.h" +#include "fsl_lpadc.h" +#include "rtconfig.h" +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals functional group */ +/* Used DMA device. */ +#define DMA4_DMA_BASEADDR (EDMA_Type *)DMA4 + + /* Channel CH0 definitions */ +/* DMA4 eDMA source request. */ +#define DMA4_CH0_DMA_REQUEST kDma4RequestMuxADC1Request0 +/* Selected eDMA channel number. */ +#define DMA4_CH0_DMA_CHANNEL 0 +/* TCD pool size */ +#define DMA4_CH0_TCD_SIZE 1 +/* DMA4 interrupt vector ID (number). */ +#define DMA4_DMA_CH_INT_DONE_0_IRQN DMA4_CH0_CH1_CH32_CH33_IRQn +/* Transfer structure index 0 definition */ +#define DMA4_CH0_TRANSFER0_CONFIG DMA4_CH0_Transfers_config[0] +/* Definition of peripheral ID */ +#define LPUART1_PERIPHERAL LPUART1 +/* Definition of the clock source frequency */ +#define LPUART1_CLOCK_SOURCE 24000000UL +/* Alias for ADC1 peripheral */ +#define ADC1_PERIPHERAL ADC1 +/* Command 1 - GRPA */ +#define ADC1_GRPA 1U +/* Command 2 - GRPB */ +#define ADC1_GRPB 2U +/* Trigger 0 - TRIG */ +#define ADC1_TRIG 0U + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +#ifdef BSP_LPADC1_USING_DMA +extern edma_config_t DMA4_config; +/* Destination address extern definition */ +extern AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[], sizeof(uint32_t)); +extern edma_handle_t DMA4_CH0_Handle; +/* Transactional transfer configurations */ +extern edma_transfer_config_t DMA4_CH0_Transfers_config[1]; +#endif +extern const lpuart_config_t LPUART1_config; +extern const lpadc_config_t ADC1_config; +extern lpadc_conv_command_config_t ADC1_commandsConfig[2]; +extern lpadc_conv_trigger_config_t ADC1_triggersConfig[1]; +#ifdef BSP_LPADC1_USING_DMA +/*********************************************************************************************************************** + * Callback functions + **********************************************************************************************************************/ +/* eDMA callback function for the 0 channel.*/ +extern void DMA_Callback(edma_handle_t*, void*, bool, uint32_t); +#endif +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c new file mode 100644 index 0000000000..ddd7a99289 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c @@ -0,0 +1,115 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 26.03.10 +board: MIMXRT1180-EVK +external_user_signals: {} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08} + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09} + - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27, direction: OUTPUT, drive_strength: Normal} + - {pin_num: R13, peripheral: ADC1, signal: 'A, 1_7', pin_signal: GPIO_AD_02} + - {pin_num: T17, peripheral: ADC1, signal: 'B, 1_5', pin_signal: GPIO_AD_07} + - {pin_num: T14, peripheral: ADC1, signal: 'A, 1_4', pin_signal: GPIO_AD_08} + - {pin_num: R15, peripheral: ADC1, signal: 'B, 1_7', pin_signal: GPIO_AD_03} + - {pin_num: P15, peripheral: ADC1, signal: 'A, 1_6', pin_signal: GPIO_AD_04} + - {pin_num: P13, peripheral: ADC1, signal: 'B, 1_6', pin_signal: GPIO_AD_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + /* GPIO configuration of USER_LED_CTL1 on GPIO_AD_27 (pin M16) */ + rgpio_pin_config_t USER_LED_CTL1_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ + RGPIO_PinInit(RGPIO4, 27U, &USER_LED_CTL1_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_02_GPIO4_IO02, /* GPIO_AD_02 is configured as GPIO4_IO02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_03_GPIO4_IO03, /* GPIO_AD_03 is configured as GPIO4_IO03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_04_GPIO4_IO04, /* GPIO_AD_04 is configured as GPIO4_IO04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_05_GPIO4_IO05, /* GPIO_AD_05 is configured as GPIO4_IO05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_07_GPIO4_IO07, /* GPIO_AD_07 is configured as GPIO4_IO07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_08_GPIO4_IO08, /* GPIO_AD_08 is configured as GPIO4_IO08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 PAD functional properties : */ + 0x04U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: normal driver + Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Force ibe off Field: Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h new file mode 100644 index 0000000000..cc8e3d69cc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h @@ -0,0 +1,110 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AON_08 (coord B1), LPUART1_TXD/U61[4]/J39[4]/J70[4] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ + +/* GPIO_AON_09 (coord A5), LPUART1_RXD/U61[3]/J39[2]/J70[3] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_AD_27 (coord M16), USER_LED_CTL1/Q7[1] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_CTL1_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_CTL1_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CTL1_CHANNEL 27U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_CTL1_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN 27U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */ + +/* GPIO_AD_02 (coord R13), DMIC_DATA1/U118[1]/J45[11]/J69[5]/J41[2]/J67[6] */ +/* Routed pin properties */ +#define BOARD_INITPINS_DMIC_DATA1_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_DMIC_DATA1_SIGNAL A /*!< Signal name */ +#define BOARD_INITPINS_DMIC_DATA1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_AD_07 (coord T17), USB_OTG2_PWR/WIFI_RST_B/J39[14]/J44[3]/J69[10]/U43[3] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG2_PWR_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG2_PWR_SIGNAL B /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG2_PWR_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_AD_08 (coord T14), USB_OTG2_ID/J39[16]/J69[11]/J62[1]/J68[4]/U40[3]/U39[A1] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG2_ID_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG2_ID_SIGNAL A /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG2_ID_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_AD_03 (coord R15), DMIC_DATA2/U117[1]/J45[9]/J69[6]/J41[4]/J67[8] */ +/* Routed pin properties */ +#define BOARD_INITPINS_DMIC_DATA2_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_DMIC_DATA2_SIGNAL B /*!< Signal name */ +#define BOARD_INITPINS_DMIC_DATA2_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_AD_04 (coord P15), DMIC_DATA3/U119[1]/J45[5]/J69[7]/J41[6]/J67[10] */ +/* Routed pin properties */ +#define BOARD_INITPINS_DMIC_DATA3_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_DMIC_DATA3_SIGNAL A /*!< Signal name */ +#define BOARD_INITPINS_DMIC_DATA3_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_AD_05 (coord P13), WL_DEV_WAKE/J45[7]/J69[8]/J41[8]/U43[10] */ +/* Routed pin properties */ +#define BOARD_INITPINS_WL_DEV_WAKE_PERIPHERAL ADC1 /*!< Peripheral name */ +#define BOARD_INITPINS_WL_DEV_WAKE_SIGNAL B /*!< Signal name */ +#define BOARD_INITPINS_WL_DEV_WAKE_CHANNEL 1U /*!< Signal channel */ + +/*! + * @brief + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.md new file mode 100644 index 0000000000..6cf3ace4e2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.md @@ -0,0 +1,113 @@ +## On-chip peripheral configuration of imxrt1180-nxp-evk --LPADC1 + +### 1. Demo feature list + +- [x] use MCUX_Config software to set pin_mux, clock and LPADC1 peripheral. +- [x] board boots up from XIP (FlexSPI1_A- QSPI Flash W25Q128) +- [x] multichannel ADC enables to sample voltage from arduino connector. +- [x] only LPADC1 enabled, eDMA4 CH0 is optional to use for CPU offload. +- [x] channel A1_4, A1_5, A1_7; B1_5, B1_6, B1_7 of LPADC1 are verified. + +### 1. Hardware configuration + +### 1.1 pin configuration in MCUX_Config software + + + +### 1.2 channel allocation in hardware + + + +### 2. LPADC1 configurations + +### 2.1 General configuration + + + +- LPADC1 Clock: 80Mhz +- enable doze mode to reduce current leakage +- enable auto calibration, offset calibration +- VREFH select VDDA_ADC_1P8, selecting from power pin directly +- enable FIFO 0 watermark event for DMA trigger + +### 2.2 Command configuration + +Command settings are consisted of group A and group B (GRPA, GRPB). GRPA is used for channel A1_4, A1_5, A1_7, while GRPB is used for channelB1_5, B1_6, B1_7. + + + +- next command: 2 +- sample mode: single +- channel starts from A1_4 +- auto channel increment enabled, conversion continues to the end. +- full scale, which means max input of analog pin is 1.8V +- conversion resolution: 16-bit +- wait for software trigger + + + +- next command: none + +- sample mode: single + +- channel starts from B1_5 + +- auto channel increment enabled, conversion continues to the end. + +- full scale, which means max input of analog pin is 1.8V + +- conversion resolution: 16-bit + +- loop count: 2 + + + +### 2.3 trigger configuration + + + +software trigger TRIG is used to trigger command group A. + +### 2.4 EDMA configuration + + + +- Channel ID: CH0 +- request source: #57: ADC1 Request 0 +- enable peripheral request to trigger DMA + + + +- source address: ADC1 result register +- destination address: NONCACHEABLE memory +- minor loop transfer: 4 +- major loop count: 7 +- adjust address after each transfer: -28 + +## 3. RTT &chip sdk configuration + +type "menuconfig.exe" in env tool, go to "Hardware Drivers Config" --> "On-chip Peripheral Drivers": + + + + + + + +The codes below shall be added to sdk module to enable codes chip-specific adding to the project. + + + + + +## 4. LPADC1 test + +in MSH console, the command below can be entered to start LPDAC1 driver test. + + + +## 5. limitation for this demo + +- Strongly relying on MCUX_Config for LPADC1 peripheral initialization, lack flexible for drv_lpadc +- Only demonstrate how to implement multichannel ADC sampling +- Max supported number of single end channel is eight, limited from RTT device driver level. verified channel in this demo is channel 4-7 representing A1_4, B1_5, A1_6, A1_7 separately.
\ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript index ad731bbaf2..09cc252053 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript @@ -5,17 +5,30 @@ import rtconfig cwd = GetCurrentDir() -# add the general drivers. -src = Split(""" -board.c -MCUX_Config/clock_config.c -MCUX_Config/pin_mux.c -""") +if GetDepend(['BSP_USING_LPADC1']): + # add the LPADC1 drivers. + src = Split(""" + board.c + MCUX_Config_LPADC1/clock_config.c + MCUX_Config_LPADC1/pin_mux.c + MCUX_Config_LPADC1/peripherals.c + """) +else: + # add the general drivers. + src = Split(""" + board.c + MCUX_Config/clock_config.c + MCUX_Config/pin_mux.c + """) if GetDepend(['BSP_USING_QSPI_FLASH_FS']): src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c'] -CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +if GetDepend(['BSP_USING_LPADC1']): + CPPPATH = [cwd,cwd + '/MCUX_Config_LPADC1',cwd + '/ports'] +else: + CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] + CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33'] if rtconfig.PLATFORM in ['gcc']: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index 2557a72bc4..eab523dd08 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -436,7 +436,7 @@ void BOARD_ConfigMPU(void) // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 - ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); + // ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 @@ -1250,13 +1250,15 @@ void imxrt_uart_pins_init(void) void rt_hw_board_init() { -// BOARD_CommonSetting(); + extern void BOARD_InitPeripherals(void); + BOARD_CommonSetting(); BOARD_ConfigMPU(); BOARD_InitPins(); - BOARD_InitLeds(); +// BOARD_InitLeds(); BOARD_BootClockRUN(); - + BOARD_InitPeripherals(); + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h index c0b50be6fc..4c728b11f4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -149,6 +149,7 @@ #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_ADC #define RT_USING_PIN /* end of Device Drivers */ @@ -296,6 +297,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -329,6 +334,10 @@ /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -419,6 +428,9 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_DMA +#define BSP_USING_LPADC +#define BSP_USING_LPADC1 +#define BSP_LPADC1_USING_DMA #define BSP_USING_LPUART #define BSP_USING_LPUART1 /* end of On-chip Peripheral Drivers */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 0000000000..5a48fc80d4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,20 @@ +scons.args: &scons + scons_arg: + - '--strict' + +# ------ component CI ------ + +# ------ Peripheral CI ------ +Peripheral.hyperflash_dma: + <<: *scons + kconfig: + - CONFIG_BSP_USING_DMA=y + - CONFIG_BSP_USING_FLEXSPI=y + - CONFIG_BSP_USING_FLEXSPI1=y + - CONFIG_BSP_USING_OSPI_FLASH=y +Peripheral.hyperflash: + <<: *scons + kconfig: + - CONFIG_BSP_USING_FLEXSPI=y + - CONFIG_BSP_USING_FLEXSPI1=y + - CONFIG_BSP_USING_OSPI_FLASH=y
\ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config index 8f89639f0f..c78e44a8db 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -184,6 +184,7 @@ CONFIG_RT_VER_NUM=0x50300 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_HW_ATOMIC=y CONFIG_ARCH_USING_HW_ATOMIC_8=y CONFIG_ARCH_USING_HW_ATOMIC_16=y @@ -191,7 +192,7 @@ CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_FPU=y -CONFIG_ARCH_ARM_CORTEX_M33=y +CONFIG_ARCH_ARM_CORTEX_M7=y # # RT-Thread Components @@ -268,8 +269,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set -# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -576,6 +579,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set # end of multimedia packages @@ -583,6 +587,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -627,6 +633,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set @@ -729,6 +736,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -812,7 +821,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -877,9 +900,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -905,6 +926,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers # end of HAL & SDK Drivers # @@ -1085,6 +1112,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set @@ -1439,7 +1467,7 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y # # On-chip Peripheral Drivers # -# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_DMA=y # CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set @@ -1450,12 +1478,15 @@ CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_LPUART1_TX_USING_DMA is not set # CONFIG_BSP_USING_LPUART3 is not set # CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_FLEXSPI is not set +CONFIG_BSP_USING_FLEXSPI=y +CONFIG_BSP_USING_FLEXSPI1=y +# CONFIG_BSP_USING_FLEXSPI2 is not set # end of On-chip Peripheral Drivers # # Onboard Peripheral Drivers # +CONFIG_BSP_USING_OSPI_FLASH=y # CONFIG_BSP_USING_SDRAM is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_FS is not set diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig index 9199e247ab..affef3fc18 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -206,6 +206,11 @@ endmenu menu "Onboard Peripheral Drivers" + config BSP_USING_OSPI_FLASH + bool "Enable HyperFlash Example" + depends on BSP_USING_FLEXSPI1 + default n + config BSP_USING_SDRAM bool "Enable SDRAM" default n diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex new file mode 100644 index 0000000000..86d08e9e4b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex @@ -0,0 +1,664 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1189xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="2789973b-4e08-461b-a604-ca74c2c2a2cf" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1189xxxxx</processor> + <package>MIMXRT1189CVM8C</package> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm7"> + <core name="Cortex-M33" id="cm33" description=""/> + <core name="Cortex-M7F" id="cm7" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>26.03.10</processor_version> + <pin_labels> + <pin_label pin_num="M16" pin_signal="GPIO_AD_27" label="USER_LED_CTL1" identifier="USER_LED_CTL1"/> + </pin_labels> + <external_user_signals> + <properties/> + </external_user_signals> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm7</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXSPI1" description="Peripheral FLEXSPI1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.rgpio" description="Pins initialization requires the RGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TXD" pin_num="B1" pin_signal="GPIO_AON_08"/> + <pin peripheral="LPUART1" signal="RXD" pin_num="A5" pin_signal="GPIO_AON_09"/> + <pin peripheral="RGPIO4" signal="gpio_io, 27" pin_num="M16" pin_signal="GPIO_AD_27"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + </pin_features> + </pin> + <pin peripheral="ARM" signal="arm_trace_swo" pin_num="A4" pin_signal="GPIO_AON_11"/> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_SCLK" pin_num="A7" pin_signal="GPIO_B2_08"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_SS0_B" pin_num="D10" pin_signal="GPIO_B2_09"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA0" pin_num="A10" pin_signal="GPIO_B2_10"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA1" pin_num="B9" pin_signal="GPIO_B2_11"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA2" pin_num="A8" pin_signal="GPIO_B2_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA3" pin_num="B8" pin_signal="GPIO_B2_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA4" pin_num="D9" pin_signal="GPIO_B2_03"/> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA5" pin_num="C9" pin_signal="GPIO_B2_04"/> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA6" pin_num="A9" pin_signal="GPIO_B2_05"/> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DATA7" pin_num="E8" pin_signal="GPIO_B2_06"/> + <pin peripheral="FLEXSPI1" signal="FLEXSPI_A_DQS" pin_num="A6" pin_signal="GPIO_B2_07"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="20.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>26.03.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.misc" description="Clocks initialization requires the MISC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.misc" description="Clocks initialization requires the MISC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.ele_base_api" description="Clocks initialization requires the ELE_BASE_API Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm33"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.ele_base_api" description="Clocks initialization requires the ELE_BASE_API Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="cm7"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="ACMP_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ADC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ADC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ARM_PLL_CLK.outFreq" value="792 MHz" locked="false" accuracy=""/> + <clock_output id="ASRC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="BUS_AON_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="BUS_WAKEUP_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="CAN1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CAN2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CAN3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="CCM_CKO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CCM_CKO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="ECAT_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="EDGELOCK_CLK_ROOT.outFreq" value="200 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_REFCLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="120 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI1_CLK_ROOT.outFreq" value="400 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="270 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_SLV_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="I3C1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="I3C2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0102_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0304_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C0506_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPIT3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0102_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0304_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI0506_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR1_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPTMR3_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0102_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0304_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0506_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0708_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART0910_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="LPUART1112_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="M33_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="M33_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/> + <clock_output id="M7_CLK_ROOT.outFreq" value="792 MHz" locked="false" accuracy=""/> + <clock_output id="M7_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/> + <clock_output id="MAC0_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="MAC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="MAC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="MAC3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="MAC4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="MIC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="NETC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_32K.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="OSC_RC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="OSC_RC_400M.outFreq" value="400 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SAI4_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="SWO_TRACE_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_CLK.outFreq" value="528 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD0_CLK.outFreq" value="352 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD1_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD2_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL2_PFD3_CLK.outFreq" value="297 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_DIV2_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD0_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD1_CLK.outFreq" value="8640/17 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD2_CLK.outFreq" value="270 MHz" locked="false" accuracy=""/> + <clock_output id="SYS_PLL3_PFD3_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/> + <clock_output id="TMR_1588_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="TMR_1588_REF_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="TPM2_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM4_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM5_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="TPM6_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="WAKEUP_AXI_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="AONDomainVoltage" value="OD" locked="false"/> + <setting id="CoreClockRootsInitializationConfig" value="selectedCore" locked="false"/> + <setting id="SOCDomainVoltage" value="OD" locked="false"/> + <setting id="ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG" value="Low" locked="false"/> + <setting id="ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL.ARM_PLL_PREDIV.scale" value="1" locked="true"/> + <setting id="ANADIG_PLL.ARM_PLL_VDIV.scale" value="132" locked="true"/> + <setting id="ANADIG_PLL.PLL_AUDIO_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL1_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2.denom" value="268435455" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2.div" value="22" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2.num" value="0" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2_PFD1_DIV.scale" value="24" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL2_SS_DIV.scale" value="268435455" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale" value="22" locked="false"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale" value="22" locked="true"/> + <setting id="ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG" value="Disabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG" value="Disabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG" value="Disabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> + <setting id="ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG" value="Enabled" locked="false"/> + <setting id="CCM.CLOCK_ROOT0.DIV.scale" value="1" locked="true"/> + <setting id="CCM.CLOCK_ROOT0.MUX.sel" value="ANADIG_PLL.ARM_PLL_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT1.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT1.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT10.DIV.scale" value="5" locked="true"/> + <setting id="CCM.CLOCK_ROOT10.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT11.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT11.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT12.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT12.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT13.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT13.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT14.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT14.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT15.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT15.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT16.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT16.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT17.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT17.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT18.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT18.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT19.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT2.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT2.MUX.sel" value="ANADIG_OSC.OSC_RC_400M" locked="false"/> + <setting id="CCM.CLOCK_ROOT20.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT21.DIV.scale" value="1" locked="true"/> + <setting id="CCM.CLOCK_ROOT21.MUX.sel" value="ANADIG_OSC.OSC_RC_400M" locked="false"/> + <setting id="CCM.CLOCK_ROOT22.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT23.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT23.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT24.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT24.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT25.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT25.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT26.DIV.scale" value="6" locked="true"/> + <setting id="CCM.CLOCK_ROOT26.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT3.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT3.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT33.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT33.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT34.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT34.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT35.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT35.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT4.DIV.scale" value="4" locked="true"/> + <setting id="CCM.CLOCK_ROOT4.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT5.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT5.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> + <setting id="CCM.CLOCK_ROOT6.DIV.scale" value="3" locked="true"/> + <setting id="CCM.CLOCK_ROOT6.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT68.DIV.scale" value="2" locked="false"/> + <setting id="CCM.CLOCK_ROOT68.MUX.sel" value="N/A" locked="false"/> + <setting id="CCM.CLOCK_ROOT7.DIV.scale" value="240" locked="true"/> + <setting id="CCM.CLOCK_ROOT7.MUX.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> + <setting id="CCM.CLOCK_ROOT8.DIV.scale" value="240" locked="false"/> + <setting id="CCM.CLOCK_ROOT9.DIV.scale" value="2" locked="true"/> + <setting id="CCM.CLOCK_ROOT9.MUX.sel" value="ANADIG_PLL.SYS_PLL3_DIV2_CLK" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="4.0" enabled="true" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>26.03.10</processor_version> + <output_format>c_array</output_format> + </dcdx_profile> + <dcdx_configurations> + <dcdx_configuration name="Device_configuration"> + <description></description> + <options/> + <command_groups> + <command_group name="Imported Commands" enabled="true"> + <commands> + <command type="write_value" address="CCM_CLOCK_ROOT4_CONTROL" value="0x602" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39" value="0x10" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20" value="0x00" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04" value="0x08" value_width="4"/> + <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05" value="0x08" value_width="4"/> + <command type="write_value" address="SEMC_MCR" value="0x10000004" value_width="4"/> + <command type="write_value" address="SEMC_BMCR0" value="0x81" value_width="4"/> + <command type="write_value" address="SEMC_BMCR1" value="0x81" value_width="4"/> + <command type="write_value" address="SEMC_BR0" value="0x8000001D" value_width="4"/> + <command type="write_value" address="SEMC_SDRAMCR0" value="0xF32" value_width="4"/> + <command type="write_value" address="SEMC_SDRAMCR1" value="0x772A22" value_width="4"/> + <command type="write_value" address="SEMC_SDRAMCR2" value="0x10A0D" value_width="4"/> + <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210408" value_width="4"/> + <command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/> + <command type="write_value" address="SEMC_IPCR1" value="0x02" value_width="4"/> + <command type="write_value" address="SEMC_IPCR2" value="0x00" value_width="4"/> + <command type="write_value" address="SEMC_IPCMD" value="0xA55A000F" value_width="4"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> + <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> + <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> + <command type="write_value" address="SEMC_IPTXDAT" value="0x33" value_width="4"/> + <command type="write_value" address="SEMC_IPCMD" value="0xA55A000A" value_width="4"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="nop"/> + <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> + <command type="nop"/> + <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210409" value_width="4"/> + </commands> + </command_group> + </command_groups> + </dcdx_configuration> + </dcdx_configurations> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <peripherals_profile> + <processor_version>26.03.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="7ee8fc36-68c9-403c-a923-44701e1362da" called_from_default_init="true" id_prefix="" core="cm7"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CM7_NVIC" uuid="8ba49e5b-e3c8-49ef-bea4-033c0f90e077" type="nvic" type_id="nvic" mode="general" peripheral="CM7_NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="58d02eb0-c8a1-4795-aa02-b881f9b49f65" type_id="system_54b53072540eeeb8f8e9343e71f28176"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="fef81701-6364-47eb-be4e-1ff685c6f487" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_uart" uuid="82bb7638-b911-4bff-8d51-e85a18d5f0c8" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="72d70388-6163-458b-9bd7-e49b1b8c0e60" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="7caa4732-5e54-4482-8d2b-2648eb52adab" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="gpio_adapter_common" uuid="c2f350f4-c700-4bc8-8fb1-aa56fd3533d1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="77d2c2b6-f8f5-4d79-9870-5662fd323401" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>N/A</processor_version> + </tee_profile> + </tee> + </tools> +</configuration>
\ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c new file mode 100644 index 0000000000..7f6a8d7218 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c @@ -0,0 +1,739 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v20.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 26.03.10 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 24 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 400 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 270 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI1_MCLK1.outFreq, value: 24 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI2_MCLK1.outFreq, value: 24 MHz} +- {id: SAI2_MCLK3.outFreq, value: 24 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI3_MCLK1.outFreq, value: 24 MHz} +- {id: SAI3_MCLK3.outFreq, value: 24 MHz} +- {id: SAI4_MCLK3.outFreq, value: 24 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 24 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 24 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_PFD1_DIV.scale, value: '24'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: N/A} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Bypass Sys Pll1. */ + CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + /* DeInit Sys Pll1. */ + CLOCK_DeinitSysPll1(); + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 24); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_RC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using OSC_RC_400M */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M, 1U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 1U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using OSC_RC_24M */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using OSC_RC_24M */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using OSC_RC_24M */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using OSC_RC_24M */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using OSC_RC_24M */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using OSC_RC_24M */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc24M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h new file mode 100644 index 0000000000..11db4bd91e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h @@ -0,0 +1,177 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 24000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 24000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 24000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 0UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 0UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 24000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 400000000UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 270000000UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 24000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 24000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 24000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 24000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 24000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 24000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 0UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 0UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 0UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 0UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 0UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 24000000UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 24000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 24000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_bottom.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_bottom.png Binary files differnew file mode 100644 index 0000000000..b35ee10aa4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_bottom.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_top.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_top.png Binary files differnew file mode 100644 index 0000000000..797acbfbca --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_top.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/MIMXRT1180_SConsript_add.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/MIMXRT1180_SConsript_add.png Binary files differnew file mode 100644 index 0000000000..dd7690f52a --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/MIMXRT1180_SConsript_add.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/flexspi_test result.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/flexspi_test result.png Binary files differnew file mode 100644 index 0000000000..49f2e2ca01 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/flexspi_test result.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/pin_config.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/pin_config.png Binary files differnew file mode 100644 index 0000000000..d524dead37 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/pin_config.png diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c new file mode 100644 index 0000000000..e68ddd42ec --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 26.03.10 +external_user_signals: {} +pin_labels: +- {pin_num: M16, pin_signal: GPIO_AD_27, label: USER_LED_CTL1, identifier: USER_LED_CTL1} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08} + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09} + - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27, direction: OUTPUT} + - {pin_num: A4, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_AON_11} + - {pin_num: A7, peripheral: FLEXSPI1, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_B2_08, software_input_on: Disable} + - {pin_num: D10, peripheral: FLEXSPI1, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_B2_09, software_input_on: Disable} + - {pin_num: A10, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_B2_10, software_input_on: Disable} + - {pin_num: B9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_B2_11, software_input_on: Disable} + - {pin_num: A8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_B2_12, software_input_on: Disable} + - {pin_num: B8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_B2_13, software_input_on: Disable} + - {pin_num: D9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA4, pin_signal: GPIO_B2_03} + - {pin_num: C9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA5, pin_signal: GPIO_B2_04} + - {pin_num: A9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA6, pin_signal: GPIO_B2_05} + - {pin_num: E8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA7, pin_signal: GPIO_B2_06} + - {pin_num: A6, peripheral: FLEXSPI1, signal: FLEXSPI_A_DQS, pin_signal: GPIO_B2_07, software_input_on: Disable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + /* GPIO configuration of USER_LED_CTL1 on GPIO_AD_27 (pin M16) */ + rgpio_pin_config_t USER_LED_CTL1_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 0U, + }; + /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ + RGPIO_PinInit(RGPIO4, 27U, &USER_LED_CTL1_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04, /* GPIO_B2_03 is configured as FLEXSPI1_BUS2BIT_A_DATA04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05, /* GPIO_B2_04 is configured as FLEXSPI1_BUS2BIT_A_DATA05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06, /* GPIO_B2_05 is configured as FLEXSPI1_BUS2BIT_A_DATA06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07, /* GPIO_B2_06 is configured as FLEXSPI1_BUS2BIT_A_DATA07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS, /* GPIO_B2_07 is configured as FLEXSPI1_BUS2BIT_A_DQS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK, /* GPIO_B2_08 is configured as FLEXSPI1_BUS2BIT_A_SCLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B, /* GPIO_B2_09 is configured as FLEXSPI1_BUS2BIT_A_SS0_B */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00, /* GPIO_B2_10 is configured as FLEXSPI1_BUS2BIT_A_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01, /* GPIO_B2_11 is configured as FLEXSPI1_BUS2BIT_A_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02, /* GPIO_B2_12 is configured as FLEXSPI1_BUS2BIT_A_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03, /* GPIO_B2_13 is configured as FLEXSPI1_BUS2BIT_A_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_11_JTAG_MUX_TDO, /* GPIO_AON_11 is configured as JTAG_MUX_TDO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h new file mode 100644 index 0000000000..a84709fede --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_27 (coord M16), USER_LED_CTL1 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_CTL1_PERIPHERAL RGPIO4 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_CTL1_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CTL1_CHANNEL 27U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO RGPIO4 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_CTL1_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN 27U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.md new file mode 100644 index 0000000000..3faabe2ea5 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.md @@ -0,0 +1,44 @@ +## On-chip peripheral configuration of imxrt1180-nxp-evk --FlexSPI1 + +### 1. Demo feature list + +- [x] use MCUX_Config software to set pin_mux, clock. +- [x] board boots up from CMSIS-DAP. (FlexSPI1_A- QSPI Flash W25Q128 is used for CM33 XIP boot-up) +- [x] FlexSPI1_B is set to octal mode for hyperFlash(MT35XU512ABA2G12-0AAT) reading&writing +- [x] when BSP_USING_DMA is enabled, eDMA4 CH0 is used for TX and CH2 for RX for CPU offload. +- [x] flexspi_test command is used for test in MSH console. + +### 2. Hardware configuration + +### 2.1 pin configuration in MCUX_Config software + + + + + +### 2.2 hardware change on top + + + +### 2.3 hardware change on bottom + + + +do hardware change to enable path for hyper Flash. + +### 2.4 chip sdk change + + + +add these codes above to "nxp-imxrt-sdk-latest/MIMXRT1180/SConscript" to enable chip specific drivers. + +### 3. FlexSPI1_b octal mode test + + + +### 4. limitation + +- only use MCUX_Config for pin_mux, clock configuration, providing enough flexibility on drv_flexspi. +- merge official examples on FlexSPI octal polling and DMA mode for hyper Flash operation. XIP and FLASH_ADESTO are not supported. +- Only support booting from CMSIS-DAP due to hardware limitation. + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript index 81007a0eeb..dabd72da3f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -2,14 +2,29 @@ from building import * cwd = GetCurrentDir() -# add the general drivers. -src = Split(""" -board.c -MCUX_Config/clock_config.c -MCUX_Config/pin_mux.c -""") +if GetDepend(['BSP_USING_OSPI_FLASH']): + # add the OSPI_hyperFlash drivers. + src = Split(""" + board.c + MCUX_Config_hyperFlash/clock_config.c + MCUX_Config_hyperFlash/pin_mux.c + """) +else: + # add the general drivers. + src = Split(""" + board.c + MCUX_Config/clock_config.c + MCUX_Config/pin_mux.c + """) + +if GetDepend(['BSP_USING_OSPI_FLASH']): + src += ['ports/flexspi_octal_flash_ops.c'] + +if GetDepend(['BSP_USING_OSPI_FLASH']): + CPPPATH = [cwd,cwd + '/MCUX_Config_hyperFlash',cwd + '/ports'] +else: + CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 'ARM_MATH_CM7'] if rtconfig.PLATFORM in ['gcc']: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c index 0c4db043d1..f0303bfc91 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -12,6 +12,10 @@ #include "fsl_iomuxc.h" #include "fsl_rgpio.h" #include "fsl_cache.h" +#include "fsl_ele_base_api.h" +#include "fsl_dcdc.h" +#include "fsl_trdc.h" +#include "fsl_rgpio.h" #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 4 bits for subpriority */ @@ -229,6 +233,478 @@ void BOARD_ConfigMPU(void) L1CACHE_EnableICache(); } +void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) +{ +#define ELE_TRDC_AON_ID 0x74 +#define ELE_TRDC_WAKEUP_ID 0x78 +#define ELE_TRDC_MEGA_ID 0x82 +#define ELE_CORE_CM33_ID 0x1 +#define ELE_CORE_CM7_ID 0x2 + +#if (__CORTEX_M == 33) + uint8_t ele_core_id = ELE_CORE_CM33_ID; +#elif (__CORTEX_M == 7) + uint8_t ele_core_id = ELE_CORE_CM7_ID; +#endif + + uint32_t ele_fw_sts; + + /* Get ELE FW status */ + ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts); + + if (bRequestAON) + { + /* Release TRDC AON to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ele_core_id); + } + + /* + * TRDC MEGA request must be prior to TRDC WAKEUP, as TRDC MEGA access + * is controlled by the TRDC WAKEUP. + * note: + * If TRDC WAKEUP has been release to one core firstly, then it will fail + * to release TRDC MEGA to same/another core. + */ + if (bReqeustMega) + { + /* Release TRDC MEGA to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_MEGA_ID, ele_core_id); + } + + if (bRequestWakeup) + { + /* Release TRDC WAKEUP to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ele_core_id); + } +} + +void APP_CommonTrdcDACSetting(void) +{ + trdc_processor_domain_assignment_t procAssign = {.domainId = 0U, + .domainIdSelect = kTRDC_DidInput, + .pidDomainHitConfig = kTRDC_pidDomainHitNone0, + .pidMask = 0U, + .secureAttr = kTRDC_ForceSecure, + .pid = 0U, + .lock = false + }; + + trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U, + .privilegeAttr = kTRDC_ForcePrivilege, + .secureAttr = kTRDC_ForceSecure, + .bypassDomainId = true, + .lock = false + }; + + /* 1. Set the MDAC Configuration in TRDC1. */ + /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */ + procAssign.domainId = 0x2U; + TRDC_SetProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterCM33, 0U, &procAssign); + /* Configure the access control for eDMA3(master 2 for TRDC1, MDAC_A2). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterDMA3, &nonProcAssign); + + /* 2. Set the MDAC Configuration in TRDC2. */ + /* Configure the access control for CM7 AHBP(master 0 for TRDC2, MDAC_W0). */ + procAssign.domainId = 0x4U; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AHBP, 0U, &procAssign); + /* Configure the access control for CM7 AXI(master 1 for TRDC2, MDAC_W1). */ + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AXI, 0U, &procAssign); + /* Configure the access control for DAP AHB_AP_SYS(master 2 for TRDC2, MDAC_W2). */ + nonProcAssign.domainId = 0x9U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDAP, &nonProcAssign); + /* Configure the access control for CoreSight(master 3 for TRDC2, MDAC_W3). */ + nonProcAssign.domainId = 0x8U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCoreSight, &nonProcAssign); + /* Configure the access control for DMA4(master 4 for TRDC2, MDAC_W4). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDMA4, &nonProcAssign); + /* Configure the access control for NETC(master 5 for TRDC2, MDAC_W5). */ + procAssign.domainId = 0xAU; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterNETC, 0U, &procAssign); + + /* 3. Set the MDAC Configuration in TRDC3. */ + /* Configure the access control for uSDHC1(master 0 for TRDC3, MDAC_M0). */ + nonProcAssign.domainId = 0x5U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC1, &nonProcAssign); + /* Configure the access control for uSDHC2(master 1 for TRDC3, MDAC_M1). */ + nonProcAssign.domainId = 0x6U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC2, &nonProcAssign); + /* Configure the access control for USB(master 3 for TRDC3, MDAC_M3). */ + nonProcAssign.domainId = 0xBU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUsb, &nonProcAssign); + /* Configure the access control for FlexSPI_FLR(master 4 for TRDC3, MDAC_M4). */ + nonProcAssign.domainId = 0xAU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterFlexspiFlr, &nonProcAssign); +} + +static bool TRDC_IsValidDomain(TRDC_Type *trdc, uint8_t domain) +{ + bool r = true; + + if ((domain > 11) || (domain < 2) || (domain == 3)) + { + r = false; + } + return r; +} + +static bool TRDC_IsValidMbc(TRDC_Type *trdc, uint8_t mbc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + case 1: /* TRDC1 MBC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + case 1: /* TRDC2 MBC_W1 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) +{ + uint32_t memNumber = 0U; + if (trdc == TRDC1) + { + uint8_t MemNum[2] = {3, 2}; + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */ + case 1: /* TRDC1 MBC_A1 CM33 Code-TCM/CM33 System-TCM */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + uint8_t MemNum[2] = {4, 4}; + switch (mbc) + { + case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */ + case 1: /* TRDC2 MBC_A1 AIPS3/AHB_ISPAP/NIC_MAIN GPV/SRAMC */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + return memNumber; +} + +static bool TRDC_IsValidMbcMem(TRDC_Type *trdc, uint8_t mbc, uint8_t mem) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A0 AIPS1 */ + r = true; + break; + case 1: /* TRDC1 MBC_A0 Edgelock */ + break; /* Intentional, Edgelock region not touched. */ + case 2: /* TRDC1 MBC_A0 GPIO1 */ + r = true; + break; + default: + break; + } + break; + case 1: /* TRDC1 MBC_A1 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A1 CM33 Code-TCM */ + case 1: /* TRDC1 MBC_A1 CM33 System-TCM */ + r = true; + break; + default: + break; + } + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W0 AIPS2 */ + case 1: /* TRDC2 MBC_W0 GPIO2, GPIO4, GPIO6 */ + case 2: /* TRDC2 MBC_W0 GPIO3, GPIO5 */ + case 3: /* TRDC2 MBC_W0 DAP (Debug) */ + r = true; + break; + + default: + break; + } + break; + case 1: /* TRDC2 MBC_W1 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W1 AIPS3 */ + case 1: /* TRDC2 MBC_W1 AHB_ISPAP */ + case 2: /* TRDC2 MBC_W1 NIC_MAIN GPV */ + case 3: /* TRDC2 MBC_W1 SRAMC */ + r = true; + break; + + default: + break; + } + break; + default: + break; + } + } + return r; +} + +static bool TRDC_IsValidMrc(TRDC_Type *trdc, uint8_t mrc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 */ + case 1: /* TRDC1 MRC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 */ + case 2: /* TRDC2 MRC_W2 */ + case 3: /* TRDC2 MRC_W3 */ + case 4: /* TRDC2 MRC_W4 */ + case 5: /* TRDC2 MRC_W5 */ + case 6: /* TRDC2 MRC_W6 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStartAddr, uint32_t *pStopAddr) +{ + bool r = true; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 CM33 ROM */ + *pStartAddr = 0x00000000UL; + *pStopAddr = 0x00027FFFUL; + break; + case 1: /* TRDC1 MRC_A1 FlexSPI2 */ + *pStartAddr = 0x04000000UL; + *pStopAddr = 0x07FFFFFFUL; + break; + default: + r = false; + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 FlexSPI1 */ + *pStartAddr = 0x28000000UL; + *pStopAddr = 0x2FFFFFFFUL; + break; + case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */ + *pStartAddr = 0x203C0000UL; + *pStopAddr = 0x2043FFFFUL; + break; + case 3: /* TRDC2 MRC_W3 OCRAM1 */ + *pStartAddr = 0x20480000UL; + *pStopAddr = 0x204FFFFFUL; + break; + case 4: /* TRDC2 MRC_W4 OCRAM2 */ + *pStartAddr = 0x20500000UL; + *pStopAddr = 0x2053FFFFUL; + break; + case 5: /* TRDC2 MRC_W5 SEMC */ + *pStartAddr = 0x80000000UL; + *pStopAddr = 0x8FFFFFFFUL; + break; + case 6: /* TRDC2 MRC_W6 NETC */ + *pStartAddr = 0x60000000UL; + *pStopAddr = 0x60FFFFFFUL; + break; + default: + r = false; + break; + } + } + return r; +} + +void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) +{ + trdc_hardware_config_t hwConfig; + trdc_memory_access_control_config_t memAccessConfig; + trdc_mbc_memory_block_config_t mbcBlockConfig; + trdc_mrc_region_descriptor_config_t mrcRegionConfig; + + TRDC_GetHardwareConfig(trdc, &hwConfig); + + /* Enable all read/write/execute access for MRC/MBC access control. */ + (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig)); + memAccessConfig.nonsecureUsrX = 1U; + memAccessConfig.nonsecureUsrW = 1U; + memAccessConfig.nonsecureUsrR = 1U; + memAccessConfig.nonsecurePrivX = 1U; + memAccessConfig.nonsecurePrivW = 1U; + memAccessConfig.nonsecurePrivR = 1U; + memAccessConfig.secureUsrX = 1U; + memAccessConfig.secureUsrW = 1U; + memAccessConfig.secureUsrR = 1U; + memAccessConfig.securePrivX = 1U; + memAccessConfig.securePrivW = 1U; + memAccessConfig.securePrivR = 1U; + + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MrcSetMemoryAccessConfig(trdc, &memAccessConfig, mrc, i); + } + } + } + + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MbcSetMemoryAccessConfig(trdc, &memAccessConfig, mbc, i); + } + } + } + + memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig)); + mbcBlockConfig.nseEnable = false; + mbcBlockConfig.memoryAccessControlSelect = 0; + + memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig)); + mrcRegionConfig.memoryAccessControlSelect = 0U; + mrcRegionConfig.valid = true; + mrcRegionConfig.nseEnable = false; + mrcRegionConfig.regionIdx = 0U; + + for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++) + { + if (TRDC_IsValidDomain(trdc, domain)) + { + /* Set the configuration for MBC. */ + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + uint32_t mem_num = TRDC_GetMbcMemNum(trdc, mbc); + for (uint32_t mem = 0; mem < mem_num; mem++) + { + if (TRDC_IsValidMbcMem(trdc, mbc, mem)) + { + trdc_slave_memory_hardware_config_t mbcHwConfig; + TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem); + for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++) + { + mbcBlockConfig.domainIdx = domain; + mbcBlockConfig.mbcIdx = mbc; + mbcBlockConfig.slaveMemoryIdx = mem; + mbcBlockConfig.memoryBlockIdx = block; + TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig); + } + } + } + } + } + + /* Set the configuration for MRC. */ + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + uint32_t start_addr, end_addr; + + if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr)) + { + mrcRegionConfig.startAddr = start_addr; + mrcRegionConfig.endAddr = end_addr; + mrcRegionConfig.domainIdx = domain; + mrcRegionConfig.mrcIdx = mrc; + TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig); + } + else + { + assert(false); + } + } + } + } + } +} + +void BOARD_GrantTRDCFullPermissions(void) +{ + /* 1. Request TRDC ownership */ + BOARD_RequestTRDC(true, true, true); + + /* 2. Config DAC. */ + APP_CommonTrdcDACSetting(); + + /* 3. Enable all access control */ + APP_CommonTrdcAccessControlSetting(TRDC1); + APP_CommonTrdcAccessControlSetting(TRDC2); +} + +void BOARD_CommonSetting(void) +{ + BOARD_GrantTRDCFullPermissions(); +} + /* This is the timer interrupt service routine. */ void SysTick_Handler(void) { @@ -271,6 +747,7 @@ void imxrt_uart_pins_init(void) void rt_hw_board_init() { + BOARD_CommonSetting(); BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c new file mode 100644 index 0000000000..0007dd5f95 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_octal_flash_ops.c @@ -0,0 +1,525 @@ +/* + * Copyright 2019-2022, 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi.h" +#include "flexspi_port.h" +#include "rtconfig.h" + +#ifdef BSP_USING_FLEXSPI1 + +#ifdef BSP_USING_DMA +#include "fsl_flexspi_edma.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/******************************************************************************* + * Variables + ******************************************************************************/ +#ifdef BSP_USING_DMA +extern volatile bool g_completionFlag; +extern flexspi_edma_handle_t flexspiHandle; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#ifdef BSP_USING_DMA + +#endif + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN +void flexspi_nor_disable_cache(flexspi_cache_status_t *cacheStatus) +{ + (void)memset(cacheStatus, 0, sizeof(flexspi_cache_status_t)); + +#if (defined __CORTEX_M) && (__CORTEX_M == 7U) +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + /* Disable D cache. */ + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + cacheStatus->DCacheEnableFlag = true; + } +#endif /* __DCACHE_PRESENT */ + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + /* Disable I cache. */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + cacheStatus->ICacheEnableFlag = true; + } +#endif /* __ICACHE_PRESENT */ + +#elif (defined FSL_FEATURE_SOC_LMEM_COUNT) && (FSL_FEATURE_SOC_LMEM_COUNT != 0U) + /* Disable code bus cache and system bus cache */ + if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) + { + L1CACHE_DisableCodeCache(); + cacheStatus->codeCacheEnableFlag = true; + } + + if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) + { + L1CACHE_DisableSystemCache(); + cacheStatus->systemCacheEnableFlag = true; + } + +#elif (defined FSL_FEATURE_SOC_CACHE64_CTRL_COUNT) && (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT != 0U) + /* Disable cache */ + CACHE64_DisableCache(EXAMPLE_CACHE); + cacheStatus->CacheEnableFlag = true; +#endif +} + +void flexspi_nor_enable_cache(flexspi_cache_status_t cacheStatus) +{ +#if (defined __CORTEX_M) && (__CORTEX_M == 7U) +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if (cacheStatus.DCacheEnableFlag) + { + /* Enable D cache. */ + SCB_EnableDCache(); + } +#endif /* __DCACHE_PRESENT */ + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (cacheStatus.ICacheEnableFlag) + { + /* Enable I cache. */ + SCB_EnableICache(); + } +#endif /* __ICACHE_PRESENT */ + +#elif (defined FSL_FEATURE_SOC_LMEM_COUNT) && (FSL_FEATURE_SOC_LMEM_COUNT != 0U) + if (cacheStatus.codeCacheEnableFlag) + { + /* Enable code cache. */ + L1CACHE_EnableCodeCache(); + } + + if (cacheStatus.systemCacheEnableFlag) + { + /* Enable system cache. */ + L1CACHE_EnableSystemCache(); + } +#elif (defined FSL_FEATURE_SOC_CACHE64_CTRL_COUNT) && (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT != 0U) + if (cacheStatus.CacheEnableFlag) + { + /* Enable cache. */ + CACHE64_EnableCache(EXAMPLE_CACHE); + } +#endif +} +#endif + +status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write enable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + if (enableOctal) + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI; + } + else + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + } + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + return status; +} + +status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue=0; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + if (enableOctal) + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI; + } + else + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS; + } + + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do + { + /* For flash targets, after doing erase/program, need to call flexspi_nor_wait_bus_busy to wait for the + operation finish, Use blocking way to read back the status instead of using DMA. The reason is that the called + DMA API calls memset which is placed in flash region, because the external flash is being erase/propgram, so + load instruction from external flash at this time may read back some invalid instructions. */ + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (FLASH_BUSY_STATUS_POL) + { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) + { + isBusy = true; + } + else + { + isBusy = false; + } + } + else + { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) + { + isBusy = false; + } + else + { + isBusy = true; + } + } + + } while (isBusy); + + return status; +} + +#if defined(FLASH_ENABLE_OCTAL_CMD) +status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base) +{ + flexspi_transfer_t flashXfer; + status_t status; + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_cache_status_t cacheStatus; + flexspi_nor_disable_cache(&cacheStatus); +#endif + + uint32_t writeValue = FLASH_ENABLE_OCTAL_CMD; + + /* Make sure external flash is not in busy status. */ + status = flexspi_nor_wait_bus_busy(base, false); + if (status != kStatus_Success) + { + return status; + } + + /* Write enable */ + status = flexspi_nor_write_enable(base, 0, false); + + if (status != kStatus_Success) + { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + if (status != kStatus_Success) + { + return status; + } + + status = flexspi_nor_wait_bus_busy(base, true); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(base); + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_nor_enable_cache(cacheStatus); +#endif + + return status; +} +#endif + +status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) +{ + status_t status; + flexspi_transfer_t flashXfer; + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_cache_status_t cacheStatus; + flexspi_nor_disable_cache(&cacheStatus); +#endif + + /* Write enable */ + status = flexspi_nor_write_enable(base, 0, true); + + if (status != kStatus_Success) + { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + + status = flexspi_nor_wait_bus_busy(base, true); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(base); + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_nor_enable_cache(cacheStatus); +#endif + + return status; +} + +status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src) +{ +#if defined(FLASH_ENABLE_OCTAL_CMD) + assert(((uint32_t)dstAddr & (0x1UL)) == 0UL); +#endif + + status_t status; + flexspi_transfer_t flashXfer; + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_cache_status_t cacheStatus; + flexspi_nor_disable_cache(&cacheStatus); +#endif + + /* Write neable */ + status = flexspi_nor_write_enable(base, dstAddr, true); + + if (status != kStatus_Success) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = dstAddr; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; +#ifdef BSP_USING_DMA + g_completionFlag = false; + status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); +#else + status = FLEXSPI_TransferBlocking(base, &flashXfer); +#endif + if (status != kStatus_Success) + { + return status; + } +#ifdef BSP_USING_DMA + /* Wait for transfer completed. */ + while (!g_completionFlag) + { + } +#endif + status = flexspi_nor_wait_bus_busy(base, true); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(base); + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + flexspi_nor_enable_cache(cacheStatus); +#endif + + return status; +} + +status_t flexspi_nor_read_data(FLEXSPI_Type *base, uint32_t startAddress, uint32_t *buffer, uint32_t length) +{ + status_t status; + flexspi_transfer_t flashXfer; + uint32_t readAddress = startAddress; + + /* Read page. */ + flashXfer.deviceAddress = readAddress; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ; + flashXfer.data = buffer; + flashXfer.dataSize = length; +#ifdef BSP_USING_DMA + g_completionFlag = false; + + status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + + /* Wait for transfer completed. */ + while (!g_completionFlag) + { + } +#else + status = FLEXSPI_TransferBlocking(base, &flashXfer); +#endif + return status; +} + +#if defined(__ICCARM__) +#pragma optimize = none +#endif +status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) +{ + /* Read manufacturer ID based on JEP106V spec, max continuation code table is 9, max manufacturer ID starts from + * 9 + 1. */ + uint8_t id[10] = {0x00U}; + flexspi_transfer_t flashXfer; + flashXfer.deviceAddress = 0; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID_OPI; + flashXfer.data = (uint32_t *)id; + flashXfer.dataSize = 10U; + + status_t status = FLEXSPI_TransferBlocking(base, &flashXfer); + + for (uint8_t i = 0x00U; i < 10U; i++) + { + if (0x7FU != id[i]) + { + *vendorId = (uint32_t)id[i]; + break; + } + } + + return status; +} + +status_t flexspi_nor_erase_chip(FLEXSPI_Type *base) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + status = flexspi_nor_write_enable(base, 0, true); + + if (status != kStatus_Success) + { + return status; + } + + flashXfer.deviceAddress = 0; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + + status = flexspi_nor_wait_bus_busy(base, true); + + return status; +} + +status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t length) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Flash program limits program size smaller than flash page size for one program command sequence. */ + assert(length <= FLASH_PAGE_SIZE); + + /* Make sure external flash is not in busy status. */ + status = flexspi_nor_wait_bus_busy(base, true); + if (status != kStatus_Success) + { + return status; + } + + /* Write enable */ + status = flexspi_nor_write_enable(base, dstAddr, true); + + if (status != kStatus_Success) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = dstAddr; + flashXfer.port = FLASH_PORT; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = length; +#ifdef BSP_USING_DMA + g_completionFlag = false; + + status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer); +#else + status = FLEXSPI_TransferBlocking(base, &flashXfer); +#endif + if (status != kStatus_Success) + { + return status; + } +#ifdef BSP_USING_DMA + /* Wait for transfer completed. */ + while (!g_completionFlag) + { + } +#endif + status = flexspi_nor_wait_bus_busy(base, true); + + /* Do software reset. */ +#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) && defined(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) && \ + defined(FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) + base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; + base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK); +#else + FLEXSPI_SoftwareReset(base); +#endif + + return status; +} +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h new file mode 100644 index 0000000000..f3e9c8e102 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-15 xjy198903 The first version for rt1170 + */ + +#ifndef FLEXSPI_PORT_H__ +#define FLEXSPI_PORT_H__ + +#include "fsl_cache.h" + +/* parameters for flexpsi peripheral */ +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI_ROOT_CLK (400000000U) /* serial root clk: 400MHz*/ +#define FLASH_SIZE (64 * 1024) /* device size 64*1024(KB) = 64MB */ +#define FLASH_PAGE_SIZE 256 +#define SECTOR_SIZE 0x1000 /* 4K */ + +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad + +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M +#define CLOCK_DIV 2U +#define CUSTOM_LUT_LENGTH 60U +#define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U) +#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) + +#define COMBINATION_MODE 0U +#define FREE_RUNNING_MODE 0U + +/* DMA related. */ +#define FLEXSPI_DMA (DMA4) +#define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx +#define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx +#define FLEXSPI_TX_DMA_CHANNEL 0U +#define FLEXSPI_RX_DMA_CHANNEL 2U + + +#define NOR_CMD_LUT_SEQ_IDX_READ 0 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 +#define NOR_CMD_LUT_SEQ_IDX_READID_OPI 3 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI 4 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 6 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 7 +#define NOR_CMD_LUT_SEQ_IDX_ENTEROPI 8 +/* NOTE: Workaround for debugger. + Must define AHB write FlexSPI sequence index to 9 to avoid debugger issue. + Debugger can attach to the CM33 core only when ROM executes to certain place. + At that point, AHB write FlexSPI sequence index is set to 9, but in LUT, the + command is not filled by ROM. If the debugger sets software breakpoint at flash + after reset/attachment, FlexSPI AHB write command will be triggered. It may + cause AHB bus hang if the command in LUT sequence index 9 is any read opeartion. + So we need to ensure at any time, the FlexSPI LUT sequence 9 for the flash must + be set to STOP command to avoid unexpected debugger behaivor. + */ +#define NOR_CMD_LUT_SEQ_IDX_WRITE 9 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI 10 + +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 +#define FLASH_ERROR_STATUS_MASK 0x0e + +/* + * If cache is enabled, this example should maintain the cache to make sure + * CPU core accesses the memory, not cache only. + */ +#define CACHE_MAINTAIN 1 + +/*${macro:end}*/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*${variable:start}*/ +#if (defined CACHE_MAINTAIN) && (CACHE_MAINTAIN == 1) +typedef struct _flexspi_cache_status +{ + volatile bool DCacheEnableFlag; + volatile bool ICacheEnableFlag; +} flexspi_cache_status_t; +#endif + + + + +#endif /* FLEXSPI_PORT_H__ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h index ef905ec632..84a578d54f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -106,6 +106,7 @@ #define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define RT_USING_CACHE #define RT_USING_HW_ATOMIC #define ARCH_USING_HW_ATOMIC_8 #define ARCH_USING_HW_ATOMIC_16 @@ -113,7 +114,7 @@ #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_FPU -#define ARCH_ARM_CORTEX_M33 +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -294,6 +295,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -327,6 +332,10 @@ /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -416,12 +425,16 @@ /* On-chip Peripheral Drivers */ +#define BSP_USING_DMA #define BSP_USING_LPUART #define BSP_USING_LPUART1 +#define BSP_USING_FLEXSPI +#define BSP_USING_FLEXSPI1 /* end of On-chip Peripheral Drivers */ /* Onboard Peripheral Drivers */ +#define BSP_USING_OSPI_FLASH /* end of Onboard Peripheral Drivers */ /* Board extended module Drivers */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c index 2fe2f2dced..d643c73f61 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c @@ -7,6 +7,7 @@ * Date Author Notes * 2022-09-14 xjy198903 the first version for 1170 * 2026-06-03 CoreBoxer support IMXRT1180-EVK + * 2026-07-03 Jasontek support hyperflash in IMXRT1180-EVK */ #include <rtthread.h> @@ -23,6 +24,22 @@ #include "flexspi_port.h" #include "fsl_flexspi.h" +#ifdef BSP_USING_DMA +#include "fsl_flexspi_edma.h" + +volatile bool g_completionFlag = false; +flexspi_edma_handle_t flexspiHandle; + +static void flexspi_callback(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData) +{ + /* Signal transfer success when received success status. */ + if (status == kStatus_Success) + { + g_completionFlag = true; + } +} +#endif + #ifndef COMBINATION_MODE #define COMBINATION_MODE 1U #endif @@ -53,7 +70,6 @@ static flexspi_device_config_t deviceconfig = { .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 0, }; - const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* 8bit mode */ [4 * ARD_SEQ_INDEX] = @@ -61,7 +77,11 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { }; #elif defined(SOC_IMXRT1180_SERIES) static flexspi_device_config_t deviceconfig = { +#ifndef BSP_USING_OSPI_FLASH .flexspiRootClk = 12000000, +#else + .flexspiRootClk = 200000000, +#endif .flashSize = FLASH_SIZE, .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, .CSInterval = 2, @@ -79,6 +99,7 @@ static flexspi_device_config_t deviceconfig = { }; const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { +#ifndef BSP_USING_OSPI_FLASH /* Normal read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, @@ -148,6 +169,68 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), +#else + /* OPI DDR read */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ + 0] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC), + [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x20), + [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), + + /* Read ID */ + [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F), + [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, + kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), + + /* Write Enable */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06), + + /* Erase Sector */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21), + [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0), + + /* Erase Chip */ + [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4), + [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0), + + /* Program */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, + kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04), + + /* Dummy write, do nothing when AHB write command is triggered. */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), + + /* Read status register using Octal DDR read */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, + kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), +#endif }; #else #error "Unsupported SOC for drv_flexspi" @@ -185,7 +268,7 @@ FLEXSPI_RAM_CODE static int rt_hw_imxrt_flexspi_init(void) s_flexspi_handle.base = FLEXSPI1_CONTROL_BASE; s_flexspi_handle.port = FLASH_PORT; s_flexspi_handle.ahb_base = FLEXSPI1_AHB_DATA_ADDRESS; - //Set root clk 80MHz + //Set root clk 80MHz for QSPI, 200MHz for OSPI flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV); #else base = FLEXSPI2_CONTROL_BASE; @@ -195,6 +278,30 @@ FLEXSPI_RAM_CODE static int rt_hw_imxrt_flexspi_init(void) flexspi_clock_init(kCLOCK_Root_Flexspi2, CLOCK_SRC, CLOCK_DIV); #endif +#ifdef BSP_USING_DMA + edma_config_t userConfig; + edma_handle_t dmaTxHandle; + edma_handle_t dmaRxHandle; + + /* EDMA init */ + /* + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableHaltOnError = true; + * userConfig.enableContinuousLinkMode = false; + * userConfig.enableDebugMode = false; + */ + EDMA_GetDefaultConfig(&userConfig); +#if defined(BOARD_GetEDMAConfig) + BOARD_GetEDMAConfig(userConfig); +#endif + EDMA_Init(FLEXSPI_DMA, &userConfig); + /* Set request */ + EDMA_SetChannelMux(FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL, FLEXSPI_TX_DMA_REQUEST_SOURCE); + EDMA_SetChannelMux(FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL, FLEXSPI_RX_DMA_REQUEST_SOURCE); + /* Create the EDMA channel handles */ + EDMA_CreateHandle(&dmaTxHandle, FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL); + EDMA_CreateHandle(&dmaRxHandle, FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL); +#endif /*Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); @@ -224,6 +331,11 @@ FLEXSPI_RAM_CODE static int rt_hw_imxrt_flexspi_init(void) /* Do software reset. */ FLEXSPI_SoftwareReset(base); +#ifdef BSP_USING_DMA + /* Create handle for flexspi. */ + FLEXSPI_TransferCreateHandleEDMA(FLEXSPI1_CONTROL_BASE, &flexspiHandle, flexspi_callback, NULL, &dmaTxHandle, + &dmaRxHandle); +#endif return 0; } @@ -232,6 +344,8 @@ INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init); #ifdef FLEXSPI_DEBUG #ifdef FINSH_USING_MSH +#ifndef BSP_USING_OSPI_FLASH + #define FLEXSPI_DATALEN 4U static rt_uint32_t send_buf[FLEXSPI_DATALEN] = {0x11223344, 0x55667788, 0x12345678, 0x9900aabb}; static uint32_t recv_buf[FLEXSPI_DATALEN]; @@ -262,8 +376,159 @@ static void flexspi_test(void) LOG_D("addr44 is 0x%x\n", recv_buf[2]); LOG_D("addr60 is 0x%x\n", recv_buf[3]); } + +#else + +#define EXAMPLE_SECTOR 20 +/******************************************************************************* + * Variables + ******************************************************************************/ +#ifdef BSP_USING_DMA +AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t s_nor_program_buffer[256], 4); +#else +static uint8_t s_nor_program_buffer[256]; +#endif +static uint8_t s_nor_read_buffer[256]; +extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); +extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src); +extern status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId); +extern status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base); + +/* read write hyper flase test */ +static void flexspi_test(void) +{ + uint32_t i = 0; + status_t status; + uint8_t vendorID = 0; +#ifdef BSP_USING_DMA + LOG_W("\r\nFLEXSPI example started! -- DMA mode\r\n"); +#else + LOG_W("\r\nFLEXSPI example started!\r\n"); +#endif +#if defined(FLASH_ENABLE_OCTAL_CMD) + /* Enter octal mode unless the FLASH boots in octal mode after reset */ + status = flexspi_nor_enable_octal_mode(FLEXSPI1_CONTROL_BASE); + if (status != kStatus_Success) + { + #ifdef BSP_USING_DMA + LOG_E("Enable octal mode failure ! -- DMA mode\r\n"); + #else + LOG_E("Enable octal mode failure !\r\n"); + #endif + return ; + } +#ifdef BSP_USING_DMA + LOG_W("Enabled octal mode. -- DMA mode\r\n"); +#else + LOG_W("Enabled octal mode.\r\n"); +#endif +#endif + + /* Get vendor ID. */ + status = flexspi_nor_get_vendor_id(FLEXSPI1_CONTROL_BASE, &vendorID); + if (status != kStatus_Success) + { + #ifdef BSP_USING_DMA + LOG_E("Get vendor id failure ! -- DMA mode\r\n"); + #else + LOG_E("Get vendor id failure !\r\n"); + #endif + return ; + } +#ifdef BSP_USING_DMA + LOG_W("Vendor ID: 0x%x -- DMA mode\r\n", vendorID); + /* Erase sectors. */ + LOG_W("Erasing Serial NOR over FlexSPI... -- DMA mode\r\n"); +#else + LOG_W("Vendor ID: 0x%x\r\n", vendorID); + /* Erase sectors. */ + LOG_W("Erasing Serial NOR over FlexSPI...\r\n"); +#endif + + status = flexspi_nor_flash_erase_sector(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE); + if (status != kStatus_Success) + { + #ifdef BSP_USING_DMA + LOG_E("Erase sector failure ! -- DMA mode\r\n"); + #else + LOG_E("Erase sector failure !\r\n"); + #endif + return ; + } + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + DCACHE_InvalidateByRange(FlexSPI1_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE, FLASH_PAGE_SIZE); +#endif + + memset(s_nor_program_buffer, 0xFFU, sizeof(s_nor_program_buffer)); + memcpy(s_nor_read_buffer, (void *)(FlexSPI1_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE), + sizeof(s_nor_read_buffer)); + + if (memcmp(s_nor_program_buffer, s_nor_read_buffer, sizeof(s_nor_program_buffer))) + { + #ifdef BSP_USING_DMA + LOG_E("Erase data - read out data value incorrect ! -- DMA mode\r\n "); + #else + LOG_E("Erase data - read out data value incorrect !\r\n "); + #endif + return ; + } + else + { + #ifdef BSP_USING_DMA + LOG_W("Erase data - successfully. -- DMA mode\r\n"); + #else + LOG_W("Erase data - successfully. \r\n"); + #endif + } + + for (i = 0; i < 0xFFU; i++) + { + s_nor_program_buffer[i] = i; + } + + status = + flexspi_nor_flash_page_program(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE, (void *)s_nor_program_buffer); + if (status != kStatus_Success) + { + #ifdef BSP_USING_DMA + LOG_E("Page program failure ! -- DMA mode\r\n"); + #else + LOG_E("Page program failure !\r\n"); + #endif + return ; + } + +#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN + DCACHE_InvalidateByRange(FlexSPI1_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE, FLASH_PAGE_SIZE); +#endif + + memcpy(s_nor_read_buffer, (void *)(FlexSPI1_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE), + sizeof(s_nor_read_buffer)); + + if (memcmp(s_nor_read_buffer, s_nor_program_buffer, sizeof(s_nor_program_buffer)) != 0) + { + #ifdef BSP_USING_DMA + LOG_E("Program data - read out data value incorrect ! -- DMA mode\r\n "); + #else + LOG_E("Program data - read out data value incorrect !\r\n "); + #endif + return ; + } + else + { + #ifdef BSP_USING_DMA + LOG_W("Program data - successfully. -- DMA mode\r\n"); + #else + LOG_W("Program data - successfully. \r\n"); + #endif + } + +} +#endif MSH_CMD_EXPORT(flexspi_test, flexspi test) #endif /* FLEXSPI_DEBUG */ #endif /* FINSH_USING_MSH */ #endif /* BSP_USING_FLEXSPI */ + diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c index 8f4f9b10be..3999b293f4 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,71 +36,120 @@ static struct rt_adc_device lpadc1_device; static struct rt_adc_device lpadc2_device; #endif -#if (defined(DEMO_LPADC_USE_HIGH_RESOLUTION) && DEMO_LPADC_USE_HIGH_RESOLUTION) -uint32_t g_LpadcResultShift = 0U; -#else -uint32_t g_LpadcResultShift = 3U; -#endif /* DEMO_LPADC_USE_HIGH_RESOLUTION */ +#if defined(BSP_LPADC1_USING_DMA) +#include "fsl_edma.h" + +volatile bool g_Transfer_Done = false; +AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = {0x0,0x0,0x0,0x0,0x0,0x0,0x0}; -static rt_err_t imxrt_hp_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +/* User callback function for EDMA transfer. */ +void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) { + if (transferDone) + { + g_Transfer_Done = true; + } +} +#endif + +static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ + ADC_Type *base; + /* channel check*/ + + if(channel < 4) return -RT_EINVAL; + + base = (ADC_Type *)(device->parent.user_data); + if( RT_TRUE == enabled ) + { + LPADC_Enable(base, true); + } else + { + LPADC_Enable(base, false); + } + return RT_EOK; } -static rt_err_t imxrt_hp_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { - LPADC1_BASE *base; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - base = (LPADC1_BASE *)(device->parent.user_data); + ADC_Type *base; + uint32_t data_mask=0xffffffff; +#if defined(BSP_LPADC1_USING_DMA) - //ADC_SetChannelConfig(base, 0, &adc_channel); - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.channelNumber = channel; -#if defined(DEMO_LPADC_USE_HIGH_RESOLUTION) && DEMO_LPADC_USE_HIGH_RESOLUTION - mLpadcCommandConfigStruct.conversionResolutionMode = kLPADC_ConversionResolutionHigh; -#endif /* DEMO_LPADC_USE_HIGH_RESOLUTION */ - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); +#else + uint8_t i=0; + uint32_t adc_result[7] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0}; /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */ + lpadc_conv_result_t mLpadcResultConfigStruct; +#endif - /* Set trigger configuration. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; - mLpadcTriggerConfigStruct.enableHardwareTrigger = false; - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + base = (ADC_Type *)(device->parent.user_data); LPADC_DoSoftwareTrigger(base, 1U); - +#if defined(BSP_LPADC1_USING_DMA) + extern edma_handle_t DMA4_CH0_Handle; + data_mask = 0xffff; + g_Transfer_Done = false; + EDMA_StartTransfer(&DMA4_CH0_Handle); + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } +#else + for(i=0;i<7;i++) + { #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U)) + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U)) #else - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + { + } + adc_result[i] = (mLpadcResultConfigStruct.convValue); + } +#endif + switch(channel) { + case 4: *value = adc_result[0] & data_mask; + break; + case 5: *value = adc_result[4] & data_mask; + break; + case 6: *value = adc_result[2] & data_mask; + break; + case 7: *value = adc_result[3] & data_mask; + break; + default: *value = 0; return -RT_EINVAL; } - *value = (mLpadcResultConfigStruct.convValue) >> g_LpadcResultShift; return RT_EOK; } +static rt_uint8_t imxrt_lp_adc_get_resolution(struct rt_adc_device *device) +{ + return 16; +} + +static rt_int16_t imxrt_lp_adc_get_vref(struct rt_adc_device *device) +{ + return 1800; +} + + static struct rt_adc_ops imxrt_lpadc_ops = { - .enabled = imxrt_hp_adc_enabled, - .convert = imxrt_hp_adc_convert, + .enabled = imxrt_lp_adc_enabled, + .convert = imxrt_lp_adc_convert, + .get_resolution = imxrt_lp_adc_get_resolution, + .get_vref = imxrt_lp_adc_get_vref, }; int rt_hw_adc_init(void) { int result = RT_EOK; - LPADC_GetDefaultConfig(&mLpadcConfigStruct); - mLpadcConfigStruct.enableAnalogPreliminary = true; -#if defined(kLPADC_ReferenceVoltageAlt1) - mLpadcConfigStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; -#endif /* DEMO_LPADC_VREF_SOURCE */ #if defined(BSP_USING_LPADC1) - LPADC_Init(LPADC1, &mLpadcConfigStruct); - result = rt_hw_adc_register(&lpadc1_device, "lpadc1", &imxrt_lpadc_ops, LPADC1); +/* on-chip peripherals are initialized in BOARD_InitPeripherals function of board.c */ + result = rt_hw_adc_register(&lpadc1_device, "lpadc1", &imxrt_lpadc_ops, ADC1); if (result != RT_EOK) { LOG_E("register lpadc1 device failed error code = %d\n", result); diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h index 2aca3ca8d8..d10a7e6e7e 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h @@ -12,6 +12,42 @@ #define DRV_ADC_H__ #include <rtdevice.h> + +/* drv adc channel definition */ +/* +#define RT_DRV_ADC_CH_A_0 0x01 +#define RT_DRV_ADC_CH_A_1 0x02 +#define RT_DRV_ADC_CH_A_2 0x04 +#define RT_DRV_ADC_CH_A_3 0x08 +#define RT_DRV_ADC_CH_A_4 0x10 +#define RT_DRV_ADC_CH_A_5 0x20 +#define RT_DRV_ADC_CH_A_6 0x40 +#define RT_DRV_ADC_CH_A_7 0x80 + +#define RT_DRV_ADC_CH_B_0 0x01 +#define RT_DRV_ADC_CH_B_1 0x02 +#define RT_DRV_ADC_CH_B_2 0x04 +#define RT_DRV_ADC_CH_B_3 0x08 +#define RT_DRV_ADC_CH_B_4 0x10 +#define RT_DRV_ADC_CH_B_5 0x20 +#define RT_DRV_ADC_CH_B_6 0x40 +#define RT_DRV_ADC_CH_B_7 0x80 +*/ + +/* +imxrt1180-nxp-evk arduino interface ADC channel configuration: +ADC1: +RT_DRV_ADC1_CH_A_4, RT_DRV_ADC1_CH_A_6, RT_DRV_ADC1_CH_A_7 +RT_DRV_ADC1_CH_B_5, RT_DRV_ADC1_CH_B_6, RT_DRV_ADC1_CH_B_7 + +ADC2: +RT_DRV_ADC1_CH_A_0, RT_DRV_ADC1_CH_B_0 + +IMPORTANT!! +Propose to change rt_adc_ops structure from rt_int8_t to rt_int16_t to enable side A and side B simultineously in same ADC !!! +*/ + + int rt_hw_adc_init(void); #endif /* DRV_ADC_H__ */ |
