diff options
| author | Fan YANG <[email protected]> | 2026-10-15 22:56:12 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2026-10-17 16:28:33 +0800 |
| commit | fc64f78669b42b35981f97c23c7e952832f3b48b (patch) | |
| tree | 8356bfed957b8ad84529e34ede28e6d65c975911 | |
| parent | 8d8dc96b67eee53af2841a8819364d52fbec39cb (diff) | |
[bsp][hpmicro] upgrade hpm_sdk to v1.13.0 and add hpm5100evk support
Sync the HPMicro BSPs with hpm_sdk v1.13.0 and add the HPM5100EVK
(HPM5151) board.
- add the hpm5100evk BSP (board/startup/applications/Kconfig/docs) and
register it in .github/ALL_BSP_COMPILE.json, bsp/README.md and the
HPMicro READMEs
- re-sync the 11 existing boards (board/startup/debug scripts/linker
scripts/applications) with hpm_sdk v1.13.0, keeping the RT-Thread
specific parts: clock_time based drv_timer, CXX wired into the scons
environment, SConscript outputs under build/, named Kconfig choices,
rt_hw_us_delay in board_delay_*, board local codec files
- sync the shared driver layer with hpm_sdk v1.13.0 (GPTMRv2/PTMR,
PUART, soft I2C/SPI and the remaining peripheral driver updates)
- select the hpm_sdk v1.13.0 online package (PKG_USING_HPM_SDK_V113)
- use -Og instead of -O0 for the debug builds and print floats with the
RT-Thread klibc implementation instead of newlib nano
- initialize the RT-Thread heap before the SDK console init: the SDK
console_init() calls setvbuf(), which allocates through the C library
malloc() and tripped RT_ASSERT() in rt_smem_alloc() on the boards
built with RT_USING_DEBUG
- keep only ram_rtt.ld/flash_rtt.ld per board, align the DLM origin to
4KB on hpm5300evk/hpm5301evklite (the unaligned origin made the
linker emit a file backed PT_LOAD for the RAM area, which broke
"program rtthread.elf"), and anchor the generated .bin at the flash
base address 0x80000000
- sync the hpm6750evk openocd debug scripts with the new style used by
the other boards (hpm_common.cfg/hpm_reset.cfg with arp_halt)
- keep the upstream synced board/startup/libraries trees of bsp/hpmicro out of the
changed-file cppcheck run (same policy as bsp/hpmicro/.clang-format-ignore): the
check runs without the hpm_sdk include paths, so it reports ATTR_PLACE_AT and the
linker script symbol arithmetic in c_startup() as errors
- give the hpmicro boards in the changed-file scons trigger list the RV32 toolchain
they need (RISC-V-GCC-RV32) and add the matching installation step to that
workflow: the entries used sourcery-arm, which only provides the ARM toolchain,
so those legs could not find riscv32-unknown-elf-gcc
- keep hpm5100evk's ram_rtt.ld identical to the hpm_sdk v1.13.0
reference: the .fast_ram sections belong in DLM there (the DLM has
enough headroom), and that also makes its RAM and flash layouts agree
- skip the dependency pre-check when cleaning (scons -c): it runs from
DoBuilding() unconditionally, so a clean request with packages/ not
fetched yet was aborted with exit code 1 instead of cleaning
- make the manual scons trigger workflow runnable: it aborted while still
downloading actions because actions/upload-artifact@v3 is deprecated,
and scons was not on PATH because ~/.env/env.sh was never sourced.
Install tools/requirements.txt and source the Env PATH script in the
build step, and use @main action versions, as bsp_buildings.yml does
- start the LED demo thread only when rt_thread_create() succeeded
Tested:
- 12 boards x {ram_debug, ram_release, flash_debug, flash_release}:
48/48 clean builds
- flash boot + msh on hpm5100evk, hpm5300evk, hpm5e00evk, hpm6200evk,
hpm6300evk, hpm6750evk, hpm6750evk2, hpm6750evkmini, hpm6800evk,
hpm6e00evk, hpm6p00evk (list device/timer, ps, free, reset, rt_kprintf
float formatting)
- re-ran .github/workflows/manual_trigger_scons_except_STM32_all.yml with
the matrix reduced to the three hpmicro rows: all three legs build and
scons --dist succeeds with no local workarounds
434 files changed, 23836 insertions, 16632 deletions
diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 090b7c0129..f0543b97ad 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -464,7 +464,8 @@ "hpmicro/hpm6800evk", "hpmicro/hpm6e00evk", "hpmicro/hpm6p00evk", - "hpmicro/hpm5e00evk" + "hpmicro/hpm5e00evk", + "hpmicro/hpm5100evk" ] }, { diff --git a/.github/membrowse-targets.json b/.github/membrowse-targets.json index 10c12b7aa5..a08a702836 100644 --- a/.github/membrowse-targets.json +++ b/.github/membrowse-targets.json @@ -194,6 +194,20 @@ ] }, { + "target_name": "hpmicro-hpm5100evk", + "toolchain": "riscv32-unknown-elf-multilib", + "bsp_path": "bsp/hpmicro/hpm5100evk", + "elf": "bsp/hpmicro/hpm5100evk/rtthread.elf", + "ld": "bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld", + "map_file": "", + "linker_vars": "", + "watch_paths": [ + "bsp/hpmicro/hpm5100evk", + "bsp/hpmicro/libraries", + "bsp/hpmicro/tools" + ] + }, + { "target_name": "xuantie-e901plus", "toolchain": "xuantie-elf-newlib", "bsp_path": "bsp/xuantie/smartl/e901plus", diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 85ab16cb49..cac5f842af 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -124,8 +124,9 @@ jobs: - {RTT_BSP_NAME: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l196"} - {RTT_BSP_NAME: "hifive1", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "hifive1"} #- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题 - - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"} - - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"} + - {RTT_BSP_NAME: "hpmicro_hpm5100evk", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm5100evk"} + - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm6750evk"} + - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "RISC-V-GCC-RV32", RTT_BSP: "hpmicro/hpm6750evkmini"} - {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"} - {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"} #- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持 @@ -294,7 +295,7 @@ jobs: steps: - uses: actions/checkout@main - name: Set up Python - uses: actions/setup-python@v3 + uses: actions/setup-python@main with: python-version: 3.8 @@ -305,9 +306,11 @@ jobs: wget https://raw.githubusercontent.com/RT-Thread/env/master/install_ubuntu.sh chmod 777 install_ubuntu.sh ./install_ubuntu.sh + pip install -r tools/requirements.txt git config --global http.postBuffer 524288000 echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV echo "RTT_CC=gcc" >> $GITHUB_ENV + echo "export PATH=~/.env/tools/scripts:$PATH" > ~/.env/env.sh - name: Install Arm ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }} @@ -344,6 +347,14 @@ jobs: /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV + - name: Install riscv32-unknown-elf ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'RISC-V-GCC-RV32' && success() }} + run: | + wget -q https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz + sudo tar zxf riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz -C /opt + /opt/riscv32-unknown-elf-newlib-multilib/bin/riscv32-unknown-elf-gcc --version + echo "RTT_EXEC_PATH=/opt/riscv32-unknown-elf-newlib-multilib/bin/" >> $GITHUB_ENV + - name: Install Riscv-none-embed ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }} run: | @@ -373,7 +384,7 @@ jobs: RTT_BSP: ${{ matrix.legs.RTT_BSP }} RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }} run: | - # source ~/.env/env.sh + source ~/.env/env.sh echo $RTT_BSP ls bsp/$RTT_BSP/Kconfig && scons -C bsp/$RTT_BSP --pyconfig-silent sed -i "s/# ${{ github.event.inputs.bsp_config }} is not set/${{ github.event.inputs.bsp_config }}=y/g" bsp/$RTT_BSP/.config @@ -386,7 +397,7 @@ jobs: cp bsp/$RTT_BSP/dist/project.zip ${{ github.workspace }}/$RTT_BSP/ ls bsp/$RTT_BSP/dist pwd - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@main if: ${{ github.event.inputs.dist_flag }} env: RTT_BSP: ${{ matrix.legs.RTT_BSP }} diff --git a/bsp/.clang-format-ignore b/bsp/.clang-format-ignore index 7286b8f79b..befc415a75 100644 --- a/bsp/.clang-format-ignore +++ b/bsp/.clang-format-ignore @@ -1 +1,2 @@ rtconfig.h +rtconfig_preinc.h diff --git a/bsp/README.md b/bsp/README.md index ac704da3f7..62c88b1c2e 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -763,6 +763,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | [hpm6800evk](hpmicro/hpm6800evk) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | | [hpm6e00evk](hpmicro/hpm6e00evk) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | | [hpm6p00evk](hpmicro/hpm6p00evk) | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [hpm5100evk](hpmicro/hpm5100evk) | ✅ | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | #### 🟢 K230 (RT-Smart) diff --git a/bsp/hpmicro/.clang-format-ignore b/bsp/hpmicro/.clang-format-ignore index 8d88b7152f..ee0d8d7fc6 100644 --- a/bsp/hpmicro/.clang-format-ignore +++ b/bsp/hpmicro/.clang-format-ignore @@ -1,3 +1,4 @@ # clang-format ignore file /**/startup/ -/libraries/hpm_sdk/ +/**/board/ +/libraries/ diff --git a/bsp/hpmicro/.gitignore b/bsp/hpmicro/.gitignore new file mode 100644 index 0000000000..f866a6c2e3 --- /dev/null +++ b/bsp/hpmicro/.gitignore @@ -0,0 +1,2 @@ +# HPMicro SDK is fetched as an RT-Thread package into the shared libraries dir +/libraries/hpm_sdk-*/ diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml new file mode 100644 index 0000000000..276544a249 --- /dev/null +++ b/bsp/hpmicro/.ignore_format.yml @@ -0,0 +1,36 @@ +# Exclude the files that are kept in sync with the upstream HPMicro sources +# (the all-in-one tree / hpm_sdk) from the changed-file checks, as already done +# for clang-format in .clang-format-ignore. +# +# tools/ci/cpp_check.py runs cppcheck with a minimal configuration (only +# '-I include -I thread/components/finsh'), so it cannot resolve the hpm_sdk +# macros used in these files (e.g. ATTR_PLACE_AT) and it reports the linker +# script symbol arithmetic in c_startup() as 'subtractPointers'; both are +# false positives for code that is not ours to restructure. + +dir_path: +- hpm5100evk/board +- hpm5100evk/startup +- hpm5300evk/board +- hpm5300evk/startup +- hpm5301evklite/board +- hpm5301evklite/startup +- hpm5e00evk/board +- hpm5e00evk/startup +- hpm6200evk/board +- hpm6200evk/startup +- hpm6300evk/board +- hpm6300evk/startup +- hpm6750evk/board +- hpm6750evk/startup +- hpm6750evk2/board +- hpm6750evk2/startup +- hpm6750evkmini/board +- hpm6750evkmini/startup +- hpm6800evk/board +- hpm6800evk/startup +- hpm6e00evk/board +- hpm6e00evk/startup +- hpm6p00evk/board +- hpm6p00evk/startup +- libraries diff --git a/bsp/hpmicro/README.md b/bsp/hpmicro/README.md index 5d21c2380e..bc8cbf1d96 100644 --- a/bsp/hpmicro/README.md +++ b/bsp/hpmicro/README.md @@ -33,6 +33,7 @@ Below is a comprehensive list of HPMicro BSPs currently supported: | hpm6800evk | HPM6800EVK | HPM6800 | Development board for HPM6800 series | | hpm6e00evk | HPM6E00EVK | HPM6E00 | Development board for HPM6E00 series | | hpm6p00evk | HPM6P00EVK | HPM6P00 | Development board for HPM6P00 series | +| hpm5100evk | HPM5100EVK | HPM5100 | Development board for HPM5100 series | ## Quick Start Guide @@ -120,7 +121,7 @@ Additional peripherals may be supported depending on the specific board: - HPM6E00EVK - HPM6P00EVK - HPM5E00EVK -- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK and HPM5E00EVK +- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK, HPM5E00EVK and HPM5100EVK - **SDIO**: Available on HPM6300EVK, HPM6750EVKMINI, HPM6750EVK, HPM6750EVK2 and HPM6800EVK - **Display/Audio**: Available on HPM6750EVK, HPM6800EVK, HPM6E00EVK，HPM6P00EVK @@ -153,6 +154,7 @@ Please refer to the individual BSP directories for detailed documentation: - `hpm6800evk/README.md` - `hpm6e00evk/README.md` - `hpm6p00evk/README.md` +- `hpm5100evk/README.md` ## Troubleshooting diff --git a/bsp/hpmicro/README_zh.md b/bsp/hpmicro/README_zh.md index ac006d2f92..a2115c6a55 100644 --- a/bsp/hpmicro/README_zh.md +++ b/bsp/hpmicro/README_zh.md @@ -33,6 +33,7 @@ | hpm6800evk | HPM6800EVK | HPM6800 | HPM6800 系列开发板 | | hpm6e00evk | HPM6E00EVK | HPM6E00 | HPM6E00 系列开发板 | | hpm6p00evk | HPM6P00EVK | HPM6P00 | HPM6P00 系列开发板 | +| hpm5100evk | HPM5100EVK | HPM5100 | HPM5100 系列开发板 | ## 快速开始指南 @@ -120,7 +121,7 @@ msh > - HPM6E00EVK - HPM6P00EVK - HPM5E00EVK -- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK 和HPM5E00EVK +- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK、HPM5E00EVK 和HPM5100EVK - **SDIO**：HPM6300EVK、HPM6750EVK 系列可用 - **显示/音频**：HPM6750EVK 系列可用 @@ -152,6 +153,7 @@ msh > - `hpm6800evk/README.md` - `hpm6e00evk/README.md` - `hpm6p00evk/README.md` +- `hpm5100evk/README.md` ## 故障排除 diff --git a/bsp/hpmicro/hpm5100evk/.config b/bsp/hpmicro/hpm5100evk/.config new file mode 100644 index 0000000000..aadef66475 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.config @@ -0,0 +1,1573 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50301 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y +# CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set +CONFIG_PKG_HPM_SDK_VER="v1.13.0" +# end of HPMicro SDK + +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_SERIES_HPM5100=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5100=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_PUART is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_GPTMRV2 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_OPAMP is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set +# end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) +# end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5100evk/.cproject b/bsp/hpmicro/hpm5100evk/.cproject new file mode 100644 index 0000000000..b7f94f01bb --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.cproject @@ -0,0 +1,227 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings /> + <extensions> + <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" /> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" /> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" /> + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" /> + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" /> + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" /> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactName="rtthread" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug"> + <folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094." name="/" resourcePath=""> + <toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1201710416" name="ARM Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.debug" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.244767666" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1055848773" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.501941135" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.dwarf2" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1696308067" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" useByScannerDiscovery="false" value="GNU Tools for ARM Embedded Processors" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.1558403188" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.749415257" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.2114153533" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1600865811" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" useByScannerDiscovery="false" value="arm-none-eabi-" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1109963929" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1040883831" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1678200391" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1171840296" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.342604837" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.898269225" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" useByScannerDiscovery="false" value="size" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2016398076" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" useByScannerDiscovery="false" value="make" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1606171496" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id.540792084" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id" useByScannerDiscovery="false" value="1287942917" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.430121817" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.none" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.966735324" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1381561249" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" useByScannerDiscovery="true" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.target.other.2041717463" name="Other target flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.target.other" useByScannerDiscovery="true" value="" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.1463655269" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated" /> + <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1798638225" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform" /> + <builder buildPath="${workspace_loc:/${ProjName}/Debug" cleanBuildTarget="clean2" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1736709688" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder" /> + <tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.1810966071" name="GNU ARM Cross Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1072524326" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.161242639" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" useByScannerDiscovery="true" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1521934876" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true" /> + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags.1325367962" name="Assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags" useByScannerDiscovery="false" valueType="stringList"> + <listOptionValue builtIn="false" value="-mimplicit-it=thumb" /> + </option> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.647856572" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" useByScannerDiscovery="false" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2" valueType="string" /> + <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1843333483" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input" /> + </tool> + <tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559" name="GNU ARM Cross C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.634882052" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="true"> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//.}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//applications}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//board}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/drivers}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/arch}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/debug_console}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/phy}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/smp_call}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/finsh}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/epoll}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/eventfd}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM5151}"" /> + </option> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -std=gnu11" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true"> + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> + </option> + <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input" /> + </tool> + <tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.869072473" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.1167322178" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart.351692886" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs.1009243715" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs.2016026082" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.923990336" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option defaultValue="true" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared.548869459" name="Shared (-shared)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared" useByScannerDiscovery="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.1818777301" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" useByScannerDiscovery="false"> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//board/linker_scripts/flash_rtt.ld}"" /> + </option> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs.1135656995" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs" useByScannerDiscovery="false"> + <listOptionValue builtIn="false" value="c " /> + <listOptionValue builtIn="false" value="m " /> + </option> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input"> + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> + <additionalInput kind="additionalinput" paths="$(LIBS)" /> + </inputType> + </tool> + <tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1601059928" name="GNU ARM Cross C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.437759352" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1101974459" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" useByScannerDiscovery="false" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref.2007675975" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.2105838438" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.934137837" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" useByScannerDiscovery="false" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.2118356996" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.1427884346" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.1433863653" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections.1387745410" name="Print removed sections (-Xlinker --print-gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip.1230158061" name="Omit all symbol information (-s)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap.1307581821" name="Print link map (-Xlinker --print-map)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat.960778920" name="Use float with nano printf (-u _printf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat.637205035" name="Use float with nano scanf (-u _scanf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> + <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input"> + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> + <additionalInput kind="additionalinput" paths="$(LIBS)" /> + </inputType> + </tool> + <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.506412204" name="GNU ARM Cross Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver" /> + <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1461589245" name="GNU ARM Cross Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1937707052" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated" /> + </tool> + <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.82359725" name="GNU ARM Cross Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.601724476" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.692505279" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.97345172" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1342893377" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1533725981" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean" /> + </tool> + <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1073550295" name="GNU ARM Cross Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.946451386" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format" useByScannerDiscovery="false" /> + </tool> + <tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1302177015" name="GNU ARM Cross C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler"> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.704468062" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.302877723" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="true"> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//.}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//applications}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//board}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/drivers}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/arch}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/debug_console}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/phy}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/smp_call}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/finsh}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/epoll}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/eventfd}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM5151}"" /> + </option> + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles"> + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> + </option> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> + <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input" /> + </tool> + </toolChain> + </folderInfo> + <sourceEntries> + <entry excluding="//dist/project|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon|//rt-thread/bsp/Vango|//rt-thread/bsp/acm32|//rt-thread/bsp/airm2m|//rt-thread/bsp/allwinner|//rt-thread/bsp/allwinner_tina|//rt-thread/bsp/amebaz|//rt-thread/bsp/apm32|//rt-thread/bsp/apollo2|//rt-thread/bsp/asm9260t|//rt-thread/bsp/at32|//rt-thread/bsp/at91|//rt-thread/bsp/avr32|//rt-thread/bsp/beaglebone|//rt-thread/bsp/bf533|//rt-thread/bsp/bluetrum|//rt-thread/bsp/bm3803|//rt-thread/bsp/bouffalo_lab|//rt-thread/bsp/ck802|//rt-thread/bsp/core-v-mcu|//rt-thread/bsp/cvitek|//rt-thread/bsp/dm365|//rt-thread/bsp/efm32|//rt-thread/bsp/essemi|//rt-thread/bsp/fm33lc026|//rt-thread/bsp/frdm-k64f|//rt-thread/bsp/ft2004|//rt-thread/bsp/ft32|//rt-thread/bsp/fujitsu|//rt-thread/bsp/gd32|//rt-thread/bsp/hc32|//rt-thread/bsp/hc32l136|//rt-thread/bsp/hc32l196|//rt-thread/bsp/hifive1|//rt-thread/bsp/hk32|//rt-thread/bsp/hpmicro/hpm5300evk|//rt-thread/bsp/hpmicro/hpm5301evklite|//rt-thread/bsp/hpmicro/hpm6200evk|//rt-thread/bsp/hpmicro/hpm6300evk|//rt-thread/bsp/hpmicro/hpm6750evk|//rt-thread/bsp/hpmicro/hpm6750evk2|//rt-thread/bsp/hpmicro/hpm6750evkmini|//rt-thread/bsp/hpmicro/hpm6800evk|//rt-thread/bsp/hpmicro/libraries/drivers/drv_adc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_can.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_dao.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet_phy.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_ewdt.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_hwtimer.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2c.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2s.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_lcd.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_mcan.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pdm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pwm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_rtc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_sdio.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_spi.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_uart_v2.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_usb.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_wdt.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/camera|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/codec|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/panel|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ppi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/sccb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/smbus|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/spi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151/hpm_trgm_soc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5100/HPM5151/toolchains|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/utils|//rt-thread/bsp/ht32|//rt-thread/bsp/juicevm|//rt-thread/bsp/k210|//rt-thread/bsp/k230|//rt-thread/bsp/lm3s8962|//rt-thread/bsp/lm3s9b9x|//rt-thread/bsp/lm4f232|//rt-thread/bsp/loongson|//rt-thread/bsp/m16c62p|//rt-thread/bsp/maxim|//rt-thread/bsp/microblaze|//rt-thread/bsp/microchip|//rt-thread/bsp/mini2440|//rt-thread/bsp/mini4020|//rt-thread/bsp/mipssim|//rt-thread/bsp/mm32|//rt-thread/bsp/mm32f103x|//rt-thread/bsp/mm32f327x|//rt-thread/bsp/mm32f526x|//rt-thread/bsp/mm32l07x|//rt-thread/bsp/mm32l3xx|//rt-thread/bsp/msp432e401y-LaunchPad|//rt-thread/bsp/n32|//rt-thread/bsp/n32g452xx|//rt-thread/bsp/nios_ii|//rt-thread/bsp/nrf5x|//rt-thread/bsp/nuclei|//rt-thread/bsp/nuvoton|//rt-thread/bsp/nv32f100x|//rt-thread/bsp/nxp|//rt-thread/bsp/phytium|//rt-thread/bsp/pic32ethernet|//rt-thread/bsp/qemu-vexpress-a9|//rt-thread/bsp/qemu-virt64-aarch64|//rt-thread/bsp/qemu-virt64-riscv|//rt-thread/bsp/raspberry-pi|//rt-thread/bsp/raspberry-pico|//rt-thread/bsp/renesas|//rt-thread/bsp/rm48x50|//rt-thread/bsp/rockchip|//rt-thread/bsp/rv32m1_vega|//rt-thread/bsp/rx|//rt-thread/bsp/sam7x|//rt-thread/bsp/samd21|//rt-thread/bsp/sep6200|//rt-thread/bsp/simulator|//rt-thread/bsp/smartfusion2|//rt-thread/bsp/sparkfun-redv|//rt-thread/bsp/stm32|//rt-thread/bsp/synopsys|//rt-thread/bsp/synwit|//rt-thread/bsp/tae32f5300|//rt-thread/bsp/taihu|//rt-thread/bsp/thead-smart|//rt-thread/bsp/ti|//rt-thread/bsp/tkm32F499|//rt-thread/bsp/tm4c123bsp|//rt-thread/bsp/tm4c129x|//rt-thread/bsp/tms320c6678|//rt-thread/bsp/upd70f3454|//rt-thread/bsp/w60x|//rt-thread/bsp/wch|//rt-thread/bsp/wh44b0|//rt-thread/bsp/x86|//rt-thread/bsp/xplorer4330|//rt-thread/bsp/yichip|//rt-thread/bsp/zynqmp-a53-dfzu2eg|//rt-thread/bsp/zynqmp-r5-axu4ev|//rt-thread/components/dfs/dfs_v1/filesystems/cromfs|//rt-thread/components/dfs/dfs_v1/filesystems/elmfat|//rt-thread/components/dfs/dfs_v1/filesystems/iso9660|//rt-thread/components/dfs/dfs_v1/filesystems/mqueue|//rt-thread/components/dfs/dfs_v1/filesystems/nfs|//rt-thread/components/dfs/dfs_v1/filesystems/ramfs|//rt-thread/components/dfs/dfs_v1/filesystems/romfs|//rt-thread/components/dfs/dfs_v1/filesystems/skeleton|//rt-thread/components/dfs/dfs_v1/filesystems/tmpfs|//rt-thread/components/dfs/dfs_v2|//rt-thread/components/drivers/ata|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/block|//rt-thread/components/drivers/can|//rt-thread/components/drivers/clk|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/mnt.c|//rt-thread/components/drivers/core/numa.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/core/power_domain.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/dma|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/iio|//rt-thread/components/drivers/ipc/completion_mp.c|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/led|//rt-thread/components/drivers/mailbox|//rt-thread/components/drivers/mfd|//rt-thread/components/drivers/misc|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/nvme|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/pci|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/phye|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pin/dev_pin_dm.c|//rt-thread/components/drivers/pin/dev_pin_ofw.c|//rt-thread/components/drivers/pinctrl|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/regulator|//rt-thread/components/drivers/reset|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/scsi|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/bypass.c|//rt-thread/components/drivers/serial/dev_serial_v2.c|//rt-thread/components/drivers/serial/serial_dm.c|//rt-thread/components/drivers/serial/serial_tty.c|//rt-thread/components/drivers/smp_call|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/thermal|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/mprotect|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/documentation|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v/common/atomic_riscv.c|//rt-thread/libcpu/risc-v/common64|//rt-thread/libcpu/risc-v/rv64|//rt-thread/libcpu/risc-v/t-head|//rt-thread/libcpu/risc-v/virt64|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu_mp.c|//rt-thread/src/klibc/rt_vsnprintf_std.c|//rt-thread/src/klibc/utest|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//startup/HPM5151/toolchains/gcc/vectors.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" /> + </sourceEntries> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings" /> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="qemu-vexpress-a9.ilg.gnuarmeclipse.managedbuild.cross.target.elf.860020518" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf" /> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" /> + <scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" /> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders" /> + <storageModule moduleId="refreshScope" versionNumber="2"> + <configuration configurationName="Debug"> + <resource resourceType="PROJECT" workspacePath="/blink_led" /> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets" /> + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"> + <doc-comment-owner id="org.eclipse.cdt.ui.doxygen"> + <path value="" /> + </doc-comment-owner> + </storageModule> +</cproject> diff --git a/bsp/hpmicro/hpm5100evk/.project b/bsp/hpmicro/hpm5100evk/.project new file mode 100644 index 0000000000..0d08d5512d --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.project @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>blink_led</name> + <comment /> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.rt-thread.studio.rttnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> +</projectDescription> diff --git a/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000..9f1acfcfba --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini b/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini new file mode 100644 index 0000000000..671d4a8a91 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration
+# Fri Apr 25 13:53:29 2025
+cfg_version=v3.0
+
+board_name=
+bsp_version=
+bsp_path=
+chip_name=
+project_base_rtt_bsp=true
+is_use_scons_build=true
+hardware_adapter=
+selected_rtt_version=latest
+board_base_nano_proj=false
+is_base_example_project=false
+example_name=
+project_type=rt-thread
+os_branch=master
+os_version=latest
+project_name=blink_led
+output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm5100evk
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/Kconfig b/bsp/hpmicro/hpm5100evk/Kconfig new file mode 100644 index 0000000000..73238d3a13 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hpmicro/hpm5100evk/README.md b/bsp/hpmicro/hpm5100evk/README.md new file mode 100644 index 0000000000..cfed70162b --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/README.md @@ -0,0 +1,115 @@ +# HPMicro HPM5100EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5100EVK development board. + +The document consists of the following parts: + +- HPM5100EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5100EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, motor control，etc. + + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| CAN | √ | | +| AUDIO | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| On-Board Debugger | √ | hslink-lite | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5100EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5100evk)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/README_zh.md b/bsp/hpmicro/hpm5100evk/README_zh.md new file mode 100644 index 0000000000..810322fbb9 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/README_zh.md @@ -0,0 +1,112 @@ +# 先楫 HPM5100EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5100EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5100EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM5100EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联和电机控制等应用。 + +开发板外观如下图所示： + + + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| 板载调试器 | √ | hslink-lite | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5100.cfg -f board\debug_scripts\openocd\boards\hpm5100evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5100EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5100evk)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/SConscript b/bsp/hpmicro/hpm5100evk/SConscript new file mode 100644 index 0000000000..606b65445b --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/SConscript @@ -0,0 +1,16 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5100evk/SConstruct b/bsp/hpmicro/hpm5100evk/SConstruct new file mode 100644 index 0000000000..c0ae22c1c2 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + if GetOption('clean'): + return + + need_update = True + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5100evk/applications/SConscript b/bsp/hpmicro/hpm5100evk/applications/SConscript new file mode 100644 index 0000000000..00bf6b8d8f --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/applications/SConscript @@ -0,0 +1,12 @@ +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/applications/main.c b/bsp/hpmicro/hpm5100evk/applications/main.c new file mode 100644 index 0000000000..ce90f2deff --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/applications/main.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } + + return 0; +} + +void thread_entry(void *arg) +{ + while (1) + { + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5100evk/board/Kconfig b/bsp/hpmicro/hpm5100evk/board/Kconfig new file mode 100644 index 0000000000..8844405bb4 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/Kconfig @@ -0,0 +1,740 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5100 + bool + select SOC_SERIES_HPM5100 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART0_DMA_PINGPONG_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 + endif + + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default y + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif + endif + + menuconfig BSP_USING_I2S + bool "Enable I2S" + default n + select RT_USING_I2S if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default n + if BSP_USING_I2S0 + config BSP_I2S0_USING_DMA + bool "Enable I2S0 DMA" + default n + config BSP_I2S0_IRQ_PRIORITY + int "I2S0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2S1 + bool "Enable I2S1" + default n + if BSP_USING_I2S1 + config BSP_I2S1_USING_DMA + bool "Enable I2S1 DMA" + default n + config BSP_I2S1_IRQ_PRIORITY + int "I2S1 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + + menuconfig BSP_USING_GPTMRV2 + bool "Enable GPTMR" + default n + select RT_USING_CLOCK_TIME if BSP_USING_GPTMRV2 + if BSP_USING_GPTMRV2 + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + if BSP_USING_ACMP + config BSP_USING_ACMP0 + bool "Enable ACMP0" + default n + config BSP_USING_ACMP1 + bool "Enable ACMP1" + default n + endif + + menuconfig BSP_USING_OPAMP + bool "Enable OPAMP (Operational Amplifier)" + default n + if BSP_USING_OPAMP + config BSP_USING_OPAMP0 + bool "Enable OPAMP0" + default n + config BSP_USING_OPAMP1 + bool "Enable OPAMP1" + default n + config BSP_USING_OPAMP2 + bool "Enable OPAMP2" + default n + config BSP_USING_OPAMP3 + bool "Enable OPAMP3" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + select RT_USING_CACHE + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + select RT_USING_CACHE + default n + endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default y + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5100evk/board/SConscript b/bsp/hpmicro/hpm5100evk/board/SConscript new file mode 100644 index 0000000000..aeb0cee8b2 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + fal_spi_flash_sfud_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D25', 'HPM5151'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/board/board.c b/bsp/hpmicro/hpm5100evk/board/board.c new file mode 100644 index 0000000000..d9515366de --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/board.c @@ -0,0 +1,666 @@ +/* + * Copyright (c) 2026 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmrv2_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" +#include <rtconfig.h> +#include <rthw.h> + + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */ + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma0, 0); + clock_add_to_group(clock_hdma1, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_ptpc, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up LDO voltage to 1175mv */ + pcfg_ldo1p1_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 360MHz, AHB to 180MHz. */ + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 2);; + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + + clock_update_core_clock(); +} + +/*============================================================================== + * RT-Thread peripheral pin dispatch wrappers + * These dispatch to the pinmux-generated init_xxx_pins() functions + *============================================================================*/ + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY07 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PGPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PGPIO_Y_07; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + init_uart0_pins(); + } else if (ptr == HPM_UART2) { + init_uart2_pins(); + } else if (ptr == HPM_UART3) { + init_uart3_pins(); + } +} + +hpm_stat_t init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + init_i2c0_pins(); + return status_success; + } else if (ptr == HPM_I2C1) { + init_i2c1_pins(); + return status_success; + } else if (ptr == HPM_I2C2) { + init_i2c2_pins(); + return status_success; + } + return status_invalid_argument; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN0) { + init_mcan0_pins(); + } +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb0_pins(); + } +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + init_spi3_pins(); + } else if (ptr == HPM_SPI0) { + init_spi_nor_flash_pins(); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + init_spi3_pins_with_gpio_as_cs(); + } else if (ptr == HPM_SPI0) { + init_spi_nor_flash_pins_with_gpio_as_cs(); + } +} + +void init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR0) { + if (as_comp) { + if (channel == 0) { + init_gptmr0_channel0_pin_as_output(); + } else if (channel == 1) { + init_gptmr0_channel1_pin_as_output(); + } else if (channel == 3) { + init_gptmr0_channel3_pin_as_output(); + } + } else { + init_gptmr0_channel0_pin_as_capture(); + } + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + init_pwm0_pins(); + } else if (ptr == HPM_PWM1) { + init_pwm1_pins(); + } else if (ptr == HPM_PWM2) { + init_pwm2_pins(); + } else if (ptr == HPM_PWM3) { + init_pwm3_pins(); + } +} + +void board_delay_us(uint32_t us) +{ + rt_hw_us_delay(us); +} + +void board_delay_ms(uint32_t ms) +{ + while (ms--) + { + rt_hw_us_delay(1000); + } +} + +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} +#endif + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + usb_phy_using_internal_vbus(ptr); + } +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + clock_add_to_group(clock_spi3, 0); + return clock_get_frequency(clock_spi3); + } else if (ptr == HPM_SPI0) { + clock_add_to_group(clock_spi0, 0); + return clock_get_frequency(clock_spi0); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { + /* Configure the ADC clock from AHB */ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk2, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { + /* Configure the ADC clock from AHB */ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk2, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + +uint32_t board_init_dac_clock(void *ptr, bool clk_src_ahb) +{ + (void)ptr; + (void)clk_src_ahb; + return 0; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } + return freq; +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_enable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_init_dac_pins(void *ptr) +{ + (void)ptr; +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART2) { + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } + + return freq; +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2c_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else { + ; + } + + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +void board_init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + +uint32_t board_init_gptmr_clock(GPTMRV2_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} diff --git a/bsp/hpmicro/hpm5100evk/board/board.h b/bsp/hpmicro/hpm5100evk/board/board.h new file mode 100644 index 0000000000..71ca2bea1e --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/board.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include <stdio.h> +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5100evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP0 +#define BOARD_ACMP_CLK clock_acmp0 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN0 +#define BOARD_ACMP_IRQ IRQn_ACMP0_0 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_1 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_DMA0 HPM_HDMA0 +#define BOARD_APP_DMA1 HPM_HDMA1 +#define BOARD_APP_DMA0_IRQ IRQn_HDMA0 +#define BOARD_APP_DMA1_IRQ IRQn_HDMA1 +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA0 +#define TEST_DMA_IRQ IRQn_HDMA0 + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX +#endif + +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PC14 + +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 /* need to match UART instance */ +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR1 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr1 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 + +/* uart lin sample section */ +#define BOARD_UART_LIN HPM_UART3 +#define BOARD_UART_LIN_IRQ IRQn_UART3 +#define BOARD_UART_LIN_CLK_NAME clock_uart3 +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (0U) /* PC00 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C1 +#define BOARD_APP_I2C_IRQ IRQn_I2C1 +#define BOARD_APP_I2C_CLK_NAME clock_i2c1 +#define BOARD_APP_I2C_DMA HPM_HDMA0 +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 18 +#define BOARD_LED_GPIO_NAME "PA18" + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 15 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A +#define BOARD_BUTTON_PRESSED_VALUE 0 + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI3 +#define BOARD_APP_SPI_CLK_NAME clock_spi3 +#define BOARD_APP_SPI_IRQ IRQn_SPI3 +#define BOARD_APP_SPI_SCLK_FREQ (10000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PC06 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRIGO_8 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* MCAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN0 +#define BOARD_APP_CAN_IRQn IRQn_MCAN0 + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR0) +#define BOARD_CALLBACK_TIMER_CH 3 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0) + +/* APP PWM */ +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM HPM_PWM3 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm3 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_PWM_IRQ IRQn_PWM3 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM3_SYNCI +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM3_TRIGO_8 + +/* moto */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/* OPAMP */ +#define BOARD_APP_OPAMP HPM_OPAMP3 +#define BOARD_APP_OPAMP_CLOCK clock_opa3 +#define BOARD_APP_OPAMP_INP_PAD inp_pad_vip1 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb(USB_Type *ptr); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_init_adc16_pins(void); +void board_init_acmp_pins(void); +void board_init_acmp_clock(ACMP_Type *ptr); +void board_init_can(MCAN_Type *ptr); +void board_init_rgb_pwm_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_dac_pins(void *ptr); +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); +void board_init_pmp(void); +uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_adc_qeiv2_pins(void); +void board_init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); +uint32_t board_init_gptmr_clock(GPTMRV2_Type *ptr); + +/* Pin dispatch wrappers (used by RT-Thread drivers) */ +void init_pwm_pins(PWM_Type *ptr); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); +void init_can_pins(MCAN_Type *ptr); +void init_usb_pins(USB_Type *ptr); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_channel_pin(GPTMRV2_Type *ptr, uint32_t channel, bool as_comp); +uint32_t board_init_spi_clock(SPI_Type *ptr); +#ifdef __cplusplus +} +#endif + +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg new file mode 100644 index 0000000000..f46beeb8eb --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/boards/hpm5100evk.cfg @@ -0,0 +1,67 @@ +# Copyright (c) 2026 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF00E0000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF00E0000 0x5 0x1000 + +proc init_clock {} { + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..d8b53cc006 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,17 @@ +# Copyright (c) 2021-2026 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +# Transport selection, defaults to jtag +# Override with e.g.: -c "set TRANSPORT cjtag" BEFORE -f options +if { ![info exists TRANSPORT] } { + set TRANSPORT jtag +} +transport select $TRANSPORT + +reset_config srst_only diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/soc/hpm5300.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm5100.cfg index c57a36d017..667aa1ae30 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/soc/hpm5300.cfg +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm5100.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm5301 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5151 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5100evk/board/fal_cfg.h b/bsp/hpmicro/hpm5100evk/board/fal_cfg.h new file mode 100644 index 0000000000..07bb0c9e53 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_cfg.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include <rtconfig.h> +#include <board.h> + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x100000UL + +#define SPI_NOR_FLASH_DEV_NAME "spi_norflash0" + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +#if defined(RT_USING_SFUD) && defined(BSP_USING_SPI) +extern struct fal_flash_dev spi_nor_flash0; +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ + &spi_nor_flash0, \ +} +#else +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +#endif + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +// #ifdef (BSP_USING_SPI) && defined(RT_USING_SFUD) && +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "app", SPI_NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", SPI_NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c b/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c new file mode 100644 index 0000000000..6960ab7f67 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include <rtthread.h> +#include <rthw.h> +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c b/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c new file mode 100644 index 0000000000..7eb0b417de --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/fal_spi_flash_sfud_port.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2026-07-02 hpmicro First implementation + * + */ +#include <rtconfig.h> +#if defined(RT_USING_SFUD) && defined(BSP_USING_SPI) && defined(RT_USING_FAL) +#include <fal.h> +#include <sfud.h> +#include <dev_spi_flash_sfud.h> + +static int init(void); +static int read(long offset, rt_uint8_t *buf, rt_size_t size); +static int write(long offset, const rt_uint8_t *buf, rt_size_t size); +static int erase(long offset, rt_size_t size); + +static sfud_flash_t sfud_dev = NULL; +struct fal_flash_dev spi_nor_flash0 = +{ + .name = SPI_NOR_FLASH_DEV_NAME, + .addr = 0, + .len = 16 * 1024 * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +static int init(void) +{ + +#ifdef RT_USING_SFUD + /* RT-Thread RTOS platform */ + sfud_dev = rt_sfud_flash_find_by_dev_name(SPI_NOR_FLASH_DEV_NAME); +#endif + + if (NULL == sfud_dev) + { + return -1; + } + + /* update the flash chip information */ + spi_nor_flash0.blk_size = sfud_dev->chip.erase_gran; + spi_nor_flash0.len = sfud_dev->chip.capacity; + + return 0; +} + +static int read(long offset, rt_uint8_t *buf, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + sfud_read(sfud_dev, spi_nor_flash0.addr + offset, size, buf); + + return size; +} + +static int write(long offset, const rt_uint8_t *buf, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + if (sfud_write(sfud_dev, spi_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +static int erase(long offset, rt_size_t size) +{ + RT_ASSERT(sfud_dev); + RT_ASSERT(sfud_dev->init_ok); + if (sfud_erase(sfud_dev, spi_nor_flash0.addr + offset, size) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +#endif
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld index 366923d61a..45bbaf5a2d 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld +++ b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,24 +1,20 @@ /* - * Copyright 2021-2025 HPMicro + * Copyright 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K - AXI_SRAM (wx) : ORIGIN = 0x01090000, LENGTH = 176K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -29,6 +25,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -53,7 +58,6 @@ SECTIONS __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(16); __vector_ram_end__ = .; } > ILM @@ -84,6 +88,9 @@ SECTIONS KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + . = ALIGN(16); __ramfunc_end__ = .; } > ILM @@ -171,10 +178,10 @@ SECTIONS .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) - } > ILM + } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; KEEP(*(.fast_ram.init)) @@ -183,19 +190,13 @@ SECTIONS . = ALIGN(8); } > DLM - .bss(NOLOAD) : { + .fast_ram.bss (NOLOAD) : { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: the .tbss and .tdata section should be adjacent */ @@ -274,18 +275,32 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; - } > AXI_SRAM - + } > DLM .stack(NOLOAD) : { . = ALIGN(8); @@ -297,14 +312,14 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .noncacheable.bss (NOLOAD) : { . = ALIGN(8); @@ -316,15 +331,9 @@ SECTIONS KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - } diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/ram_rtt.ld index 7b04b9be32..e2e457c583 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm5100evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,23 +1,18 @@ /* - * Copyright 2021-2025 HPMicro + * Copyright 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k } SECTIONS @@ -25,14 +20,14 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > AXI_SRAM + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > AXI_SRAM + } > ILM .text : { . = ALIGN(8); @@ -91,33 +86,37 @@ SECTIONS __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > AXI_SRAM + + } > ILM .rel : { KEEP(*(.rel*)) - } > AXI_SRAM + } > DLM .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: .tbss and .tdata should be adjacent */ @@ -125,6 +124,7 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; @@ -137,6 +137,7 @@ SECTIONS __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM @@ -188,7 +189,6 @@ SECTIONS KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) - . = ALIGN(8); __data_end__ = .; PROVIDE (__edata = .); @@ -201,18 +201,51 @@ SECTIONS . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) + *(.fast.*) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > ILM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM + } > DLM .noncacheable.bss (NOLOAD) : { . = ALIGN(8); @@ -224,33 +257,9 @@ SECTIONS KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + } > DLM - .ahb_sram (NOLOAD) : { + .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > DLM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM } diff --git a/bsp/hpmicro/hpm5100evk/board/pinmux.c b/bsp/hpmicro/hpm5100evk/board/pinmux.c new file mode 100644 index 0000000000..8c372161f5 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/pinmux.c @@ -0,0 +1,345 @@ + +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * + * Automatically generated by HPM Pinmux Tool + * + * + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + */ + +#include "pinmux.h" +#include "board.h" +#include "hpm_trgm_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_gpiom_drv.h" + + +void init_uart0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; +} + +void init_uart2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART2_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; + + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART2_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; +} + +void init_uart3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_UART3_RXD; + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_UART3_TXD; +} + +void init_uart3_pin_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_GPIO_C_05; + HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_GPIO_C_00; + HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_i2c0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_IOC->PAD[IOC_PAD_PY01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_IOC->PAD[IOC_PAD_PY00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2c1_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03; + HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_I2C1_SDA; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2c2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA23].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(0) | IOC_PAD_PAD_CTL_OD_SET(1); + + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_I2C2_SDA; + HPM_IOC->PAD[IOC_PAD_PA22].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(0) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_i2s0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2S0_BCLK; + + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2S0_FCLK; + + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_I2S0_MCLK; + + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2S0_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_I2S0_TXD_0; +} + +void init_spi3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_SPI3_CS_0; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_spi3_pins_with_gpio_as_cs(void) +{ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPIO_C_06; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(7); + + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_gptmr0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_GPTMR0_CAPT_0; + + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_GPTMR0_COMP_0; + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPTMR0_COMP_1; + + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPTMR0_COMP_3; +} + +void init_gpio_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); +} + +void init_butn_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); +} + +void init_acmp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PWM0_P_6; + + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PWM0_P_5; +} + +void init_pwm1_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PWM1_P_6; + + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PWM1_P_7; +} + +void init_pwm2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PWM2_P_1; + + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_PWM2_P_5; +} + +void init_pwm3_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_PWM3_P_0; + + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_PWM3_P_1; + + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM3_P_4; + + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM3_P_5; + + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM3_P_6; + + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM3_P_7; +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_diff_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_USB0_ID; + + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_USB0_OC; + + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_USB0_PWR; +} + +void init_mcan0_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_MCAN0_RXD; + + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_MCAN0_TXD; +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_GPIO_A_18; +} + +void init_led_pins_as_pwm(void) +{ +} + +void init_opamp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_GPIO_C_14; + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_gptmr0_channel0_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_GPTMR0_COMP_0; +} + +void init_gptmr0_channel1_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPTMR0_COMP_1; +} + +void init_gptmr0_channel3_pin_as_output(void) +{ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPTMR0_COMP_3; +} + +void init_gptmr0_channel0_pin_as_capture(void) +{ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_GPTMR0_CAPT_0; +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_SOC_REF1; +} + +void init_brownout_indicate_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_GPIO_A_27; +} + +void init_trgm_gptmr0_cap2_invert_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_TRGM_P_02; + + trgm_output_t trgm0_io_config0 = {0}; + trgm0_io_config0.invert = 1; + trgm0_io_config0.type = trgm_output_same_as_input; + trgm0_io_config0.input = HPM_TRGM0_INPUT_SRC_TRGM0_P02; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2, &trgm0_io_config0); +} + +void init_spi_nor_flash_pins_with_gpio_as_cs(void) +{ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SPI0_DAT2; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SPI0_DAT3; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_SPI0_MISO; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_SPI0_MOSI; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_SPI0_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_GPIO_A_11; + + gpiom_set_pin_controller(HPM_GPIOM, GPIOM_ASSIGN_GPIOA, 11, gpiom_soc_gpio0); + gpio_set_pin_output(HPM_GPIO0, GPIO_OE_GPIOA, 11); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 11, 1); +} + +void init_spi_nor_flash_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SPI0_DAT2; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SPI0_DAT3; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_SPI0_MISO; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_SPI0_MOSI; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_SPI0_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3); + + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_SPI0_CS_0; +} diff --git a/bsp/hpmicro/hpm5100evk/board/pinmux.h b/bsp/hpmicro/hpm5100evk/board/pinmux.h new file mode 100644 index 0000000000..496d97f2e6 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/pinmux.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * + * Automatically generated by HPM Pinmux Tool + * + * + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +void init_uart0_pins(void); +void init_uart2_pins(void); +void init_uart3_pins(void); +void init_uart3_pin_as_gpio(void); +void init_i2c0_pins(void); +void init_i2c1_pins(void); +void init_i2c2_pins(void); +void init_i2s0_pins(void); +void init_spi3_pins(void); +void init_spi3_pins_with_gpio_as_cs(void); +void init_gptmr0_pins(void); +void init_gpio_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm0_pins(void); +void init_pwm1_pins(void); +void init_pwm2_pins(void); +void init_pwm3_pins(void); +void init_adc_pins(void); +void init_adc16_diff_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_usb0_pins(void); +void init_mcan0_pins(void); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_opamp_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr0_channel0_pin_as_output(void); +void init_gptmr0_channel1_pin_as_output(void); +void init_gptmr0_channel3_pin_as_output(void); +void init_gptmr0_channel0_pin_as_capture(void); +void init_clk_ref_pin(void); +void init_brownout_indicate_pin(void); +void init_trgm_gptmr0_cap2_invert_pins(void); +void init_spi_nor_flash_pins(void); +void init_spi_nor_flash_pins_with_gpio_as_cs(void); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5100evk/board/rtt_board.c b/bsp/hpmicro/hpm5100evk/board/rtt_board.c new file mode 100644 index 0000000000..412a10747f --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/rtt_board.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include <rthw.h> +#include <rtthread.h> +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Configure the USB pins*/ + board_init_usb(HPM_USB0); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + board_init_led_pins(); + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb(HPM_USB0); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE |= (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk0 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk0 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_pwm2, 0); + freq = clock_get_frequency(clock_pwm2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_pwm3, 0); + freq = clock_get_frequency(clock_pwm3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/board/rtt_board.h b/bsp/hpmicro/hpm5100evk/board/rtt_board.h new file mode 100644 index 0000000000..39e627cc8d --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/board/rtt_board.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include "board.h" + +/* gpio section */ +#define APP_LED0 (0U) +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOA +#define APP_LED0_GPIO_PIN 18 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm3" +#define BOARD_PWM_CHANNEL (0U) + +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + +#define IRQn_PendSV IRQn_DEBUG0 + +/* CAN section */ +#define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (1U) + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5100evk/figures/board.png b/bsp/hpmicro/hpm5100evk/figures/board.png Binary files differnew file mode 100644 index 0000000000..6783e4efb6 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/figures/board.png diff --git a/bsp/hpmicro/hpm5100evk/makefile.targets b/bsp/hpmicro/hpm5100evk/makefile.targets new file mode 100644 index 0000000000..8469d7d2aa --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/rtconfig.h b/bsp/hpmicro/hpm5100evk/rtconfig.h new file mode 100644 index 0000000000..4ade257d72 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig.h @@ -0,0 +1,475 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50301 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_V113 +/* end of HPMicro SDK */ + +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_SERIES_HPM5100 + +/* Hardware Drivers Config */ + +#define SOC_HPM5100 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 +/* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ +/* end of Hardware Drivers Config */ + +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + +#endif diff --git a/bsp/hpmicro/hpm5100evk/rtconfig.py b/bsp/hpmicro/hpm5100evk/rtconfig.py new file mode 100644 index 0000000000..5febf5ae4b --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig.py @@ -0,0 +1,131 @@ +# Copyright 2021-2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +SOC_FAMILY='HPM5100' +CHIP_NAME='HPM5151' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + elif RTT_EXEC_PATH: + EXEC_PATH = RTT_EXEC_PATH + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) + +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -Og' + LFLAGS += ' -Og' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -Og' + LFLAGS += ' -Og' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h new file mode 100644 index 0000000000..4de2806b54 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/rtconfig_preinc.h @@ -0,0 +1,21 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5151 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 59 +#define RT_HW_ISR_NUM HPM_SOC_ISR_NUM +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript b/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript new file mode 100644 index 0000000000..7ade8d38e4 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c b/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c new file mode 100644 index 0000000000..78705526d8 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/startup.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include <rtthread.h> + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ +#ifndef __SES_RISCV + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } +#endif +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + +#ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S new file mode 100644 index 0000000000..fa7e7f9c1c --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + .section .text.entry, "ax" + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S new file mode 100644 index 0000000000..4774dbd092 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/start.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include <rtconfig.h> + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..5703e22330 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/toolchains/gcc/vectors.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c b/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c new file mode 100644 index 0000000000..470b3fe266 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/HPM5151/trap.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include <rtthread.h> +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +}
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5100evk/startup/SConscript b/bsp/hpmicro/hpm5100evk/startup/SConscript new file mode 100644 index 0000000000..11a9d203d4 --- /dev/null +++ b/bsp/hpmicro/hpm5100evk/startup/SConscript @@ -0,0 +1,12 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) + +Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/.config b/bsp/hpmicro/hpm5300evk/.config index da0ebf1b1f..81fe5184e5 100644 --- a/bsp/hpmicro/hpm5300evk/.config +++ b/bsp/hpmicro/hpm5300evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -177,7 +187,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -236,11 +246,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -261,10 +271,10 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -457,6 +467,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -572,6 +583,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -631,6 +643,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -779,6 +793,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -812,7 +828,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -891,12 +921,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -904,6 +941,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -983,6 +1037,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1037,6 +1092,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1087,6 +1143,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1104,6 +1161,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1161,6 +1221,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1186,6 +1248,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1425,12 +1488,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5300_SERIES=y +CONFIG_SOC_SERIES_HPM5300=y # # Hardware Drivers Config # -CONFIG_SOC_HPM5300=y +CONFIG_SOC_HPM5000=y # # On-chip Peripheral Drivers @@ -1442,12 +1505,14 @@ CONFIG_BSP_USING_UART0=y CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set @@ -1457,5 +1522,60 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_OPAMP is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEO is not set +# CONFIG_BSP_USING_RDC is not set +# CONFIG_BSP_USING_SEI is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_MMC is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5300evk/README.md b/bsp/hpmicro/hpm5300evk/README.md index 4e6ad210a6..b51709900c 100644 --- a/bsp/hpmicro/hpm5300evk/README.md +++ b/bsp/hpmicro/hpm5300evk/README.md @@ -71,7 +71,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -79,7 +79,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm5300evk/README_zh.md b/bsp/hpmicro/hpm5300evk/README_zh.md index 2da65d7f9d..29d4fb396e 100644 --- a/bsp/hpmicro/hpm5300evk/README_zh.md +++ b/bsp/hpmicro/hpm5300evk/README_zh.md @@ -71,14 +71,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\probes\ft2232.cfg -f board\debug_scripts\soc\hpm5300.cfg -f board\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\probes\ft2232.cfg -f board\debug_scripts\soc\hpm5300.cfg -f board\debug_scripts\boards\hpm5300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5300evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm5300evk/SConscript b/bsp/hpmicro/hpm5300evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm5300evk/SConscript +++ b/bsp/hpmicro/hpm5300evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct index 601a33ec91..de5155656d 100644 --- a/bsp/hpmicro/hpm5300evk/SConstruct +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -76,6 +76,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5300evk/applications/SConscript b/bsp/hpmicro/hpm5300evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm5300evk/applications/SConscript +++ b/bsp/hpmicro/hpm5300evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm5300evk/applications/main.c b/bsp/hpmicro/hpm5300evk/applications/main.c index 0bbf637038..98ea3be7a3 100644 --- a/bsp/hpmicro/hpm5300evk/applications/main.c +++ b/bsp/hpmicro/hpm5300evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig index ba0d903c26..5763d1a2b4 100644 --- a/bsp/hpmicro/hpm5300evk/board/Kconfig +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5300 +config SOC_HPM5000 bool - select SOC_HPM5300_SERIES + select SOC_SERIES_HPM5300 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -51,6 +51,43 @@ menu "On-chip Peripheral Drivers" int "UART0 Interrupt Priority" range 1 7 default 1 + config BSP_UART0_DMA_PINGPONG_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -78,6 +115,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -105,6 +147,11 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" @@ -132,6 +179,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -159,6 +211,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -186,6 +243,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -209,6 +271,30 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif @@ -228,7 +314,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -236,7 +322,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -258,7 +344,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -266,7 +352,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -288,7 +374,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -296,7 +382,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -318,7 +404,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -326,7 +412,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -381,6 +467,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -446,7 +541,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWM + select RT_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -521,7 +616,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -535,5 +630,338 @@ menu "On-chip Peripheral Drivers" default n endif endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_OPAMP + bool "Enable OPAMP (Operational Amplifier)" + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + + menuconfig BSP_USING_QEIV2 + bool "Enable QEIV2 (Quadrature Encoder Interface V2)" + default n + + menuconfig BSP_USING_QEO + bool "Enable QEO (Quadrature Encoder Output)" + default n + + menuconfig BSP_USING_RDC + bool "Enable RDC (Resolver to Digital Converter)" + default n + + menuconfig BSP_USING_SEI + bool "Enable SEI (Synchronous Encoder Interface)" + default n + + menuconfig BSP_USING_PLB + bool "Enable PLB" + default n + + menuconfig BSP_USING_MMC + bool "Enable MMC (Motor Control Module)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Maichine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + endmenu diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/boards/hpm5300evk.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg index 7d495f5b38..7bb2e8c773 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/boards/hpm5300evk.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg @@ -46,27 +46,15 @@ # - flash ctrl index: 0xF3000000 # - base address: 0x80000000 # - flash size: 0x2000000 -# - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg index 0aa1eed3da..0aa1eed3da 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/cmsis_dap.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft2232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg index 782edbcf50..782edbcf50 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft2232.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg index e2c01a2d78..e2c01a2d78 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/ft232.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/jlink.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg index 5d565c0ecc..5d565c0ecc 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/jlink.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg index a9421a8387..a9421a8387 100644 --- a/bsp/hpmicro/hpm5300evk/board/debug_scripts/probes/nds_aice_micro.cfg +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg new file mode 100644 index 0000000000..935b5e87dd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2023,2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5361 +} +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld index 12af13362e..6591432556 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -26,6 +26,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -165,11 +174,19 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + /* The first 0x300 bytes of DLM are reserved; keep them as an explicit NOLOAD + * placeholder. This also keeps the DLM region 4KB aligned so that the linker does + * not emit an extra file-backed PT_LOAD (which made "program rtthread.elf" fail). + */ + .dlm_reserved (NOLOAD) : { + . = . + 0x300; + } > DLM + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -179,6 +196,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); @@ -256,7 +282,7 @@ SECTIONS PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -295,7 +321,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld index 26d5785602..6753ecbafd 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld @@ -112,6 +112,16 @@ SECTIONS . = ALIGN(8); } > ILM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > ILM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -213,7 +223,7 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > DLM + } > ILM __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.c b/bsp/hpmicro/hpm5300evk/board/pinmux.c index 268926772e..f4e655a732 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.c @@ -66,7 +66,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -79,8 +79,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else { - ; + return status_invalid_argument; } + return status_success; } void init_gpio_pins(void) diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.h b/bsp/hpmicro/hpm5300evk/board/pinmux.h index 738593a2b6..aaa5b391cf 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.c b/bsp/hpmicro/hpm5300evk/board/rtt_board.c index e5b5d95897..d4cd474e10 100644 --- a/bsp/hpmicro/hpm5300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm5300evk/makefile.targets b/bsp/hpmicro/hpm5300evk/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.h b/bsp/hpmicro/hpm5300evk/rtconfig.h index 1793c387c0..b75bcbad96 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.h +++ b/bsp/hpmicro/hpm5300evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -102,7 +112,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -288,6 +298,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -315,12 +329,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -400,11 +426,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM5300_SERIES +#define SOC_SERIES_HPM5300 /* Hardware Drivers Config */ -#define SOC_HPM5300 +#define SOC_HPM5000 /* On-chip Peripheral Drivers */ @@ -416,6 +442,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.py b/bsp/hpmicro/hpm5300evk/rtconfig.py index ab7d843770..1ea9e310de 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.py +++ b/bsp/hpmicro/hpm5300evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options @@ -60,9 +59,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -82,7 +85,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -90,8 +93,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -100,8 +103,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h new file mode 100644 index 0000000000..85109511cd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/rtconfig_preinc.h @@ -0,0 +1,20 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5361 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 73 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c index 36ec033432..96699f5bfd 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S index 2ba3169ea4..4774dbd092 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S @@ -19,14 +19,6 @@ _start: la tp, __thread_pointer .option pop -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif /* Initialize stack pointer */ la t0, _stack mv sp, t0 @@ -45,12 +37,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 - + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ call reset_handler @@ -62,6 +62,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -74,3 +75,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm5300evk/startup/SConscript b/bsp/hpmicro/hpm5300evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm5300evk/startup/SConscript +++ b/bsp/hpmicro/hpm5300evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/.config b/bsp/hpmicro/hpm5301evklite/.config index 19cd38cfbc..c028e0baa6 100644 --- a/bsp/hpmicro/hpm5301evklite/.config +++ b/bsp/hpmicro/hpm5301evklite/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,12 +922,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,12 +1489,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5300_SERIES=y +CONFIG_SOC_SERIES_HPM5300=y # # Hardware Drivers Config # -CONFIG_SOC_HPM5300=y +CONFIG_SOC_HPM5000=y # # On-chip Peripheral Drivers @@ -1446,6 +1509,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set @@ -1453,5 +1517,49 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5301evklite/README.md b/bsp/hpmicro/hpm5301evklite/README.md index ba4ad0b50f..f1deec4a81 100644 --- a/bsp/hpmicro/hpm5301evklite/README.md +++ b/bsp/hpmicro/hpm5301evklite/README.md @@ -70,7 +70,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -78,7 +78,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm5301evklite/README_zh.md b/bsp/hpmicro/hpm5301evklite/README_zh.md index 905d164908..a32ce56e57 100644 --- a/bsp/hpmicro/hpm5301evklite/README_zh.md +++ b/bsp/hpmicro/hpm5301evklite/README_zh.md @@ -70,14 +70,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm5300.cfg -f board\debug_scripts\openocd\boards\hpm5301evklite.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm5301evklite/SConscript b/bsp/hpmicro/hpm5301evklite/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm5301evklite/SConscript +++ b/bsp/hpmicro/hpm5301evklite/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm5301evklite/SConstruct b/bsp/hpmicro/hpm5301evklite/SConstruct index d41dbd7584..69d7c1ccf7 100644 --- a/bsp/hpmicro/hpm5301evklite/SConstruct +++ b/bsp/hpmicro/hpm5301evklite/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -78,6 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5301evklite/applications/SConscript b/bsp/hpmicro/hpm5301evklite/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm5301evklite/applications/SConscript +++ b/bsp/hpmicro/hpm5301evklite/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm5301evklite/applications/main.c b/bsp/hpmicro/hpm5301evklite/applications/main.c index 0bbf637038..98ea3be7a3 100644 --- a/bsp/hpmicro/hpm5301evklite/applications/main.c +++ b/bsp/hpmicro/hpm5301evklite/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm5301evklite/board/Kconfig b/bsp/hpmicro/hpm5301evklite/board/Kconfig index b900b8e34e..77dec23981 100644 --- a/bsp/hpmicro/hpm5301evklite/board/Kconfig +++ b/bsp/hpmicro/hpm5301evklite/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5300 +config SOC_HPM5000 bool - select SOC_HPM5300_SERIES + select SOC_SERIES_HPM5300 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -78,6 +78,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -105,6 +110,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -132,6 +142,30 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif @@ -151,7 +185,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -159,7 +193,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -181,7 +215,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -189,7 +223,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -211,7 +245,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -219,7 +253,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -241,7 +275,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -249,7 +283,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -262,7 +296,6 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n @@ -270,6 +303,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -304,6 +338,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -396,7 +439,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -407,6 +450,294 @@ menu "On-chip Peripheral Drivers" default y endif endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + endmenu endmenu diff --git a/bsp/hpmicro/hpm5301evklite/board/SConscript b/bsp/hpmicro/hpm5301evklite/board/SConscript index dcd1e3543f..31b197126b 100644 --- a/bsp/hpmicro/hpm5301evklite/board/SConscript +++ b/bsp/hpmicro/hpm5301evklite/board/SConscript @@ -11,7 +11,7 @@ src = Split(""" """) CPPPATH = [cwd] -CPPDEFINES=['D25', 'HPM5361'] +CPPDEFINES=['D25', 'HPM5301'] group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg index 7d495f5b38..fbe2379e96 100644 --- a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/boards/hpm5301evklite.cfg @@ -16,7 +16,7 @@ # 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI # [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) # 0 - Not needed -# 1 - QE bit is at bit 6 in Status Register 1 +# 1 - QE bit is at bit6 in Status Register 1 # 2 - QE bit is at bit1 in Status Register 2 # 3 - QE bit is at bit7 in Status Register 2 # 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 @@ -46,27 +46,15 @@ # - flash ctrl index: 0xF3000000 # - base address: 0x80000000 # - flash size: 0x2000000 -# - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg index c57a36d017..935b5e87dd 100644 --- a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2023,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm5301 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5361 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr_lite.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld index 12af13362e..6591432556 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -26,6 +26,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -165,11 +174,19 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + /* The first 0x300 bytes of DLM are reserved; keep them as an explicit NOLOAD + * placeholder. This also keeps the DLM region 4KB aligned so that the linker does + * not emit an extra file-backed PT_LOAD (which made "program rtthread.elf" fail). + */ + .dlm_reserved (NOLOAD) : { + . = . + 0x300; + } > DLM + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -179,6 +196,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); @@ -256,7 +282,7 @@ SECTIONS PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -295,7 +321,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld index 26d5785602..6753ecbafd 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld @@ -112,6 +112,16 @@ SECTIONS . = ALIGN(8); } > ILM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > ILM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -213,7 +223,7 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > DLM + } > ILM __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.c b/bsp/hpmicro/hpm5301evklite/board/pinmux.c index 439a57dd45..596b052e2a 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.c +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.c @@ -53,7 +53,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C2) { HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -65,7 +65,10 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + return status_invalid_argument; } + return status_success; } void init_gpio_pins(void) diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.h b/bsp/hpmicro/hpm5301evklite/board/pinmux.h index 3e37d1bf1b..f786446117 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.h +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c index 3c1ef45f2b..ac7edf6d44 100644 --- a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm5301evklite/makefile.targets b/bsp/hpmicro/hpm5301evklite/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.h b/bsp/hpmicro/hpm5301evklite/rtconfig.h index a2b1da3c16..77da4e4121 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.h +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -290,6 +300,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -317,12 +331,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -402,11 +428,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM5300_SERIES +#define SOC_SERIES_HPM5300 /* Hardware Drivers Config */ -#define SOC_HPM5300 +#define SOC_HPM5000 /* On-chip Peripheral Drivers */ @@ -418,6 +444,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.py b/bsp/hpmicro/hpm5301evklite/rtconfig.py index dc209cee21..b7720eadf3 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.py +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h b/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h new file mode 100644 index 0000000000..f2f33d8ed1 --- /dev/null +++ b/bsp/hpmicro/hpm5301evklite/rtconfig_preinc.h @@ -0,0 +1,20 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D25 +#define HPM5301 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 73 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript index 3e8dd931d3..406b141409 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/SConscript @@ -15,7 +15,7 @@ if rtconfig.PLATFORM == 'gcc': src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] CPPPATH = [cwd] -CPPDEFINES=['D45', rtconfig.CHIP_NAME] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c index 36ec033432..96699f5bfd 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S index 7646393644..d4e7a4fd61 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/start.S @@ -19,14 +19,6 @@ _start: la tp, __thread_pointer .option pop -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif /* Initialize stack pointer */ la t0, _stack mv sp, t0 @@ -45,12 +37,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 - + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ call reset_handler @@ -62,7 +62,7 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -75,3 +75,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S index 8f10ab7bdd..5703e22330 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/vectors.S @@ -20,74 +20,90 @@ __vector_table: IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_HANDLER 11 /* DAC IRQ handler */ - IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_HANDLER 18 /* UART0 IRQ handler */ - IRQ_HANDLER 19 /* UART1 IRQ handler */ - IRQ_HANDLER 20 /* UART2 IRQ handler */ - IRQ_HANDLER 21 /* UART3 IRQ handler */ - IRQ_HANDLER 22 /* UART4 IRQ handler */ - IRQ_HANDLER 23 /* UART5 IRQ handler */ - IRQ_HANDLER 24 /* UART6 IRQ handler */ - IRQ_HANDLER 25 /* UART7 IRQ handler */ - IRQ_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_HANDLER 28 /* PTPC IRQ handler */ - IRQ_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_HANDLER 31 /* TSNS IRQ handler */ - IRQ_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_HANDLER 48 /* SDP IRQ handler */ - IRQ_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_HANDLER 51 /* XDMA IRQ handler */ - IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* DRAM IRQ handler */ - IRQ_HANDLER 54 /* RNG IRQ handler */ - IRQ_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_HANDLER 57 /* DAO IRQ handler */ - IRQ_HANDLER 58 /* PDM IRQ handler */ - IRQ_HANDLER 59 /* FFA IRQ handler */ - IRQ_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_HANDLER 61 /* USB0 IRQ handler */ - IRQ_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_HANDLER 64 /* PSEC IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PWDG IRQ handler */ - IRQ_HANDLER 67 /* PTMR IRQ handler */ - IRQ_HANDLER 68 /* PUART IRQ handler */ - IRQ_HANDLER 69 /* FUSE IRQ handler */ - IRQ_HANDLER 70 /* SECMON IRQ handler */ - IRQ_HANDLER 71 /* RTC IRQ handler */ - IRQ_HANDLER 72 /* BUTN IRQ handler */ - IRQ_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_HANDLER 74 /* BVIO IRQ handler */ - IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/bsp/hpmicro/hpm5301evklite/startup/SConscript b/bsp/hpmicro/hpm5301evklite/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/SConscript +++ b/bsp/hpmicro/hpm5301evklite/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/.config b/bsp/hpmicro/hpm5e00evk/.config index 56353cc1ce..a5e80f4105 100644 --- a/bsp/hpmicro/hpm5e00evk/.config +++ b/bsp/hpmicro/hpm5e00evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,12 +922,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,7 +1489,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM5E00_SERIES=y +CONFIG_SOC_SERIES_HPM5E00=y # # Hardware Drivers Config @@ -1452,15 +1515,72 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_EWDG is not set # CONFIG_BSP_USING_PWMV2 is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_OWR is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEOV2 is not set +# CONFIG_BSP_USING_SDM is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_PPI is not set +# CONFIG_BSP_USING_LOBS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_ESC is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm5e00evk/.cproject b/bsp/hpmicro/hpm5e00evk/.cproject index eafefd8ef5..437444787b 100644 --- a/bsp/hpmicro/hpm5e00evk/.cproject +++ b/bsp/hpmicro/hpm5e00evk/.cproject @@ -20,7 +20,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.debug" valueType="enumerated" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean" /> @@ -70,9 +70,9 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/ip}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> @@ -87,10 +87,10 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6E80}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM5E31}"" /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -std=gnu11" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -std=gnu11" valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> @@ -111,7 +111,7 @@ <listOptionValue builtIn="false" value="m " /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> @@ -135,7 +135,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> <additionalInput kind="additionalinput" paths="$(LIBS)" /> @@ -168,9 +168,9 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/ip}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> @@ -185,18 +185,18 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6E80}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM5E31}"" /> </option> <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input" /> </tool> </toolChain> </folderInfo> <sourceEntries> - <entry excluding="//dist/project|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon|//rt-thread/bsp/Vango|//rt-thread/bsp/acm32|//rt-thread/bsp/airm2m|//rt-thread/bsp/allwinner|//rt-thread/bsp/allwinner_tina|//rt-thread/bsp/amebaz|//rt-thread/bsp/apm32|//rt-thread/bsp/apollo2|//rt-thread/bsp/asm9260t|//rt-thread/bsp/at32|//rt-thread/bsp/at91|//rt-thread/bsp/avr32|//rt-thread/bsp/beaglebone|//rt-thread/bsp/bf533|//rt-thread/bsp/bluetrum|//rt-thread/bsp/bm3803|//rt-thread/bsp/bouffalo_lab|//rt-thread/bsp/ck802|//rt-thread/bsp/core-v-mcu|//rt-thread/bsp/cvitek|//rt-thread/bsp/dm365|//rt-thread/bsp/efm32|//rt-thread/bsp/essemi|//rt-thread/bsp/fm33lc026|//rt-thread/bsp/frdm-k64f|//rt-thread/bsp/ft2004|//rt-thread/bsp/ft32|//rt-thread/bsp/fujitsu|//rt-thread/bsp/gd32|//rt-thread/bsp/hc32|//rt-thread/bsp/hc32l136|//rt-thread/bsp/hc32l196|//rt-thread/bsp/hifive1|//rt-thread/bsp/hk32|//rt-thread/bsp/hpmicro/hpm5300evk|//rt-thread/bsp/hpmicro/hpm5301evklite|//rt-thread/bsp/hpmicro/hpm6200evk|//rt-thread/bsp/hpmicro/hpm6300evk|//rt-thread/bsp/hpmicro/hpm6750evk|//rt-thread/bsp/hpmicro/hpm6750evk2|//rt-thread/bsp/hpmicro/hpm6750evkmini|//rt-thread/bsp/hpmicro/hpm6800evk|//rt-thread/bsp/hpmicro/libraries/drivers/drv_adc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_can.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_dao.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet_phy.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_ewdt.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_hwtimer.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2c.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2s.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_lcd.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_mcan.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pdm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pwm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_rtc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_sdio.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_spi.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_uart_v2.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_usb.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_wdt.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/camera|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/codec|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/panel|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ppi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/sccb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/smbus|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/spi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/utils|//rt-thread/bsp/ht32|//rt-thread/bsp/juicevm|//rt-thread/bsp/k210|//rt-thread/bsp/k230|//rt-thread/bsp/lm3s8962|//rt-thread/bsp/lm3s9b9x|//rt-thread/bsp/lm4f232|//rt-thread/bsp/loongson|//rt-thread/bsp/m16c62p|//rt-thread/bsp/maxim|//rt-thread/bsp/microblaze|//rt-thread/bsp/microchip|//rt-thread/bsp/mini2440|//rt-thread/bsp/mini4020|//rt-thread/bsp/mipssim|//rt-thread/bsp/mm32|//rt-thread/bsp/mm32f103x|//rt-thread/bsp/mm32f327x|//rt-thread/bsp/mm32f526x|//rt-thread/bsp/mm32l07x|//rt-thread/bsp/mm32l3xx|//rt-thread/bsp/msp432e401y-LaunchPad|//rt-thread/bsp/n32|//rt-thread/bsp/n32g452xx|//rt-thread/bsp/nios_ii|//rt-thread/bsp/nrf5x|//rt-thread/bsp/nuclei|//rt-thread/bsp/nuvoton|//rt-thread/bsp/nv32f100x|//rt-thread/bsp/nxp|//rt-thread/bsp/phytium|//rt-thread/bsp/pic32ethernet|//rt-thread/bsp/qemu-vexpress-a9|//rt-thread/bsp/qemu-virt64-aarch64|//rt-thread/bsp/qemu-virt64-riscv|//rt-thread/bsp/raspberry-pi|//rt-thread/bsp/raspberry-pico|//rt-thread/bsp/renesas|//rt-thread/bsp/rm48x50|//rt-thread/bsp/rockchip|//rt-thread/bsp/rv32m1_vega|//rt-thread/bsp/rx|//rt-thread/bsp/sam7x|//rt-thread/bsp/samd21|//rt-thread/bsp/sep6200|//rt-thread/bsp/simulator|//rt-thread/bsp/smartfusion2|//rt-thread/bsp/sparkfun-redv|//rt-thread/bsp/stm32|//rt-thread/bsp/synopsys|//rt-thread/bsp/synwit|//rt-thread/bsp/tae32f5300|//rt-thread/bsp/taihu|//rt-thread/bsp/thead-smart|//rt-thread/bsp/ti|//rt-thread/bsp/tkm32F499|//rt-thread/bsp/tm4c123bsp|//rt-thread/bsp/tm4c129x|//rt-thread/bsp/tms320c6678|//rt-thread/bsp/upd70f3454|//rt-thread/bsp/w60x|//rt-thread/bsp/wch|//rt-thread/bsp/wh44b0|//rt-thread/bsp/x86|//rt-thread/bsp/xplorer4330|//rt-thread/bsp/yichip|//rt-thread/bsp/zynqmp-a53-dfzu2eg|//rt-thread/bsp/zynqmp-r5-axu4ev|//rt-thread/components/dfs/dfs_v1/filesystems/cromfs|//rt-thread/components/dfs/dfs_v1/filesystems/elmfat|//rt-thread/components/dfs/dfs_v1/filesystems/iso9660|//rt-thread/components/dfs/dfs_v1/filesystems/mqueue|//rt-thread/components/dfs/dfs_v1/filesystems/nfs|//rt-thread/components/dfs/dfs_v1/filesystems/ramfs|//rt-thread/components/dfs/dfs_v1/filesystems/romfs|//rt-thread/components/dfs/dfs_v1/filesystems/skeleton|//rt-thread/components/dfs/dfs_v1/filesystems/tmpfs|//rt-thread/components/dfs/dfs_v2|//rt-thread/components/drivers/ata|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/block|//rt-thread/components/drivers/can|//rt-thread/components/drivers/clk|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/mnt.c|//rt-thread/components/drivers/core/numa.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/core/power_domain.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/dma|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/iio|//rt-thread/components/drivers/ipc/completion_mp.c|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/led|//rt-thread/components/drivers/mailbox|//rt-thread/components/drivers/mfd|//rt-thread/components/drivers/misc|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/nvme|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/pci|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/phye|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pin/dev_pin_dm.c|//rt-thread/components/drivers/pin/dev_pin_ofw.c|//rt-thread/components/drivers/pinctrl|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/regulator|//rt-thread/components/drivers/reset|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/scsi|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/bypass.c|//rt-thread/components/drivers/serial/dev_serial_v2.c|//rt-thread/components/drivers/serial/serial_dm.c|//rt-thread/components/drivers/serial/serial_tty.c|//rt-thread/components/drivers/smp_call|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/thermal|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/mprotect|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/documentation|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v/common/atomic_riscv.c|//rt-thread/libcpu/risc-v/common64|//rt-thread/libcpu/risc-v/rv64|//rt-thread/libcpu/risc-v/t-head|//rt-thread/libcpu/risc-v/virt64|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu_mp.c|//rt-thread/src/klibc/rt_vsnprintf_std.c|//rt-thread/src/klibc/utest|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//startup/HPM6E80/toolchains/gcc/vectors.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" /> + <entry excluding="//dist/project|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon|//rt-thread/bsp/Vango|//rt-thread/bsp/acm32|//rt-thread/bsp/airm2m|//rt-thread/bsp/allwinner|//rt-thread/bsp/allwinner_tina|//rt-thread/bsp/amebaz|//rt-thread/bsp/apm32|//rt-thread/bsp/apollo2|//rt-thread/bsp/asm9260t|//rt-thread/bsp/at32|//rt-thread/bsp/at91|//rt-thread/bsp/avr32|//rt-thread/bsp/beaglebone|//rt-thread/bsp/bf533|//rt-thread/bsp/bluetrum|//rt-thread/bsp/bm3803|//rt-thread/bsp/bouffalo_lab|//rt-thread/bsp/ck802|//rt-thread/bsp/core-v-mcu|//rt-thread/bsp/cvitek|//rt-thread/bsp/dm365|//rt-thread/bsp/efm32|//rt-thread/bsp/essemi|//rt-thread/bsp/fm33lc026|//rt-thread/bsp/frdm-k64f|//rt-thread/bsp/ft2004|//rt-thread/bsp/ft32|//rt-thread/bsp/fujitsu|//rt-thread/bsp/gd32|//rt-thread/bsp/hc32|//rt-thread/bsp/hc32l136|//rt-thread/bsp/hc32l196|//rt-thread/bsp/hifive1|//rt-thread/bsp/hk32|//rt-thread/bsp/hpmicro/hpm5300evk|//rt-thread/bsp/hpmicro/hpm5301evklite|//rt-thread/bsp/hpmicro/hpm6200evk|//rt-thread/bsp/hpmicro/hpm6300evk|//rt-thread/bsp/hpmicro/hpm6750evk|//rt-thread/bsp/hpmicro/hpm6750evk2|//rt-thread/bsp/hpmicro/hpm6750evkmini|//rt-thread/bsp/hpmicro/hpm6800evk|//rt-thread/bsp/hpmicro/libraries/drivers/drv_adc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_can.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_dao.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet_phy.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_ewdt.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_hwtimer.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2c.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2s.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_lcd.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_mcan.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pdm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pwm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_rtc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_sdio.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_spi.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_uart_v2.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_usb.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_wdt.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/camera|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/codec|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/panel|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ppi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/sccb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/smbus|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/spi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31/hpm_trgm_soc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5E00/HPM5E31/toolchains|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/utils|//rt-thread/bsp/ht32|//rt-thread/bsp/juicevm|//rt-thread/bsp/k210|//rt-thread/bsp/k230|//rt-thread/bsp/lm3s8962|//rt-thread/bsp/lm3s9b9x|//rt-thread/bsp/lm4f232|//rt-thread/bsp/loongson|//rt-thread/bsp/m16c62p|//rt-thread/bsp/maxim|//rt-thread/bsp/microblaze|//rt-thread/bsp/microchip|//rt-thread/bsp/mini2440|//rt-thread/bsp/mini4020|//rt-thread/bsp/mipssim|//rt-thread/bsp/mm32|//rt-thread/bsp/mm32f103x|//rt-thread/bsp/mm32f327x|//rt-thread/bsp/mm32f526x|//rt-thread/bsp/mm32l07x|//rt-thread/bsp/mm32l3xx|//rt-thread/bsp/msp432e401y-LaunchPad|//rt-thread/bsp/n32|//rt-thread/bsp/n32g452xx|//rt-thread/bsp/nios_ii|//rt-thread/bsp/nrf5x|//rt-thread/bsp/nuclei|//rt-thread/bsp/nuvoton|//rt-thread/bsp/nv32f100x|//rt-thread/bsp/nxp|//rt-thread/bsp/phytium|//rt-thread/bsp/pic32ethernet|//rt-thread/bsp/qemu-vexpress-a9|//rt-thread/bsp/qemu-virt64-aarch64|//rt-thread/bsp/qemu-virt64-riscv|//rt-thread/bsp/raspberry-pi|//rt-thread/bsp/raspberry-pico|//rt-thread/bsp/renesas|//rt-thread/bsp/rm48x50|//rt-thread/bsp/rockchip|//rt-thread/bsp/rv32m1_vega|//rt-thread/bsp/rx|//rt-thread/bsp/sam7x|//rt-thread/bsp/samd21|//rt-thread/bsp/sep6200|//rt-thread/bsp/simulator|//rt-thread/bsp/smartfusion2|//rt-thread/bsp/sparkfun-redv|//rt-thread/bsp/stm32|//rt-thread/bsp/synopsys|//rt-thread/bsp/synwit|//rt-thread/bsp/tae32f5300|//rt-thread/bsp/taihu|//rt-thread/bsp/thead-smart|//rt-thread/bsp/ti|//rt-thread/bsp/tkm32F499|//rt-thread/bsp/tm4c123bsp|//rt-thread/bsp/tm4c129x|//rt-thread/bsp/tms320c6678|//rt-thread/bsp/upd70f3454|//rt-thread/bsp/w60x|//rt-thread/bsp/wch|//rt-thread/bsp/wh44b0|//rt-thread/bsp/x86|//rt-thread/bsp/xplorer4330|//rt-thread/bsp/yichip|//rt-thread/bsp/zynqmp-a53-dfzu2eg|//rt-thread/bsp/zynqmp-r5-axu4ev|//rt-thread/components/dfs/dfs_v1/filesystems/cromfs|//rt-thread/components/dfs/dfs_v1/filesystems/elmfat|//rt-thread/components/dfs/dfs_v1/filesystems/iso9660|//rt-thread/components/dfs/dfs_v1/filesystems/mqueue|//rt-thread/components/dfs/dfs_v1/filesystems/nfs|//rt-thread/components/dfs/dfs_v1/filesystems/ramfs|//rt-thread/components/dfs/dfs_v1/filesystems/romfs|//rt-thread/components/dfs/dfs_v1/filesystems/skeleton|//rt-thread/components/dfs/dfs_v1/filesystems/tmpfs|//rt-thread/components/dfs/dfs_v2|//rt-thread/components/drivers/ata|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/block|//rt-thread/components/drivers/can|//rt-thread/components/drivers/clk|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/mnt.c|//rt-thread/components/drivers/core/numa.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/core/power_domain.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/dma|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/iio|//rt-thread/components/drivers/ipc/completion_mp.c|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/led|//rt-thread/components/drivers/mailbox|//rt-thread/components/drivers/mfd|//rt-thread/components/drivers/misc|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/nvme|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/pci|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/phye|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pin/dev_pin_dm.c|//rt-thread/components/drivers/pin/dev_pin_ofw.c|//rt-thread/components/drivers/pinctrl|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/regulator|//rt-thread/components/drivers/reset|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/scsi|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/bypass.c|//rt-thread/components/drivers/serial/dev_serial_v2.c|//rt-thread/components/drivers/serial/serial_dm.c|//rt-thread/components/drivers/serial/serial_tty.c|//rt-thread/components/drivers/smp_call|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/thermal|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/mprotect|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/documentation|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v/common/atomic_riscv.c|//rt-thread/libcpu/risc-v/common64|//rt-thread/libcpu/risc-v/rv64|//rt-thread/libcpu/risc-v/t-head|//rt-thread/libcpu/risc-v/virt64|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu_mp.c|//rt-thread/src/klibc/rt_vsnprintf_std.c|//rt-thread/src/klibc/utest|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//startup/HPM5E31/toolchains/gcc/vectors.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" /> </sourceEntries> </configuration> </storageModule> diff --git a/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini b/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini index 421ec3853e..3b5f39d9dc 100644 --- a/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini +++ b/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini @@ -17,4 +17,4 @@ project_type=rt-thread os_branch=master
os_version=latest
project_name=blink_led
-output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk
\ No newline at end of file +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm5e00evk
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/README.md b/bsp/hpmicro/hpm5e00evk/README.md index 1852f9e539..5af90b2054 100644 --- a/bsp/hpmicro/hpm5e00evk/README.md +++ b/bsp/hpmicro/hpm5e00evk/README.md @@ -72,7 +72,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5e00.cfg -f board\debug_scripts\openocd\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -80,7 +80,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5e00.cfg -f board\debug_scripts\openocd\boards\hpm5e00evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm5e00evk/README_zh.md b/bsp/hpmicro/hpm5e00evk/README_zh.md index c22d6f2c06..9ef19f76bf 100644 --- a/bsp/hpmicro/hpm5e00evk/README_zh.md +++ b/bsp/hpmicro/hpm5e00evk/README_zh.md @@ -72,14 +72,14 @@ HPM5E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，� - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5e00.cfg -f board\debug_scripts\openocd\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm5e00.cfg -f board\debug_scripts\openocd\boards\hpm5e00evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm5e00evk/SConscript b/bsp/hpmicro/hpm5e00evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm5e00evk/SConscript +++ b/bsp/hpmicro/hpm5e00evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm5e00evk/SConstruct b/bsp/hpmicro/hpm5e00evk/SConstruct index d41dbd7584..69d7c1ccf7 100644 --- a/bsp/hpmicro/hpm5e00evk/SConstruct +++ b/bsp/hpmicro/hpm5e00evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -78,6 +78,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5e00evk/applications/SConscript b/bsp/hpmicro/hpm5e00evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm5e00evk/applications/SConscript +++ b/bsp/hpmicro/hpm5e00evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm5e00evk/applications/main.c b/bsp/hpmicro/hpm5e00evk/applications/main.c index a5a7f07c73..8aff6b8126 100644 --- a/bsp/hpmicro/hpm5e00evk/applications/main.c +++ b/bsp/hpmicro/hpm5e00evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm5e00evk/board/Kconfig b/bsp/hpmicro/hpm5e00evk/board/Kconfig index e07e937b37..0c4568edfb 100644 --- a/bsp/hpmicro/hpm5e00evk/board/Kconfig +++ b/bsp/hpmicro/hpm5e00evk/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_HPM5E00 bool - select SOC_HPM5E00_SERIES + select SOC_SERIES_HPM5E00 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -61,6 +61,7 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + menuconfig BSP_USING_UART1 bool "Enable UART1" default n @@ -87,6 +88,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -114,6 +120,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -141,10 +152,15 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" - default n + default y if BSP_USING_UART4 config BSP_UART4_RX_USING_DMA bool "Enable UART4 RX DMA" @@ -168,6 +184,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -195,6 +216,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -222,6 +248,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -249,10 +280,33 @@ menu "On-chip Peripheral Drivers" int "UART7 Interrupt Priority" range 1 7 default 1 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -269,7 +323,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -277,7 +331,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -290,7 +344,7 @@ menu "On-chip Peripheral Drivers" endif config BSP_USING_SPI1 bool "Enable SPI1" - default n + default y if BSP_USING_SPI1 config BSP_SPI1_USING_DMA bool "Enable SPI1 DMA" @@ -299,7 +353,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -307,7 +361,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -323,13 +377,13 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n config BSP_SPI2_IRQ_PRIORITY int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -337,7 +391,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -353,13 +407,13 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n config BSP_SPI3_IRQ_PRIORITY int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -367,7 +421,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -388,7 +442,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PHY if BSP_USING_ETH if BSP_USING_ETH - choice BSP_ETH0_SEL + choice prompt "ETH" default BSP_USING_ETH0 @@ -405,6 +459,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -439,6 +494,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -496,12 +560,33 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n select RT_USING_FAL if BSP_USING_XPI_FLASH + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S3 + bool "Enable I2S3" + default y + config BSP_USING_AUDIO_CODEC_WM8960 + bool "Enable audio codec on board" + default y + endif menuconfig BSP_USING_USB bool "Enable USB" @@ -517,7 +602,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_EWDG bool "Enable EWDG" default n @@ -534,7 +618,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWMV2 bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWMV2 + select RT_USING_PWM menuconfig BSP_USING_MCAN bool "Enable MCAN" @@ -582,7 +666,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -597,10 +681,329 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_OWR + bool "Enable OWR (One Wire)" + default n + + menuconfig BSP_USING_QEIV2 + bool "Enable QEIV2 (Quadrature Encoder Interface V2)" + default n + + menuconfig BSP_USING_QEOV2 + bool "Enable QEOV2 (Quadrature Encoder Output V2)" + default n + + menuconfig BSP_USING_SDM + bool "Enable SDM (Sigma-Delta Modulator)" + default n + + menuconfig BSP_USING_PLB + bool "Enable PLB" + default n + + menuconfig BSP_USING_PPI + bool "Enable PPI (Parallel Port Interface)" + default n + + menuconfig BSP_USING_LOBS + bool "Enable LOBS" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_ESC + bool "Enable ESC (EtherCAT Slave Controller)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. endmenu +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu +menu "Third-Party Add-ons" +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif endmenu +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg index e3c75108fc..cb3b6e0e9a 100644 --- a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg @@ -60,23 +60,10 @@ flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 flash bank xpi0_hybrid hpm_xpi 0xB0000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg index 2f4045a406..04377ea25a 100644 --- a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2024 HPMicro +# Copyright (c) 2024-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm5e00 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm5e00 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -12,7 +16,9 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + proc reset_soc {} { - $::_TARGET0 riscv dmi_write 0x39 0xF410001C - $::_TARGET0 riscv dmi_write 0x3C 24000000 + sba_write_mem 0xF410001C 24000000 } diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c deleted file mode 100644 index bbb1b25beb..0000000000 --- a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include <stdio.h> -#include "hpm_wm8960.h" - -#ifndef HPM_WM8960_MCLK_TOLERANCE -#define HPM_WM8960_MCLK_TOLERANCE (4U) -#endif - -/* wm8960 register default value */ -static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { - 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, -}; - -/* store reg value */ -static uint16_t wm8960_reg_val[WM8960_REG_NUM]; - -hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) -{ - assert(control != NULL); - assert(config != NULL); - - hpm_stat_t stat = status_success; - - (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); - - /* Reset */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); - - /* Power on input modules */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); - /* Power on output modules */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); - /* Power on PGA and mixer */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); - - /* ADC and DAC uses same clock */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); - - /* set data protocol */ - HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); - - /* set wm8960 as slave */ - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); - - /* invert LRCLK */ - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); - - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); - - /* ADC volume, 8dB */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); - - /* Digital DAC volume, 0dB */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); - - /* Headphone volume, LOUT1 and ROUT1, 6dB */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); - - /* speaker volume 6dB */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); - /* enable class D output */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); - - /* Unmute DAC. */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); - - HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); - - /* set data route */ - HPM_CHECK_RET(wm8960_set_data_route(control, config)); - - return status_success; -} - -hpm_stat_t wm8960_deinit(wm8960_control_t *control) -{ - hpm_stat_t stat = status_success; - - /* power off all modules */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); - - return status_success; -} - -hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) -{ - return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); -} - -hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) -{ - hpm_stat_t stat = status_success; - switch (module) { - case wm8960_module_adc: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, - ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, - ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); - break; - case wm8960_module_dac: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, - ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, - ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); - break; - case wm8960_module_vref: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, - ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); - break; - case wm8960_module_ana_in: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, - ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, - ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, - ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, - ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); - break; - case wm8960_module_lineout: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, - ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, - ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); - break; - case wm8960_module_micbais: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, - ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); - break; - case wm8960_module_speaker: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, - ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, - ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); - break; - case wm8960_module_output_mixer: - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, - ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, - ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) -{ - hpm_stat_t stat = status_success; - - /* select left input */ - HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); - /* select right input */ - HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); - /* select source to output mixer */ - HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); - - switch (config->route) { - case wm8960_route_bypass: - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); - break; - case wm8960_route_playback: - /* I2S_IN-> DAC-> HP */ - /* Set power for DAC */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); - break; - case wm8960_route_playback_and_record: - /* Set power */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); - break; - case wm8960_route_record: - /* ANA_IN->ADC->I2S_OUT */ - /* Power up ADC and AIN */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); - HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) -{ - hpm_stat_t stat = status_success; - uint16_t val = 0; - - switch (input) { - case wm8960_input_closed: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - break; - case wm8960_input_single_ended_mic: - /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); - break; - case wm8960_input_differential_mic_input2: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); - break; - case wm8960_input_differential_mic_input3: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); - break; - case wm8960_input_line_input2: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); - val |= 0xEU; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); - break; - case wm8960_input_line_input3: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); - val |= 0x70U; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) -{ - hpm_stat_t stat = status_success; - uint16_t val = 0; - - switch (input) { - case wm8960_input_closed: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - break; - case wm8960_input_single_ended_mic: - /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); - break; - case wm8960_input_differential_mic_input2: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); - break; - case wm8960_input_differential_mic_input3: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); - break; - case wm8960_input_line_input2: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); - val |= 0xEU; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); - break; - case wm8960_input_line_input3: - HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); - val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); - HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); - val |= 0x70U; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) -{ - uint16_t vol = 0; - hpm_stat_t stat = status_success; - switch (module) { - case wm8960_module_adc: - if (volume > 255U) { - stat = status_invalid_argument; - } else { - vol = (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); - /* Update volume */ - vol = (uint16_t)(0x100U | volume); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); - } - break; - case wm8960_module_dac: - if (volume > 255U) { - stat = status_invalid_argument; - } else { - vol = (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); - vol = 0x100U | (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); - } - break; - case wm8960_module_headphone: - if (volume > 0x7FU) { - stat = status_invalid_argument; - } else { - vol = (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); - vol = 0x100U | (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); - } - break; - case wm8960_module_ana_in: - if (volume > 0x3FU) { - stat = status_invalid_argument; - } else { - vol = (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); - vol = 0x100U | (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); - } - break; - case wm8960_module_speaker: - if (volume > 0x7FU) { - stat = status_invalid_argument; - } else { - vol = (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); - vol = 0x100U | (uint16_t)volume; - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); - } - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) -{ - uint32_t delta = (source >= target) ? (source - target) : (target - source); - if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { - return true; - } - return false; -} - -hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) -{ - hpm_stat_t stat = status_success; - uint16_t val = 0; - uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; - bool clock_meet_requirement = false; - - if (sysclk / sample_rate > 256 * 6) { - sysclk = sysclk / 2; - val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ - } - - for (uint8_t i = 0; i < 7; i++) { - if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { - val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); - clock_meet_requirement = true; - break; - } - } - - if (!clock_meet_requirement) { - return status_invalid_argument; - } - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); - - /* set sample bit */ - switch (bits) { - case 16: - stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); - break; - case 20: - stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); - break; - case 24: - stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); - break; - case 32: - stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) -{ - hpm_stat_t stat = status_success; - - if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); - } - - if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); - } - - if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); - HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); - } - - return stat; -} - - -hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) -{ - /* The first 7 bits (B15 to B9) are address bits that select which control register */ - /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ - rt_size_t size; - rt_uint8_t data[2]; - data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); - data[1] = (uint8_t)(val & 0xFFU); - - size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); - if (size != 2) { - return status_fail; - } - - wm8960_reg_val[reg] = val; - return status_success; -} - -hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) -{ - if (reg >= WM8960_REG_NUM) { - return status_invalid_argument; - } - *val = wm8960_reg_val[reg]; - - return status_success; -} - -hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) -{ - hpm_stat_t stat = 0; - uint16_t reg_val; - - /* Read the register value out */ - stat = wm8960_read_reg(reg, ®_val); - if (stat != status_success) { - return status_fail; - } - - /* Modify the value */ - reg_val &= (uint16_t)~mask; - reg_val |= val; - - /* Write the data to register */ - stat = wm8960_write_reg(control, reg, reg_val); - if (stat != status_success) { - return status_fail; - } - - return status_success; -} diff --git a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h deleted file mode 100644 index a163a52390..0000000000 --- a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_WM8960_H_ -#define _HPM_WM8960_H_ - -//#include "hpm_i2c_drv.h" -//#include "hpm_common.h" -#include <rtthread.h> -#include <rtdevice.h> -#include "rtt_board.h" -#include "drivers/dev_i2c.h" -#include "hpm_wm8960_regs.h" - -#define WM8960_I2C_ADDR 0x1A - -typedef enum wm8960_module { - wm8960_module_adc = 0, /* ADC module in WM8960 */ - wm8960_module_dac = 1, /* DAC module in WM8960 */ - wm8960_module_vref = 2, /* VREF module */ - wm8960_module_headphone = 3, /* Headphone */ - wm8960_module_micbais = 4, /* Mic bias */ - wm8960_module_ana_in = 6, /* Analog in PGA */ - wm8960_module_lineout = 7, /* Line out module */ - wm8960_module_speaker = 8, /* Speaker module */ - wm8960_module_output_mixer = 9, /* Output mixer */ -} wm8960_module_t; - -/* wm8960 play source for output mixer */ -typedef enum wm8960_play_source { - wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ - wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ - wm8960_play_source_dac = 4, /* DAC to Output Mixer */ -} wm8960_play_source_t; - -/* WM8960 data route */ -typedef enum wm8960_route { - wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ - wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ - wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ - wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ -} wm8960_route_t; - -/* The audio data transfer protocol choice */ -typedef enum wm8960_protocol { - wm8960_bus_i2s = 2, /* I2S type */ - wm8960_bus_left_justified = 1, /* Left justified mode */ - wm8960_bus_right_justified = 0, /* Right justified mode */ - wm8960_bus_pcma = 3, /* PCM A mode */ - wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ -} wm8960_protocol_t; - -/* wm8960 input source */ -typedef enum wm8960_input { - wm8960_input_closed = 0, /* Input device is closed */ - wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ - wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ - wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ - wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ - wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ -} wm8960_input_t; - -/* wm8960 audio format */ -typedef struct wm8960_audio_format { - uint32_t mclk_hz; /* master clock frequency */ - uint32_t sample_rate; /* sample rate */ - uint32_t bit_width; /* bit width */ -} wm8960_audio_format_t; - -/* configure structure of WM8960 */ -typedef struct wm8960_config { - wm8960_route_t route; /* Audio data route.*/ - wm8960_protocol_t bus; /* Audio transfer protocol */ - bool enable_speaker; /* True means enable class D speaker as output, false means no */ - wm8960_input_t left_input; /* Left input source for WM8960 */ - wm8960_input_t right_input; /* Right input source for wm8960 */ - wm8960_play_source_t play_source; /* play source */ - wm8960_audio_format_t format; /* Audio format */ -} wm8960_config_t; - -typedef struct { - struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ - uint8_t slave_address; /* code device address */ -} wm8960_control_t; - - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * @brief WM8960 initialize function. - * - * @param control WM8960 control structure. - * @param config WM8960 configuration structure. - */ -hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); - -/** - * @brief Deinit the WM8960 codec. - * - * This function close all modules in WM8960 to save power. - * - * @param control WM8960 control structure pointer. - */ -hpm_stat_t wm8960_deinit(wm8960_control_t *control); - -/** - * @brief Set audio data route in WM8960. - * - * This function would set the data route according to route. - * - * @param control WM8960 control structure. - * @param config Audio configure structure in WM8960. - */ -hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); - -/** - * @brief Set left audio input source in WM8960. - * - * @param control WM8960 control structure. - * @param input Audio input source. - */ -hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); - -/** - * @brief Set right audio input source in WM8960. - * - * @param control WM8960 control structure. - * @param input Audio input source. - */ -hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); - -/** - * @brief Set the audio transfer protocol. - * - * @param control WM8960 control structure. - * @param protocol Audio data transfer protocol. - */ -hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); - -/** - * @brief Set the volume of different modules in WM8960. - * - * This function would set the volume of WM8960 modules. Uses need to appoint the module. - * The function assume that left channel and right channel has the same volume. - * - * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db - * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db - * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db - * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db - * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db - * - * - * @param control WM8960 control structure. - * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. - * @param volume Volume value need to be set. - */ -hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); - -/** - * @brief Enable/disable expected module. - * - * @param control WM8960 control structure. - * @param module Module expected to enable. - * @param enable Enable or disable moudles. - */ -hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); - -/** - * @brief SET the WM8960 play source. - * - * @param control WM8960 control structure. - * @param play_source play source - * - * @return kStatus_WM8904_Success if successful, different code otherwise.. - */ -hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); - -/** - * @brief Configure the data format of audio data. - * - * This function would configure the registers about the sample rate, bit depths. - * - * @param control WM8960 control structure pointer. - * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. - * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now - * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. - * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit - * and 32 bit in HW). - */ -hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); - - -/** - * @brief Write register to WM8960 using I2C. - * - * @param control WM8960 control structure. - * @param reg The register address in WM8960. - * @param val Value needs to write into the register. - */ -hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); - -/** - * @brief Read register from WM8960 using I2C. - * @param reg The register address in WM8960. - * @param val Value written to. - */ -hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); - -/** - * @brief Modify some bits in the register using I2C. - * @param control WM8960 control structure. - * @param reg The register address in WM8960. - * @param mask The mask code for the bits want to write. The bit you want to write should be 0. - * @param val Value needs to write into the register. - */ -hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); - - -#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960_regs.h b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960_regs.h deleted file mode 100644 index a484f2937c..0000000000 --- a/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960_regs.h +++ /dev/null @@ -1,2139 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_WM8960_REG_H_ -#define _HPM_WM8960_REG_H_ - -/* WM8960 register number */ -#define WM8960_REG_NUM 56U - -/* Define the register address of WM8960 */ -#define WM8960_LINVOL 0x0U /* Left Input Volume */ -#define WM8960_RINVOL 0x1U /* Right Input Volume */ -#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ -#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ -#define WM8960_CLOCK1 0x4U /* Clocking(1) */ -#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ -#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ -#define WM8960_IFACE1 0x7U /* Audio Interface */ -#define WM8960_CLOCK2 0x8U /* Clocking(2) */ -#define WM8960_IFACE2 0x9U /* Audio Interface */ -#define WM8960_LDAC 0xaU /* Left DAC */ -#define WM8960_RDAC 0xbU /* Right DAC Volume */ -#define WM8960_RESET 0xfU /* RESET */ -#define WM8960_3D 0x10U /* 3D Control */ -#define WM8960_ALC1 0x11U /* ALC (1) */ -#define WM8960_ALC2 0x12U /* ALC (2) */ -#define WM8960_ALC3 0x13U /* ALC (3) */ -#define WM8960_NOISEG 0x14U /* Noise Gate */ -#define WM8960_LADC 0x15U /* Left ADC Volume */ -#define WM8960_RADC 0x16U /* Right ADC Volume */ -#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ -#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ -#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ -#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ -#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ -#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ -#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ -#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ -#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ -#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ -#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ -#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ -#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ -#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ -#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ -#define WM8960_MONO 0x2aU /* OUT3 Volume */ -#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ -#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ -#define WM8960_BYPASS1 0x2dU /* Left Bypass */ -#define WM8960_BYPASS2 0x2eU /* Right Bypass */ -#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ -#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ -#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ -#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ -#define WM8960_PLL1 0x34U /* PLL (1) */ -#define WM8960_PLL2 0x35U /* PLL (2) */ -#define WM8960_PLL3 0x36U /* PLL (3) */ -#define WM8960_PLL4 0x37U /* PLL (4) */ - -/* Bitfield definition for register: LINVO */ -/* - * IPVU (RW) - * - * Input PGA Volume Update - * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) - */ -#define WM8960_LINVO_IPVU_MASK (0x100U) -#define WM8960_LINVO_IPVU_SHIFT (8U) -#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) -#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) - -/* - * LINMUTE (RW) - * - * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. - */ -#define WM8960_LINVO_LINMUTE_MASK (0x80U) -#define WM8960_LINVO_LINMUTE_SHIFT (7U) -#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) -#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) - -/* - * LIZC (RW) - * - * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately - */ -#define WM8960_LINVO_LIZC_MASK (0x40U) -#define WM8960_LINVO_LIZC_SHIFT (6U) -#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) -#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) - -/* - * LINVOL (RW) - * - * Left Input PGA Volume Control - * 111111 = +30dB - * 111110 = +29.25dB - * . . 0.75dB steps down to - * 000000 = -17.25dB - */ -#define WM8960_LINVO_LINVOL_MASK (0x3FU) -#define WM8960_LINVO_LINVOL_SHIFT (0U) -#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) -#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) - -/* Bitfield definition for register: RINVOL */ -/* - * IPVU (RW) - * - * Input PGA Volume Update - * Writing a 1 to this bit will cause left and right - * input PGA volumes to be updated (LINVOL and RINVOL) - */ -#define WM8960_RINVOL_IPVU_MASK (0x100U) -#define WM8960_RINVOL_IPVU_SHIFT (8U) -#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) -#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) - -/* - * RINMUTE (RW) - * - * Right Input PGA Analogue Mute - * 1 = Enable Mute - * 0 = Disable Mute - * Note: IPVU must be set to un-mute. - */ -#define WM8960_RINVOL_RINMUTE_MASK (0x80U) -#define WM8960_RINVOL_RINMUTE_SHIFT (7U) -#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) -#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) - -/* - * RIZC (RW) - * - * Right Input PGA Zero Cross Detector - * 1 = Change gain on zero cross only - * 0 = Change gain immediately - */ -#define WM8960_RINVOL_RIZC_MASK (0x40U) -#define WM8960_RINVOL_RIZC_SHIFT (6U) -#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) -#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) - -/* - * RINVOL (RW) - * - * Right Input PGA Volume Control - * 111111 = +30dB - * 111110 = +29.25dB - * . . 0.75dB steps down to - * 000000 = -17.25dB - */ -#define WM8960_RINVOL_RINVOL_MASK (0x3FU) -#define WM8960_RINVOL_RINVOL_SHIFT (0U) -#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) -#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) - -/* Bitfield definition for register: LOUT1 */ -/* - * OUT1VU (RW) - * - * Headphone Output PGA Volume Update - * Writing a 1 to this bit will cause left and right - * headphone output volumes to be updated - * (LOUT1VOL and ROUT1VOL) - */ -#define WM8960_LOUT1_OUT1VU_MASK (0x100U) -#define WM8960_LOUT1_OUT1VU_SHIFT (8U) -#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) -#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) - -/* - * LO1ZC (RW) - * - * Left Headphone Output Zero Cross Enable - * 0 = Change gain immediately - * 1 = Change gain on zero cross only - */ -#define WM8960_LOUT1_LO1ZC_MASK (0x80U) -#define WM8960_LOUT1_LO1ZC_SHIFT (7U) -#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) -#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) - -/* - * LOUT1VOL (RW) - * - * LOUT1 Volume - * 1111111 = +6dB - * … 1dB steps down to - * 0110000 = -73dB - * 0101111 to 0000000 = Analogue MUTE - */ -#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) -#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) -#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) -#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) - -/* Bitfield definition for register: ROUT1 */ -/* - * OUT1VU (RW) - * - * Headphone Output PGA Volume Update - * Writing a 1 to this bit will cause left and right - * headphone output volumes to be updated - * (LOUT1VOL and ROUT1VOL) - */ -#define WM8960_ROUT1_OUT1VU_MASK (0x100U) -#define WM8960_ROUT1_OUT1VU_SHIFT (8U) -#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) -#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) - -/* - * RO1ZC (RW) - * - * Right Headphone Output Zero Cross Enable - * 0 = Change gain immediately - * 1 = Change gain on zero cross only - */ -#define WM8960_ROUT1_RO1ZC_MASK (0x80U) -#define WM8960_ROUT1_RO1ZC_SHIFT (7U) -#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) -#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) - -/* - * ROUT1VOL (RW) - * - * ROUT1 Volume - * 1111111 = +6dB - * … 1dB steps down to - * 0110000 = -73dB - * 0101111 to 0000000 = Analogue MUTE - */ -#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) -#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) -#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) -#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) - -/* Bitfield definition for register: CLOCK1 */ -/* - * ADCDIV (RW) - * - * ADC Sample rate divider (Also determines - * ADCLRC in master mode) - * 000 = SYSCLK / (1.0 * 256) - * 001 = SYSCLK / (1.5 * 256) - * 010 = SYSCLK / (2 * 256) - * 011 = SYSCLK / (3 * 256) - * 100 = SYSCLK / (4 * 256) - * 101 = SYSCLK / (5.5 * 256) - * 110 = SYSCLK / (6 * 256) - * 111 = Reserved - */ -#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) -#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) -#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) -#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) - -/* - * DACDIV (RW) - * - * DAC Sample rate divider (Also determines - * DACLRC in master mode) - * 000 = SYSCLK / (1.0 * 256) - * 001 = SYSCLK / (1.5 * 256) - * 010 = SYSCLK / (2 * 256) - * 011 = SYSCLK / (3 * 256) - * 100 = SYSCLK / (4 * 256) - * 101 = SYSCLK / (5.5 * 256) - * 110 = SYSCLK / (6 * 256) - * 111 = Reserved - */ -#define WM8960_CLOCK1_DACDIV_MASK (0x38U) -#define WM8960_CLOCK1_DACDIV_SHIFT (3U) -#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) -#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) - -/* - * SYSCLKDIV (RW) - * - * SYSCLK Pre-divider. Clock source (MCLK or - * PLL output) will be divided by this value to - * generate SYSCLK. - * 00 = Divide SYSCLK by 1 - * 01 = Reserved - * 10 = Divide SYSCLK by 2 - * 11 = Reserved - */ -#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) -#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) -#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) -#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) - -/* - * CLKSEL (RW) - * - * SYSCLK Selection - * 0 = SYSCLK derived from MCLK - * 1 = SYSCLK derived from PLL output - */ -#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) -#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) -#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) -#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) - -/* Bitfield definition for register: DACCTL1 */ -/* - * DACDIV2 (RW) - * - * DAC 6dB Attenuate Enable - * 0 = Disabled (0dB) - * 1 = -6dB Enabled - */ -#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) -#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) -#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) -#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) - -/* - * ADCPOL (RW) - * - * ADC polarity control: - * 00 = Polarity not inverted - * 01 = ADC L inverted - * 10 = ADC R inverted - * 11 = ADC L and R inverted - */ -#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) -#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) -#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) -#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) - -/* - * DACMU (RW) - * - * DAC Digital Soft Mute - * 1 = Mute - * 0 = No mute (signal active) - */ -#define WM8960_DACCTL1_DACMU_MASK (0x8U) -#define WM8960_DACCTL1_DACMU_SHIFT (3U) -#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) -#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) - -/* - * DEEMPH (RW) - * - * De-emphasis Control - * 11 = 48kHz sample rate - * 10 = 44.1kHz sample rate - * 01 = 32kHz sample rate - * 00 = No de-emphasis - */ -#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) -#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) -#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) -#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) - -/* - * ADCHPD (RW) - * - * ADC High Pass Filter Disable - * 0 = Enable high pass filter on left and right channels - * 1 = Disable high pass filter on left and right channels - */ -#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) -#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) -#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) -#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) - -/* Bitfield definition for register: DACCTL2 */ -/* - * DACPOL (RW) - * - * DAC polarity control: - * 00 = Polarity not inverted - * 01 = DAC L inverted - * 10 = DAC R inverted - * 11 = DAC L and R inverted - */ -#define WM8960_DACCTL2_DACPOL_MASK (0x60U) -#define WM8960_DACCTL2_DACPOL_SHIFT (5U) -#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) -#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) - -/* - * DACSMM (RW) - * - * DAC Soft Mute Mode - * 0 = Disabling soft-mute (DACMU=0) will cause - * the volume to change immediately to the - * LDACVOL / RDACVOL settings - * 1 = Disabling soft-mute (DACMU=0) will cause - * the volume to ramp up gradually to the - * LDACVOL / RDACVOL settings - */ -#define WM8960_DACCTL2_DACSMM_MASK (0x8U) -#define WM8960_DACCTL2_DACSMM_SHIFT (3U) -#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) -#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) - -/* - * DACMR (RW) - * - * DAC Soft Mute Ramp Rate - * 0 = Fast ramp (24kHz at fs=48k, providing - * maximum delay of 10.7ms) - * 1 = Slow ramp (1.5kHz at fs=48k, providing - * maximum delay of 171ms) - */ -#define WM8960_DACCTL2_DACMR_MASK (0x4U) -#define WM8960_DACCTL2_DACMR_SHIFT (2U) -#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) -#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) - -/* - * DACSLOPE (RW) - * - * Selects DAC filter characteristics - * 0 = Normal mode - * 1 = Sloping stopband - */ -#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) -#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) -#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) -#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) - -/* Bitfield definition for register: IFACE1 */ -/* - * ALRSWAP (RW) - * - * Left/Right ADC Channel Swap - * 1 = Swap left and right ADC data in audio - * interface - * 0 = Output left and right data as normal - */ -#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) -#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) -#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) -#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) - -/* - * BCLKINV (RW) - * - * BCLK invert bit (for master and slave modes) - * 0 = BCLK not inverted - * 1 = BCLK inverted - */ -#define WM8960_IFACE1_BCLKINV_MASK (0x80U) -#define WM8960_IFACE1_BCLKINV_SHIFT (7U) -#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) -#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) - -/* - * MS (RW) - * - * Master / Slave Mode Control - * 0 = Enable slave mode - * 1 = Enable master mode - */ -#define WM8960_IFACE1_MS_MASK (0x40U) -#define WM8960_IFACE1_MS_SHIFT (6U) -#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) -#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) - -/* - * DLRSWAP (RW) - * - * Left/Right DAC Channel Swap - * 0 = Output left and right data as normal - * 1 = Swap left and right DAC data in audio interface - */ -#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) -#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) -#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) -#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) - -/* - * LRP (RW) - * - * Right, left and I2S modes – LRCLK polarity - * 0 = normal LRCLK polarity - * 1 = invert LRCLK polarity - * DSP Mode – mode A/B select - * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) - * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) - */ -#define WM8960_IFACE1_LRP_MASK (0x10U) -#define WM8960_IFACE1_LRP_SHIFT (4U) -#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) -#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) - -/* - * WL (RW) - * - * Audio Data Word Length - * 00 = 16 bits - * 01 = 20 bits - * 10 = 24 bits - * 11 = 32 bits (see Note) - */ -#define WM8960_IFACE1_WL_MASK (0xCU) -#define WM8960_IFACE1_WL_SHIFT (2U) -#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) -#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) - -/* - * FORMAT (RW) - * - * 00 = Right justified - * 01 = Left justified - * 10 = I2S Format - * 11 = DSP Mode - */ -#define WM8960_IFACE1_FORMAT_MASK (0x3U) -#define WM8960_IFACE1_FORMAT_SHIFT (0U) -#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) -#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) - -/* Bitfield definition for register: CLOCK2 */ -/* - * DCLKDIV (RW) - * - * Class D switching clock divider. - * 000 = SYSCLK / 1.5 (Not recommended) - * 001 = SYSCLK / 2 - * 010 = SYSCLK / 3 - * 011 = SYSCLK / 4 - * 100 = SYSCLK / 6 - * 101 = SYSCLK / 8 - * 110 = SYSCLK / 12 - * 111 = SYSCLK / 16 - */ -#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) -#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) -#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) -#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) - -/* - * BCLKDIV (RW) - * - * BCLK Frequency (Master Mode) - * 0000 = SYSCLK - * 0001 = SYSCLK / 1.5 - * 0010 = SYSCLK / 2 - * 0011 = SYSCLK / 3 - * 0100 = SYSCLK / 4 - * 0101 = SYSCLK / 5.5 - * 0110 = SYSCLK / 6 - * 0111 = SYSCLK / 8 - * 1000 = SYSCLK / 11 - * 1001 = SYSCLK / 12 - * 1010 = SYSCLK / 16 - * 1011 = SYSCLK / 22 - * 1100 = SYSCLK / 24 - * 1101 to 1111 = SYSCLK / 32 - */ -#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) -#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) -#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) -#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) - -/* Bitfield definition for register: IFACE2 */ -/* - * ALRCGPIO (RW) - * - * ADCLRC/GPIO1 Pin Function Select - * 0 = ADCLRC frame clock for ADC - * 1 = GPIO pin - */ -#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) -#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) -#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) -#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) - -/* - * WL8 (RW) - * - * 8-Bit Word Length Select (Used with - * companding) - * 0 = Off - * 1 = Device operates in 8-bit mode. - */ -#define WM8960_IFACE2_WL8_MASK (0x20U) -#define WM8960_IFACE2_WL8_SHIFT (5U) -#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) -#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) - -/* - * DACCOMP (RW) - * - * DAC companding - * 00 = off - * 01 = reserved - * 10 = μ-law - * 11 = A-law - */ -#define WM8960_IFACE2_DACCOMP_MASK (0x18U) -#define WM8960_IFACE2_DACCOMP_SHIFT (3U) -#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) -#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) - -/* - * ADCCOMP (RW) - * - * ADC companding - * 00 = off - * 01 = reserved - * 10 = μ-law - * 11 = A-law - */ -#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) -#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) -#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) -#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) - -/* - * LOOPBACK (RW) - * - * Digital Loopback Function - * 0 = No loopback. - * 1 = Loopback enabled, ADC data output is fed - * directly into DAC data input - */ -#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) -#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) -#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) -#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) - -/* Bitfield definition for register: LDAC */ -/* - * DACVU (RW) - * - * DAC Volume Update - * Writing a 1 to this bit will cause left and right - * DAC volumes to be updated (LDACVOL and RDACVOL) - */ -#define WM8960_LDAC_DACVU_MASK (0x100U) -#define WM8960_LDAC_DACVU_SHIFT (8U) -#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) -#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) - -/* - * LDACVOL (RW) - * - * Left DAC Digital Volume Control - * 0000 0000 = Digital Mute - * 0000 0001 = -127dB - * 0000 0010 = -126.5dB - * ... 0.5dB steps up to - * 1111 1111 = 0dB - */ -#define WM8960_LDAC_LDACVOL_MASK (0xFFU) -#define WM8960_LDAC_LDACVOL_SHIFT (0U) -#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) -#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) - -/* Bitfield definition for register: RDAC */ -/* - * DACVU (RW) - * - * DAC Volume Update - * Writing a 1 to this bit will cause left and right - * DAC volumes to be updated (LDACVOL and RDACVOL) - */ -#define WM8960_RDAC_DACVU_MASK (0x100U) -#define WM8960_RDAC_DACVU_SHIFT (8U) -#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) -#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) - -/* - * RDACVOL (RW) - * - * Right DAC Digital Volume Control - * 0000 0000 = Digital Mute - * 0000 0001 = -127dB - * 0000 0010 = -126.5dB - * ... 0.5dB steps up to - * 1111 1111 = 0dB - */ -#define WM8960_RDAC_RDACVOL_MASK (0xFFU) -#define WM8960_RDAC_RDACVOL_SHIFT (0U) -#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) -#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) - -/* Bitfield definition for register: RESET */ -/* - * RESET (RW) - * - * Writing to this register resets all registers to their default state. - */ -#define WM8960_RESET_RESET_MASK (0x1FFU) -#define WM8960_RESET_RESET_SHIFT (0U) -#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) -#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) - -/* Bitfield definition for register: 3D */ -/* - * 3DUC (RW) - * - * 3D Enhance Filter Upper Cut-Off Frequency - * 0 = High (Recommended for fs>=32kHz) - * 1 = Low (Recommended for fs<32kHz) - */ -#define WM8960_3D_3DUC_MASK (0x40U) -#define WM8960_3D_3DUC_SHIFT (6U) -#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) -#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) - -/* - * 3DLC (RW) - * - * 3D Enhance Filter Lower Cut-Off Frequency - * 0 = Low (Recommended for fs>=32kHz) - * 1 = High (Recommended for fs<32kHz) - */ -#define WM8960_3D_3DLC_MASK (0x20U) -#define WM8960_3D_3DLC_SHIFT (5U) -#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) -#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) - -/* - * 3DDEPTH (RW) - * - * 3D Stereo Depth - * 0000 = 0% (minimum 3D effect) - * 0001 = 6.67% - * .... - * 1110 = 93.3% - * 1111 = 100% (maximum 3D effect) - */ -#define WM8960_3D_3DDEPTH_MASK (0x1EU) -#define WM8960_3D_3DDEPTH_SHIFT (1U) -#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) -#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) - -/* - * 3DEN (RW) - * - * 3D Stereo Enhancement Enable - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_3D_3DEN_MASK (0x1U) -#define WM8960_3D_3DEN_SHIFT (0U) -#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) -#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) - -/* Bitfield definition for register: ALC1 */ -/* - * ALCSEL (RW) - * - * ALC Function Select - * 00 = ALC off (PGA gain set by register) - * 01 = Right channel only - * 10 = Left channel only - * 11 = Stereo (PGA registers unused) Note: - * ensure that LINVOL and RINVOL settings - * (reg. 0 and 1) are the same before entering this mode. - */ -#define WM8960_ALC1_ALCSEL_MASK (0x180U) -#define WM8960_ALC1_ALCSEL_SHIFT (7U) -#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) -#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) - -/* - * MAXGAIN (RW) - * - * Set Maximum Gain of PGA (During ALC - * operation) - * 111 : +30dB - * 110 : +24dB - * ….(-6dB steps) - * 001 : -6dB - * 000 : -12dB - */ -#define WM8960_ALC1_MAXGAIN_MASK (0x70U) -#define WM8960_ALC1_MAXGAIN_SHIFT (4U) -#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) -#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) - -/* - * ALCL (RW) - * - * ALC Target (Sets signal level at ADC input) - * 0000 = -22.5dB FS - * 0001 = -21.0dB FS - * … (1.5dB steps) - * 1101 = -3.0dB FS - * 1110 = -1.5dB FS - * 1111 = -1.5dB FS - */ -#define WM8960_ALC1_ALCL_MASK (0xFU) -#define WM8960_ALC1_ALCL_SHIFT (0U) -#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) -#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) - -/* Bitfield definition for register: ALC2 */ -/* - * MINGAIN (RW) - * - * Set Minimum Gain of PGA (During ALC - * operation) - * 000 = -17.25dB - * 001 = -11.25dB - * 010 = -5.25dB - * 011 = +0.75dB - * 100 = +6.75dB - * 101 = +12.75dB - * 110 = +18.75dB - * 111 = +24.75dB - */ -#define WM8960_ALC2_MINGAIN_MASK (0x70U) -#define WM8960_ALC2_MINGAIN_SHIFT (4U) -#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) -#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) - -/* - * HLD (RW) - * - * ALC hold time before gain is increased. - * 0000 = 0ms - * 0001 = 2.67ms - * 0010 = 5.33ms - * … (time doubles with every step) - * 1111 = 43.691s - */ -#define WM8960_ALC2_HLD_MASK (0xFU) -#define WM8960_ALC2_HLD_SHIFT (0U) -#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) -#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) - -/* Bitfield definition for register: ALC3 */ -/* - * ALCMODE (RW) - * - * Determines the ALC mode of operation: - * 0 = ALC mode - * 1 = Limiter mode - */ -#define WM8960_ALC3_ALCMODE_MASK (0x100U) -#define WM8960_ALC3_ALCMODE_SHIFT (8U) -#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) -#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) - -/* - * DCY (RW) - * - * ALC decay (gain ramp-up) time - * 0000 = 24ms - * 0001 = 48ms - * 0010 = 96ms - * … (time doubles with every step) - * 1010 or higher = 24.58s - */ -#define WM8960_ALC3_DCY_MASK (0xF0U) -#define WM8960_ALC3_DCY_SHIFT (4U) -#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) -#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) - -/* - * ATK (RW) - * - * ALC attack (gain ramp-down) time - * 0000 = 6ms - * 0001 = 12ms - * 0010 = 24ms - * … (time doubles with every step) - * 1010 or higher = 6.14s - */ -#define WM8960_ALC3_ATK_MASK (0xFU) -#define WM8960_ALC3_ATK_SHIFT (0U) -#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) -#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) - -/* Bitfield definition for register: NOISEG */ -/* - * NGTH (RW) - * - * Noise gate threshold - * 00000 -76.5dBfs - * 00001 -75dBfs - * … 1.5 dB steps - * 11110 -31.5dBfs - * 11111 -30dBfs - */ -#define WM8960_NOISEG_NGTH_MASK (0xF8U) -#define WM8960_NOISEG_NGTH_SHIFT (3U) -#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) -#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) - -/* - * NGAT (RW) - * - * Noise gate function enable - * 0 = disable - * 1 = enable - */ -#define WM8960_NOISEG_NGAT_MASK (0x1U) -#define WM8960_NOISEG_NGAT_SHIFT (0U) -#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) -#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) - -/* Bitfield definition for register: LADC */ -/* - * ADCVU (RW) - * - * ADC Volume Update - * Writing a 1 to this bit will cause left and right - * ADC volumes to be updated (LADCVOL and - * RADCVOL) - */ -#define WM8960_LADC_ADCVU_MASK (0x100U) -#define WM8960_LADC_ADCVU_SHIFT (8U) -#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) -#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) - -/* - * LADCVOL (RW) - * - * Left ADC Digital Volume Control - * 0000 0000 = Digital Mute - * 0000 0001 = -97dB - * 0000 0010 = -96.5dB - * ... 0.5dB steps up to - * 1111 1111 = +30dB - */ -#define WM8960_LADC_LADCVOL_MASK (0xFFU) -#define WM8960_LADC_LADCVOL_SHIFT (0U) -#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) -#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) - -/* Bitfield definition for register: RADC */ -/* - * ADCVU (RW) - * - * ADC Volume Update - * Writing a 1 to this bit will cause left and right - * ADC volumes to be updated (LADCVOL and RADCVOL) - */ -#define WM8960_RADC_ADCVU_MASK (0x100U) -#define WM8960_RADC_ADCVU_SHIFT (8U) -#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) -#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) - -/* - * RADCVOL (RW) - * - * Right ADC Digital Volume Control - * 0000 0000 = Digital Mute - * 0000 0001 = -97dB - * 0000 0010 = -96.5dB - * ... 0.5dB steps up to - * 1111 1111 = +30dB - */ -#define WM8960_RADC_RADCVOL_MASK (0xFFU) -#define WM8960_RADC_RADCVOL_SHIFT (0U) -#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) -#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) - -/* Bitfield definition for register: ADDCTL1 */ -/* - * TSDEN (RW) - * - * Thermal Shutdown Enable - * 0 = Thermal shutdown disabled - * 1 = Thermal shutdown enabled - * (TSENSEN must be enabled for this function to work) - */ -#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) -#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) -#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) -#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) - -/* - * VSEL (RW) - * - * Analogue Bias Optimisation - * 00 = Reserved - * 01 = Increased bias current optimized for - * AVDD=2.7V - * 1X = Lowest bias current, optimized for - * AVDD=3.3V - */ -#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) -#define WM8960_ADDCTL1_VSEL_SHIFT (6U) -#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) -#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) - -/* - * DMONOMIX (RW) - * - * DAC Mono Mix - * 0 = Stereo - * 1 = Mono (Mono MIX output on enabled DACs - */ -#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) -#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) -#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) -#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) - -/* - * DATSEL (RW) - * - * ADC Data Output Select - * 00: left data = left ADC; right data =right ADC - * 01: left data = left ADC; right data = left ADC - * 10: left data = right ADC; right data =right ADC - * 11: left data = right ADC; right data = left ADC - */ -#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) -#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) -#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) -#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) - -/* - * TOCLKSEL (RW) - * - * Slow Clock Select (Used for volume update - * timeouts and for jack detect debounce) - * 0 = SYSCLK / 221 (Slower Response) - * 1 = SYSCLK / 219 (Faster Response) - */ -#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) -#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) -#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) -#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) - -/* - * TOEN (RW) - * - * Enables Slow Clock for Volume Update Timeout - * and Jack Detect Debounce - * 0 = Slow clock disabled - * 1 = Slow clock enabled - */ -#define WM8960_ADDCTL1_TOEN_MASK (0x1U) -#define WM8960_ADDCTL1_TOEN_SHIFT (0U) -#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) -#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) - -/* Bitfield definition for register: ADDCTL2 */ -/* - * HPSWEN (RW) - * - * Headphone Switch Enable - * 0 = Headphone switch disabled - * 1 = Headphone switch enabled - */ -#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) -#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) -#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) -#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) - -/* - * HPSWPOL (RW) - * - * Headphone Switch Polarity - * 0 = HPDETECT high = headphone - * 1 = HPDETECT high = speaker - */ -#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) -#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) -#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) -#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) - -/* - * TRIS (RW) - * - * Tristates ADCDAT and switches ADCLRC, - * DACLRC and BCLK to inputs. - * 0 = ADCDAT is an output; ADCLRC, DACLRC - * and BCLK are inputs (slave mode) or outputs - * (master mode) - * 1 = ADCDAT is tristated; DACLRC and BCLK - * are inputs; ADCLRC is an input (when not - * configured as a GPIO) - */ -#define WM8960_ADDCTL2_TRIS_MASK (0x8U) -#define WM8960_ADDCTL2_TRIS_SHIFT (3U) -#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) -#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) - -/* - * LRCM (RW) - * - * Selects disable mode for ADCLRC and DACLRC - * (Master mode) - * 0 = ADCLRC disabled when ADC (Left and - * Right) disabled; DACLRC disabled when - * DAC (Left and Right) disabled. - * 1 = ADCLRC and DACLRC disabled only when - * ADC (Left and Right) and DAC (Left and Right) - * are disabled. - */ -#define WM8960_ADDCTL2_LRCM_MASK (0x4U) -#define WM8960_ADDCTL2_LRCM_SHIFT (2U) -#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) -#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) - -/* Bitfield definition for register: POWER1 */ -/* - * VMIDSEL (RW) - * - * Vmid Divider Enable and Select - * 00 = Vmid disabled (for OFF mode) - * 01 = 2 x 50k divider enabled (for playback / - * record) - * 10 = 2 x 250k divider enabled (for low-power - * standby) - * 11 = 2 x 5k divider enabled (for fast start-up) - */ -#define WM8960_POWER1_VMIDSEL_MASK (0x180U) -#define WM8960_POWER1_VMIDSEL_SHIFT (7U) -#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) -#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) - -/* - * VREF (RW) - * - * VREF (necessary for all other functions) - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_VREF_MASK (0x40U) -#define WM8960_POWER1_VREF_SHIFT (6U) -#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) -#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) - -/* - * AINL (RW) - * - * Analogue in PGA Left - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_AINL_MASK (0x20U) -#define WM8960_POWER1_AINL_SHIFT (5U) -#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) -#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) - -/* - * AINR (RW) - * - * Analogue in PGA Right - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_AINR_MASK (0x10U) -#define WM8960_POWER1_AINR_SHIFT (4U) -#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) -#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) - -/* - * ADCL (RW) - * - * ADC Left - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_ADCL_MASK (0x8U) -#define WM8960_POWER1_ADCL_SHIFT (3U) -#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) -#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) - -/* - * ADCR (RW) - * - * ADC Right - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_ADCR_MASK (0x4U) -#define WM8960_POWER1_ADCR_SHIFT (2U) -#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) -#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) - -/* - * MICB (RW) - * - * MICBIAS - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER1_MICB_MASK (0x2U) -#define WM8960_POWER1_MICB_SHIFT (1U) -#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) -#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) - -/* - * DIGENB (RW) - * - * Master Clock Disable - * 0 = Master clock enabled - * 1 = Master clock disabled - */ -#define WM8960_POWER1_DIGENB_MASK (0x1U) -#define WM8960_POWER1_DIGENB_SHIFT (0U) -#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) -#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) - -/* Bitfield definition for register: POWER2 */ -/* - * DACL (RW) - * - * DAC Left - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_DACL_MASK (0x100U) -#define WM8960_POWER2_DACL_SHIFT (8U) -#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) -#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) - -/* - * DACR (RW) - * - * DAC Right - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_DACR_MASK (0x80U) -#define WM8960_POWER2_DACR_SHIFT (7U) -#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) -#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) - -/* - * LOUT1 (RW) - * - * LOUT1 Output Buffer - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_LOUT1_MASK (0x40U) -#define WM8960_POWER2_LOUT1_SHIFT (6U) -#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) -#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) - -/* - * ROUT1 (RW) - * - * ROUT1 Output Buffer - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_ROUT1_MASK (0x20U) -#define WM8960_POWER2_ROUT1_SHIFT (5U) -#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) -#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) - -/* - * SPKL (RW) - * - * SPK_LP/SPK_LN Output Buffers - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_SPKL_MASK (0x10U) -#define WM8960_POWER2_SPKL_SHIFT (4U) -#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) -#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) - -/* - * SPKR (RW) - * - * SPK_RP/SPK_RN Output Buffers - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_SPKR_MASK (0x8U) -#define WM8960_POWER2_SPKR_SHIFT (3U) -#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) -#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) - -/* - * OUT3 (RW) - * - * OUT3 Output Buffer - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_OUT3_MASK (0x2U) -#define WM8960_POWER2_OUT3_SHIFT (1U) -#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) -#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) - -/* - * PLL_EN (RW) - * - * PLL Enable - * 0 = Power down - * 1 = Power up - */ -#define WM8960_POWER2_PLL_EN_MASK (0x1U) -#define WM8960_POWER2_PLL_EN_SHIFT (0U) -#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) -#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) - -/* Bitfield definition for register: ADDCTL3 */ -/* - * VROI (RW) - * - * VREF to Analogue Output Resistance (Disabled - * Outputs) - * 0 = 500 VMID to output - * 1 = 20k VMID to output - */ -#define WM8960_ADDCTL3_VROI_MASK (0x40U) -#define WM8960_ADDCTL3_VROI_SHIFT (6U) -#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) -#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) - -/* - * OUT3CAP (RW) - * - * Capless Mode Headphone Switch Enable - * 0 = OUT3 unaffected by jack detect events - * 1 = OUT3 enabled and disabled together with - * HP_L and HP_R in response to jack detect - * events - */ -#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) -#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) -#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) -#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) - -/* - * ADC_ALC_SR (RW) - * - * ALC Sample Rate - * 000 = 44.1k / 48k - * 001 = 32k - * 010 = 22.05k / 24k - * 011 = 16k - * 100 = 11.25k / 12k - * 101 = 8k - * 110 and 111 = Reserved - */ -#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) -#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) -#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) -#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) - -/* Bitfield definition for register: APOP1 */ -/* - * POBCTRL (RW) - * - * Selects the bias current source for output - * amplifiers and VMID buffer - * 0 = VMID / R bias - * 1 = VGS / R bias - */ -#define WM8960_APOP1_POBCTRL_MASK (0x80U) -#define WM8960_APOP1_POBCTRL_SHIFT (7U) -#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) -#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) - -/* - * BUFDCOPEN (RW) - * - * Enables the VGS / R current generator - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) -#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) -#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) -#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) - -/* - * BUFIOEN (RW) - * - * Enables the VGS / R current generator and the - * analogue input and output bias - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_APOP1_BUFIOEN_MASK (0x8U) -#define WM8960_APOP1_BUFIOEN_SHIFT (3U) -#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) -#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) - -/* - * SOFT_ST (RW) - * - * Enables VMID soft start - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_APOP1_SOFT_ST_MASK (0x4U) -#define WM8960_APOP1_SOFT_ST_SHIFT (2U) -#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) -#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) - -/* - * HPSTBY (RW) - * - * Headphone Amplifier Standby - * 0 = Standby mode disabled (Normal operation) - * 1 = Standby mode enabled - */ -#define WM8960_APOP1_HPSTBY_MASK (0x1U) -#define WM8960_APOP1_HPSTBY_SHIFT (0U) -#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) -#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) - -/* Bitfield definition for register: APOP2 */ -/* - * DISOP (RW) - * - * Discharges the DC-blocking headphone - * capacitors on HP_L and HP_R - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_APOP2_DISOP_MASK (0x40U) -#define WM8960_APOP2_DISOP_SHIFT (6U) -#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) -#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) - -/* - * DRES (RW) - * - * DRES determines the value of the resistors used - * to discharge the DC-blocking headphone - * capacitors when DISOP=1 - * DRES[1:0] Resistance (Ohms) - * 0 0 400 - * 0 1 200 - * 1 0 600 - * 1 1 150 - */ -#define WM8960_APOP2_DRES_MASK (0x30U) -#define WM8960_APOP2_DRES_SHIFT (4U) -#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) -#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) - -/* Bitfield definition for register: LINPATH */ -/* - * LMN1 (RW) - * - * Connect LINPUT1 to inverting input of Left Input - * PGA - * 0 = LINPUT1 not connected to PGA - * 1 = LINPUT1 connected to PGA - */ -#define WM8960_LINPATH_LMN1_MASK (0x100U) -#define WM8960_LINPATH_LMN1_SHIFT (8U) -#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) -#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) - -/* - * LMP3 (RW) - * - * Connect LINPUT3 to non-inverting input of Left - * Input PGA - * 0 = LINPUT3 not connected to PGA - * 1 = LINPUT3 connected to PGA (Constant input - * impedance) - */ -#define WM8960_LINPATH_LMP3_MASK (0x80U) -#define WM8960_LINPATH_LMP3_SHIFT (7U) -#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) -#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) - -/* - * LMP2 (RW) - * - * Connect LINPUT2 to non-inverting input of Left - * Input PGA - * 0 = LINPUT2 not connected to PGA - * 1 = LINPUT2 connected to PGA (Constant input impedance) - */ -#define WM8960_LINPATH_LMP2_MASK (0x40U) -#define WM8960_LINPATH_LMP2_SHIFT (6U) -#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) -#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) - -/* - * LMICBOOST (RW) - * - * Left Channel Input PGA Boost Gain - * 00 = +0dB - * 01 = +13dB - * 10 = +20dB - * 11 = +29dB - */ -#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) -#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) -#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) -#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) - -/* - * LMIC2B (RW) - * - * Connect Left Input PGA to Left Input Boost Mixer - * 0 = Not connected - * 1 = Connected - */ -#define WM8960_LINPATH_LMIC2B_MASK (0x8U) -#define WM8960_LINPATH_LMIC2B_SHIFT (3U) -#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) -#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) - -/* Bitfield definition for register: RINPATH */ -/* - * RMN1 (RW) - * - * Connect RINPUT1 to inverting input of Right - * Input PGA - * 0 = RINPUT1 not connected to PGA - * 1 = RINPUT1 connected to PGA - */ -#define WM8960_RINPATH_RMN1_MASK (0x100U) -#define WM8960_RINPATH_RMN1_SHIFT (8U) -#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) -#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) - -/* - * RMP3 (RW) - * - * Connect RINPUT3 to non-inverting input of Right - * Input PGA - * 0 = RINPUT3 not connected to PGA - * 1 = RINPUT3 connected to PGA (Constant input impedance) - */ -#define WM8960_RINPATH_RMP3_MASK (0x80U) -#define WM8960_RINPATH_RMP3_SHIFT (7U) -#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) -#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) - -/* - * RMP2 (RW) - * - * Connect RINPUT2 to non-inverting input of Right - * Input PGA - * 0 = RINPUT2 not connected to PGA - * 1 = RINPUT2 connected to PGA (Constant input - * impedance) - */ -#define WM8960_RINPATH_RMP2_MASK (0x40U) -#define WM8960_RINPATH_RMP2_SHIFT (6U) -#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) -#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) - -/* - * RMICBOOST (RW) - * - * Right Channel Input PGA Boost Gain - * 00 = +0dB - * 01 = +13dB - * 10 = +20dB - * 11 = +29dB - */ -#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) -#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) -#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) -#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) - -/* - * RMIC2B (RW) - * - * Connect Right Input PGA to Right Input Boost - * Mixer - * 0 = Not connected - * 1 = Connected - */ -#define WM8960_RINPATH_RMIC2B_MASK (0x8U) -#define WM8960_RINPATH_RMIC2B_SHIFT (3U) -#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) -#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) - -/* Bitfield definition for register: LOUTMIX */ -/* - * LD2LO (RW) - * - * Left DAC to Left Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) -#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) -#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) -#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) - -/* - * LI2LO (RW) - * - * LINPUT3 to Left Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) -#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) -#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) -#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) - -/* - * LI2LOVOL (RW) - * - * LINPUT3 to Left Output Mixer Volume - * 000 = 0dB - * ...(3dB steps) - * 111 = -21dB - */ -#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) -#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) -#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) -#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) - -/* Bitfield definition for register: ROUTMIX */ -/* - * RD2RO (RW) - * - * Right DAC to Right Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) -#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) -#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) -#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) - -/* - * RI2RO (RW) - * - * RINPUT3 to Right Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) -#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) -#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) -#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) - -/* - * RI2ROVOL (RW) - * - * RINPUT3 to Right Output Mixer Volume - * 000 = 0dB - * ...(3dB steps) - * 111 = -21dB - */ -#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) -#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) -#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) -#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) - -/* Bitfield definition for register: MONOMIX1 */ -/* - * L2MO (RW) - * - * Left Output Mixer to Mono Output Mixer Control - * 0 = Left channel mix disabled - * 1 = Left channel mix enabled - */ -#define WM8960_MONOMIX1_L2MO_MASK (0x80U) -#define WM8960_MONOMIX1_L2MO_SHIFT (7U) -#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) -#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) - -/* Bitfield definition for register: MONOMIX2 */ -/* - * R2MO (RW) - * - * Right Output Mixer to Mono Output Mixer Control - * 0 = Right channel mix disabled - * 1 = Right channel mix enabled - */ -#define WM8960_MONOMIX2_R2MO_MASK (0x80U) -#define WM8960_MONOMIX2_R2MO_SHIFT (7U) -#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) -#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) - -/* Bitfield definition for register: LOUT2 */ -/* - * SPKVU (RW) - * - * Speaker Volume Update - * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) - */ -#define WM8960_LOUT2_SPKVU_MASK (0x100U) -#define WM8960_LOUT2_SPKVU_SHIFT (8U) -#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) -#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) - -/* - * SPKLZC (RW) - * - * Left Speaker Zero Cross Enable - * 1 = Change gain on zero cross only - * 0 = Change gain immediately - */ -#define WM8960_LOUT2_SPKLZC_MASK (0x80U) -#define WM8960_LOUT2_SPKLZC_SHIFT (7U) -#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) -#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) - -/* - * SPKLVOL (RW) - * - * SPK_LP/SPK_LN Volume - * 1111111 = +6dB - * … 1dB steps down to - * 0110000 = -73dB - * 0101111 to 0000000 = Analogue MUTE - */ -#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) -#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) -#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) -#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) - -/* Bitfield definition for register: ROUT2 */ -/* - * SPKVU (RW) - * - * Speaker Volume Update - * Writing a 1 to this bit will cause left and right - * speaker volumes to be updated (SPKLVOL and SPKRVOL) - */ -#define WM8960_ROUT2_SPKVU_MASK (0x100U) -#define WM8960_ROUT2_SPKVU_SHIFT (8U) -#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) -#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) - -/* - * SPKRZC (RW) - * - * Right Speaker Zero Cross Enable - * 1 = Change gain on zero cross only - * 0 = Change gain immediately - */ -#define WM8960_ROUT2_SPKRZC_MASK (0x80U) -#define WM8960_ROUT2_SPKRZC_SHIFT (7U) -#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) -#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) - -/* - * SPKRVOL (RW) - * - * SPK_RP/SPK_RN Volume - * 1111111 = +6dB - * … 1dB steps down to - * 0110000 = -73dB - * 0101111 to 0000000 = Analogue MUTE - */ -#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) -#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) -#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) -#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) - -/* Bitfield definition for register: MONO */ -/* - * MOUTVOL (RW) - * - * Mono Output Mixer Volume Control - * 0 = 0dB - * 1 = -6dB - */ -#define WM8960_MONO_MOUTVOL_MASK (0x40U) -#define WM8960_MONO_MOUTVOL_SHIFT (6U) -#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) -#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) - -/* Bitfield definition for register: INBMIX1 */ -/* - * LIN3BOOST (RW) - * - * LINPUT3 to Boost Mixer Gain - * 000 = Mute - * 001 = -12dB - * ...3dB steps up to - * 111 = +6dB - */ -#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) -#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) -#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) -#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) - -/* - * LIN2BOOST (RW) - * - * LINPUT2 to Boost Mixer Gain - * 000 = Mute - * 001 = -12dB - * ...3dB steps up to - * 111 = +6dB - */ -#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) -#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) -#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) -#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) - -/* Bitfield definition for register: INBMIX2 */ -/* - * RIN3BOOST (RW) - * - * RINPUT3 to Boost Mixer Gain - * 000 = Mute - * 001 = -12dB - * ...3dB steps up to - * 111 = +6dB - */ -#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) -#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) -#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) -#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) - -/* - * RIN2BOOST (RW) - * - * RINPUT2 to Boost Mixer Gain - * 000 = Mute - * 001 = -12dB - * ...3dB steps up to - * 111 = +6dB - */ -#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) -#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) -#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) -#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) - -/* Bitfield definition for register: BYPASS1 */ -/* - * LB2LO (RW) - * - * Left Input Boost Mixer to Left Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_BYPASS1_LB2LO_MASK (0x80U) -#define WM8960_BYPASS1_LB2LO_SHIFT (7U) -#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) -#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) - -/* - * LB2LOVOL (RW) - * - * Left Input Boost Mixer to Left Output Mixer - * Volume - * 000 = 0dB - * ...(3dB steps) - * 111 = -21dB - */ -#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) -#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) -#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) -#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) - -/* Bitfield definition for register: BYPASS2 */ -/* - * RB2RO (RW) - * - * Right Input Boost Mixer to Right Output Mixer - * 0 = Disable (Mute) - * 1 = Enable Path - */ -#define WM8960_BYPASS2_RB2RO_MASK (0x80U) -#define WM8960_BYPASS2_RB2RO_SHIFT (7U) -#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) -#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) - -/* - * RB2ROVOL (RW) - * - * Right Input Boost Mixer to Right Output Mixer - * Volume - * 000 = 0dB - * ...(3dB steps) - * 111 = -21dB - */ -#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) -#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) -#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) -#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) - -/* Bitfield definition for register: POWER3 */ -/* - * LMIC (RW) - * - * Left Channel Input PGA Enable - * 0 = PGA disabled - * 1 = PGA enabled (if AINL = 1) - */ -#define WM8960_POWER3_LMIC_MASK (0x20U) -#define WM8960_POWER3_LMIC_SHIFT (5U) -#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) -#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) - -/* - * RMIC (RW) - * - * Right Channel Input PGA Enable - * 0 = PGA disabled - * 1 = PGA enabled (if AINR = 1) - */ -#define WM8960_POWER3_RMIC_MASK (0x10U) -#define WM8960_POWER3_RMIC_SHIFT (4U) -#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) -#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) - -/* - * LOMIX (RW) - * - * Left Output Mixer Enable Control - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_POWER3_LOMIX_MASK (0x8U) -#define WM8960_POWER3_LOMIX_SHIFT (3U) -#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) -#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) - -/* - * ROMIX (RW) - * - * Right Output Mixer Enable Control - * 0 = Disabled - * 1 = Enabled - */ -#define WM8960_POWER3_ROMIX_MASK (0x4U) -#define WM8960_POWER3_ROMIX_SHIFT (2U) -#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) -#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) - -/* Bitfield definition for register: ADDCTL4 */ -/* - * GPIOPOL (RW) - * - * GPIO Polarity Invert - * 0 = Non inverted - * 1 = Inverted - */ -#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) -#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) -#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) -#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) - -/* - * GPIOSEL (RW) - * - * ADCLRC/GPIO1 GPIO Function Select: - * 000 = Jack detect input - * 001 = Reserved - * 010 = Temperature ok - * 011 = Debounced jack detect output - * 100 = SYSCLK output - * 101 = PLL lock - * 110 = Logic 0 - * 111 = Logic 1 - */ -#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) -#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) -#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) -#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) - -/* - * HPSEL (RW) - * - * Headphone Switch Input Select - * 0X = GPIO1 used for jack detect input (Requires - * ADCLRC pin to be configured as a GPIO) - * 10 = JD2 used for jack detect input - * 11 = JD3 used for jack detect input - */ -#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) -#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) -#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) -#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) - -/* - * TSENSEN (RW) - * - * Temperature Sensor Enable - * 0 = Temperature sensor disabled - * 1 = Temperature sensor enabled - */ -#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) -#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) -#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) -#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) - -/* - * MBSEL (RW) - * - * Microphone Bias Voltage Control - * 0 = 0.9 * AVDD - * 1 = 0.65 * AVDD - */ -#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) -#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) -#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) -#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) - -/* Bitfield definition for register: CLASSD1 */ -/* - * SPK_OP_EN (RW) - * - * Enable Class D Speaker Outputs - * 00 = Off - * 01 = Left speaker only - * 10 = Right speaker only - * 11 = Left and right speakers enabled - */ -#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) -#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) -#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) -#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) - -/* Bitfield definition for register: CLASSD3 */ -/* - * DCGAIN (RW) - * - * DC Speaker Boost (Boosts speaker DC output - * level by up to 1.8 x on left and right channels) - * 000 = 1.00x boost (+0dB) - * 001 = 1.27x boost (+2.1dB) - * 010 = 1.40x boost (+2.9dB) - * 011 = 1.52x boost (+3.6dB) - * 100 = 1.67x boost (+4.5dB) - * 101 = 1.8x boost (+5.1dB) - * 110 to 111 = Reserved - */ -#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) -#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) -#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) -#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) - -/* - * ACGAIN (RW) - * - * AC Speaker Boost (Boosts speaker AC output - * signal by up to 1.8 x on left and right channels) - * 000 = 1.00x boost (+0dB) - * 001 = 1.27x boost (+2.1dB) - * 010 = 1.40x boost (+2.9dB) - * 011 = 1.52x boost (+3.6dB) - * 100 = 1.67x boost (+4.5dB) - * 101 = 1.8x boost (+5.1dB) - * 110 to 111 = Reserved - */ -#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) -#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) -#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) -#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) - -/* Bitfield definition for register: PLL1 */ -/* - * OPCLKDIV (RW) - * - * SYSCLK Output to GPIO Clock Division ratio - * 000 = SYSCLK - * 001 = SYSCLK / 2 - * 010 = SYSCLK / 3 - * 011 = SYSCLK / 4 - * 100 = SYSCLK / 5.5 - * 101 = SYSCLK / 6 - */ -#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) -#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) -#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) -#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) - -/* - * SDM (RW) - * - * Enable Integer Mode - * 0 = Integer mode - * 1 = Fractional mode - */ -#define WM8960_PLL1_SDM_MASK (0x20U) -#define WM8960_PLL1_SDM_SHIFT (5U) -#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) -#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) - -/* - * PLLPRESCALE (RW) - * - * Divide MCLK by 2 before input to PLL - * 0 = Divide by 1 - * 1 = Divide by 2 - */ -#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) -#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) -#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) -#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) - -/* - * PLLN (RW) - * - * Integer (N) part of PLL input/output frequency - * ratio. Use values greater than 5 and less than 13 - */ -#define WM8960_PLL1_PLLN_MASK (0xFU) -#define WM8960_PLL1_PLLN_SHIFT (0U) -#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) -#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) - -/* Bitfield definition for register: PLL2 */ -/* - * PLLK (RW) - * - * Fractional (K) part of PLL1 input/output - * frequency ratio (treat as one 24-digit binary number). - */ -#define WM8960_PLL2_PLLK_MASK (0xFFU) -#define WM8960_PLL2_PLLK_SHIFT (0U) -#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) -#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) - -/* Bitfield definition for register: PLL3 */ -/* - * PLLK (RW) - * - * Fractional (K) part of PLL1 input/output - * frequency ratio (treat as one 24-digit binary number). - */ -#define WM8960_PLL3_PLLK_MASK (0xFFU) -#define WM8960_PLL3_PLLK_SHIFT (0U) -#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) -#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) - -/* Bitfield definition for register: PLL4 */ -/* - * PLLK (RW) - * - * Fractional (K) part of PLL1 input/output - * frequency ratio (treat as one 24-digit binary number). - */ -#define WM8960_PLL4_PLLK_MASK (0xFFU) -#define WM8960_PLL4_PLLK_SHIFT (0U) -#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) -#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) - - -#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld deleted file mode 100644 index 6fba880361..0000000000 --- a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 64K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0xB0000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K - AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(FLASH) + 0x400; -__boot_header_load_addr__ = ORIGIN(FLASH) + 0x1000; -__app_load_addr__ = ORIGIN(FLASH) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > FLASH - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > FLASH - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > FLASH - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > FLASH - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > FLASH - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > FLASH - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > FLASH - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > ILM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > ILM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > ILM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > ILM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > ILM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > ILM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_start__ = .; - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - __noncacheable_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - -} diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld index 25384416a2..fc0e874889 100644 --- a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -26,6 +26,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -173,7 +182,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -183,6 +192,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -276,7 +294,8 @@ SECTIONS } > AXI_SRAM __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + /* Calculate firmware size based on actual addresses to avoid SIZEOF() issues with LLVM lld */ + __fw_size__ = (__noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init)) - __app_load_addr__; .heap(NOLOAD) : { . = ALIGN(8); @@ -301,7 +320,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_start__ = .; diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index f71e19fab9..0000000000 --- a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 256K - AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_start__ = .; - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - __noncacheable_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - -} diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld index d3f989e15c..b499ac1e37 100644 --- a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -111,6 +111,16 @@ SECTIONS . = ALIGN(8); } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; diff --git a/bsp/hpmicro/hpm5e00evk/board/pinmux.c b/bsp/hpmicro/hpm5e00evk/board/pinmux.c index a110e7b956..101200fe72 100644 --- a/bsp/hpmicro/hpm5e00evk/board/pinmux.c +++ b/bsp/hpmicro/hpm5e00evk/board/pinmux.c @@ -39,7 +39,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { #if 1 @@ -60,8 +60,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PD03].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PD02].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - ; + return status_invalid_argument; } + return status_success; } void init_ppi_pins(void) diff --git a/bsp/hpmicro/hpm5e00evk/board/pinmux.h b/bsp/hpmicro/hpm5e00evk/board/pinmux.h index 427479bab2..bb3d96fd28 100644 --- a/bsp/hpmicro/hpm5e00evk/board/pinmux.h +++ b/bsp/hpmicro/hpm5e00evk/board/pinmux.h @@ -13,7 +13,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_ppi_pins(void); void init_sdm_pins(void); void init_pwm_pin_as_sdm_clock(void); diff --git a/bsp/hpmicro/hpm5e00evk/board/rtt_board.c b/bsp/hpmicro/hpm5e00evk/board/rtt_board.c index d93e3a314c..66571a1a96 100644 --- a/bsp/hpmicro/hpm5e00evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm5e00evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); @@ -121,7 +127,7 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } #endif -uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ { uint32_t freq = 0; diff --git a/bsp/hpmicro/hpm5e00evk/makefile.targets b/bsp/hpmicro/hpm5e00evk/makefile.targets index e71da5a6e1..8469d7d2aa 100644 --- a/bsp/hpmicro/hpm5e00evk/makefile.targets +++ b/bsp/hpmicro/hpm5e00evk/makefile.targets @@ -3,4 +3,4 @@ clean2: -$(RM) $(OBJS) *.elf -@echo ' ' -*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds)
\ No newline at end of file +*.elf: $(wildcard board/linker_scripts/gcc/*.ld)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig.h b/bsp/hpmicro/hpm5e00evk/rtconfig.h index 19c927d335..deadf6c3a1 100644 --- a/bsp/hpmicro/hpm5e00evk/rtconfig.h +++ b/bsp/hpmicro/hpm5e00evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -291,6 +301,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -318,12 +332,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -403,7 +429,7 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM5E00_SERIES +#define SOC_SERIES_HPM5E00 /* Hardware Drivers Config */ @@ -419,6 +445,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig.py b/bsp/hpmicro/hpm5e00evk/rtconfig.py index 14789f56ff..962fe9789b 100644 --- a/bsp/hpmicro/hpm5e00evk/rtconfig.py +++ b/bsp/hpmicro/hpm5e00evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h index b7ae18b326..704fe412de 100644 --- a/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h +++ b/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h @@ -6,8 +6,7 @@ /* RT-Thread pre-include file */ #define D45 -#define HPM6880 -#define HPM6E80 +#define HPM5E31 #define HPMSOC_HAS_HPMSDK_DMAV2 #define RT_USING_LIBC #define RT_USING_NEWLIBC diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c index e3f85a9e0e..78705526d8 100644 --- a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c @@ -54,6 +54,8 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ __attribute__((weak)) void c_startup(void) for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S index c200076924..0262684ad3 100644 --- a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S @@ -77,6 +77,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -89,3 +90,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm5e00evk/startup/SConscript b/bsp/hpmicro/hpm5e00evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm5e00evk/startup/SConscript +++ b/bsp/hpmicro/hpm5e00evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/.config b/bsp/hpmicro/hpm6200evk/.config index 201f27f95c..1b12c8e7aa 100644 --- a/bsp/hpmicro/hpm6200evk/.config +++ b/bsp/hpmicro/hpm6200evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,12 +922,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,25 +1489,33 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6200_SERIES=y +CONFIG_SOC_SERIES_HPM6000=y # # Hardware Drivers Config # -CONFIG_SOC_HPM6200=y +CONFIG_SOC_HPM6000=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_UART0_RX_USING_DMA is not set # CONFIG_BSP_UART0_TX_USING_DMA is not set CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_GPTMR is not set @@ -1455,5 +1526,57 @@ CONFIG_BSP_UART0_TX_BUFSIZE=0 # CONFIG_BSP_USING_WDG is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_SDM is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_PLA is not set +# CONFIG_BSP_USING_LIN is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_TAMP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6200evk/README.md b/bsp/hpmicro/hpm6200evk/README.md index fe1b40a1a5..b1e86a105e 100644 --- a/bsp/hpmicro/hpm6200evk/README.md +++ b/bsp/hpmicro/hpm6200evk/README.md @@ -72,7 +72,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6280-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -80,7 +80,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6280-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6200evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6200evk/README_zh.md b/bsp/hpmicro/hpm6200evk/README_zh.md index d1fc210afd..d64e808dc0 100644 --- a/bsp/hpmicro/hpm6200evk/README_zh.md +++ b/bsp/hpmicro/hpm6200evk/README_zh.md @@ -74,14 +74,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6280-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6280-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6200evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6200evk/SConscript b/bsp/hpmicro/hpm6200evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6200evk/SConscript +++ b/bsp/hpmicro/hpm6200evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6200evk/SConstruct b/bsp/hpmicro/hpm6200evk/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6200evk/SConstruct +++ b/bsp/hpmicro/hpm6200evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6200evk/applications/SConscript b/bsp/hpmicro/hpm6200evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6200evk/applications/SConscript +++ b/bsp/hpmicro/hpm6200evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6200evk/applications/main.c b/bsp/hpmicro/hpm6200evk/applications/main.c index 0bbf637038..98ea3be7a3 100644 --- a/bsp/hpmicro/hpm6200evk/applications/main.c +++ b/bsp/hpmicro/hpm6200evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6200evk/board/Kconfig b/bsp/hpmicro/hpm6200evk/board/Kconfig index 0b5373e534..b6b80277da 100644 --- a/bsp/hpmicro/hpm6200evk/board/Kconfig +++ b/bsp/hpmicro/hpm6200evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6200 +config SOC_HPM6000 bool - select SOC_HPM6200_SERIES + select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers" bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -41,6 +47,47 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART0_DMA_PINGPONG_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -64,6 +111,111 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -87,84 +239,308 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif - - menuconfig BSP_USING_SPI bool "Enable SPI" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" default y if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C bool "Enable I2C" default n + select RT_USING_I2C if BSP_USING_I2C if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" default y - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n - endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -173,6 +549,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -180,14 +557,25 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB HOST" select RT_USING_CACHE default n + if PKG_CHERRYUSB_HOST_ASIX || PKG_CHERRYUSB_HOST_RTL8152 + config LWIP_TCPIP_CORE_LOCKING_INPUT + int + default 1 + config LWIP_TCPIP_CORE_LOCKING + int + default 1 + config RT_LWIP_PBUF_POOL_BUFSIZE + int + default 1600 + endif endif - menuconfig BSP_USING_WDG bool "Enable Watchdog" default n @@ -209,21 +597,45 @@ menu "On-chip Peripheral Drivers" config BSP_USING_MCAN0 bool "Enable MCAN0" default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN1 bool "Enable MCAN1" default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN2 bool "Enable MCAN2" default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN3 bool "Enable MCAN3" default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -240,6 +652,325 @@ menu "On-chip Peripheral Drivers" default n endif endif + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + + menuconfig BSP_USING_SDM + bool "Enable SDM (Sigma-Delta Modulator)" + default n + + menuconfig BSP_USING_QEI + bool "Enable QEI (Quadrature Encoder Interface)" + default n + + menuconfig BSP_USING_PLA + bool "Enable PLA" + default n + + menuconfig BSP_USING_LIN + bool "Enable LIN" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + endmenu endmenu diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg index a9bc40baae..f1f7664f66 100644 --- a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg @@ -1,26 +1,59 @@ # Copyright 2023 hpmicro # SPDX-License-Identifier: BSD-3-Clause +# +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x1000000 flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + # enable all clocks + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg index 1db506d3cf..a9924231dc 100644 --- a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg @@ -14,6 +14,9 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + proc dmi_write {reg value} { $::_TARGET0 riscv dmi_write ${reg} ${value} } diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg index 24cbdeddd0..b284a6d281 100644 --- a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2023,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6280 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6280 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld index 8539708e36..f3e3505e75 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld @@ -29,6 +29,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -173,7 +182,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -183,6 +192,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -274,7 +292,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -297,7 +315,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld index 83c625a644..cc356a0069 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld @@ -104,6 +104,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.c b/bsp/hpmicro/hpm6200evk/board/pinmux.c index 9b022a40ce..11e915113a 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.c @@ -48,7 +48,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins_as_gpio(I2C_Type *ptr) +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr) { if (ptr == HPM_I2C0) { /* I2C0 */ @@ -59,12 +59,12 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_GPIO_B_21; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_I2C0_SCL @@ -81,9 +81,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } void init_sdm_pins(void) diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.h b/bsp/hpmicro/hpm6200evk/board/pinmux.h index c91350dd66..579922dda1 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.h @@ -13,7 +13,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -31,7 +31,7 @@ void init_usb_pins(USB_Type *ptr); void init_can_pins(MCAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); -void init_i2c_pins_as_gpio(I2C_Type *ptr); +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_led_pins_as_pwm(void); void init_trgmux_pins(uint32_t pin); diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.c b/bsp/hpmicro/hpm6200evk/board/rtt_board.c index 86b5a92a25..6abf614988 100644 --- a/bsp/hpmicro/hpm6200evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm6200evk/makefile.targets b/bsp/hpmicro/hpm6200evk/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.h b/bsp/hpmicro/hpm6200evk/rtconfig.h index 627acbf5de..025c77de7b 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.h +++ b/bsp/hpmicro/hpm6200evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -103,7 +113,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -290,6 +300,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -317,12 +331,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -402,20 +428,45 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6200_SERIES +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ -#define SOC_HPM6200 +#define SOC_HPM6000 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_UART0_RX_BUFSIZE 128 #define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.py b/bsp/hpmicro/hpm6200evk/rtconfig.py index 28d0b94cb9..fc0b56fb23 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.py +++ b/bsp/hpmicro/hpm6200evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6200evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6200evk/rtconfig_preinc.h new file mode 100644 index 0000000000..d6ccee3303 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/rtconfig_preinc.h @@ -0,0 +1,19 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HPM6280 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 94 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c b/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c index 1928adaf58..a3e04d3e18 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S index 93ff037c99..59675cb3fd 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S @@ -37,11 +37,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ @@ -54,6 +63,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -66,3 +76,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* #ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6200evk/startup/SConscript b/bsp/hpmicro/hpm6200evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm6200evk/startup/SConscript +++ b/bsp/hpmicro/hpm6200evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/.config b/bsp/hpmicro/hpm6300evk/.config index 0db62e87a3..278e781231 100644 --- a/bsp/hpmicro/hpm6300evk/.config +++ b/bsp/hpmicro/hpm6300evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -264,10 +274,10 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -460,6 +470,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -575,6 +586,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -634,6 +646,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -782,6 +796,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -815,7 +831,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -894,12 +924,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -907,6 +944,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -986,6 +1040,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1040,6 +1095,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1090,6 +1146,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1107,6 +1164,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1164,6 +1224,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1189,6 +1251,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1428,12 +1491,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6300_SERIES=y +CONFIG_SOC_SERIES_HPM6000=y # # Hardware Drivers Config # -CONFIG_SOC_HPM6300=y +CONFIG_SOC_HPM6000=y # # On-chip Peripheral Drivers @@ -1452,6 +1515,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set @@ -1466,5 +1530,59 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_WDG is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_FFA is not set +# CONFIG_BSP_USING_TAMP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config + +# +# AMPAK Wi-Fi module Configuration +# +# end of AMPAK Wi-Fi module Configuration +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6300evk/README.md b/bsp/hpmicro/hpm6300evk/README.md index 75dea3f4af..62fc9e9c80 100644 --- a/bsp/hpmicro/hpm6300evk/README.md +++ b/bsp/hpmicro/hpm6300evk/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6360.cfg -f board\debug_scripts\openocd\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6360.cfg -f board\debug_scripts\openocd\boards\hpm6300evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6300evk/README_zh.md b/bsp/hpmicro/hpm6300evk/README_zh.md index 884e84a948..5165a53b25 100644 --- a/bsp/hpmicro/hpm6300evk/README_zh.md +++ b/bsp/hpmicro/hpm6300evk/README_zh.md @@ -74,14 +74,14 @@ - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6360.cfg -f board\debug_scripts\openocd\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6360.cfg -f board\debug_scripts\openocd\boards\hpm6300evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6300evk/SConscript b/bsp/hpmicro/hpm6300evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6300evk/SConscript +++ b/bsp/hpmicro/hpm6300evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6300evk/SConstruct b/bsp/hpmicro/hpm6300evk/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6300evk/SConstruct +++ b/bsp/hpmicro/hpm6300evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6300evk/applications/SConscript b/bsp/hpmicro/hpm6300evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6300evk/applications/SConscript +++ b/bsp/hpmicro/hpm6300evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6300evk/applications/main.c b/bsp/hpmicro/hpm6300evk/applications/main.c index 0bbf637038..98ea3be7a3 100644 --- a/bsp/hpmicro/hpm6300evk/applications/main.c +++ b/bsp/hpmicro/hpm6300evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) { static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6300evk/board/Kconfig b/bsp/hpmicro/hpm6300evk/board/Kconfig index fa34502a82..efcacc3f89 100644 --- a/bsp/hpmicro/hpm6300evk/board/Kconfig +++ b/bsp/hpmicro/hpm6300evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6300 +config SOC_HPM6000 bool - select SOC_HPM6300_SERIES + select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -251,6 +251,25 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_SPI @@ -269,7 +288,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -277,7 +296,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -299,7 +318,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -307,7 +326,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -329,7 +348,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -337,7 +356,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -350,7 +369,7 @@ menu "On-chip Peripheral Drivers" endif config BSP_USING_SPI3 bool "Enable SPI3" - default n + default y if BSP_USING_SPI3 config BSP_SPI3_USING_DMA bool "Enable SPI3 DMA" @@ -359,7 +378,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -367,7 +386,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -393,7 +412,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PHY if BSP_USING_ETH if BSP_USING_ETH - choice BSP_ETH0_SEL + choice prompt "ETH" config BSP_USING_ETH0 bool "Enable ETH0" @@ -414,7 +433,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC0_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC0_USE_CACHEABLE_BUFFER config BSP_SDXC0_USE_CACHEABLE_BUFFER @@ -442,7 +461,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC0_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_4BIT config BSP_SDXC0_BUS_WIDTH_1BIT @@ -450,7 +469,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_BUS_WIDTH_4BIT bool "4-bit" endchoice - choice VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC0_VOLTAGE_3V3 config BSP_SDXC0_VOLTAGE_3V3 @@ -472,6 +491,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -506,11 +526,21 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C bool "Enable I2C" default n + select RT_USING_I2C if BSP_USING_I2C if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" @@ -570,7 +600,6 @@ menu "On-chip Peripheral Drivers" bool "INIT_EXT_RAM_FOR_DATA" default y - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -579,7 +608,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWM + select RT_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -595,7 +624,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_WDG bool "Enable Watchdog" default n @@ -637,7 +665,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -654,6 +682,326 @@ menu "On-chip Peripheral Drivers" default n endif endif + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + + menuconfig BSP_USING_QEI + bool "Enable QEI (Quadrature Encoder Interface)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_FFA + bool "Enable FFA" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +menu "AMPAK Wi-Fi module Configuration" +config BSP_USING_MHD_WIFI +bool +default y if RT_USING_MHD +select BSP_USING_SDXC +select BSP_USING_SDXC0 +select BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN +help + Automatically enable SDXC1 interface when WiFi MHD driver is enabled. + Note: Please manually select non-cacheable buffer and fast RAM options for SDXC1 if needed. + endmenu endmenu diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg index bca3b8dc16..7fb3a7a74c 100644 --- a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg @@ -1,245 +1,194 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause +# +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x1000000 flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } proc init_sdram { } { -# configure dram frequency -# 133Mhz pll1_clk0: 266Mhz divide by 2 - #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 -# 166Mhz pll2_clk0: 333Mhz divide by 2 - $::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x401 +# configure femc frequency +# 166Mhz pll0_clk1: 333Mhz divide by 2 + mww 0xF4001808 0x201 - # PD13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040368 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040360 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040350 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040348 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040340 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040338 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040330 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040328 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040320 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040318 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040310 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040308 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040300 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC29 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC28 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC27 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + # PA25 + mww 0xF40400C8 0xC + # PA26 + mww 0xF40400D0 0xC + # PA27 + mww 0xF40400D8 0xC + # PA28 + mww 0xF40400E0 0xC + # PA29 + mww 0xF40400E8 0xC + # PA30 + mww 0xF40400F0 0xC + # PA31 + mww 0xF40400F8 0xC + # PB00 + mww 0xF4040100 0xC + # PB01 + mww 0xF4040108 0xC + # PB02 + mww 0xF4040110 0xC + # PB03 + mww 0xF4040118 0xC + # PB04 + mww 0xF4040120 0xC + # PB05 + mww 0xF4040128 0xC + # PB06 + mww 0xF4040130 0xC + # PB07 + mww 0xF4040138 0xC + # PB08 + mww 0xF4040140 0xC - # PC22 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC21 - $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC17 - $::_TARGET0 riscv dmi_write 0x39 0xF4040288 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC15 - $::_TARGET0 riscv dmi_write 0x39 0xF4040278 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040260 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC11 - $::_TARGET0 riscv dmi_write 0x39 0xF4040258 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040250 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040248 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040240 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040238 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040230 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040228 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040220 - $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB09 + mww 0xF4040148 0xC + # PB10 + mww 0xF4040150 0xC + # PB11 + mww 0xF4040158 0xC + # PB12 + mww 0xF4040160 0xC + # PB13 + mww 0xF4040168 0xC + # PB14 + mww 0xF4040170 0xC + # PB15 + mww 0xF4040178 0xC + # PB16 + mww 0xF4040180 0xC + # PB17 + mww 0xF4040188 0xC + # PB18 + mww 0xF4040190 0xC + # PB19 + mww 0xF4040198 0xC + # PB20 + mww 0xF40401A0 0xC - # PC14 - $::_TARGET0 riscv dmi_write 0x39 0xF4040270 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040268 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC16 - # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C - # PC26 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC25 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040298 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040290 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC23 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC24 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC30 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC31 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040210 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040218 - $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB21 + mww 0xF40401A8 0xC + # PB22 + mww 0xF40401B0 0xC + # PB23 + mww 0xF40401B8 0xC + # PB24 + mww 0xF40401C0 0xC + # PB25 + mww 0xF40401C8 0xC + # PB26 + mww 0xF40401D0 0xC + # PB27 + mww 0xF40401D8 0xC + # PB28 + mww 0xF40401E0 0xC + # PB29 + mww 0xF40401E8 0xC + # PB30 + mww 0xF40401F0 0xC + # PB31 + mww 0xF40401F8 0xC - # dramc configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 + # femc configuration + mww 0xF3050000 0x1 sleep 10 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - $::_TARGET0 riscv dmi_write 0x39 0xF3050008 - $::_TARGET0 riscv dmi_write 0x3C 0x30524 - $::_TARGET0 riscv dmi_write 0x39 0xF305000C - $::_TARGET0 riscv dmi_write 0x3C 0x6030524 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + mww 0xF3050000 0x2 + mww 0xF3050008 0x30524 + mww 0xF305000C 0x6030524 + mww 0xF3050000 0x10000004 # 32MB - $::_TARGET0 riscv dmi_write 0x39 0xF3050010 - $::_TARGET0 riscv dmi_write 0x3C 0x4000001b - $::_TARGET0 riscv dmi_write 0x39 0xF3050014 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF3050010 0x4000001b + mww 0xF3050014 0 # 16-bit - $::_TARGET0 riscv dmi_write 0x39 0xF3050040 - $::_TARGET0 riscv dmi_write 0x3C 0xf31 + mww 0xF3050040 0xf31 - # 133Mhz configuration - #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 # 166Mhz configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + mww 0xF3050044 0x884e33 - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + mww 0xF3050048 0x1020d0d + mww 0xF3050048 0x1020d0d + mww 0xF305004C 0x2020300 # config delay cell - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x3b - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x203b + mww 0xF3050150 0x2000 - $::_TARGET0 riscv dmi_write 0x39 0xF3050094 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050098 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF3050094 0 + mww 0xF3050098 0 # precharge all - $::_TARGET0 riscv dmi_write 0x39 0xF3050090 - $::_TARGET0 riscv dmi_write 0x3C 0x40000000 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + mww 0xF3050090 0x40000000 + mww 0xF305009C 0xA55A000F sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # auto refresh - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305003C 0x3 + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # set mode - $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 - $::_TARGET0 riscv dmi_write 0x3C 0x33 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + mww 0xF30500A0 0x33 + mww 0xF305009C 0xA55A000A sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + mww 0xF305004C 0x2020301 echo "SDRAM has been initialized" } diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg index bfce20c208..eaf2924962 100644 --- a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg @@ -1,7 +1,11 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6360 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6360 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c deleted file mode 100644 index 663518be09..0000000000 --- a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2021 - 2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Change Logs: - * Date Author Notes - * 2022-01-11 hpmicro First version - */ - -#include "rtthread.h" - -#ifdef RT_USING_PHY -#include <rtdevice.h> -#include <rtdbg.h> -#include "hpm_enet_drv.h" -#include "eth_phy_port.h" -#include "hpm_soc.h" -#include "netif/ethernetif.h" -#include "board.h" - -typedef struct -{ - char *mdio_name; - ENET_Type *instance; - struct eth_device *eth_dev; - phy_device_t *phy_dev; - struct rt_mdio_bus *mdio_bus; -} eth_phy_handle_t; - -typedef struct -{ - uint8_t phy_handle_cnt; - eth_phy_handle_t **phy_handle; -} eth_phy_monitor_handle_t; - -#ifdef BSP_USING_ETH0 -extern struct eth_device eth0_dev; -static struct rt_mdio_bus mdio0_bus; -static phy_device_t phy0_dev; -static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; - -static eth_phy_handle_t eth0_phy_handle = -{ - .instance = HPM_ENET0, - .eth_dev = ð0_dev, - .phy_dev = &phy0_dev, - .mdio_name = "MDIO0", - .mdio_bus = &mdio0_bus, -}; -#endif - -#ifdef BSP_USING_ETH1 -extern struct eth_device eth1_dev; -static struct rt_mdio_bus mdio1_bus; -static phy_device_t phy1_dev; -static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; - -static eth_phy_handle_t eth1_phy_handle = -{ - .instance = HPM_ENET1, - .eth_dev = ð1_dev, - .phy_dev = &phy1_dev, - .mdio_name = "MDIO1", - .mdio_bus = &mdio1_bus, -}; -#endif - -static eth_phy_handle_t *s_gphys[] = -{ -#ifdef BSP_USING_ETH0 -ð0_phy_handle, -#endif - -#ifdef BSP_USING_ETH1 -ð1_phy_handle -#endif -}; - -static uint8_t *s_gphy_reg_list[] = -{ -#ifdef BSP_USING_ETH0 -phy0_reg_list, -#endif - -#ifdef BSP_USING_ETH1 -phy1_reg_list, -#endif -}; - -eth_phy_monitor_handle_t phy_monitor_handle = -{ - .phy_handle_cnt = ARRAY_SIZE(s_gphys), - .phy_handle = s_gphys -}; - -static struct rt_phy_ops phy_ops; - -static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) -{ - return PHY_STATUS_OK; -} - -static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); - - return size; -} - -static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) -{ - enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); - - return size; -} - -static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); - - #if PHY_AUTO_NEGO - reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - - #else - reg_status &= PHY_LINKED_STATUS_MASK; - *status = reg_status ? RT_TRUE : RT_FALSE; - #endif - - return PHY_STATUS_OK; -} - -static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) -{ - uint16_t reg_status; - - reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); - - *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M; - *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; - - return PHY_STATUS_OK; -} - -static void phy_poll_status(void *parameter) -{ - int ret; - phy_info_t phy_info; - rt_bool_t status; - rt_device_t dev; - rt_phy_msg_t msg; - rt_uint32_t speed, duplex; - phy_device_t *phy_dev; - struct eth_device* eth_dev; - char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; - enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; - phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; - - phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); - - if (status) - { - phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); - - ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - if (ret != 0) - { - memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - } - } - - if (phy_dev->phy_link != status) - { - phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; - eth_device_linkchange(eth_dev, status); - LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); - if (status == PHY_LINK_UP) - { - LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); - LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); - enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); - enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); - } - } - } -} - -static void phy_detection(void *parameter) -{ - uint8_t detected_count = 0; - struct rt_phy_msg msg = {0, 0}; - phy_device_t *phy_dev = (phy_device_t *)parameter; - rt_uint32_t i; - - msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; - phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); - - while(phy_dev->phy.addr == 0xffff) - { - /* Search a PHY */ - for (i = 0; i <= 0x1f; i++) - { - ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; - phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); - - if (msg.value == PHY_ID1) - { - phy_dev->phy.addr = i; - LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); - return; - } - } - - phy_dev->phy.addr = 0xffff; - detected_count++; - rt_thread_mdelay(1000); - - if (detected_count > 3) - { - LOG_E("No any PHY device is detected! Please check your hardware!\n"); - return; - } - } -} - -static void phy_monitor_thread_entry(void *args) -{ - rt_timer_t phy_status_timer; - - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; - - for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) - { - LOG_D("Detect a PHY%d\n", i); - phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); - } - - phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); - - if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) - { - LOG_E("Failed to start link change detection timer\n"); - } -} - -int phy_device_register(void) -{ - rt_err_t err = RT_ERROR; - rt_thread_t thread_phy_monitor; - - /* Set ops for PHY */ - phy_ops.init = phy_init; - phy_ops.get_link_status = phy_get_link_status; - phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; - - for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) - { - /* Set PHY address */ - s_gphys[i]->phy_dev->phy.addr = 0xffff; - - /* Set MIDO bus */ - s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; - s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; - s_gphys[i]->mdio_bus->ops->read = phy_read; - s_gphys[i]->mdio_bus->ops->write = phy_write; - s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; - s_gphys[i]->phy_dev->phy.ops = &phy_ops; - - /* Set PHY register list */ - s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; - - rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); - } - - /* Start PHY monitor */ - thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); - - if (thread_phy_monitor != RT_NULL) - { - rt_thread_startup(thread_phy_monitor); - } - else - { - err = RT_ERROR; - } - - return err; -} -INIT_PREV_EXPORT(phy_device_register); -#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h deleted file mode 100644 index 70c24775e4..0000000000 --- a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2021 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef ETH_PHY_PORT_H -#define ETH_PHY_PORT_H - -#include "hpm_ioc_regs.h" -#include <rtdevice.h> - -#ifndef PHY_AUTO_NEGO -#define PHY_AUTO_NEGO (1U) -#endif - -#ifndef PHY_MDIO_CSR_CLK_FREQ -#define PHY_MDIO_CSR_CLK_FREQ (200000000U) -#endif - -enum phy_link_status -{ - PHY_LINK_DOWN = 0U, - PHY_LINK_UP -}; - -typedef struct { - rt_uint32_t phy_speed; - rt_uint32_t phy_duplex; -} phy_info_t; - -typedef struct { - rt_uint32_t phy_link; - rt_phy_t phy; - phy_info_t phy_info; -} phy_device_t; - -/** @note PHY: RTL8201 */ - -#define PHY_NAME ("RTL8201") -#define PHY_ID1 (0x1CU) - -/* The PHY basic control register */ -#define PHY_BASIC_CONTROL_REG (0x00U) -#define PHY_RESET_MASK (1U << 15) -#define PHY_AUTO_NEGOTIATION_MASK (1U << 12) - -/* The PHY basic status register */ -#define PHY_BASIC_STATUS_REG (0x01U) -#define PHY_LINKED_STATUS_MASK (1U << 2) -#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) - -/* The PHY ID one register */ -#define PHY_ID1_REG (0x02U) - -/* The PHY ID two register */ -#define PHY_ID2_REG (0x03U) - -/* The PHY auto-negotiate advertise register */ -#define PHY_AUTONEG_ADVERTISE_REG (0x04U) - -/* The PHY status register. */ -#define PHY_STATUS_REG (0x00U) -#define PHY_10M_MASK (1 << 13) -#define PHY_100M_MASK (1 << 13) -#define PHY_FULL_DUPLEX_MASK (1 << 8) -#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_100M_MASK) ? 0: 1 -#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) -#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) - -/* PHY0 register list */ -#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ - PHY_BASIC_STATUS_REG,\ - PHY_ID1_REG,\ - PHY_ID2_REG,\ - PHY_AUTONEG_ADVERTISE_REG,\ - PHY_STATUS_REG - -/* PHY0 register index */ -#define PHY_BASIC_STATUS_REG_IDX (1U) -#define PHY_ID1_REG_IDX (2U) -#define PHY_STATUS_REG_IDX (5U) - -#endif diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld deleted file mode 100644 index d083b1957f..0000000000 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - /* WHD related */ - KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) - KEEP(*whd_buffer_api.o (.text .text* .rodata .rodata*)) - KEEP(*whd_cdc_bdc.o (.text .text* .rodata .rodata*)) - KEEP(*whd_events.o (.text .text* .rodata .rodata*)) - KEEP(*whd_msgbuf_txrx.o (.text .text* .rodata .rodata*)) - KEEP(*whd_network_if.o (.text .text* .rodata .rodata*)) - KEEP(*whd_sdpcm.o (.text .text* .rodata .rodata*)) - KEEP(*whd_thread.o (.text .text* .rodata .rodata*)) - KEEP(*cyhal*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld index f17f102088..f8761a1dea 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld @@ -30,6 +30,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -177,7 +186,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -187,6 +196,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -278,7 +296,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -305,7 +323,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; @@ -336,7 +354,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index 2bcf46ee20..0000000000 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - . += SDRAM_SIZE; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld deleted file mode 100644 index 8e0be81fec..0000000000 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld index 39525b220b..d4a80b999e 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld @@ -115,6 +115,16 @@ SECTIONS . = ALIGN(8); } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -217,7 +227,7 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.c b/bsp/hpmicro/hpm6300evk/board/pinmux.c index 864ac47897..7db0f81ab4 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.c @@ -46,19 +46,19 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins_as_gpio(I2C_Type *ptr) +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr) { if (ptr == HPM_I2C0) { /* I2C0 */ HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPIO_C_13; HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_GPIO_C_14; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_I2C0_SCL @@ -75,9 +75,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } void init_femc_pins(void) diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.h b/bsp/hpmicro/hpm6300evk/board/pinmux.h index 2d6f6c8259..c8963a17d7 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.h @@ -13,7 +13,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_femc_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); @@ -35,7 +35,7 @@ void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); -void init_i2c_pins_as_gpio(I2C_Type *ptr); +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.c b/bsp/hpmicro/hpm6300evk/board/rtt_board.c index 6335b08037..3201681140 100644 --- a/bsp/hpmicro/hpm6300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm6300evk/makefile.targets b/bsp/hpmicro/hpm6300evk/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.h b/bsp/hpmicro/hpm6300evk/rtconfig.h index 6b3e075574..2d179724dd 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.h +++ b/bsp/hpmicro/hpm6300evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -291,6 +301,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -318,12 +332,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -403,11 +429,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6300_SERIES +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ -#define SOC_HPM6300 +#define SOC_HPM6000 /* On-chip Peripheral Drivers */ @@ -419,6 +445,33 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ + +/* AMPAK Wi-Fi module Configuration */ + +/* end of AMPAK Wi-Fi module Configuration */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.py b/bsp/hpmicro/hpm6300evk/rtconfig.py index dcf456c802..3b276240c1 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.py +++ b/bsp/hpmicro/hpm6300evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6300evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6300evk/rtconfig_preinc.h new file mode 100644 index 0000000000..40641e6c86 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/rtconfig_preinc.h @@ -0,0 +1,19 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HPM6360 +#define HPM_SDK_L1C_NO_REENTRANT 1 +#define HPM_SOC_ISR_NUM 79 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define USE_DMA_DECLARE_EXT_ISR_M 1 +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c index 1928adaf58..a3e04d3e18 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S index 350628abeb..912f0df957 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S @@ -52,11 +52,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ @@ -69,6 +78,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -81,3 +91,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6300evk/startup/SConscript b/bsp/hpmicro/hpm6300evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm6300evk/startup/SConscript +++ b/bsp/hpmicro/hpm6300evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/.config b/bsp/hpmicro/hpm6750evk/.config index 518620520f..855565dd2b 100644 --- a/bsp/hpmicro/hpm6750evk/.config +++ b/bsp/hpmicro/hpm6750evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,11 +188,14 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -234,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -261,10 +274,10 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -457,6 +470,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -572,6 +586,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -631,6 +646,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -779,6 +796,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -809,9 +828,24 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -890,12 +924,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -903,6 +944,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -982,6 +1040,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1036,6 +1095,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1086,6 +1146,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1103,6 +1164,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1160,6 +1224,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1185,6 +1251,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1424,6 +1491,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_SERIES_HPM6000=y + # # Hardware Drivers Config # @@ -1433,6 +1502,7 @@ CONFIG_SOC_HPM6000=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y CONFIG_BSP_UART0_RX_BUFSIZE=128 @@ -1467,4 +1537,28 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_PANEL is not set # CONFIG_BSP_USING_RTT_LCD_DRIVER is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini b/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini index 1ae5ab7322..b977a95fea 100644 --- a/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini +++ b/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini @@ -10,7 +10,7 @@ chip_name=HPM6750 selected_rtt_version=4.0.5 bsp_version=0.3.0 os_branch=full -output_project_path=C\:/DevTools/RT-ThreadStudio/workspace +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6750evk is_base_example_project=True is_use_scons_build=True project_base_bsp=true diff --git a/bsp/hpmicro/hpm6750evk/README.md b/bsp/hpmicro/hpm6750evk/README.md index e0b34306cf..0ab280a029 100644 --- a/bsp/hpmicro/hpm6750evk/README.md +++ b/bsp/hpmicro/hpm6750evk/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6750evk/README_zh.md b/bsp/hpmicro/hpm6750evk/README_zh.md index 9d8effddaf..82f75ade0c 100644 --- a/bsp/hpmicro/hpm6750evk/README_zh.md +++ b/bsp/hpmicro/hpm6750evk/README_zh.md @@ -74,14 +74,14 @@ HPM6750EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，� - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6750evk/SConscript b/bsp/hpmicro/hpm6750evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6750evk/SConscript +++ b/bsp/hpmicro/hpm6750evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6750evk/SConstruct b/bsp/hpmicro/hpm6750evk/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6750evk/SConstruct +++ b/bsp/hpmicro/hpm6750evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6750evk/applications/SConscript b/bsp/hpmicro/hpm6750evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6750evk/applications/SConscript +++ b/bsp/hpmicro/hpm6750evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6750evk/applications/main.c b/bsp/hpmicro/hpm6750evk/applications/main.c index b766dd547e..a70f2f26dd 100644 --- a/bsp/hpmicro/hpm6750evk/applications/main.c +++ b/bsp/hpmicro/hpm6750evk/applications/main.c @@ -22,7 +22,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6750evk/board/Kconfig b/bsp/hpmicro/hpm6750evk/board/Kconfig index 7d7f861b6a..5f101bc9c0 100644 --- a/bsp/hpmicro/hpm6750evk/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk/board/Kconfig @@ -15,11 +15,23 @@ config BSP_USING_ENET_PHY_DP83848 bool default n +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -122,8 +134,6 @@ menu "On-chip Peripheral Drivers" endif endif - - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -134,36 +144,63 @@ menu "On-chip Peripheral Drivers" default y if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH config BSP_USING_ETH0 bool "Enable ETH0" @@ -180,12 +217,23 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC" default n select RT_USING_SDIO if BSP_USING_SDXC + select RT_USING_PIN if BSP_USING_SDXC if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" default n if BSP_USING_SDXC0 - choice BSP_SDXC0_BUS_WIDTH_SEL + config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + config BSP_SDXC0_REQUIRE_CACHELINE_ALIGNED_BUF + bool "Always require cache-line aligned buffer" + default n + config BSP_SDXC0_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 + choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT config BSP_SDXC0_BUS_WIDTH_1BIT @@ -195,7 +243,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_BUS_WIDTH_8BIT bool "8-bit" endchoice - choice BSP_SDXC0_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC0_VOLTAGE_3V3 config BSP_SDXC0_VOLTAGE_3V3 @@ -217,7 +265,17 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC1" default n if BSP_USING_SDXC1 - choice BSP_SDXC1_BUS_WIDTH_SEL + config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + config BSP_SDXC1_REQUIRE_CACHELINE_ALIGNED_BUF + bool "Always require cache-line aligned buffer" + default n + config BSP_SDXC1_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 + choice prompt "Select BUS_WIDTH" default BSP_SDXC1_BUS_WIDTH_4BIT config BSP_SDXC1_BUS_WIDTH_1BIT @@ -225,7 +283,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_BUS_WIDTH_4BIT bool "4-bit" endchoice - choice BSP_SDXC1_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC1_VOLTAGE_3V3 config BSP_SDXC1_VOLTAGE_3V3 @@ -248,8 +306,8 @@ menu "On-chip Peripheral Drivers" bool "Enable touch" default n if BSP_USING_TOUCH - config BSP_USING_TOUCH_GT911 - bool "Enable GT911" + config BSP_USING_TOUCH_GT9xx + bool "Enable GT9xx" default y config BSP_USING_TOUCH_FT5406 @@ -326,7 +384,6 @@ menu "On-chip Peripheral Drivers" bool "INIT_EXT_RAM_FOR_DATA" default y - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -335,6 +392,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -372,7 +430,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_WDG bool "Enable Watchdog" default n @@ -414,7 +471,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC12 bool "Enable ADC12" @@ -479,7 +536,51 @@ menu "On-chip Peripheral Drivers" select BSP_USING_LCD default n +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +endmenu + +menu "Third-Party Add-ons" +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c index 80914af5aa..24bfbc6e6b 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.c +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -1276,3 +1276,61 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} diff --git a/bsp/hpmicro/hpm6750evk/board/board.h b/bsp/hpmicro/hpm6750evk/board/board.h index da43d3b139..3d50238749 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.h +++ b/bsp/hpmicro/hpm6750evk/board/board.h @@ -633,6 +633,8 @@ uint32_t board_init_cam_clock(CAM_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); void board_init_acmp_clock(ACMP_Type *ptr); diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg index 9f15d4c2ec..c361eb0d57 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg @@ -47,7 +47,7 @@ # - base address: 0x80000000 # - flash size: 0x2000000 # - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 0xe proc init_clock {} { $::_TARGET0 riscv dmi_write 0x39 0xF4002000 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 1e5fd26f1d..59a3f2310d 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,9 +1,12 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause # - -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -14,43 +17,25 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -proc dmi_write {reg value} { - $::_TARGET0 riscv dmi_write ${reg} ${value} -} - -proc dmi_read {reg} { - set v [$::_TARGET0 riscv dmi_read ${reg}] - return ${v} -} -proc dmi_write_memory {addr value} { - dmi_write 0x39 ${addr} - dmi_write 0x3C ${value} -} - -proc dmi_read_memory {addr} { - set sbcs [expr 0x100000 | [dmi_read 0x38]] - dmi_write 0x38 ${sbcs} - dmi_write 0x39 ${addr} - set value [dmi_read 0x3C] - return ${value} -} +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] proc release_core1 {} { - set chip_rev [dmi_read_memory 0x2001FF00] + set chip_rev [sba_read_mem 0x2001FF00] if {$chip_rev != 0x56010100 } { # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + sba_write_mem 0xF4002C08 0x20016284 } else { - dmi_write_memory 0xF4002C08 0x2001660c + sba_write_mem 0xF4002C08 0x2001660c } # set boot flag for core1 - dmi_write_memory 0xF4002C0C 0xC1BEF1A9 + sba_write_mem 0xF4002C0C 0xC1BEF1A9 # release core1 - dmi_write_memory 0xF4002C00 0x1000 + sba_write_mem 0xF4002C00 0x1000 } set _TARGET1 $_CHIP.cpu1 @@ -66,3 +51,6 @@ $_TARGET1 configure -event reset-deassert-pre { release_core1 } +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index f873527fb7..0454c4d0f9 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld deleted file mode 100644 index 2f39e2409d..0000000000 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 768K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - /* hpm_sdk drivers */ - KEEP(*hpm_sdxc_drv*.o (.text .text* .rodata .rodata*)) - - /* WHD related */ - KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) - KEEP(*whd_sdpcm*.o (.text .text* .rodata .rodata*)) - KEEP(*whd_thread*.o (.text .text* .rodata .rodata*)) - - /* LWIP */ - KEEP(*lwip*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld index 8b4f6137da..22c8ee3a20 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -31,6 +31,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -46,26 +55,24 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) - . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); + . = ALIGN(8); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(16); + . = ALIGN(8); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); + __fast_load_addr__ = etext + __data_end__ - __tdata_start__; + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); __ramfunc_start__ = .; *(.fast) - *(.fast.*) - . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -89,12 +96,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(16); + . = ALIGN(8); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); *(.text) *(.text*) *(.rodata) @@ -152,20 +159,6 @@ SECTIONS } > XPI0 - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - .rel : { KEEP(*(.rel*)) } > XPI0 @@ -178,8 +171,8 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; KEEP(*(.fast_ram.init)) @@ -188,6 +181,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -208,26 +210,24 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) - *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { + .tdata : AT(etext) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) - *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { + __data_load_addr__ = etext + __tdata_end__ - __tdata_start__; + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -279,9 +279,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; .heap(NOLOAD) : { . = ALIGN(8); @@ -306,8 +304,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { + __noncacheable_init_load_addr__ = etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__; + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index bcd6c6e125..0000000000 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld deleted file mode 100644 index 8618b40e55..0000000000 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld index e03cd86e66..ee99c9c406 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld @@ -12,10 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K - AXI_SRAM1 (w) : ORIGIN = 0x01100000, LENGTH = 768K + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -88,53 +87,65 @@ SECTIONS /* RT-Thread related sections - end */ - /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - . = ALIGN(8); - } > AXI_SRAM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > AXI_SRAM - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > AXI_SRAM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM .rel : { KEEP(*(.rel*)) } > AXI_SRAM - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - /* NOTE: - Please keep in mind that the load section for rw data is after .text section - Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section - and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: - 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ - 2. the generated binary file will be larger because the space occupied by - NOLOAD sections will be filled - */ - __data_load_addr__ = __etext; - .data : AT(__data_load_addr__) { - __data_start__ = .; + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + __data_load_addr__ = etext + __tdata_end__ - __tdata_start__; + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; __global_pointer$ = . + 0x800; *(.data) *(.data*) @@ -184,27 +195,18 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > AXI_SRAM + } > DLM - __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - PROVIDE(__ramfunc_start__ = .); + __fast_load_addr__ = etext + __data_end__ - __tdata_start__; + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -214,45 +216,23 @@ SECTIONS . = ALIGN(8); } > DLM - /* Note: .tbss and .tdata should be adjacent */ - __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) + .fast_ram.bss (NOLOAD) : { . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - /* Note: Place all NOLOAD sections together */ - .tbss(NOLOAD) : { - . += SIZEOF(.noncacheable.init); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM1 + } > DLM - .bss(NOLOAD) : { + __noncacheable_init_load_addr__ = etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__; + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM1 + } > NONCACHEABLE_RAM .noncacheable.bss (NOLOAD) : { . = ALIGN(8); @@ -284,11 +264,11 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE (__rt_rvstack = .); - } > AXI_SRAM1 + } > DLM .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) - } > AXI_SRAM1 + } > AXI_SRAM .heap (NOLOAD) : { . = ALIGN(8); @@ -296,7 +276,7 @@ SECTIONS . += HEAP_SIZE; __heap_end__ = .; - } > AXI_SRAM1 + } > AXI_SRAM .sdram (NOLOAD) : { . = ALIGN(8); diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld deleted file mode 100644 index fc810f781d..0000000000 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > AXI_SRAM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - *(FalPartTable) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > AXI_SRAM - - .rel : { - KEEP(*(.rel*)) - } > AXI_SRAM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > AXI_SRAM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > AXI_SRAM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - . = ALIGN(8); - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - /* NOTE: - Please keep in mind that the load section for rw data is after .text section - Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section - and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: - 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ - 2. the generated binary file will be larger because the space occupied by - NOLOAD sections will be filled - */ - __data_load_addr__ = __etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - /* Note: Place all NOLOAD sections together */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.c b/bsp/hpmicro/hpm6750evk/board/rtt_board.c index ea3693f141..46ec3e07b5 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.c @@ -39,14 +39,20 @@ void rtt_board_init(void) { rtt_os_tick_clock(); board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); @@ -128,64 +134,12 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) uint32_t rtt_board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) { - uint32_t freq = 0; - - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { - /* Configure the ADC clock from AHB (@200MHz by default)*/ - clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); - } else { - /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - } - clock_add_to_group(clock_adc0, 0); - freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { - /* Configure the ADC clock from AHB (@200MHz by default)*/ - clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); - } else { - /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); - } - clock_add_to_group(clock_adc1, 0); - freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { - /* Configure the ADC clock from AHB (@200MHz by default)*/ - clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); - } else { - /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana2); - clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); - } - clock_add_to_group(clock_adc2, 0); - freq = clock_get_frequency(clock_adc2); - } - - return freq; + return board_init_adc12_clock(ptr, clk_src_ahb); } uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { - uint32_t freq = 0; - - if (ptr == HPM_ADC3) { - if (clk_src_ahb) { - /* Configure the ADC clock from AHB (@200MHz by default)*/ - clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); - } else { - /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana2); - clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); - } - clock_add_to_group(clock_adc3, 0); - freq = clock_get_frequency(clock_adc3); - } - - return freq; + return board_init_adc16_clock(ptr, clk_src_ahb); } uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) @@ -260,4 +214,4 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; rt_tick_increase(); -}
\ No newline at end of file +} diff --git a/bsp/hpmicro/hpm6750evk/makefile.targets b/bsp/hpmicro/hpm6750evk/makefile.targets index 502182f4e7..4583a13f1c 100644 --- a/bsp/hpmicro/hpm6750evk/makefile.targets +++ b/bsp/hpmicro/hpm6750evk/makefile.targets @@ -3,4 +3,4 @@ clean2: -$(RM) $(OBJS) *.elf -@echo ' ' -*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld) +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.h b/bsp/hpmicro/hpm6750evk/rtconfig.h index 146fd6e9ff..51268a678d 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.h +++ b/bsp/hpmicro/hpm6750evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,9 +114,11 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -289,6 +301,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -316,12 +332,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -401,6 +429,7 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ @@ -409,6 +438,7 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_UART0_RX_BUFSIZE 128 @@ -416,6 +446,21 @@ #define BSP_USING_FEMC #define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.py b/bsp/hpmicro/hpm6750evk/rtconfig.py index 14ba9b7129..a859c323d7 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c index 4fc6914d56..54517adc4d 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram * function code to its destination. */ diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S index 5ac683dbc2..6b394172aa 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S @@ -58,11 +58,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ @@ -75,6 +84,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -87,3 +97,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6750evk/startup/SConscript b/bsp/hpmicro/hpm6750evk/startup/SConscript index 3c804fe451..97393e8517 100644 --- a/bsp/hpmicro/hpm6750evk/startup/SConscript +++ b/bsp/hpmicro/hpm6750evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs') diff --git a/bsp/hpmicro/hpm6750evk2/.config b/bsp/hpmicro/hpm6750evk2/.config index 9b7c8b0fb7..fd23979bf7 100644 --- a/bsp/hpmicro/hpm6750evk2/.config +++ b/bsp/hpmicro/hpm6750evk2/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -254,11 +264,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -279,10 +289,10 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -485,6 +495,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -600,6 +611,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -659,6 +671,8 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -807,6 +821,8 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -840,7 +856,21 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -919,12 +949,19 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -932,6 +969,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -1011,6 +1065,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1065,6 +1120,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1115,6 +1171,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1132,6 +1189,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1189,6 +1249,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1214,6 +1276,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1453,12 +1516,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6700_SERIES=y +CONFIG_SOC_SERIES_HPM6000=y # # Hardware Drivers Config # -CONFIG_SOC_HPM6700=y +CONFIG_SOC_HPM6000=y # # On-chip Peripheral Drivers @@ -1485,6 +1548,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set # CONFIG_BSP_USING_UART15 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set @@ -1511,5 +1575,57 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_CAM is not set # CONFIG_BSP_USING_PANEL is not set # CONFIG_BSP_USING_RTT_LCD_DRIVER is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_TAMP is not set +# CONFIG_BSP_USING_VAD is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config + +# +# AMPAK Wi-Fi module Configuration +# +# end of AMPAK Wi-Fi module Configuration +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6750evk2/README.md b/bsp/hpmicro/hpm6750evk2/README.md index dd06637e34..f1b197e67b 100644 --- a/bsp/hpmicro/hpm6750evk2/README.md +++ b/bsp/hpmicro/hpm6750evk2/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk2.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6750evk2/README_zh.md b/bsp/hpmicro/hpm6750evk2/README_zh.md index ab908fe462..16d5471502 100644 --- a/bsp/hpmicro/hpm6750evk2/README_zh.md +++ b/bsp/hpmicro/hpm6750evk2/README_zh.md @@ -74,14 +74,14 @@ HPM6750EVK2 是由先楫半导体推出的一款基于RISCV内核的开发板， - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\cmsis_dap.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evk2.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6750evk2/SConscript b/bsp/hpmicro/hpm6750evk2/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6750evk2/SConscript +++ b/bsp/hpmicro/hpm6750evk2/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6750evk2/SConstruct b/bsp/hpmicro/hpm6750evk2/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6750evk2/SConstruct +++ b/bsp/hpmicro/hpm6750evk2/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6750evk2/applications/SConscript b/bsp/hpmicro/hpm6750evk2/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6750evk2/applications/SConscript +++ b/bsp/hpmicro/hpm6750evk2/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6750evk2/applications/main.c b/bsp/hpmicro/hpm6750evk2/applications/main.c index b766dd547e..a70f2f26dd 100644 --- a/bsp/hpmicro/hpm6750evk2/applications/main.c +++ b/bsp/hpmicro/hpm6750evk2/applications/main.c @@ -22,7 +22,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6750evk2/board/Kconfig b/bsp/hpmicro/hpm6750evk2/board/Kconfig index 5e67a28a13..2b9d9b1e8e 100644 --- a/bsp/hpmicro/hpm6750evk2/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk2/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6700 +config SOC_HPM6000 bool - select SOC_HPM6700_SERIES + select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -466,9 +466,27 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 + endif endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -485,7 +503,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -493,7 +511,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -515,7 +533,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -523,7 +541,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -536,7 +554,7 @@ menu "On-chip Peripheral Drivers" endif config BSP_USING_SPI2 bool "Enable SPI2" - default n + default y if BSP_USING_SPI2 config BSP_SPI2_USING_DMA bool "Enable SPI2 DMA" @@ -545,7 +563,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -553,7 +571,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -575,7 +593,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -583,7 +601,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -633,7 +651,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC0_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC0_USE_CACHEABLE_BUFFER config BSP_SDXC0_USE_CACHEABLE_BUFFER @@ -661,7 +679,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC0_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT config BSP_SDXC0_BUS_WIDTH_1BIT @@ -671,7 +689,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_BUS_WIDTH_8BIT bool "8-bit" endchoice - choice BSP_SDXC0_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC0_VOLTAGE_3V3 config BSP_SDXC0_VOLTAGE_3V3 @@ -696,7 +714,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC1_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC1_USE_CACHEABLE_BUFFER config BSP_SDXC1_USE_CACHEABLE_BUFFER @@ -723,7 +741,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC1_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC1_BUS_WIDTH_4BIT config BSP_SDXC1_BUS_WIDTH_1BIT @@ -731,7 +749,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_BUS_WIDTH_4BIT bool "4-bit" endchoice - choice BSP_SDXC1_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC1_VOLTAGE_3V3 config BSP_SDXC1_VOLTAGE_3V3 @@ -789,6 +807,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -859,6 +878,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -923,7 +951,6 @@ menu "On-chip Peripheral Drivers" bool "INIT_EXT_RAM_FOR_DATA" default y - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -932,7 +959,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWM + select RT_USING_PWM menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -971,7 +998,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_WDG bool "Enable Watchdog" default n @@ -1037,7 +1063,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC12 bool "Enable ADC12" @@ -1052,7 +1078,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC2 bool "Enable ADC2" default n - endif + endif menuconfig BSP_USING_ADC16 bool "Enable ADC16" default n @@ -1061,7 +1087,7 @@ menu "On-chip Peripheral Drivers" bool "Enable ADC3" default n endif - endif + endif menuconfig BSP_USING_CAMERA bool "Enable camera" @@ -1106,6 +1132,322 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_QEI + bool "Enable QEI (Quadrature Encoder Interface)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_FEMC + bool "Enable FEMC (Flexible External Memory Controller)" + default n + + menuconfig BSP_USING_VAD + bool "Enable VAD" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +menu "AMPAK Wi-Fi module Configuration" +config BSP_USING_MHD_WIFI +bool +default y if RT_USING_MHD +select BSP_USING_SDXC +select BSP_USING_SDXC1 +select BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN +help + Automatically enable SDXC1 interface when WiFi MHD driver is enabled. + Note: Please manually select non-cacheable buffer and fast RAM options for SDXC1 if needed. + endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg index 4af46a3ebb..9882c35c99 100644 --- a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg @@ -16,7 +16,7 @@ # 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI # [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) # 0 - Not needed -# 1 - QE bit is at bit 6 in Status Register 1 +# 1 - QE bit is at bit6 in Status Register 1 # 2 - QE bit is at bit1 in Status Register 2 # 3 - QE bit is at bit7 in Status Register 2 # 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 @@ -50,288 +50,187 @@ flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } proc init_sdram { } { # configure femc frequency # 133Mhz pll1_clk0: 266Mhz divide by 2 - #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - #$::_TARGET0 riscv dmi_write 0x3C 0x201 + #mww 0xF4001820 0x201 # 166Mhz pll2_clk0: 333Mhz divide by 2 - $::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x401 + mww 0xF4001820 0x401 # PC01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040208 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040208 0xC # PC00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040200 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040200 0xC # PB31 - $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401F8 0xC # PB30 - $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401F0 0xC # PB29 - $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401E8 0xC # PB28 - $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401E0 0xC # PB27 - $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401D8 0xC # PB26 - $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401D0 0xC # PB25 - $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401C8 0xC # PB24 - $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401C0 0xC # PB23 - $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401B8 0xC # PB22 - $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401B0 0xC # PB21 - $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401A8 0xC # PB20 - $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40401A0 0xC # PB19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040198 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040198 0xC # PB18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040190 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040190 0xC # PD13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040368 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040368 0xC # PD12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040360 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040360 0xC # PD10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040350 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040350 0xC # PD09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040348 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040348 0xC # PD08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040340 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040340 0xC # PD07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040338 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040338 0xC # PD06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040330 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040330 0xC # PD05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040328 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040328 0xC # PD04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040320 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040320 0xC # PD03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040318 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040318 0xC # PD02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040310 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040310 0xC # PD01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040308 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040308 0xC # PD00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040300 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040300 0xC # PC29 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402E8 0xC # PC28 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402E0 0xC # PC27 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402D8 0xC # PC22 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402B0 0xC # PC21 - $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402A8 0xC # PC17 - $::_TARGET0 riscv dmi_write 0x39 0xF4040288 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040288 0xC # PC15 - $::_TARGET0 riscv dmi_write 0x39 0xF4040278 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040278 0xC # PC12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040260 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040260 0xC # PC11 - $::_TARGET0 riscv dmi_write 0x39 0xF4040258 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040258 0xC # PC10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040250 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040250 0xC # PC09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040248 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040248 0xC # PC08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040240 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040240 0xC # PC07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040238 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040238 0xC # PC06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040230 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040230 0xC # PC05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040228 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040228 0xC # PC04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040220 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040220 0xC # PC14 - $::_TARGET0 riscv dmi_write 0x39 0xF4040270 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040270 0xC # PC13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040268 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040268 0xC # PC16 - # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - #$::_TARGET0 riscv dmi_write 0x3C 0x1000C + # mww 0xF4040280 0x1000C # PC26 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402D0 0xC # PC25 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402C8 0xC # PC19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040298 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040298 0xC # PC18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040290 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040290 0xC # PC23 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402B8 0xC # PC24 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402C0 0xC # PC30 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402F0 0xC # PC31 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402F8 0xC # PC02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040210 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040210 0xC # PC03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040218 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040218 0xC # femc configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 + mww 0xF3050000 0x1 sleep 10 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - $::_TARGET0 riscv dmi_write 0x39 0xF3050008 - $::_TARGET0 riscv dmi_write 0x3C 0x30524 - $::_TARGET0 riscv dmi_write 0x39 0xF305000C - $::_TARGET0 riscv dmi_write 0x3C 0x6030524 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + mww 0xF3050000 0x2 + mww 0xF3050008 0x30524 + mww 0xF305000C 0x6030524 + mww 0xF3050000 0x10000000 - $::_TARGET0 riscv dmi_write 0x39 0xF3050010 - $::_TARGET0 riscv dmi_write 0x3C 0x4000001b - $::_TARGET0 riscv dmi_write 0x39 0xF3050014 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050040 - $::_TARGET0 riscv dmi_write 0x3C 0xf32 + mww 0xF3050010 0x4000001b + mww 0xF3050014 0 + mww 0xF3050040 0xf32 # 133Mhz configuration - #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - #$::_TARGET0 riscv dmi_write 0x3C 0x884e22 + #mww 0xF3050044 0x884e22 # 166Mhz configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + mww 0xF3050044 0x884e33 - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + mww 0xF3050048 0x1020d0d + mww 0xF3050048 0x1020d0d + mww 0xF305004C 0x2020300 # config delay cell - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x3b - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x203b + mww 0xF3050150 0x3b + mww 0xF3050150 0x203b - $::_TARGET0 riscv dmi_write 0x39 0xF3050094 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050098 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF3050094 0 + mww 0xF3050098 0 # precharge all - $::_TARGET0 riscv dmi_write 0x39 0xF3050090 - $::_TARGET0 riscv dmi_write 0x3C 0x40000000 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + mww 0xF3050090 0x40000000 + mww 0xF305009C 0xA55A000F sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # auto refresh - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305003C 0x3 + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # set mode - $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 - $::_TARGET0 riscv dmi_write 0x3C 0x33 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + mww 0xF30500A0 0x33 + mww 0xF305009C 0xA55A000A sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + mww 0xF305004C 0x2020301 echo "SDRAM has been initialized" } diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 32b87da2cf..59a3f2310d 100644 --- a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,9 +1,12 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause # - -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -14,43 +17,25 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -proc dmi_write {reg value} { - $::_TARGET0 riscv dmi_write ${reg} ${value} -} - -proc dmi_read {reg} { - set v [$::_TARGET0 riscv dmi_read ${reg}] - return ${v} -} -proc dmi_write_memory {addr value} { - dmi_write 0x39 ${addr} - dmi_write 0x3C ${value} -} - -proc dmi_read_memory {addr} { - set sbcs [expr 0x100000 | [dmi_read 0x38]] - dmi_write 0x38 ${sbcs} - dmi_write 0x39 ${addr} - set value [dmi_read 0x3C] - return ${value} -} +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] proc release_core1 {} { - set chip_rev [dmi_read_memory 0x2001FF00] + set chip_rev [sba_read_mem 0x2001FF00] if {$chip_rev != 0x56010100 } { # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + sba_write_mem 0xF4002C08 0x20016284 } else { - dmi_write_memory 0xF4002C08 0x2001660c + sba_write_mem 0xF4002C08 0x2001660c } # set boot flag for core1 - dmi_write_memory 0xF4002C0C 0xC1BEF1A9 + sba_write_mem 0xF4002C0C 0xC1BEF1A9 # release core1 - dmi_write_memory 0xF4002C00 0x1000 + sba_write_mem 0xF4002C00 0x1000 } set _TARGET1 $_CHIP.cpu1 @@ -65,3 +50,7 @@ $_TARGET1 configure -event reset-deassert-pre { $::_TARGET0 arp_poll release_core1 } + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index f873527fb7..0454c4d0f9 100644 --- a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld deleted file mode 100644 index 2f39e2409d..0000000000 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 768K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - /* hpm_sdk drivers */ - KEEP(*hpm_sdxc_drv*.o (.text .text* .rodata .rodata*)) - - /* WHD related */ - KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) - KEEP(*whd_sdpcm*.o (.text .text* .rodata .rodata*)) - KEEP(*whd_thread*.o (.text .text* .rodata .rodata*)) - - /* LWIP */ - KEEP(*lwip*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld index 8b4f6137da..0c85c770f1 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld @@ -31,6 +31,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -178,7 +187,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -188,6 +197,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -279,7 +297,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -306,7 +324,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index bcd6c6e125..0000000000 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld deleted file mode 100644 index 8618b40e55..0000000000 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld index e03cd86e66..a97ce80e97 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld @@ -214,6 +214,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + /* Note: .tbss and .tdata should be adjacent */ __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); .tdata : AT(__tdata_load_addr__) { diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld deleted file mode 100644 index fc810f781d..0000000000 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > AXI_SRAM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - *(FalPartTable) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > AXI_SRAM - - .rel : { - KEEP(*(.rel*)) - } > AXI_SRAM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > AXI_SRAM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > AXI_SRAM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - . = ALIGN(8); - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - /* NOTE: - Please keep in mind that the load section for rw data is after .text section - Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section - and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: - 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ - 2. the generated binary file will be larger because the space occupied by - NOLOAD sections will be filled - */ - __data_load_addr__ = __etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - /* Note: Place all NOLOAD sections together */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.c b/bsp/hpmicro/hpm6750evk2/board/pinmux.c index 2abb2245be..d6db7a525c 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.c @@ -114,7 +114,7 @@ void init_trgmux_pins(uint32_t pin) HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); } -void init_i2c_pins_as_gpio(I2C_Type *ptr) +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr) { if (ptr == HPM_I2C0) { /* I2C0 */ @@ -124,12 +124,12 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_I2C0_SCL @@ -142,9 +142,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } void init_femc_pins(void) diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.h b/bsp/hpmicro/hpm6750evk2/board/pinmux.h index ac8a2e7c35..24c4c4fbe0 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_femc_pins(void); void init_gpio_pins(void); @@ -43,7 +43,7 @@ void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); -void init_i2c_pins_as_gpio(I2C_Type *ptr); +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c index ea3693f141..cedf0c49b7 100644 --- a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c @@ -39,14 +39,20 @@ void rtt_board_init(void) { rtt_os_tick_clock(); board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm6750evk2/makefile.targets b/bsp/hpmicro/hpm6750evk2/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.h b/bsp/hpmicro/hpm6750evk2/rtconfig.h index b7f19f119f..00cfd7d890 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.h +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -103,7 +113,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -302,6 +312,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -329,12 +343,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -414,11 +440,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6700_SERIES +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ -#define SOC_HPM6700 +#define SOC_HPM6000 /* On-chip Peripheral Drivers */ @@ -432,6 +458,33 @@ #define BSP_USING_FEMC #define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ + +/* AMPAK Wi-Fi module Configuration */ + +/* end of AMPAK Wi-Fi module Configuration */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.py b/bsp/hpmicro/hpm6750evk2/rtconfig.py index e37092268b..bc118615e0 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c index 4fc6914d56..54517adc4d 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram * function code to its destination. */ diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S index 5ac683dbc2..6b394172aa 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S @@ -58,11 +58,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ @@ -75,6 +84,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -87,3 +97,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6750evk2/startup/SConscript b/bsp/hpmicro/hpm6750evk2/startup/SConscript index 3c804fe451..97393e8517 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/SConscript +++ b/bsp/hpmicro/hpm6750evk2/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs') diff --git a/bsp/hpmicro/hpm6750evkmini/.config b/bsp/hpmicro/hpm6750evkmini/.config index 0af46a1cdc..e3256fb40f 100644 --- a/bsp/hpmicro/hpm6750evkmini/.config +++ b/bsp/hpmicro/hpm6750evkmini/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -264,10 +274,10 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -461,6 +471,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -576,6 +587,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -635,6 +647,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -783,6 +797,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -816,7 +832,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -895,12 +925,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -908,6 +945,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -987,6 +1041,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1041,6 +1096,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1091,6 +1147,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1108,6 +1165,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1165,6 +1225,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1190,6 +1252,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1429,12 +1492,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6700_SERIES=y +CONFIG_SOC_SERIES_HPM6000=y # # Hardware Drivers Config # -CONFIG_SOC_HPM6700=y +CONFIG_SOC_HPM6000=y # # On-chip Peripheral Drivers @@ -1462,6 +1525,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set # CONFIG_BSP_USING_UART15 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set @@ -1488,5 +1552,55 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_CAM is not set # CONFIG_BSP_USING_PANEL is not set # CONFIG_BSP_USING_RTT_LCD_DRIVER is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_TAMP is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config + +# +# AMPAK Wi-Fi module Configuration +# +# end of AMPAK Wi-Fi module Configuration +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini b/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini index 1ae5ab7322..65ac9a0814 100644 --- a/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini +++ b/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini @@ -10,7 +10,7 @@ chip_name=HPM6750 selected_rtt_version=4.0.5 bsp_version=0.3.0 os_branch=full -output_project_path=C\:/DevTools/RT-ThreadStudio/workspace +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6750evkmini is_base_example_project=True is_use_scons_build=True project_base_bsp=true diff --git a/bsp/hpmicro/hpm6750evkmini/README.md b/bsp/hpmicro/hpm6750evkmini/README.md index 00cfb6542a..6e8fc45719 100644 --- a/bsp/hpmicro/hpm6750evkmini/README.md +++ b/bsp/hpmicro/hpm6750evkmini/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evkmini.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6750evkmini/README_zh.md b/bsp/hpmicro/hpm6750evkmini/README_zh.md index 00b4c9bb14..69f6be8825 100644 --- a/bsp/hpmicro/hpm6750evkmini/README_zh.md +++ b/bsp/hpmicro/hpm6750evkmini/README_zh.md @@ -74,14 +74,14 @@ HPM6750EVKMINI 是由先楫半导体推出的一款基于RISCV内核的开发板 - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6750-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6750evkmini.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6750evkmini/SConscript b/bsp/hpmicro/hpm6750evkmini/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6750evkmini/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6750evkmini/SConstruct b/bsp/hpmicro/hpm6750evkmini/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6750evkmini/SConstruct +++ b/bsp/hpmicro/hpm6750evkmini/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6750evkmini/applications/SConscript b/bsp/hpmicro/hpm6750evkmini/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6750evkmini/applications/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6750evkmini/applications/main.c b/bsp/hpmicro/hpm6750evkmini/applications/main.c index a5a7f07c73..8aff6b8126 100644 --- a/bsp/hpmicro/hpm6750evkmini/applications/main.c +++ b/bsp/hpmicro/hpm6750evkmini/applications/main.c @@ -19,7 +19,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig index bc3cdc8111..caff3fd139 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/Kconfig +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6700 +config SOC_HPM6000 bool - select SOC_HPM6700_SERIES + select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -478,6 +478,25 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_SPI @@ -496,7 +515,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -504,7 +523,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -526,7 +545,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -534,7 +553,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -547,7 +566,7 @@ menu "On-chip Peripheral Drivers" endif config BSP_USING_SPI2 bool "Enable SPI2" - default n + default y if BSP_USING_SPI2 config BSP_SPI2_USING_DMA bool "Enable SPI2 DMA" @@ -556,7 +575,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -564,7 +583,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -586,7 +605,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -594,7 +613,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -639,7 +658,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC0_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC0_USE_CACHEABLE_BUFFER config BSP_SDXC0_USE_CACHEABLE_BUFFER @@ -667,7 +686,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC0_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT config BSP_SDXC0_BUS_WIDTH_1BIT @@ -677,7 +696,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_BUS_WIDTH_8BIT bool "8-bit" endchoice - choice BSP_SDXC0_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC0_VOLTAGE_3V3 config BSP_SDXC0_VOLTAGE_3V3 @@ -702,7 +721,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC1_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC1_USE_CACHEABLE_BUFFER config BSP_SDXC1_USE_CACHEABLE_BUFFER @@ -729,7 +748,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC1_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC1_BUS_WIDTH_4BIT config BSP_SDXC1_BUS_WIDTH_1BIT @@ -737,7 +756,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_BUS_WIDTH_4BIT bool "4-bit" endchoice - choice BSP_SDXC1_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC1_VOLTAGE_3V3 config BSP_SDXC1_VOLTAGE_3V3 @@ -749,10 +768,10 @@ menu "On-chip Peripheral Drivers" endchoice config BSP_SDXC1_VSEL_PIN default "PD29" - string "VSEL pin name" + string "VSEL pin name" config BSP_SDXC1_PWR_PIN default "None" - string "PWR pin name" + string "PWR pin name" endif endif @@ -795,6 +814,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -865,6 +885,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -929,7 +958,6 @@ menu "On-chip Peripheral Drivers" bool "INIT_EXT_RAM_FOR_DATA" default y - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -938,7 +966,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWM + select RT_USING_PWM menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -974,7 +1002,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_WDG bool "Enable Watchdog" default n @@ -1040,7 +1067,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC12 bool "Enable ADC12" @@ -1111,6 +1138,309 @@ menu "On-chip Peripheral Drivers" default 1 endif + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_QEI + bool "Enable QEI (Quadrature Encoder Interface)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +menu "AMPAK Wi-Fi module Configuration" +config BSP_USING_MHD_WIFI +bool +default y if RT_USING_MHD +select BSP_USING_SDXC +select BSP_USING_SDXC1 +select BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN +help + Automatically enable SDXC1 interface when WiFi MHD driver is enabled. + Note: Please manually select non-cacheable buffer and fast RAM options for SDXC1 if needed. + endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg index 0c0dc2e3c4..bd37e92835 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 HPMicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # openocd flash driver argument: @@ -16,7 +16,7 @@ # 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI # [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) # 0 - Not needed -# 1 - QE bit is at bit 6 in Status Register 1 +# 1 - QE bit is at bit6 in Status Register 1 # 2 - QE bit is at bit1 in Status Register 2 # 3 - QE bit is at bit7 in Status Register 2 # 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 @@ -50,242 +50,157 @@ flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } proc init_sdram { } { -# configure dram frequency +# configure femc frequency # 133Mhz pll1_clk0: 266Mhz divide by 2 - #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 + #mww 0xF4001820 0x201 # 166Mhz pll2_clk0: 333Mhz divide by 2 - $::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x401 + mww 0xF4001820 0x401 # PD13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040368 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040368 0xC # PD12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040360 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040360 0xC # PD10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040350 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040350 0xC # PD09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040348 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040348 0xC # PD08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040340 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040340 0xC # PD07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040338 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040338 0xC # PD06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040330 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040330 0xC # PD05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040328 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040328 0xC # PD04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040320 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040320 0xC # PD03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040318 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040318 0xC # PD02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040310 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040310 0xC # PD01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040308 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040308 0xC # PD00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040300 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040300 0xC # PC29 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402E8 0xC # PC28 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402E0 0xC # PC27 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402D8 0xC # PC22 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402B0 0xC # PC21 - $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402A8 0xC # PC17 - $::_TARGET0 riscv dmi_write 0x39 0xF4040288 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040288 0xC # PC15 - $::_TARGET0 riscv dmi_write 0x39 0xF4040278 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040278 0xC # PC12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040260 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040260 0xC # PC11 - $::_TARGET0 riscv dmi_write 0x39 0xF4040258 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040258 0xC # PC10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040250 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040250 0xC # PC09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040248 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040248 0xC # PC08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040240 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040240 0xC # PC07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040238 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040238 0xC # PC06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040230 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040230 0xC # PC05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040228 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040228 0xC # PC04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040220 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040220 0xC # PC14 - $::_TARGET0 riscv dmi_write 0x39 0xF4040270 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040270 0xC # PC13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040268 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040268 0xC # PC16 - # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # mww 0xF4040280 0x1000C # PC26 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402D0 0xC # PC25 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402C8 0xC # PC19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040298 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040298 0xC # PC18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040290 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040290 0xC # PC23 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402B8 0xC # PC24 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402C0 0xC # PC30 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402F0 0xC # PC31 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF40402F8 0xC # PC02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040210 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040210 0xC # PC03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040218 - $::_TARGET0 riscv dmi_write 0x3C 0xC + mww 0xF4040218 0xC - # dramc configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 + # femc configuration + mww 0xF3050000 0x1 sleep 10 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - $::_TARGET0 riscv dmi_write 0x39 0xF3050008 - $::_TARGET0 riscv dmi_write 0x3C 0x30524 - $::_TARGET0 riscv dmi_write 0x39 0xF305000C - $::_TARGET0 riscv dmi_write 0x3C 0x6030524 - $::_TARGET0 riscv dmi_write 0x39 0xF3050000 - $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + mww 0xF3050000 0x2 + mww 0xF3050008 0x30524 + mww 0xF305000C 0x6030524 + mww 0xF3050000 0x10000000 # 16MB - $::_TARGET0 riscv dmi_write 0x39 0xF3050010 - $::_TARGET0 riscv dmi_write 0x3C 0x40000019 - $::_TARGET0 riscv dmi_write 0x39 0xF3050014 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF3050010 0x40000019 + mww 0xF3050014 0 # 16-bit - $::_TARGET0 riscv dmi_write 0x39 0xF3050040 - $::_TARGET0 riscv dmi_write 0x3C 0xf31 + mww 0xF3050040 0xf31 # 133Mhz configuration - #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + #mww 0xF3050044 0x884e22 # 166Mhz configuration - $::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + mww 0xF3050044 0x884e33 - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF3050048 - $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + mww 0xF3050048 0x1020d0d + mww 0xF3050048 0x1020d0d + mww 0xF305004C 0x2020300 # config delay cell - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x3b - $::_TARGET0 riscv dmi_write 0x39 0xF3050150 - $::_TARGET0 riscv dmi_write 0x3C 0x203b + mww 0xF3050150 0x3b + mww 0xF3050150 0x203b - $::_TARGET0 riscv dmi_write 0x39 0xF3050094 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3050098 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF3050094 0 + mww 0xF3050098 0 # precharge all - $::_TARGET0 riscv dmi_write 0x39 0xF3050090 - $::_TARGET0 riscv dmi_write 0x3C 0x40000000 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + mww 0xF3050090 0x40000000 + mww 0xF305009C 0xA55A000F sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # auto refresh - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + mww 0xF305003C 0x3 + mww 0xF305009C 0xA55A000C sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 # set mode - $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 - $::_TARGET0 riscv dmi_write 0x3C 0x33 - $::_TARGET0 riscv dmi_write 0x39 0xF305009C - $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + mww 0xF30500A0 0x33 + mww 0xF305009C 0xA55A000A sleep 500 - $::_TARGET0 riscv dmi_write 0x39 0xF305003C - $::_TARGET0 riscv dmi_write 0x3C 0x3 + mww 0xF305003C 0x3 - $::_TARGET0 riscv dmi_write 0x39 0xF305004C - $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + mww 0xF305004C 0x2020301 echo "SDRAM has been initialized" } diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 610d4c578b..504900a919 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,9 +1,12 @@ -# Copyright 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause # - -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -14,48 +17,41 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -proc dmi_write {reg value} { - $::_TARGET0 riscv dmi_write ${reg} ${value} -} +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] -proc dmi_read {reg} { - set v [$::_TARGET0 riscv dmi_read ${reg}] - return ${v} -} -proc dmi_write_memory {addr value} { - dmi_write 0x39 ${addr} - dmi_write 0x3C ${value} -} +proc release_core1 {} { -proc dmi_read_memory {addr} { - set sbcs [expr 0x100000 | [dmi_read 0x38]] - dmi_write 0x38 ${sbcs} - dmi_write 0x39 ${addr} - set value [dmi_read 0x3C] - return ${value} -} + set chip_rev [sba_read_mem 0x2001FF00] -proc release_core1 {} { - # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + if {$chip_rev != 0x56010100 } { + # set start point for core1 + sba_write_mem 0xF4002C08 0x20016284 + } else { + sba_write_mem 0xF4002C08 0x2001660c + } # set boot flag for core1 - dmi_write_memory 0xF4002C0C 0xC1BEF1A9 + sba_write_mem 0xF4002C0C 0xC1BEF1A9 # release core1 - dmi_write_memory 0xF4002C00 0x1000 -} - -$_TARGET0 configure -event examine-end { - release_core1 + sba_write_mem 0xF4002C00 0x1000 } set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event examine-start { + release_core1 +} + $_TARGET1 configure -event reset-deassert-pre { - $::_TARGET1 arp_poll + $::_TARGET0 arp_poll release_core1 } +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index 44c232b962..0454c4d0f9 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright 2021 HPMicro +# Copyright (c) 2021,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6750 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6750 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF40C001C 24000000 +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld index 21ea55a2cb..6a8cf70c9c 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld @@ -31,6 +31,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -178,7 +187,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -188,6 +197,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -279,7 +297,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -306,7 +324,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index d46f1913ff..0000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld deleted file mode 100644 index cae486ba98..0000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > AXI_SRAM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > AXI_SRAM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld index cc221f78bf..d94c0968ed 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld @@ -212,7 +212,16 @@ SECTIONS KEEP(*(.fast_ram.init.*)) __fast_ram_init_end__ = .; . = ALIGN(8); - } > DLM + } > AXI_SRAM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM /* Note: .tbss and .tdata should be adjacent */ __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld deleted file mode 100644 index d702772429..0000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > AXI_SRAM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - *(FalPartTable) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > AXI_SRAM - - .rel : { - KEEP(*(.rel*)) - } > AXI_SRAM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > AXI_SRAM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > AXI_SRAM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - . = ALIGN(8); - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - /* NOTE: - Please keep in mind that the load section for rw data is after .text section - Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section - and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: - 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ - 2. the generated binary file will be larger because the space occupied by - NOLOAD sections will be filled - */ - __data_load_addr__ = __etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - /* Note: Place all NOLOAD sections together */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c index 68ce3d99ad..bcdcad2a7f 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c @@ -126,19 +126,19 @@ void init_trgmux_pins(uint32_t pin) HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); } -void init_i2c_pins_as_gpio(I2C_Type *ptr) +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr) { if (ptr == HPM_I2C0) { /* I2C0 */ HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL @@ -155,9 +155,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while (1) { - } + return status_invalid_argument; } + return status_success; } void init_femc_pins(void) { diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h index 1ae0f3ffad..0fed486aa9 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h @@ -15,7 +15,7 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_femc_pins(void); void init_gpio_pins(void); @@ -46,7 +46,7 @@ void init_adc12_pins(void); void init_adc16_pins(void); void init_adc_bldc_pins(void); -void init_i2c_pins_as_gpio(I2C_Type *ptr); +hpm_stat_t init_i2c_pins_as_gpio(I2C_Type *ptr); void init_beep_pwm_pins(void); void init_led_pins_as_pwm(void); diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c index 056bd3902f..ea8b677b9d 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c @@ -39,14 +39,20 @@ void rtt_board_init(void) { rtt_os_tick_clock(); board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm6750evkmini/makefile.targets b/bsp/hpmicro/hpm6750evkmini/makefile.targets index 502182f4e7..4583a13f1c 100644 --- a/bsp/hpmicro/hpm6750evkmini/makefile.targets +++ b/bsp/hpmicro/hpm6750evkmini/makefile.targets @@ -3,4 +3,4 @@ clean2: -$(RM) $(OBJS) *.elf -@echo ' ' -*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld) +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.h b/bsp/hpmicro/hpm6750evkmini/rtconfig.h index ec1e6443a7..d01da9d651 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.h +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -291,6 +301,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -318,12 +332,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -403,11 +429,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6700_SERIES +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ -#define SOC_HPM6700 +#define SOC_HPM6000 /* On-chip Peripheral Drivers */ @@ -421,6 +447,33 @@ #define BSP_USING_FEMC #define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ + +/* AMPAK Wi-Fi module Configuration */ + +/* end of AMPAK Wi-Fi module Configuration */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py index e37092268b..bc118615e0 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.py +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c index 4fc6914d56..54517adc4d 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c @@ -54,6 +54,8 @@ extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram * function code to its destination. */ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S index 5ac683dbc2..6b394172aa 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S @@ -58,11 +58,20 @@ _start: /* Initialize FCSR */ fscsr zero #endif - /* Disable Vector mode */ - csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ la t0, SW_handler csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif /* System reset handler */ @@ -75,6 +84,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -87,3 +97,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/SConscript b/bsp/hpmicro/hpm6750evkmini/startup/SConscript index 3c804fe451..97393e8517 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs') diff --git a/bsp/hpmicro/hpm6800evk/.config b/bsp/hpmicro/hpm6800evk/.config index 9e781ff3ba..a96ab924f1 100644 --- a/bsp/hpmicro/hpm6800evk/.config +++ b/bsp/hpmicro/hpm6800evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -182,7 +192,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -241,11 +251,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -266,10 +276,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -462,6 +472,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -577,6 +588,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -636,6 +648,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -784,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -817,7 +833,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -896,12 +926,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -909,6 +946,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -988,6 +1042,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1042,6 +1097,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1092,6 +1148,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1109,6 +1166,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1166,6 +1226,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1191,6 +1253,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1430,12 +1493,12 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6800_SERIES=y +CONFIG_SOC_SERIES_HPM6000=y # # Hardware Drivers Config # -CONFIG_SOC_HPM6800=y +CONFIG_SOC_HPM6000=y # # On-chip Peripheral Drivers @@ -1461,6 +1524,7 @@ CONFIG_BSP_UART3_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set @@ -1490,5 +1554,61 @@ CONFIG_BSP_UART3_IRQ_PRIORITY=1 # CONFIG_BSP_USING_LVB is not set # CONFIG_BSP_USING_LCB is not set # CONFIG_BSP_USING_RTT_LCD_DRIVER is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_FFA is not set +# CONFIG_BSP_USING_TAMP is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_GWC is not set +# CONFIG_BSP_USING_VAD is not set +# CONFIG_BSP_USING_SMIX is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config + +# +# AMPAK Wi-Fi module Configuration +# +# end of AMPAK Wi-Fi module Configuration +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6800evk/README.md b/bsp/hpmicro/hpm6800evk/README.md index 651cd94dd0..861a18413a 100644 --- a/bsp/hpmicro/hpm6800evk/README.md +++ b/bsp/hpmicro/hpm6800evk/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6880.cfg -f board\debug_scripts\openocd\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6880.cfg -f board\debug_scripts\openocd\boards\hpm6800evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6800evk/README_zh.md b/bsp/hpmicro/hpm6800evk/README_zh.md index b9c0722889..b19d4ae55a 100644 --- a/bsp/hpmicro/hpm6800evk/README_zh.md +++ b/bsp/hpmicro/hpm6800evk/README_zh.md @@ -74,14 +74,14 @@ HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，� - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6880.cfg -f board\debug_scripts\openocd\boards\hpm6800evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6880.cfg -f boards\debug_scripts\boards\hpm6800evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6880.cfg -f board\debug_scripts\openocd\boards\hpm6800evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6800evk/SConscript b/bsp/hpmicro/hpm6800evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6800evk/SConscript +++ b/bsp/hpmicro/hpm6800evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6800evk/SConstruct b/bsp/hpmicro/hpm6800evk/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6800evk/SConstruct +++ b/bsp/hpmicro/hpm6800evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6800evk/applications/SConscript b/bsp/hpmicro/hpm6800evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6800evk/applications/SConscript +++ b/bsp/hpmicro/hpm6800evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6800evk/applications/main.c b/bsp/hpmicro/hpm6800evk/applications/main.c index a5a7f07c73..8aff6b8126 100644 --- a/bsp/hpmicro/hpm6800evk/applications/main.c +++ b/bsp/hpmicro/hpm6800evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6800evk/board/Kconfig b/bsp/hpmicro/hpm6800evk/board/Kconfig index f1a0f79a98..bd88a4fe63 100644 --- a/bsp/hpmicro/hpm6800evk/board/Kconfig +++ b/bsp/hpmicro/hpm6800evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6800 +config SOC_HPM6000 bool - select SOC_HPM6800_SERIES + select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -87,6 +87,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -114,6 +119,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -141,6 +151,11 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" @@ -168,6 +183,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -195,6 +215,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -222,6 +247,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -249,6 +279,30 @@ menu "On-chip Peripheral Drivers" int "UART7 Interrupt Priority" range 1 7 default 1 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif @@ -268,7 +322,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -276,7 +330,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -298,7 +352,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -306,7 +360,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -328,7 +382,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -336,7 +390,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -358,7 +412,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -366,7 +420,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -392,7 +446,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PHY if BSP_USING_ETH if BSP_USING_ETH - choice BSP_ETH0_SEL + choice prompt "ETH" default BSP_USING_ETH0 @@ -415,7 +469,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC0_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC0_USE_CACHEABLE_BUFFER config BSP_SDXC0_USE_CACHEABLE_BUFFER @@ -443,7 +497,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC0_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT config BSP_SDXC0_BUS_WIDTH_1BIT @@ -453,7 +507,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_BUS_WIDTH_8BIT bool "8-bit" endchoice - choice BSP_SDXC0_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC0_VOLTAGE_1V8 config BSP_SDXC0_VOLTAGE_3V3 @@ -478,7 +532,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN bool "Enable Interrupt-driven mode" default n - choice BSP_SDXC1_SEL + choice prompt "Select buffer type for unaligned data transfer" default BSP_SDXC1_USE_CACHEABLE_BUFFER config BSP_SDXC1_USE_CACHEABLE_BUFFER @@ -505,7 +559,7 @@ menu "On-chip Peripheral Drivers" int "SDXC Interrupt Priority" range 1 7 default 1 - choice BSP_SDXC1_BUS_WIDTH_SEL + choice prompt "Select BUS_WIDTH" default BSP_SDXC1_BUS_WIDTH_4BIT config BSP_SDXC1_BUS_WIDTH_1BIT @@ -513,7 +567,7 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC1_BUS_WIDTH_4BIT bool "4-bit" endchoice - choice BSP_SDXC1_VOLT_SEL + choice prompt "Select Voltage" default BSP_SDXC1_VOLTAGE_3V3 config BSP_SDXC1_VOLTAGE_3V3 @@ -571,6 +625,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -641,6 +696,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -698,12 +762,10 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig INIT_EXT_RAM_FOR_DATA bool "INIT_EXT_RAM_FOR_DATA" default y - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -746,7 +808,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_EWDG bool "Enable EWDG" default n @@ -842,16 +903,11 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" default n - if BSP_USING_ADC16 - config BSP_USING_ADC3 - bool "Enable ADC3" - default n - endif endif menuconfig BSP_USING_CAMERA @@ -860,7 +916,7 @@ menu "On-chip Peripheral Drivers" select BSP_USING_CAM if BSP_USING_CAMERA select BSP_USING_MIPI_CSI if BSP_USING_CAMERA if BSP_USING_CAMERA - choice BSP_CAMERA_SEL + choice prompt "Select camera" default BSP_USING_CAMERA_OV5640 config BSP_USING_CAMERA_MT9M114 @@ -886,7 +942,7 @@ menu "On-chip Peripheral Drivers" select BSP_USING_MIPI_DSI if BSP_USING_PANEL select BSP_USING_PIXELMUX if BSP_USING_PANEL if BSP_USING_PANEL - choice BSP_USEING_PANEL_SEL + choice prompt "Select Panel" default BSP_USEING_PANEL_MIPI_MC10128007_31B config BSP_USEING_PANEL_RGB_TM070RDH13 @@ -930,7 +986,335 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_FFA + bool "Enable FFA" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_GWC + bool "Enable GWC" + default n + + menuconfig BSP_USING_VAD + bool "Enable VAD" + default n + + menuconfig BSP_USING_SMIX + bool "Enable SMIX" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" +endmenu + +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + endmenu +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif endmenu +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +menu "AMPAK Wi-Fi module Configuration" +config BSP_USING_MHD_WIFI +bool +default y if RT_USING_MHD +select BSP_USING_SDXC +select BSP_USING_SDXC1 +select BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN +help + Automatically enable SDXC1 interface when WiFi MHD driver is enabled. + Note: Please manually select non-cacheable buffer and fast RAM options for SDXC1 if needed. + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg index 5f21fd27b4..a97c83715d 100644 --- a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg @@ -1,110 +1,116 @@ # Copyright (c) 2023 HPMicro # SPDX-License-Identifier: BSD-3-Clause +# +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } proc init_ddr3 {} { # ddr dcdc setup - $::_TARGET0 riscv dmi_write 0x39 0xF4104080 - $::_TARGET0 riscv dmi_write 0x3C 0x10578 + mww 0xF4104080 0x10578 # ddr3 setup - $::_TARGET0 riscv dmi_write 0x39 0xF40C0180 - $::_TARGET0 riscv dmi_write 0x3C 0x30000019 - $::_TARGET0 riscv dmi_write 0x39 0xF400180C - $::_TARGET0 riscv dmi_write 0x3C 0x09100401 + mww 0xF40C0180 0x30000019 + mww 0xF400180C 0x09100401 - $::_TARGET0 riscv dmi_write 0x39 0xF4153000 - $::_TARGET0 riscv dmi_write 0x3C 0xF0000010 + mww 0xF4153000 0xF0000010 - $::_TARGET0 riscv dmi_write 0x39 0xF30101B0 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF30101B0 0 - $::_TARGET0 riscv dmi_write 0x39 0xF4150040 - $::_TARGET0 riscv dmi_write 0x3C 0xf004641f + mww 0xF4150040 0xf004641f - $::_TARGET0 riscv dmi_write 0x39 0xF4153000 - $::_TARGET0 riscv dmi_write 0x3C 0xf0000011 + mww 0xF4153000 0xf0000011 - $::_TARGET0 riscv dmi_write 0x39 0xF3013000 - $::_TARGET0 riscv dmi_write 0x3C 0xf4000000 + mww 0xF3013000 0xf4000000 - $::_TARGET0 riscv dmi_write 0x39 0xF3010490 - $::_TARGET0 riscv dmi_write 0x3C 1 + mww 0xF3010490 1 - $::_TARGET0 riscv dmi_write 0x39 0xF3010000 - $::_TARGET0 riscv dmi_write 0x3C 0x1040001 + mww 0xF3010000 0x1040001 - $::_TARGET0 riscv dmi_write 0x39 0xF30100D0 - $::_TARGET0 riscv dmi_write 0x3C 0x4002004e + mww 0xF30100D0 0x4002004e - $::_TARGET0 riscv dmi_write 0x39 0xF3010110 - $::_TARGET0 riscv dmi_write 0x3C 0x05010407 - $::_TARGET0 riscv dmi_write 0x39 0xF3010190 - $::_TARGET0 riscv dmi_write 0x3C 0x07040102 - $::_TARGET0 riscv dmi_write 0x39 0xF3010194 - $::_TARGET0 riscv dmi_write 0x3C 0x20404 - $::_TARGET0 riscv dmi_write 0x39 0xF30101A4 - $::_TARGET0 riscv dmi_write 0x3C 0x20008 - $::_TARGET0 riscv dmi_write 0x39 0xF3010240 - $::_TARGET0 riscv dmi_write 0x3C 0x06000600 + mww 0xF3010110 0x05010407 + mww 0xF3010190 0x07040102 + mww 0xF3010194 0x20404 + mww 0xF30101A4 0x20008 + mww 0xF3010240 0x06000600 - $::_TARGET0 riscv dmi_write 0x39 0xF3010200 - $::_TARGET0 riscv dmi_write 0x3C 0x1F1F1F - $::_TARGET0 riscv dmi_write 0x39 0xF3010204 - $::_TARGET0 riscv dmi_write 0x3C 0x121212 - $::_TARGET0 riscv dmi_write 0x39 0xF3010208 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF301020C - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3010210 - $::_TARGET0 riscv dmi_write 0x3C 0x1F1F - $::_TARGET0 riscv dmi_write 0x39 0xF3010214 - $::_TARGET0 riscv dmi_write 0x3C 0x06030303 - $::_TARGET0 riscv dmi_write 0x39 0xF3010218 - $::_TARGET0 riscv dmi_write 0x3C 0x0F060606 + mww 0xF3010200 0x1F1F1F + mww 0xF3010204 0x121212 + mww 0xF3010208 0 + mww 0xF301020C 0 + mww 0xF3010210 0x1F1F + mww 0xF3010214 0x06030303 + mww 0xF3010218 0x0F060606 - $::_TARGET0 riscv dmi_write 0x39 0xF3013000 - $::_TARGET0 riscv dmi_write 0x3C 0xFC000000 + mww 0xF3013000 0xFC000000 - $::_TARGET0 riscv dmi_write 0x39 0xF4150054 - $::_TARGET0 riscv dmi_write 0x3C 0xc70 - $::_TARGET0 riscv dmi_write 0x39 0xF4150058 - $::_TARGET0 riscv dmi_write 0x3C 0x6 - $::_TARGET0 riscv dmi_write 0x39 0xF415005c - $::_TARGET0 riscv dmi_write 0x3C 0x18 - $::_TARGET0 riscv dmi_write 0x39 0xF4150048 - $::_TARGET0 riscv dmi_write 0x3C 0x919c8866 - $::_TARGET0 riscv dmi_write 0x39 0xF415004c - $::_TARGET0 riscv dmi_write 0x3C 0x1a838360 - $::_TARGET0 riscv dmi_write 0x39 0xF415008c - $::_TARGET0 riscv dmi_write 0x3C 0xf06d50 - $::_TARGET0 riscv dmi_write 0x39 0xF4150050 - $::_TARGET0 riscv dmi_write 0x3C 0x3002d200 + mww 0xF4150054 0xc70 + mww 0xF4150058 0x6 + mww 0xF415005c 0x18 + mww 0xF4150048 0x919c8866 + mww 0xF415004c 0x1a838360 + mww 0xF415008c 0xf06d50 + mww 0xF4150050 0x3002d200 - $::_TARGET0 riscv dmi_write 0x39 0xF30101b0 - $::_TARGET0 riscv dmi_write 0x3C 1 + mww 0xF30101b0 1 sleep 100 - $::_TARGET0 riscv dmi_write 0x39 0xF4150068 - $::_TARGET0 riscv dmi_write 0x3C 0x930035C7 - $::_TARGET0 riscv dmi_write 0x39 0xF4150004 - $::_TARGET0 riscv dmi_write 0x3C 0xFF81 + mww 0xF4150068 0x930035C7 + mww 0xF4150004 0xFF81 sleep 200 echo "ddr3 has been enabled!" @@ -112,107 +118,65 @@ proc init_ddr3 {} { proc init_dram {} { # ddr dcdc setup - $::_TARGET0 riscv dmi_write 0x39 0xF4104080 - $::_TARGET0 riscv dmi_write 0x3C 0x10708 + mww 0xF4104080 0x10708 # pll1 setup - $::_TARGET0 riscv dmi_write 0x39 0xF40c0180 - $::_TARGET0 riscv dmi_write 0x3C 0xb0000016 - $::_TARGET0 riscv dmi_write 0x39 0xF40c0184 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF40c0188 - $::_TARGET0 riscv dmi_write 0x3C 0xe4e1c00 + mww 0xF40c0180 0xb0000016 + mww 0xF40c0184 0 + mww 0xF40c0188 0xe4e1c00 #ddr setup - $::_TARGET0 riscv dmi_write 0x39 0xF3010000 - $::_TARGET0 riscv dmi_write 0x3C 0x3040000 + mww 0xF3010000 0x3040000 - $::_TARGET0 riscv dmi_write 0x39 0xF30101B0 - $::_TARGET0 riscv dmi_write 0x3C 0 + mww 0xF30101B0 0 - $::_TARGET0 riscv dmi_write 0x39 0xF4150044 - $::_TARGET0 riscv dmi_write 0x3C 0x40a + mww 0xF4150044 0x40a - $::_TARGET0 riscv dmi_write 0x39 0xF4150040 - $::_TARGET0 riscv dmi_write 0x3C 0xf004641f + mww 0xF4150040 0xf004641f - $::_TARGET0 riscv dmi_write 0x39 0xF4153000 - $::_TARGET0 riscv dmi_write 0x3C 0xf0000011 + mww 0xF4153000 0xf0000011 - $::_TARGET0 riscv dmi_write 0x39 0xF3013000 - $::_TARGET0 riscv dmi_write 0x3C 0xf4000000 + mww 0xF3013000 0xf4000000 - $::_TARGET0 riscv dmi_write 0x39 0xF3010490 - $::_TARGET0 riscv dmi_write 0x3C 1 + mww 0xF3010490 1 - $::_TARGET0 riscv dmi_write 0x39 0xF3010000 - $::_TARGET0 riscv dmi_write 0x3C 0x1040000 - $::_TARGET0 riscv dmi_write 0x39 0xF3010190 - $::_TARGET0 riscv dmi_write 0x3C 0x07010101 - $::_TARGET0 riscv dmi_write 0x39 0xF3010194 - $::_TARGET0 riscv dmi_write 0x3C 0x20404 - $::_TARGET0 riscv dmi_write 0x39 0xF30101A4 - $::_TARGET0 riscv dmi_write 0x3C 0x20008 - $::_TARGET0 riscv dmi_write 0x39 0xF3010240 - $::_TARGET0 riscv dmi_write 0x3C 0x6000600 - $::_TARGET0 riscv dmi_write 0x39 0xF3010200 - $::_TARGET0 riscv dmi_write 0x3C 0x1f1f1f - $::_TARGET0 riscv dmi_write 0x39 0xF3010204 - $::_TARGET0 riscv dmi_write 0x3C 0x70707 - $::_TARGET0 riscv dmi_write 0x39 0xF3010208 - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF301020c - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF3010210 - $::_TARGET0 riscv dmi_write 0x3C 0x1f1f - $::_TARGET0 riscv dmi_write 0x39 0xF3010214 - $::_TARGET0 riscv dmi_write 0x3C 0x6060606 - $::_TARGET0 riscv dmi_write 0x39 0xF3010218 - $::_TARGET0 riscv dmi_write 0x3C 0xf0f0606 + mww 0xF3010000 0x1040000 + mww 0xF3010190 0x07010101 + mww 0xF3010194 0x20404 + mww 0xF30101A4 0x20008 + mww 0xF3010240 0x6000600 + mww 0xF3010200 0x1f1f1f + mww 0xF3010204 0x70707 + mww 0xF3010208 0 + mww 0xF301020c 0 + mww 0xF3010210 0x1f1f + mww 0xF3010214 0x6060606 + mww 0xF3010218 0xf0f0606 - $::_TARGET0 riscv dmi_write 0x39 0xF3013000 - $::_TARGET0 riscv dmi_write 0x3C 0xfc000000 - $::_TARGET0 riscv dmi_write 0x39 0xF4150020 - $::_TARGET0 riscv dmi_write 0x3C 0x3000100 - $::_TARGET0 riscv dmi_write 0x39 0xF4150028 - $::_TARGET0 riscv dmi_write 0x3C 0x18002356 - $::_TARGET0 riscv dmi_write 0x39 0xF415002c - $::_TARGET0 riscv dmi_write 0x3C 0x0aac4156 - $::_TARGET0 riscv dmi_write 0x39 0xF4150054 - $::_TARGET0 riscv dmi_write 0x3C 0xe73 - $::_TARGET0 riscv dmi_write 0x39 0xF4150058 - $::_TARGET0 riscv dmi_write 0x3C 0x5 - $::_TARGET0 riscv dmi_write 0x39 0xF415005c - $::_TARGET0 riscv dmi_write 0x3C 0 - $::_TARGET0 riscv dmi_write 0x39 0xF4150048 - $::_TARGET0 riscv dmi_write 0x3C 0xf2adfe53 - $::_TARGET0 riscv dmi_write 0x39 0xF415004c - $::_TARGET0 riscv dmi_write 0x3C 0x22820362 - $::_TARGET0 riscv dmi_write 0x39 0xF4150050 - $::_TARGET0 riscv dmi_write 0x3C 0x30020100 - $::_TARGET0 riscv dmi_write 0x39 0xF415008c - $::_TARGET0 riscv dmi_write 0x3C 0xf06d50 + mww 0xF3013000 0xfc000000 + mww 0xF4150020 0x3000100 + mww 0xF4150028 0x18002356 + mww 0xF415002c 0x0aac4156 + mww 0xF4150054 0xe73 + mww 0xF4150058 0x5 + mww 0xF415005c 0 + mww 0xF4150048 0xf2adfe53 + mww 0xF415004c 0x22820362 + mww 0xF4150050 0x30020100 + mww 0xF415008c 0xf06d50 - $::_TARGET0 riscv dmi_write 0x39 0xF30101b0 - $::_TARGET0 riscv dmi_write 0x3C 1 + mww 0xF30101b0 1 sleep 100 - $::_TARGET0 riscv dmi_write 0x39 0xF4150068 - $::_TARGET0 riscv dmi_write 0x3C 0x91003587 - $::_TARGET0 riscv dmi_write 0x39 0xF4150004 - $::_TARGET0 riscv dmi_write 0x3C 0xF501 + mww 0xF4150068 0x91003587 + mww 0xF4150004 0xF501 sleep 200 echo "ddr has been enabled!" } -$_TARGET0 configure -event reset-end { - # init_clock - # init_ddr3 -} - $_TARGET0 configure -event reset-init { - init_clock - # init_ddr3 + init_clock + init_ddr3 } $_TARGET0 configure -event gdb-attach { diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg index f1785609ba..7c02320e75 100644 --- a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm6880.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2023 HPMicro +# Copyright (c) 2023,2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6880 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6880 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -11,3 +15,10 @@ target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 targets $_TARGET0 + +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + +proc reset_soc {} { + sba_write_mem 0xF410001C 24000000 +} diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld deleted file mode 100644 index 07a7c2e8a4..0000000000 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 64K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 448K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01270000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - /* WHD kernel and HAL layer */ - KEEP(*whd_*.o (.text .text* .rodata .rodata*)) - KEEP(*cyhal_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld index 5757100f7d..86b15d2b2f 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld @@ -31,6 +31,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -178,7 +187,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -188,6 +197,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -279,7 +297,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -306,7 +324,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index aa69823989..0000000000 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 384K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01260000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - __sdram_end__ = .; - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld deleted file mode 100644 index 7879f8390d..0000000000 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 8M; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32M; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld index 84a5a55901..258c5f764c 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld @@ -116,6 +116,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -274,7 +283,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld deleted file mode 100644 index f990ab84ed..0000000000 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32M; - -MEMORY -{ - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > AXI_SRAM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - *(FalPartTable) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - } > AXI_SRAM - - .rel : { - KEEP(*(.rel*)) - } > AXI_SRAM - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE (__rt_rvstack = .); - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - - } > SDRAM -} diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.c b/bsp/hpmicro/hpm6800evk/board/pinmux.c index 84314edd47..9cd4276d9c 100644 --- a/bsp/hpmicro/hpm6800evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.c @@ -56,7 +56,7 @@ void init_cap_pins(void) HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C3) { /* Audio */ HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_I2C3_SDA @@ -80,8 +80,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PF09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - ; + return status_invalid_argument; } + return status_success; } void init_cam_pins(void) diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.h b/bsp/hpmicro/hpm6800evk/board/pinmux.h index a95cd360a8..413faf4ce2 100644 --- a/bsp/hpmicro/hpm6800evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.h @@ -14,7 +14,7 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); void init_cap_pins(void); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); diff --git a/bsp/hpmicro/hpm6800evk/board/rtt_board.c b/bsp/hpmicro/hpm6800evk/board/rtt_board.c index 338e4ad77f..fae419d22d 100644 --- a/bsp/hpmicro/hpm6800evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6800evk/board/rtt_board.c @@ -41,14 +41,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); diff --git a/bsp/hpmicro/hpm6800evk/makefile.targets b/bsp/hpmicro/hpm6800evk/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.h b/bsp/hpmicro/hpm6800evk/rtconfig.h index 9e40580fb6..24397a8cb9 100644 --- a/bsp/hpmicro/hpm6800evk/rtconfig.h +++ b/bsp/hpmicro/hpm6800evk/rtconfig.h @@ -7,6 +7,17 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -108,7 +119,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -294,6 +305,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -321,12 +336,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -406,11 +433,11 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6800_SERIES +#define SOC_SERIES_HPM6000 /* Hardware Drivers Config */ -#define SOC_HPM6800 +#define SOC_HPM6000 /* On-chip Peripheral Drivers */ @@ -426,6 +453,33 @@ #define BSP_UART3_TX_BUFSIZE 0 #define BSP_UART3_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ + +/* AMPAK Wi-Fi module Configuration */ + +/* end of AMPAK Wi-Fi module Configuration */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.py b/bsp/hpmicro/hpm6800evk/rtconfig.py index 31a6e62e5e..c5744e06c8 100644 --- a/bsp/hpmicro/hpm6800evk/rtconfig.py +++ b/bsp/hpmicro/hpm6800evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c index c0a88c3209..5afe1cece4 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c @@ -56,6 +56,8 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -98,6 +100,18 @@ __attribute__((weak)) void c_startup(void) for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S index c200076924..90e9037e7a 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S @@ -77,6 +77,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -87,5 +88,14 @@ default_irq_handler: .set default_isr_\irq, default_irq_handler .long default_isr_\irq .endm - #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S index 319bd00b27..fe9766842f 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/vectors.S @@ -29,7 +29,7 @@ __vector_table: IRQ_HANDLER 16 /* CAN6 IRQ handler */ IRQ_HANDLER 17 /* CAN7 IRQ handler */ IRQ_HANDLER 18 /* PTPC IRQ handler */ - IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 19 /* Reserved */ IRQ_HANDLER 20 /* Reserved */ IRQ_HANDLER 21 /* Reserved */ IRQ_HANDLER 22 /* Reserved */ diff --git a/bsp/hpmicro/hpm6800evk/startup/SConscript b/bsp/hpmicro/hpm6800evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm6800evk/startup/SConscript +++ b/bsp/hpmicro/hpm6800evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/.config b/bsp/hpmicro/hpm6e00evk/.config index dacf916f90..589ae1a20e 100644 --- a/bsp/hpmicro/hpm6e00evk/.config +++ b/bsp/hpmicro/hpm6e00evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -178,7 +188,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -237,11 +247,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -262,10 +272,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -458,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -573,6 +584,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -632,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -780,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -813,7 +829,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -892,12 +922,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -905,6 +942,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -984,6 +1038,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1038,6 +1093,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1088,6 +1144,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1105,6 +1162,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1162,6 +1222,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1187,6 +1249,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1426,7 +1489,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6E00_SERIES=y +CONFIG_SOC_SERIES_HPM6E00=y # # Hardware Drivers Config @@ -1460,6 +1523,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set # CONFIG_BSP_USING_UART15 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_TSW is not set @@ -1475,5 +1539,70 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_PWMV2 is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_FFA is not set +# CONFIG_BSP_USING_TAMP is not set +CONFIG_BSP_USING_FEMC=y +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_PPI is not set +# CONFIG_BSP_USING_LOBS is not set +# CONFIG_BSP_USING_PDMLITE is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEOV2 is not set +# CONFIG_BSP_USING_RDC is not set +# CONFIG_BSP_USING_SDM is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_SEI is not set +# CONFIG_BSP_USING_MTG is not set +# CONFIG_BSP_USING_VSC is not set +# CONFIG_BSP_USING_CLC is not set +# CONFIG_BSP_USING_ESC is not set +# CONFIG_BSP_USING_MCHTMR is not set +CONFIG_INIT_EXT_RAM_FOR_DATA=y +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6e00evk/.cproject b/bsp/hpmicro/hpm6e00evk/.cproject index eafefd8ef5..ef87c72be5 100644 --- a/bsp/hpmicro/hpm6e00evk/.cproject +++ b/bsp/hpmicro/hpm6e00evk/.cproject @@ -20,7 +20,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.debug" valueType="enumerated" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean" /> @@ -90,7 +90,7 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6E80}"" /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -std=gnu11" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -std=gnu11" valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> @@ -111,7 +111,7 @@ <listOptionValue builtIn="false" value="m " /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> @@ -135,7 +135,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> <additionalInput kind="additionalinput" paths="$(LIBS)" /> @@ -190,7 +190,7 @@ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input" /> </tool> </toolChain> diff --git a/bsp/hpmicro/hpm6e00evk/README.md b/bsp/hpmicro/hpm6e00evk/README.md index a00e74ec0b..c12fd8d17d 100644 --- a/bsp/hpmicro/hpm6e00evk/README.md +++ b/bsp/hpmicro/hpm6e00evk/README.md @@ -74,7 +74,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6e80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -82,7 +82,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6e80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6e00evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6e00evk/README_zh.md b/bsp/hpmicro/hpm6e00evk/README_zh.md index 0af8550fe0..68bca79d6b 100644 --- a/bsp/hpmicro/hpm6e00evk/README_zh.md +++ b/bsp/hpmicro/hpm6e00evk/README_zh.md @@ -74,14 +74,14 @@ HPM6E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，� - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6e80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6e80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6e00evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6e00evk/SConscript b/bsp/hpmicro/hpm6e00evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6e00evk/SConscript +++ b/bsp/hpmicro/hpm6e00evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6e00evk/SConstruct b/bsp/hpmicro/hpm6e00evk/SConstruct index 11f8073bd4..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6e00evk/SConstruct +++ b/bsp/hpmicro/hpm6e00evk/SConstruct @@ -15,6 +15,26 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + if GetOption('clean'): + return + + need_update = True + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', @@ -47,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -60,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6e00evk/applications/SConscript b/bsp/hpmicro/hpm6e00evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6e00evk/applications/SConscript +++ b/bsp/hpmicro/hpm6e00evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6e00evk/applications/main.c b/bsp/hpmicro/hpm6e00evk/applications/main.c index a5a7f07c73..8aff6b8126 100644 --- a/bsp/hpmicro/hpm6e00evk/applications/main.c +++ b/bsp/hpmicro/hpm6e00evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6e00evk/board/Kconfig b/bsp/hpmicro/hpm6e00evk/board/Kconfig index b41d283c6a..7f0bca8783 100644 --- a/bsp/hpmicro/hpm6e00evk/board/Kconfig +++ b/bsp/hpmicro/hpm6e00evk/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_HPM6E00 bool - select SOC_HPM6E00_SERIES + select SOC_SERIES_HPM6E00 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -91,6 +91,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -118,6 +123,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -145,6 +155,11 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" @@ -172,6 +187,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -199,6 +219,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -226,6 +251,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -253,6 +283,11 @@ menu "On-chip Peripheral Drivers" int "UART7 Interrupt Priority" range 1 7 default 1 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART8 bool "Enable UART8" @@ -280,6 +315,11 @@ menu "On-chip Peripheral Drivers" int "UART8 Interrupt Priority" range 1 7 default 1 + config BSP_UART8_DMA_PINGPONG_BUFSIZE + int "Set UART8 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART8_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART9 bool "Enable UART9" @@ -307,6 +347,11 @@ menu "On-chip Peripheral Drivers" int "UART9 Interrupt Priority" range 1 7 default 1 + config BSP_UART9_DMA_PINGPONG_BUFSIZE + int "Set UART9 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART9_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART10 bool "Enable UART10" @@ -334,6 +379,11 @@ menu "On-chip Peripheral Drivers" int "UART10 Interrupt Priority" range 1 7 default 1 + config BSP_UART10_DMA_PINGPONG_BUFSIZE + int "Set UART10 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART10_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART11 bool "Enable UART11" @@ -361,6 +411,11 @@ menu "On-chip Peripheral Drivers" int "UART11 Interrupt Priority" range 1 7 default 1 + config BSP_UART11_DMA_PINGPONG_BUFSIZE + int "Set UART11 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART11_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART12 bool "Enable UART12" @@ -388,6 +443,11 @@ menu "On-chip Peripheral Drivers" int "UART12 Interrupt Priority" range 1 7 default 1 + config BSP_UART12_DMA_PINGPONG_BUFSIZE + int "Set UART12 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART12_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART13 bool "Enable UART13" @@ -415,6 +475,11 @@ menu "On-chip Peripheral Drivers" int "UART13 Interrupt Priority" range 1 7 default 1 + config BSP_UART13_DMA_PINGPONG_BUFSIZE + int "Set UART13 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART13_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART14 bool "Enable UART14" @@ -442,6 +507,11 @@ menu "On-chip Peripheral Drivers" int "UART14 Interrupt Priority" range 1 7 default 1 + config BSP_UART14_DMA_PINGPONG_BUFSIZE + int "Set UART14 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART14_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART15 bool "Enable UART15" @@ -469,10 +539,33 @@ menu "On-chip Peripheral Drivers" int "UART15 Interrupt Priority" range 1 7 default 1 + config BSP_UART15_DMA_PINGPONG_BUFSIZE + int "Set UART15 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART15_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -489,7 +582,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -497,7 +590,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -519,7 +612,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -527,7 +620,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -549,7 +642,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -557,7 +650,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -579,7 +672,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -587,7 +680,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -609,7 +702,7 @@ menu "On-chip Peripheral Drivers" int "SPI4 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI4_CS_SEL + choice prompt "Select SPI4 CS TYPE" default BSP_SPI4_USING_SOFT_CS config BSP_SPI4_USING_SOFT_CS @@ -617,7 +710,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI4_USING_HARD_CS bool "Enable SPI4 hardware cs" endchoice - choice BSP_SPI4_IO_MODE_SEL + choice prompt "Select SPI4 IO mode" default BSP_SPI4_USING_SINGLE_IO config BSP_SPI4_USING_SINGLE_IO @@ -639,7 +732,7 @@ menu "On-chip Peripheral Drivers" int "SPI5 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI5_CS_SEL + choice prompt "Select SPI5 CS TYPE" default BSP_SPI5_USING_SOFT_CS config BSP_SPI5_USING_SOFT_CS @@ -647,7 +740,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI5_USING_HARD_CS bool "Enable SPI5 hardware cs" endchoice - choice BSP_SPI5_IO_MODE_SEL + choice prompt "Select SPI5 IO mode" default BSP_SPI5_USING_SINGLE_IO config BSP_SPI5_USING_SINGLE_IO @@ -669,7 +762,7 @@ menu "On-chip Peripheral Drivers" int "SPI6 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI6_CS_SEL + choice prompt "Select SPI6 CS TYPE" default BSP_SPI6_USING_SOFT_CS config BSP_SPI6_USING_SOFT_CS @@ -677,7 +770,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI6_USING_HARD_CS bool "Enable SPI6 hardware cs" endchoice - choice BSP_SPI6_IO_MODE_SEL + choice prompt "Select SPI6 IO mode" default BSP_SPI6_USING_SINGLE_IO config BSP_SPI6_USING_SINGLE_IO @@ -699,7 +792,7 @@ menu "On-chip Peripheral Drivers" int "SPI7 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI7_CS_SEL + choice prompt "Select SPI7 CS TYPE" default BSP_SPI7_USING_SOFT_CS config BSP_SPI7_USING_SOFT_CS @@ -707,7 +800,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI7_USING_HARD_CS bool "Enable SPI7 hardware cs" endchoice - choice BSP_SPI7_IO_MODE_SEL + choice prompt "Select SPI7 IO mode" default BSP_SPI7_USING_SINGLE_IO config BSP_SPI7_USING_SINGLE_IO @@ -740,7 +833,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PHY if BSP_USING_ETH if BSP_USING_ETH - choice BSP_ETH0_SEL + choice prompt "ETH" default BSP_USING_ETH0 @@ -828,6 +921,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -933,7 +1035,6 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -976,7 +1077,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_EWDG bool "Enable EWDG" default n @@ -993,7 +1093,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWMV2 bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWMV2 + select RT_USING_PWM menuconfig BSP_USING_MCAN bool "Enable MCAN" @@ -1077,7 +1177,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -1098,7 +1198,378 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_QEI + bool "Enable QEI (Quadrature Encoder Interface)" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_FFA + bool "Enable FFA" + default n + + menuconfig BSP_USING_TAMP + bool "Enable TAMP (Tamper)" + default n + + menuconfig BSP_USING_FEMC + bool "Enable FEMC (Flexible External Memory Controller)" + default n + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_PPI + bool "Enable PPI (Parallel Port Interface)" + default n + + menuconfig BSP_USING_LOBS + bool "Enable LOBS" + default n + + menuconfig BSP_USING_PDMLITE + bool "Enable PDMLITE" + default n + + menuconfig BSP_USING_QEIV2 + bool "Enable QEIV2 (Quadrature Encoder Interface V2)" + default n + + menuconfig BSP_USING_QEOV2 + bool "Enable QEOV2 (Quadrature Encoder Output V2)" + default n + + menuconfig BSP_USING_RDC + bool "Enable RDC (Resolver to Digital Converter)" + default n + + menuconfig BSP_USING_SDM + bool "Enable SDM (Sigma-Delta Modulator)" + default n + + menuconfig BSP_USING_PLB + bool "Enable PLB" + default n + + menuconfig BSP_USING_SEI + bool "Enable SEI (Synchronous Encoder Interface)" + default n + + menuconfig BSP_USING_MTG + bool "Enable MTG (Motor Timing Generator)" + default n + + menuconfig BSP_USING_VSC + bool "Enable VSC" + default n + + menuconfig BSP_USING_CLC + bool "Enable CLC" + default n + + menuconfig BSP_USING_ESC + bool "Enable ESC (EtherCAT Slave Controller)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + select BSP_USING_FEMC if INIT_EXT_RAM_FOR_DATA + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + endmenu +menu "HPMicro Interrupt Config" endmenu +menu "HPMicro RT-Thread Interrupt Framework" +endmenu + +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu + +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif +endmenu + +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg index 3147f1b559..4814347e61 100644 --- a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg @@ -50,23 +50,10 @@ flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg index 3776573604..9bc5396879 100644 --- a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg @@ -1,9 +1,12 @@ -# Copyright (c) 2024 HPMicro +# Copyright (c) 2024-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause # - -set _CHIP hpm6e00 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6e00 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -14,35 +17,19 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -proc dmi_write {reg value} { - $::_TARGET0 riscv dmi_write ${reg} ${value} -} - -proc dmi_read {reg} { - set v [$::_TARGET0 riscv dmi_read ${reg}] - return ${v} -} -proc dmi_write_memory {addr value} { - dmi_write 0x39 ${addr} - dmi_write 0x3C ${value} -} - -proc dmi_read_memory {addr} { - set sbcs [expr { 0x100000 | [dmi_read 0x38] }] - dmi_write 0x38 ${sbcs} - dmi_write 0x39 ${addr} - set value [dmi_read 0x3C] - return ${value} -} +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] proc release_core1 {} { - dmi_write_memory 0xF4002C00 0x1000 + sba_write_mem 0xF4002C00 0x1000 } set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 +source [find soc/hpm_common_csr.cfg] + $_TARGET1 configure -event examine-start { release_core1 } @@ -53,11 +40,9 @@ $_TARGET1 configure -event reset-deassert-pre { } $_TARGET0 configure -event reset-end { - $::_TARGET0 riscv dmi_write 0x39 0xF4002010 - $::_TARGET0 riscv dmi_write 0x3C 0x2 + sba_write_mem 0xF4002010 0x2 } proc reset_soc {} { - $::_TARGET0 riscv dmi_write 0x39 0xF410001C - $::_TARGET0 riscv dmi_write 0x3C 24000000 + sba_write_mem 0xF410001C 24000000 } diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg index b80ad2027b..3e020331c7 100644 --- a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2024 HPMicro +# Copyright (c) 2024-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6e00 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6e00 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -12,7 +16,9 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + proc reset_soc {} { - $::_TARGET0 riscv dmi_write 0x39 0xF410001C - $::_TARGET0 riscv dmi_write 0x3C 24000000 + sba_write_mem 0xF410001C 24000000 } diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld index f2cbfced97..6f6b31b2bb 100644 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -28,6 +28,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -175,7 +184,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -185,6 +194,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -276,7 +294,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -303,7 +321,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index e1068d6059..0000000000 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*ip*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld index 8bcf794005..4a9b7523fe 100644 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -113,6 +113,16 @@ SECTIONS . = ALIGN(8); } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf deleted file mode 100644 index d098add1f1..0000000000 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region FLASH = [from 0x80003000 size 16M - 0x3000 ]; /* FLASH */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = 64K, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region FLASH; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; - - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __rt_rvstack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; - -initialize by copy { - section .text.rt_*, - section .text.trap*, - section .text.entry, - section .text.context_gcc, - }; -place in ILM { - section .text.rt_*, - section .text.trap*, - section .text.entry, - section .text.context_gcc, - }; - - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of FLASH with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in FLASH with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - block cherryusb_usbh_class_info, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; -place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf deleted file mode 100644 index e41aca2d4e..0000000000 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region FLASH = [from 0x80003000 size 16M - 0x3000 ]; /* FLASH */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = 32K, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region FLASH; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __rt_rvstack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; - -initialize by copy { - section .text.rt_*, - section .text.trap*, - section .text.entry, - section .text.context_gcc, - - section .text.tcpip_*, - section .text.tcp_*, - section .text.ethernet_*, - section .text.lwip_*, - section .text.eth_rx_thread_entry, - section .text.enet0_pbuf_free_custom, - section .text.enet1_pbuf_free_custom, - section .text.free_rx_dma_descriptor, - section .text.isr_enet, - section .text.eth_rx_callback, - section .text.eth_device_ready, - section .text._rt_*, - section .text.enet_*, - section .text.pbuf_*, - section .text.do_memp_malloc_pool, - section .text.do_memp_free_pool, - section .text.sys_*, - section .text.*tcp*, - section .text.*udp*, - section .text.raw*, - section .text.iperf*, - section .text.netconn*, - section .text.net*, - section .text.ip4*, - section .text.recv*, - section .text.sal*, - section .text.send*, - section .text.etharp*, - section .text.phy*, - section .text.ethernetif*, - section .text.mem*, - section .text.memp*, - section .text.event_callback, - }; -place in ILM { - section .text.rt_*, - section .text.trap*, - section .text.entry, - section .text.context_gcc, - - section .text.tcpip_*, - section .text.tcp_*, - section .text.ethernet_*, - section .text.lwip_*, - section .text.eth_rx_thread_entry, - section .text.enet0_pbuf_free_custom, - section .text.enet1_pbuf_free_custom, - section .text.free_rx_dma_descriptor, - section .text.isr_enet, - section .text.eth_rx_callback, - section .text.eth_device_ready, - section .text._rt_*, - section .text.enet_*, - section .text.pbuf_*, - section .text.do_memp_malloc_pool, - section .text.do_memp_free_pool, - section .text.sys_*, - section .text.*tcp*, - section .text.*udp*, - section .text.raw*, - section .text.iperf*, - section .text.netconn*, - section .text.net*, - section .text.ip4*, - section .text.recv*, - section .text.sal*, - section .text.send*, - section .text.etharp*, - section .text.phy*, - section .text.ethernetif*, - section .text.mem*, - section .text.memp*, - section .text.event_callback, - }; - - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of FLASH with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in FLASH with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - block cherryusb_usbh_class_info, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; -place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf deleted file mode 100644 index bd71a9e7dd..0000000000 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 512k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = 128K, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __rt_rvstack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; - - -/* Placement */ -place at start of AXI_SRAM with fixed order { symbol _start, block vectors, block vectors_s }; -place in AXI_SRAM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - block cherryusb_usbh_class_info, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section -place in AXI_SRAM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; -place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.c b/bsp/hpmicro/hpm6e00evk/board/pinmux.c index 1de940b4a0..a88b53f6e9 100644 --- a/bsp/hpmicro/hpm6e00evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.c @@ -49,7 +49,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -70,8 +70,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PF12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PF13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - ; + return status_invalid_argument; } + return status_success; } void init_femc_pins(void) diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.h b/bsp/hpmicro/hpm6e00evk/board/pinmux.h index 01aa0f437f..4b7fbdcaea 100644 --- a/bsp/hpmicro/hpm6e00evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.h @@ -13,7 +13,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_femc_pins(void); void init_ppi_pins(void); void init_sdm_pins(void); diff --git a/bsp/hpmicro/hpm6e00evk/board/rtt_board.c b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c index 034b6ea751..a260758cb5 100644 --- a/bsp/hpmicro/hpm6e00evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c @@ -41,14 +41,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); @@ -132,7 +138,7 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } #endif -uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ { uint32_t freq = 0; @@ -148,7 +154,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste } clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == (void *)HPM_ADC1) { + } else if (ptr == HPM_ADC1) { if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); @@ -159,7 +165,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste } clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == (void *)HPM_ADC2) { + } else if (ptr == HPM_ADC2) { if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); @@ -170,7 +176,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste } clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); - } else if (ptr == (void *)HPM_ADC3) { + } else if (ptr == HPM_ADC3) { if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); diff --git a/bsp/hpmicro/hpm6e00evk/makefile.targets b/bsp/hpmicro/hpm6e00evk/makefile.targets new file mode 100644 index 0000000000..4583a13f1c --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard board/linker_scripts/gcc/*.ld) diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.h b/bsp/hpmicro/hpm6e00evk/rtconfig.h index 47db2c1614..4a699f214e 100644 --- a/bsp/hpmicro/hpm6e00evk/rtconfig.h +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -104,7 +114,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -290,6 +300,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -317,12 +331,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -402,7 +428,7 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6E00_SERIES +#define SOC_SERIES_HPM6E00 /* Hardware Drivers Config */ @@ -417,7 +443,32 @@ #define BSP_UART0_RX_BUFSIZE 128 #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 +#define BSP_USING_FEMC +#define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.py b/bsp/hpmicro/hpm6e00evk/rtconfig.py index 81110453e9..72dd531804 100644 --- a/bsp/hpmicro/hpm6e00evk/rtconfig.py +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,30 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options @@ -83,9 +59,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -105,7 +85,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -113,8 +93,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -123,8 +103,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h index b7ae18b326..e4431f23a5 100644 --- a/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h +++ b/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h @@ -6,7 +6,6 @@ /* RT-Thread pre-include file */ #define D45 -#define HPM6880 #define HPM6E80 #define HPMSOC_HAS_HPMSDK_DMAV2 #define RT_USING_LIBC diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c index e3f85a9e0e..78705526d8 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c @@ -54,6 +54,8 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ __attribute__((weak)) void c_startup(void) for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S index c200076924..0262684ad3 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S @@ -77,6 +77,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -89,3 +90,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6e00evk/startup/SConscript b/bsp/hpmicro/hpm6e00evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/SConscript +++ b/bsp/hpmicro/hpm6e00evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/.config b/bsp/hpmicro/hpm6p00evk/.config index 1f8257f0f7..b3905d1c2f 100644 --- a/bsp/hpmicro/hpm6p00evk/.config +++ b/bsp/hpmicro/hpm6p00evk/.config @@ -11,8 +11,18 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set -# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_vsnprintf options # @@ -182,7 +192,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50301 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -241,11 +251,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -266,10 +276,10 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -462,6 +472,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -577,6 +588,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # @@ -636,6 +648,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -784,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set # end of STM32 HAL & SDK Drivers # @@ -817,7 +833,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -896,12 +926,19 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HPM_SDK=y CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" -CONFIG_PKG_USING_HPM_SDK_V110=y +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_V113=y # CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION is not set -CONFIG_PKG_HPM_SDK_VER="v1.10.0" +CONFIG_PKG_HPM_SDK_VER="v1.13.0" # end of HPMicro SDK # +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# # FT32 HAL & SDK Drivers # # CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set @@ -909,6 +946,23 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -988,6 +1042,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1042,6 +1097,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1092,6 +1148,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1109,6 +1166,9 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1166,6 +1226,8 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1191,6 +1253,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1430,7 +1493,7 @@ CONFIG_PKG_HPM_SDK_VER="v1.10.0" # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_HPM6P00_SERIES=y +CONFIG_SOC_SERIES_HPM6P00=y # # Hardware Drivers Config @@ -1456,6 +1519,7 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_PUART is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_GPTMR is not set @@ -1469,5 +1533,64 @@ CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_PWMV2 is not set # CONFIG_BSP_USING_MCAN is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_TSNS is not set +# CONFIG_BSP_USING_ACMP is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_QEIV2 is not set +# CONFIG_BSP_USING_QEOV2 is not set +# CONFIG_BSP_USING_RDC is not set +# CONFIG_BSP_USING_SEI is not set +# CONFIG_BSP_USING_MTGV2 is not set +# CONFIG_BSP_USING_VSC is not set +# CONFIG_BSP_USING_CLC is not set +# CONFIG_BSP_USING_SDM is not set +# CONFIG_BSP_USING_PLB is not set +# CONFIG_BSP_USING_PPI is not set +# CONFIG_BSP_USING_LOBS is not set +# CONFIG_BSP_USING_PTPC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_SDP is not set +# CONFIG_BSP_USING_MCHTMR is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SOFT_SPI is not set # end of On-chip Peripheral Drivers + +# +# HPMicro Interrupt Config +# + +# +# HPMicro RT-Thread Interrupt Framework +# + +# +# HPMicro Use Generic Startup Implementation +# +# end of HPMicro Use Generic Startup Implementation + +# +# HPMicro RT-Thread backtrace configuration (experimental) +# +# CONFIG_HPM_ENABLE_RTTHREAD_BACKTRACE_PORT is not set +# CONFIG_HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER is not set +# end of HPMicro RT-Thread backtrace configuration (experimental) # end of Hardware Drivers Config + +# +# Third-Party Add-ons +# + +# +# Segger SystemView Config +# +# CONFIG_BSP_USING_SYSTEMVIEW is not set +# end of Segger SystemView Config + +# +# RT-Thread Insight Config +# +# CONFIG_BSP_USING_RTI is not set +# end of RT-Thread Insight Config +# end of Third-Party Add-ons diff --git a/bsp/hpmicro/hpm6p00evk/.cproject b/bsp/hpmicro/hpm6p00evk/.cproject index eafefd8ef5..a38d669790 100644 --- a/bsp/hpmicro/hpm6p00evk/.cproject +++ b/bsp/hpmicro/hpm6p00evk/.cproject @@ -20,7 +20,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.debug" valueType="enumerated" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean" /> @@ -70,9 +70,9 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/ip}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> @@ -87,10 +87,10 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6E80}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6P81}"" /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -std=gnu11" valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -std=gnu11" valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> @@ -111,7 +111,7 @@ <listOptionValue builtIn="false" value="m " /> </option> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> @@ -135,7 +135,7 @@ <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean" /> <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false" /> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections -O0 " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcmodel=medlow --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections -Og " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input"> <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" /> <additionalInput kind="additionalinput" paths="$(LIBS)" /> @@ -168,9 +168,9 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/inc}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81/boot}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/ip}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/filesystems/devfs}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/dfs/dfs_v1/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" /> @@ -185,18 +185,18 @@ <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" /> <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/risc-v/common}"" /> - <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6E80}"" /> + <listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//startup/HPM6P81}"" /> </option> <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles"> <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" /> </option> - <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -O0 -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> + <option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value=" -mcmodel=medlow -DUSE_NONVECTOR_MODE=1 -ffunction-sections -fdata-sections -fno-common -gdwarf-2 -Og -DFLASH_XIP=1 -Woverloaded-virtual -fno-exceptions -fno-rtti " valueType="string" /> <inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input" /> </tool> </toolChain> </folderInfo> <sourceEntries> - <entry excluding="//dist/project|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon|//rt-thread/bsp/Vango|//rt-thread/bsp/acm32|//rt-thread/bsp/airm2m|//rt-thread/bsp/allwinner|//rt-thread/bsp/allwinner_tina|//rt-thread/bsp/amebaz|//rt-thread/bsp/apm32|//rt-thread/bsp/apollo2|//rt-thread/bsp/asm9260t|//rt-thread/bsp/at32|//rt-thread/bsp/at91|//rt-thread/bsp/avr32|//rt-thread/bsp/beaglebone|//rt-thread/bsp/bf533|//rt-thread/bsp/bluetrum|//rt-thread/bsp/bm3803|//rt-thread/bsp/bouffalo_lab|//rt-thread/bsp/ck802|//rt-thread/bsp/core-v-mcu|//rt-thread/bsp/cvitek|//rt-thread/bsp/dm365|//rt-thread/bsp/efm32|//rt-thread/bsp/essemi|//rt-thread/bsp/fm33lc026|//rt-thread/bsp/frdm-k64f|//rt-thread/bsp/ft2004|//rt-thread/bsp/ft32|//rt-thread/bsp/fujitsu|//rt-thread/bsp/gd32|//rt-thread/bsp/hc32|//rt-thread/bsp/hc32l136|//rt-thread/bsp/hc32l196|//rt-thread/bsp/hifive1|//rt-thread/bsp/hk32|//rt-thread/bsp/hpmicro/hpm5300evk|//rt-thread/bsp/hpmicro/hpm5301evklite|//rt-thread/bsp/hpmicro/hpm6200evk|//rt-thread/bsp/hpmicro/hpm6300evk|//rt-thread/bsp/hpmicro/hpm6750evk|//rt-thread/bsp/hpmicro/hpm6750evk2|//rt-thread/bsp/hpmicro/hpm6750evkmini|//rt-thread/bsp/hpmicro/hpm6800evk|//rt-thread/bsp/hpmicro/libraries/drivers/drv_adc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_can.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_dao.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet_phy.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_ewdt.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_hwtimer.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2c.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2s.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_lcd.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_mcan.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pdm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pwm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_rtc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_sdio.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_spi.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_uart_v2.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_usb.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_wdt.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/camera|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/codec|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/panel|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ppi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/sccb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/smbus|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/spi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/utils|//rt-thread/bsp/ht32|//rt-thread/bsp/juicevm|//rt-thread/bsp/k210|//rt-thread/bsp/k230|//rt-thread/bsp/lm3s8962|//rt-thread/bsp/lm3s9b9x|//rt-thread/bsp/lm4f232|//rt-thread/bsp/loongson|//rt-thread/bsp/m16c62p|//rt-thread/bsp/maxim|//rt-thread/bsp/microblaze|//rt-thread/bsp/microchip|//rt-thread/bsp/mini2440|//rt-thread/bsp/mini4020|//rt-thread/bsp/mipssim|//rt-thread/bsp/mm32|//rt-thread/bsp/mm32f103x|//rt-thread/bsp/mm32f327x|//rt-thread/bsp/mm32f526x|//rt-thread/bsp/mm32l07x|//rt-thread/bsp/mm32l3xx|//rt-thread/bsp/msp432e401y-LaunchPad|//rt-thread/bsp/n32|//rt-thread/bsp/n32g452xx|//rt-thread/bsp/nios_ii|//rt-thread/bsp/nrf5x|//rt-thread/bsp/nuclei|//rt-thread/bsp/nuvoton|//rt-thread/bsp/nv32f100x|//rt-thread/bsp/nxp|//rt-thread/bsp/phytium|//rt-thread/bsp/pic32ethernet|//rt-thread/bsp/qemu-vexpress-a9|//rt-thread/bsp/qemu-virt64-aarch64|//rt-thread/bsp/qemu-virt64-riscv|//rt-thread/bsp/raspberry-pi|//rt-thread/bsp/raspberry-pico|//rt-thread/bsp/renesas|//rt-thread/bsp/rm48x50|//rt-thread/bsp/rockchip|//rt-thread/bsp/rv32m1_vega|//rt-thread/bsp/rx|//rt-thread/bsp/sam7x|//rt-thread/bsp/samd21|//rt-thread/bsp/sep6200|//rt-thread/bsp/simulator|//rt-thread/bsp/smartfusion2|//rt-thread/bsp/sparkfun-redv|//rt-thread/bsp/stm32|//rt-thread/bsp/synopsys|//rt-thread/bsp/synwit|//rt-thread/bsp/tae32f5300|//rt-thread/bsp/taihu|//rt-thread/bsp/thead-smart|//rt-thread/bsp/ti|//rt-thread/bsp/tkm32F499|//rt-thread/bsp/tm4c123bsp|//rt-thread/bsp/tm4c129x|//rt-thread/bsp/tms320c6678|//rt-thread/bsp/upd70f3454|//rt-thread/bsp/w60x|//rt-thread/bsp/wch|//rt-thread/bsp/wh44b0|//rt-thread/bsp/x86|//rt-thread/bsp/xplorer4330|//rt-thread/bsp/yichip|//rt-thread/bsp/zynqmp-a53-dfzu2eg|//rt-thread/bsp/zynqmp-r5-axu4ev|//rt-thread/components/dfs/dfs_v1/filesystems/cromfs|//rt-thread/components/dfs/dfs_v1/filesystems/elmfat|//rt-thread/components/dfs/dfs_v1/filesystems/iso9660|//rt-thread/components/dfs/dfs_v1/filesystems/mqueue|//rt-thread/components/dfs/dfs_v1/filesystems/nfs|//rt-thread/components/dfs/dfs_v1/filesystems/ramfs|//rt-thread/components/dfs/dfs_v1/filesystems/romfs|//rt-thread/components/dfs/dfs_v1/filesystems/skeleton|//rt-thread/components/dfs/dfs_v1/filesystems/tmpfs|//rt-thread/components/dfs/dfs_v2|//rt-thread/components/drivers/ata|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/block|//rt-thread/components/drivers/can|//rt-thread/components/drivers/clk|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/mnt.c|//rt-thread/components/drivers/core/numa.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/core/power_domain.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/dma|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/iio|//rt-thread/components/drivers/ipc/completion_mp.c|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/led|//rt-thread/components/drivers/mailbox|//rt-thread/components/drivers/mfd|//rt-thread/components/drivers/misc|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/nvme|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/pci|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/phye|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pin/dev_pin_dm.c|//rt-thread/components/drivers/pin/dev_pin_ofw.c|//rt-thread/components/drivers/pinctrl|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/regulator|//rt-thread/components/drivers/reset|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/scsi|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/bypass.c|//rt-thread/components/drivers/serial/dev_serial_v2.c|//rt-thread/components/drivers/serial/serial_dm.c|//rt-thread/components/drivers/serial/serial_tty.c|//rt-thread/components/drivers/smp_call|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/thermal|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/mprotect|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/documentation|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v/common/atomic_riscv.c|//rt-thread/libcpu/risc-v/common64|//rt-thread/libcpu/risc-v/rv64|//rt-thread/libcpu/risc-v/t-head|//rt-thread/libcpu/risc-v/virt64|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu_mp.c|//rt-thread/src/klibc/rt_vsnprintf_std.c|//rt-thread/src/klibc/utest|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//startup/HPM6E80/toolchains/gcc/vectors.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" /> + <entry excluding="//dist/project|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon|//rt-thread/bsp/Vango|//rt-thread/bsp/acm32|//rt-thread/bsp/airm2m|//rt-thread/bsp/allwinner|//rt-thread/bsp/allwinner_tina|//rt-thread/bsp/amebaz|//rt-thread/bsp/apm32|//rt-thread/bsp/apollo2|//rt-thread/bsp/asm9260t|//rt-thread/bsp/at32|//rt-thread/bsp/at91|//rt-thread/bsp/avr32|//rt-thread/bsp/beaglebone|//rt-thread/bsp/bf533|//rt-thread/bsp/bluetrum|//rt-thread/bsp/bm3803|//rt-thread/bsp/bouffalo_lab|//rt-thread/bsp/ck802|//rt-thread/bsp/core-v-mcu|//rt-thread/bsp/cvitek|//rt-thread/bsp/dm365|//rt-thread/bsp/efm32|//rt-thread/bsp/essemi|//rt-thread/bsp/fm33lc026|//rt-thread/bsp/frdm-k64f|//rt-thread/bsp/ft2004|//rt-thread/bsp/ft32|//rt-thread/bsp/fujitsu|//rt-thread/bsp/gd32|//rt-thread/bsp/hc32|//rt-thread/bsp/hc32l136|//rt-thread/bsp/hc32l196|//rt-thread/bsp/hifive1|//rt-thread/bsp/hk32|//rt-thread/bsp/hpmicro/hpm5300evk|//rt-thread/bsp/hpmicro/hpm5301evklite|//rt-thread/bsp/hpmicro/hpm6200evk|//rt-thread/bsp/hpmicro/hpm6300evk|//rt-thread/bsp/hpmicro/hpm6750evk|//rt-thread/bsp/hpmicro/hpm6750evk2|//rt-thread/bsp/hpmicro/hpm6750evkmini|//rt-thread/bsp/hpmicro/hpm6800evk|//rt-thread/bsp/hpmicro/libraries/drivers/drv_adc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_can.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_dao.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_enet_phy.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_ewdt.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_hwtimer.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2c.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_i2s.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_lcd.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_mcan.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pdm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_pwm.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_rtc.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_sdio.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_spi.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_uart_v2.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_usb.c|//rt-thread/bsp/hpmicro/libraries/drivers/drv_wdt.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/camera|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/codec|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/panel|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/ppi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/sccb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/smbus|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/spi|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/touch|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/components/usb|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81/hpm_trgm_soc_drv.c|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6P00/HPM6P81/toolchains|//rt-thread/bsp/hpmicro/libraries/hpm_sdk/utils|//rt-thread/bsp/ht32|//rt-thread/bsp/juicevm|//rt-thread/bsp/k210|//rt-thread/bsp/k230|//rt-thread/bsp/lm3s8962|//rt-thread/bsp/lm3s9b9x|//rt-thread/bsp/lm4f232|//rt-thread/bsp/loongson|//rt-thread/bsp/m16c62p|//rt-thread/bsp/maxim|//rt-thread/bsp/microblaze|//rt-thread/bsp/microchip|//rt-thread/bsp/mini2440|//rt-thread/bsp/mini4020|//rt-thread/bsp/mipssim|//rt-thread/bsp/mm32|//rt-thread/bsp/mm32f103x|//rt-thread/bsp/mm32f327x|//rt-thread/bsp/mm32f526x|//rt-thread/bsp/mm32l07x|//rt-thread/bsp/mm32l3xx|//rt-thread/bsp/msp432e401y-LaunchPad|//rt-thread/bsp/n32|//rt-thread/bsp/n32g452xx|//rt-thread/bsp/nios_ii|//rt-thread/bsp/nrf5x|//rt-thread/bsp/nuclei|//rt-thread/bsp/nuvoton|//rt-thread/bsp/nv32f100x|//rt-thread/bsp/nxp|//rt-thread/bsp/phytium|//rt-thread/bsp/pic32ethernet|//rt-thread/bsp/qemu-vexpress-a9|//rt-thread/bsp/qemu-virt64-aarch64|//rt-thread/bsp/qemu-virt64-riscv|//rt-thread/bsp/raspberry-pi|//rt-thread/bsp/raspberry-pico|//rt-thread/bsp/renesas|//rt-thread/bsp/rm48x50|//rt-thread/bsp/rockchip|//rt-thread/bsp/rv32m1_vega|//rt-thread/bsp/rx|//rt-thread/bsp/sam7x|//rt-thread/bsp/samd21|//rt-thread/bsp/sep6200|//rt-thread/bsp/simulator|//rt-thread/bsp/smartfusion2|//rt-thread/bsp/sparkfun-redv|//rt-thread/bsp/stm32|//rt-thread/bsp/synopsys|//rt-thread/bsp/synwit|//rt-thread/bsp/tae32f5300|//rt-thread/bsp/taihu|//rt-thread/bsp/thead-smart|//rt-thread/bsp/ti|//rt-thread/bsp/tkm32F499|//rt-thread/bsp/tm4c123bsp|//rt-thread/bsp/tm4c129x|//rt-thread/bsp/tms320c6678|//rt-thread/bsp/upd70f3454|//rt-thread/bsp/w60x|//rt-thread/bsp/wch|//rt-thread/bsp/wh44b0|//rt-thread/bsp/x86|//rt-thread/bsp/xplorer4330|//rt-thread/bsp/yichip|//rt-thread/bsp/zynqmp-a53-dfzu2eg|//rt-thread/bsp/zynqmp-r5-axu4ev|//rt-thread/components/dfs/dfs_v1/filesystems/cromfs|//rt-thread/components/dfs/dfs_v1/filesystems/elmfat|//rt-thread/components/dfs/dfs_v1/filesystems/iso9660|//rt-thread/components/dfs/dfs_v1/filesystems/mqueue|//rt-thread/components/dfs/dfs_v1/filesystems/nfs|//rt-thread/components/dfs/dfs_v1/filesystems/ramfs|//rt-thread/components/dfs/dfs_v1/filesystems/romfs|//rt-thread/components/dfs/dfs_v1/filesystems/skeleton|//rt-thread/components/dfs/dfs_v1/filesystems/tmpfs|//rt-thread/components/dfs/dfs_v2|//rt-thread/components/drivers/ata|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/block|//rt-thread/components/drivers/can|//rt-thread/components/drivers/clk|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/mnt.c|//rt-thread/components/drivers/core/numa.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/core/power_domain.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/dma|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/iio|//rt-thread/components/drivers/ipc/completion_mp.c|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/led|//rt-thread/components/drivers/mailbox|//rt-thread/components/drivers/mfd|//rt-thread/components/drivers/misc|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/nvme|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/pci|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/phye|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pin/dev_pin_dm.c|//rt-thread/components/drivers/pin/dev_pin_ofw.c|//rt-thread/components/drivers/pinctrl|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/regulator|//rt-thread/components/drivers/reset|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/scsi|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/bypass.c|//rt-thread/components/drivers/serial/dev_serial_v2.c|//rt-thread/components/drivers/serial/serial_dm.c|//rt-thread/components/drivers/serial/serial_tty.c|//rt-thread/components/drivers/smp_call|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/thermal|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/mprotect|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/documentation|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v/common/atomic_riscv.c|//rt-thread/libcpu/risc-v/common64|//rt-thread/libcpu/risc-v/rv64|//rt-thread/libcpu/risc-v/t-head|//rt-thread/libcpu/risc-v/virt64|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu_mp.c|//rt-thread/src/klibc/rt_vsnprintf_std.c|//rt-thread/src/klibc/utest|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//startup/HPM6P81/toolchains/gcc/vectors.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" /> </sourceEntries> </configuration> </storageModule> diff --git a/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini b/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini index 421ec3853e..d0fbffb9b7 100644 --- a/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini +++ b/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini @@ -17,4 +17,4 @@ project_type=rt-thread os_branch=master
os_version=latest
project_name=blink_led
-output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk
\ No newline at end of file +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6p00evk
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/README.md b/bsp/hpmicro/hpm6p00evk/README.md index 355edee54e..3e4ee4ce20 100644 --- a/bsp/hpmicro/hpm6p00evk/README.md +++ b/bsp/hpmicro/hpm6p00evk/README.md @@ -73,7 +73,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Users can download the project via the below command: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6p80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - Users can debug the project via the below command: @@ -81,7 +81,7 @@ Open RT-Thread ENV command-line, and change directory to this BSP directory, the - Connect debugger via `OpenOCD`: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6p80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6p00evk.cfg ``` - Start Debugger via `GDB`: diff --git a/bsp/hpmicro/hpm6p00evk/README_zh.md b/bsp/hpmicro/hpm6p00evk/README_zh.md index e4a10fef31..13b92c11fd 100644 --- a/bsp/hpmicro/hpm6p00evk/README_zh.md +++ b/bsp/hpmicro/hpm6p00evk/README_zh.md @@ -73,14 +73,14 @@ HPM6P00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，� - 通过如下命令完成下载: ```console - %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + %OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6p80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" ``` - 通过如下命令实现调试: - 通过 `OpenOCD` 来连接开发板: ```console -%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg +%OPENOCD_HPMICRO%\openocd.exe -f board\debug_scripts\openocd\probes\ft2232.cfg -f board\debug_scripts\openocd\soc\hpm6p80-single-core.cfg -f board\debug_scripts\openocd\boards\hpm6p00evk.cfg ``` - 通过 `GDB` 实现调试: ```console diff --git a/bsp/hpmicro/hpm6p00evk/SConscript b/bsp/hpmicro/hpm6p00evk/SConscript index 014c428d0a..606b65445b 100644 --- a/bsp/hpmicro/hpm6p00evk/SConscript +++ b/bsp/hpmicro/hpm6p00evk/SConscript @@ -7,7 +7,6 @@ cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) -ASFLAGS = ' -I' + cwd for d in list: path = os.path.join(cwd, d) diff --git a/bsp/hpmicro/hpm6p00evk/SConstruct b/bsp/hpmicro/hpm6p00evk/SConstruct index d48a9a0956..c0ae22c1c2 100644 --- a/bsp/hpmicro/hpm6p00evk/SConstruct +++ b/bsp/hpmicro/hpm6p00evk/SConstruct @@ -16,13 +16,16 @@ except: exit(-1) def bsp_pkg_check(): - import subprocess - + if GetOption('clean'): + return + need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break + + if os.path.isdir("packages"): + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break if need_update: print("\n===============================================================================") print("Dependency packages missing, please running 'pkgs --update'...") @@ -64,9 +67,6 @@ if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): else: libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - GDB = rtconfig.GDB @@ -77,6 +77,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'), variant_dir='build/libraries/drivers', duplicate=0)) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'misc', 'SConscript'), variant_dir='build/libraries/misc', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6p00evk/applications/SConscript b/bsp/hpmicro/hpm6p00evk/applications/SConscript index a65aa4d855..00bf6b8d8f 100644 --- a/bsp/hpmicro/hpm6p00evk/applications/SConscript +++ b/bsp/hpmicro/hpm6p00evk/applications/SConscript @@ -1,5 +1,3 @@ -import rtconfig - from building import * cwd = GetCurrentDir() diff --git a/bsp/hpmicro/hpm6p00evk/applications/main.c b/bsp/hpmicro/hpm6p00evk/applications/main.c index a5a7f07c73..8aff6b8126 100644 --- a/bsp/hpmicro/hpm6p00evk/applications/main.c +++ b/bsp/hpmicro/hpm6p00evk/applications/main.c @@ -19,7 +19,10 @@ int main(void) static uint32_t led_thread_arg = 0; rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); - rt_thread_startup(led_thread); + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } return 0; } diff --git a/bsp/hpmicro/hpm6p00evk/board/Kconfig b/bsp/hpmicro/hpm6p00evk/board/Kconfig index 7cb6b9a996..e3b792d30d 100644 --- a/bsp/hpmicro/hpm6p00evk/board/Kconfig +++ b/bsp/hpmicro/hpm6p00evk/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_HPM6P00 bool - select SOC_HPM6P00_SERIES + select SOC_SERIES_HPM6P00 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -87,6 +87,11 @@ menu "On-chip Peripheral Drivers" int "UART1 Interrupt Priority" range 1 7 default 1 + config BSP_UART1_DMA_PINGPONG_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -114,6 +119,11 @@ menu "On-chip Peripheral Drivers" int "UART2 Interrupt Priority" range 1 7 default 1 + config BSP_UART2_DMA_PINGPONG_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -141,10 +151,15 @@ menu "On-chip Peripheral Drivers" int "UART3 Interrupt Priority" range 1 7 default 1 + config BSP_UART3_DMA_PINGPONG_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART4 bool "Enable UART4" - default n + default y if BSP_USING_UART4 config BSP_UART4_RX_USING_DMA bool "Enable UART4 RX DMA" @@ -168,6 +183,11 @@ menu "On-chip Peripheral Drivers" int "UART4 Interrupt Priority" range 1 7 default 1 + config BSP_UART4_DMA_PINGPONG_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART5 bool "Enable UART5" @@ -195,6 +215,11 @@ menu "On-chip Peripheral Drivers" int "UART5 Interrupt Priority" range 1 7 default 1 + config BSP_UART5_DMA_PINGPONG_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -222,6 +247,11 @@ menu "On-chip Peripheral Drivers" int "UART6 Interrupt Priority" range 1 7 default 1 + config BSP_UART6_DMA_PINGPONG_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 128 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -249,10 +279,33 @@ menu "On-chip Peripheral Drivers" int "UART7 Interrupt Priority" range 1 7 default 1 + config BSP_UART7_DMA_PINGPONG_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 8192 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 128 + endif + menuconfig BSP_USING_PUART + bool "Enable PUART" + default n + if BSP_USING_PUART + config BSP_PUART_RX_BUFSIZE + int "Set PUART RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_PUART_TX_BUFSIZE + int "Set PUART TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_PUART_IRQ_PRIORITY + int "PUART Interrupt Priority" + range 1 7 + default 1 endif endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n @@ -269,7 +322,7 @@ menu "On-chip Peripheral Drivers" int "SPI0 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI0_CS_SEL + choice prompt "Select SPI0 CS TYPE" default BSP_SPI0_USING_SOFT_CS config BSP_SPI0_USING_SOFT_CS @@ -277,7 +330,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI0_USING_HARD_CS bool "Enable SPI0 hardware cs" endchoice - choice BSP_SPI0_IO_MODE_SEL + choice prompt "Select SPI0 IO mode" default BSP_SPI0_USING_SINGLE_IO config BSP_SPI0_USING_SINGLE_IO @@ -299,7 +352,7 @@ menu "On-chip Peripheral Drivers" int "SPI1 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI1_CS_SEL + choice prompt "Select SPI1 CS TYPE" default BSP_SPI1_USING_SOFT_CS config BSP_SPI1_USING_SOFT_CS @@ -307,7 +360,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI1_USING_HARD_CS bool "Enable SPI1 hardware cs" endchoice - choice BSP_SPI1_IO_MODE_SEL + choice prompt "Select SPI1 IO mode" default BSP_SPI1_USING_SINGLE_IO config BSP_SPI1_USING_SINGLE_IO @@ -329,7 +382,7 @@ menu "On-chip Peripheral Drivers" int "SPI2 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI2_CS_SEL + choice prompt "Select SPI2 CS TYPE" default BSP_SPI2_USING_SOFT_CS config BSP_SPI2_USING_SOFT_CS @@ -337,7 +390,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI2_USING_HARD_CS bool "Enable SPI2 hardware cs" endchoice - choice BSP_SPI2_IO_MODE_SEL + choice prompt "Select SPI2 IO mode" default BSP_SPI2_USING_SINGLE_IO config BSP_SPI2_USING_SINGLE_IO @@ -359,7 +412,7 @@ menu "On-chip Peripheral Drivers" int "SPI3 Interrupt Priority" range 1 7 default 1 - choice BSP_SPI3_CS_SEL + choice prompt "Select SPI3 CS TYPE" default BSP_SPI3_USING_SOFT_CS config BSP_SPI3_USING_SOFT_CS @@ -367,7 +420,7 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_HARD_CS bool "Enable SPI3 hardware cs" endchoice - choice BSP_SPI3_IO_MODE_SEL + choice prompt "Select SPI3 IO mode" default BSP_SPI3_USING_SINGLE_IO config BSP_SPI3_USING_SINGLE_IO @@ -388,7 +441,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PHY if BSP_USING_ETH if BSP_USING_ETH - choice BSP_ETH0_SEL + choice prompt "ETH" default BSP_USING_ETH0 @@ -405,6 +458,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n if BSP_USING_GPTMR0 config BSP_GPTMR0_IRQ_PRIORITY @@ -439,6 +493,15 @@ menu "On-chip Peripheral Drivers" range 1 7 default 1 endif + config BSP_USING_PTMR + bool "Enable PTMR" + default n + if BSP_USING_PTMR + config BSP_PTMR_IRQ_PRIORITY + int "PTMR Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -496,7 +559,6 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n @@ -539,7 +601,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_EWDG bool "Enable EWDG" default n @@ -556,7 +617,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWMV2 bool "Enable PWM" default n - select RT_USING_PWM if BSP_USING_PWMV2 + select RT_USING_PWM menuconfig BSP_USING_MCAN bool "Enable MCAN" @@ -604,7 +665,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC bool "Enable ADC" default n - select RT_USING_ADC if BSP_USING_ADC + select RT_USING_ADC if BSP_USING_ADC menuconfig BSP_USING_ADC16 bool "Enable ADC16" @@ -622,13 +683,362 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC3 bool "Enable ADC3" default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n endif endif + menuconfig BSP_USING_WDG + bool "Enable WDG" + default n + select RT_USING_WDT if BSP_USING_WDG + + menuconfig BSP_USING_CRC + bool "Enable CRC" + default n + + menuconfig BSP_USING_TSNS + bool "Enable TSNS (Temperature Sensor)" + default n + + menuconfig BSP_USING_ACMP + bool "Enable ACMP (Analog Comparator)" + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + + menuconfig BSP_USING_QEIV2 + bool "Enable QEIV2 (Quadrature Encoder Interface V2)" + default n + + menuconfig BSP_USING_QEOV2 + bool "Enable QEOV2 (Quadrature Encoder Output V2)" + default n + + menuconfig BSP_USING_RDC + bool "Enable RDC (Resolver to Digital Converter)" + default n + + menuconfig BSP_USING_SEI + bool "Enable SEI (Synchronous Encoder Interface)" + default n + + menuconfig BSP_USING_MTGV2 + bool "Enable MTGV2 (Motor Timing Generator V2)" + default n + + menuconfig BSP_USING_VSC + bool "Enable VSC" + default n + + menuconfig BSP_USING_CLC + bool "Enable CLC" + default n + + menuconfig BSP_USING_SDM + bool "Enable SDM (Sigma-Delta Modulator)" + default n + + menuconfig BSP_USING_PLB + bool "Enable PLB" + default n + + menuconfig BSP_USING_PPI + bool "Enable PPI (Parallel Port Interface)" + default n + + menuconfig BSP_USING_LOBS + bool "Enable LOBS" + default n + + menuconfig BSP_USING_PTPC + bool "Enable PTPC (PTP Controller)" + default n + + menuconfig BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + default n + + menuconfig BSP_USING_SDP + bool "Enable SDP (Secure Data Processing)" + default n + + menuconfig BSP_USING_MCHTMR + bool "Enable MCHTMR (Machine Timer)" + default n + + menuconfig BSP_USING_SOFT_I2C + bool "Enable Software I2C" + default n + select RT_USING_I2C if BSP_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + + config BSP_USING_SOFT_I2C_TIMING_DELAY_US + int "Soft I2C timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_I2C_TIMING_TIMEOUT + int "Soft I2C timing timeout" + range 10 10000 + default 100 + + config BSP_USING_SOFT_I2C0 + bool "Enable Soft I2C0" + default n + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + string "Soft I2C0 SCL pin name" + default "None" + config BSP_SOFT_I2C0_SDA_PIN + string "Soft I2C0 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable Soft I2C1" + default n + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + string "Soft I2C1 SCL pin name" + default "None" + config BSP_SOFT_I2C1_SDA_PIN + string "Soft I2C1 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C2 + bool "Enable Soft I2C2" + default n + if BSP_USING_SOFT_I2C2 + config BSP_SOFT_I2C2_SCL_PIN + string "Soft I2C2 SCL pin name" + default "None" + config BSP_SOFT_I2C2_SDA_PIN + string "Soft I2C2 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C3 + bool "Enable Soft I2C3" + default n + if BSP_USING_SOFT_I2C3 + config BSP_SOFT_I2C3_SCL_PIN + string "Soft I2C3 SCL pin name" + default "None" + config BSP_SOFT_I2C3_SDA_PIN + string "Soft I2C3 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C4 + bool "Enable Soft I2C4" + default n + if BSP_USING_SOFT_I2C4 + config BSP_SOFT_I2C4_SCL_PIN + string "Soft I2C4 SCL pin name" + default "None" + config BSP_SOFT_I2C4_SDA_PIN + string "Soft I2C4 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C5 + bool "Enable Soft I2C5" + default n + if BSP_USING_SOFT_I2C5 + config BSP_SOFT_I2C5_SCL_PIN + string "Soft I2C5 SCL pin name" + default "None" + config BSP_SOFT_I2C5_SDA_PIN + string "Soft I2C5 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C6 + bool "Enable Soft I2C6" + default n + if BSP_USING_SOFT_I2C6 + config BSP_SOFT_I2C6_SCL_PIN + string "Soft I2C6 SCL pin name" + default "None" + config BSP_SOFT_I2C6_SDA_PIN + string "Soft I2C6 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C7 + bool "Enable Soft I2C7" + default n + if BSP_USING_SOFT_I2C7 + config BSP_SOFT_I2C7_SCL_PIN + string "Soft I2C7 SCL pin name" + default "None" + config BSP_SOFT_I2C7_SDA_PIN + string "Soft I2C7 SDA pin name" + default "None" + endif + + config BSP_USING_SOFT_I2C8 + bool "Enable Soft I2C8" + default n + if BSP_USING_SOFT_I2C8 + config BSP_SOFT_I2C8_SCL_PIN + string "Soft I2C8 SCL pin name" + default "None" + config BSP_SOFT_I2C8_SDA_PIN + string "Soft I2C8 SDA pin name" + default "None" + endif + + endif + + menuconfig BSP_USING_SOFT_SPI + bool "Enable Software SPI" + default n + select RT_USING_SPI if BSP_USING_SOFT_SPI + select RT_USING_PIN if BSP_USING_SOFT_SPI + select RT_USING_SPI_BITOPS if BSP_USING_SOFT_SPI + if BSP_USING_SOFT_SPI + + config BSP_USING_SOFT_SPI_TIMING_DELAY_US + int "Soft SPI timing delay in microseconds" + range 1 1000 + default 1 + + config BSP_USING_SOFT_SPI0 + bool "Enable Soft SPI0" + default n + if BSP_USING_SOFT_SPI0 + config BSP_SOFT_SPI0_SCK_PIN + string "Soft SPI0 SCK pin name" + default "None" + config BSP_SOFT_SPI0_MOSI_PIN + string "Soft SPI0 MOSI pin name" + default "None" + config BSP_SOFT_SPI0_MISO_PIN + string "Soft SPI0 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI1 + bool "Enable Soft SPI1" + default n + if BSP_USING_SOFT_SPI1 + config BSP_SOFT_SPI1_SCK_PIN + string "Soft SPI1 SCK pin name" + default "None" + config BSP_SOFT_SPI1_MOSI_PIN + string "Soft SPI1 MOSI pin name" + default "None" + config BSP_SOFT_SPI1_MISO_PIN + string "Soft SPI1 MISO pin name" + default "None" + endif + + config BSP_USING_SOFT_SPI2 + bool "Enable Soft SPI2" + default n + if BSP_USING_SOFT_SPI2 + config BSP_SOFT_SPI2_SCK_PIN + string "Soft SPI2 SCK pin name" + default "None" + config BSP_SOFT_SPI2_MOSI_PIN + string "Soft SPI2 MOSI pin name" + default "None" + config BSP_SOFT_SPI2_MISO_PIN + string "Soft SPI2 MISO pin name" + default "None" + endif + + endif + +endmenu + +menu "HPMicro Interrupt Config" endmenu +menu "HPMicro RT-Thread Interrupt Framework" +endmenu +menu "HPMicro Use Generic Startup Implementation" + config HPM_BSP_USING_GENERIC_STARTUP + bool "Enable this to use the common/startup/generic implementation" + default n + depends on HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + help + Enable this to use the common/startup/generic implementation. + This option is only available when RT-Thread Interrupt Framework is enabled. +endmenu +menu "HPMicro RT-Thread backtrace configuration (experimental)" + config HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Enable RT-Thread Backtrace for HPMicro BSP" + default n + help + Enable RT-Thread Backtrace to support backtrace feature + config HPM_USE_RTTHREAD_BACKTRACE_IN_EXCEPTION_HANDLER + select HPM_ENABLE_RTTHREAD_BACKTRACE_PORT + bool "Use RT-Thread Backtrace in Exception Handler" + default n + help + Use RT-Thread Backtrace in Exception Handler to print backtrace information +endmenu + +endmenu + +menu "Third-Party Add-ons" + +menu "Segger SystemView Config" + config BSP_USING_SYSTEMVIEW + select RT_USING_SYSTEMVIEW + select RT_USING_LEGACY + bool "Enable Segger SystemView" + default n + + if BSP_USING_SYSTEMVIEW + menuconfig BSP_SYSTEMVIEW_RTT_SECTION + bool "enable SystemView RTT section" + default y + if BSP_SYSTEMVIEW_RTT_SECTION + config SEGGER_RTT_SECTION + string "segger rtt section" + default ".noncacheable.bss" + config SEGGER_RTT_BUFFER_SECTION + string "segger rtt buffer section" + default ".noncacheable.bss" + config SEGGER_SYSVIEW_SECTION + string "segger sysview section" + default ".noncacheable.bss" + endif + endif endmenu +menu "RT-Thread Insight Config" + config BSP_USING_RTI + select BSP_USING_MCHTMR + select RT_USING_RTI + select RT_USING_RT_TUNNEL + bool "Enable RT-Thread Insight(experimental)" + default n + + if BSP_USING_RTI + config RT_TUNNEL_USE_NONCACHE_RAM + bool "Enable RT-Thread Insight Non-cacheable RAM support" + default y + help + Enable this to use non-cacheable RAM for RT-Thread Insight data transfer. + This option is useful when RT-Thread Insight is used with cache enabled. + + endif + +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg index 9e3359ae88..2dc61768c2 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg @@ -51,23 +51,10 @@ flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 proc init_clock {} { - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x1 - - $::_TARGET0 riscv dmi_write 0x39 0xF4002000 - $::_TARGET0 riscv dmi_write 0x3C 0x2 - - $::_TARGET0 riscv dmi_write 0x39 0xF4000800 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000810 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000820 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF - - $::_TARGET0 riscv dmi_write 0x39 0xF4000830 - $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + mww 0xF4000800 0xFFFFFFFF + mww 0xF4000810 0xFFFFFFFF + mww 0xF4000820 0xFFFFFFFF + mww 0xF4000830 0xFFFFFFFF echo "clocks has been enabled!" } diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg index b9ae112104..0aa1eed3da 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -1,8 +1,8 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 -adapter speed 10000 +adapter speed 8000 adapter srst delay 500 source [find interface/cmsis-dap.cfg] diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg index 580d98ef85..39cc8580f9 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -1,10 +1,8 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 adapter speed 10000 -reset_config trst_and_srst -adapter srst delay 50 adapter driver ftdi ftdi_vid_pid 0x0403 0x6010 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg index 4fb0fba2e7..e2c01a2d78 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg index fd8f04428c..5d565c0ecc 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg index e9d6e6d698..a9421a8387 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg index a3f2ee73f0..877324c042 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg @@ -1,9 +1,12 @@ -# Copyright (c) 2024 HPMicro +# Copyright (c) 2024-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause # - -set _CHIP hpm6p00 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6p00 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -14,39 +17,18 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -# source [find soc/hpm_common_csr.cfg] +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] -proc dmi_write {reg value} { - $::_TARGET0 riscv dmi_write ${reg} ${value} -} - -proc dmi_read {reg} { - set v [$::_TARGET0 riscv dmi_read ${reg}] - return ${v} -} -proc dmi_write_memory {addr value} { - dmi_write 0x39 ${addr} - dmi_write 0x3C ${value} -} - -proc dmi_read_memory {addr} { - set sbcs [expr { 0x100000 | [dmi_read 0x38] }] - dmi_write 0x38 ${sbcs} - dmi_write 0x39 ${addr} - set value [dmi_read 0x3C] - return ${value} -} proc release_core1 {} { - dmi_write_memory 0xF4002C00 0x1000 + sba_write_mem 0xF4002C00 0x1000 } set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 -# source [find soc/hpm_common_csr.cfg] - $_TARGET1 configure -event examine-start { release_core1 } @@ -57,11 +39,9 @@ $_TARGET1 configure -event reset-deassert-pre { } $_TARGET0 configure -event reset-end { - $::_TARGET0 riscv dmi_write 0x39 0xF4002010 - $::_TARGET0 riscv dmi_write 0x3C 0x2 + sba_write_mem 0xF4002010 0x2 } proc reset_soc {} { - $::_TARGET0 riscv dmi_write 0x39 0xF410001C - $::_TARGET0 riscv dmi_write 0x3C 24000000 + sba_write_mem 0xF410001C 24000000 } diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg index e370159ab6..2a1a8e0411 100644 --- a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg @@ -1,7 +1,11 @@ -# Copyright (c) 2024 HPMicro +# Copyright (c) 2024-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause -set _CHIP hpm6p00 +if { [info exists CHIPNAME] } { + set _CHIP $CHIPNAME +} else { + set _CHIP hpm6p00 +} set _CPUTAPID 0x1000563D jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID @@ -12,9 +16,10 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -# source [find soc/hpm_common_csr.cfg] +source [file join [file dirname [info script]] hpm_common.cfg] +source [file join [file dirname [info script]] hpm_common_csr.cfg] + proc reset_soc {} { - $::_TARGET0 riscv dmi_write 0x39 0xF410001C - $::_TARGET0 riscv dmi_write 0x3C 24000000 + sba_write_mem 0xF410001C 24000000 } diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common.cfg new file mode 100644 index 0000000000..ae9233e5e5 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common.cfg @@ -0,0 +1,29 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +source [file join [file dirname [info script]] hpm_reset.cfg] + +set dmsbcs 0x38 +set dmsbaddress0 0x39 +set dmsbdata0 0x3C + +proc target0_dmi_write_reg {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc target0_dmi_read_reg {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc sba_write_mem {addr value} { + target0_dmi_write_reg $::dmsbaddress0 ${addr} + target0_dmi_write_reg $::dmsbdata0 ${value} +} + +proc sba_read_mem {addr} { + set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }] + target0_dmi_write_reg $::dmsbcs ${sbcs} + target0_dmi_write_reg $::dmsbaddress0 ${addr} + set value [target0_dmi_read_reg $::dmsbdata0] + return ${value} +} diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg new file mode 100644 index 0000000000..4f4b6dcd86 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr.cfg @@ -0,0 +1,101 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# mslideleg +riscv expose_csrs 2005 +# mclk_ctl +riscv expose_csrs 2015 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# slie +riscv expose_csrs 2500 +# slip +riscv expose_csrs 2501 +# sdcause +riscv expose_csrs 2505 +# scctldata +riscv expose_csrs 2509 +# scounterinten +riscv expose_csrs 2511 +# scountermask_m +riscv expose_csrs 2513 +# scountermask_s +riscv expose_csrs 2514 +# scountermask_u +riscv expose_csrs 2515 +# scounterovf +riscv expose_csrs 2516 +# scountinhibit +riscv expose_csrs 2528 +# shpmevent3 +riscv expose_csrs 2531 +# shpmevent4 +riscv expose_csrs 2532 +# shpmevent5 +riscv expose_csrs 2533 +# shpmevent6 +riscv expose_csrs 2534 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg new file mode 100644 index 0000000000..096cee0635 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_common_csr_lite.cfg @@ -0,0 +1,69 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# expose non-standard csr registers +# milmb +riscv expose_csrs 1984 +# mdlmb +riscv expose_csrs 1985 +# mecc_code +riscv expose_csrs 1986 +# mnvec +riscv expose_csrs 1987 +# mxstatus +riscv expose_csrs 1988 +# mpft_ctl +riscv expose_csrs 1989 +# mhsp_ctl +riscv expose_csrs 1990 +# msp_bound +riscv expose_csrs 1991 +# msp_base +riscv expose_csrs 1992 +# mdcause +riscv expose_csrs 1993 +# mcache_ctl +riscv expose_csrs 1994 +# mcctlbeginaddr +riscv expose_csrs 1995 +# mcctlcommand +riscv expose_csrs 1996 +# mcctldata +riscv expose_csrs 1997 +# mcounterwen +riscv expose_csrs 1998 +# mcounterinten +riscv expose_csrs 1999 +# mmisc_ctl +riscv expose_csrs 2000 +# mcountermask_m +riscv expose_csrs 2001 +# mcountermask_s +riscv expose_csrs 2002 +# mcountermask_u +riscv expose_csrs 2003 +# mcounterovf +riscv expose_csrs 2004 +# dexc2dbg +riscv expose_csrs 2016 +# ddcause +riscv expose_csrs 2017 +# uitb +riscv expose_csrs 2048 +# ucode +riscv expose_csrs 2049 +# udcause +riscv expose_csrs 2057 +# ucctlbeginaddr +riscv expose_csrs 2059 +# ucctlcommand +riscv expose_csrs 2060 +# micm_cfg +riscv expose_csrs 4032 +# mdcm_cfg +riscv expose_csrs 4033 +# mmsc_cfg +riscv expose_csrs 4034 +# mmsc_cfg2 +riscv expose_csrs 4035 + diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg new file mode 100644 index 0000000000..681c599547 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm_reset.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +$_TARGET0 configure -event reset-deassert-pre { + sleep 1 + if {$halt} { + $::_TARGET0 arp_halt + } +} diff --git a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld index 8dc4e5efc8..acb9bb4829 100644 --- a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld +++ b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -28,6 +28,15 @@ __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; SECTIONS { + /* Anchor the lowest LMA at the flash base address (0x80000000): objcopy takes the + * lowest LMA as the start address of the generated .bin, so without this marker the + * .bin starts at .nor_cfg_option (0x80000400). The value is all ones (erased flash), + * so programming it does not change the flash state. + */ + .flash_base ORIGIN(XPI0) : { + LONG(0xFFFFFFFF) + } > XPI0 + .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) } > XPI0 @@ -175,7 +184,7 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); __fast_ram_init_start__ = .; @@ -185,6 +194,15 @@ SECTIONS . = ALIGN(8); } > DLM + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -276,7 +294,7 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); @@ -304,7 +322,7 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld deleted file mode 100644 index 5790d33157..0000000000 --- a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright 2021-2025 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; -FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01200000, LENGTH = NONCACHEABLE_SIZE - AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 128K - AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - . = ALIGN(16); - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors : AT(__vector_load_addr__) { - . = ALIGN(16); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - - . = ALIGN(16); - __vector_ram_end__ = .; - } > ILM - - .fast : AT(__fast_load_addr__) { - . = ALIGN(16); - __ramfunc_start__ = .; - *(.fast) - *(.fast.*) - . = ALIGN(16); - - /* RT-Thread Core Start */ - KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*port*.o (.text .text* .rodata .rodata*)) - KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) - KEEP(*trap_common.o (.text .text* .rodata .rodata*)) - KEEP(*irq.o (.text .text* .rodata .rodata*)) - KEEP(*clock.o (.text .text* .rodata .rodata*)) - KEEP(*kservice.o (.text .text* .rodata .rodata*)) - KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) - KEEP(*trap*.o (.text .text* .rodata .rodata*)) - KEEP(*idle.o (.text .text* .rodata .rodata*)) - KEEP(*ipc.o (.text .text* .rodata .rodata*)) - KEEP(*slab.o (.text .text* .rodata .rodata*)) - KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) - KEEP(*timer.o (.text .text* .rodata .rodata*)) - KEEP(*mem.o (.text .text* .rodata .rodata*)) - KEEP(*memheap.o (.text .text* .rodata .rodata*)) - KEEP(*mempool.o (.text .text* .rodata .rodata*)) - /* RT-Thread Core End */ - - /* HPMicro Driver Wrapper */ - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) - KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) - KEEP(*if_api*.o (.text .text* .rodata .rodata*)) - KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*netdb*.o (.text .text* .rodata .rodata*)) - KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) - KEEP(*sockets*.o (.text .text* .rodata .rodata*)) - KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) - KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) - KEEP(*memp*.o (.text .text* .rodata .rodata*)) - KEEP(*netif*.o (.text .text* .rodata .rodata*)) - KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) - KEEP(*tcp*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) - KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - - . = ALIGN(16); - __ramfunc_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(16); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP(*(.eh_frame)) - *(.eh_frame*) - - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - - /********************************************* - * - * RT-Thread related sections - Start - * - *********************************************/ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - } > XPI0 - - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - KEEP(*(.fast_ram.init.*)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: the .tbss and .tdata section should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.gnu.linkonce.tb.*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - __tdata_load_addr__ = etext; - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - __data_load_addr__ = etext + SIZEOF(.tdata); - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__fini_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__ctors_start__ = .); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - - - - .heap(NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .stack(NOLOAD) : { - . = ALIGN(8); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(8); - PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); - PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - KEEP(*(.noncacheable.non_init)) - KEEP(*(.noncacheable.non_init.*)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - KEEP(*(.noncacheable.bss.*)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); -} diff --git a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld index 717bb05827..05726ca78b 100644 --- a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld +++ b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -113,6 +113,16 @@ SECTIONS . = ALIGN(8); } > DLM + + .fast_ram.bss (NOLOAD) : { + . = ALIGN(8); + __fast_ram_bss_start__ = .; + *(.fast_ram.bss) + *(.fast_ram.bss.*) + __fast_ram_bss_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; diff --git a/bsp/hpmicro/hpm6p00evk/board/pinmux.c b/bsp/hpmicro/hpm6p00evk/board/pinmux.c index 00da125e99..f2d4a5b153 100644 --- a/bsp/hpmicro/hpm6p00evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6p00evk/board/pinmux.c @@ -50,7 +50,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr) } } -void init_i2c_pins(I2C_Type *ptr) +hpm_stat_t init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C3) { /* Codec */ HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; @@ -63,8 +63,9 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC29].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PC28].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - ; + return status_invalid_argument; } + return status_success; } void init_femc_pins(void) diff --git a/bsp/hpmicro/hpm6p00evk/board/pinmux.h b/bsp/hpmicro/hpm6p00evk/board/pinmux.h index 66c226788d..9f3d7ccfb2 100644 --- a/bsp/hpmicro/hpm6p00evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6p00evk/board/pinmux.h @@ -13,7 +13,7 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins(I2C_Type *ptr); +hpm_stat_t init_i2c_pins(I2C_Type *ptr); void init_femc_pins(void); void init_ppi_pins(void); void init_sdm_pins(void); diff --git a/bsp/hpmicro/hpm6p00evk/board/rtt_board.c b/bsp/hpmicro/hpm6p00evk/board/rtt_board.c index a20fe8ea45..cc36dc9d9b 100644 --- a/bsp/hpmicro/hpm6p00evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6p00evk/board/rtt_board.c @@ -40,14 +40,20 @@ void os_tick_config(void) void rtt_board_init(void) { board_init_clock(); + + /* initialize memory system + * NOTE: this must happen before board_init_console(), because the SDK console_init() + * calls setvbuf(), which allocates through the C library malloc() -> rt_malloc() and + * therefore requires the RT-Thread heap to be ready. Otherwise RT_ASSERT() fires in + * rt_smem_alloc() whenever RT_USING_DEBUG is enabled. + */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + board_init_console(); board_init_pmp(); dma_mgr_init(); - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); - /* Configure the OS Tick */ os_tick_config(); @@ -121,11 +127,11 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } #endif -uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ { uint32_t freq = 0; - if (ptr == (void *)HPM_ADC0) { + if (ptr == HPM_ADC0) { clock_add_to_group(clock_adc0, 0); if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ @@ -136,7 +142,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); } freq = clock_get_frequency(clock_adc0); - } else if (ptr == (void *)HPM_ADC1) { + } else if (ptr == HPM_ADC1) { clock_add_to_group(clock_adc1, 0); if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ @@ -147,7 +153,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); } freq = clock_get_frequency(clock_adc1); - } else if (ptr == (void *)HPM_ADC2) { + } else if (ptr == HPM_ADC2) { clock_add_to_group(clock_adc2, 0); if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ @@ -158,7 +164,7 @@ uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor syste clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); } freq = clock_get_frequency(clock_adc2); - } else if (ptr == (void *)HPM_ADC3) { + } else if (ptr == HPM_ADC3) { clock_add_to_group(clock_adc3, 0); if (clk_src_ahb) { /* Configure the ADC clock from AHB (@200MHz by default)*/ diff --git a/bsp/hpmicro/hpm6p00evk/makefile.targets b/bsp/hpmicro/hpm6p00evk/makefile.targets index e71da5a6e1..8469d7d2aa 100644 --- a/bsp/hpmicro/hpm6p00evk/makefile.targets +++ b/bsp/hpmicro/hpm6p00evk/makefile.targets @@ -3,4 +3,4 @@ clean2: -$(RM) $(OBJS) *.elf -@echo ' ' -*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds)
\ No newline at end of file +*.elf: $(wildcard board/linker_scripts/gcc/*.ld)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig.h b/bsp/hpmicro/hpm6p00evk/rtconfig.h index 908c7f404f..7886de7929 100644 --- a/bsp/hpmicro/hpm6p00evk/rtconfig.h +++ b/bsp/hpmicro/hpm6p00evk/rtconfig.h @@ -7,6 +7,16 @@ /* rt_vsnprintf options */ +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -108,7 +118,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50301 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -294,6 +304,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -321,12 +335,24 @@ /* HPMicro SDK */ #define PKG_USING_HPM_SDK -#define PKG_USING_HPM_SDK_V110 +#define PKG_USING_HPM_SDK_V113 /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -406,7 +432,7 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_HPM6P00_SERIES +#define SOC_SERIES_HPM6P00 /* Hardware Drivers Config */ @@ -422,6 +448,29 @@ #define BSP_UART0_TX_BUFSIZE 0 #define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ + +/* HPMicro Interrupt Config */ + +/* HPMicro RT-Thread Interrupt Framework */ + +/* HPMicro Use Generic Startup Implementation */ + +/* end of HPMicro Use Generic Startup Implementation */ + +/* HPMicro RT-Thread backtrace configuration (experimental) */ + +/* end of HPMicro RT-Thread backtrace configuration (experimental) */ /* end of Hardware Drivers Config */ +/* Third-Party Add-ons */ + +/* Segger SystemView Config */ + +/* end of Segger SystemView Config */ + +/* RT-Thread Insight Config */ + +/* end of RT-Thread Insight Config */ +/* end of Third-Party Add-ons */ + #endif diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig.py b/bsp/hpmicro/hpm6p00evk/rtconfig.py index accc54ed8c..52990f6b60 100644 --- a/bsp/hpmicro/hpm6p00evk/rtconfig.py +++ b/bsp/hpmicro/hpm6p00evk/rtconfig.py @@ -3,7 +3,6 @@ import os import sys -import rtconfig if os.getenv('RTT_ROOT'): @@ -11,7 +10,7 @@ if os.getenv('RTT_ROOT'): else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +sys.path.insert(0, os.path.join(RTT_ROOT, 'tools')) # toolchains options ARCH='risc-v' @@ -59,9 +58,13 @@ if CROSS_TOOL == 'gcc': else: EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' else: - print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + print("CROSS_TOOL = {} not yet supported, only gcc is supported".format(CROSS_TOOL)) + exit(-1) -BUILD = 'flash_debug' +if os.getenv('RTT_BUILD_TYPE'): + BUILD = os.getenv('RTT_BUILD_TYPE') +else: + BUILD = 'flash_debug' if PLATFORM == 'gcc': PREFIX = 'riscv32-unknown-elf-' @@ -81,7 +84,7 @@ if PLATFORM == 'gcc': DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' CFLAGS = DEVICE AFLAGS = CFLAGS - LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' CPATH = '' LPATH = '' @@ -89,8 +92,8 @@ if PLATFORM == 'gcc': if BUILD == 'ram_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' @@ -99,8 +102,8 @@ if PLATFORM == 'gcc': elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - LFLAGS += ' -O0' + CFLAGS += ' -Og' + LFLAGS += ' -Og' CFLAGS += ' -DFLASH_XIP=1' LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h index b7ae18b326..a21f4c7482 100644 --- a/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h +++ b/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h @@ -6,8 +6,7 @@ /* RT-Thread pre-include file */ #define D45 -#define HPM6880 -#define HPM6E80 +#define HPM6P81 #define HPMSOC_HAS_HPMSDK_DMAV2 #define RT_USING_LIBC #define RT_USING_NEWLIBC diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c index e3f85a9e0e..78705526d8 100644 --- a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c @@ -54,6 +54,8 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; + extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; /* tbss section */ size = __tbss_end__ - __tbss_start__; @@ -96,6 +98,18 @@ __attribute__((weak)) void c_startup(void) for (i = 0; i < size; i++) { *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } + + /* fast_ram bss section */ + size = __fast_ram_bss_end__ - __fast_ram_bss_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_bss_start__ + i) = 0; + } + + /* fast_ram init section LMA: etext + data length + ramfunc length + tdata length */ + size = __fast_ram_init_end__ - __fast_ram_init_start__; + for (i = 0; i < size; i++) { + *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); + } #endif } diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S index c200076924..0262684ad3 100644 --- a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S @@ -77,6 +77,7 @@ _start: nmi_handler: 1: j 1b +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK .weak default_irq_handler .align 2 default_irq_handler: @@ -89,3 +90,13 @@ default_irq_handler: .endm #include "vectors.S" +#else + .section .vector_table, "a" + .global __vector_table + .align 9 + +__vector_table: + .rept RT_HW_ISR_NUM + .long handle_trap + .endr +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S index 51d8f5dc5c..cc6604ec3b 100644 --- a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S @@ -15,109 +15,160 @@ __vector_table: IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 8 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 9 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 10 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 11 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 13 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 14 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 15 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 16 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 17 /* Reserved */ - IRQ_HANDLER 18 /* Reserved */ - IRQ_HANDLER 19 /* Reserved */ - IRQ_HANDLER 20 /* Reserved */ - IRQ_HANDLER 21 /* UART0 IRQ handler */ - IRQ_HANDLER 22 /* UART1 IRQ handler */ - IRQ_HANDLER 23 /* UART2 IRQ handler */ - IRQ_HANDLER 24 /* UART3 IRQ handler */ - IRQ_HANDLER 25 /* UART4 IRQ handler */ - IRQ_HANDLER 26 /* UART5 IRQ handler */ - IRQ_HANDLER 27 /* UART6 IRQ handler */ - IRQ_HANDLER 28 /* UART7 IRQ handler */ - IRQ_HANDLER 29 /* I2C0 IRQ handler */ - IRQ_HANDLER 30 /* I2C1 IRQ handler */ - IRQ_HANDLER 31 /* I2C2 IRQ handler */ - IRQ_HANDLER 32 /* I2C3 IRQ handler */ - IRQ_HANDLER 33 /* SPI0 IRQ handler */ - IRQ_HANDLER 34 /* SPI1 IRQ handler */ - IRQ_HANDLER 35 /* SPI2 IRQ handler */ - IRQ_HANDLER 36 /* SPI3 IRQ handler */ - IRQ_HANDLER 37 /* TSNS IRQ handler */ - IRQ_HANDLER 38 /* MBX0A IRQ handler */ - IRQ_HANDLER 39 /* MBX0B IRQ handler */ - IRQ_HANDLER 40 /* MBX1A IRQ handler */ - IRQ_HANDLER 41 /* MBX1B IRQ handler */ - IRQ_HANDLER 42 /* EWDG0 IRQ handler */ - IRQ_HANDLER 43 /* EWDG1 IRQ handler */ - IRQ_HANDLER 44 /* EWDG2 IRQ handler */ - IRQ_HANDLER 45 /* EWDG3 IRQ handler */ - IRQ_HANDLER 46 /* HDMA IRQ handler */ - IRQ_HANDLER 47 /* LOBS IRQ handler */ - IRQ_HANDLER 48 /* ADC0 IRQ handler */ - IRQ_HANDLER 49 /* ADC1 IRQ handler */ - IRQ_HANDLER 50 /* ADC2 IRQ handler */ - IRQ_HANDLER 51 /* ADC3 IRQ handler */ - IRQ_HANDLER 52 /* DAC0 IRQ handler */ - IRQ_HANDLER 53 /* DAC1 IRQ handler */ - IRQ_HANDLER 54 /* ACMP0[0] IRQ handler */ - IRQ_HANDLER 55 /* ACMP0[1] IRQ handler */ - IRQ_HANDLER 56 /* ACMP1[0] IRQ handler */ - IRQ_HANDLER 57 /* ACMP1[1] IRQ handler */ - IRQ_HANDLER 58 /* ACMP2[0] IRQ handler */ - IRQ_HANDLER 59 /* ACMP2[1] IRQ handler */ - IRQ_HANDLER 60 /* ACMP3[0] IRQ handler */ - IRQ_HANDLER 61 /* ACMP3[1] IRQ handler */ - IRQ_HANDLER 62 /* I2S0 IRQ handler */ - IRQ_HANDLER 63 /* I2S1 IRQ handler */ - IRQ_HANDLER 64 /* DAO IRQ handler */ - IRQ_HANDLER 65 /* PDM IRQ handler */ - IRQ_HANDLER 66 /* MCAN0 IRQ handler */ - IRQ_HANDLER 67 /* MCAN1 IRQ handler */ - IRQ_HANDLER 68 /* MCAN2 IRQ handler */ - IRQ_HANDLER 69 /* MCAN3 IRQ handler */ - IRQ_HANDLER 70 /* PTPC IRQ handler */ - IRQ_HANDLER 71 /* QEI0 IRQ handler */ - IRQ_HANDLER 72 /* QEI1 IRQ handler */ - IRQ_HANDLER 73 /* PWM0 IRQ handler */ - IRQ_HANDLER 74 /* PWM1 IRQ handler */ - IRQ_HANDLER 75 /* PWM2 IRQ handler */ - IRQ_HANDLER 76 /* PWM3 IRQ handler */ - IRQ_HANDLER 77 /* RDC0 IRQ handler */ - IRQ_HANDLER 78 /* SDM0 IRQ handler */ - IRQ_HANDLER 79 /* SEI0[0] IRQ handler */ - IRQ_HANDLER 80 /* SEI0[1] IRQ handler */ - IRQ_HANDLER 81 /* MTG0 IRQ handler */ - IRQ_HANDLER 82 /* VSC0 IRQ handler */ - IRQ_HANDLER 83 /* CLC0[0] IRQ handler */ - IRQ_HANDLER 84 /* CLC0[1] IRQ handler */ - IRQ_HANDLER 85 /* TRGMUX0 IRQ handler */ - IRQ_HANDLER 86 /* TRGMUX1 IRQ handler */ - IRQ_HANDLER 87 /* ENET0 IRQ handler */ - IRQ_HANDLER 88 /* NTMR0 IRQ handler */ - IRQ_HANDLER 89 /* USB0 IRQ handler */ - IRQ_HANDLER 90 /* XPI0 IRQ handler */ - IRQ_HANDLER 91 /* FEMC IRQ handler */ - IRQ_HANDLER 92 /* PPI IRQ handler */ - IRQ_HANDLER 93 /* XDMA IRQ handler */ - IRQ_HANDLER 94 /* FFA IRQ handler */ - IRQ_HANDLER 95 /* SDP IRQ handler */ - IRQ_HANDLER 96 /* RNG IRQ handler */ - IRQ_HANDLER 97 /* PSEC IRQ handler */ - IRQ_HANDLER 98 /* PGPIO IRQ handler */ - IRQ_HANDLER 99 /* PEWDG IRQ handler */ - IRQ_HANDLER 100 /* PTMR IRQ handler */ - IRQ_HANDLER 101 /* PUART IRQ handler */ - IRQ_HANDLER 102 /* FUSE IRQ handler */ - IRQ_HANDLER 103 /* SECMON IRQ handler */ - IRQ_HANDLER 104 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 105 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 106 /* SYSCTL IRQ handler */ - IRQ_HANDLER 107 /* CPU0 IRQ handler */ - IRQ_HANDLER 108 /* CPU1 IRQ handler */ - IRQ_HANDLER 109 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 110 /* DEBUG1 IRQ handler */
\ No newline at end of file + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_V IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_W IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_V IRQ handler */ + IRQ_HANDLER 19 /* GPIO1_W IRQ handler */ + IRQ_HANDLER 20 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 23 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 24 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 25 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 26 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 27 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 28 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 29 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 30 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* I2C0 IRQ handler */ + IRQ_HANDLER 40 /* I2C1 IRQ handler */ + IRQ_HANDLER 41 /* I2C2 IRQ handler */ + IRQ_HANDLER 42 /* I2C3 IRQ handler */ + IRQ_HANDLER 43 /* SPI0 IRQ handler */ + IRQ_HANDLER 44 /* SPI1 IRQ handler */ + IRQ_HANDLER 45 /* SPI2 IRQ handler */ + IRQ_HANDLER 46 /* SPI3 IRQ handler */ + IRQ_HANDLER 47 /* TSNS IRQ handler */ + IRQ_HANDLER 48 /* MBX0A IRQ handler */ + IRQ_HANDLER 49 /* MBX0B IRQ handler */ + IRQ_HANDLER 50 /* MBX1A IRQ handler */ + IRQ_HANDLER 51 /* MBX1B IRQ handler */ + IRQ_HANDLER 52 /* EWDG0 IRQ handler */ + IRQ_HANDLER 53 /* EWDG1 IRQ handler */ + IRQ_HANDLER 54 /* EWDG2 IRQ handler */ + IRQ_HANDLER 55 /* EWDG3 IRQ handler */ + IRQ_HANDLER 56 /* HDMA IRQ handler */ + IRQ_HANDLER 57 /* LOBS IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_HANDLER 60 /* ADC2 IRQ handler */ + IRQ_HANDLER 61 /* ADC3 IRQ handler */ + IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */ + IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */ + IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */ + IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */ + IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */ + IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */ + IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */ + IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */ + IRQ_HANDLER 70 /* I2S0 IRQ handler */ + IRQ_HANDLER 71 /* I2S1 IRQ handler */ + IRQ_HANDLER 72 /* DAO IRQ handler */ + IRQ_HANDLER 73 /* PDM IRQ handler */ + IRQ_HANDLER 74 /* UART8 IRQ handler */ + IRQ_HANDLER 75 /* UART9 IRQ handler */ + IRQ_HANDLER 76 /* UART10 IRQ handler */ + IRQ_HANDLER 77 /* UART11 IRQ handler */ + IRQ_HANDLER 78 /* UART12 IRQ handler */ + IRQ_HANDLER 79 /* UART13 IRQ handler */ + IRQ_HANDLER 80 /* UART14 IRQ handler */ + IRQ_HANDLER 81 /* UART15 IRQ handler */ + IRQ_HANDLER 82 /* I2C4 IRQ handler */ + IRQ_HANDLER 83 /* I2C5 IRQ handler */ + IRQ_HANDLER 84 /* I2C6 IRQ handler */ + IRQ_HANDLER 85 /* I2C7 IRQ handler */ + IRQ_HANDLER 86 /* SPI4 IRQ handler */ + IRQ_HANDLER 87 /* SPI5 IRQ handler */ + IRQ_HANDLER 88 /* SPI6 IRQ handler */ + IRQ_HANDLER 89 /* SPI7 IRQ handler */ + IRQ_HANDLER 90 /* MCAN0 IRQ handler */ + IRQ_HANDLER 91 /* MCAN1 IRQ handler */ + IRQ_HANDLER 92 /* MCAN2 IRQ handler */ + IRQ_HANDLER 93 /* MCAN3 IRQ handler */ + IRQ_HANDLER 94 /* MCAN4 IRQ handler */ + IRQ_HANDLER 95 /* MCAN5 IRQ handler */ + IRQ_HANDLER 96 /* MCAN6 IRQ handler */ + IRQ_HANDLER 97 /* MCAN7 IRQ handler */ + IRQ_HANDLER 98 /* PTPC IRQ handler */ + IRQ_HANDLER 99 /* QEI0 IRQ handler */ + IRQ_HANDLER 100 /* QEI1 IRQ handler */ + IRQ_HANDLER 101 /* QEI2 IRQ handler */ + IRQ_HANDLER 102 /* QEI3 IRQ handler */ + IRQ_HANDLER 103 /* PWM0 IRQ handler */ + IRQ_HANDLER 104 /* PWM1 IRQ handler */ + IRQ_HANDLER 105 /* PWM2 IRQ handler */ + IRQ_HANDLER 106 /* PWM3 IRQ handler */ + IRQ_HANDLER 107 /* RDC0 IRQ handler */ + IRQ_HANDLER 108 /* RDC1 IRQ handler */ + IRQ_HANDLER 109 /* SDM0 IRQ handler */ + IRQ_HANDLER 110 /* SDM1 IRQ handler */ + IRQ_HANDLER 111 /* SEI[0] IRQ handler */ + IRQ_HANDLER 112 /* SEI[1] IRQ handler */ + IRQ_HANDLER 113 /* SEI[2] IRQ handler */ + IRQ_HANDLER 114 /* SEI[3] IRQ handler */ + IRQ_HANDLER 115 /* MTG0 IRQ handler */ + IRQ_HANDLER 116 /* MTG1 IRQ handler */ + IRQ_HANDLER 117 /* VSC0 IRQ handler */ + IRQ_HANDLER 118 /* VSC1 IRQ handler */ + IRQ_HANDLER 119 /* CLC0[0] IRQ handler */ + IRQ_HANDLER 120 /* CLC0[1] IRQ handler */ + IRQ_HANDLER 121 /* CLC1[0] IRQ handler */ + IRQ_HANDLER 122 /* CLC1[1] IRQ handler */ + IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 125 /* ENET0 IRQ handler */ + IRQ_HANDLER 126 /* NTMR0 IRQ handler */ + IRQ_HANDLER 127 /* USB0 IRQ handler */ + IRQ_HANDLER 128 /* TSW[0] IRQ handler */ + IRQ_HANDLER 129 /* TSW[1] IRQ handler */ + IRQ_HANDLER 130 /* TSW[2] IRQ handler */ + IRQ_HANDLER 131 /* TSW[3] IRQ handler */ + IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ + IRQ_HANDLER 133 /* ESC IRQ handler */ + IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */ + IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */ + IRQ_HANDLER 136 /* ESC_RESET IRQ handler */ + IRQ_HANDLER 137 /* XPI0 IRQ handler */ + IRQ_HANDLER 138 /* FEMC IRQ handler */ + IRQ_HANDLER 139 /* PPI IRQ handler */ + IRQ_HANDLER 140 /* XDMA IRQ handler */ + IRQ_HANDLER 141 /* FFA IRQ handler */ + IRQ_HANDLER 142 /* SDP IRQ handler */ + IRQ_HANDLER 143 /* RNG IRQ handler */ + IRQ_HANDLER 144 /* PKA IRQ handler */ + IRQ_HANDLER 145 /* PSEC IRQ handler */ + IRQ_HANDLER 146 /* PGPIO IRQ handler */ + IRQ_HANDLER 147 /* PEWDG IRQ handler */ + IRQ_HANDLER 148 /* PTMR IRQ handler */ + IRQ_HANDLER 149 /* PUART IRQ handler */ + IRQ_HANDLER 150 /* FUSE IRQ handler */ + IRQ_HANDLER 151 /* SECMON IRQ handler */ + IRQ_HANDLER 152 /* RTC IRQ handler */ + IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 154 /* BGPIO IRQ handler */ + IRQ_HANDLER 155 /* BVIO IRQ handler */ + IRQ_HANDLER 156 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 157 /* SYSCTL IRQ handler */ + IRQ_HANDLER 158 /* CPU0 IRQ handler */ + IRQ_HANDLER 159 /* CPU1 IRQ handler */ + IRQ_HANDLER 160 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 161 /* DEBUG1 IRQ handler */
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/startup/SConscript b/bsp/hpmicro/hpm6p00evk/startup/SConscript index 10776376b7..11a9d203d4 100644 --- a/bsp/hpmicro/hpm6p00evk/startup/SConscript +++ b/bsp/hpmicro/hpm6p00evk/startup/SConscript @@ -8,6 +8,5 @@ cwd = GetCurrentDir() objs = [] objs = objs + SConscript(os.path.join(rtconfig.CHIP_NAME, 'SConscript')) -ASFLAGS = ' -I' + cwd Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/libraries/Kconfig b/bsp/hpmicro/libraries/Kconfig index 2384b53176..1a1608e178 100644 --- a/bsp/hpmicro/libraries/Kconfig +++ b/bsp/hpmicro/libraries/Kconfig @@ -1,47 +1,42 @@ -config SOC_HPM6700_SERIES +config SOC_SERIES_HPM5000 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM6300_SERIES +config SOC_SERIES_HPM5100 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM6200_SERIES +config SOC_SERIES_HPM5300 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM5300_SERIES +config SOC_SERIES_HPM5E00 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM6800_SERIES +config SOC_SERIES_HPM6000 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM6E00_SERIES +config SOC_SERIES_HPM6E00 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM6P00_SERIES +config SOC_SERIES_HPM6P00 bool select ARCH_RISCV32 select ARCH_RISCV_DPU select PKG_USING_HPM_SDK -config SOC_HPM5E00_SERIES - bool - select ARCH_RISCV32 - select ARCH_RISCV_DPU - select PKG_USING_HPM_SDK
\ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript index 4f5fa25d84..0a93a0b282 100644 --- a/bsp/hpmicro/libraries/drivers/SConscript +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -33,7 +33,7 @@ if GetDepend('BSP_USING_SDXC'): if GetDepend('BSP_USING_PWM') or GetDepend('BSP_USING_PWMV2'): src += ['drv_pwm.c'] -if GetDepend('BSP_USING_GPTMR'): +if GetDepend('BSP_USING_GPTMR') or GetDepend('BSP_USING_GPTMRV2'): src += ['drv_timer.c'] if GetDepend('BSP_USING_CAN'): @@ -72,6 +72,12 @@ if GetDepend(['BSP_USING_RTT_LCD_DRIVER']): if GetDepend('BSP_USING_TSW'): src += ['drv_tsw.c'] src += ['drv_tsw_phy.c'] + +if GetDepend('BSP_USING_SOFT_I2C'): + src += ['drv_soft_i2c.c'] + +if GetDepend('BSP_USING_SOFT_SPI'): + src += ['drv_soft_spi.c'] path = [cwd] diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.c b/bsp/hpmicro/libraries/drivers/drv_adc.c index f29ad15310..f0192b1613 100644 --- a/bsp/hpmicro/libraries/drivers/drv_adc.c +++ b/bsp/hpmicro/libraries/drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,11 +17,17 @@ #endif #include "hpm_sysctl_drv.h" +#if defined(BSP_USING_ADC16) && defined(ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN +#define HPM_ADC16_HAS_TEMP_SENSOR (1) +#define HPM_ADC16_TEMP_SAMPLE_CYCLE (511U) +#else +#define HPM_ADC16_HAS_TEMP_SENSOR (0) +#endif + +#ifndef BOARD_ADC_VREF_MV +#define BOARD_ADC_VREF_MV (3300) +#endif -typedef struct -{ - bool enabled; -} adc_channel_state_t; typedef struct { @@ -30,16 +36,17 @@ typedef struct bool is_adc12; bool adc_enabled; uint32_t adc_base; - adc_channel_state_t chn_state[16]; + rt_atomic_t enabled_channels; }hpm_rtt_adc; #if defined(ADC12_SOC_MAX_CH_NUM) -extern uint32_t rtt_board_init_adc12_clock(ADC16_Type *ptr); +extern uint32_t rtt_board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); #endif extern uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); static uint32_t hpm_adc_init_clock(struct rt_adc_device *device); static void hpm_adc_init_pins(struct rt_adc_device *device); +static bool hpm_adc_get_channel(const hpm_rtt_adc *adc, rt_int8_t channel, uint8_t *adc_chn); static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled); static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value); @@ -106,6 +113,39 @@ static hpm_rtt_adc hpm_adc_config_tbl[] = static uint8_t adc_nums = sizeof(hpm_adc_config_tbl) / sizeof(hpm_rtt_adc); +static bool hpm_adc_get_channel(const hpm_rtt_adc *adc, rt_int8_t channel, uint8_t *adc_chn) +{ + RT_ASSERT(adc_chn != RT_NULL); + +#if HPM_ADC16_HAS_TEMP_SENSOR + if (!adc->is_adc12 && channel == RT_ADC_INTERN_CH_TEMPER) { + *adc_chn = ADC16_SOC_TEMP_CH_NUM; + return true; + } +#endif + + if (channel < 0) { + return false; + } + + *adc_chn = (uint8_t)channel; + + if (adc->is_adc12) { +#ifdef BSP_USING_ADC12 + return !ADC12_IS_CHANNEL_INVALID(*adc_chn); +#else + return false; +#endif + } + +#ifdef BSP_USING_ADC16 + return !ADC16_IS_CHANNEL_INVALID(*adc_chn); +#else + return false; +#endif +} + + static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) { hpm_rtt_adc *hpm_adc; @@ -116,7 +156,7 @@ static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) #if defined(ADC12_SOC_MAX_CH_NUM) if (hpm_adc->is_adc12) { - clock_freq = rtt_board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base,true); + clock_freq = rtt_board_init_adc12_clock((ADC12_Type *)hpm_adc->adc_base, true); } else #endif { @@ -151,8 +191,8 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) adc12_get_default_config(&cfg); cfg.res = adc12_res_12_bits; cfg.conv_mode = adc12_conv_mode_oneshot; - cfg.adc_ahb_en = true; cfg.adc_clk_div = 3; + cfg.wait_dis = false; ret = adc12_init((ADC12_Type *)adc->adc_base, &cfg); if (ret != status_success) { return -RT_ERROR; @@ -166,8 +206,9 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) cfg.conv_mode = adc16_conv_mode_oneshot; cfg.res = adc16_res_16_bits; cfg.adc_clk_div = 4; +#if !defined(HPM_IP_FEATURE_ADC16_FORCE_SYNC_AHB) || !HPM_IP_FEATURE_ADC16_FORCE_SYNC_AHB cfg.sel_sync_ahb = true; - cfg.adc_ahb_en = true; +#endif cfg.wait_dis = 0; ret = adc16_init((ADC16_Type *)adc->adc_base, &cfg); if (ret != status_success) { @@ -206,11 +247,23 @@ static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) adc16_get_channel_default_config(&ch_cfg); ch_cfg.ch = channel; - ch_cfg.sample_cycle = 20; +#if HPM_ADC16_HAS_TEMP_SENSOR + if (channel == ADC16_SOC_TEMP_CH_NUM) { + ch_cfg.sample_cycle = HPM_ADC16_TEMP_SAMPLE_CYCLE; + } else +#endif + { + ch_cfg.sample_cycle = 20; + } ret = adc16_init_channel((ADC16_Type *)adc->adc_base, &ch_cfg); if (ret != status_success) { return -RT_ERROR; } +#if HPM_ADC16_HAS_TEMP_SENSOR + if (channel == ADC16_SOC_TEMP_CH_NUM) { + adc16_enable_temp_sensor((ADC16_Type *)adc->adc_base); + } +#endif #endif } return RT_EOK; @@ -219,12 +272,21 @@ static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) { hpm_rtt_adc *hpm_adc; - rt_err_t ret; + rt_err_t ret = RT_EOK; + rt_base_t critical_level; + rt_atomic_t channel_mask; + uint8_t adc_chn; RT_ASSERT(device != RT_NULL); hpm_adc = (hpm_rtt_adc *)device->parent.user_data; + if (!hpm_adc_get_channel(hpm_adc, channel, &adc_chn)) { + return -RT_EINVAL; + } + + channel_mask = (rt_atomic_t)1U << adc_chn; + critical_level = rt_enter_critical(); if (enabled == RT_TRUE) { - if (!hpm_adc->chn_state[channel].enabled) + if ((rt_atomic_load(&hpm_adc->enabled_channels) & channel_mask) == 0) { if (!hpm_adc->adc_enabled) { @@ -232,49 +294,76 @@ static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, (void)hpm_adc_init_clock(device); ret = init_adc_config(hpm_adc); if (ret != RT_EOK) { - return -RT_ERROR; + goto exit; } hpm_adc->adc_enabled = true; } - hpm_adc->chn_state[channel].enabled = true; - ret = init_channel_config(hpm_adc, channel); + ret = init_channel_config(hpm_adc, adc_chn); if (ret != RT_EOK) { - return -RT_ERROR; + goto exit; } + (void)rt_atomic_or(&hpm_adc->enabled_channels, channel_mask); } } else { - /* Since the ADC channel cannot be truly disabled, do nothing here */ + /* The hardware has no per-channel disable in oneshot mode. */ +#if HPM_ADC16_HAS_TEMP_SENSOR + rt_atomic_t old_channels; + + old_channels = rt_atomic_and(&hpm_adc->enabled_channels, ~channel_mask); + if (!hpm_adc->is_adc12 && adc_chn == ADC16_SOC_TEMP_CH_NUM + && (old_channels & channel_mask) != 0) { + adc16_disable_temp_sensor((ADC16_Type *)hpm_adc->adc_base); + } +#else + (void)rt_atomic_and(&hpm_adc->enabled_channels, ~channel_mask); +#endif } - return RT_EOK; +exit: + rt_exit_critical_safe(critical_level); + return ret; } static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { hpm_rtt_adc *hpm_adc; - rt_err_t ret; + hpm_stat_t status; rt_uint16_t val; + uint8_t adc_chn; RT_ASSERT(device != RT_NULL); RT_ASSERT(value != RT_NULL); hpm_adc = (hpm_rtt_adc *)device->parent.user_data; - uint32_t adc_chn = (uint16_t)channel; + if (!hpm_adc_get_channel(hpm_adc, channel, &adc_chn)) { + return -RT_EINVAL; + } + if ((rt_atomic_load(&hpm_adc->enabled_channels) & ((rt_atomic_t)1U << adc_chn)) == 0) { + return -RT_EINVAL; + } + if (hpm_adc->is_adc12) { #ifdef BSP_USING_ADC12 - adc12_get_oneshot_result((ADC12_Type *)hpm_adc->adc_base, adc_chn, &val); - *value = val; + status = adc12_get_oneshot_result((ADC12_Type *)hpm_adc->adc_base, adc_chn, &val); +#else + return -RT_ENOSYS; #endif } else { #ifdef BSP_USING_ADC16 - hpm_stat_t status = adc16_get_oneshot_result((ADC16_Type *)hpm_adc->adc_base, adc_chn, &val); - *value = val; + status = adc16_get_oneshot_result((ADC16_Type *)hpm_adc->adc_base, adc_chn, &val); +#else + return -RT_ENOSYS; #endif } + if (status != status_success) { + return -RT_ERROR; + } + *value = val; + return RT_EOK; } @@ -293,7 +382,9 @@ static rt_uint8_t hpm_get_resolution(struct rt_adc_device *device) static rt_int16_t hpm_get_vref(struct rt_adc_device *device) { - return -RT_EIO; + RT_UNUSED(device); + + return BOARD_ADC_VREF_MV; } int rt_hw_adc_init(void) @@ -306,7 +397,7 @@ int rt_hw_adc_init(void) &hpm_adc_ops, &hpm_adc_config_tbl[i]); if (ret != RT_EOK) { - ret = RT_ERROR; + ret = -RT_ERROR; break; } } diff --git a/bsp/hpmicro/libraries/drivers/drv_can.c b/bsp/hpmicro/libraries/drivers/drv_can.c index b94f0e10ea..b5428fe31a 100644 --- a/bsp/hpmicro/libraries/drivers/drv_can.c +++ b/bsp/hpmicro/libraries/drivers/drv_can.c @@ -3,183 +3,289 @@ * * SPDX-License-Identifier: BSD-3-Clause * + * @file drv_can.c + * @brief CAN driver implementation for RT-Thread + * + * This file implements the CAN (Controller Area Network) driver for HPM6700 + * and HPM6300 series, providing a complete interface between RT-Thread's CAN + * framework and the HPM CAN hardware. + * + * Features: + * - Support for up to 4 CAN controllers (CAN0-CAN3) + * - CAN 2.0A/B and CAN FD support + * - Hardware filtering with up to 16 filters + * - Interrupt-driven operation + * - Error handling and status reporting + * - Configurable baud rates and timing parameters + * * Change Logs: * Date Author Notes * 2022-05-08 HPMicro the first version * 2023-05-08 HPMicro Adapt RT-Thread v5.0.0 + * 2025/03-25 HPMicro Add configurable interrupt priority support + * 2025-09-01 HPMicro Revised the code, reduced repetitive codes */ +#include "rtconfig.h" + +#ifdef RT_USING_CAN + +/* RT-Thread includes */ #include <rtthread.h> #include <rtdevice.h> -#include <rthw.h> + +/* HPM SDK includes */ #include "board.h" #include "hpm_can_drv.h" - #include "hpm_clock_drv.h" +#include <rthw.h> -#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ -#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ -#define CAN_FILTER_NUM_MAX (16U) /* CAN Hardware Filter number */ +/* CAN Driver Configuration Constants */ +#define CAN_SEND_WAIT_MS_MAX (1000U) /* Maximum wait time for transmission (ms) */ +#define CAN_SENDBOX_NUM (1U) /* Number of hardware transmission buffers */ +#define CAN_FILTER_NUM_MAX (16U) /* Maximum number of hardware filters */ -#ifdef RT_USING_CAN +/* + * Interrupt Priority Configuration Macros + * These macros handle the configuration of interrupt priorities for each CAN controller. + * If a specific priority is defined in the board configuration, it will be used; + * otherwise, a default priority of 1 is applied. + */ + +/* CAN IRQ Priority Configuration Macros */ +#ifdef BSP_CAN0_IRQ_PRIORITY +#define CAN_IRQ_PRI_VAL_0 BSP_CAN0_IRQ_PRIORITY +#else +#define CAN_IRQ_PRI_VAL_0 1 +#endif + +#ifdef BSP_CAN1_IRQ_PRIORITY +#define CAN_IRQ_PRI_VAL_1 BSP_CAN1_IRQ_PRIORITY +#else +#define CAN_IRQ_PRI_VAL_1 1 +#endif +#ifdef BSP_CAN2_IRQ_PRIORITY +#define CAN_IRQ_PRI_VAL_2 BSP_CAN2_IRQ_PRIORITY +#else +#define CAN_IRQ_PRI_VAL_2 1 +#endif + +#ifdef BSP_CAN3_IRQ_PRIORITY +#define CAN_IRQ_PRI_VAL_3 BSP_CAN3_IRQ_PRIORITY +#else +#define CAN_IRQ_PRI_VAL_3 1 +#endif + +#define CAN_IRQ_PRI_VAL(n) CAN_IRQ_PRI_VAL_##n + +#define CAN_UNITED (0UL) +#define CAN_INITED (1UL) +#define CAN_RUNNING (2UL) +#define CAN_STOPPED (3UL) + +/* + * CAN Device Definition Macro + * This macro creates a complete CAN device structure and its associated ISR. + * It reduces code duplication by generating device-specific code for each CAN controller. + * + * @param n CAN controller number (0-3) + */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +#define CAN_DEVICE_DEFINE(n) \ + static hpm_can_t dev_can##n = \ + { \ + .can_base = HPM_CAN##n, \ + .name = "can" #n, \ + .irq_num = IRQn_CAN##n, \ + .fifo_index = n, \ + .clk_name = clock_can##n, \ + .irq_priority = CAN_IRQ_PRI_VAL(n), \ + }; \ + SDK_DECLARE_EXT_ISR_M(IRQn_CAN##n, can##n##_isr); \ + void can##n##_isr(void) \ + { \ + hpm_can_isr(&dev_can##n); \ + } +#else +#define CAN_DEVICE_DEFINE(n) \ + static hpm_can_t dev_can##n = \ + { \ + .can_base = HPM_CAN##n, \ + .name = "can" #n, \ + .irq_num = IRQn_CAN##n, \ + .fifo_index = n, \ + .clk_name = clock_can##n, \ + .irq_priority = CAN_IRQ_PRI_VAL(n), \ + }; +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +/* + * Common Pattern Macros + * These macros simplify repetitive code patterns throughout the driver. + */ + +/* Macro to extract CAN driver context from RT-Thread device structure */ +#define CAN_GET_DRV(can) \ + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; \ + RT_ASSERT(drv_can) + +/* Interrupt mask definitions for different CAN event types */ +#define CAN_RX_IRQ_MASK (CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN) +#define CAN_TX_IRQ_MASK (CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF) +#define CAN_ERR_IRQ_MASK (CAN_ERROR_ARBITRATION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE) + +/** + * @brief HPM CAN driver context structure + * + * This structure contains all the necessary information to manage a CAN controller, + * including hardware registers, configuration, and RT-Thread device interface. + */ typedef struct _hpm_can_struct { - CAN_Type *can_base; /**< CAN Base address */ - const char *name; /**< CAN device name */ - int32_t irq_num; /**< CAN IRQ index */ - uint8_t irq_priority; /**< CAN IRQ priority */ - clock_name_t clk_name; /**< CAN clock name */ - uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ - can_config_t can_config; /**< CAN configuration for IP */ - struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ - uint32_t filter_num; /**< Filter number */ - can_filter_config_t filter_list[CAN_FILTER_NUM_MAX]; /**< Filter list */ + CAN_Type *can_base; /**< CAN hardware base address */ + const char *name; /**< CAN device name (e.g., "can0", "can1") */ + rt_int32_t irq_num; /**< CAN interrupt number */ + rt_uint8_t irq_priority; /**< CAN interrupt priority */ + clock_name_t clk_name; /**< CAN clock source name */ + rt_uint32_t fifo_index; /**< FIFO index (used for RT-Thread framework compatibility) */ + can_config_t can_config; /**< HPM CAN hardware configuration */ + struct rt_can_device can_dev; /**< RT-Thread CAN device structure */ + rt_uint32_t filter_num; /**< Number of active hardware filters */ + can_filter_config_t filter_list[CAN_FILTER_NUM_MAX]; /**< Array of hardware filter configurations */ + rt_uint8_t can_stat; /**< CAN status */ } hpm_can_t; +/* ============================================================================ + * Function Declarations + * ============================================================================ */ + /** - * @brief Configure CAN controller - * @param [in/out] can CAN device pointer - * @param [in] cfg CAN configuration pointer - * @retval RT_EOK for valid configuration - * @retval -RT_ERROR for invalid configuration + * @brief Configure CAN controller with specified parameters + * + * This function configures the CAN controller with the provided configuration + * including baud rate, mode, timing parameters, and filter settings. + * + * @param [in/out] can Pointer to RT-Thread CAN device structure + * @param [in] cfg Pointer to CAN configuration structure + * @retval RT_EOK Configuration successful + * @retval -RT_ERROR Configuration failed */ static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg); /** - * @brief Control/Get CAN state - * including:interrupt, mode, priority, baudrate, filter, status - * @param [in/out] can CAN device pointer - * @param [in] cmd Control command - * @param [in/out] arg Argument pointer - * @retval RT_EOK for valid control command and arg - * @retval -RT_ERROR for invalid control command or arg + * @brief Control CAN device and get/set various parameters + * + * This function handles various control commands including: + * - Interrupt enable/disable + * - Filter configuration + * - Mode changes + * - Baud rate changes + * - Status retrieval + * + * @param [in/out] can Pointer to RT-Thread CAN device structure + * @param [in] cmd Control command (see RT_CAN_CMD_* definitions) + * @param [in/out] arg Command argument (input/output depending on command) + * @retval RT_EOK Command executed successfully + * @retval -RT_ERROR Invalid command or argument */ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg); /** - * @brief Send out CAN message - * @param [in] can CAN device pointer - * @param [in] buf CAN message buffer - * @param [in] boxno Mailbox number, it is not used in this porting - * @retval RT_EOK No error - * @retval -RT_ETIMEOUT timeout happened - * @retval -RT_EFULL Transmission buffer is full + * @brief Send CAN message + * + * This function transmits a CAN message using the hardware transmission buffers. + * It supports both standard and extended frame formats, as well as CAN FD. + * + * @param [in] can Pointer to RT-Thread CAN device structure + * @param [in] buf Pointer to CAN message structure + * @param [in] boxno Mailbox number (not used in this implementation) + * @retval RT_EOK Message sent successfully + * @retval -RT_ETIMEOUT Transmission timeout + * @retval -RT_EFULL Transmission buffer full */ static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); /** - * @brief Receive message from CAN - * @param [in] can CAN device pointer - * @param [out] buf CAN receive buffer - * @param [in] boxno Mailbox Number, it is not used in this porting - * @retval RT_EOK no error - * @retval -RT_ERROR Error happened during reading receive FIFO - * @retval -RT_EMPTY no data in receive FIFO + * @brief Receive CAN message + * + * This function receives a CAN message from the hardware receive FIFO. + * It handles both standard and extended frame formats, as well as CAN FD. + * + * @param [in] can Pointer to RT-Thread CAN device structure + * @param [out] buf Pointer to buffer for received CAN message + * @param [in] boxno Mailbox number (not used in this implementation) + * @retval RT_EOK Message received successfully + * @retval -RT_ERROR Error during reception + * @retval -RT_EMPTY No data available in receive FIFO */ static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); /** - * @brief Common Interrupt Service routine - * @param [in] hpm_can HPM CAN pointer + * @brief CAN interrupt service routine + * + * This function handles all CAN-related interrupts including: + * - Transmission completion + * - Reception of new messages + * - Error conditions + * - FIFO overflow + * + * @param [in] hpm_can Pointer to HPM CAN driver context */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_can_isr(hpm_can_t *hpm_can); +#else +static void hpm_can_isr(int vector, hpm_can_t *hpm_can); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ /** - * @brief Decode data bytes from DLC - * @param [in] dlc Data Length Code - * @return decoded data bytes + * @brief Convert DLC (Data Length Code) to actual data bytes + * + * This function converts the CAN DLC field to the actual number of data bytes. + * It handles both CAN 2.0 (up to 8 bytes) and CAN FD (up to 64 bytes) formats. + * + * @param [in] dlc Data Length Code from CAN frame + * @return Number of actual data bytes */ static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); -#if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0) -static hpm_can_t dev_can0 = -{ - .can_base = HPM_CAN0, - .name = "can0", - .irq_num = IRQn_CAN0, - .fifo_index = 0, - .clk_name = clock_can0, -#if defined(BSP_CAN0_IRQ_PRIORITY) - .irq_priority = BSP_CAN0_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif -}; +/** + * @brief Update CAN error status from hardware registers + * + * This function reads the current error status from the CAN hardware registers + * and updates the driver's error status structure with the latest information. + * + * @param [in] hpm_can Pointer to HPM CAN driver context + */ +static void can_update_error_status(hpm_can_t *hpm_can); -SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); -void can0_isr(void) -{ - hpm_can_isr(&dev_can0); -} +/* ============================================================================ + * CAN Device Instances + * ============================================================================ */ +/* CAN0 device instance - created if HPM_CAN0_BASE is defined and BSP_USING_CAN0 is enabled */ +#if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0) +CAN_DEVICE_DEFINE(0) #endif +/* CAN1 device instance - created if HPM_CAN1_BASE is defined and BSP_USING_CAN1 is enabled */ #if defined(HPM_CAN1_BASE) && defined(BSP_USING_CAN1) -static hpm_can_t dev_can1 = -{ - .can_base = HPM_CAN1, - .name = "can1", - .irq_num = IRQn_CAN1, - .fifo_index = 1, - .clk_name = clock_can1, -#if defined(BSP_CAN1_IRQ_PRIORITY) - .irq_priority = BSP_CAN1_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); -void can1_isr(void) -{ - hpm_can_isr(&dev_can1); -} +CAN_DEVICE_DEFINE(1) #endif +/* CAN2 device instance - created if HPM_CAN2_BASE is defined and BSP_USING_CAN2 is enabled */ #if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2) -static hpm_can_t dev_can2 = -{ - .can_base = HPM_CAN2, - .name = "can2", - .irq_num = IRQn_CAN2, - .fifo_index = 2, - .clk_name = clock_can2, -#if defined(BSP_CAN2_IRQ_PRIORITY) - .irq_priority = BSP_CAN2_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); -void can2_isr(void) -{ - hpm_can_isr(&dev_can2); -} +CAN_DEVICE_DEFINE(2) #endif +/* CAN3 device instance - created if HPM_CAN3_BASE is defined and BSP_USING_CAN3 is enabled */ #if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3) -static hpm_can_t dev_can3 = -{ - .can_base = HPM_CAN3, - .name = "can3", - .irq_num = IRQn_CAN3, - .fifo_index = 3, - .clk_name = clock_can3, -#if defined(BSP_CAN3_IRQ_PRIORITY) - .irq_priority = BSP_CAN3_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); -void can3_isr(void) -{ - hpm_can_isr(&dev_can3); -} +CAN_DEVICE_DEFINE(3) #endif +/* Array of CAN device pointers - used for initialization and management */ static hpm_can_t *hpm_cans[] = { #if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0) &dev_can0, @@ -195,48 +301,66 @@ static hpm_can_t *hpm_cans[] = { #endif }; - +/* RT-Thread CAN operations structure - defines the interface between RT-Thread and this driver */ static const struct rt_can_ops hpm_can_ops = { - .configure = hpm_can_configure, - .control = hpm_can_control, - .sendmsg = hpm_can_sendmsg, - .recvmsg = hpm_can_recvmsg, + .configure = hpm_can_configure, /* Configure CAN controller */ + .control = hpm_can_control, /* Control CAN device operations */ + .sendmsg = hpm_can_sendmsg, /* Send CAN message */ + .recvmsg = hpm_can_recvmsg, /* Receive CAN message */ }; +/* ============================================================================ + * Function Implementations + * ============================================================================ */ + +/** + * @brief CAN interrupt service routine + * + * This function is called when a CAN interrupt occurs. It handles various + * interrupt types including transmission completion, reception, and errors. + * + * @param [in] hpm_can Pointer to HPM CAN driver context + */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_can_isr(hpm_can_t *hpm_can) +#else +static void hpm_can_isr(int vector, hpm_can_t *hpm_can) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { + /* Read interrupt flags from hardware */ uint8_t tx_rx_flags = can_get_tx_rx_flags(hpm_can->can_base); uint8_t error_flags = can_get_error_interrupt_flags(hpm_can->can_base); - /* High-priority message transmission done */ + /* Handle high-priority message transmission completion */ if ((tx_rx_flags & CAN_EVENT_TX_PRIMARY_BUF) != 0U) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); } - /* Normal priority message transmission done */ + /* Handle normal priority message transmission completion */ if ((tx_rx_flags & CAN_EVENT_TX_SECONDARY_BUF) != 0U) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); } - /* Data available in FIFO */ - if ((tx_rx_flags & CAN_EVENT_RECEIVE) == CAN_EVENT_RECEIVE) + /* Handle new message reception */ + if (((tx_rx_flags & CAN_EVENT_RECEIVE) == CAN_EVENT_RECEIVE) && ((hpm_can->can_stat != CAN_STOPPED) || (hpm_can->can_stat != CAN_UNITED))) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8)); } - /* RX FIFO overflow */ - if ((tx_rx_flags & CAN_EVENT_RX_BUF_OVERRUN) != 0U) + /* Handle receive FIFO overflow */ + if (((tx_rx_flags & CAN_EVENT_RX_BUF_OVERRUN) != 0U) && ((hpm_can->can_stat != CAN_STOPPED) || (hpm_can->can_stat != CAN_UNITED))) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); } - /* Error happened on CAN Bus */ + /* Handle CAN bus errors */ if (((tx_rx_flags & CAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) { + /* Get the specific error type and update error counters */ uint8_t err_kind = can_get_last_error_kind(hpm_can->can_base); switch(err_kind) { @@ -257,35 +381,32 @@ static void hpm_can_isr(hpm_can_t *hpm_can) break; } - hpm_can->can_dev.status.rcverrcnt = can_get_receive_error_count(hpm_can->can_base); - hpm_can->can_dev.status.snderrcnt = can_get_transmit_error_count(hpm_can->can_base); - hpm_can->can_dev.status.lasterrtype = can_get_last_error_kind(hpm_can->can_base); - hpm_can->can_dev.status.errcode = 0; - if ((error_flags & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U) - { - hpm_can->can_dev.status.errcode |= ERRWARNING; - } - if ((error_flags & CAN_ERROR_PASSIVE_INT_FLAG) != 0U) - { - hpm_can->can_dev.status.errcode |= ERRPASSIVE; - } - if (can_is_in_bus_off_mode(hpm_can->can_base)) - { - hpm_can->can_dev.status.errcode |= BUSOFF; - } + /* Update error status from hardware registers */ + can_update_error_status(hpm_can); } + /* Clear processed interrupt flags */ can_clear_tx_rx_flags(hpm_can->can_base, tx_rx_flags); can_clear_error_interrupt_flags(hpm_can->can_base, error_flags); } +/** + * @brief Configure CAN controller with specified parameters + * + * This function configures the CAN controller with the provided configuration + * including baud rate, mode, timing parameters, and filter settings. + * + * @param [in/out] can Pointer to RT-Thread CAN device structure + * @param [in] cfg Pointer to CAN configuration structure + * @retval RT_EOK Configuration successful + * @retval -RT_ERROR Configuration failed + */ static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg) { RT_ASSERT(can); RT_ASSERT(cfg); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; - RT_ASSERT(drv_can); + CAN_GET_DRV(can); #ifdef RT_CAN_USING_CANFD drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false; @@ -340,7 +461,7 @@ static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configur { return -RT_ERROR; } - + drv_can->can_stat = CAN_INITED; return RT_EOK; } @@ -348,73 +469,54 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; - RT_ASSERT(drv_can); + CAN_GET_DRV(can); uint32_t arg_val; rt_err_t err = RT_EOK; - uint32_t temp; - switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: arg_val = (uint32_t) arg; intc_m_disable_irq(drv_can->irq_num); - if (arg_val == RT_DEVICE_FLAG_INT_RX) - { - uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN; - drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; - can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + if (arg_val & RT_DEVICE_FLAG_INT_RX) { + drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~CAN_RX_IRQ_MASK; + can_disable_tx_rx_irq(drv_can->can_base, CAN_RX_IRQ_MASK); } - else if (arg_val == RT_DEVICE_FLAG_INT_TX) - { - uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF; - drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; - can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + if (arg_val & RT_DEVICE_FLAG_INT_TX) { + drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~CAN_TX_IRQ_MASK; + can_disable_tx_rx_irq(drv_can->can_base, CAN_TX_IRQ_MASK); } - else if (arg_val == RT_DEVICE_CAN_INT_ERR) - { + if (arg_val & RT_DEVICE_CAN_INT_ERR) { uint8_t irq_txrx_mask = CAN_EVENT_ERROR; - uint8_t irq_error_mask = CAN_ERROR_ARBITRATION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE; drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; - drv_can->can_config.irq_error_enable_mask &= (uint8_t)~irq_error_mask; + drv_can->can_config.irq_error_enable_mask &= (uint8_t)~CAN_ERR_IRQ_MASK; can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); - can_disable_error_irq(drv_can->can_base, irq_error_mask); - } - else - { + can_disable_error_irq(drv_can->can_base, CAN_ERR_IRQ_MASK); + } else { err = -RT_ERROR; } break; case RT_DEVICE_CTRL_SET_INT: arg_val = (uint32_t) arg; - if (arg_val == RT_DEVICE_FLAG_INT_RX) - { - uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN; - drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; - can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + if (arg_val & RT_DEVICE_FLAG_INT_RX) { + drv_can->can_config.irq_txrx_enable_mask |= CAN_RX_IRQ_MASK; + can_enable_tx_rx_irq(drv_can->can_base, CAN_RX_IRQ_MASK); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } - else if (arg_val == RT_DEVICE_FLAG_INT_TX) - { - uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF; - drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; - can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + if (arg_val & RT_DEVICE_FLAG_INT_TX) { + drv_can->can_config.irq_txrx_enable_mask |= CAN_TX_IRQ_MASK; + can_enable_tx_rx_irq(drv_can->can_base, CAN_TX_IRQ_MASK); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } - else if (arg_val == RT_DEVICE_CAN_INT_ERR) - { + if (arg_val & RT_DEVICE_CAN_INT_ERR) { uint8_t irq_txrx_mask = CAN_EVENT_ERROR; - uint8_t irq_error_mask = CAN_ERROR_ARBITRATION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE; drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; - drv_can->can_config.irq_error_enable_mask |= irq_error_mask; + drv_can->can_config.irq_error_enable_mask |= CAN_ERR_IRQ_MASK; can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); - can_enable_error_irq(drv_can->can_base, irq_error_mask); + can_enable_error_irq(drv_can->can_base, CAN_ERR_IRQ_MASK); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); - } - else - { + } else { err = -RT_ERROR; } break; @@ -520,25 +622,22 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) } break; case RT_CAN_CMD_GET_STATUS: - drv_can->can_dev.status.rcverrcnt = can_get_receive_error_count(drv_can->can_base); - drv_can->can_dev.status.snderrcnt = can_get_transmit_error_count(drv_can->can_base); - drv_can->can_dev.status.lasterrtype = can_get_last_error_kind(drv_can->can_base); - temp = can_get_error_interrupt_flags(drv_can->can_base); - drv_can->can_dev.status.errcode = 0; - if ((temp & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U) - { - drv_can->can_dev.status.errcode |= ERRWARNING; - } - if ((temp & CAN_ERROR_PASSIVE_INT_FLAG) != 0U) - { - drv_can->can_dev.status.errcode |= ERRPASSIVE; - } - if (can_is_in_bus_off_mode(drv_can->can_base)) - { - drv_can->can_dev.status.errcode |= BUSOFF; - } + can_update_error_status(drv_can); rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; + case RT_CAN_CMD_START: + arg_val = (rt_uint32_t)arg; + if (arg_val == 0) { + can_deinit(drv_can->can_base); + drv_can->can_stat = CAN_STOPPED; + } else { + if (can_init(drv_can->can_base, &drv_can->can_config, clock_get_frequency(drv_can->clk_name)) != status_success) { + err = -RT_ERROR; + } else { + drv_can->can_stat = CAN_RUNNING; + } + } + break; } return err; } @@ -547,11 +646,14 @@ static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32 { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; - RT_ASSERT(drv_can); + CAN_GET_DRV(can); struct rt_can_msg *can_msg = (struct rt_can_msg *) buf; + if ((drv_can->can_stat == CAN_UNITED) || (drv_can->can_stat == CAN_STOPPED)) { + return -RT_ERROR; + } + can_transmit_buf_t tx_buf = { 0 }; tx_buf.id = can_msg->id; if (can_msg->ide == RT_CAN_STDID) @@ -636,8 +738,7 @@ static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t box { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; - RT_ASSERT(drv_can); + CAN_GET_DRV(can); rt_can_msg_t can_msg = (rt_can_msg_t)buf; @@ -684,6 +785,28 @@ static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t box return RT_EOK; } +static void can_update_error_status(hpm_can_t *hpm_can) +{ + hpm_can->can_dev.status.rcverrcnt = can_get_receive_error_count(hpm_can->can_base); + hpm_can->can_dev.status.snderrcnt = can_get_transmit_error_count(hpm_can->can_base); + hpm_can->can_dev.status.lasterrtype = can_get_last_error_kind(hpm_can->can_base); + hpm_can->can_dev.status.errcode = 0; + + uint32_t temp = can_get_error_interrupt_flags(hpm_can->can_base); + if ((temp & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRWARNING; + } + if ((temp & CAN_ERROR_PASSIVE_INT_FLAG) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (can_is_in_bus_off_mode(hpm_can->can_base)) + { + hpm_can->can_dev.status.errcode |= BUSOFF; + } +} + static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc) { uint32_t data_bytes = 0; @@ -723,25 +846,55 @@ static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc) return data_bytes; } +/* ============================================================================ + * Driver Initialization + * ============================================================================ */ + +/** + * @brief Initialize CAN hardware drivers + * + * This function initializes all available CAN controllers and registers them + * with the RT-Thread device framework. It sets up default configurations + * and prepares the hardware for operation. + * + * @retval RT_EOK Initialization successful + */ int rt_hw_can_init(void) { + /* Set up default CAN configuration */ struct can_configure config = CANDEFAULTCONFIG; - config.privmode = RT_CAN_MODE_NOPRIV; - config.sndboxnumber = CAN_SENDBOX_NUM; - config.ticks = 50; + config.privmode = RT_CAN_MODE_NOPRIV; /* Disable private mode by default */ + config.sndboxnumber = CAN_SENDBOX_NUM; /* Set number of send mailboxes */ + config.ticks = 50; /* Set timeout ticks */ + #ifdef RT_CAN_USING_HDR - config.maxhdr = 16; + config.maxhdr = 16; /* Set maximum number of hardware filters */ #endif + + /* Initialize each available CAN controller */ for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { + /* Set default configuration */ hpm_cans[i]->can_dev.config = config; - hpm_cans[i]->filter_num = 0; + hpm_cans[i]->filter_num = 0; /* No filters active initially */ + hpm_cans[i]->can_stat = CAN_UNITED; /* Set initial status */ + + /* Get default hardware configuration from HPM SDK */ can_get_default_config(&hpm_cans[i]->can_config); + + /* Register CAN device with RT-Thread */ rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); + +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register CAN device to irq table */ + rt_hw_interrupt_install(hpm_cans[i]->irq_num, (rt_isr_handler_t)hpm_can_isr, hpm_cans[i], hpm_cans[i]->name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } + return RT_EOK; } +/* Register initialization function to be called during system startup */ INIT_BOARD_EXPORT(rt_hw_can_init); -#endif +#endif /* RT_USING_CAN */ diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.c b/bsp/hpmicro/libraries/drivers/drv_dao.c index caa73dd86b..d81cecf0cd 100644 --- a/bsp/hpmicro/libraries/drivers/drv_dao.c +++ b/bsp/hpmicro/libraries/drivers/drv_dao.c @@ -109,17 +109,14 @@ static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) transfer.sample_rate = samplerate; bool is_enabled = i2s_is_enabled(DAO_I2S); if (is_enabled) { - dma_abort_channel(dma_resource.base, dma_resource.channel); + LOG_E("dao_i2s mot support to configure samplerate when dao_i2s is active\n"); + return -RT_ERROR; } if (status_success != i2s_config_tx(DAO_I2S, mclk_hz, &transfer)) { LOG_E("dao_i2s configure transfer failed\n"); return -RT_ERROR; } - if (is_enabled) - { - i2s_enable(DAO_I2S); - } return RT_EOK; } @@ -149,6 +146,7 @@ static rt_err_t hpm_dao_configure(struct rt_audio_device* audio, struct rt_audio result = -RT_ERROR; break; } + break; } default: @@ -170,7 +168,10 @@ static rt_err_t hpm_dao_init(struct rt_audio_device* audio) board_init_dao_clock(); i2s_get_default_config(DAO_I2S, &i2s_config); - i2s_init(DAO_I2S, &i2s_config); + if (status_success != i2s_init(DAO_I2S, &i2s_config)) { + LOG_E("dao_i2s init failed\n"); + return -RT_ERROR; + } i2s_enable_tx_dma_request(DAO_I2S); mclk_hz = clock_get_frequency(clock_i2s1); @@ -217,7 +218,11 @@ static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) } /* fill 2 dummy data, it is suitable for 1/2 channel of audio */ - i2s_reset_tx(DAO_I2S); + if (status_success != i2s_reset_tx(DAO_I2S)) { + LOG_E("dao_i2s reset tx failed\n"); + return -RT_ERROR; + } + i2s_enable_tx_line(DAO_I2S, DAO_I2S_DATA_LINE); if (i2s_fill_tx_dummy_data(DAO_I2S, DAO_I2S_DATA_LINE, 2) != status_success) { return -RT_ERROR; } @@ -236,7 +241,7 @@ static rt_err_t hpm_dao_stop(struct rt_audio_device* audio, int stream) dao_stop(HPM_DAO); i2s_stop(DAO_I2S); - dma_abort_channel(dma_resource.base, dma_resource.channel); + dma_mgr_abort_chn_transfer(&dma_resource); dma_mgr_release_resource(&dma_resource); return RT_EOK; @@ -257,6 +262,7 @@ static rt_ssize_t hpm_dao_transmit(struct rt_audio_device* audio, const void* wr ch_config.size_in_byte = size; ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch_config.interrupt_mask = DMA_INTERRUPT_MASK_ABORT; if (l1c_dc_is_enabled()) { /* cache writeback for sent buff */ diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.c b/bsp/hpmicro/libraries/drivers/drv_enet.c index 1b5a48b637..6ab01d76d2 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet.c @@ -5,21 +5,33 @@ * * Change Logs: * Date Author Notes - * 2022-01-11 HPMicro First version - * 2022-07-10 HPMicro Driver optimization for multiple instances - * 2024-04-15 HPMicro Fixed an issue that received data is probabilistically overwritten + * 2022-01-11 Jiading First version + * 2022-07-10 Jiading Driver optimization for multiple instances + * 2025-04-15 Jiading Fixed an issue that received data is probabilistically overwritten + * 2025-12-01 Jiading Optimized the driver for PTP initialization + * 2026-07-18 Jiading Align ENET HW checksum with RT_LWIP_USING_HW_CHECKSUM + * 2026-07-18 Jiading Align ENET ISR and MMC interrupt init with hpm_sdk v1.12.0 + * 2026-10-08 Jiading Use enet_set_hw_checksum_config() instead of register poke */ #include <rtdevice.h> #ifdef BSP_USING_ETH +#ifdef LWIP_NO_RX_THREAD +#error "LWIP_NO_RX_THREAD is not supported in current implementation!" +#endif #include <rtdbg.h> +#include "rtconfig.h" #include "drv_enet.h" #include "hpm_otp_drv.h" +#if defined(LWIP_PTP) && LWIP_PTP +#include "lwip_ptp_tx_ts.h" +#include "hpm_soc.h" +#endif + #ifdef BSP_USING_ETH0 -/* cppcheck-suppress-begin unknownMacro */ ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) __RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT]; /* Ethernet0 Rx DMA Descriptor */ @@ -31,7 +43,6 @@ __RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */ -/* cppcheck-suppress-end unknownMacro */ LWIP_MEMPOOL_DECLARE(enet0_rx_pool, ENET0_RX_BUFF_COUNT, sizeof(my_custom_pbuf_t), "Custom RX PBUF pool"); static enet_frame_t enet0_frame[ENET0_RX_BUFF_COUNT] = {0}; @@ -50,10 +61,7 @@ static enet_buff_config_t enet0_tx_buff_cfg = {.buffer = (uint32_t)enet0_tx_buff #if defined(__USE_ENET_PTP) && __USE_ENET_PTP static enet_ptp_ts_update_t ptp_timestamp0 = {0, 0}; -static enet_ptp_config_t ptp_config0 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, - .update_method = enet_ptp_time_fine_update, - .addend = 0xffffffff, - }; +static enet_ptp_config_t ptp_config0 = {.update_method = enet_ptp_time_fine_update}; #endif static hpm_enet_t enet0 = {.name = "E0", @@ -90,7 +98,6 @@ mac_init_t mac_init[] = { #ifdef BSP_USING_ETH1 -/* cppcheck-suppress-begin unknownMacro */ ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) __RW enet_rx_desc_t enet1_dma_rx_desc_tab[ENET1_RX_BUFF_COUNT]; /* Ethernet1 Rx DMA Descriptor */ @@ -102,7 +109,6 @@ __RW uint8_t enet1_rx_buff[ENET1_RX_BUFF_COUNT][ENET1_RX_BUFF_SIZE]; /* Ethernet ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet1_tx_buff[ENET1_TX_BUFF_COUNT][ENET1_TX_BUFF_SIZE]; /* Ethernet1 Transmit Buffer */ -/* cppcheck-suppress-end unknownMacro */ LWIP_MEMPOOL_DECLARE(enet1_rx_pool, ENET1_RX_BUFF_COUNT, sizeof(my_custom_pbuf_t), "Custom RX PBUF pool"); static enet_frame_t enet1_frame[ENET1_RX_BUFF_COUNT] = {0}; @@ -121,10 +127,7 @@ static enet_buff_config_t enet1_tx_buff_cfg = {.buffer = (uint32_t)enet1_tx_buff #if defined(__USE_ENET_PTP) && __USE_ENET_PTP static enet_ptp_ts_update_t ptp_timestamp1 = {0, 0}; -static enet_ptp_config_t ptp_config1 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, - .update_method = enet_ptp_time_fine_update, - .addend = 0xffffffff, - }; +static enet_ptp_config_t ptp_config1 = {.update_method = enet_ptp_time_fine_update}; #endif static hpm_enet_t enet1 = {.name = "E1", @@ -182,7 +185,7 @@ void free_rx_dma_descriptor(void *p) /* Clear Segment_Count */ frame->seg = 0; - frame->free = 0; + frame->used = 0; } #ifdef BSP_USING_ETH0 @@ -252,12 +255,14 @@ ATTR_WEAK uint8_t enet_get_mac_address(ENET_Type *ptr, uint8_t *mac) } /* load MAC address from MACRO definitions */ - memcpy(mac, &mac_init[i], ENET_MAC); + memcpy(mac, &mac_init[i], ENET_MAC_SIZE); return ENET_MAC_ADDR_FROM_MACRO; } static rt_err_t hpm_enet_init(enet_device *init) { + enet_hw_checksum_config_t hw_cksum_cfg; + if (init->media_interface == enet_inf_rmii) { /* Initialize reference clock */ @@ -277,6 +282,15 @@ static rt_err_t hpm_enet_init(enet_device *init) /* Initialize eth controller */ enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config); + enet_get_default_tx_control_config(init->instance, &init->desc.tx_control_config); + +#ifdef RT_LWIP_USING_HW_CHECKSUM + enet_get_default_hw_checksum_config(&hw_cksum_cfg, true); +#else + enet_get_default_hw_checksum_config(&hw_cksum_cfg, false); +#endif + enet_set_hw_checksum_config(init->instance, &init->desc.tx_control_config, &hw_cksum_cfg); + /* Disable LPI interrupt */ enet_disable_lpi_interrupt(init->instance); @@ -284,12 +298,8 @@ static rt_err_t hpm_enet_init(enet_device *init) /* initialize PTP Clock */ board_init_enet_ptp_clock(init->instance); - /* initialize Ethernet PTP Module */ - init->ptp_config.ssinc = ENET_ONE_SEC_IN_NANOSEC / clock_get_frequency(init->ptp_clk_src); + /* initialize ptp timer, the config is prepared in rt_hw_eth_init() */ enet_init_ptp(init->instance, &init->ptp_config); - - /* set the initial timestamp */ - enet_set_ptp_timestamp(init->instance, &init->ptp_timestamp); #endif /* enable irq */ @@ -300,7 +310,7 @@ static rt_err_t hpm_enet_init(enet_device *init) static rt_err_t rt_hpm_eth_init(rt_device_t dev) { - uint8_t mac[ENET_MAC]; + uint8_t mac[ENET_MAC_SIZE]; enet_device *enet_dev = (enet_device *)dev->user_data; @@ -362,7 +372,7 @@ static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args) if (args != NULL) { enet_get_mac_address(enet_dev->instance, (uint8_t *)mac); - SMEMCPY(args, mac, ENET_MAC); + SMEMCPY(args, mac, ENET_MAC_SIZE); } else { @@ -463,7 +473,30 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) LOG_D("The length of the transmitted frame: %d\n", frame_length); frame_length += 4; - status = enet_prepare_transmission_descriptors(enet_dev->instance, &enet_dev->desc.tx_desc_list_cur, frame_length, enet_dev->desc.tx_buff_cfg.size); +#if defined(LWIP_PTP) && LWIP_PTP + { + enet_ptp_ts_system_t timestamp; + enet_tx_control_config_t tx_cfg = enet_dev->desc.tx_control_config; + + tx_cfg.enable_ttse = lwip_ptp_frame_needs_tx_hw_timestamp(p); + status = enet_prepare_tx_desc_with_ts_record(enet_dev->instance, + &enet_dev->desc.tx_desc_list_cur, + &tx_cfg, + frame_length, + enet_dev->desc.tx_buff_cfg.size, + ×tamp); + if (tx_cfg.enable_ttse) { + p->time_sec = timestamp.sec; + p->time_nsec = timestamp.nsec; + } + } +#else + status = enet_prepare_tx_desc(enet_dev->instance, + &enet_dev->desc.tx_desc_list_cur, + &enet_dev->desc.tx_control_config, + frame_length, + enet_dev->desc.tx_buff_cfg.size); +#endif if (status != ENET_SUCCESS) { LOG_E("Ethernet controller transmit unsuccessfully: %d\n", status); @@ -486,8 +519,8 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) uint32_t i = 0; /* Get a received frame */ - RT_ASSERT(!enet_dev->frame[enet_dev->cnt].free); - if (enet_dev->frame[enet_dev->cnt].free == 0) { + RT_ASSERT(!enet_dev->frame[enet_dev->cnt].used); + if (enet_dev->frame[enet_dev->cnt].used == 0) { enet_dev->frame[enet_dev->cnt] = enet_get_received_frame_interrupt(&enet_dev->desc.rx_desc_list_cur, &enet_dev->desc.rx_frame_info, enet_dev->desc.rx_buff_cfg.count); } else { return p; @@ -500,7 +533,7 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) if (len > 0) { - enet_dev->frame[enet_dev->cnt].free = 1; + enet_dev->frame[enet_dev->cnt].used = 1; #ifdef BSP_USING_ETH0 if (enet_dev->instance == HPM_ENET0) { @@ -508,6 +541,16 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) my_pbuf->p.custom_free_function = enet0_pbuf_free_custom; my_pbuf->dma_descriptor = (void *)&enet_dev->frame[enet_dev->cnt]; p = pbuf_alloced_custom(PBUF_RAW, enet_dev->frame[enet_dev->cnt].length, PBUF_REF, &my_pbuf->p, buffer, enet_dev->desc.rx_buff_cfg.size); +#if defined(LWIP_PTP) && LWIP_PTP + if (p != NULL) { + enet_rx_desc_t *rx_desc = enet_dev->frame[enet_dev->cnt].rx_desc; + + if (rx_desc != NULL) { + p->time_sec = rx_desc->rdes7_bm.rtsh; + p->time_nsec = rx_desc->rdes6_bm.rtsl; + } + } +#endif enet_dev->cnt = ++enet_dev->cnt % enet_dev->desc.rx_buff_cfg.count; } #endif @@ -518,6 +561,16 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) my_pbuf->p.custom_free_function = enet1_pbuf_free_custom; my_pbuf->dma_descriptor = (void *)&enet_dev->frame[enet_dev->cnt]; p = pbuf_alloced_custom(PBUF_RAW, enet_dev->frame[enet_dev->cnt].length, PBUF_REF, &my_pbuf->p, buffer, enet_dev->desc.rx_buff_cfg.size); +#if defined(LWIP_PTP) && LWIP_PTP + if (p != NULL) { + enet_rx_desc_t *rx_desc = enet_dev->frame[enet_dev->cnt].rx_desc; + + if (rx_desc != NULL) { + p->time_sec = rx_desc->rdes7_bm.rtsh; + p->time_nsec = rx_desc->rdes6_bm.rtsl; + } + } +#endif enet_dev->cnt = ++enet_dev->cnt % enet_dev->desc.rx_buff_cfg.count; } #endif @@ -541,22 +594,42 @@ static void eth_rx_callback(struct eth_device* dev) } } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void isr_enet(hpm_enet_t *obj) +#else +void isr_enet(int vector, hpm_enet_t *obj) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { uint32_t status; + uint32_t rxgbfrmis; + uint32_t intr_status; + ENET_Type *ptr = obj->base; - status = obj->base->DMA_STATUS; + status = ptr->DMA_STATUS; + rxgbfrmis = ptr->MMC_INTR_RX; + intr_status = ptr->INTR_STATUS; if (ENET_DMA_STATUS_GLPII_GET(status)) { - (void)obj->base->LPI_CSR; + /* read LPI_CSR to clear interrupt status */ + ptr->LPI_CSR; + } + + if (ENET_INTR_STATUS_RGSMIIIS_GET(intr_status)) { + /* read XMII_CSR to clear interrupt status */ + ptr->XMII_CSR; } if (ENET_DMA_STATUS_RI_GET(status)) { - obj->base->DMA_STATUS |= ENET_DMA_STATUS_RI_SET(ENET_DMA_STATUS_RI_GET(status)); eth_rx_callback(obj->eth_dev); + ptr->DMA_STATUS |= ENET_DMA_STATUS_RI_MASK; + } + + if (ENET_MMC_INTR_RX_RXCTRLFIS_GET(rxgbfrmis)) { + ptr->RXFRAMECOUNT_GB; } } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK #ifdef BSP_USING_ETH0 SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0) void isr_enet0(void) @@ -572,6 +645,7 @@ void isr_enet1(void) isr_enet(&enet1); } #endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ int rt_hw_eth_init(void) { @@ -591,10 +665,8 @@ int rt_hw_eth_init(void) memset((uint8_t *)s_geths[i]->dma_rx_desc_tab, 0x00, sizeof(enet_rx_desc_t) * s_geths[i]->rx_buff_cfg->count); memset((uint8_t *)s_geths[i]->dma_tx_desc_tab, 0x00, sizeof(enet_tx_desc_t) * s_geths[i]->tx_buff_cfg->count); - memset((uint8_t *)s_geths[i]->rx_buff_cfg->buffer, 0x00, - s_geths[i]->rx_buff_cfg->count * s_geths[i]->rx_buff_cfg->size); - memset((uint8_t *)s_geths[i]->tx_buff_cfg->buffer, 0x00, - s_geths[i]->tx_buff_cfg->count * s_geths[i]->tx_buff_cfg->size); + memset((uint8_t *)s_geths[i]->rx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->rx_buff_cfg->size)); + memset((uint8_t *)s_geths[i]->tx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->tx_buff_cfg->size)); /* Set list heads */ s_geths[i]->enet_dev->desc.tx_desc_list_head = (enet_tx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)s_geths[i]->dma_tx_desc_tab); @@ -634,8 +706,16 @@ int rt_hw_eth_init(void) #if defined(__USE_ENET_PTP) && __USE_ENET_PTP /* Set PTP function */ s_geths[i]->enet_dev->ptp_clk_src = s_geths[i]->ptp_clk_src; - s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config; s_geths[i]->enet_dev->ptp_timestamp = *s_geths[i]->ptp_timestamp; + + /* Runtime defaults: ssinc is derived from the real PTP clock frequency */ + enet_get_default_ptp_config(s_geths[i]->enet_dev->instance, + clock_get_frequency(s_geths[i]->ptp_clk_src), + &s_geths[i]->enet_dev->ptp_config); + /* Board config overrides the runtime default */ + s_geths[i]->enet_dev->ptp_config.update_method = s_geths[i]->ptp_config->update_method; + /* enet_init_ptp() requires a valid timestamp pointer */ + s_geths[i]->enet_dev->ptp_config.ptp_timestamp = &s_geths[i]->enet_dev->ptp_timestamp; #endif /* Set the irq number */ @@ -658,6 +738,11 @@ int rt_hw_eth_init(void) s_geths[i]->eth_dev->eth_rx = rt_hpm_eth_rx; s_geths[i]->eth_dev->eth_tx = rt_hpm_eth_tx; +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register ENET device to irq table */ + rt_hw_interrupt_install(s_geths[i]->irq_num, (rt_isr_handler_t)isr_enet, s_geths[i], s_geths[i]->name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + err = eth_device_init(s_geths[i]->eth_dev, s_geths[i]->name); if (RT_EOK == err) diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.h b/bsp/hpmicro/libraries/drivers/drv_enet.h index c8137e365d..2985985008 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.h +++ b/bsp/hpmicro/libraries/drivers/drv_enet.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,15 @@ #include <netif/ethernetif.h> #include "hpm_enet_drv.h" #include "board.h" +#include "rtt_board.h" +#include "lwip/sys.h" + +#if defined(LWIP_SUPPORT_CUSTOM_PBUF) && LWIP_SUPPORT_CUSTOM_PBUF +typedef struct my_custom_pbuf { + struct pbuf_custom p; + void *dma_descriptor; +} my_custom_pbuf_t; +#endif typedef enum { ENET_MAC_ADDR_PARA_ERROR = -1, @@ -30,6 +39,7 @@ typedef struct { typedef struct { ENET_Type * instance; + clock_name_t clock_name; enet_desc_t desc; enet_mac_config_t mac_config; uint8_t media_interface; @@ -38,7 +48,9 @@ typedef struct { uint8_t tx_delay; uint8_t rx_delay; enet_int_config_t int_config; -#if __USE_ENET_PTP + enet_frame_t *frame; + int cnt; +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP bool ptp_enable; uint32_t ptp_clk_src; enet_ptp_config_t ptp_config; @@ -62,7 +74,9 @@ typedef struct _hpm_enet uint8_t tx_delay; uint8_t rx_delay; bool int_refclk; -#if __USE_ENET_PTP + enet_frame_t *frame; + int cnt; +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP bool ptp_enable; uint32_t ptp_clk_src; enet_ptp_config_t *ptp_config; @@ -82,15 +96,7 @@ typedef struct _hpm_enet MAC[4] == 0 && \ MAC[5] == 0) -#if ENET_SOC_RGMII_EN -#ifndef ENET0_TX_BUFF_COUNT -#define ENET0_TX_BUFF_COUNT (50U) -#endif -#ifndef ENET0_RX_BUFF_COUNT -#define ENET0_RX_BUFF_COUNT (60U) -#endif -#else #ifndef ENET0_TX_BUFF_COUNT #define ENET0_TX_BUFF_COUNT (10U) #endif @@ -98,14 +104,13 @@ typedef struct _hpm_enet #ifndef ENET0_RX_BUFF_COUNT #define ENET0_RX_BUFF_COUNT (20U) #endif -#endif #ifndef ENET0_RX_BUFF_SIZE -#define ENET0_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#define ENET0_RX_BUFF_SIZE (1536U) #endif #ifndef ENET0_TX_BUFF_SIZE -#define ENET0_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#define ENET0_TX_BUFF_SIZE (1536U) #endif #ifndef ENET1_TX_BUFF_COUNT @@ -113,15 +118,15 @@ typedef struct _hpm_enet #endif #ifndef ENET1_RX_BUFF_COUNT -#define ENET1_RX_BUFF_COUNT (30U) +#define ENET1_RX_BUFF_COUNT (20U) #endif #ifndef ENET1_RX_BUFF_SIZE -#define ENET1_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#define ENET1_RX_BUFF_SIZE (1536U) #endif #ifndef ENET1_TX_BUFF_SIZE -#define ENET1_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#define ENET1_TX_BUFF_SIZE (1536U) #endif #ifndef MAC0_ADDR0 diff --git a/bsp/hpmicro/libraries/drivers/drv_enet_phy.c b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c index 0e809a2564..d30afbdb0e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet_phy.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c @@ -7,6 +7,7 @@ * Date Author Notes * 2023-12-20 Jiading Optimization for all-in-one version * 2024-04-17 Jiading Support multiple PHYs + * 2026-09-28 Jiading Wait for enet_phy_speed_valid before announcing link-up */ #include "rtthread.h" @@ -18,12 +19,13 @@ #ifdef RT_USING_PHY #include <rtdevice.h> #include <rtdbg.h> -#include "hpm_enet_drv.h" +#include "drv_enet.h" #include "drv_enet_phy.h" #include "hpm_enet_phy.h" #include "hpm_soc.h" #include "netif/ethernetif.h" #include "board.h" +#include "hpm_enet_drv.h" typedef struct { @@ -117,9 +119,9 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr { rtl8211_config_t phy_config; - rtl8211_reset((ENET_Type *)object); + rtl8211_reset((ENET_Type *)object, RTL8211_ADDR); rtl8211_basic_mode_default_config((ENET_Type *)object, &phy_config); - if (rtl8211_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + if (rtl8211_basic_mode_init((ENET_Type *)object, RTL8211_ADDR, &phy_config) == true) { return PHY_STATUS_OK; } else { return PHY_STATUS_FAIL; @@ -131,10 +133,11 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr if ((ENET_Type *)object == HPM_ENET0) { rtl8201_config_t phy_config; - - rtl8201_reset((ENET_Type *)object); + rtl8201_reset((ENET_Type *)object, RTL8201_ADDR); rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); - if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + phy_config.media_interface = ((enet_device *)eth0_phy_handle.eth_dev->parent.user_data)->media_interface; + phy_config.rmii_refclk_dir = ((enet_device *)eth0_phy_handle.eth_dev->parent.user_data)->int_refclk; + if (rtl8201_basic_mode_init((ENET_Type *)object, RTL8201_ADDR, &phy_config) == true) { return PHY_STATUS_OK; } else { return PHY_STATUS_FAIL; @@ -162,9 +165,11 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr { rtl8201_config_t phy_config; - rtl8201_reset((ENET_Type *)object); + rtl8201_reset((ENET_Type *)object, RTL8201_ADDR); rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); - if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + phy_config.media_interface = ((enet_device *)eth1_phy_handle.eth_dev->parent.user_data)->media_interface; + phy_config.rmii_refclk_dir = ((enet_device *)eth1_phy_handle.eth_dev->parent.user_data)->int_refclk; + if (rtl8201_basic_mode_init((ENET_Type *)object, RTL8201_ADDR, &phy_config) == true) { return PHY_STATUS_OK; } else { return PHY_STATUS_FAIL; @@ -177,20 +182,22 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr { lan8720_config_t phy_config; - lan8720_reset((ENET_Type *)object); + lan8720_reset((ENET_Type *)object, LAN8720_ADDR); lan8720_basic_mode_default_config((ENET_Type *)object, &phy_config); - if (lan8720_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + if (lan8720_basic_mode_init((ENET_Type *)object, LAN8720_ADDR, &phy_config) == true) { return PHY_STATUS_OK; } else { return PHY_STATUS_FAIL; } } #endif + + return PHY_STATUS_FAIL; } static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) { - *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); + enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, (uint16_t *)data); return size; } @@ -202,22 +209,24 @@ static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *d return size; } -static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +static rt_phy_status phy_query_status(rt_phy_t *phy, enet_phy_status_t *phy_status) { - enet_phy_status_t phy_status = {0}; + hpm_stat_t stat = status_fail; + + *phy_status = (enet_phy_status_t){0}; if (phy->bus->hw_obj == HPM_ENET0) { #if defined(__USE_DP83867) && __USE_DP83867 - dp83867_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = dp83867_get_phy_status(phy->bus->hw_obj, DP83867_ADDR, phy_status); #endif #if defined(__USE_RTL8211) && __USE_RTL8211 - rtl8211_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = rtl8211_get_phy_status(phy->bus->hw_obj, RTL8211_ADDR, phy_status); #endif #if defined(__USE_RTL8201) && __USE_RTL8201 && !defined(BSP_USING_ETH1) - rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = rtl8201_get_phy_status(phy->bus->hw_obj, RTL8201_ADDR, phy_status); #endif } @@ -225,59 +234,63 @@ static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) if (phy->bus->hw_obj == HPM_ENET1) { #if defined(__USE_DP83848) && __USE_DP83848 - dp83848_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = dp83848_get_phy_status(phy->bus->hw_obj, DP83848_ADDR, phy_status); #endif #if defined(__USE_RTL8201) && __USE_RTL8201 - rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = rtl8201_get_phy_status(phy->bus->hw_obj, RTL8201_ADDR, phy_status); #endif #if defined(__USE_LAN8720) && __USE_LAN8720 - lan8720_get_phy_status(phy->bus->hw_obj, &phy_status); + stat = lan8720_get_phy_status(phy->bus->hw_obj, LAN8720_ADDR, phy_status); #endif } #endif - *status = phy_status.enet_phy_link; + if (stat != status_success) { + return PHY_STATUS_FAIL; + } return PHY_STATUS_OK; } -static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +static void phy_apply_mac(ENET_Type *instance, const phy_info_t *phy_info) { - enet_phy_status_t phy_status; + enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; - if (phy->bus->hw_obj == HPM_ENET0) - { - #if defined(__USE_DP83867) && __USE_DP83867 - dp83867_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif + if (phy_info->phy_speed >= ARRAY_SIZE(line_speed)) { + return; + } - #if defined(__USE_RTL8211) && __USE_RTL8211 - rtl8211_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif + enet_set_line_speed(instance, line_speed[phy_info->phy_speed]); + enet_set_duplex_mode(instance, phy_info->phy_duplex); +} - #if defined(__USE_RTL8201) && __USE_RTL8201 && !defined(BSP_USING_ETH1) - rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + enet_phy_status_t phy_status; + + if (phy_query_status(phy, &phy_status) != PHY_STATUS_OK) { + *status = RT_FALSE; + return PHY_STATUS_FAIL; } -#if defined(HPM_ENET1_BASE) - if (phy->bus->hw_obj == HPM_ENET1) - { - #if defined(__USE_DP83848) && __USE_DP83848 - dp83848_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif + *status = (phy_status.enet_phy_link == enet_phy_link_up) ? RT_TRUE : RT_FALSE; - #if defined(__USE_RTL8201) && __USE_RTL8201 - rtl8201_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif + return PHY_STATUS_OK; +} - #if defined(__USE_LAN8720) && __USE_LAN8720 - lan8720_get_phy_status(phy->bus->hw_obj, &phy_status); - #endif +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + enet_phy_status_t phy_status; + + if (phy_query_status(phy, &phy_status) != PHY_STATUS_OK) { + return PHY_STATUS_FAIL; + } + + if (!enet_phy_link_up_with_valid_speed(&phy_status)) { + return PHY_STATUS_FAIL; } -#endif *speed = phy_status.enet_phy_speed; *duplex = phy_status.enet_phy_duplex; @@ -289,15 +302,10 @@ static void phy_poll_status(void *parameter) { int ret; phy_info_t phy_info; - rt_bool_t status; - rt_device_t dev; - rt_phy_msg_t msg; - rt_uint32_t speed, duplex; + enet_phy_status_t phy_status; phy_device_t *phy_dev; - struct eth_device* eth_dev; + struct eth_device *eth_dev; char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; - enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; - eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) @@ -305,33 +313,52 @@ static void phy_poll_status(void *parameter) eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; - phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + if (phy_dev->phy.ops == NULL) { + LOG_E("phy.ops is NULL! Please check your initialization of phy.ops in phy_device_register()!\n"); + return; + } - if (status) - { - phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + if (phy_query_status(&phy_dev->phy, &phy_status) != PHY_STATUS_OK) { + continue; + } - ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - if (ret != 0) - { - memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (phy_status.enet_phy_link == enet_phy_link_down) { + if (phy_dev->phy_link != PHY_LINK_DOWN) { + phy_dev->phy_link = PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, RT_FALSE); + LOG_I("%s", phy_dev->phy.bus->hw_obj == HPM_ENET0 ? "ENET0" : "ENET1"); + LOG_I("PHY Status: %s", "Link down\n"); } + continue; } - if (phy_dev->phy_link != status) - { - phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; - eth_device_linkchange(eth_dev, status); - LOG_I("%s", phy_dev->phy.bus->hw_obj == HPM_ENET0 ? "ENET0" : "ENET1"); - LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); - if (status == PHY_LINK_UP) - { + if (!enet_phy_link_up_with_valid_speed(&phy_status)) { + continue; + } + + phy_info.phy_speed = phy_status.enet_phy_speed; + phy_info.phy_duplex = phy_status.enet_phy_duplex; + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (phy_dev->phy_link == PHY_LINK_UP) { + phy_apply_mac(phy_monitor_handle->phy_handle[i]->instance, &phy_dev->phy_info); + LOG_I("%s", phy_dev->phy.bus->hw_obj == HPM_ENET0 ? "ENET0" : "ENET1"); LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); - enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); - enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); } } + + if (phy_dev->phy_link != PHY_LINK_UP) { + phy_dev->phy_link = PHY_LINK_UP; + eth_device_linkchange(eth_dev, RT_TRUE); + LOG_I("%s", phy_dev->phy.bus->hw_obj == HPM_ENET0 ? "ENET0" : "ENET1"); + LOG_I("PHY Status: %s", "Link up"); + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + phy_apply_mac(phy_monitor_handle->phy_handle[i]->instance, &phy_dev->phy_info); + } } } @@ -343,9 +370,6 @@ static void phy_detection(void *parameter) { LOG_E("No any PHY device is detected! Please check your hardware!\n"); } - - return; - } static void phy_monitor_thread_entry(void *args) @@ -372,6 +396,7 @@ int phy_device_register(void) { rt_err_t err = -RT_ERROR; rt_thread_t thread_phy_monitor; + char phy_dev_name[8]={0}; /* Set ops for PHY */ phy_ops.init = phy_init; @@ -383,7 +408,7 @@ int phy_device_register(void) /* Set PHY address */ s_gphys[i]->phy_dev->phy.addr = 0xffff; - /* Set MIDO bus */ + /* Set MDIO bus */ s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; s_gphys[i]->mdio_bus->ops->read = phy_read; @@ -391,7 +416,8 @@ int phy_device_register(void) s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; s_gphys[i]->phy_dev->phy.ops = &phy_ops; - rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, NULL); + sprintf(phy_dev_name, "PHYDev%d", i); + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, phy_dev_name); } /* Start PHY monitor */ @@ -400,6 +426,7 @@ int phy_device_register(void) if (thread_phy_monitor != RT_NULL) { rt_thread_startup(thread_phy_monitor); + err = RT_EOK; } else { diff --git a/bsp/hpmicro/libraries/drivers/drv_ewdt.c b/bsp/hpmicro/libraries/drivers/drv_ewdt.c index 02496c2c36..6cd06aa691 100644 --- a/bsp/hpmicro/libraries/drivers/drv_ewdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_ewdt.c @@ -14,7 +14,6 @@ #include "hpm_sysctl_drv.h" - #ifdef BSP_USING_EWDG #define EWDG_CNT_CLK_FREQ 32768UL @@ -35,83 +34,87 @@ static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt); static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt); static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_wdog_isr(rt_watchdog_t *wdt); +/* Macro to declare watchdog device and ISR handler */ +#define HPM_EWDG_DECLARE_DEVICE_ISR(idx) \ + rt_watchdog_t wdog##idx; \ + SDK_DECLARE_EXT_ISR_M(IRQn_EWDG##idx, wdog##idx##_isr) \ + void wdog##idx##_isr(void) \ + { \ + hpm_wdog_isr(&wdog##idx); \ + } + #if defined(BSP_USING_EWDG0) -rt_watchdog_t wdog0; -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG0, wdog0_isr) -void wdog0_isr(void) -{ - hpm_wdog_isr(&wdog0); -} +HPM_EWDG_DECLARE_DEVICE_ISR(0) #endif #if defined(BSP_USING_EWDG1) -rt_watchdog_t wdog1; -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG1, wdog1_isr) -void wdog1_isr(void) -{ - hpm_wdog_isr(&wdog1); -} +HPM_EWDG_DECLARE_DEVICE_ISR(1) #endif #if defined(BSP_USING_EWDG2) -rt_watchdog_t wdog2; -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG2, wdog2_isr) -void wdog2_isr(void) -{ - hpm_wdog_isr(&wdog2); -} +HPM_EWDG_DECLARE_DEVICE_ISR(2) #endif #if defined(BSP_USING_EWDG3) +HPM_EWDG_DECLARE_DEVICE_ISR(3) +#endif +#else +#ifdef BSP_USING_EWDG0 +rt_watchdog_t wdog0; +#endif +#ifdef BSP_USING_EWDG1 +rt_watchdog_t wdog1; +#endif +#ifdef BSP_USING_EWDG2 +rt_watchdog_t wdog2; +#endif +#ifdef BSP_USING_EWDG3 +rt_watchdog_t wdog3; +#endif +static void hpm_wdog_isr(int vector, rt_watchdog_t *wdt); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +/* Macro to configure watchdog instance */ +#define HPM_EWDG_CONFIG(idx) \ + { \ + .wdog_base = HPM_EWDG##idx, \ + .device_name = "wdt"#idx, \ + .clock_name = clock_watchdog##idx, \ + .irq_num = IRQn_EWDG##idx, \ + .wdog = &wdog##idx, \ + } + +#ifdef BSP_USING_EWDG0 +rt_watchdog_t wdog0; +#endif +#ifdef BSP_USING_EWDG1 +rt_watchdog_t wdog1; +#endif +#ifdef BSP_USING_EWDG2 +rt_watchdog_t wdog2; +#endif +#ifdef BSP_USING_EWDG3 rt_watchdog_t wdog3; -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG3, wdog3_isr) -void wdog3_isr(void) -{ - hpm_wdog_isr(&wdog3); -} #endif static hpm_wdog_t wdogs[] = { #ifdef BSP_USING_EWDG0 - { - .wdog_base = HPM_EWDG0, - .device_name = "wdt0", - .clock_name = clock_watchdog0, - .irq_num = IRQn_EWDG0, - .wdog = &wdog0, - }, + HPM_EWDG_CONFIG(0), #endif #ifdef BSP_USING_EWDG1 - { - .wdog_base = HPM_EWDG1, - .device_name = "wdt1", - .clock_name = clock_watchdog1, - .irq_num = IRQn_EWDG1, - .wdog = &wdog1, - }, + HPM_EWDG_CONFIG(1), #endif #ifdef BSP_USING_EWDG2 - { - .wdog_base = HPM_EWDG2, - .device_name = "wdt2", - .clock_name = clock_watchdog2, - .irq_num = IRQn_EWDG2, - .wdog = &wdog2, - }, + HPM_EWDG_CONFIG(2), #endif #ifdef BSP_USING_EWDG3 - { - .wdog_base = HPM_EWDG3, - .device_name = "wdt3", - .clock_name = clock_watchdog3, - .irq_num = IRQn_EWDG3, - .wdog = &wdog3, - }, + HPM_EWDG_CONFIG(3), #endif }; @@ -154,6 +157,7 @@ static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) rt_enter_critical(); ewdg_enable(base); rt_exit_critical(); + return RT_EOK; } static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) @@ -230,10 +234,14 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) break; } - return RT_EOK; + return ret; } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void hpm_wdog_isr(rt_watchdog_t *wdt) +#else +void hpm_wdog_isr(int vector, rt_watchdog_t *wdt) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; EWDG_Type *base = hpm_wdog->wdog_base; @@ -260,6 +268,10 @@ int rt_hw_wdt_init(void) { LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err); } +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register EWDT device to irq table */ + rt_hw_interrupt_install(wdogs[i].irq_num, (rt_isr_handler_t)hpm_wdog_isr, &wdogs[i], wdogs[i].device_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } #endif return err; diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c index 663e7918cf..043822b651 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.c +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -1,8 +1,23 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * + * @file drv_gpio.c + * @brief GPIO driver implementation for RT-Thread + * + * This file implements the GPIO (General Purpose Input/Output) driver for HPMicro + * microcontrollers, providing a complete interface between RT-Thread's pin framework + * and the HPM GPIO hardware. + * + * Features: + * - Support for multiple GPIO ports (A, B, C, D, E, F, V, W, X, Y, Z) + * - Configurable pin modes (input, output, pull-up, pull-down, open-drain) + * - Interrupt-driven GPIO operations with configurable triggers + * - Pin naming convention: P<PORT><INDEX> (e.g., PA00, PZ03) + * - Configurable interrupt priorities + * - Real-time pin state monitoring + * * Change Logs: * Date Author Notes * 2022-01-11 HPMicro First version @@ -11,202 +26,235 @@ * 2023-08-15 HPMicro Enable pad loopback feature * 2024-01-08 HPMicro Implemented pin_get * 2024-04-17 HPMicro Refined pin irq implementation - * 2024-05-31 HPMicro Adapt later PIN driver framework * 2024-07-03 HPMicro Determined the existence of GPIO via GPIO_DO_GPIOx macro + * 2025-09-01 HPMicro Revised the code, reduced repetitive codes, added comments + * 2025-12-04 HPMicro Changed the return type of hpm_pin_read from int to rt_ssize_t */ -#include <rtthread.h> +#include "rtconfig.h" #ifdef BSP_USING_GPIO + +/* RT-Thread includes */ #include <rthw.h> #include <rtdevice.h> + +/* HPM SDK includes */ #include "drv_gpio.h" #include "hpm_gpio_drv.h" #include "hpm_gpiom_drv.h" #include "hpm_clock_drv.h" #include "hpm_soc_feature.h" +#include <rtthread.h> +#include "hpm_soc.h" + +/* ============================================================================ + * Configuration Macros + * ============================================================================ */ + +/* + * GPIO Pin Interrupt Header Declaration Macro + * Creates a static array of pin interrupt headers for a specific GPIO port. + * Each GPIO port can have up to 32 pins, each with its own interrupt handler. + * + * @param port GPIO port letter (A, B, C, D, E, F, V, W, X, Y, Z) + */ +#define GPIO_PIN_HDR_DECLARE(port) \ + static struct rt_pin_irq_hdr hpm_gpio0_##port##_pin_hdr[32] + +/* + * GPIO Interrupt Priority Configuration Macro + * Handles the configuration of interrupt priority for GPIO controllers. + * If a specific priority is defined in the board configuration, it will be used; + * otherwise, a default priority of 1 is applied. + */ +#ifdef BSP_GPIO_IRQ_PRIORITY +#define GPIO_IRQ_PRIORITY_VAL BSP_GPIO_IRQ_PRIORITY +#else +#define GPIO_IRQ_PRIORITY_VAL 1 +#endif + +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +/* + * GPIO Interrupt Mapping Entry Macro + * Creates an entry in the GPIO interrupt mapping table that associates + * GPIO port indices with their corresponding interrupt numbers, priorities, + * and pin interrupt header tables. + * + * @param port GPIO port letter (A, B, C, D, E, F, V, W, X, Y, Z) + */ +#define GPIO_IRQ_MAP_ENTRY(port) \ + { \ + GPIO_IE_GPIO##port, \ + IRQn_GPIO0_##port, \ + GPIO_IRQ_PRIORITY_VAL, \ + hpm_gpio0_##port##_pin_hdr \ + } + +/* + * GPIO ISR Definition Macro + * Creates the interrupt service routine function and its declaration + * for a specific GPIO port. The ISR handles pin-level interrupts + * and calls the common GPIO interrupt handler. + * + * @param port GPIO port letter (A, B, C, D, E, F, V, W, X, Y, Z) + */ +#define GPIO_ISR_DEFINE(port) \ + SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_##port, gpio##port##_isr) \ + void gpio##port##_isr(void) \ + { \ + hpm_gpio_isr(GPIO_IF_GPIO##port, HPM_GPIO0); \ + } +#else +/** + * @brief GPIO interrupt parameter structure + * + * This structure used for passing parameters to the GPIO interrupt service routine. + */ +typedef struct +{ + uint32_t gpio_idx; /**< GPIO port index (0-11 for A-Z) */ + GPIO_Type *base; +} gpio_irq_param_t; +/* + * GPIO Interrupt Mapping Entry Macro + * Creates an entry in the GPIO interrupt mapping table that associates + * GPIO port indices with their corresponding interrupt numbers, priorities, + * and pin interrupt header tables. + * + * @param port GPIO port letter (A, B, C, D, E, F, V, W, X, Y, Z) + */ +#define GPIO_IRQ_MAP_ENTRY(port) \ + { \ + GPIO_IE_GPIO##port, \ + IRQn_GPIO0_##port, \ + GPIO_IRQ_PRIORITY_VAL, \ + hpm_gpio0_##port##_pin_hdr, \ + &(gpio_irq_param_t){ \ + .gpio_idx = GPIO_IE_GPIO##port, \ + .base = HPM_GPIO0 \ + } \ + } +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +/* ============================================================================ + * Data Structures + * ============================================================================ */ +/** + * @brief GPIO interrupt mapping structure + * + * This structure maps GPIO port indices to their corresponding interrupt + * configuration and pin interrupt handler tables. + */ typedef struct { - uint32_t gpio_idx; - uint32_t irq_num; - uint8_t irq_priority; - struct rt_pin_irq_hdr *pin_irq_tbl; + uint32_t gpio_idx; /**< GPIO port index (0-11 for A-Z) */ + uint32_t irq_num; /**< Interrupt number for this GPIO port */ + uint8_t irq_priority; /**< Interrupt priority for this GPIO port */ + struct rt_pin_irq_hdr *pin_irq_tbl; /**< Pointer to pin interrupt handler table */ +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + gpio_irq_param_t *irq_param; /**< Pointer to GPIO interrupt parameter structure */ +#endif } gpio_irq_map_t; +/* ============================================================================ + * GPIO Device Instances + * ============================================================================ */ + +/* GPIO Pin Interrupt Header Declarations - created for each enabled GPIO port */ #ifdef GPIO_DO_GPIOA -static struct rt_pin_irq_hdr hpm_gpio0_a_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(A); #endif #ifdef GPIO_DO_GPIOB -static struct rt_pin_irq_hdr hpm_gpio0_b_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(B); #endif #ifdef GPIO_DO_GPIOC -static struct rt_pin_irq_hdr hpm_gpio0_c_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(C); #endif #ifdef GPIO_DO_GPIOD -static struct rt_pin_irq_hdr hpm_gpio0_d_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(D); #endif #ifdef GPIO_DO_GPIOE -static struct rt_pin_irq_hdr hpm_gpio0_e_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(E); #endif #ifdef GPIO_DO_GPIOF -static struct rt_pin_irq_hdr hpm_gpio0_f_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(F); #endif #ifdef GPIO_DO_GPIOV -static struct rt_pin_irq_hdr hpm_gpio0_v_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(V); #endif #ifdef GPIO_DO_GPIOW -static struct rt_pin_irq_hdr hpm_gpio0_w_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(W); #endif #ifdef GPIO_DO_GPIOX -static struct rt_pin_irq_hdr hpm_gpio0_x_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(X); #endif #ifdef GPIO_DO_GPIOY -static struct rt_pin_irq_hdr hpm_gpio0_y_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(Y); #endif #ifdef GPIO_DO_GPIOZ -static struct rt_pin_irq_hdr hpm_gpio0_z_pin_hdr[32]; +GPIO_PIN_HDR_DECLARE(Z); #endif +/* GPIO Interrupt Mapping Table - maps GPIO ports to their interrupt configuration */ static const gpio_irq_map_t hpm_gpio_irq_map[] = { #ifdef GPIO_DO_GPIOA - { - GPIO_IE_GPIOA, - IRQn_GPIO0_A, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_a_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(A), #endif #ifdef GPIO_DO_GPIOB - { - GPIO_IE_GPIOB, - IRQn_GPIO0_B, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_b_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(B), #endif #ifdef GPIO_DO_GPIOC - { - GPIO_IE_GPIOC, - IRQn_GPIO0_C, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_c_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(C), #endif #ifdef GPIO_DO_GPIOD - { - GPIO_IE_GPIOD, - IRQn_GPIO0_D, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_d_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(D), #endif #ifdef GPIO_DO_GPIOE - { - GPIO_IE_GPIOE, - IRQn_GPIO0_E, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_e_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(E), #endif #ifdef GPIO_DO_GPIOF - { - GPIO_IE_GPIOF, - IRQn_GPIO0_F, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_f_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(F), #endif #ifdef GPIO_DO_GPIOV - { - GPIO_IE_GPIOV, - IRQn_GPIO0_V, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_v_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(V), #endif #ifdef GPIO_DO_GPIOW - { - GPIO_IE_GPIOW, - IRQn_GPIO0_W, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_w_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(W), #endif #ifdef GPIO_DO_GPIOX - { - GPIO_IE_GPIOX, - IRQn_GPIO0_X, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_x_pin_hdr }, + GPIO_IRQ_MAP_ENTRY(X), #endif #ifdef GPIO_DO_GPIOY - { - GPIO_IE_GPIOY, - IRQn_GPIO0_Y, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_y_pin_hdr - }, + GPIO_IRQ_MAP_ENTRY(Y), #endif #ifdef GPIO_DO_GPIOZ - { - GPIO_IE_GPIOZ, - IRQn_GPIO0_Z, -#if defined(BSP_GPIO_IRQ_PRIORITY) - BSP_GPIO_IRQ_PRIORITY, -#else - 1, -#endif - hpm_gpio0_z_pin_hdr }, + GPIO_IRQ_MAP_ENTRY(Z), #endif }; +/* ============================================================================ + * Function Implementations + * ============================================================================ */ + +/** + * @brief Lookup pin interrupt header table for a given pin + * + * This function finds the appropriate pin interrupt header table for a given + * pin number by extracting the GPIO port index and searching the interrupt + * mapping table. + * + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @return Pointer to pin interrupt header table, or RT_NULL if not found + */ static struct rt_pin_irq_hdr *lookup_pin_irq_hdr_tbl(rt_base_t pin) { struct rt_pin_irq_hdr *pin_irq_hdr_tbl = RT_NULL; - uint32_t gpio_idx = pin >> 5; + uint32_t gpio_idx = pin >> 5; /* Extract GPIO port index (upper bits) */ + /* Search through the GPIO interrupt mapping table */ for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) { if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) @@ -218,10 +266,20 @@ static struct rt_pin_irq_hdr *lookup_pin_irq_hdr_tbl(rt_base_t pin) return pin_irq_hdr_tbl; } +/** + * @brief Get interrupt number for a GPIO port + * + * This function retrieves the interrupt number associated with a specific + * GPIO port index by searching the interrupt mapping table. + * + * @param [in] gpio_idx GPIO port index (0-11 for A-Z) + * @return Interrupt number, or -1 if not found + */ static int hpm_get_gpio_irq_num(uint32_t gpio_idx) { int irq_num = -1; + /* Search through the GPIO interrupt mapping table */ for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) { if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) @@ -233,10 +291,20 @@ static int hpm_get_gpio_irq_num(uint32_t gpio_idx) return irq_num; } +/** + * @brief Get interrupt priority for a GPIO port + * + * This function retrieves the interrupt priority associated with a specific + * GPIO port index by searching the interrupt mapping table. + * + * @param [in] gpio_idx GPIO port index (0-11 for A-Z) + * @return Interrupt priority, or -1 if not found + */ static int hpm_get_gpio_irq_priority(uint32_t gpio_idx) { int irq_priority = -1; + /* Search through the GPIO interrupt mapping table */ for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) { if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) @@ -248,9 +316,28 @@ static int hpm_get_gpio_irq_priority(uint32_t gpio_idx) return irq_priority; } +/** + * @brief GPIO interrupt service routine + * + * This function is called when a GPIO interrupt occurs. It handles pin-level + * interrupts by checking which pins have triggered interrupts, clearing the + * interrupt flags, and calling the appropriate user-defined interrupt handlers. + * + * @param [in] gpio_idx GPIO port index that triggered the interrupt + * @param [in] base GPIO hardware base address + */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) +#else +static void hpm_gpio_isr(int vector, gpio_irq_param_t *param) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { - /* Lookup the Pin IRQ Header Table */ +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + uint32_t gpio_idx = param->gpio_idx; + GPIO_Type *base = param->base; +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + /* Lookup the Pin IRQ Header Table for this GPIO port */ + struct rt_pin_irq_hdr *pin_irq_hdr = RT_NULL; for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) { @@ -261,12 +348,15 @@ static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) } } + /* Check each pin in the GPIO port for interrupt flags */ for(uint32_t pin_idx = 0; pin_idx < 32; pin_idx++) { if (gpio_check_pin_interrupt_flag(base, gpio_idx, pin_idx)) { + /* Clear the interrupt flag for this pin */ gpio_clear_pin_interrupt_flag(base, gpio_idx, pin_idx); + /* Call user-defined interrupt handler if registered */ if (pin_irq_hdr[pin_idx].hdr != RT_NULL) { pin_irq_hdr[pin_idx].hdr(pin_irq_hdr[pin_idx].args); @@ -275,136 +365,143 @@ static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) } } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +/* ============================================================================ + * GPIO Interrupt Service Routines + * ============================================================================ */ + +/* GPIOA ISR - created if GPIO_DO_GPIOA is enabled */ #ifdef GPIO_DO_GPIOA -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr) -void gpioa_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0); -} +GPIO_ISR_DEFINE(A); #endif +/* GPIOB ISR - created if GPIO_DO_GPIOB is enabled */ #ifdef GPIO_DO_GPIOB -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr) -void gpiob_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0); -} +GPIO_ISR_DEFINE(B); #endif +/* GPIOC ISR - created if GPIO_DO_GPIOC is enabled */ #ifdef GPIO_DO_GPIOC -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr) -void gpioc_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0); -} +GPIO_ISR_DEFINE(C); #endif +/* GPIOD ISR - created if GPIO_DO_GPIOD is enabled */ #ifdef GPIO_DO_GPIOD -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr) -void gpiod_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0); -} +GPIO_ISR_DEFINE(D); #endif +/* GPIOE ISR - created if GPIO_DO_GPIOE is enabled */ #ifdef GPIO_DO_GPIOE -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr) -void gpioe_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0); -} +GPIO_ISR_DEFINE(E); #endif +/* GPIOF ISR - created if GPIO_DO_GPIOF is enabled */ #ifdef GPIO_DO_GPIOF -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr) -void gpiof_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0); -} +GPIO_ISR_DEFINE(F); #endif +/* GPIOV ISR - created if GPIO_DO_GPIOV is enabled */ #ifdef GPIO_DO_GPIOV -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_V, gpiox_isr) -void gpiov_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOV, HPM_GPIO0); -} +GPIO_ISR_DEFINE(V); #endif +/* GPIOW ISR - created if GPIO_DO_GPIOW is enabled */ #ifdef GPIO_DO_GPIOW -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_W, gpiox_isr) -void gpiow_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOW, HPM_GPIO0); -} +GPIO_ISR_DEFINE(W); #endif +/* GPIOX ISR - created if GPIO_DO_GPIOX is enabled */ #ifdef GPIO_DO_GPIOX -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr) -void gpiox_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0); -} +GPIO_ISR_DEFINE(X); #endif +/* GPIOY ISR - created if GPIO_DO_GPIOY is enabled */ #ifdef GPIO_DO_GPIOY -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr) -void gpioy_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0); -} +GPIO_ISR_DEFINE(Y); #endif +/* GPIOZ ISR - created if GPIO_DO_GPIOZ is enabled */ #ifdef GPIO_DO_GPIOZ -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr) -void gpioz_isr(void) -{ - hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0); -} +GPIO_ISR_DEFINE(Z); #endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ /** - * @brief Get Pin index from name - * - * Name rule is : <GPIO NAME><Index> - * for example: PA00, PZ03 + * @brief Get Pin index from name string + * + * This function converts a pin name string to a pin index number. + * The pin naming convention follows the pattern: P<PORT><INDEX> + * + * Supported formats: + * - PA00 to PF99: GPIO ports A-F with pin indices 00-99 + * - PV00 to PZ99: GPIO ports V-Z with pin indices 00-99 + * + * Examples: + * - "PA00" -> pin index 0 (GPIO A, pin 0) + * - "PZ03" -> pin index 355 (GPIO Z, pin 3) + * - "PB15" -> pin index 47 (GPIO B, pin 15) * - **/ + * @param [in] name Pin name string (must be exactly 4 characters) + * @return Pin index number, or -RT_EINVAL if name is invalid + */ static rt_base_t hpm_pin_get(const char *name) { - if (!( (rt_strlen(name) == 4) && - (name[0] == 'P') && - ((('A' <= name[1]) && (name[1] <= 'F')) || (('V' <= name[1]) && (name[1] <= 'Z'))) && - (('0' <= name[2]) && (name[2] <= '9')) && - (('0' <= name[3]) && (name[3] <= '9')) + /* Validate pin name format: P<PORT><INDEX> (4 characters total) */ + if (!( (rt_strlen(name) == 4) && /* Exactly 4 characters */ + (name[0] == 'P') && /* First character is 'P' */ + ((('A' <= name[1]) && (name[1] <= 'F')) || /* Port A-F or V-Z */ + (('V' <= name[1]) && (name[1] <= 'Z'))) && + (('0' <= name[2]) && (name[2] <= '9')) && /* Third character is digit */ + (('0' <= name[3]) && (name[3] <= '9')) /* Fourth character is digit */ )) { return -RT_EINVAL; } + /* Calculate GPIO port index */ uint32_t gpio_idx = (name[1] <= 'F') ? (name[1] - 'A') : (11 + name[1] - 'V'); + + /* Calculate pin index within the port */ uint32_t pin_idx = (uint32_t)(name[2] - '0') * 10 + (name[3] - '0'); + + /* Return combined pin index (gpio_idx * 32 + pin_idx) */ return (gpio_idx * 32 + pin_idx); } +/** + * @brief Configure GPIO pin mode + * + * This function configures a GPIO pin for the specified mode, including + * direction (input/output), pull-up/pull-down resistors, and open-drain settings. + * It also configures the pin controller and pad settings. + * + * @param [in] dev Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @param [in] mode Pin mode (PIN_MODE_*) + */ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { /* TODO: Check the validity of the pin value */ - uint32_t gpio_idx = pin >> 5; - uint32_t pin_idx = pin & 0x1FU; + uint32_t gpio_idx = pin >> 5; /* Extract GPIO port index */ + uint32_t pin_idx = pin & 0x1FU; /* Extract pin index within port */ + /* Configure pin controller to use GPIO0 */ gpiom_set_pin_controller(HPM_GPIOM, gpio_idx, pin_idx, gpiom_soc_gpio0); + /* Clear function control register */ HPM_IOC->PAD[pin].FUNC_CTL = 0; + /* Handle special cases for specific GPIO ports */ switch (gpio_idx) { case GPIO_DI_GPIOY : + /* GPIOY requires special PIOC configuration */ HPM_PIOC->PAD[pin].FUNC_CTL = 3; break; #ifdef GPIO_DI_GPIOZ case GPIO_DI_GPIOZ : #ifdef HPM_BIOC + /* GPIOZ requires special BIOC configuration if available */ HPM_BIOC->PAD[pin].FUNC_CTL = 3; #endif break; @@ -413,109 +510,194 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; } + /* Configure pin mode and pad settings */ switch (mode) { case PIN_MODE_OUTPUT: + /* Configure as output with push-pull driver */ gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx); HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_OD_MASK); break; + case PIN_MODE_INPUT: + /* Configure as input with no pull resistors */ gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK); break; + case PIN_MODE_INPUT_PULLDOWN: + /* Configure as input with pull-down resistor */ gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~IOC_PAD_PAD_CTL_PS_MASK) | IOC_PAD_PAD_CTL_PE_SET(1); break; + case PIN_MODE_INPUT_PULLUP: + /* Configure as input with pull-up resistor */ gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); HPM_IOC->PAD[pin].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); break; + case PIN_MODE_OUTPUT_OD: + /* Configure as output with open-drain driver */ gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx); HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK)) | IOC_PAD_PAD_CTL_OD_SET(1); break; + default: - /* Invalid mode */ + /* Invalid mode - no action taken */ break; } + + /* Enable pad loopback feature */ HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; } +/** + * @brief Read GPIO pin state + * + * This function reads the current state (high/low) of a GPIO pin. + * + * @param [in] dev Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @return Pin state: 1 for high, 0 for low + */ static rt_ssize_t hpm_pin_read(rt_device_t dev, rt_base_t pin) { /* TODO: Check the validity of the pin value */ - uint32_t gpio_idx = pin >> 5; - uint32_t pin_idx = pin & 0x1FU; + uint32_t gpio_idx = pin >> 5; /* Extract GPIO port index */ + uint32_t pin_idx = pin & 0x1FU; /* Extract pin index within port */ return (rt_ssize_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); } +/** + * @brief Write GPIO pin state + * + * This function sets the output state of a GPIO pin to high or low. + * + * @param [in] dev Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @param [in] value Pin state: 1 for high, 0 for low + */ static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) { /* TODO: Check the validity of the pin value */ - uint32_t gpio_idx = pin >> 5; - uint32_t pin_idx = pin & 0x1FU; + uint32_t gpio_idx = pin >> 5; /* Extract GPIO port index */ + uint32_t pin_idx = pin & 0x1FU; /* Extract pin index within port */ gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value); } +/** + * @brief Attach interrupt handler to GPIO pin + * + * This function registers an interrupt handler for a specific GPIO pin. + * The handler will be called when the pin triggers an interrupt based on + * the specified mode (rising edge, falling edge, high level, low level). + * + * @param [in] device Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @param [in] mode Interrupt mode (PIN_IRQ_MODE_*) + * @param [in] hdr Interrupt handler function pointer + * @param [in] args Arguments to pass to the interrupt handler + * @retval RT_EOK Interrupt handler attached successfully + * @retval -RT_EINVAL Invalid pin number + */ static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args) { + /* Lookup the pin interrupt header table for this pin */ struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); if (pin_irq_hdr_tbl == RT_NULL) { return -RT_EINVAL; } + /* Disable interrupts during registration to ensure atomic operation */ rt_base_t level = rt_hw_interrupt_disable(); - uint32_t pin_idx = pin & 0x1FUL; + uint32_t pin_idx = pin & 0x1FUL; /* Extract pin index within port */ + + /* Register the interrupt handler */ pin_irq_hdr_tbl[pin_idx].pin = pin; pin_irq_hdr_tbl[pin_idx].hdr = hdr; pin_irq_hdr_tbl[pin_idx].mode = mode; pin_irq_hdr_tbl[pin_idx].args = args; + + /* Re-enable interrupts */ rt_hw_interrupt_enable(level); return RT_EOK; } +/** + * @brief Detach interrupt handler from GPIO pin + * + * This function removes the interrupt handler registration for a specific GPIO pin. + * After calling this function, the pin will no longer trigger interrupts. + * + * @param [in] device Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @retval RT_EOK Interrupt handler detached successfully + * @retval -RT_EINVAL Invalid pin number + */ static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_base_t pin) { + /* Lookup the pin interrupt header table for this pin */ struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); if (pin_irq_hdr_tbl == RT_NULL) { return -RT_EINVAL; } + + /* Disable interrupts during deregistration to ensure atomic operation */ rt_base_t level = rt_hw_interrupt_disable(); - uint32_t pin_idx = pin & 0x1FUL; + uint32_t pin_idx = pin & 0x1FUL; /* Extract pin index within port */ + + /* Clear the interrupt handler registration */ pin_irq_hdr_tbl[pin_idx].pin = -1; pin_irq_hdr_tbl[pin_idx].hdr = RT_NULL; pin_irq_hdr_tbl[pin_idx].mode = 0; pin_irq_hdr_tbl[pin_idx].args = RT_NULL; + + /* Re-enable interrupts */ rt_hw_interrupt_enable(level); return RT_EOK; } +/** + * @brief Enable or disable GPIO pin interrupt + * + * This function enables or disables interrupt generation for a specific GPIO pin. + * When enabling, it configures the interrupt trigger mode and enables the hardware + * interrupt. When disabling, it disables the hardware interrupt. + * + * @param [in] device Device pointer (unused) + * @param [in] pin Pin number (encoded as gpio_idx * 32 + pin_idx) + * @param [in] enabled Enable/disable flag (PIN_IRQ_ENABLE or PIN_IRQ_DISABLE) + * @retval RT_EOK Operation completed successfully + * @retval -RT_EINVAL Invalid pin number or enable flag + */ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) { /* TODO: Check the validity of the pin value */ - uint32_t gpio_idx = pin >> 5; - uint32_t pin_idx = pin & 0x1FU; + uint32_t gpio_idx = pin >> 5; /* Extract GPIO port index */ + uint32_t pin_idx = pin & 0x1FU; /* Extract pin index within port */ + /* Lookup the pin interrupt header table for this pin */ struct rt_pin_irq_hdr *pin_irq_hdr_tbl = lookup_pin_irq_hdr_tbl(pin); if (pin_irq_hdr_tbl == RT_NULL) { return -RT_EINVAL; } - gpio_interrupt_trigger_t trigger; if (enabled == PIN_IRQ_ENABLE) { + /* Configure interrupt trigger mode based on registered mode */ + gpio_interrupt_trigger_t trigger; switch(pin_irq_hdr_tbl[pin_idx].mode) { case PIN_IRQ_MODE_RISING: @@ -534,14 +716,21 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u trigger = gpio_interrupt_trigger_edge_rising; break; } + + /* Configure and enable the pin interrupt */ gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger); + + /* Get interrupt number and priority for this GPIO port */ rt_uint32_t irq_num = hpm_get_gpio_irq_num(gpio_idx); rt_uint32_t irq_priority = hpm_get_gpio_irq_priority(gpio_idx); + + /* Enable pin interrupt and system interrupt */ gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); intc_m_enable_irq_with_priority(irq_num, irq_priority); } else if (enabled == PIN_IRQ_DISABLE) { + /* Disable the pin interrupt */ gpio_disable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); } else @@ -552,25 +741,54 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u return RT_EOK; } +/* ============================================================================ + * RT-Thread Interface Structures + * ============================================================================ */ + +/* RT-Thread pin operations structure - defines the interface between RT-Thread and this driver */ const static struct rt_pin_ops hpm_pin_ops = { - .pin_mode = hpm_pin_mode, - .pin_write = hpm_pin_write, - .pin_read = hpm_pin_read, - .pin_attach_irq = hpm_pin_attach_irq, - .pin_detach_irq = hpm_pin_detach_irq, - .pin_irq_enable = hpm_pin_irq_enable, - .pin_get = hpm_pin_get, + .pin_mode = hpm_pin_mode, /* Configure pin mode */ + .pin_write = hpm_pin_write, /* Write pin state */ + .pin_read = hpm_pin_read, /* Read pin state */ + .pin_attach_irq = hpm_pin_attach_irq, /* Attach interrupt handler */ + .pin_detach_irq = hpm_pin_detach_irq, /* Detach interrupt handler */ + .pin_irq_enable = hpm_pin_irq_enable, /* Enable/disable interrupt */ + .pin_get = hpm_pin_get, /* Get pin index from name */ }; +/* ============================================================================ + * Driver Initialization + * ============================================================================ */ + +/** + * @brief Initialize GPIO driver + * + * This function initializes the GPIO driver and registers it with the + * RT-Thread device framework. It sets up the pin operations structure + * and makes the GPIO functionality available to the system. + * + * @retval RT_EOK Initialization successful + * @retval -RT_ERROR Initialization failed + */ int rt_hw_pin_init(void) { int ret = RT_EOK; + /* Register the pin device with RT-Thread */ ret = rt_device_pin_register("pin", &hpm_pin_ops, RT_NULL); +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) + { + /* Register GPIO device to irq table */ + rt_hw_interrupt_install(hpm_gpio_irq_map[i].irq_num, (rt_isr_handler_t)hpm_gpio_isr, hpm_gpio_irq_map[i].irq_param, "GPIO"); + } +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + return ret; } +/* Register initialization function to be called during system startup */ INIT_BOARD_EXPORT(rt_hw_pin_init); #endif /* BSP_USING_GPIO */ diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.c b/bsp/hpmicro/libraries/drivers/drv_i2c.c index 15481ca8c0..d55e2f732c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2c.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2024 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,10 +12,9 @@ #include "drv_i2c.h" #include "hpm_i2c_drv.h" #include "hpm_dma_mgr.h" -#include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" #include "board.h" - +#include "hpm_dmamux_drv.h" #ifdef RT_USING_I2C @@ -31,7 +30,8 @@ struct hpm_i2c I2C_Type *base; clock_name_t clk_name; char *bus_name; - rt_sem_t xfer_sem; + rt_sem_t i2c_xfer_sem; + rt_sem_t dma_xfer_sem; rt_bool_t enable_dma; rt_uint8_t dmamux; dma_resource_t dma; @@ -40,158 +40,174 @@ struct hpm_i2c rt_uint8_t irq_priority; }; -static struct hpm_i2c hpm_i2cs[] = -{ -#if defined(BSP_USING_I2C0) - { - .base = HPM_I2C0, - .bus_name = "i2c0", - .clk_name = clock_i2c0, +/* Macros to reduce repetitive I2C configuration code */ +#define HPM_I2C_CONFIG(idx) \ + { \ + .base = HPM_I2C##idx, \ + .bus_name = "i2c"#idx, \ + .clk_name = clock_i2c##idx, \ + HPM_I2C_DMA_CONFIG_##idx \ + .dmamux = HPM_DMA_SRC_I2C##idx, \ + .i2c_irq = IRQn_I2C##idx, \ + HPM_I2C_IRQ_PRIORITY_##idx \ + } + +/* DMA configuration per instance */ #if defined(BSP_I2C0_USING_DMA) - .enable_dma = RT_TRUE, -#endif - .dmamux = HPM_DMA_SRC_I2C0, - .i2c_irq = IRQn_I2C0, -#if defined(BSP_I2C0_IRQ_PRIORITY) - .irq_priority = BSP_I2C0_IRQ_PRIORITY, +#define HPM_I2C_DMA_CONFIG_0 .enable_dma = RT_TRUE, #else - .irq_priority = 1, -#endif - }, +#define HPM_I2C_DMA_CONFIG_0 .enable_dma = RT_FALSE, #endif -#if defined(BSP_USING_I2C1) - { - .base = HPM_I2C1, - .bus_name = "i2c1", - .clk_name = clock_i2c1, + #if defined(BSP_I2C1_USING_DMA) - .enable_dma = RT_TRUE, +#define HPM_I2C_DMA_CONFIG_1 .enable_dma = RT_TRUE, +#else +#define HPM_I2C_DMA_CONFIG_1 #endif - .dmamux = HPM_DMA_SRC_I2C1, - .i2c_irq = IRQn_I2C1, -#if defined(BSP_I2C1_IRQ_PRIORITY) - .irq_priority = BSP_I2C1_IRQ_PRIORITY, + +#if defined(BSP_I2C2_USING_DMA) +#define HPM_I2C_DMA_CONFIG_2 .enable_dma = RT_TRUE, #else - .irq_priority = 1, +#define HPM_I2C_DMA_CONFIG_2 .enable_dma = RT_FALSE, #endif - }, + +#if defined(BSP_I2C3_USING_DMA) +#define HPM_I2C_DMA_CONFIG_3 .enable_dma = RT_TRUE, +#else +#define HPM_I2C_DMA_CONFIG_3 .enable_dma = RT_FALSE, #endif -#if defined(BSP_USING_I2C2) - { - .base = HPM_I2C2, - .bus_name = "i2c2", - .clk_name = clock_i2c2, -#if defined(BSP_I2C2_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_I2C4_USING_DMA) +#define HPM_I2C_DMA_CONFIG_4 .enable_dma = RT_TRUE, +#else +#define HPM_I2C_DMA_CONFIG_4 #endif - .dmamux = HPM_DMA_SRC_I2C2, - .i2c_irq = IRQn_I2C2, -#if defined(BSP_I2C2_IRQ_PRIORITY) - .irq_priority = BSP_I2C2_IRQ_PRIORITY, + +#if defined(BSP_I2C5_USING_DMA) +#define HPM_I2C_DMA_CONFIG_5 .enable_dma = RT_TRUE, #else - .irq_priority = 1, +#define HPM_I2C_DMA_CONFIG_5 .enable_dma = RT_FALSE, #endif - }, + +#if defined(BSP_I2C6_USING_DMA) +#define HPM_I2C_DMA_CONFIG_6 .enable_dma = RT_TRUE, +#else +#define HPM_I2C_DMA_CONFIG_6 .enable_dma = RT_FALSE, #endif -#if defined(BSP_USING_I2C3) - { - .base = HPM_I2C3, - .bus_name = "i2c3", - .clk_name = clock_i2c3, -#if defined(BSP_I2C3_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_I2C7_USING_DMA) +#define HPM_I2C_DMA_CONFIG_7 .enable_dma = RT_TRUE, +#else +#define HPM_I2C_DMA_CONFIG_7 #endif - .dmamux = HPM_DMA_SRC_I2C3, - .i2c_irq = IRQn_I2C3, -#if defined(BSP_I2C3_IRQ_PRIORITY) - .irq_priority = BSP_I2C3_IRQ_PRIORITY, + +/* IRQ priority configuration per instance */ +#if defined(BSP_I2C0_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_0 .irq_priority = BSP_I2C0_IRQ_PRIORITY, #else - .irq_priority = 1, +#define HPM_I2C_IRQ_PRIORITY_0 .irq_priority = 1, #endif - }, + +#if defined(BSP_I2C1_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_1 .irq_priority = BSP_I2C1_IRQ_PRIORITY, +#else +#define HPM_I2C_IRQ_PRIORITY_1 .irq_priority = 1, #endif -#if defined(BSP_USING_I2C4) - { - .base = HPM_I2C4, - .bus_name = "i2c4", - .clk_name = clock_i2c4, -#if defined(BSP_I2C4_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_I2C2_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_2 .irq_priority = BSP_I2C2_IRQ_PRIORITY, +#else +#define HPM_I2C_IRQ_PRIORITY_2 .irq_priority = 1, +#endif + +#if defined(BSP_I2C3_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_3 .irq_priority = BSP_I2C3_IRQ_PRIORITY, +#else +#define HPM_I2C_IRQ_PRIORITY_3 .irq_priority = 1, #endif - .dmamux = HPM_DMA_SRC_I2C4, - .i2c_irq = IRQn_I2C4, + #if defined(BSP_I2C4_IRQ_PRIORITY) - .irq_priority = BSP_I2C4_IRQ_PRIORITY, +#define HPM_I2C_IRQ_PRIORITY_4 .irq_priority = BSP_I2C4_IRQ_PRIORITY, #else - .irq_priority = 1, +#define HPM_I2C_IRQ_PRIORITY_4 .irq_priority = 1, #endif - }, + +#if defined(BSP_I2C5_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_5 .irq_priority = BSP_I2C5_IRQ_PRIORITY, +#else +#define HPM_I2C_IRQ_PRIORITY_5 .irq_priority = 1, #endif -#if defined(BSP_USING_I2C5) - { - .base = HPM_I2C5, - .bus_name = "i2c5", - .clk_name = clock_i2c5, -#if defined(BSP_I2C5_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_I2C6_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_6 .irq_priority = BSP_I2C6_IRQ_PRIORITY, +#else +#define HPM_I2C_IRQ_PRIORITY_6 .irq_priority = 1, #endif - .dmamux = HPM_DMA_SRC_I2C5, - .i2c_irq = IRQn_I2C5, -#if defined(BSP_I2C5_IRQ_PRIORITY) - .irq_priority = BSP_I2C5_IRQ_PRIORITY, + +#if defined(BSP_I2C7_IRQ_PRIORITY) +#define HPM_I2C_IRQ_PRIORITY_7 .irq_priority = BSP_I2C7_IRQ_PRIORITY, #else - .irq_priority = 1, +#define HPM_I2C_IRQ_PRIORITY_7 .irq_priority = 1, +#endif + +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +/* Macro for ISR handler declaration and implementation */ +#define HPM_I2C_ISR_HANDLER(idx) \ + SDK_DECLARE_EXT_ISR_M(IRQn_I2C##idx, i2c##idx##_isr); \ + void i2c##idx##_isr(void) \ + { \ + handle_i2c_isr(HPM_I2C##idx); \ + } +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +static struct hpm_i2c hpm_i2cs[] = +{ +#if defined(BSP_USING_I2C0) + HPM_I2C_CONFIG(0), #endif - }, +#if defined(BSP_USING_I2C1) + HPM_I2C_CONFIG(1), #endif -#if defined(BSP_USING_I2C6) - { - .base = HPM_I2C6, - .bus_name = "i2c6", - .clk_name = clock_i2c6, -#if defined(BSP_I2C6_USING_DMA) - .enable_dma = RT_TRUE, +#if defined(BSP_USING_I2C2) + HPM_I2C_CONFIG(2), #endif - .dmamux = HPM_DMA_SRC_I2C6, - .i2c_irq = IRQn_I2C6, -#if defined(BSP_I2C6_IRQ_PRIORITY) - .irq_priority = BSP_I2C6_IRQ_PRIORITY, -#else - .irq_priority = 1, +#if defined(BSP_USING_I2C3) + HPM_I2C_CONFIG(3), #endif - }, +#if defined(BSP_USING_I2C4) + HPM_I2C_CONFIG(4), #endif -#if defined(BSP_USING_I2C7) - { - .base = HPM_I2C7, - .bus_name = "i2c7", - .clk_name = clock_i2c7, -#if defined(BSP_I2C7_USING_DMA) - .enable_dma = RT_TRUE, +#if defined(BSP_USING_I2C5) + HPM_I2C_CONFIG(5), #endif - .dmamux = HPM_DMA_SRC_I2C7, - .i2c_irq = IRQn_I2C7, -#if defined(BSP_I2C7_IRQ_PRIORITY) - .irq_priority = BSP_I2C7_IRQ_PRIORITY, -#else - .irq_priority = 1, +#if defined(BSP_USING_I2C6) + HPM_I2C_CONFIG(6), #endif - }, +#if defined(BSP_USING_I2C7) + HPM_I2C_CONFIG(7), #endif }; static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); -static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size); -static hpm_stat_t i2c_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size); +static rt_err_t hpm_i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args); +static hpm_stat_t i2c_tx_trigger_dma(const dma_resource_t *resource, I2C_Type *i2c_ptr, uint32_t src, uint32_t size); +static hpm_stat_t i2c_rx_trigger_dma(const dma_resource_t *resource, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size); +static hpm_stat_t hpm_i2c_master_start_dma_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, uint16_t flags); +static void hpm_i2c_clear_xfer_sems(struct hpm_i2c *i2c); +static void hpm_i2c_prepare_dma_xfer(struct hpm_i2c *i2c); struct rt_i2c_bus_device_ops hpm_i2c_ops = { hpm_i2c_master_transfer, RT_NULL, - RT_NULL + hpm_i2c_bus_control }; +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static inline void handle_i2c_isr(I2C_Type *ptr) +#else +static inline void handle_i2c_isr(int vector, I2C_Type *ptr) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { volatile uint32_t irq_status; RT_ASSERT(ptr != RT_NULL); @@ -204,7 +220,7 @@ static inline void handle_i2c_isr(I2C_Type *ptr) { if (hpm_i2cs[i].base == ptr) { - rt_sem_release(hpm_i2cs[i].xfer_sem); + rt_sem_release(hpm_i2cs[i].i2c_xfer_sem); } } i2c_disable_irq(ptr, I2C_EVENT_TRANSACTION_COMPLETE); @@ -213,101 +229,207 @@ static inline void handle_i2c_isr(I2C_Type *ptr) rt_hw_interrupt_enable(level); } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK #if defined(BSP_USING_I2C0) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C0, i2c0_isr); -void i2c0_isr(void) -{ - handle_i2c_isr(HPM_I2C0); -} +HPM_I2C_ISR_HANDLER(0) #endif #if defined(BSP_USING_I2C1) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C1, i2c1_isr); -void i2c1_isr(void) -{ - handle_i2c_isr(HPM_I2C1); -} +HPM_I2C_ISR_HANDLER(1) #endif #if defined(BSP_USING_I2C2) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C2, i2c2_isr); -void i2c2_isr(void) -{ - handle_i2c_isr(HPM_I2C2); -} +HPM_I2C_ISR_HANDLER(2) #endif #if defined(BSP_USING_I2C3) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C3, i2c3_isr); -void i2c3_isr(void) -{ - handle_i2c_isr(HPM_I2C3); -} +HPM_I2C_ISR_HANDLER(3) #endif #if defined(BSP_USING_I2C4) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C4, i2c4_isr); -void i2c4_isr(void) -{ - handle_i2c_isr(HPM_I2C4); -} +HPM_I2C_ISR_HANDLER(4) #endif #if defined(BSP_USING_I2C5) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C5, i2c5_isr); -void i2c5_isr(void) -{ - handle_i2c_isr(HPM_I2C5); -} +HPM_I2C_ISR_HANDLER(5) #endif #if defined(BSP_USING_I2C6) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C6, i2c6_isr); -void i2c6_isr(void) -{ - handle_i2c_isr(HPM_I2C6); -} +HPM_I2C_ISR_HANDLER(6) #endif #if defined(BSP_USING_I2C7) -SDK_DECLARE_EXT_ISR_M(IRQn_I2C7, i2c7_isr); -void i2c7_isr(void) +HPM_I2C_ISR_HANDLER(7) +#endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +static hpm_stat_t i2c_tx_trigger_dma(const dma_resource_t *resource, I2C_Type *i2c_ptr, uint32_t src, uint32_t size) { - handle_i2c_isr(HPM_I2C7); + hpm_stat_t stat = status_success; + + HPM_CHECK_RET(dma_mgr_set_chn_src_work_mode(resource, DMA_MGR_HANDSHAKE_MODE_NORMAL)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_work_mode(resource, DMA_MGR_HANDSHAKE_MODE_HANDSHAKE)); + HPM_CHECK_RET(dma_mgr_set_chn_src_addr_ctrl(resource, DMA_MGR_ADDRESS_CONTROL_INCREMENT)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_addr_ctrl(resource, DMA_MGR_ADDRESS_CONTROL_FIXED)); + HPM_CHECK_RET(dma_mgr_set_chn_src_width(resource, DMA_MGR_TRANSFER_WIDTH_BYTE)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_width(resource, DMA_MGR_TRANSFER_WIDTH_BYTE)); + HPM_CHECK_RET(dma_mgr_set_chn_src_addr(resource, src)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_addr(resource, (uint32_t)&i2c_ptr->DATA)); + HPM_CHECK_RET(dma_mgr_set_chn_transize(resource, size)); + HPM_CHECK_RET(dma_mgr_enable_channel(resource)); + + return stat; } -#endif +static hpm_stat_t i2c_rx_trigger_dma(const dma_resource_t *resource, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size) +{ + hpm_stat_t stat = status_success; + + HPM_CHECK_RET(dma_mgr_set_chn_src_work_mode(resource, DMA_MGR_HANDSHAKE_MODE_HANDSHAKE)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_work_mode(resource, DMA_MGR_HANDSHAKE_MODE_NORMAL)); + HPM_CHECK_RET(dma_mgr_set_chn_src_addr_ctrl(resource, DMA_MGR_ADDRESS_CONTROL_FIXED)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_addr_ctrl(resource, DMA_MGR_ADDRESS_CONTROL_INCREMENT)); + HPM_CHECK_RET(dma_mgr_set_chn_src_width(resource, DMA_MGR_TRANSFER_WIDTH_BYTE)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_width(resource, DMA_MGR_TRANSFER_WIDTH_BYTE)); + HPM_CHECK_RET(dma_mgr_set_chn_src_addr(resource, (uint32_t)&i2c_ptr->DATA)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_addr(resource, dst)); + HPM_CHECK_RET(dma_mgr_set_chn_transize(resource, size)); + HPM_CHECK_RET(dma_mgr_enable_channel(resource)); + + return stat; +} -static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size) +static void hpm_i2c_clear_sem(rt_sem_t sem) { - dma_handshake_config_t config; + while (rt_sem_take(sem, 0) == RT_EOK) + { + } +} - dma_default_handshake_config(dma_ptr, &config); - config.ch_index = ch_num; - config.dst = (uint32_t)&i2c_ptr->DATA; - config.dst_fixed = true; - config.src = src; - config.src_fixed = false; - config.data_width = DMA_TRANSFER_WIDTH_BYTE; - config.size_in_byte = size; +static void hpm_i2c_clear_xfer_sems(struct hpm_i2c *i2c) +{ + hpm_i2c_clear_sem(i2c->i2c_xfer_sem); + hpm_i2c_clear_sem(i2c->dma_xfer_sem); +} - return dma_setup_handshake(dma_ptr, &config, true); +static void hpm_i2c_prepare_dma_xfer(struct hpm_i2c *i2c) +{ + dma_mgr_disable_chn_irq(&i2c->dma, DMA_MGR_INTERRUPT_MASK_TC); + i2c_disable_irq(i2c->base, I2C_EVENT_TRANSACTION_COMPLETE); + hpm_i2c_clear_xfer_sems(i2c); + dma_clear_transfer_status(i2c->dma.base, i2c->dma.channel); + i2c_clear_status(i2c->base, I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK); } -static hpm_stat_t i2c_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size) +static hpm_stat_t hpm_i2c_master_start_dma_transfer(I2C_Type *i2c_ptr, + const uint16_t device_address, + uint32_t size, + uint16_t flags) { - dma_handshake_config_t config; + uint32_t retry = 0; + uint32_t ctrl = 0; + + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } + + if (flags & I2C_ADDR_10BIT) { + i2c_enable_10bit_address_mode(i2c_ptr, true); + } else { + i2c_enable_10bit_address_mode(i2c_ptr, false); + } + + i2c_clear_status(i2c_ptr, I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK); + i2c_clear_fifo(i2c_ptr); + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + if (flags & I2C_RD) { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); + } else { + ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE); + } + + if (flags & I2C_NO_START) { + ctrl |= I2C_CTRL_PHASE_START_SET(false); + } else { + ctrl |= I2C_CTRL_PHASE_START_SET(true); + } + + if (flags & I2C_NO_STOP) { + ctrl |= I2C_CTRL_PHASE_STOP_SET(false); + } else { + ctrl |= I2C_CTRL_PHASE_STOP_SET(true); + } - dma_default_handshake_config(dma_ptr, &config); - config.ch_index = ch_num; - config.dst = dst; - config.dst_fixed = false; - config.src = (uint32_t)&i2c_ptr->DATA; - config.src_fixed = true; - config.data_width = DMA_TRANSFER_WIDTH_BYTE; - config.size_in_byte = size; + i2c_ptr->CTRL = ctrl | I2C_CTRL_PHASE_ADDR_SET(true) + | I2C_CTRL_PHASE_DATA_SET(true) +#ifdef I2C_CTRL_DATACNT_HIGH_MASK + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) +#endif + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + + i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; + i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + while (i2c_is_addrhit(i2c_ptr) == false) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_i2c_no_addr_hit; + } + retry++; + } + i2c_clear_status(i2c_ptr, I2C_STATUS_ADDRHIT_MASK); - return dma_setup_handshake(dma_ptr, &config, true); + return status_success; +} + +static i2c_mode_t hpm_i2c_mode_from_hz(rt_uint32_t hz) +{ + if (hz <= 100000U) + { + return i2c_mode_normal; + } + if (hz <= 400000U) + { + return i2c_mode_fast; + } + + return i2c_mode_fast_plus; +} + +static rt_err_t hpm_i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args) +{ + struct hpm_i2c *i2c_info = (struct hpm_i2c *)bus; + i2c_config_t config; + hpm_stat_t stat; + rt_uint32_t freq; + rt_uint32_t hz; + + RT_ASSERT(bus != RT_NULL); + + switch (cmd) + { + case RT_I2C_DEV_CTRL_CLK: + if (args == RT_NULL) + { + return -RT_EINVAL; + } + hz = *(rt_uint32_t *)args; + if (hz == 0U) + { + return -RT_EINVAL; + } + config.i2c_mode = hpm_i2c_mode_from_hz(hz); + config.is_10bit_addressing = false; + freq = clock_get_frequency(i2c_info->clk_name); + stat = i2c_init_master(i2c_info->base, freq, &config); + if (i2c_info->enable_dma) + { + i2c_disable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); + } + return stat == status_success ? RT_EOK : -RT_ERROR; + default: + return -RT_EINVAL; + } } void i2c_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) @@ -320,10 +442,7 @@ void i2c_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_dat if ((i2c->dma.base == ptr) && i2c->dma.channel == channel) { dma_mgr_disable_chn_irq(&i2c->dma, DMA_MGR_INTERRUPT_MASK_TC); - if (i2c->is_read == true) - { - rt_sem_release(i2c->xfer_sem); - } + rt_sem_release(i2c->dma_xfer_sem); } rt_hw_interrupt_enable(level); } @@ -345,9 +464,11 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_uint32_t aligned_len = 0; rt_uint32_t remaining_size = 0; rt_uint32_t transfer_len; + for (i = 0; i < num; i++) { msg = &msgs[i]; + aligned_buf = (uint8_t*) msg->buf; remaining_size = msg->len; if ((msg->len > 0) && (i2c_info->enable_dma)) { @@ -359,6 +480,7 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct /* The allocated pointer is always RT_ALIGN_SIZE aligned */ raw_alloc_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); RT_ASSERT(raw_alloc_buf != RT_NULL); + aligned_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_buf); } else { @@ -399,31 +521,35 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct transfer_len = MIN(I2C_SOC_TRANSFER_COUNT_MAX, remaining_size); if ((i2c_info->enable_dma)) { - /* sequential transfer now is not support dma */ - if ((msg->flags & RT_I2C_NO_START) || (msg->flags & RT_I2C_NO_STOP) || - (msg->flags & RT_I2C_NO_READ_ACK) || (msg->flags & RT_I2C_NO_READ_ACK) ) { + if (msg->flags & RT_I2C_NO_READ_ACK) { i2c_stat = status_invalid_argument; break; } i2c_info->is_read = true; - i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); - dmamux_config(HPM_DMAMUX, i2c_info->dma.channel, i2c_info->dmamux, true); - i2c_stat = i2c_rx_trigger_dma(i2c_info->dma.base, i2c_info->dma.channel, i2c_info->base, + hpm_i2c_prepare_dma_xfer(i2c_info); + i2c_stat = i2c_rx_trigger_dma(&i2c_info->dma, i2c_info->base, core_local_mem_to_sys_address(0, (uint32_t) dummy_buf), transfer_len); if (i2c_stat != status_success) { break; } - i2c_stat = i2c_master_start_dma_read(i2c_info->base, msg->addr, msg->len); + dma_mgr_enable_chn_irq(&i2c_info->dma, DMA_MGR_INTERRUPT_MASK_TC); + i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); + i2c_stat = hpm_i2c_master_start_dma_transfer(i2c_info->base, msg->addr, transfer_len, msg->flags); if (i2c_stat != status_success) { break; } - rt_sem_take(i2c_info->xfer_sem, RT_WAITING_FOREVER); + rt_sem_take(i2c_info->dma_xfer_sem, RT_WAITING_FOREVER); + rt_sem_take(i2c_info->i2c_xfer_sem, RT_WAITING_FOREVER); } else { - i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + i2c_stat = i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + if (i2c_stat != status_success) + { + break; + } } dummy_buf += transfer_len; remaining_size -= transfer_len; @@ -452,31 +578,35 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct transfer_len = MIN(I2C_SOC_TRANSFER_COUNT_MAX, remaining_size); if (i2c_info->enable_dma) { - /* sequential transfer now is not support dma */ - if ((msg->flags & RT_I2C_NO_START) || (msg->flags & RT_I2C_NO_STOP) || - (msg->flags & RT_I2C_NO_READ_ACK) || (msg->flags & RT_I2C_NO_READ_ACK) ) { + if (msg->flags & RT_I2C_NO_READ_ACK) { i2c_stat = status_invalid_argument; break; } i2c_info->is_read = false; - i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); - dmamux_config(HPM_DMAMUX, i2c_info->dma.channel, i2c_info->dmamux, true); - i2c_stat = i2c_tx_trigger_dma(i2c_info->dma.base, i2c_info->dma.channel, i2c_info->base, + hpm_i2c_prepare_dma_xfer(i2c_info); + i2c_stat = i2c_tx_trigger_dma(&i2c_info->dma, i2c_info->base, core_local_mem_to_sys_address(0, (uint32_t) dummy_buf), transfer_len); if (i2c_stat != status_success) { break; } - i2c_stat = i2c_master_start_dma_write(i2c_info->base, msg->addr, msg->len); + dma_mgr_enable_chn_irq(&i2c_info->dma, DMA_MGR_INTERRUPT_MASK_TC); + i2c_enable_irq(i2c_info->base, I2C_EVENT_TRANSACTION_COMPLETE); + i2c_stat = hpm_i2c_master_start_dma_transfer(i2c_info->base, msg->addr, transfer_len, msg->flags); if (i2c_stat != status_success) { break; } - rt_sem_take(i2c_info->xfer_sem, RT_WAITING_FOREVER); + rt_sem_take(i2c_info->dma_xfer_sem, RT_WAITING_FOREVER); + rt_sem_take(i2c_info->i2c_xfer_sem, RT_WAITING_FOREVER); } else { - i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + i2c_stat = i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags); + if (i2c_stat != status_success) + { + break; + } } dummy_buf += transfer_len; remaining_size -= transfer_len; @@ -493,14 +623,9 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct { break; } + ret++; } - if (i2c_stat != status_success) - { - return ret; - } - - ret = i; return ret; } @@ -510,11 +635,16 @@ int rt_hw_i2c_init(void) rt_err_t ret = RT_EOK; hpm_stat_t stat; i2c_config_t config; + dma_mgr_chn_conf_t dma_config; rt_uint32_t freq; char sem_name[RT_NAME_MAX]; for (uint32_t i = 0; i < sizeof(hpm_i2cs) / sizeof(hpm_i2cs[0]); i++) { - init_i2c_pins(hpm_i2cs[i].base); + if (init_i2c_pins(hpm_i2cs[i].base) != status_success) { + LOG_E("Failed to initialize I2C%u pins. Please check board configuration", i); + ret = -RT_ERROR; + continue; + } clock_add_to_group(hpm_i2cs[i].clk_name, BOARD_RUNNING_CORE & 0x1); clock_set_source_divider(hpm_i2cs[i].clk_name, clk_src_osc24m, 1U); @@ -524,6 +654,7 @@ int rt_hw_i2c_init(void) stat = i2c_init_master(hpm_i2cs[i].base, freq, &config); if (stat != status_success) { LOG_E("rt i2c device %s init failed", hpm_i2cs[i].bus_name); + ret = -RT_ERROR; } hpm_i2cs[i].bus.ops = &hpm_i2c_ops; @@ -534,15 +665,34 @@ int rt_hw_i2c_init(void) { return -RT_ERROR; } + dma_mgr_get_default_chn_config(&dma_config); + dma_config.en_dmamux = true; + dma_config.dmamux_src = hpm_i2cs[i].dmamux; + dma_config.src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + dma_config.dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + stat = dma_mgr_setup_channel(&hpm_i2cs[i].dma, &dma_config); + if (stat != status_success) + { + return -RT_ERROR; + } dma_mgr_install_chn_tc_callback(&hpm_i2cs[i].dma, i2c_dma_channel_tc_callback, (void *)&hpm_i2cs[i]); dma_mgr_enable_dma_irq_with_priority(&hpm_i2cs[i].dma, 1); intc_m_enable_irq_with_priority(hpm_i2cs[i].i2c_irq, hpm_i2cs[i].irq_priority); i2c_disable_irq(hpm_i2cs[i].base, I2C_EVENT_TRANSACTION_COMPLETE); - rt_sprintf(sem_name, "%s_s", hpm_i2cs[i].bus_name); - hpm_i2cs[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); - if (hpm_i2cs[i].xfer_sem == RT_NULL) + rt_sprintf(sem_name, "%s_i", hpm_i2cs[i].bus_name); + hpm_i2cs[i].i2c_xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_i2cs[i].i2c_xfer_sem == RT_NULL) + { + ret = -RT_ENOMEM; + break; + } + rt_sprintf(sem_name, "%s_d", hpm_i2cs[i].bus_name); + hpm_i2cs[i].dma_xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + if (hpm_i2cs[i].dma_xfer_sem == RT_NULL) { - ret = RT_ENOMEM; + rt_sem_delete(hpm_i2cs[i].i2c_xfer_sem); + hpm_i2cs[i].i2c_xfer_sem = RT_NULL; + ret = -RT_ENOMEM; break; } } @@ -550,6 +700,10 @@ int rt_hw_i2c_init(void) if (ret != RT_EOK) { LOG_E("rt i2c device %s register failed, status=%d\n", hpm_i2cs[i].bus_name, ret); } +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register I2C device to irq table */ + rt_hw_interrupt_install(hpm_i2cs[i].i2c_irq, (rt_isr_handler_t)handle_i2c_isr, hpm_i2cs[i].base, hpm_i2cs[i].bus_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return ret; @@ -559,4 +713,3 @@ INIT_DEVICE_EXPORT(rt_hw_i2c_init); #endif /* RT_USING_I2C */ #endif /*BSP_USING_I2C*/ - diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.c b/bsp/hpmicro/libraries/drivers/drv_i2s.c index 3c96618622..26d623c086 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2025 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -157,7 +157,10 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) i2s_get_default_config(hpm_audio->base, &i2s_config); i2s_config.enable_mclk_out = true; - i2s_init(hpm_audio->base, &i2s_config); + if (status_success != i2s_init(hpm_audio->base, &i2s_config)) { + LOG_E("%s init failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } mclk_hz = clock_get_frequency(hpm_audio->clk_name); i2s_get_default_transfer_config(&transfer); @@ -414,16 +417,19 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio /* Stop I2S transfer if the I2S needs to be re-configured */ bool is_enabled = i2s_is_enabled(hpm_audio->base); i2s_disable(hpm_audio->base); - i2s_reset_tx_rx(hpm_audio->base); + if (status_success != i2s_reset_tx_rx(hpm_audio->base)) { + LOG_E("%s reset tx_rx failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } if (is_enabled) { if (hpm_audio->i2s_state == hpm_i2s_state_read) { - dma_abort_channel(hpm_audio->rx_dma_resource.base, 1u << hpm_audio->rx_dma_resource.channel); + dma_mgr_abort_chn_transfer(&(hpm_audio->rx_dma_resource)); } if (hpm_audio->i2s_state == hpm_i2s_state_write) { - dma_abort_channel(hpm_audio->tx_dma_resource.base, 1u << hpm_audio->tx_dma_resource.channel); + dma_mgr_abort_chn_transfer(&(hpm_audio->tx_dma_resource)); } } if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) @@ -469,9 +475,13 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) LOG_E("no dma resource available for I2S TX transfer.\n"); return -RT_ERROR; } - i2s_reset_tx(hpm_audio->base); /* disable and reset tx */ + if (status_success != i2s_reset_tx(hpm_audio->base)) { /* disable and reset tx */ + LOG_E("%s reset tx failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } + i2s_enable_tx_line(hpm_audio->base, hpm_audio->transfer.data_line); /* fill 2 dummy data, it is suitable for 1/2 channel of audio */ - if (i2s_fill_tx_dummy_data(hpm_audio->base, hpm_audio->transfer.data_line , 2) != status_success) { + if (i2s_fill_tx_dummy_data(hpm_audio->base, hpm_audio->transfer.data_line, 2) != status_success) { return -RT_ERROR; } rt_audio_tx_complete(audio); @@ -491,7 +501,11 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) LOG_E("no dma resource available for I2S RX transfer.\n"); return -RT_ERROR; } - i2s_reset_rx(hpm_audio->base); /* disable and reset rx */ + if (status_success != i2s_reset_rx(hpm_audio->base)) { /* disable and reset rx */ + LOG_E("%s reset rx failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } + i2s_enable_rx_line(hpm_audio->base, hpm_audio->transfer.data_line); if (I2S_FIFO_SIZE != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { return -RT_ERROR; } @@ -513,12 +527,12 @@ static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream) if (stream == AUDIO_STREAM_REPLAY) { dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - dma_abort_channel(dma_resource->base, 1u << dma_resource->channel); + dma_mgr_abort_chn_transfer(dma_resource); dma_mgr_release_resource(dma_resource); } else if (stream == AUDIO_STREAM_RECORD) { dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - dma_abort_channel(dma_resource->base, 1u << dma_resource->channel); + dma_mgr_abort_chn_transfer(dma_resource); dma_mgr_release_resource(dma_resource); } else { return -RT_ERROR; @@ -559,6 +573,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr ch_config.size_in_byte = size; ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch_config.interrupt_mask = DMA_INTERRUPT_MASK_ABORT; if (l1c_dc_is_enabled()) { /* cache writeback for sent buff */ @@ -583,6 +598,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr ch_config.size_in_byte = size; ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch_config.interrupt_mask = DMA_INTERRUPT_MASK_ABORT; hpm_audio->i2s_state = hpm_i2s_state_read; if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { diff --git a/bsp/hpmicro/libraries/drivers/drv_lcd.c b/bsp/hpmicro/libraries/drivers/drv_lcd.c index 1fa4951f9d..f2541d3b92 100644 --- a/bsp/hpmicro/libraries/drivers/drv_lcd.c +++ b/bsp/hpmicro/libraries/drivers/drv_lcd.c @@ -17,11 +17,10 @@ #include "hpm_pdma_drv.h" #include "hpm_panel.h" - #define LCD_BITS_PER_PIXEL 16 #define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 #define LCD_LAYER_INDEX (0) -#define LCD_LAYER_DONE_MASK (1U << LCD_LAYER_INDEX) +#define LCD_LAYER_DONE_MASK (1U<<LCD_LAYER_INDEX) struct hpm_lcd { LCDC_Type *lcd_base; @@ -78,13 +77,22 @@ static struct hpm_lcd hpm_lcds[] = }, }; -SDK_DECLARE_EXT_ISR_M(BOARD_LCD_IRQ, isr_lcd_d0) +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void isr_lcd_d0(void) { lcdc_disable_interrupt(hpm_lcds[0].lcd_base, LCDC_INT_EN_VSYNC_MASK); rt_sem_release(&hpm_lcds[0].lcd_lock); lcdc_clear_status(hpm_lcds[0].lcd_base, LCDC_ST_VSYNC_MASK); } +SDK_DECLARE_EXT_ISR_M(BOARD_LCD_IRQ, isr_lcd_d0) +#else +void isr_lcd_d(int vector, hpm_lcd *hpm_lcds_pram) +{ + lcdc_disable_interrupt(hpm_lcds_pram->lcd_base, LCDC_INT_EN_VSYNC_MASK); + rt_sem_release(&hpm_lcds_pram->lcd_lock); + lcdc_clear_status(hpm_lcds_pram->lcd_base, LCDC_ST_VSYNC_MASK); +} +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ static rt_err_t hpm_lcd_init(struct rt_device *device) { @@ -100,6 +108,7 @@ static rt_err_t hpm_lcd_control(struct rt_device *device, int cmd, void *args) hpm_panel_t *panel = hpm_panel_find_device_default(); struct rt_device_graphic_info *info = RT_NULL; uint32_t buffer; + rt_err_t err = RT_EOK; switch (cmd) { @@ -108,7 +117,7 @@ static rt_err_t hpm_lcd_control(struct rt_device *device, int cmd, void *args) rt_sem_trytake(&lcd->lcd_lock); lcdc_disable_interrupt(lcd->lcd_base, LCDC_INT_EN_VSYNC_MASK); rt_thread_delay(10); - hpm_lcdc_init(lcd, info); + err = hpm_lcdc_init(lcd, info); break; case RTGRAPHIC_CTRL_RECT_UPDATE: @@ -161,6 +170,7 @@ static rt_err_t hpm_lcd_control(struct rt_device *device, int cmd, void *args) default: break; } + return err; } static int hpm_lcdc_init(struct hpm_lcd *lcd, struct rt_device_graphic_info *info) @@ -240,6 +250,10 @@ int drv_lcd_hw_init(void) result = -RT_ERROR; goto __exit; } +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register LCD device to irq table */ + rt_hw_interrupt_install(hpm_lcds[i].lcd_irq, (rt_isr_handler_t)isr_lcd_d, hpm_lcds[i], hpm_lcds[i].bus_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ __exit: if (result != RT_EOK) { diff --git a/bsp/hpmicro/libraries/drivers/drv_mcan.c b/bsp/hpmicro/libraries/drivers/drv_mcan.c index 55dcfcb8ad..191613af49 100644 --- a/bsp/hpmicro/libraries/drivers/drv_mcan.c +++ b/bsp/hpmicro/libraries/drivers/drv_mcan.c @@ -1,499 +1,630 @@ + + /* * Copyright (c) 2023-2025 HPMicro - * * SPDX-License-Identifier: BSD-3-Clause + * @file drv_mcan.c + * @brief MCAN (CAN-FD) driver implementation for RT-Thread + * + * This file implements the MCAN (CAN with Flexible Data-rate) driver for HPMicro + * microcontrollers, supporting up to 8 MCAN instances (MCAN0-MCAN7). The driver + * provides both classic CAN and CAN-FD functionality with configurable bit rates, + * message filtering, and interrupt handling. + * + * Features: + * - Support for up to 8 MCAN controllers (MCAN0-MCAN7) + * - CAN 2.0A/B and CAN FD support + * - Hardware filtering with up to 128 standard and 64 extended filters + * - Interrupt-driven operation + * - Error handling and status reporting + * - Configurable baud rates and timing parameters + * - AHB RAM message buffer support for improved performance * * Change Logs: * Date Author Notes * 2023-04-07 HPMicro the first version * 2024-05-31 HPMicro add MCAN4-7 support + * 2025-09-01 HPMicro remove repetitive codes and optimize the implementation */ -#include <rtthread.h> -#include <rtdevice.h> -#include <rthw.h> -#include "board.h" -#include "hpm_mcan_drv.h" +#include "rtconfig.h" -#include "hpm_clock_drv.h" +#ifdef RT_USING_CAN -#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ -#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ -#define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */ -#define CAN_EXT_FILTER_NUM_MAX (64U) /* ext Filter number */ +/* ============================================================================ + * Include Files + * ============================================================================ */ -#ifdef RT_USING_CAN +/* HPMicro SDK includes */ +#include "board.h" /* Board support package definitions */ +#include "hpm_clock_drv.h" /* Clock management functions */ +#include "hpm_mcan_drv.h" /* MCAN hardware abstraction layer */ -typedef struct _hpm_can_struct -{ - MCAN_Type *can_base; /**< CAN Base address */ - const char *name; /**< CAN device name */ - int32_t irq_num; /**< CAN IRQ index */ - uint8_t irq_priority; /**< CAN IRQ priority */ - clock_name_t clk_name; /**< CAN clock name */ - uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - uint32_t ram_base; - uint32_t ram_size; +/* RT-Thread includes */ +#include <rtdevice.h> /* RT-Thread device framework */ +#include <rthw.h> /* RT-Thread hardware abstraction */ +#include <rtthread.h> /* RT-Thread core services */ + +/* ============================================================================ + * Configuration Constants + * ============================================================================ */ + +#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ +#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ +#define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */ +#define CAN_EXT_FILTER_NUM_MAX (64U) /* ext Filter number */ + +#define CAN_STD_ID_MASK (0x7FFU) +#define CAN_EXT_ID_MASK (0x1FFFFFFFUL) + +/* ============================================================================ + * IRQ Priority Configuration Macros + * ============================================================================ */ + +/** + * @brief MCAN IRQ Priority Configuration Macros + * + * These macros provide a flexible way to configure IRQ priorities for each MCAN + * instance. Each macro checks if a BSP-specific priority is defined, otherwise + * defaults to priority 1. + * + * Usage: + * - MCAN_IRQ_PRI_VAL_0 through MCAN_IRQ_PRI_VAL_7: Get priority for specific instance + * - MCAN_IRQ_PRI_VAL(n): Generic macro to get priority for instance n + */ + +/* MCAN IRQ Priority Configuration Macros */ +#ifdef BSP_MCAN0_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_0 BSP_MCAN0_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_0 1 #endif - mcan_config_t can_config; /**< CAN configuration for IP */ - struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ - uint32_t irq_txrx_err_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ - uint32_t std_filter_num; /**< std Filter number */ - mcan_filter_elem_t std_can_filters[CAN_STD_FILTER_NUM_MAX]; - uint32_t ext_filter_num; /**< ext Filter number */ - mcan_filter_elem_t ext_can_filters[CAN_EXT_FILTER_NUM_MAX]; + +#ifdef BSP_MCAN1_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_1 BSP_MCAN1_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_1 1 +#endif + +#ifdef BSP_MCAN2_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_2 BSP_MCAN2_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_2 1 +#endif + +#ifdef BSP_MCAN3_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_3 BSP_MCAN3_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_3 1 +#endif + +#ifdef BSP_MCAN4_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_4 BSP_MCAN4_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_4 1 +#endif + +#ifdef BSP_MCAN5_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_5 BSP_MCAN5_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_5 1 +#endif + +#ifdef BSP_MCAN6_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_6 BSP_MCAN6_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_6 1 +#endif + +#ifdef BSP_MCAN7_IRQ_PRIORITY +#define MCAN_IRQ_PRI_VAL_7 BSP_MCAN7_IRQ_PRIORITY +#else +#define MCAN_IRQ_PRI_VAL_7 1 +#endif + +/** @brief Generic macro to get IRQ priority for MCAN instance n */ +#define MCAN_IRQ_PRI_VAL(n) MCAN_IRQ_PRI_VAL_##n + +#define CAN_UNITED (0UL) +#define CAN_INITED (1UL) +#define CAN_RUNNING (2UL) +#define CAN_STOPPED (3UL) + + +/* ============================================================================ + * Data Structures + * ============================================================================ */ + +/** + * @brief HPM MCAN device structure + * + * This structure contains all the necessary information for managing a single + * MCAN instance, including hardware configuration, RT-Thread device integration, + * and message filtering capabilities. + */ +typedef struct _hpm_can_struct { + MCAN_Type *can_base; /**< MCAN hardware base address */ + const char *name; /**< Device name (e.g., "can0", "can1") */ + rt_int32_t irq_num; /**< Interrupt number for this MCAN instance */ + rt_uint8_t irq_priority; /**< Interrupt priority for this MCAN instance */ + clock_name_t clk_name; /**< Clock source name for this MCAN instance */ + rt_uint32_t fifo_index; /**< FIFO index (used for RT-Thread framework compatibility) */ + rt_uint32_t ram_base; /**< Message buffer RAM base address (NULL for HPM6200) */ + rt_uint32_t ram_size; /**< Message buffer RAM size (0 for HPM6200) */ + mcan_config_t can_config; /**< MCAN hardware configuration structure */ + struct rt_can_device can_dev; /**< RT-Thread CAN device structure */ + rt_uint32_t irq_txrx_err_enable_mask; /**< Bitmask for enabled TX/RX/Error interrupts */ + rt_uint32_t std_filter_num; /**< Number of configured standard ID filters */ + mcan_filter_elem_t std_can_filters[CAN_STD_FILTER_NUM_MAX]; /**< Standard ID filter array */ + rt_uint32_t ext_filter_num; /**< Number of configured extended ID filters */ + mcan_filter_elem_t ext_can_filters[CAN_EXT_FILTER_NUM_MAX]; /**< Extended ID filter array */ + rt_uint32_t can_tx_fifo_index; /**< CAN TX FIFO index */ + rt_uint8_t can_stat; /**< CAN status */ } hpm_can_t; +/* ============================================================================ + * Default Filter Configurations + * ============================================================================ */ + +/** + * @brief Default standard ID filter configuration + * + * This filter accepts all standard ID messages and stores them in RXFIFO0. + * Used when no specific filters are configured by the application. + */ static const mcan_filter_elem_t k_default_std_id_filter = { - /* Use classic filter */ - .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, - /* Store message into RXFIFO0 if matching */ - .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Standard ID only */ - .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, - /* Sync Message, only evaluated when "CCCR.UTSU" is set */ - .sync_message = 0U, - /* Don't care if mask is set to all 1s */ - .filter_id = 0U, - /* Accept all messages */ - .filter_mask = 0x7FFU, + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, /**< Use classic filter type */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, /**< Store in RXFIFO0 on match */ + .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, /**< Standard 11-bit ID */ + .sync_message = 0U, /**< Not a sync message */ + .filter_id = 0U, /**< Filter ID (don't care) */ + .filter_mask = 0U, /**< Accept all messages */ }; +/** + * @brief Default extended ID filter configuration + * + * This filter accepts all extended ID messages and stores them in RXFIFO0. + * Used when no specific filters are configured by the application. + */ static const mcan_filter_elem_t k_default_ext_id_filter = { - /* Use classic filter */ - .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, - /* Store message into RXFIFO0 if matching */ - .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Extended ID only */ - .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, - /* Sync Message, only evaluated when "CCCR.UTSU" is set */ - .sync_message = 0, - /* Don't care if mask is set to all 1s */ - .filter_id = 0, - /* Accept all messages */ - .filter_mask = 0x1FFFFFFFUL, + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, /**< Use classic filter type */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, /**< Store in RXFIFO0 on match */ + .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, /**< Extended 29-bit ID */ + .sync_message = 0, /**< Not a sync message */ + .filter_id = 0, /**< Filter ID (don't care) */ + .filter_mask = 0U, /**< Accept all messages */ }; +/* ============================================================================ + * Function Declarations + * ============================================================================ */ /** - * @brief Configure CAN controller - * @param [in/out] can CAN device pointer - * @param [in] cfg CAN configuration pointer - * @retval RT_EOK for valid configuration - * @retval -RT_ERROR for invalid configuration + * @brief Configure MCAN controller + * + * Initializes the MCAN hardware with the specified configuration including + * baud rate, mode, and timing parameters. + * + * @param[in,out] can Pointer to RT-Thread CAN device structure + * @param[in] cfg Pointer to CAN configuration structure + * @return RT_EOK on success, -RT_ERROR on failure */ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg); /** - * @brief Control/Get CAN state - * including:interrupt, mode, priority, baudrate, filter, status - * @param [in/out] can CAN device pointer - * @param [in] cmd Control command - * @param [in/out] arg Argument pointer - * @retval RT_EOK for valid control command and arg - * @retval -RT_ERROR for invalid control command or arg + * @brief Control MCAN device operations + * + * Handles various control commands including interrupt management, mode changes, + * baud rate configuration, filter setup, and status retrieval. + * + * @param[in,out] can Pointer to RT-Thread CAN device structure + * @param[in] cmd Control command (RT_DEVICE_CTRL_*, RT_CAN_CMD_*) + * @param[in,out] arg Command-specific argument pointer + * @return RT_EOK on success, -RT_ERROR on failure */ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg); /** - * @brief Send out CAN message - * @param [in] can CAN device pointer - * @param [in] buf CAN message buffer - * @param [in] boxno Mailbox number, it is not used in this porting - * @retval RT_EOK No error - * @retval -RT_ETIMEOUT timeout happened - * @retval -RT_EFULL Transmission buffer is full + * @brief Send CAN message + * + * Transmits a CAN message through the specified MCAN instance. + * Supports both classic CAN and CAN-FD frames. + * + * @param[in] can Pointer to RT-Thread CAN device structure + * @param[in] buf Pointer to CAN message buffer + * @param[in] boxno Mailbox number (not used in this implementation) + * @return RT_EOK on success, -RT_ETIMEOUT on timeout, -RT_EFULL if buffer full */ -static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); +static rt_ssize_t hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); /** - * @brief Receive message from CAN - * @param [in] can CAN device pointer - * @param [out] buf CAN receive buffer - * @param [in] boxno Mailbox Number, it is not used in this porting - * @retval RT_EOK no error - * @retval -RT_ERROR Error happened during reading receive FIFO - * @retval -RT_EMPTY no data in receive FIFO + * @brief Receive CAN message + * + * Receives a CAN message from the MCAN RX FIFO. + * Supports both classic CAN and CAN-FD frames. + * + * @param[in] can Pointer to RT-Thread CAN device structure + * @param[out] buf Pointer to receive buffer for CAN message + * @param[in] boxno Mailbox number (not used in this implementation) + * @return RT_EOK on success, -RT_ERROR on error, -RT_EMPTY if no data */ -static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); +static rt_ssize_t hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); /** - * @brief Common Interrupt Service routine - * @param [in] hpm_can HPM CAN pointer + * @brief MCAN interrupt service routine + * + * Handles all MCAN interrupts including transmission completion, reception, + * FIFO overflow, and error conditions. Updates RT-Thread CAN device status. + * + * @param[in] hpm_can Pointer to HPM MCAN device structure */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_mcan_isr(hpm_can_t *hpm_can); +#else +static void hpm_mcan_isr(int vector, hpm_can_t *hpm_can); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ /** - * @brief Decode data bytes from DLC - * @param [in] dlc Data Length Code - * @return decoded data bytes + * @brief Convert DLC to data byte count + * + * Converts Data Length Code (DLC) to actual number of data bytes. + * Handles both classic CAN (0-8 bytes) and CAN-FD (0-64 bytes) formats. + * + * @param[in] dlc Data Length Code value + * @return Number of data bytes */ static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); +/* ============================================================================ + * Device Definition Macros + * ============================================================================ */ + +/** + * @brief Define MCAN device instance macro + * + * This macro creates a complete MCAN device instance including: + * - Device structure initialization + * - Interrupt service routine declaration + * - ISR function implementation + * + * @param n MCAN instance number (0-7) + */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +#define MCAN_DEFINE_DEVICE(n) \ + static hpm_can_t dev_can##n = { \ + .can_base = HPM_MCAN##n, \ + .name = "can" #n, \ + .irq_num = IRQn_MCAN##n, \ + .irq_priority = MCAN_IRQ_PRI_VAL(n), \ + .fifo_index = n, \ + .clk_name = clock_can##n, \ + MCAN_RAM_PARAMS(n), \ + }; \ + SDK_DECLARE_EXT_ISR_M(IRQn_MCAN##n, can##n##_isr); \ + void can##n##_isr(void) \ + { \ + hpm_mcan_isr(&dev_can##n); \ + } +#else +#define MCAN_DEFINE_DEVICE(n) \ + static hpm_can_t dev_can##n = { \ + .can_base = HPM_MCAN##n, \ + .name = "can" #n, \ + .irq_num = IRQn_MCAN##n, \ + .irq_priority = MCAN_IRQ_PRI_VAL(n), \ + .fifo_index = n, \ + .clk_name = clock_can##n, \ + MCAN_RAM_PARAMS(n), \ + }; +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +/** + * @brief RAM parameters macro for MCAN device + * + * Conditionally sets RAM base and size parameters based on SoC capabilities. + * Some SoCs (like HPM6200) don't support AHB RAM message buffers. + * + * @param n MCAN instance number (0-7) + */ +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) +#define MCAN_RAM_PARAMS(n) .ram_base = (uint32_t)mcan##n##_msg_buf, .ram_size = mcan##n##_msg_buf_size +#else +#define MCAN_RAM_PARAMS(n) .ram_base = (uint32_t)NULL, .ram_size = 0 +#endif + +/** + * @brief Initialize message buffer in AHB RAM macro + * + * Creates message buffer arrays in AHB RAM for SoCs that support it. + * This improves performance by placing message buffers in faster memory. + * + * @param n MCAN instance number (0-7) + */ #if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) +#define MCAN_INIT_MSG_BUF_IN_AHB_RAM(n) \ + ATTR_PLACE_AT(".ahb_sram") \ + uint32_t mcan##n##_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; \ + const uint32_t mcan##n##_msg_buf_size = sizeof(mcan##n##_msg_buf); + +/* ============================================================================ + * Message Buffer Allocation (AHB RAM) + * ============================================================================ */ + +/** + * @brief Allocate message buffers in AHB RAM for each enabled MCAN instance + * + * These buffers are placed in AHB RAM for improved performance on supported SoCs. + * Each MCAN instance gets its own dedicated message buffer space. + */ + #if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan0_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(0) #endif + #if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan1_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(1) #endif + #if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan2_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(2) #endif + #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan3_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(3) #endif + #if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan4_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(4) #endif + #if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan5_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(5) #endif + #if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan6_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +MCAN_INIT_MSG_BUF_IN_AHB_RAM(6) #endif + #if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan7_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; -#endif +MCAN_INIT_MSG_BUF_IN_AHB_RAM(7) #endif -#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) -static hpm_can_t dev_can0 = -{ - .can_base = HPM_MCAN0, - .name = "can0", - .irq_num = IRQn_MCAN0, -#if defined(BSP_MCAN0_IRQ_PRIORITY) - .irq_priority = BSP_MCAN0_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 0, - .clk_name = clock_can0, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan0_msg_buf, - .ram_size = sizeof(mcan0_msg_buf), -#endif -}; +#endif /* MCAN_SOC_MSG_BUF_IN_AHB_RAM */ -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN0, can0_isr); -void can0_isr(void) -{ - hpm_mcan_isr(&dev_can0); -} +/* ============================================================================ + * MCAN Device Instances + * ============================================================================ */ +/** + * @brief Create MCAN device instances for each enabled MCAN peripheral + * + * Each enabled MCAN instance gets its own device structure, interrupt handler, + * and ISR function. The MCAN_DEFINE_DEVICE macro handles all the boilerplate + * code for device initialization. + */ + +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) +MCAN_DEFINE_DEVICE(0) #endif #if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) -static hpm_can_t dev_can1 = -{ - .can_base = HPM_MCAN1, - .name = "can1", - .irq_num = IRQn_MCAN1, -#if defined(BSP_MCAN1_IRQ_PRIORITY) - .irq_priority = BSP_MCAN1_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 1, - .clk_name = clock_can1, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan1_msg_buf, - .ram_size = sizeof(mcan1_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN1, can1_isr); -void can1_isr(void) -{ - hpm_mcan_isr(&dev_can1); -} +MCAN_DEFINE_DEVICE(1) #endif #if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) -static hpm_can_t dev_can2 = -{ - .can_base = HPM_MCAN2, - .name = "can2", - .irq_num = IRQn_MCAN2, -#if defined(BSP_MCAN2_IRQ_PRIORITY) - .irq_priority = BSP_MCAN2_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 2, - .clk_name = clock_can2, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan2_msg_buf, - .ram_size = sizeof(mcan2_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN2, can2_isr); -void can2_isr(void) -{ - hpm_mcan_isr(&dev_can2); -} +MCAN_DEFINE_DEVICE(2) #endif #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) -static hpm_can_t dev_can3 = -{ - .can_base = HPM_MCAN3, - .name = "can3", - .irq_num = IRQn_MCAN3, -#if defined(BSP_MCAN3_IRQ_PRIORITY) - .irq_priority = BSP_MCAN3_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 3, - .clk_name = clock_can3, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan3_msg_buf, - .ram_size = sizeof(mcan3_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN3, can3_isr); -void can3_isr(void) -{ - hpm_mcan_isr(&dev_can3); -} +MCAN_DEFINE_DEVICE(3) #endif #if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) -static hpm_can_t dev_can4 = -{ - .can_base = HPM_MCAN4, - .name = "can4", - .irq_num = IRQn_MCAN4, -#if defined(BSP_MCAN4_IRQ_PRIORITY) - .irq_priority = BSP_MCAN4_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 4, - .clk_name = clock_can4, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan4_msg_buf, - .ram_size = sizeof(mcan4_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN4, can4_isr); -void can4_isr(void) -{ - hpm_mcan_isr(&dev_can4); -} +MCAN_DEFINE_DEVICE(4) #endif #if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) -static hpm_can_t dev_can5 = -{ - .can_base = HPM_MCAN5, - .name = "can5", - .irq_num = IRQn_MCAN5, -#if defined(BSP_MCAN5_IRQ_PRIORITY) - .irq_priority = BSP_MCAN5_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 5, - .clk_name = clock_can5, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan5_msg_buf, - .ram_size = sizeof(mcan5_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN5, can5_isr); -void can5_isr(void) -{ - hpm_mcan_isr(&dev_can5); -} +MCAN_DEFINE_DEVICE(5) #endif #if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) -static hpm_can_t dev_can6 = -{ - .can_base = HPM_MCAN6, - .name = "can6", - .irq_num = IRQn_MCAN6, -#if defined(BSP_MCAN6_IRQ_PRIORITY) - .irq_priority = BSP_MCAN6_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 6, - .clk_name = clock_can6, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan6_msg_buf, - .ram_size = sizeof(mcan6_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN6, can6_isr); -void can6_isr(void) -{ - hpm_mcan_isr(&dev_can6); -} +MCAN_DEFINE_DEVICE(6) #endif #if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) -static hpm_can_t dev_can7 = -{ - .can_base = HPM_MCAN7, - .name = "can7", - .irq_num = IRQn_MCAN7, -#if defined(BSP_MCAN7_IRQ_PRIORITY) - .irq_priority = BSP_MCAN7_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - .fifo_index = 7, - .clk_name = clock_can7, -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) - .ram_base = (uint32_t) &mcan7_msg_buf, - .ram_size = sizeof(mcan7_msg_buf), -#endif -}; -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN7, can7_isr); -void can7_isr(void) -{ - hpm_mcan_isr(&dev_can7); -} +MCAN_DEFINE_DEVICE(7) #endif +/* ============================================================================ + * Device Management Arrays + * ============================================================================ */ + +/** + * @brief Array of pointers to all enabled MCAN device instances + * + * This array is used by the initialization function to iterate through + * all enabled MCAN instances and register them with RT-Thread. + */ static hpm_can_t *hpm_cans[] = { #if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) - &dev_can0, + &dev_can0, #endif #if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) - &dev_can1, + &dev_can1, #endif #if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) - &dev_can2, + &dev_can2, #endif #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) - &dev_can3, + &dev_can3, #endif #if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) - &dev_can4, + &dev_can4, #endif #if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) - &dev_can5, + &dev_can5, #endif #if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) - &dev_can6, + &dev_can6, #endif #if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) - &dev_can7, + &dev_can7, #endif - }; - +}; +/** + * @brief RT-Thread CAN device operations structure + * + * This structure defines the function pointers that RT-Thread uses to + * interact with the MCAN driver. It implements the standard CAN device + * interface for RT-Thread. + */ static const struct rt_can_ops hpm_can_ops = { - .configure = hpm_mcan_configure, - .control = hpm_mcan_control, - .sendmsg = hpm_mcan_sendmsg, - .recvmsg = hpm_mcan_recvmsg, + .configure = hpm_mcan_configure, /**< Configure MCAN controller */ + .control = hpm_mcan_control, /**< Control MCAN device operations */ + .sendmsg = hpm_mcan_sendmsg, /**< Send CAN message */ + .recvmsg = hpm_mcan_recvmsg, /**< Receive CAN message */ }; +/* ============================================================================ + * Interrupt Service Routine + * ============================================================================ */ - +/** + * @brief MCAN interrupt service routine + * + * Handles all MCAN interrupts including transmission completion, reception, + * FIFO overflow, and error conditions. Updates RT-Thread CAN device status + * and notifies the framework of events. + * + * @param[in] hpm_can Pointer to HPM MCAN device structure + */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_mcan_isr(hpm_can_t *hpm_can) +#else +static void hpm_mcan_isr(int vector, hpm_can_t *hpm_can) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { uint8_t error_flags = mcan_get_last_error_code(hpm_can->can_base); uint32_t flags = mcan_get_interrupt_flags(hpm_can->can_base); mcan_error_count_t err_cnt; - /* Transmit completed */ + + /* Handle transmission completion interrupt */ if ((flags & (MCAN_EVENT_TRANSMIT)) != 0U) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); } - /* Data available in FIFO */ - if ((flags & MCAN_EVENT_RECEIVE) != 0) - { + /* Handle reception interrupt - data available in FIFO */ + if (((flags & MCAN_EVENT_RECEIVE) != 0) && ((hpm_can->can_stat != CAN_STOPPED) || (hpm_can->can_stat != CAN_UNITED))) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8)); } - /* RX FIFO overflow */ - if ((flags & MCAN_INT_RXFIFO0_FULL) != 0U) - { + /* Handle RX FIFO overflow interrupts */ + if (((flags & MCAN_INT_RXFIFO0_FULL) != 0U) && ((hpm_can->can_stat != CAN_STOPPED) || (hpm_can->can_stat != CAN_UNITED))) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); } - if ((flags & MCAN_INT_RXFIFO1_FULL) != 0U) - { + if (((flags & MCAN_INT_RXFIFO1_FULL) != 0U) && ((hpm_can->can_stat != CAN_STOPPED) || (hpm_can->can_stat != CAN_UNITED))) { rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); } - /* Error happened on CAN Bus */ - if (((flags & MCAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) - { + /* Handle CAN bus error conditions */ + if (((flags & MCAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) { mcan_get_error_counter(hpm_can->can_base, &err_cnt); - switch(error_flags) - { - case 3: + + /* Update specific error counters based on error type */ + switch (error_flags) { + case 3: /* Acknowledgment error */ hpm_can->can_dev.status.ackerrcnt++; break; - case 4: + case 4: /* Bit error */ hpm_can->can_dev.status.biterrcnt++; break; - case 6: + case 6: /* CRC error */ hpm_can->can_dev.status.crcerrcnt++; break; - case 2: + case 2: /* Form error */ hpm_can->can_dev.status.formaterrcnt++; break; - case 1: + case 1: /* Bit padding error */ hpm_can->can_dev.status.bitpaderrcnt++; break; } + /* Update error status information */ hpm_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; hpm_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count; hpm_can->can_dev.status.lasterrtype = mcan_get_last_error_code(hpm_can->can_base); hpm_can->can_dev.status.errcode = 0; - if ((error_flags & MCAN_INT_WARNING_STATUS) != 0U) - { + + /* Set error state flags */ + if ((error_flags & MCAN_INT_WARNING_STATUS) != 0U) { hpm_can->can_dev.status.errcode |= ERRWARNING; } - if ((error_flags & MCAN_INT_ERROR_PASSIVE) != 0U) - { + if ((error_flags & MCAN_INT_ERROR_PASSIVE) != 0U) { hpm_can->can_dev.status.errcode |= ERRPASSIVE; } - if (mcan_is_in_busoff_state(hpm_can->can_base)) - { + if (mcan_is_in_busoff_state(hpm_can->can_base)) { hpm_can->can_dev.status.errcode |= BUSOFF; } } + /* Clear all processed interrupt flags */ mcan_clear_interrupt_flags(hpm_can->can_base, flags); } +/* ============================================================================ + * Configuration Functions + * ============================================================================ */ + +/** + * @brief Configure MCAN controller + * + * Initializes the MCAN hardware with the specified configuration including + * baud rate, mode, timing parameters, and message filters. This function + * is called during device initialization and when configuration changes + * are requested. + * + * @param[in,out] can Pointer to RT-Thread CAN device structure + * @param[in] cfg Pointer to CAN configuration structure + * @return RT_EOK on success, -RT_ERROR on failure + */ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg) { RT_ASSERT(can); RT_ASSERT(cfg); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + hpm_can_t *drv_can = (hpm_can_t *)can->parent.user_data; RT_ASSERT(drv_can); #ifdef RT_CAN_USING_CANFD + /* Configure CAN-FD settings if supported */ drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false; - if (cfg->use_bit_timing != 0U) - { + /* Keep the existing MCAN config, only rebuild the RAM layout for current frame format. */ + mcan_get_default_ram_config(drv_can->can_base, + &drv_can->can_config.ram_config, + drv_can->can_config.enable_canfd); + + /* Configure bit timing parameters if custom timing is used */ + if (cfg->use_bit_timing != 0U) { drv_can->can_config.use_lowlevel_timing_setting = true; + + /* Configure classic CAN timing parameters */ drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler; drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1; drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2; drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw; + /* Configure CAN-FD timing parameters */ drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler; drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1; drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2; drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw; - } - else + } else #endif { + /* Use automatic baud rate calculation */ drv_can->can_config.use_lowlevel_timing_setting = false; drv_can->can_config.baudrate = cfg->baud_rate; #ifdef RT_CAN_USING_CANFD @@ -501,9 +632,8 @@ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configu #endif } - - switch (cfg->mode) - { + /* Configure CAN operation mode */ + switch (cfg->mode) { case RT_CAN_MODE_NORMAL: drv_can->can_config.mode = mcan_mode_normal; break; @@ -518,31 +648,46 @@ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configu break; } + /* Initialize CAN pins and clock */ init_can_pins(drv_can->can_base); clock_add_to_group(drv_can->clk_name, BOARD_RUNNING_CORE & 0x1); uint32_t can_clk = clock_get_frequency(drv_can->clk_name); - drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0]; - drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num; - drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; - drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; - drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL; - drv_can->can_config.txbuf_trans_interrupt_mask = ~0UL; + /* Configure message filters */ + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0]; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; + drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 29) - 1UL; + drv_can->can_config.txbuf_trans_interrupt_mask = ~0UL; + /* Initialize MCAN hardware with configuration */ hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk); - if (status != status_success) - { + if (status != status_success) { return -RT_ERROR; } + drv_can->can_stat = CAN_INITED; return RT_EOK; } +/** + * @brief Control MCAN device operations + * + * Handles various control commands including interrupt management, mode changes, + * baud rate configuration, filter setup, and status retrieval. This function + * implements the RT-Thread device control interface for CAN devices. + * + * @param[in,out] can Pointer to RT-Thread CAN device structure + * @param[in] cmd Control command (RT_DEVICE_CTRL_*, RT_CAN_CMD_*) + * @param[in,out] arg Command-specific argument pointer + * @return RT_EOK on success, -RT_ERROR on failure + */ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + hpm_can_t *drv_can = (hpm_can_t *)can->parent.user_data; RT_ASSERT(drv_can); uint32_t arg_val; @@ -551,46 +696,48 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) uint32_t temp; uint32_t irq_txrx_mask; - switch (cmd) - { + switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: - arg_val = (uint32_t) arg; + /* Disable specific interrupt types */ + arg_val = (uint32_t)arg; intc_m_disable_irq(drv_can->irq_num); - if (arg_val == RT_DEVICE_FLAG_INT_RX) - { + if (arg_val & RT_DEVICE_FLAG_INT_RX) { + /* Disable receive interrupt */ irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); } - else if (arg_val == RT_DEVICE_FLAG_INT_TX) - { + if (arg_val & RT_DEVICE_FLAG_INT_TX) { + /* Disable transmit interrupt */ irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL); - } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { + } + if (arg_val & RT_DEVICE_CAN_INT_ERR) { + /* Disable error interrupt */ irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); - } else { - err = -RT_ERROR; } break; + case RT_DEVICE_CTRL_SET_INT: - arg_val = (uint32_t) arg; - if (arg_val == RT_DEVICE_FLAG_INT_RX) - { + /* Enable specific interrupt types */ + arg_val = (uint32_t)arg; + if (arg_val & RT_DEVICE_FLAG_INT_RX) { + /* Enable receive interrupt */ irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } - else if (arg_val == RT_DEVICE_FLAG_INT_TX) - { + if (arg_val & RT_DEVICE_FLAG_INT_TX) { + /* Enable transmit interrupt */ irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; drv_can->can_config.interrupt_mask |= irq_txrx_mask; @@ -598,175 +745,176 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } - else if (arg_val == RT_DEVICE_CAN_INT_ERR) - { + if (arg_val & RT_DEVICE_CAN_INT_ERR) { + /* Enable error interrupt */ irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } - else - { - err = -RT_ERROR; - } break; - case RT_CAN_CMD_SET_FILTER: - { - /* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */ - struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg; - drv_can->std_filter_num = 0; - drv_can->ext_filter_num = 0; - if (filter != NULL) - { - for (uint32_t i = 0; i < filter->count; i++) - { - if (filter->items[i].ide != 0) - { - drv_can->ext_can_filters[drv_can->ext_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; - drv_can->ext_can_filters[drv_can->ext_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; - drv_can->ext_can_filters[drv_can->ext_filter_num].can_id_type = MCAN_CAN_ID_TYPE_EXTENDED; - drv_can->ext_can_filters[drv_can->ext_filter_num].filter_id = filter->items[i].id; - drv_can->ext_can_filters[drv_can->ext_filter_num].filter_mask = filter->items[i].mask; - drv_can->ext_filter_num++; - RT_ASSERT(drv_can->ext_filter_num <= CAN_EXT_FILTER_NUM_MAX); - } - else - { - drv_can->std_can_filters[drv_can->std_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; - drv_can->std_can_filters[drv_can->std_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; - drv_can->std_can_filters[drv_can->std_filter_num].can_id_type = MCAN_CAN_ID_TYPE_STANDARD; - drv_can->std_can_filters[drv_can->std_filter_num].filter_id = filter->items[i].id; - drv_can->std_can_filters[drv_can->std_filter_num].filter_mask = filter->items[i].mask; - drv_can->std_filter_num++; - RT_ASSERT(drv_can->std_filter_num <= CAN_STD_FILTER_NUM_MAX); + case RT_CAN_CMD_SET_FILTER: { + /* Configure message filters for CAN reception */ + struct rt_can_filter_config *filter = (struct rt_can_filter_config *)arg; + drv_can->std_filter_num = 0; + drv_can->ext_filter_num = 0; + + if (filter != NULL) { + /* Process each filter item in the configuration */ + for (uint32_t i = 0; i < filter->count; i++) { + if (filter->items[i].ide != 0) { + /* Configure extended ID filter */ + if (drv_can->ext_filter_num >= CAN_EXT_FILTER_NUM_MAX) { + return -RT_EFULL; } - if (filter->items[i].rtr != 0) - { - if (drv_can->ext_filter_num) - { - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; - } - else - { - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = true; - } - if (drv_can->std_filter_num) - { - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; - } - else - { - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = true; - } + filter->items[i].mask &= CAN_EXT_ID_MASK; /* Ensure mask is within valid range */ + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->ext_can_filters[drv_can->ext_filter_num].can_id_type = MCAN_CAN_ID_TYPE_EXTENDED; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_id = filter->items[i].id; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_mask = filter->items[i].mask; + drv_can->ext_filter_num++; + } else { + /* Configure standard ID filter */ + if (drv_can->std_filter_num >= CAN_STD_FILTER_NUM_MAX) { + return -RT_EFULL; } + filter->items[i].mask &= CAN_STD_ID_MASK; /* Ensure mask is within valid range */ + drv_can->std_can_filters[drv_can->std_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->std_can_filters[drv_can->std_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->std_can_filters[drv_can->std_filter_num].can_id_type = MCAN_CAN_ID_TYPE_STANDARD; + drv_can->std_can_filters[drv_can->std_filter_num].filter_id = filter->items[i].id; + drv_can->std_can_filters[drv_can->std_filter_num].filter_mask = filter->items[i].mask; + drv_can->std_filter_num++; } - - if (filter->actived != 0U) - { - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; - } - else - { - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + /* Handle RTR (Remote Transmission Request) frame filtering */ + if (filter->items[i].rtr != 0) { + if (drv_can->ext_filter_num) { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + } else { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = true; + } + if (drv_can->std_filter_num) { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + } else { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = true; + } } } - else - { - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; - drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; - drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; - drv_can->can_config.all_filters_config.ext_id_mask = 0x1FFFFFFFUL; - drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &k_default_std_id_filter; - drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = 1; - drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; - drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; + + /* Configure filter activation behavior */ + if (filter->actived != 0U) { + /* Reject non-matching frames when filters are active */ + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + } else { + /* Accept all frames when filters are not active */ + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; } - err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } else { + /* Use default filters when no filter configuration provided */ + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.ext_id_mask = 0x1FFFFFFFUL; + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &k_default_std_id_filter; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = 1; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; + } + /* Apply filter configuration to hardware */ + err = hpm_mcan_configure(can, &drv_can->can_dev.config); #ifdef RT_CAN_USING_HDR - if (filter == RT_NULL) { - /*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/ - err = -RT_ETRAP; - } -#endif + if (filter == RT_NULL) { + /* Special case for HDR: return error when using default filters */ + err = -RT_ETRAP; } - break; +#endif + } break; + case RT_CAN_CMD_SET_MODE: - arg_val = (uint32_t) arg; - if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK)) - { + /* Set CAN operation mode */ + arg_val = (uint32_t)arg; + if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK)) { err = -RT_ERROR; break; } - if (arg_val != drv_can->can_dev.config.mode) - { + if (arg_val != drv_can->can_dev.config.mode) { drv_can->can_dev.config.mode = arg_val; err = hpm_mcan_configure(can, &drv_can->can_dev.config); } - break; + case RT_CAN_CMD_SET_BAUD: - arg_val = (uint32_t) arg; - if (arg_val != drv_can->can_dev.config.baud_rate) - { + /* Set CAN baud rate */ + arg_val = (uint32_t)arg; +#ifdef RT_CAN_USING_CANFD + drv_can->can_dev.config.use_bit_timing = 0U; +#endif + if (arg_val != drv_can->can_dev.config.baud_rate) { drv_can->can_dev.config.baud_rate = arg_val; } err = hpm_mcan_configure(can, &drv_can->can_dev.config); break; #ifdef RT_CAN_USING_CANFD case RT_CAN_CMD_SET_CANFD: - arg_val = (uint32_t) arg; - if (arg_val != drv_can->can_dev.config.enable_canfd) - { + /* Enable/disable CAN-FD mode */ + arg_val = (uint32_t)arg; + if (arg_val != drv_can->can_dev.config.enable_canfd) { drv_can->can_dev.config.enable_canfd = arg_val; err = hpm_mcan_configure(can, &drv_can->can_dev.config); } break; + case RT_CAN_CMD_SET_BAUD_FD: - arg_val = (uint32_t) arg; - if (arg_val != drv_can->can_dev.config.baud_rate_fd) - { + /* Set CAN-FD data phase baud rate */ + arg_val = (uint32_t)arg; + drv_can->can_dev.config.use_bit_timing = 0U; + if (arg_val != drv_can->can_dev.config.baud_rate_fd) { drv_can->can_dev.config.baud_rate_fd = arg_val; err = hpm_mcan_configure(can, &drv_can->can_dev.config); } break; - case RT_CAN_CMD_SET_BITTIMING: - { - struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg; - if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2)) - { - return -RT_ERROR; - } - if (timing_configs->count != 0U) - { - drv_can->can_dev.config.can_timing = timing_configs->items[0]; - } - if (timing_configs->count == 2) - { - drv_can->can_dev.config.canfd_timing = timing_configs->items[1]; - } - err = hpm_mcan_configure(can, &drv_can->can_dev.config); + case RT_CAN_CMD_SET_BITTIMING: { + /* Set custom bit timing parameters */ + struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config *)arg; + if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2)) { + return -RT_ERROR; } - break; + + drv_can->can_dev.config.use_bit_timing = 1U; + /* Configure classic CAN timing (first item) */ + if (timing_configs->count != 0U) { + drv_can->can_dev.config.can_timing = timing_configs->items[0]; + } + /* Configure CAN-FD timing (second item) */ + if (timing_configs->count == 2) { + drv_can->can_dev.config.canfd_timing = timing_configs->items[1]; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } break; #endif case RT_CAN_CMD_SET_PRIV: + /* Set privacy mode (privileged/non-privileged) */ arg_val = (uint32_t)arg; - if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV)) - { + if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV)) { return -RT_ERROR; } - if (arg_val != drv_can->can_dev.config.privmode) - { + if (arg_val != drv_can->can_dev.config.privmode) { drv_can->can_dev.config.privmode = arg_val; err = hpm_mcan_configure(can, &drv_can->can_dev.config); } break; + case RT_CAN_CMD_GET_STATUS: + /* Get CAN controller status and error information */ mcan_error_count_t err_cnt; mcan_get_error_counter(drv_can->can_base, &err_cnt); drv_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; @@ -774,148 +922,215 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->can_dev.status.lasterrtype = mcan_get_last_error_code(drv_can->can_base); temp = mcan_get_interrupt_flags(drv_can->can_base); drv_can->can_dev.status.errcode = 0; - if ((temp & MCAN_INT_WARNING_STATUS) != 0U) - { + + /* Set error state flags */ + if ((temp & MCAN_INT_WARNING_STATUS) != 0U) { drv_can->can_dev.status.errcode |= ERRWARNING; } - if ((temp & MCAN_INT_ERROR_PASSIVE) != 0U) - { + if ((temp & MCAN_INT_ERROR_PASSIVE) != 0U) { drv_can->can_dev.status.errcode |= ERRPASSIVE; } - if (mcan_is_in_busoff_state(drv_can->can_base)) - { + if (mcan_is_in_busoff_state(drv_can->can_base)) { drv_can->can_dev.status.errcode |= BUSOFF; } rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; + + case RT_CAN_CMD_START: + arg_val = (rt_uint32_t)arg; + if (arg_val == 0) { + /* Stop CAN (enter Init Mode) */ + mcan_enter_init_mode(drv_can->can_base); + drv_can->can_stat = CAN_STOPPED; + } else { + /* 1. Clear all TX buffers */ + for (uint32_t i = 0; i < MCAN_TXBUF_SIZE_CAN_DEFAULT; i++) { + if (mcan_is_transmit_request_pending(drv_can->can_base, i)) { + mcan_cancel_tx_buf_send_request(drv_can->can_base, i); + } + } + rt_thread_mdelay(5); + /* 2. Clear all interrupt flags */ + mcan_clear_interrupt_flags(drv_can->can_base, 0xFFFFFFFF); + /* 3. Enter Normal Mode */ + mcan_enter_normal_mode(drv_can->can_base); + rt_thread_mdelay(5); + drv_can->can_stat = CAN_RUNNING; + } + break; } return err; } -static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +/* ============================================================================ + * Message Transmission and Reception Functions + * ============================================================================ */ + +/** + * @brief Send CAN message + * + * Transmits a CAN message through the specified MCAN instance. + * Supports both classic CAN and CAN-FD frames with proper frame formatting + * and transmission buffer management. + * + * @param[in] can Pointer to RT-Thread CAN device structure + * @param[in] buf Pointer to CAN message buffer + * @param[in] boxno Mailbox number (not used in this implementation) + * @return RT_EOK on success, -RT_ETIMEOUT on timeout, -RT_EFULL if buffer full + */ +static rt_ssize_t hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + hpm_can_t *drv_can = (hpm_can_t *)can->parent.user_data; RT_ASSERT(drv_can); - struct rt_can_msg *can_msg = (struct rt_can_msg *) buf; + struct rt_can_msg *can_msg = (struct rt_can_msg *)buf; + if ((drv_can->can_stat == CAN_UNITED) || (drv_can->can_stat == CAN_STOPPED)) { + return -RT_ERROR; + } - mcan_tx_frame_t tx_frame = {0}; + /* Initialize transmission frame structure */ + mcan_tx_frame_t tx_frame = { 0 }; memset(&tx_frame, 0, sizeof(tx_frame)); - if (can_msg->ide == RT_CAN_STDID) - { + + /* Configure CAN ID (standard or extended) */ + if (can_msg->ide == RT_CAN_STDID) { tx_frame.use_ext_id = 0; tx_frame.std_id = can_msg->id; - } - else - { + } else { tx_frame.use_ext_id = 1; tx_frame.ext_id = can_msg->id; } - if (can_msg->rtr == RT_CAN_DTR) - { + + /* Configure RTR (Remote Transmission Request) flag */ + if (can_msg->rtr == RT_CAN_DTR) { tx_frame.rtr = false; - } - else - { + } else { tx_frame.rtr = true; } - #ifdef RT_CAN_USING_CANFD +#ifdef RT_CAN_USING_CANFD + /* Configure CAN-FD specific parameters */ tx_frame.bitrate_switch = can_msg->brs; - if (can_msg->fd_frame != 0) - { - tx_frame.canfd_frame = 1; - RT_ASSERT(can_msg->len <= 15); - } - else - #endif + if (can_msg->fd_frame != 0) { + tx_frame.canfd_frame = 1; + RT_ASSERT(can_msg->len <= 15); /* CAN-FD supports up to 64 bytes (DLC 15) */ + } else +#endif { - RT_ASSERT(can_msg->len <= 8); + RT_ASSERT(can_msg->len <= 8); /* Classic CAN supports up to 8 bytes */ } + /* Copy message data to transmission frame */ uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); - for (uint32_t i = 0; i < msg_len; i++) - { + for (uint32_t i = 0; i < msg_len; i++) { tx_frame.data_8[i] = can_msg->data[i]; } tx_frame.dlc = can_msg->len; + /* Wait for transmission buffer to become available */ uint32_t delay_cnt = 0; - while (mcan_is_txfifo_full(drv_can->can_base)) - { + while (mcan_is_txfifo_full(drv_can->can_base)) { rt_thread_mdelay(1); delay_cnt++; - if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) - { + if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) { return -RT_ETIMEOUT; } } - hpm_stat_t status = mcan_transmit_via_txbuf_nonblocking(drv_can->can_base, 0, &tx_frame); - if (status != status_success) - { + + /* Transmit through TX FIFO to avoid overwriting a still-pending dedicated buffer. */ + hpm_stat_t status = mcan_transmit_via_txfifo_nonblocking(drv_can->can_base, &tx_frame, &drv_can->can_tx_fifo_index); + if (status != status_success) { return -RT_EFULL; } return RT_EOK; } -static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +/** + * @brief Receive CAN message + * + * Receives a CAN message from the MCAN RX FIFO. + * Supports both classic CAN and CAN-FD frames with proper frame parsing + * and data extraction. + * + * @param[in] can Pointer to RT-Thread CAN device structure + * @param[out] buf Pointer to receive buffer for CAN message + * @param[in] boxno Mailbox number (not used in this implementation) + * @return RT_EOK on success, -RT_ERROR on error, -RT_EMPTY if no data + */ +static rt_ssize_t hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) { RT_ASSERT(can); - hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + hpm_can_t *drv_can = (hpm_can_t *)can->parent.user_data; RT_ASSERT(drv_can); rt_can_msg_t can_msg = (rt_can_msg_t)buf; - mcan_rx_message_t rx_buf; + mcan_rx_message_t rx_buf = { 0 }; + + /* Read message from RX FIFO */ hpm_stat_t status = mcan_read_rxfifo(drv_can->can_base, 0, &rx_buf); - if (status == status_success) - { - if (rx_buf.use_ext_id) - { + if (status == status_success) { + /* Extract CAN ID information */ + if (rx_buf.use_ext_id) { can_msg->ide = RT_CAN_EXTID; can_msg->id = rx_buf.ext_id; - } - else - { + } else { can_msg->ide = RT_CAN_STDID; can_msg->id = rx_buf.std_id; } - + /* Extract RTR flag */ if (rx_buf.rtr != 0) { can_msg->rtr = RT_CAN_RTR; - } - else { + } else { can_msg->rtr = RT_CAN_DTR; } + #ifdef RT_CAN_USING_CANFD + /* Extract CAN-FD specific information */ can_msg->fd_frame = rx_buf.canfd_frame; can_msg->brs = rx_buf.bitrate_switch; #endif + + /* Extract message length and data */ can_msg->len = rx_buf.dlc; uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); - for(uint32_t i = 0; i < msg_len; i++) { + memset(can_msg->data, 0, sizeof(can_msg->data)); + for (uint32_t i = 0; i < msg_len; i++) { can_msg->data[i] = rx_buf.data_8[i]; } + #ifdef RT_CAN_USING_HDR - /* Hardware filter messages are valid */ + /* Update hardware filter status for HDR support */ can_msg->hdr_index = boxno; can->hdr[can_msg->hdr_index].connected = 1; #endif - } - else - { + } else { return -RT_EEMPTY; } return RT_EOK; } +/* ============================================================================ + * Initialization Function + * ============================================================================ */ + +/** + * @brief Initialize MCAN hardware and register devices with RT-Thread + * + * This function initializes all enabled MCAN instances, configures their + * default settings, and registers them with the RT-Thread device framework. + * It is called during system startup through the INIT_BOARD_EXPORT macro. + * + * @return RT_EOK on success + */ int rt_hw_mcan_init(void) { + /* Initialize default CAN configuration */ struct can_configure config = CANDEFAULTCONFIG; config.privmode = RT_CAN_MODE_NOPRIV; config.sndboxnumber = CAN_SENDBOX_NUM; @@ -923,22 +1138,35 @@ int rt_hw_mcan_init(void) #ifdef RT_CAN_USING_HDR config.maxhdr = 32; #endif - for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) - { + + /* Initialize each enabled MCAN instance */ + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { + /* Set default configuration */ hpm_cans[i]->can_dev.config = config; hpm_cans[i]->ext_filter_num = 0; hpm_cans[i]->std_filter_num = 0; + hpm_cans[i]->can_stat = CAN_UNITED; + #if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + /* Configure message buffer attributes for AHB RAM */ mcan_msg_buf_attr_t attr = { hpm_cans[i]->ram_base, hpm_cans[i]->ram_size }; hpm_stat_t status = mcan_set_msg_buf_attr(hpm_cans[i]->can_base, &attr); #endif + + /* Get default MCAN configuration from hardware */ mcan_get_default_config(hpm_cans[i]->can_base, &hpm_cans[i]->can_config); + + /* Register device with RT-Thread */ rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register MCAN device to irq table */ + rt_hw_interrupt_install(hpm_cans[i]->irq_num, (rt_isr_handler_t)hpm_mcan_isr, hpm_cans[i], hpm_cans[i]->name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return RT_EOK; } +/* Register initialization function to be called during board startup */ INIT_BOARD_EXPORT(rt_hw_mcan_init); -#endif - +#endif /* RT_USING_CAN */ diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.c b/bsp/hpmicro/libraries/drivers/drv_pdm.c index 8fa3d20a13..b1d0f7a97c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pdm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.c @@ -121,7 +121,15 @@ static rt_err_t hpm_pdm_set_channels(uint32_t channel) bool is_enabled = i2s_is_enabled(PDM_I2S); if (is_enabled) { - dma_abort_channel(dma_resource.base, dma_resource.channel); + dma_mgr_abort_chn_transfer(&dma_resource); + pdm_stop(HPM_PDM); + pdm_software_reset(HPM_PDM); + i2s_disable(PDM_I2S); + i2s_disable_rx_dma_request(PDM_I2S); + if (status_success != i2s_reset_rx(PDM_I2S)) { + LOG_E("pdm_i2s reset rx failed\n"); + return -RT_ERROR; + } } if (status_success != i2s_config_rx(PDM_I2S, mclk_hz, &transfer)) { @@ -130,7 +138,10 @@ static rt_err_t hpm_pdm_set_channels(uint32_t channel) } if (is_enabled) { - i2s_enable(PDM_I2S); + hpm_pdm_dma_transmit(); + pdm_start(HPM_PDM); + i2s_enable_rx_dma_request(PDM_I2S); + i2s_start(PDM_I2S); } return RT_EOK; @@ -161,6 +172,7 @@ static rt_err_t hpm_pdm_configure(struct rt_audio_device* audio, struct rt_audio result = -RT_ERROR; break; } + break; } default: @@ -184,7 +196,10 @@ static rt_err_t hpm_pdm_init(struct rt_audio_device* audio) i2s_get_default_config(PDM_I2S, &i2s_config); i2s_enable_rx_dma_request(PDM_I2S); - i2s_init(PDM_I2S, &i2s_config); + if (status_success != i2s_init(PDM_I2S, &i2s_config)) { + LOG_E("pdm_i2s init failed\n"); + return -RT_ERROR; + } i2s_get_default_transfer_config_for_pdm(&transfer); transfer.data_line = PDM_I2S_DATA_LINE; @@ -232,11 +247,14 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) return -RT_ERROR; } - i2s_reset_rx(PDM_I2S); + if (status_success != i2s_reset_rx(PDM_I2S)) { + LOG_E("pdm_i2s reset rx failed\n"); + return -RT_ERROR; + } + i2s_enable_rx_line(PDM_I2S, PDM_I2S_DATA_LINE); if (RT_EOK != hpm_pdm_dma_transmit()) { return -RT_ERROR; } - pdm_start(HPM_PDM); i2s_enable_rx_dma_request(PDM_I2S); i2s_start(PDM_I2S); @@ -253,14 +271,14 @@ static rt_err_t hpm_pdm_stop(struct rt_audio_device* audio, int stream) pdm_stop(HPM_PDM); i2s_stop(PDM_I2S); - dma_abort_channel(dma_resource.base, dma_resource.channel); + dma_mgr_abort_chn_transfer(&dma_resource); dma_mgr_release_resource(&dma_resource); } return RT_EOK; } -static rt_err_t hpm_pdm_dma_transmit() +static rt_err_t hpm_pdm_dma_transmit(void) { dma_channel_config_t ch_config = {0}; dma_default_channel_config(dma_resource.base, &ch_config); @@ -273,6 +291,7 @@ static rt_err_t hpm_pdm_dma_transmit() ch_config.size_in_byte = PDM_FIFO_SIZE; ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch_config.interrupt_mask = DMA_INTERRUPT_MASK_ABORT; if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.c b/bsp/hpmicro/libraries/drivers/drv_pwm.c index 7d1d0a4996..6e31ea6721 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pwm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2024 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,7 +8,9 @@ * 2022-05-09 HPMicro First version * 2023-04-12 HPMicro Adapt hpm_sdk v1.0.0 * 2023-05-13 HPMicro Fix compiling error on HPM6360/HPM6200 - * 2023-06-10 HPMicro Add PWMv2 support + * 2026-09-10 HPMicro Check shared counter frequency conflicts + * 2026-09-10 HPMicro Support optional RT-Thread PWM controls + * 2026-09-11 HPMicro Fix runtime updates and shared counter handling */ #include <rtthread.h> @@ -28,6 +30,16 @@ #endif #include "hpm_clock_drv.h" +#define PWM_CHANNEL_NUM PWM_SOC_PWM_MAX_COUNT + +typedef struct { + struct rt_pwm_configuration config; + uint32_t reload; + bool configured; + bool enabled; + bool irq_enabled; +} hpm_pwm_channel_state_t; + #ifdef HPM_PWM3 #define PWM_INSTANCE_NUM 4 #elif defined(HPM_PWM2) @@ -55,33 +67,20 @@ static PWM_Type * pwm_base_tbl[PWM_INSTANCE_NUM] = { #endif }; -#if defined(HPMSOC_HAS_HPMSDK_PWMV2) +static hpm_pwm_channel_state_t pwm_channel_state[PWM_INSTANCE_NUM][PWM_CHANNEL_NUM]; -#ifdef PWMV2_CNT_3 -#define PWMV2_CNT_NUM 4 -#elif PWMV2_CNT_2 -#define PWMV2_CNT_NUM 3 -#elif PWMV2_CNT_1 -#define PWMV2_CNT_NUM 2 -#else -#define PWMV2_CNT_NUM 1 -#endif +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) +#define PWMV2_RELOAD_MAX 0xFFFFFFU -static pwm_counter_t pwmv2_counter_tbl[PWMV2_CNT_NUM * 2] = { +static const pwm_counter_t pwmv2_counter_tbl[PWM_CHANNEL_NUM] = { pwm_counter_0, pwm_counter_0, -#ifdef PWMV2_CNT_1 pwm_counter_1, pwm_counter_1, -#endif -#ifdef PWMV2_CNT_2 pwm_counter_2, pwm_counter_2, -#endif -#ifdef PWMV2_CNT_3 pwm_counter_3, pwm_counter_3, -#endif }; #endif @@ -91,7 +90,228 @@ extern uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr); extern uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr); #endif -rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) +static rt_err_t hpm_pwm_calculate_timing(uint8_t pwm_index, uint32_t period, uint32_t pulse, + uint32_t *reload, uint32_t *duty) +{ + uint32_t freq; + uint64_t reload_ticks; + uint64_t duty_ticks; + + if ((pwm_index >= PWM_INSTANCE_NUM) || (period == 0U) || (pulse > period)) { + return -RT_EINVAL; + } + + freq = rtt_board_init_pwm_clock(pwm_base_tbl[pwm_index]); + reload_ticks = (uint64_t)freq * period / 1000000000U; + duty_ticks = (uint64_t)freq * pulse / 1000000000U; + + if ((reload_ticks == 0U) || (reload_ticks > UINT32_MAX)) { + return -RT_EINVAL; + } +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + if (reload_ticks > PWMV2_RELOAD_MAX) { + return -RT_EINVAL; + } +#else + if (reload_ticks > PWM_RLD_RLD_GET(PWM_RLD_RLD_MASK)) { + return -RT_EINVAL; + } +#endif + + *reload = (uint32_t)reload_ticks; + *duty = (uint32_t)duty_ticks; + + return RT_EOK; +} + +static rt_err_t hpm_pwm_calculate_dead_time(uint8_t pwm_index, uint32_t dead_time, + uint32_t *dead_ticks) +{ + uint32_t freq; + uint64_t ticks; + + if (pwm_index >= PWM_INSTANCE_NUM) { + return -RT_EINVAL; + } + + if (dead_time == 0U) { + *dead_ticks = 0U; + return RT_EOK; + } + + freq = rtt_board_init_pwm_clock(pwm_base_tbl[pwm_index]); +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + ticks = ((uint64_t)freq * dead_time + 999999999U) / 1000000000U; + /* Values below two clocks disable dead-area insertion. */ + if (ticks < 2U) { + ticks = 2U; + } + if (ticks > UINT16_MAX) { + return -RT_EINVAL; + } +#else + ticks = ((uint64_t)freq * dead_time * 2U + 999999999U) / 1000000000U; + /* The dead-area unit is half a clock and the hardware minimum is one clock. */ + if (ticks < 2U) { + ticks = 2U; + } + if (ticks > PWM_PWMCFG_DEADAREA_GET(PWM_PWMCFG_DEADAREA_MASK)) { + return -RT_EINVAL; + } +#endif + + *dead_ticks = (uint32_t)ticks; + return RT_EOK; +} + +static bool hpm_pwm_use_complementary(uint8_t channel, bool requested) +{ + /* RT-Thread cannot represent negative channel zero, so keep channel zero as normal output. */ + return requested && (channel != 0U); +} + +static bool hpm_pwm_channel_has_pair(uint8_t channel) +{ + return ((channel & 1U) == 0U) && ((channel + 1U) < PWM_CHANNEL_NUM); +} + +static rt_err_t hpm_pwm_validate_configuration(uint8_t pwm_index, + const struct rt_pwm_configuration *config, + uint32_t *reload, uint32_t *duty, + uint32_t *dead_ticks) +{ + bool complementary; + + if (config->phase > 360U) { + return -RT_EINVAL; + } + + complementary = hpm_pwm_use_complementary(config->channel, config->complementary); + if (complementary && !hpm_pwm_channel_has_pair(config->channel)) { + return -RT_EINVAL; + } + + if (hpm_pwm_calculate_timing(pwm_index, config->period, config->pulse, + reload, duty) != RT_EOK) { + return -RT_EINVAL; + } + + return hpm_pwm_calculate_dead_time(pwm_index, config->dead_time, dead_ticks); +} + +static void hpm_pwm_calculate_compare(uint32_t reload, uint32_t duty, uint32_t phase, + uint32_t *cmp_a, uint32_t *cmp_b, bool *invert) +{ + uint32_t phase_ticks; + uint64_t start; + uint64_t end; + + phase_ticks = (uint32_t)((uint64_t)reload * (phase % 360U) / 360U); + start = (uint64_t)((reload - duty) >> 1) + phase_ticks; + end = ((uint64_t)reload + duty) / 2U + phase_ticks; + *invert = false; + + if (start >= reload) { + start -= reload; + end -= reload; + } else if (end > reload) { + uint32_t wrapped_end = end - reload; + + end = start; + start = wrapped_end; + *invert = true; + } + *cmp_a = (uint32_t)start; + *cmp_b = (uint32_t)end; +} + +static bool hpm_pwm_channel_shares_counter(uint8_t channel_a, uint8_t channel_b) +{ +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + return (channel_a / 2U) == (channel_b / 2U); +#else + (void)channel_a; + (void)channel_b; + return true; +#endif +} + +static bool hpm_pwm_counter_is_active(uint8_t pwm_index, uint8_t channel) +{ + uint8_t index; + + for (index = 0; index < PWM_CHANNEL_NUM; index++) { + if (pwm_channel_state[pwm_index][index].enabled + && hpm_pwm_channel_shares_counter(channel, index)) { + return true; + } + } + + return false; +} + +static void hpm_pwm_stop_counter(uint8_t pwm_index, uint8_t channel) +{ +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + pwmv2_disable_counter(pwm_base_tbl[pwm_index], pwmv2_counter_tbl[channel]); +#else + (void)channel; + pwm_stop_counter(pwm_base_tbl[pwm_index]); +#endif +} + +static rt_err_t hpm_pwm_check_frequency_conflict(uint8_t pwm_index, uint8_t channel, uint32_t reload) +{ + uint8_t index; + + for (index = 0; index < PWM_CHANNEL_NUM; index++) { + if ((index != channel) + && pwm_channel_state[pwm_index][index].enabled + && hpm_pwm_channel_shares_counter(channel, index) + && (pwm_channel_state[pwm_index][index].reload != reload)) { + rt_kprintf("pwm%u channel %u conflicts with enabled channel %u: " + "shared counter requires the same frequency\n", + (unsigned int)pwm_index, (unsigned int)channel, (unsigned int)index); + return -RT_EINVAL; + } + } + + return RT_EOK; +} + +static rt_err_t hpm_pwm_check_pair_conflict(uint8_t pwm_index, + const struct rt_pwm_configuration *config) +{ + uint8_t channel = config->channel; + bool complementary = hpm_pwm_use_complementary(channel, config->complementary); + + if (complementary && !hpm_pwm_channel_has_pair(channel)) { + return -RT_EINVAL; + } + + if (complementary && pwm_channel_state[pwm_index][channel + 1U].enabled) { + rt_kprintf("pwm%u channel %u conflicts with enabled channel %u: " + "complementary output requires the channel pair\n", + (unsigned int)pwm_index, (unsigned int)channel, + (unsigned int)(channel + 1U)); + return -RT_EBUSY; + } + + if (((channel & 1U) != 0U) + && pwm_channel_state[pwm_index][channel - 1U].enabled + && hpm_pwm_use_complementary(channel - 1U, + pwm_channel_state[pwm_index][channel - 1U].config.complementary)) { + rt_kprintf("pwm%u channel %u is used by complementary channel %u\n", + (unsigned int)pwm_index, (unsigned int)channel, + (unsigned int)(channel - 1U)); + return -RT_EBUSY; + } + + return RT_EOK; +} + +static rt_err_t hpm_generate_central_aligned_waveform( + uint8_t pwm_index, const struct rt_pwm_configuration *config) { #if defined(HPMSOC_HAS_HPMSDK_PWMV2) PWMV2_Type * pwm_base; @@ -100,31 +320,41 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe PWM_Type * pwm_base; pwm_cmp_config_t cmp_config[2] = {0}; pwm_config_t pwm_config = {0}; + pwm_pair_config_t pair_config = {0}; #endif + uint8_t channel = config->channel; uint32_t duty; - uint32_t reload = 0; - uint32_t freq; + uint32_t reload; + uint32_t dead_ticks; + uint32_t cmp_a; + uint32_t cmp_b; + bool complementary; + bool counter_active; + bool invert; + pwm_base = pwm_base_tbl[pwm_index]; init_pwm_pins(pwm_base); - freq = rtt_board_init_pwm_clock(pwm_base); - if(period != 0) { - reload = (uint64_t)freq * period / 1000000000; - } else { - reload = 0; + if (hpm_pwm_validate_configuration(pwm_index, config, &reload, &duty, + &dead_ticks) != RT_EOK) { + return -RT_EINVAL; } - duty = (uint64_t)freq * pulse / 1000000000; + complementary = hpm_pwm_use_complementary(channel, config->complementary); + counter_active = hpm_pwm_counter_is_active(pwm_index, channel); + hpm_pwm_calculate_compare(reload, duty, config->phase, &cmp_a, &cmp_b, &invert); #if defined(HPMSOC_HAS_HPMSDK_PWMV2) pwm_counter = pwmv2_counter_tbl[channel]; - pwmv2_disable_counter(pwm_base, pwm_counter); - pwmv2_reset_counter(pwm_base, pwm_counter); + if (!counter_active) { + pwmv2_disable_counter(pwm_base, pwm_counter); + pwmv2_reset_counter(pwm_base, pwm_counter); + } pwmv2_shadow_register_unlock(pwm_base); pwmv2_set_shadow_val(pwm_base, channel / 2, reload, 0, false); /**< cnt use 0-3 shadow */ - pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, reload + 1, 0, false); + pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, reload, 0, false); pwmv2_set_shadow_val(pwm_base, channel * 2 + 5, reload, 0, false); pwmv2_counter_select_data_offset_from_shadow_value(pwm_base, pwm_counter, channel / 2); @@ -135,47 +365,84 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe pwmv2_select_cmp_source(pwm_base, channel * 2 + 1, cmp_value_from_shadow_val, channel * 2 + 5); pwmv2_shadow_register_lock(pwm_base); + pwmv2_cmp_update_trig_time(pwm_base, channel * 2, + pwm_shadow_register_update_on_reload); + pwmv2_cmp_update_trig_time(pwm_base, channel * 2 + 1, + pwm_shadow_register_update_on_reload); pwmv2_disable_four_cmp(pwm_base, channel); + if (invert) { + pwmv2_enable_output_invert(pwm_base, channel); + } else { + pwmv2_disable_output_invert(pwm_base, channel); + } + pwmv2_disable_pair_mode(pwm_base, channel & ~1U); + pwmv2_disable_pair_mode(pwm_base, (channel & ~1U) + 1U); + if (complementary) { + pwmv2_set_dead_area(pwm_base, channel, dead_ticks); + pwmv2_set_dead_area(pwm_base, channel + 1U, dead_ticks); + pwmv2_enable_pair_mode(pwm_base, channel); + pwmv2_enable_pair_mode(pwm_base, channel + 1U); + pwmv2_channel_enable_output(pwm_base, channel + 1U); + } pwmv2_channel_enable_output(pwm_base, channel); pwmv2_enable_counter(pwm_base, pwm_counter); pwmv2_start_pwm_output(pwm_base, pwm_counter); pwmv2_shadow_register_unlock(pwm_base); - pwmv2_set_shadow_val(pwm_base, channel * 2, (reload - duty) >> 1, 0, false); - pwmv2_set_shadow_val(pwm_base, channel * 2, (reload + duty) >> 1, 0, false); + pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, cmp_a, 0, false); + pwmv2_set_shadow_val(pwm_base, channel * 2 + 5, cmp_b, 0, false); pwmv2_shadow_register_lock(pwm_base); #else - pwm_stop_counter(pwm_base); - pwm_get_default_pwm_config(pwm_base, &pwm_config); + if (!counter_active) { + pwm_stop_counter(pwm_base); + } /* * reload and start counter */ pwm_set_reload(pwm_base, 0, reload); - pwm_set_start_count(pwm_base, 0, 0); + if (!counter_active) { + pwm_set_start_count(pwm_base, 0, 0); + } /* * config cmp1 and cmp2 */ cmp_config[0].mode = pwm_cmp_mode_output_compare; - cmp_config[0].cmp = (reload - duty) >> 1; + cmp_config[0].cmp = cmp_a; cmp_config[0].update_trigger = pwm_shadow_register_update_on_shlk; cmp_config[1].mode = pwm_cmp_mode_output_compare; - cmp_config[1].cmp = (reload + duty) >> 1; + cmp_config[1].cmp = cmp_b; cmp_config[1].update_trigger = pwm_shadow_register_update_on_shlk; - - pwm_config.enable_output = true; - pwm_config.dead_zone_in_half_cycle = 0; - pwm_config.invert_output = false; /* * config pwm */ - if (status_success != pwm_setup_waveform(pwm_base, channel, &pwm_config, channel * 2, cmp_config, 2)) { - return -RT_ERROR; + if (complementary) { + pwm_get_default_pwm_pair_config(pwm_base, &pair_config); + pair_config.pwm[0].enable_output = true; + pair_config.pwm[0].dead_zone_in_half_cycle = dead_ticks; + pair_config.pwm[0].invert_output = invert; + pair_config.pwm[1].enable_output = true; + pair_config.pwm[1].dead_zone_in_half_cycle = dead_ticks; + pair_config.pwm[1].invert_output = invert; + if (status_success != pwm_setup_waveform_in_pair(pwm_base, channel, &pair_config, + channel * 2, cmp_config, 2)) { + return -RT_ERROR; + } + } else { + pwm_get_default_pwm_config(pwm_base, &pwm_config); + pwm_config.enable_output = true; + pwm_config.invert_output = invert; + if (status_success != pwm_setup_waveform(pwm_base, channel, &pwm_config, + channel * 2, cmp_config, 2)) { + return -RT_ERROR; + } + pwm_base->PWMCFG[channel & ~1U] &= ~PWM_PWMCFG_PAIR_MASK; + pwm_base->PWMCFG[(channel & ~1U) + 1U] &= ~PWM_PWMCFG_PAIR_MASK; } pwm_start_counter(pwm_base); pwm_issue_shadow_register_lock_event(pwm_base); @@ -185,165 +452,321 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe } -rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) +static rt_err_t hpm_set_central_aligned_waveform( + uint8_t pwm_index, const struct rt_pwm_configuration *config) { #if defined(HPMSOC_HAS_HPMSDK_PWMV2) PWMV2_Type * pwm_base; #else PWM_Type * pwm_base; - pwm_config_t pwm_config = {0}; #endif - + uint8_t channel = config->channel; uint32_t duty; - uint32_t reload = 0; - uint32_t freq; + uint32_t reload; + uint32_t dead_ticks; + uint32_t cmp_a; + uint32_t cmp_b; + bool complementary; + bool invert; pwm_base = pwm_base_tbl[pwm_index]; - freq = rtt_board_init_pwm_clock(pwm_base); - if(period != 0) { - reload = (uint64_t)freq * period / 1000000000; - } else { - reload = 0; + if (hpm_pwm_validate_configuration(pwm_index, config, &reload, &duty, + &dead_ticks) != RT_EOK) { + return -RT_EINVAL; } - duty = (uint64_t)freq * pulse / 1000000000; + complementary = hpm_pwm_use_complementary(channel, config->complementary); + hpm_pwm_calculate_compare(reload, duty, config->phase, &cmp_a, &cmp_b, &invert); #if defined(HPMSOC_HAS_HPMSDK_PWMV2) pwmv2_shadow_register_unlock(pwm_base); pwmv2_set_shadow_val(pwm_base, channel / 2, reload, 0, false); /**< cnt use 0-3 shadow */ - pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, (reload - duty) >> 1, 0, false); - pwmv2_set_shadow_val(pwm_base, channel * 2 + 5, (reload + duty) >> 1, 0, false); + pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, cmp_a, 0, false); + pwmv2_set_shadow_val(pwm_base, channel * 2 + 5, cmp_b, 0, false); pwmv2_shadow_register_lock(pwm_base); + if (invert) { + pwmv2_enable_output_invert(pwm_base, channel); + } else { + pwmv2_disable_output_invert(pwm_base, channel); + } + if (complementary) { + pwmv2_set_dead_area(pwm_base, channel, dead_ticks); + pwmv2_set_dead_area(pwm_base, channel + 1U, dead_ticks); + } #else - pwm_get_default_pwm_config(pwm_base, &pwm_config); + if (complementary) { + pwm_disable_output(pwm_base, channel); + pwm_disable_output(pwm_base, channel + 1U); + } pwm_set_reload(pwm_base, 0, reload); - pwm_update_raw_cmp_central_aligned(pwm_base, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); + pwm_shadow_register_unlock(pwm_base); + pwm_cmp_update_cmp_value(pwm_base, channel * 2, cmp_a, 0); + pwm_cmp_update_cmp_value(pwm_base, channel * 2 + 1, cmp_b, 0); + pwm_base->CHCFG[channel] = (pwm_base->CHCFG[channel] & ~PWM_CHCFG_OUTPOL_MASK) + | PWM_CHCFG_OUTPOL_SET(invert); + if (complementary) { + pwm_base->CHCFG[channel + 1U] = + (pwm_base->CHCFG[channel + 1U] & ~PWM_CHCFG_OUTPOL_MASK) + | PWM_CHCFG_OUTPOL_SET(invert); + pwm_base->PWMCFG[channel] = (pwm_base->PWMCFG[channel] & ~PWM_PWMCFG_DEADAREA_MASK) + | PWM_PWMCFG_PAIR_MASK + | PWM_PWMCFG_DEADAREA_SET(dead_ticks); + pwm_base->PWMCFG[channel + 1U] = + (pwm_base->PWMCFG[channel + 1U] & ~PWM_PWMCFG_DEADAREA_MASK) + | PWM_PWMCFG_PAIR_MASK + | PWM_PWMCFG_DEADAREA_SET(dead_ticks); + pwm_enable_output(pwm_base, channel); + pwm_enable_output(pwm_base, channel + 1U); + } pwm_issue_shadow_register_lock_event(pwm_base); #endif return RT_EOK; } -rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel) +static rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel, bool complementary) { #if defined(HPMSOC_HAS_HPMSDK_PWMV2) - PWMV2_Type * pwm_base; - - pwm_base = pwm_base_tbl[pwm_index]; - pwmv2_shadow_register_unlock(pwm_base); - pwmv2_set_shadow_val(pwm_base, channel * 2 + 4, 0, 0, false); - pwmv2_set_shadow_val(pwm_base, channel * 2 + 5, 0, 0, false); - pwmv2_shadow_register_lock(pwm_base); + pwmv2_channel_disable_output(pwm_base_tbl[pwm_index], channel); + if (complementary) { + pwmv2_channel_disable_output(pwm_base_tbl[pwm_index], channel + 1U); + } #else pwm_disable_output(pwm_base_tbl[pwm_index], channel); + if (complementary) { + pwm_disable_output(pwm_base_tbl[pwm_index], channel + 1U); + } #endif return RT_EOK; } -rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg) +static rt_err_t hpm_pwm_update_configuration(uint8_t pwm_index, + hpm_pwm_channel_state_t *state, + struct rt_pwm_configuration *config) { - uint8_t channel; - uint32_t period; - uint32_t pulse; - rt_err_t sta = RT_EOK; - unsigned char pwm_name; - struct rt_pwm_configuration * configuration; - configuration = (struct rt_pwm_configuration * )arg; - channel = configuration->channel; - period = configuration->period; - pulse = configuration->pulse; - if (strcmp("pwm0", device->parent.parent.name) == 0) { - pwm_name = 0; - } else if (strcmp("pwm1", device->parent.parent.name) == 0) { - pwm_name = 1; - } else if (strcmp("pwm2", device->parent.parent.name) == 0) { - pwm_name = 2; - } else if (strcmp("pwm3", device->parent.parent.name) == 0) { - pwm_name = 3; - } else { - return -RT_ERROR; + uint32_t reload; + uint32_t duty; + uint32_t dead_ticks; + rt_err_t status; + + config->complementary = hpm_pwm_use_complementary(config->channel, + config->complementary); + status = hpm_pwm_validate_configuration(pwm_index, config, &reload, &duty, + &dead_ticks); + if (status != RT_EOK) { + return status; + } + status = hpm_pwm_check_frequency_conflict(pwm_index, config->channel, reload); + if (status != RT_EOK) { + return status; + } + status = hpm_pwm_check_pair_conflict(pwm_index, config); + if (status != RT_EOK) { + return status; } - switch(cmd) { - case PWM_CMD_ENABLE: { - sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse); - break; - } - case PWM_CMD_DISABLE: { - hpm_disable_pwm(pwm_name, channel); - break; + if (state->enabled) { + status = hpm_set_central_aligned_waveform(pwm_index, config); + if (status != RT_EOK) { + return status; } - case PWM_CMD_SET: { - sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse); - break; + } + + state->config = *config; + state->reload = reload; + state->configured = true; + return RT_EOK; +} + +static rt_err_t hpm_pwm_set_reload_irq(uint8_t pwm_index, uint8_t channel, bool enable) +{ + uint8_t index; + bool shared_irq_enabled = false; + + pwm_channel_state[pwm_index][channel].irq_enabled = enable; + if (!enable) { + for (index = 0; index < PWM_CHANNEL_NUM; index++) { + if ((index != channel) + && pwm_channel_state[pwm_index][index].irq_enabled + && hpm_pwm_channel_shares_counter(channel, index)) { + shared_irq_enabled = true; + break; + } } - case PWM_CMD_GET: { - sta = RT_EOK; - break; + } + + if (enable || !shared_irq_enabled) { +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + if (enable) { + pwmv2_clear_reload_irq_status(pwm_base_tbl[pwm_index], + 1U << pwmv2_counter_tbl[channel]); + pwmv2_enable_reload_irq(pwm_base_tbl[pwm_index], pwmv2_counter_tbl[channel]); + } else { + pwmv2_disable_reload_irq(pwm_base_tbl[pwm_index], pwmv2_counter_tbl[channel]); } - default: { - sta = -RT_ERROR; - break; +#else + if (enable) { + pwm_clear_status(pwm_base_tbl[pwm_index], PWM_IRQ_RELOAD); + pwm_enable_irq(pwm_base_tbl[pwm_index], PWM_IRQ_RELOAD); + } else { + pwm_disable_irq(pwm_base_tbl[pwm_index], PWM_IRQ_RELOAD); } +#endif } - return sta; + + return RT_EOK; } -rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg) +static rt_err_t hpm_pwm_execute_control_impl(uint8_t pwm_index, int cmd, + struct rt_pwm_configuration *configuration) { - uint8_t channel; - uint32_t period; - uint32_t pulse; - rt_err_t sta = RT_EOK; - uint8_t pwm_name; - struct rt_pwm_configuration * configuration; - configuration = (struct rt_pwm_configuration * )arg; - channel = configuration->channel; - period = configuration->period; - pulse = configuration->pulse; - if (strcmp("pwm0", device->parent.name) == 0) { - pwm_name = 0; - } else if (strcmp("pwm1", device->parent.name) == 0) { - pwm_name = 1; - } else if (strcmp("pwm2", device->parent.name) == 0) { - pwm_name = 2; - } else if (strcmp("pwm3", device->parent.name) == 0) { - pwm_name = 3; - } else { - return -RT_ERROR; + hpm_pwm_channel_state_t *state; + struct rt_pwm_configuration config; + bool release_complementary_output; + rt_err_t status; + + if ((configuration == RT_NULL) || (pwm_index >= PWM_INSTANCE_NUM) + || (configuration->channel >= PWM_CHANNEL_NUM)) { + return -RT_EINVAL; } - switch(cmd) { - case PWM_CMD_ENABLE: { - sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse); - break; + state = &pwm_channel_state[pwm_index][configuration->channel]; + + switch (cmd) { + case PWM_CMD_ENABLE: + if (!state->configured) { + rt_kprintf("pwm%u channel %u has not been configured\n", + (unsigned int)pwm_index, (unsigned int)configuration->channel); + return -RT_EINVAL; } - case PWM_CMD_DISABLE: { - hpm_disable_pwm(pwm_name, channel); - break; + config = state->config; + config.complementary = hpm_pwm_use_complementary(config.channel, + configuration->complementary); + status = hpm_pwm_check_frequency_conflict(pwm_index, config.channel, state->reload); + if (status != RT_EOK) { + return status; } - case PWM_CMD_SET: { - sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse); - break; + status = hpm_pwm_check_pair_conflict(pwm_index, &config); + if (status != RT_EOK) { + return status; } - case PWM_CMD_GET: { - sta = RT_EOK; - break; + release_complementary_output = state->enabled + && state->config.complementary + && !config.complementary; + if (release_complementary_output) { +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + pwmv2_channel_disable_output(pwm_base_tbl[pwm_index], config.channel + 1U); +#else + pwm_disable_output(pwm_base_tbl[pwm_index], config.channel + 1U); +#endif } - default: { - sta = -RT_ERROR; - break; + status = hpm_generate_central_aligned_waveform(pwm_index, &config); + if (status == RT_EOK) { + state->config = config; + state->enabled = true; + } else if (release_complementary_output) { +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) + pwmv2_channel_enable_output(pwm_base_tbl[pwm_index], config.channel + 1U); +#else + pwm_enable_output(pwm_base_tbl[pwm_index], config.channel + 1U); +#endif + } + return status; + + case PWM_CMD_DISABLE: + status = hpm_disable_pwm(pwm_index, configuration->channel, + state->configured && state->config.complementary); + if (status == RT_EOK) { + state->enabled = false; + if (!hpm_pwm_counter_is_active(pwm_index, configuration->channel)) { + hpm_pwm_stop_counter(pwm_index, configuration->channel); + } + } + return status; + + case PWM_CMD_SET: + config = *configuration; + if (state->configured) { + config.dead_time = state->config.dead_time; + config.phase = state->config.phase; + config.complementary = state->config.complementary; + } + return hpm_pwm_update_configuration(pwm_index, state, &config); + + case PWM_CMD_GET: + if (!state->configured) { + return -RT_EINVAL; } + *configuration = state->config; + return RT_EOK; + + case PWM_CMD_SET_PERIOD: + if (!state->configured) { + return -RT_EINVAL; + } + config = state->config; + config.period = configuration->period; + return hpm_pwm_update_configuration(pwm_index, state, &config); + + case PWM_CMD_SET_PULSE: + if (!state->configured) { + return -RT_EINVAL; + } + config = state->config; + config.pulse = configuration->pulse; + return hpm_pwm_update_configuration(pwm_index, state, &config); + + case PWM_CMD_SET_DEAD_TIME: + if (!state->configured) { + return -RT_EINVAL; + } + config = state->config; + config.dead_time = configuration->dead_time; + return hpm_pwm_update_configuration(pwm_index, state, &config); + + case PWM_CMD_SET_PHASE: + if (!state->configured) { + return -RT_EINVAL; + } + config = state->config; + config.phase = configuration->phase; + return hpm_pwm_update_configuration(pwm_index, state, &config); + + case PWM_CMD_ENABLE_IRQ: + return hpm_pwm_set_reload_irq(pwm_index, configuration->channel, true); + + case PWM_CMD_DISABLE_IRQ: + return hpm_pwm_set_reload_irq(pwm_index, configuration->channel, false); + + default: + return -RT_EINVAL; } - return sta; } -const static struct rt_pwm_ops hpm_pwm_ops = { - .control = &hpm_pwm_control -}; +static rt_err_t hpm_pwm_execute_control(uint8_t pwm_index, int cmd, + struct rt_pwm_configuration *configuration) +{ + rt_base_t critical_level; + rt_err_t status; + + critical_level = rt_enter_critical(); + status = hpm_pwm_execute_control_impl(pwm_index, cmd, configuration); + rt_exit_critical_safe(critical_level); -static struct rt_device hpm_pwm_parent = { - .control = hpm_pwm_dev_control + return status; +} + +static rt_err_t hpm_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + uint8_t pwm_index; + + pwm_index = (uint8_t)(rt_ubase_t)device->parent.user_data; + + return hpm_pwm_execute_control(pwm_index, cmd, (struct rt_pwm_configuration *)arg); +} + +static const struct rt_pwm_ops hpm_pwm_ops = { + .control = &hpm_pwm_control }; #ifdef HPM_PWM0 @@ -376,21 +799,33 @@ int rt_hw_pwm_init(void) int ret = RT_EOK; #ifdef HPM_PWM0 - hpm_dev_pwm0.parent = hpm_pwm_parent; - ret = rt_device_pwm_register(&hpm_dev_pwm0, "pwm0", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm0, "pwm0", &hpm_pwm_ops, + (void *)(rt_ubase_t)0U); + if (ret != RT_EOK) { + return ret; + } #endif #ifdef HPM_PWM1 - hpm_dev_pwm1.parent = hpm_pwm_parent; - ret = rt_device_pwm_register(&hpm_dev_pwm1, "pwm1", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm1, "pwm1", &hpm_pwm_ops, + (void *)(rt_ubase_t)1U); + if (ret != RT_EOK) { + return ret; + } #endif #ifdef HPM_PWM2 - hpm_dev_pwm2.parent = hpm_pwm_parent; - ret = rt_device_pwm_register(&hpm_dev_pwm2, "pwm2", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm2, "pwm2", &hpm_pwm_ops, + (void *)(rt_ubase_t)2U); + if (ret != RT_EOK) { + return ret; + } #endif #ifdef HPM_PWM3 - hpm_dev_pwm3.parent = hpm_pwm_parent; - ret = rt_device_pwm_register(&hpm_dev_pwm3, "pwm3", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm3, "pwm3", &hpm_pwm_ops, + (void *)(rt_ubase_t)3U); + if (ret != RT_EOK) { + return ret; + } #endif return ret; diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.c b/bsp/hpmicro/libraries/drivers/drv_rtc.c index c87e23cf05..a73a3d992c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_rtc.c +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -67,10 +67,18 @@ static struct rt_device hpm_rtc= { #endif }; +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +static struct rtc_isr_t { + RTC_Type *rtc_base; + struct rt_device *rtc_dev; +} hpm_rtc_isr; +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + /***************************************************** * RTC interrupt handler ******************************************************/ #ifdef RT_USING_ALARM +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void rtc_isr(void) { uint32_t rtc_alarm_flag = rtc_get_alarm_flags(HPM_RTC); @@ -80,7 +88,20 @@ void rtc_isr(void) } rtc_clear_alarm_flags(HPM_RTC, RTC_ALARM_FLAG_ALARM0_MASK | RTC_ALARM_FLAG_ALARM1_MASK); } -RTT_DECLARE_EXT_ISR_M(IRQn_RTC, rtc_isr); +SDK_DECLARE_EXT_ISR_M(IRQn_RTC, rtc_isr); +#else +void rtc_isr(int vector, struct rtc_isr_t *hpm_rtc) +{ + RTC_Type *rtc_base = hpm_rtc->rtc_base; + struct rt_device *rtc_dev = hpm_rtc->rtc_dev; + uint32_t rtc_alarm_flag = rtc_get_alarm_flags(rtc_base); + if ((rtc_alarm_flag & RTC_ALARM_FLAG_ALARM0_MASK) != 0) + { + rt_alarm_update(rtc_dev, 1); + } + rtc_clear_alarm_flags(rtc_base, RTC_ALARM_FLAG_ALARM0_MASK | RTC_ALARM_FLAG_ALARM1_MASK); +} +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ #endif /******************************************************************************************* * @@ -117,6 +138,11 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args) struct timeval tv; + if (args == RT_NULL) + { + return -RT_EINVAL; + } + switch(cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: if (sizeof(uint32_t) == sizeof(time_t)) { @@ -143,7 +169,7 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args) err = hpm_rtc_get_alarm((struct rt_rtc_wkalarm *)args); break; default: - err = RT_EINVAL; + err = -RT_EINVAL; break; } @@ -248,6 +274,15 @@ int rt_hw_rtc_init(void) rt_device_open(&hpm_rtc, RT_DEVICE_FLAG_RDWR); +#ifdef RT_USING_ALARM +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + hpm_rtc_isr.rtc_base = HPM_RTC; + hpm_rtc_isr.rtc_dev = &hpm_rtc; + /* Register RTC device to irq table */ + rt_hw_interrupt_install(IRQn_RTC, (rt_isr_handler_t)rtc_isr, &hpm_rtc_isr, "RTC"); +#endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + return RT_EOK; } diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c index f820c7e0d3..cd601a5661 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.c +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -28,7 +28,6 @@ #include "hpm_sdxc_drv.h" #include "hpm_l1c_drv.h" - #define CACHELINE_SIZE HPM_L1C_CACHELINE_SIZE #define SDXC_ADMA_TABLE_WORDS SDXC_AMDA3_DESC_MIN_WORDS #define SDXC_AMDA_ADDR_ALIGNMENT (4U) @@ -97,7 +96,7 @@ static hpm_stat_t hpm_sdmmc_transfer_polling(struct hpm_mmcsd *mmcsd, sdxc_adma_ static hpm_stat_t hpm_sdmmc_transfer_interrupt_driven(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); static hpm_stat_t hpm_sdmmc_transfer(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode); -static rt_err_t hpm_sdmmc_signal_voltage_switch(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); +static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host); static void hpm_sdmmc_power_on_via_pin(struct hpm_mmcsd *mmcsd); static void hpm_sdmmc_power_off_via_pin(struct hpm_mmcsd *mmcsd); @@ -152,7 +151,7 @@ static void hpm_sdmmc_switch_to_1v8_via_pin(struct hpm_mmcsd *mmcsd) } -static rt_err_t hpm_sdmmc_signal_voltage_switch(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host) { struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; SDXC_Type *base = mmcsd->sdxc_base; @@ -174,17 +173,9 @@ static rt_err_t hpm_sdmmc_signal_voltage_switch(struct rt_mmcsd_host *host, stru return -RT_ETIMEOUT; } - /* 3. Switch to 1.8V/3.3V */ - if (ios->signal_voltage == MMCSD_SIGNAL_VOLTAGE_330) - { - hpm_sdmmc_switch_to_3v3_via_pin(mmcsd); - sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_3v3); - } - else - { - hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); - sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); - } + /* 3. Switch to 1.8V */ + hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); + sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); /* 4. spec:host delay 5ms, host: give more delay time here */ rt_thread_mdelay(10); @@ -221,7 +212,7 @@ static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = .get_card_status = NULL, .enable_sdio_irq = hpm_sdmmc_enable_sdio_irq, .execute_tuning = hpm_sdmmc_execute_tuning, - .signal_voltage_switch = hpm_sdmmc_signal_voltage_switch, + .switch_uhs_voltage = hpm_sdmmc_switch_uhs_voltage, }; void hpm_sdmmc_isr(struct hpm_mmcsd *mmcsd) @@ -249,7 +240,6 @@ void hpm_sdmmc_isr(struct hpm_mmcsd *mmcsd) } #if defined(BSP_USING_SDXC0) -void sdxc0_isr(void); /* Place the ADMA table to non-cacheable region */ ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) static uint32_t s_sdxc0_adma_table[SDXC_ADMA_TABLE_WORDS]; @@ -316,15 +306,16 @@ static struct hpm_mmcsd s_hpm_sdxc0 = .data_buf_size = BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE, #endif }; -SDK_DECLARE_EXT_ISR_M(IRQn_SDXC0, sdxc0_isr); +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void sdxc0_isr(void) { hpm_sdmmc_isr(&s_hpm_sdxc0); } +SDK_DECLARE_EXT_ISR_M(IRQn_SDXC0, sdxc0_isr); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ #endif #if defined(BSP_USING_SDXC1) -void sdxc1_isr(void); /* Place the ADMA table to non-cacheable region */ ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) static uint32_t s_sdxc1_adma_table[SDXC_ADMA_TABLE_WORDS]; #if defined(BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR) @@ -388,13 +379,22 @@ static struct hpm_mmcsd s_hpm_sdxc1 = .data_buf_size = BSP_SDXC1_CACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE, #endif }; -SDK_DECLARE_EXT_ISR_M(IRQn_SDXC1, sdxc1_isr); +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void sdxc1_isr(void) { hpm_sdmmc_isr(&s_hpm_sdxc1); } +SDK_DECLARE_EXT_ISR_M(IRQn_SDXC1, sdxc1_isr); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ #endif +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +void sdxc_isr(int vector, struct hpm_mmcsd *sdxc) +{ + hpm_sdmmc_isr(sdxc); +} +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + static struct hpm_mmcsd *hpm_sdxcs[] = { #if defined(BSP_USING_SDXC0) @@ -1170,6 +1170,11 @@ int rt_hw_sdio_init(void) intc_m_enable_irq_with_priority(mmcsd->irq_num, mmcsd->irq_priority); mmcsd_change(host); + +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register SDXC device to irq table */ + rt_hw_interrupt_install(mmcsd->irq_num, (rt_isr_handler_t)sdxc_isr, hpm_sdxcs[i], mmcsd->name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } if (err != RT_EOK) diff --git a/bsp/hpmicro/libraries/drivers/drv_soft_i2c.c b/bsp/hpmicro/libraries/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..5aa0139fe5 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_soft_i2c.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "drv_soft_i2c.h" +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> +#include "rtt_board.h" + +#ifdef BSP_USING_SOFT_I2C + +#define DBG_TAG "drv.soft_i2c" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +/* + * I2C device structure initialization macro + * This macro initializes a soft I2C configuration structure with pin names and bus name + * Usage: I2C_INIT_STRUCT(n) where n is the I2C number (1-8) + */ +#define I2C_INIT_STRUCT(n) \ + { \ + .scl_pin_name = BSP_SOFT_I2C##n##_SCL_PIN, \ + .sda_pin_name = BSP_SOFT_I2C##n##_SDA_PIN, \ + .bus_name = "soft_i2c"#n, \ + } + +/* + * Dynamically build configuration array using weak symbol. + * Users define I2C configuration macros in board.h or rtconfig.h: + #define I2C1_BUS_CONFIG \ + { \ + .scl = "PD20", \ + .sda = "PD21", \ + .bus_name = "i2c1", \ + } + */ + +ATTR_WEAK struct hpm_soft_i2c_config soft_i2c_configs[] = { +#if defined(BSP_USING_SOFT_I2C0) + I2C_INIT_STRUCT(0), +#endif + +#if defined(BSP_USING_SOFT_I2C1) + I2C_INIT_STRUCT(1), +#endif + +#if defined(BSP_USING_SOFT_I2C2) + I2C_INIT_STRUCT(2), +#endif + +#if defined(BSP_USING_SOFT_I2C3) + I2C_INIT_STRUCT(3), +#endif + +#if defined(BSP_USING_SOFT_I2C4) + I2C_INIT_STRUCT(4), +#endif + +#if defined(BSP_USING_SOFT_I2C5) + I2C_INIT_STRUCT(5), +#endif + +#if defined(BSP_USING_SOFT_I2C6) + I2C_INIT_STRUCT(6), +#endif + +#if defined(BSP_USING_SOFT_I2C7) + I2C_INIT_STRUCT(7), +#endif + +#if defined(BSP_USING_SOFT_I2C8) + I2C_INIT_STRUCT(8), +#endif +}; + +/* Number of soft I2C devices configured */ +#define SOFT_I2C_PTRS_NUM (sizeof(soft_i2c_configs) / sizeof(soft_i2c_configs[0])) + +static struct hpm_i2c i2c_obj[SOFT_I2C_PTRS_NUM]; + +/** + * This function initializes the i2c pin. + * + * @param hpm i2c driver class. + */ +static void hpm_i2c_gpio_init(struct hpm_i2c *i2c) +{ + struct hpm_soft_i2c_config* cfg = (struct hpm_soft_i2c_config*)i2c->ops.data; + rt_base_t scl_pin = rt_pin_get(cfg->scl_pin_name); + rt_base_t sda_pin = rt_pin_get(cfg->sda_pin_name); + if (scl_pin < 0 || sda_pin < 0) + { + LOG_E("i2c bus %s pin init error!", cfg->bus_name); + return; + } + + rt_pin_mode(scl_pin, PIN_MODE_OUTPUT_OD); + rt_pin_mode(sda_pin, PIN_MODE_OUTPUT_OD); + + rt_pin_write(scl_pin, PIN_HIGH); + rt_pin_write(sda_pin, PIN_HIGH); +} + +static void hpm_i2c_pin_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct hpm_i2c); + + for(rt_size_t i = 0; i < obj_num; i++) + { + hpm_i2c_gpio_init(&i2c_obj[i]); + } +} + +/** + * This function sets the sda pin. + * + * @param hpm config class. + * @param The sda pin state. + */ +static void hpm_set_sda(void *data, rt_int32_t state) +{ + struct hpm_soft_i2c_config* cfg = (struct hpm_soft_i2c_config*)data; + rt_base_t sda_pin = rt_pin_get(cfg->sda_pin_name); + if (state) + { + rt_pin_write(sda_pin, PIN_HIGH); + } + else + { + rt_pin_write(sda_pin, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param hpm config class. + * @param The scl pin state. + */ +static void hpm_set_scl(void *data, rt_int32_t state) +{ + struct hpm_soft_i2c_config* cfg = (struct hpm_soft_i2c_config*)data; + rt_base_t scl_pin = rt_pin_get(cfg->scl_pin_name); + if (state) + { + rt_pin_write(scl_pin, PIN_HIGH); + } + else + { + rt_pin_write(scl_pin, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t hpm_get_sda(void *data) +{ + struct hpm_soft_i2c_config* cfg = (struct hpm_soft_i2c_config*)data; + rt_base_t sda_pin = rt_pin_get(cfg->sda_pin_name); + return rt_pin_read(sda_pin); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t hpm_get_scl(void *data) +{ + struct hpm_soft_i2c_config* cfg = (struct hpm_soft_i2c_config*)data; + rt_base_t scl_pin = rt_pin_get(cfg->scl_pin_name); + return rt_pin_read(scl_pin); +} + +static const struct rt_i2c_bit_ops hpm_bit_ops_default = +{ + .data = RT_NULL, + .pin_init = hpm_i2c_pin_init, + .set_sda = hpm_set_sda, + .set_scl = hpm_set_scl, + .get_sda = hpm_get_sda, + .get_scl = hpm_get_scl, + .udelay = rt_hw_us_delay, + .delay_us = BSP_USING_SOFT_I2C_TIMING_DELAY_US, + .timeout = BSP_USING_SOFT_I2C_TIMING_TIMEOUT, + .i2c_pin_init_flag = RT_FALSE +}; + +/** + * if i2c is locked, this function will unlock it + * + * @param hpm config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t hpm_i2c_bus_unlock(const struct hpm_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + rt_base_t sda_pin = rt_pin_get(cfg->sda_pin_name); + rt_base_t scl_pin = rt_pin_get(cfg->scl_pin_name); + if (PIN_LOW == rt_pin_read(sda_pin)) + { + while (i++ < 9) + { + rt_pin_write(scl_pin, PIN_HIGH); + rt_hw_us_delay(100); + rt_pin_write(scl_pin, PIN_LOW); + rt_hw_us_delay(100); + } + } + if (PIN_LOW == rt_pin_read(sda_pin)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_software_i2c_init(void) +{ + rt_err_t result = RT_EOK; + for (rt_size_t i = 0; i < SOFT_I2C_PTRS_NUM; i++) + { + if ((soft_i2c_configs[i].scl_pin_name == RT_NULL) + || (soft_i2c_configs[i].sda_pin_name == RT_NULL)) + { + LOG_E("soft i2c%d pin config error!", i); + result = -RT_ERROR; + continue; + } + if ((rt_strcmp(soft_i2c_configs[i].scl_pin_name, "None") == 0) + || (rt_strcmp(soft_i2c_configs[i].sda_pin_name, "None") == 0)) + { + LOG_E("soft i2c%d pin name is None, please check!", i); + result = -RT_ERROR; + continue; + } + i2c_obj[i].ops = hpm_bit_ops_default; + i2c_obj[i].ops.data = (void*)&soft_i2c_configs[i]; + i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_configs[i].bus_name); + RT_ASSERT(result == RT_EOK); + hpm_i2c_bus_unlock(&soft_i2c_configs[i]); + LOG_D("software simulation %s init done, pin scl: %s, pin sda %s", + soft_i2c_configs[i].bus_name, + soft_i2c_configs[i].scl_pin_name, + soft_i2c_configs[i].sda_pin_name); + } + + return result; +} +INIT_BOARD_EXPORT(rt_software_i2c_init); + +#endif /* BSP_USING_SOFT_I2C */ diff --git a/bsp/hpmicro/libraries/drivers/drv_soft_i2c.h b/bsp/hpmicro/libraries/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..384e13e18a --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_soft_i2c.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DRV_SOFT_I2C__ +#define __DRV_SOFT_I2C__ + +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> + +/* HPM config class */ +struct hpm_soft_i2c_config +{ + const char *scl_pin_name; + const char *sda_pin_name; + const char *bus_name; +}; + +/* HPM i2c driver class */ +struct hpm_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c_bus; +}; + +int rt_hw_i2c_init(void); + +#endif /* __DRV_SOFT_I2C__ */ diff --git a/bsp/hpmicro/libraries/drivers/drv_soft_spi.c b/bsp/hpmicro/libraries/drivers/drv_soft_spi.c new file mode 100644 index 0000000000..7d2282fbea --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_soft_spi.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "drv_soft_spi.h" +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> +#include "rtt_board.h" + +#ifdef BSP_USING_SOFT_SPI +#include <dev_spi_bit_ops.h> + +#define DBG_TAG "drv.soft_spi" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +/* + * SPI device structure initialization macro + * This macro initializes a soft SPI configuration structure with pin names and bus name + * Usage: SPI_INIT_STRUCT(n) where n is the SPI number (0-2) + */ +#define SPI_INIT_STRUCT(n) \ + { \ + .sck_pin_name = BSP_SOFT_SPI##n##_SCK_PIN, \ + .mosi_pin_name = BSP_SOFT_SPI##n##_MOSI_PIN, \ + .miso_pin_name = BSP_SOFT_SPI##n##_MISO_PIN, \ + .bus_name = "soft_spi"#n, \ + } + +/* + * Dynamically build configuration array using weak symbol. + * Users define SPI configuration macros in board.h or rtconfig.h: + #define SPI1_BUS_CONFIG \ + { \ + .sck = "PD20", \ + .mosi = "PD21", \ + .miso = "PD22", \ + .bus_name = "spi1", \ + } + */ + +ATTR_WEAK struct hpm_soft_spi_config soft_spi_configs[] = { +#if defined(BSP_USING_SOFT_SPI0) + SPI_INIT_STRUCT(0), +#endif + +#if defined(BSP_USING_SOFT_SPI1) + SPI_INIT_STRUCT(1), +#endif + +#if defined(BSP_USING_SOFT_SPI2) + SPI_INIT_STRUCT(2), +#endif +}; + +/* Number of soft SPI devices configured */ +#define SOFT_SPI_PTRS_NUM (sizeof(soft_spi_configs) / sizeof(soft_spi_configs[0])) + +static struct hpm_soft_spi spi_obj[SOFT_SPI_PTRS_NUM]; + +/** + * This function initializes the spi pin. + * + * @param hpm spi driver class. + */ +static void hpm_spi_gpio_init(struct hpm_soft_spi *spi) +{ + /* use cfg pointer stored in our hpm_soft_spi instance */ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)spi->cfg; + rt_base_t sck_pin = rt_pin_get(cfg->sck_pin_name); + rt_base_t mosi_pin = rt_pin_get(cfg->mosi_pin_name); + rt_base_t miso_pin = rt_pin_get(cfg->miso_pin_name); + if (sck_pin < 0 || mosi_pin < 0 || miso_pin < 0) + { + LOG_E("spi bus %s pin init error!", cfg->bus_name); + return; + } + + rt_pin_mode(sck_pin, PIN_MODE_OUTPUT); + rt_pin_mode(mosi_pin, PIN_MODE_OUTPUT); + rt_pin_mode(miso_pin, PIN_MODE_INPUT); + + rt_pin_write(sck_pin, PIN_HIGH); + rt_pin_write(mosi_pin, PIN_HIGH); +} + +static void hpm_spi_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct hpm_soft_spi); + + for(rt_size_t i = 0; i < obj_num; i++) + { + hpm_spi_gpio_init(&spi_obj[i]); + } +} + +/** + * This function toggle the sck pin. + * + * @param hpm config class. + */ +static void hpm_tog_sck(void *data) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t sck_pin = rt_pin_get(cfg->sck_pin_name); + if(rt_pin_read(sck_pin) == PIN_HIGH) + { + rt_pin_write(sck_pin, PIN_LOW); + } + else + { + rt_pin_write(sck_pin, PIN_HIGH); + } +} + +/** + * This function sets the sck pin. + * + * @param hpm config class. + * @param The sck pin state. + */ +static void hpm_set_sck(void *data, rt_int32_t state) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t sck_pin = rt_pin_get(cfg->sck_pin_name); + if (state) + { + rt_pin_write(sck_pin, PIN_HIGH); + } + else + { + rt_pin_write(sck_pin, PIN_LOW); + } +} + +/** + * This function sets the mosi pin. + * + * @param hpm config class. + * @param The mosi pin state. + */ +static void hpm_set_mosi(void *data, rt_int32_t state) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t mosi_pin = rt_pin_get(cfg->mosi_pin_name); + if (state) + { + rt_pin_write(mosi_pin, PIN_HIGH); + } + else + { + rt_pin_write(mosi_pin, PIN_LOW); + } +} + +/** + * This function sets the miso pin. + * + * @param hpm config class. + * @param The miso pin state. + */ +static void hpm_set_miso(void *data, rt_int32_t state) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t miso_pin = rt_pin_get(cfg->miso_pin_name); + if (state) + { + rt_pin_write(miso_pin, PIN_HIGH); + } + else + { + rt_pin_write(miso_pin, PIN_LOW); + } +} + +/** + * This function gets the sck pin state. + * + * @param The sck pin state. + */ +static rt_int32_t hpm_get_sck(void *data) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t sck_pin = rt_pin_get(cfg->sck_pin_name); + return rt_pin_read(sck_pin); +} + +/** + * This function gets the mosi pin state. + * + * @param The mosi pin state. + */ +static rt_int32_t hpm_get_mosi(void *data) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t mosi_pin = rt_pin_get(cfg->mosi_pin_name); + return rt_pin_read(mosi_pin); +} + +/** + * This function gets the miso pin state. + * + * @param The miso pin state. + */ +static rt_int32_t hpm_get_miso(void *data) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t miso_pin = rt_pin_get(cfg->miso_pin_name); + return rt_pin_read(miso_pin); +} + +/** + * This function sets the mosi pin direction (input/output). + * + * @param hpm config class. + * @param state: 1 for input, 0 for output. + */ +static void hpm_dir_mosi(void *data, rt_int32_t state) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t mosi_pin = rt_pin_get(cfg->mosi_pin_name); + if (state) + { + rt_pin_mode(mosi_pin, PIN_MODE_INPUT); + } + else + { + rt_pin_mode(mosi_pin, PIN_MODE_OUTPUT); + } +} + +/** + * This function sets the miso pin direction (input/output). + * + * @param hpm config class. + * @param state: 1 for input, 0 for output. + */ +static void hpm_dir_miso(void *data, rt_int32_t state) +{ + struct hpm_soft_spi_config* cfg = (struct hpm_soft_spi_config*)data; + rt_base_t miso_pin = rt_pin_get(cfg->miso_pin_name); + if (state) + { + rt_pin_mode(miso_pin, PIN_MODE_INPUT); + } + else + { + rt_pin_mode(miso_pin, PIN_MODE_OUTPUT); + } +} + +/** + * This function provides microsecond delay. + * + * @param us: microseconds to delay. + */ +static void hpm_spi_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +static const struct rt_spi_bit_ops hpm_bit_ops_default = +{ + .data = RT_NULL, + .pin_init = hpm_spi_pin_init, + .tog_sclk = hpm_tog_sck, + .set_sclk = hpm_set_sck, + .set_mosi = hpm_set_mosi, + .set_miso = hpm_set_miso, + .get_sclk = hpm_get_sck, + .get_mosi = hpm_get_mosi, + .get_miso = hpm_get_miso, + .dir_mosi = hpm_dir_mosi, + .dir_miso = hpm_dir_miso, + .udelay = hpm_spi_udelay, + .delay_us = BSP_USING_SOFT_SPI_TIMING_DELAY_US, +}; + +/** + * Attach the spi device to soft SPI bus, this function must be used after initialization. + * + * @param bus_name: soft spi bus name. + * @param device_name: spi device name. + * @param pin_name: chip select pin name. + * + * @return RT_EOK indicates successful attachment. + */ +rt_err_t rt_hw_soft_spi_device_attach(const char *bus_name, const char *device_name, const char *pin_name) +{ + rt_err_t result; + struct rt_spi_device *spi_device; + + /* initialize the cs pin && select the slave */ + rt_base_t cs_pin = rt_pin_get(pin_name); + rt_pin_mode(cs_pin, PIN_MODE_OUTPUT); + rt_pin_write(cs_pin, PIN_HIGH); + + /* attach the device to soft spi bus */ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result == RT_EOK) + { + LOG_D("soft spi device %s attach to %s success (cs_pin: %s)", + device_name, bus_name, pin_name); + } + else + { + LOG_E("soft spi device %s attach to %s failed", device_name, bus_name); + } + + return result; +} + +/* SPI initialization function */ +int rt_software_spi_init(void) +{ + rt_err_t result = RT_EOK; + + for (rt_size_t i = 0; i < SOFT_SPI_PTRS_NUM; i++) + { + if ((soft_spi_configs[i].sck_pin_name == RT_NULL) + || (soft_spi_configs[i].mosi_pin_name == RT_NULL) || (soft_spi_configs[i].miso_pin_name == RT_NULL)) + { + LOG_E("soft spi%d pin config error!", i); + result = -RT_ERROR; + continue; + } + if ((rt_strcmp(soft_spi_configs[i].sck_pin_name, "None") == 0) + || (rt_strcmp(soft_spi_configs[i].mosi_pin_name, "None") == 0) + || (rt_strcmp(soft_spi_configs[i].miso_pin_name, "None") == 0)) + { + LOG_E("soft spi%d pin name is None, please check!", i); + result = -RT_ERROR; + continue; + } + /* copy default ops into instance, set private data, and register bit-banged bus */ + rt_memcpy(&spi_obj[i].ops, &hpm_bit_ops_default, sizeof(struct rt_spi_bit_ops)); + spi_obj[i].ops.data = (void*)&soft_spi_configs[i]; + /* point bus.ops to our instance ops */ + spi_obj[i].spi.ops = &spi_obj[i].ops; + spi_obj[i].cfg = (void *)&soft_spi_configs[i]; + /* initialize gpio for this instance */ + hpm_spi_gpio_init(&spi_obj[i]); + result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_configs[i].bus_name, &spi_obj[i].ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("software simulation %s init done, pin sck: %s, pin mosi: %s, pin miso: %s", + soft_spi_configs[i].bus_name, + soft_spi_configs[i].sck_pin_name, + soft_spi_configs[i].mosi_pin_name, + soft_spi_configs[i].miso_pin_name); + } + + return result; +} +INIT_BOARD_EXPORT(rt_software_spi_init); + +#endif /* BSP_USING_SOFT_SPI */ diff --git a/bsp/hpmicro/libraries/drivers/drv_soft_spi.h b/bsp/hpmicro/libraries/drivers/drv_soft_spi.h new file mode 100644 index 0000000000..21c56bcd87 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_soft_spi.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DRV_SOFT_SPI__ +#define __DRV_SOFT_SPI__ + +#include <rtthread.h> +#ifdef BSP_USING_SOFT_SPI +#include <rthw.h> +#include <rtdevice.h> +/* rt_spi_bit_ops is defined in dev_spi_bit_ops.h */ +#include <dev_spi_bit_ops.h> + +/* HPM config class */ +struct hpm_soft_spi_config +{ + const char *sck_pin_name; + const char *mosi_pin_name; + const char *miso_pin_name; + const char *bus_name; +}; + +/* HPM spi driver class */ +struct hpm_soft_spi +{ + struct rt_spi_bit_obj spi; /* bit-banged spi object (contains rt_spi_bus inside) */ + struct rt_spi_bit_ops ops; /* local copy of bit ops */ + void *cfg; /* pointer to hpm_soft_spi_config */ +}; + +int rt_hw_spi_init(void); +rt_err_t rt_hw_soft_spi_device_attach(const char *bus_name, const char *device_name, const char *pin_name); +#endif /* BSP_USING_SOFT_SPI */ + +#endif /* __DRV_SOFT_SPI__ */ diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.c b/bsp/hpmicro/libraries/drivers/drv_spi.c index bfdfd26276..5b5ece2a21 100644 --- a/bsp/hpmicro/libraries/drivers/drv_spi.c +++ b/bsp/hpmicro/libraries/drivers/drv_spi.c @@ -31,6 +31,7 @@ #define DBG_LVL DBG_INFO #include <rtdbg.h> +/* Set default IO mode to SINGLE_IO if not specified */ #if defined(BSP_USING_SPI0) #ifndef BSP_SPI0_USING_QUAD_IO #ifndef BSP_SPI0_USING_DUAL_IO @@ -146,279 +147,271 @@ typedef struct { static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); static rt_ssize_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg); -static struct hpm_spi hpm_spis[] = -{ -#if defined(BSP_USING_SPI0) - { +/* Macros to reduce repetitive SPI configuration code */ +#define HPM_SPI_BUS_NAME_MODE(idx) HPM_SPI_BUS_NAME_MODE_##idx +#define HPM_SPI_IO_MODE(idx) HPM_SPI_IO_MODE_##idx + +/* Bus name based on IO mode */ #if defined(BSP_SPI0_USING_SINGLE_IO) - .bus_name = "spi0", - .spi_io_mode = spi_single_io_mode, -#endif -#if defined(BSP_SPI0_USING_DUAL_IO) - .bus_name = "dspi0", - .spi_io_mode = spi_dual_io_mode, -#endif -#if defined(BSP_SPI0_USING_QUAD_IO) - .bus_name = "qspi0", - .spi_io_mode = spi_quad_io_mode, +#define HPM_SPI_BUS_NAME_MODE_0 .bus_name = "spi0", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI0_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_0 .bus_name = "dspi0", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI0_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_0 .bus_name = "qspi0", .spi_io_mode = spi_quad_io_mode, #endif - .spi_base = HPM_SPI0, - .clk_name = clock_spi0, -#if defined(BSP_SPI0_USING_DMA) - .enable_dma = RT_TRUE, -#endif - .tx_dmamux = HPM_DMA_SRC_SPI0_TX, - .rx_dmamux = HPM_DMA_SRC_SPI0_RX, - .spi_irq = IRQn_SPI0, -#if defined(BSP_SPI0_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI0_IRQ_PRIORITY, -#else - .spi_irq_priority = 1, -#endif -#if !defined BSP_SPI0_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, -#else - .spi_pins_init = init_spi_pins, + +#if defined(BSP_SPI1_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_1 .bus_name = "spi1", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI1_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_1 .bus_name = "dspi1", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI1_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_1 .bus_name = "qspi1", .spi_io_mode = spi_quad_io_mode, +#endif + +#if defined(BSP_SPI2_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_2 .bus_name = "spi2", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI2_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_2 .bus_name = "dspi2", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI2_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_2 .bus_name = "qspi2", .spi_io_mode = spi_quad_io_mode, #endif - }, + +#if defined(BSP_SPI3_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_3 .bus_name = "spi3", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI3_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_3 .bus_name = "dspi3", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI3_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_3 .bus_name = "qspi3", .spi_io_mode = spi_quad_io_mode, #endif -#if defined(BSP_USING_SPI1) - { -#if defined(BSP_SPI1_USING_SINGLE_IO) - .bus_name = "spi1", - .spi_io_mode = spi_single_io_mode, + +#if defined(BSP_SPI4_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_4 .bus_name = "spi4", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI4_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_4 .bus_name = "dspi4", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI4_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_4 .bus_name = "qspi4", .spi_io_mode = spi_quad_io_mode, #endif -#if defined(BSP_SPI1_USING_DUAL_IO) - .bus_name = "dspi1", - .spi_io_mode = spi_dual_io_mode, + +#if defined(BSP_SPI5_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_5 .bus_name = "spi5", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI5_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_5 .bus_name = "dspi5", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI5_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_5 .bus_name = "qspi5", .spi_io_mode = spi_quad_io_mode, #endif -#if defined(BSP_SPI1_USING_QUAD_IO) - .bus_name = "qspi1", - .spi_io_mode = spi_quad_io_mode, + +#if defined(BSP_SPI6_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_6 .bus_name = "spi6", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI6_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_6 .bus_name = "dspi6", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI6_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_6 .bus_name = "qspi6", .spi_io_mode = spi_quad_io_mode, #endif - .spi_base = HPM_SPI1, - .clk_name = clock_spi1, -#if defined(BSP_SPI1_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_SPI7_USING_SINGLE_IO) +#define HPM_SPI_BUS_NAME_MODE_7 .bus_name = "spi7", .spi_io_mode = spi_single_io_mode, +#elif defined(BSP_SPI7_USING_DUAL_IO) +#define HPM_SPI_BUS_NAME_MODE_7 .bus_name = "dspi7", .spi_io_mode = spi_dual_io_mode, +#elif defined(BSP_SPI7_USING_QUAD_IO) +#define HPM_SPI_BUS_NAME_MODE_7 .bus_name = "qspi7", .spi_io_mode = spi_quad_io_mode, #endif - .tx_dmamux = HPM_DMA_SRC_SPI1_TX, - .rx_dmamux = HPM_DMA_SRC_SPI1_RX, - .spi_irq = IRQn_SPI1, -#if defined(BSP_SPI1_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI1_IRQ_PRIORITY, + +/* DMA configuration per instance */ +#if defined(BSP_SPI0_USING_DMA) +#define HPM_SPI_DMA_CONFIG_0 .enable_dma = RT_TRUE, #else - .spi_irq_priority = 1, +#define HPM_SPI_DMA_CONFIG_0 #endif -#if !defined BSP_SPI1_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +#if defined(BSP_SPI1_USING_DMA) +#define HPM_SPI_DMA_CONFIG_1 .enable_dma = RT_TRUE, #else - .spi_pins_init = init_spi_pins, -#endif - }, -#endif -#if defined(BSP_USING_SPI2) - { -#if defined(BSP_SPI2_USING_SINGLE_IO) - .bus_name = "spi2", - .spi_io_mode = spi_single_io_mode, -#endif -#if defined(BSP_SPI2_USING_DUAL_IO) - .bus_name = "dspi2", - .spi_io_mode = spi_dual_io_mode, +#define HPM_SPI_DMA_CONFIG_1 #endif -#if defined(BSP_SPI2_USING_QUAD_IO) - .bus_name = "qspi2", - .spi_io_mode = spi_quad_io_mode, -#endif - .spi_base = HPM_SPI2, - .clk_name = clock_spi2, + #if defined(BSP_SPI2_USING_DMA) - .enable_dma = RT_TRUE, -#endif - .tx_dmamux = HPM_DMA_SRC_SPI2_TX, - .rx_dmamux = HPM_DMA_SRC_SPI2_RX, - .spi_irq = IRQn_SPI2, -#if defined(BSP_SPI2_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI2_IRQ_PRIORITY, +#define HPM_SPI_DMA_CONFIG_2 .enable_dma = RT_TRUE, #else - .spi_irq_priority = 1, +#define HPM_SPI_DMA_CONFIG_2 #endif -#if !defined BSP_SPI2_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +#if defined(BSP_SPI3_USING_DMA) +#define HPM_SPI_DMA_CONFIG_3 .enable_dma = RT_TRUE, #else - .spi_pins_init = init_spi_pins, -#endif - }, +#define HPM_SPI_DMA_CONFIG_3 #endif -#if defined(BSP_USING_SPI3) - { -#if defined(BSP_SPI3_USING_SINGLE_IO) - .bus_name = "spi3", - .spi_io_mode = spi_single_io_mode, -#endif -#if defined(BSP_SPI3_USING_DUAL_IO) - .bus_name = "dspi3", - .spi_io_mode = spi_dual_io_mode, -#endif -#if defined(BSP_SPI3_USING_QUAD_IO) - .bus_name = "qspi3", - .spi_io_mode = spi_quad_io_mode, -#endif - .spi_base = HPM_SPI3, - .clk_name = clock_spi3, -#if defined(BSP_SPI3_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_SPI4_USING_DMA) +#define HPM_SPI_DMA_CONFIG_4 .enable_dma = RT_TRUE, +#else +#define HPM_SPI_DMA_CONFIG_4 #endif - .tx_dmamux = HPM_DMA_SRC_SPI3_TX, - .rx_dmamux = HPM_DMA_SRC_SPI3_RX, - .spi_irq = IRQn_SPI3, -#if defined(BSP_SPI3_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI3_IRQ_PRIORITY, + +#if defined(BSP_SPI5_USING_DMA) +#define HPM_SPI_DMA_CONFIG_5 .enable_dma = RT_TRUE, #else - .spi_irq_priority = 1, +#define HPM_SPI_DMA_CONFIG_5 #endif -#if !defined BSP_SPI3_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +#if defined(BSP_SPI6_USING_DMA) +#define HPM_SPI_DMA_CONFIG_6 .enable_dma = RT_TRUE, #else - .spi_pins_init = init_spi_pins, +#define HPM_SPI_DMA_CONFIG_6 #endif - }, + +#if defined(BSP_SPI7_USING_DMA) +#define HPM_SPI_DMA_CONFIG_7 .enable_dma = RT_TRUE, +#else +#define HPM_SPI_DMA_CONFIG_7 #endif -#if defined(BSP_USING_SPI4) - { -#if defined(BSP_SPI4_USING_SINGLE_IO) - .bus_name = "spi4", - .spi_io_mode = spi_single_io_mode, + +/* IRQ priority configuration per instance */ +#if defined(BSP_SPI0_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_0 .spi_irq_priority = BSP_SPI0_IRQ_PRIORITY, +#else +#define HPM_SPI_IRQ_PRIORITY_0 .spi_irq_priority = 1, #endif -#if defined(BSP_SPI4_USING_DUAL_IO) - .bus_name = "dspi4", - .spi_io_mode = spi_dual_io_mode, + +#if defined(BSP_SPI1_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_1 .spi_irq_priority = BSP_SPI1_IRQ_PRIORITY, +#else +#define HPM_SPI_IRQ_PRIORITY_1 .spi_irq_priority = 1, #endif -#if defined(BSP_SPI4_USING_QUAD_IO) - .bus_name = "qspi4", - .spi_io_mode = spi_quad_io_mode, + +#if defined(BSP_SPI2_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_2 .spi_irq_priority = BSP_SPI2_IRQ_PRIORITY, +#else +#define HPM_SPI_IRQ_PRIORITY_2 .spi_irq_priority = 1, #endif - .spi_base = HPM_SPI4, - .clk_name = clock_spi4, -#if defined(BSP_SPI4_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_SPI3_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_3 .spi_irq_priority = BSP_SPI3_IRQ_PRIORITY, +#else +#define HPM_SPI_IRQ_PRIORITY_3 .spi_irq_priority = 1, #endif - .tx_dmamux = HPM_DMA_SRC_SPI4_TX, - .rx_dmamux = HPM_DMA_SRC_SPI4_RX, - .spi_irq = IRQn_SPI4, + #if defined(BSP_SPI4_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI4_IRQ_PRIORITY, +#define HPM_SPI_IRQ_PRIORITY_4 .spi_irq_priority = BSP_SPI4_IRQ_PRIORITY, #else - .spi_irq_priority = 1, +#define HPM_SPI_IRQ_PRIORITY_4 .spi_irq_priority = 1, #endif -#if !defined BSP_SPI4_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +#if defined(BSP_SPI5_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_5 .spi_irq_priority = BSP_SPI5_IRQ_PRIORITY, #else - .spi_pins_init = init_spi_pins, -#endif - }, -#endif -#if defined(BSP_USING_SPI5) - { -#if defined(BSP_SPI5_USING_SINGLE_IO) - .bus_name = "spi5", - .spi_io_mode = spi_single_io_mode, +#define HPM_SPI_IRQ_PRIORITY_5 .spi_irq_priority = 1, #endif -#if defined(BSP_SPI5_USING_DUAL_IO) - .bus_name = "dspi5", - .spi_io_mode = spi_dual_io_mode, -#endif -#if defined(BSP_SPI5_USING_QUAD_IO) - .bus_name = "qspi5", - .spi_io_mode = spi_quad_io_mode, -#endif - .spi_base = HPM_SPI5, - .clk_name = clock_spi5, -#if defined(BSP_SPI5_USING_DMA) - .enable_dma = RT_TRUE, + +#if defined(BSP_SPI6_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_6 .spi_irq_priority = BSP_SPI6_IRQ_PRIORITY, +#else +#define HPM_SPI_IRQ_PRIORITY_6 .spi_irq_priority = 1, #endif - .tx_dmamux = HPM_DMA_SRC_SPI5_TX, - .rx_dmamux = HPM_DMA_SRC_SPI5_RX, - .spi_irq = IRQn_SPI5, -#if defined(BSP_SPI5_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI5_IRQ_PRIORITY, + +#if defined(BSP_SPI7_IRQ_PRIORITY) +#define HPM_SPI_IRQ_PRIORITY_7 .spi_irq_priority = BSP_SPI7_IRQ_PRIORITY, #else - .spi_irq_priority = 1, +#define HPM_SPI_IRQ_PRIORITY_7 .spi_irq_priority = 1, #endif -#if !defined BSP_SPI5_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +/* CS pin init configuration per instance */ +#if !defined(BSP_SPI0_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_0 .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else - .spi_pins_init = init_spi_pins, +#define HPM_SPI_PINS_INIT_0 .spi_pins_init = init_spi_pins, #endif - }, + +#if !defined(BSP_SPI1_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_1 .spi_pins_init = init_spi_pins_with_gpio_as_cs, +#else +#define HPM_SPI_PINS_INIT_1 .spi_pins_init = init_spi_pins, #endif -#if defined(BSP_USING_SPI6) - { -#if defined(BSP_SPI6_USING_SINGLE_IO) - .bus_name = "spi6", - .spi_io_mode = spi_single_io_mode, + +#if !defined(BSP_SPI2_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_2 .spi_pins_init = init_spi_pins_with_gpio_as_cs, +#else +#define HPM_SPI_PINS_INIT_2 .spi_pins_init = init_spi_pins, #endif -#if defined(BSP_SPI6_USING_DUAL_IO) - .bus_name = "dspi6", - .spi_io_mode = spi_dual_io_mode, + +#if !defined(BSP_SPI3_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_3 .spi_pins_init = init_spi_pins_with_gpio_as_cs, +#else +#define HPM_SPI_PINS_INIT_3 .spi_pins_init = init_spi_pins, #endif -#if defined(BSP_SPI6_USING_QUAD_IO) - .bus_name = "qspi6", - .spi_io_mode = spi_quad_io_mode, + +#if !defined(BSP_SPI4_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_4 .spi_pins_init = init_spi_pins_with_gpio_as_cs, +#else +#define HPM_SPI_PINS_INIT_4 .spi_pins_init = init_spi_pins, #endif - .spi_base = HPM_SPI6, - .clk_name = clock_spi6, -#if defined(BSP_SPI6_USING_DMA) - .enable_dma = RT_TRUE, + +#if !defined(BSP_SPI5_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_5 .spi_pins_init = init_spi_pins_with_gpio_as_cs, +#else +#define HPM_SPI_PINS_INIT_5 .spi_pins_init = init_spi_pins, #endif - .tx_dmamux = HPM_DMA_SRC_SPI6_TX, - .rx_dmamux = HPM_DMA_SRC_SPI6_RX, - .spi_irq = IRQn_SPI6, -#if defined(BSP_SPI6_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI6_IRQ_PRIORITY, + +#if !defined(BSP_SPI6_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_6 .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else - .spi_irq_priority = 1, +#define HPM_SPI_PINS_INIT_6 .spi_pins_init = init_spi_pins, #endif -#if !defined BSP_SPI6_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, + +#if !defined(BSP_SPI7_USING_HARD_CS) +#define HPM_SPI_PINS_INIT_7 .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else - .spi_pins_init = init_spi_pins, +#define HPM_SPI_PINS_INIT_7 .spi_pins_init = init_spi_pins, #endif - }, + +/* Main SPI configuration macro */ +#define HPM_SPI_CONFIG(idx) \ + { \ + HPM_SPI_BUS_NAME_MODE_##idx \ + .spi_base = HPM_SPI##idx, \ + .clk_name = clock_spi##idx, \ + HPM_SPI_DMA_CONFIG_##idx \ + .tx_dmamux = HPM_DMA_SRC_SPI##idx##_TX, \ + .rx_dmamux = HPM_DMA_SRC_SPI##idx##_RX, \ + .spi_irq = IRQn_SPI##idx, \ + HPM_SPI_IRQ_PRIORITY_##idx \ + HPM_SPI_PINS_INIT_##idx \ + } + +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +/* Macro for ISR handler declaration and implementation */ +#define HPM_SPI_ISR_HANDLER(idx) \ + SDK_DECLARE_EXT_ISR_M(IRQn_SPI##idx, spi##idx##_isr); \ + void spi##idx##_isr(void) \ + { \ + handle_spi_isr(HPM_SPI##idx); \ + } +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +static struct hpm_spi hpm_spis[] = +{ +#if defined(BSP_USING_SPI0) + HPM_SPI_CONFIG(0), #endif -#if defined(BSP_USING_SPI7) - { -#if defined(BSP_SPI7_USING_SINGLE_IO) - .bus_name = "spi7", - .spi_io_mode = spi_single_io_mode, +#if defined(BSP_USING_SPI1) + HPM_SPI_CONFIG(1), #endif -#if defined(BSP_SPI7_USING_DUAL_IO) - .bus_name = "dspi7", - .spi_io_mode = spi_dual_io_mode, +#if defined(BSP_USING_SPI2) + HPM_SPI_CONFIG(2), #endif -#if defined(BSP_SPI7_USING_QUAD_IO) - .bus_name = "qspi7", - .spi_io_mode = spi_quad_io_mode, +#if defined(BSP_USING_SPI3) + HPM_SPI_CONFIG(3), #endif - .spi_base = HPM_SPI7, - .clk_name = clock_spi7, -#if defined(BSP_SPI7_USING_DMA) - .enable_dma = RT_TRUE, +#if defined(BSP_USING_SPI4) + HPM_SPI_CONFIG(4), #endif - .tx_dmamux = HPM_DMA_SRC_SPI7_TX, - .rx_dmamux = HPM_DMA_SRC_SPI7_RX, - .spi_irq = IRQn_SPI7, -#if defined(BSP_SPI7_IRQ_PRIORITY) - .spi_irq_priority = BSP_SPI7_IRQ_PRIORITY, -#else - .spi_irq_priority = 1, +#if defined(BSP_USING_SPI5) + HPM_SPI_CONFIG(5), #endif -#if !defined BSP_SPI7_USING_HARD_CS - .spi_pins_init = init_spi_pins_with_gpio_as_cs, -#else - .spi_pins_init = init_spi_pins, +#if defined(BSP_USING_SPI6) + HPM_SPI_CONFIG(6), #endif - }, +#if defined(BSP_USING_SPI7) + HPM_SPI_CONFIG(7), #endif }; static struct rt_spi_ops hpm_spi_ops = @@ -427,7 +420,11 @@ static struct rt_spi_ops hpm_spi_ops = .xfer = hpm_spi_xfer, }; +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static inline void handle_spi_isr(SPI_Type *ptr) +#else +static inline void handle_spi_isr(int vector, SPI_Type *ptr) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { volatile uint32_t irq_status; RT_ASSERT(ptr != RT_NULL); @@ -449,69 +446,39 @@ static inline void handle_spi_isr(SPI_Type *ptr) rt_hw_interrupt_enable(level); } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK #if defined(BSP_USING_SPI0) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI0, spi0_isr); -void spi0_isr(void) -{ - handle_spi_isr(HPM_SPI0); -} +HPM_SPI_ISR_HANDLER(0) #endif #if defined(BSP_USING_SPI1) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI1, spi1_isr); -void spi1_isr(void) -{ - handle_spi_isr(HPM_SPI1); -} +HPM_SPI_ISR_HANDLER(1) #endif #if defined(BSP_USING_SPI2) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI2, spi2_isr); -void spi2_isr(void) -{ - handle_spi_isr(HPM_SPI2); -} +HPM_SPI_ISR_HANDLER(2) #endif #if defined(BSP_USING_SPI3) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI3, spi3_isr); -void spi3_isr(void) -{ - handle_spi_isr(HPM_SPI3); -} +HPM_SPI_ISR_HANDLER(3) #endif #if defined(BSP_USING_SPI4) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI4, spi4_isr); -void spi4_isr(void) -{ - handle_spi_isr(HPM_SPI4); -} +HPM_SPI_ISR_HANDLER(4) #endif #if defined(BSP_USING_SPI5) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI5, spi5_isr); -void spi5_isr(void) -{ - handle_spi_isr(HPM_SPI5); -} +HPM_SPI_ISR_HANDLER(5) #endif #if defined(BSP_USING_SPI6) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI6, spi6_isr); -void spi6_isr(void) -{ - handle_spi_isr(HPM_SPI6); -} +HPM_SPI_ISR_HANDLER(6) #endif #if defined(BSP_USING_SPI7) -SDK_DECLARE_EXT_ISR_M(IRQn_SPI7, spi7_isr); -void spi7_isr(void) -{ - handle_spi_isr(HPM_SPI7); -} +HPM_SPI_ISR_HANDLER(7) #endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ void spi_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { @@ -538,14 +505,20 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co spi_timing_config_t timing_config = { 0 }; spi_format_config_t format_config = { 0 }; struct hpm_spi *spi = RT_NULL; + struct rt_spi_configuration *spi_cfg = RT_NULL; hpm_stat_t stat = status_success; spi = (struct hpm_spi *)(device->bus->parent.user_data); RT_ASSERT(spi != RT_NULL); +#ifdef RT_USING_QSPI + struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *)device; + spi_cfg = (struct rt_spi_configuration *)&qspi_dev->config.parent; + RT_ASSERT((spi_cfg->data_width > 0) && (spi_cfg->data_width <= 32)); +#else /* hpm spi data width support 1 ~ 32 */ RT_ASSERT((cfg->data_width > 0) && (cfg->data_width <= 32)); - + spi_cfg = cfg; +#endif spi->spi_pins_init(spi->spi_base); - struct rt_spi_configuration *spi_cfg = cfg; if (spi_cfg->mode & RT_SPI_SLAVE) { spi_slave_get_default_format_config(&format_config); @@ -571,11 +544,11 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co } } - format_config.common_config.data_len_in_bits = cfg->data_width; - format_config.common_config.cpha = (cfg->mode & RT_SPI_CPHA) ? spi_sclk_sampling_even_clk_edges : spi_sclk_sampling_odd_clk_edges; - format_config.common_config.cpol = (cfg->mode & RT_SPI_CPOL) ? spi_sclk_high_idle : spi_sclk_low_idle; - format_config.common_config.lsb = (cfg->mode & RT_SPI_MSB) ? false : true; - format_config.common_config.mosi_bidir = cfg->mode & RT_SPI_3WIRE ? true : false; + format_config.common_config.data_len_in_bits = spi_cfg->data_width; + format_config.common_config.cpha = (spi_cfg->mode & RT_SPI_CPHA) ? spi_sclk_sampling_even_clk_edges : spi_sclk_sampling_odd_clk_edges; + format_config.common_config.cpol = (spi_cfg->mode & RT_SPI_CPOL) ? spi_sclk_high_idle : spi_sclk_low_idle; + format_config.common_config.lsb = (spi_cfg->mode & RT_SPI_MSB) ? false : true; + format_config.common_config.mosi_bidir = spi_cfg->mode & RT_SPI_3WIRE ? true : false; spi_format_init(spi->spi_base, &format_config); @@ -642,47 +615,59 @@ static rt_err_t hpm_spi_check_params(struct rt_spi_device *device, struct rt_spi return -RT_EINVAL; } - if (qspi_cfg->qspi_dl_width != 0) { - switch (qspi_cfg->qspi_dl_width) + if (qspi_msg->qspi_data_lines != 0) { + if ((qspi_msg->qspi_data_lines != 1) && (qspi_msg->qspi_data_lines != 2) && (qspi_msg->qspi_data_lines != 4)) { + LOG_E("dspi/qspi only support data phase qspi lines 1/2/4 for master\n"); + return -RT_EINVAL; + } + if ((qspi_cfg->qspi_dl_width != 0) && (qspi_msg->qspi_data_lines > qspi_cfg->qspi_dl_width)) { + LOG_E("msg data_lines must not exceed qspi_dl_width, qspi_dl_width=%d, data_lines=%d\n", + qspi_cfg->qspi_dl_width, qspi_msg->qspi_data_lines); + return -RT_EINVAL; + } + } + + if ((qspi_cfg->qspi_dl_width != 0) && (qspi_msg->address.qspi_lines > qspi_cfg->qspi_dl_width)) { + LOG_E("msg address_lines must not exceed qspi_dl_width, qspi_dl_width=%d, address_lines=%d\n", + qspi_cfg->qspi_dl_width, qspi_msg->address.qspi_lines); + return -RT_EINVAL; + } + + if (qspi_msg->dummy_cycles != 0) { + switch (qspi_msg->qspi_data_lines) { case 1: - if (qspi_msg->dummy_cycles != 0) { - if ((qspi_msg->dummy_cycles > (4 * 8))) { - LOG_E("spi only support dummy phase cycles < 32 for master\n"); - return -RT_EINVAL; - } - if ((qspi_msg->dummy_cycles != 0) && (qspi_msg->dummy_cycles % 8)) { - LOG_E("The number of cycles should be an integer multiple of 8 for spi master\n"); - return -RT_EINVAL; - } + if ((qspi_msg->dummy_cycles > (4 * 8))) { + LOG_E("spi only support dummy phase cycles < 32 for master\n"); + return -RT_EINVAL; + } + if (qspi_msg->dummy_cycles % 8) { + LOG_E("The number of cycles should be an integer multiple of 8 for spi master\n"); + return -RT_EINVAL; } break; case 2: - if (qspi_msg->dummy_cycles != 0) { - if (qspi_msg->dummy_cycles > (4 * 4)) { - LOG_E("dspi only support dummy phase cycles < 16 for master\n"); - return -RT_EINVAL; - } - if (qspi_msg->dummy_cycles % 4) { - LOG_E("The number of cycles should be an integer multiple of 4 for spi master\n"); - return -RT_EINVAL; - } + if (qspi_msg->dummy_cycles > (4 * 4)) { + LOG_E("dspi only support dummy phase cycles < 16 for master\n"); + return -RT_EINVAL; + } + if (qspi_msg->dummy_cycles % 4) { + LOG_E("The number of cycles should be an integer multiple of 4 for spi master\n"); + return -RT_EINVAL; } break; case 4: - if (qspi_msg->dummy_cycles != 0) { - if (qspi_msg->dummy_cycles > (4 * 2)) { - LOG_E("qspi only support dummy phase cycles < 8 for master\n"); - return -RT_EINVAL; - } - if (qspi_msg->dummy_cycles % 2) { - LOG_E("The number of cycles should be an integer multiple of 2 for spi master\n"); - return -RT_EINVAL; - } + if (qspi_msg->dummy_cycles > (4 * 2)) { + LOG_E("qspi only support dummy phase cycles < 8 for master\n"); + return -RT_EINVAL; + } + if (qspi_msg->dummy_cycles % 2) { + LOG_E("The number of cycles should be an integer multiple of 2 for spi master\n"); + return -RT_EINVAL; } break; default: - LOG_E("spi only support data phase qspi lines 1/2/4 for master\n"); + LOG_E("dummy phase requires data phase qspi lines 1/2/4 for master\n"); return -RT_EINVAL; } } @@ -699,8 +684,6 @@ bool hpm_qspi_parse_phase_message(struct rt_spi_device *device, struct rt_qspi_m struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); #ifdef RT_USING_QSPI struct rt_qspi_message *qspi_msg = (struct rt_qspi_message *)msg; - struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *)device; - struct rt_qspi_configuration *qspi_cfg = (struct rt_qspi_configuration *)&qspi_dev->config; if ((device->bus->mode == RT_SPI_BUS_MODE_QSPI) && ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER)) { if (msg->instruction.qspi_lines == 1) { (*cmd) = msg->instruction.content; @@ -784,32 +767,19 @@ bool hpm_qspi_parse_phase_message(struct rt_spi_device *device, struct rt_qspi_m break; } } - if (qspi_cfg->qspi_dl_width == 1) { - if (msg->qspi_data_lines == 1) { - spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; - } else { - LOG_E("msg data_lines must be 1 when qspi_dl_width is 1, but msg data_lines is %d\n", msg->qspi_data_lines); - } - } else if (qspi_cfg->qspi_dl_width == 2) { - if (msg->qspi_data_lines == 1) { - spi->control_config.common_config.data_phase_fmt = spi_dual_io_mode; - } else if (msg->qspi_data_lines == 2) { - spi->control_config.common_config.data_phase_fmt = spi_quad_io_mode; - } else { - LOG_E("msg data_lines must be 1 or 2 when qspi_dl_width is 2, but msg data_lines is %d\n", msg->qspi_data_lines); - } - } else if (qspi_cfg->qspi_dl_width == 4) { - if (msg->qspi_data_lines == 1) { - spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; - } else if (msg->qspi_data_lines == 2) { - spi->control_config.common_config.data_phase_fmt = spi_dual_io_mode; - } else if (msg->qspi_data_lines == 4) { - spi->control_config.common_config.data_phase_fmt = spi_quad_io_mode; - } else { - spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; - } - } else { - spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; + switch (qspi_msg->qspi_data_lines) { + case 1: + control_config->common_config.data_phase_fmt = spi_single_io_mode; + break; + case 2: + control_config->common_config.data_phase_fmt = spi_dual_io_mode; + break; + case 4: + control_config->common_config.data_phase_fmt = spi_quad_io_mode; + break; + default: + control_config->common_config.data_phase_fmt = spi_single_io_mode; + break; } } #endif @@ -858,6 +828,7 @@ static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s hpm_stat_t spi_stat = status_success; struct rt_spi_message *_msg = (struct rt_spi_message *)msg; struct rt_spi_message *spi_msg = (struct rt_spi_message *)_msg; + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); #ifdef RT_USING_QSPI struct rt_qspi_message *qspi_msg = RT_NULL; #endif @@ -888,16 +859,16 @@ static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s if (hpm_spi_check_params(device, _msg) != RT_EOK) { return -RT_EINVAL; } + remaining_size = _msg->length; #ifdef RT_USING_QSPI qspi_msg = (struct rt_qspi_message *)_msg; need_dummy = hpm_qspi_parse_phase_message(device, qspi_msg, &spi->control_config, &cmd, &addr); - remaining_size = _msg->length; if (remaining_size == 0) { actual_len = hpm_spi_send_no_data(spi->spi_base, &spi->control_config, &cmd, &addr, qspi_msg); } #endif while (remaining_size > 0) { - transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes, remaining_size); /* Next sub-packet: Disable CMD and ADDR phase for the following packet */ if (index > 0) { spi->control_config.master_config.cmd_enable = RT_FALSE; @@ -905,7 +876,7 @@ static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s } if ((_msg->send_buf != NULL) && (_msg->recv_buf != NULL)) { spi->control_config.common_config.trans_mode = spi_trans_write_read_together; - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, tx_buf, transfer_len, rx_buf, transfer_len); + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, tx_buf, transfer_len / data_len_in_bytes, rx_buf, transfer_len / data_len_in_bytes); } else if (_msg->send_buf != NULL) { if ((need_dummy == RT_TRUE) && (index == 0)) { @@ -913,7 +884,7 @@ static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s } else { spi->control_config.common_config.trans_mode = spi_trans_write_only; } - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, (uint8_t*) tx_buf, transfer_len, NULL, 0); + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, (uint8_t*) tx_buf, transfer_len / data_len_in_bytes, NULL, 0); } else if (_msg->recv_buf != NULL){ if ((need_dummy == RT_TRUE) && (index == 0)) { @@ -921,7 +892,7 @@ static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_s } else { spi->control_config.common_config.trans_mode = spi_trans_read_only; } - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, NULL, 0, rx_buf, transfer_len); + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, NULL, 0, rx_buf, transfer_len / data_len_in_bytes); } if (spi_stat != status_success) { actual_len = -RT_EIO; @@ -1020,9 +991,6 @@ static hpm_stat_t hpm_spi_rx_dma_start(struct rt_spi_device *device) static void hpm_spi_transfer_data_cache_handle(struct rt_spi_message *msg, spi_dma_buf_ctx_t *ctx, rt_uint32_t len) { - rt_uint32_t transfer_len; - rt_uint8_t *tx_buf = RT_NULL; - rt_uint8_t *rx_buf = RT_NULL; uint32_t aligned_start = 0; uint32_t aligned_end = 0; uint32_t aligned_size = 0; @@ -1073,21 +1041,26 @@ static hpm_stat_t hpm_spi_transmit_use_fifo(struct rt_spi_device *device, struct { hpm_stat_t stat = status_fail; struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); - if (((*remaining_size) <= SPI_SOC_FIFO_DEPTH) && ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER) + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); + rt_uint32_t transfer_count = (*remaining_size) / data_len_in_bytes; + + if ((transfer_count <= SPI_SOC_FIFO_DEPTH) && ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER) && (msg->send_buf != NULL) && (msg->recv_buf == NULL)) { + /* Clear the semaphore */ + while (rt_sem_take(spi->spi_xfer_done_sem, 0) == RT_EOK) { + } spi_enable_interrupt(spi->spi_base, spi_end_int); if ((*need_dummy) == RT_TRUE) { spi->control_config.common_config.trans_mode = spi_trans_dummy_write; } else { spi->control_config.common_config.trans_mode = spi_trans_write_only; } - stat = spi_control_init(spi->spi_base, &spi->control_config, (*remaining_size), 0); + stat = spi_control_init(spi->spi_base, &spi->control_config, transfer_count, 0); if (stat != status_success) { return stat; } - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); if (msg->send_buf != NULL) { - for (uint8_t j = 0; j < (*remaining_size); j++) { + for (uint8_t j = 0; j < transfer_count; j++) { switch (data_len_in_bytes) { case 1: spi->spi_base->DATA = *(uint8_t *)msg->send_buf; @@ -1114,24 +1087,24 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m { spi_dma_buf_ctx_t dma_buf_ctx = {0}; rt_uint8_t cmd = 0; - rt_uint32_t addr = 0, aligned_len = 0; + rt_uint32_t addr = 0; rt_uint32_t remaining_size = msg->length; rt_uint32_t transfer_len; rt_uint8_t *tx_buf = RT_NULL; rt_uint8_t *rx_buf = RT_NULL; - uint32_t aligned_start = 0; - uint32_t aligned_end = 0; - uint32_t aligned_size = 0; rt_ssize_t actual_len = 0; bool need_dummy = RT_FALSE; hpm_stat_t stat = status_success; rt_uint32_t index; struct rt_spi_message *_msg = (struct rt_spi_message *)msg; - struct rt_spi_message *spi_msg = (struct rt_spi_message *)_msg; #ifdef RT_USING_QSPI struct rt_qspi_message *qspi_msg = RT_NULL; #endif struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); + /* Clear the semaphore */ + while (rt_sem_take(spi->spi_xfer_done_sem, 0) == RT_EOK) { + } spi_enable_interrupt(spi->spi_base, spi_end_int); while (_msg != RT_NULL) { index = 0; @@ -1154,7 +1127,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m _msg = _msg->next; continue; } - hpm_spi_transfer_data_cache_handle(_msg, &dma_buf_ctx, msg->length); + hpm_spi_transfer_data_cache_handle(_msg, &dma_buf_ctx, _msg->length); tx_buf = dma_buf_ctx.aligned_tx_buf; rx_buf = dma_buf_ctx.aligned_rx_buf; dma_mgr_disable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); @@ -1162,7 +1135,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m } } while (remaining_size > 0) { - transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes, remaining_size); /* Next sub-packet: Disable CMD and ADDR phase for the following packet */ if (index > 0) { spi->control_config.master_config.cmd_enable = RT_FALSE; @@ -1190,7 +1163,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m break; } /* third: config spi */ - stat = spi_control_init(spi->spi_base, &spi->control_config, transfer_len, transfer_len); + stat = spi_control_init(spi->spi_base, &spi->control_config, transfer_len / data_len_in_bytes, transfer_len / data_len_in_bytes); if (stat != status_success) { break; } @@ -1221,7 +1194,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m } else { spi->control_config.common_config.trans_mode = spi_trans_write_only; } - stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, transfer_len, RT_NULL); + stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, transfer_len / data_len_in_bytes, RT_NULL); if (stat != status_success) { break; } @@ -1253,7 +1226,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m if (stat != status_success) { break; } - stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, RT_NULL, transfer_len); + stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, RT_NULL, transfer_len / data_len_in_bytes); if (stat != status_success) { break; } @@ -1272,7 +1245,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m index++; } if (l1c_dc_is_enabled() && (_msg->length > 0)) { - if (((rt_uint32_t)msg->send_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { + if (((rt_uint32_t)_msg->send_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { if (dma_buf_ctx.aligned_tx_buf != RT_NULL) { rt_free_align(dma_buf_ctx.raw_alloc_tx_buf); dma_buf_ctx.raw_alloc_tx_buf = RT_NULL; @@ -1281,7 +1254,7 @@ static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_m } if ((l1c_dc_is_enabled() == true) && (_msg->recv_buf != RT_NULL) && (dma_buf_ctx.aligned_rx_buf != RT_NULL)) { l1c_dc_invalidate((uint32_t) dma_buf_ctx.aligned_rx_buf, dma_buf_ctx.aligned_size); - if (((rt_uint32_t)msg->recv_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { + if (((rt_uint32_t)_msg->recv_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { rt_memcpy(_msg->recv_buf, dma_buf_ctx.aligned_rx_buf, _msg->length); rt_free_align(dma_buf_ctx.raw_alloc_rx_buf); dma_buf_ctx.raw_alloc_rx_buf = RT_NULL; @@ -1371,9 +1344,10 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, #ifdef RT_USING_QSPI struct rt_qspi_device *qspi_dev; qspi_dev = (struct rt_qspi_device *) rt_malloc(sizeof(struct rt_qspi_device)); + RT_ASSERT(qspi_dev != RT_NULL); + rt_memset(qspi_dev, 0, sizeof(struct rt_qspi_device)); qspi_dev->enter_qspi_mode = enter_qspi_mode; qspi_dev->exit_qspi_mode = exit_qspi_mode; - RT_ASSERT(qspi_dev != RT_NULL); result = rt_spi_bus_attach_device(&qspi_dev->parent, device_name, bus_name, (void*)callback); RT_ASSERT(result == RT_EOK); struct hpm_spi *spi = RT_NULL; @@ -1435,8 +1409,18 @@ int rt_hw_spi_init(void) chg_config.dst_addr = (uint32_t)&spi->spi_base->DATA; chg_config.en_dmamux = true; chg_config.dmamux_src = spi->tx_dmamux; - dma_mgr_setup_channel(&spi->tx_dma, &chg_config); - dma_mgr_install_chn_tc_callback(&spi->tx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + stat = dma_mgr_setup_channel(&spi->tx_dma, &chg_config); + if (stat != status_success) + { + LOG_E("[spi%d]tx dma setup channel failed\n", i); + return -RT_ERROR; + } + stat = dma_mgr_install_chn_tc_callback(&spi->tx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + if (stat != status_success) + { + LOG_E("[spi%d]tx dma install callback failed\n", i); + return -RT_ERROR; + } /* spi rx dma config */ stat = dma_mgr_request_resource(&spi->rx_dma); if (stat != status_success) { @@ -1450,8 +1434,18 @@ int rt_hw_spi_init(void) chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; chg_config.en_dmamux = true; chg_config.dmamux_src = spi->rx_dmamux; - dma_mgr_setup_channel(&spi->rx_dma, &chg_config); - dma_mgr_install_chn_tc_callback(&spi->rx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + stat = dma_mgr_setup_channel(&spi->rx_dma, &chg_config); + if (stat != status_success) + { + LOG_E("[spi%d]rx dma setup channel failed\n", i); + return -RT_ERROR; + } + stat = dma_mgr_install_chn_tc_callback(&spi->rx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + if (stat != status_success) + { + LOG_E("[spi%d]rx dma install callback failed\n", i); + return -RT_ERROR; + } intc_m_enable_irq_with_priority(hpm_spis[i].spi_irq, hpm_spis[i].spi_irq_priority); dma_mgr_enable_dma_irq_with_priority(&spi->tx_dma, 1); @@ -1472,7 +1466,7 @@ int rt_hw_spi_init(void) hpm_spis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); if (hpm_spis[i].xfer_sem == RT_NULL) { - ret = RT_ENOMEM; + ret = -RT_ENOMEM; break; } @@ -1480,7 +1474,7 @@ int rt_hw_spi_init(void) hpm_spis[i].spi_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); if (hpm_spis[i].spi_xfer_done_sem == RT_NULL) { - ret = RT_ENOMEM; + ret = -RT_ENOMEM; break; } @@ -1488,7 +1482,7 @@ int rt_hw_spi_init(void) hpm_spis[i].rxdma_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); if (hpm_spis[i].rxdma_xfer_done_sem == RT_NULL) { - ret = RT_ENOMEM; + ret = -RT_ENOMEM; break; } @@ -1496,9 +1490,14 @@ int rt_hw_spi_init(void) hpm_spis[i].txdma_xfer_done_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); if (hpm_spis[i].txdma_xfer_done_sem == RT_NULL) { - ret = RT_ENOMEM; + ret = -RT_ENOMEM; break; } + +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register SPI device to irq table */ + rt_hw_interrupt_install(hpm_spis[i].spi_irq, (rt_isr_handler_t)handle_spi_isr, hpm_spis[i].spi_base, hpm_spis[i].bus_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return ret; diff --git a/bsp/hpmicro/libraries/drivers/drv_timer.c b/bsp/hpmicro/libraries/drivers/drv_timer.c index 3c3a37c4f4..9e366f47ff 100644 --- a/bsp/hpmicro/libraries/drivers/drv_timer.c +++ b/bsp/hpmicro/libraries/drivers/drv_timer.c @@ -12,7 +12,14 @@ #include "drv_timer.h" #include "board.h" +#ifdef BSP_USING_GPTMRV2 +#include "hpm_gptmrv2_drv.h" +#ifndef GPTMRV2_DEFAULT_FREQ +#define GPTMRV2_DEFAULT_FREQ (100000UL) /* 100KHz */ +#endif +#else #include "hpm_gptmr_drv.h" +#endif #include "hpm_clock_drv.h" @@ -46,7 +53,11 @@ static const struct rt_clock_timer_ops hpm_clock_timer_ops = { static const struct rt_clock_timer_info hpm_clock_timer_info = { .maxfreq = 100000000UL, .minfreq = 93750UL, +#ifdef BSP_USING_GPTMRV2 + .maxcnt = 0xFFFFFFUL, +#else .maxcnt = 0xFFFFFFFFUL, +#endif .cntmode = CLOCK_TIMER_CNTMODE_UP }; @@ -278,6 +289,10 @@ static void hpm_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) clock_add_to_group(hpm_gptmr->clock_name, BOARD_RUNNING_CORE & 0x1); hpm_gptmr->timer.freq = clock_get_frequency(hpm_gptmr->clock_name); gptmr_channel_get_default_config(base, &config); +#ifdef BSP_USING_GPTMRV2 + hpm_gptmr->timer.freq = GPTMRV2_DEFAULT_FREQ; + config.prescaler = clock_get_frequency(hpm_gptmr->clock_name) / hpm_gptmr->timer.freq; +#endif gptmr_channel_config(base, hpm_gptmr->channel, &config, false); } } @@ -291,6 +306,9 @@ static rt_err_t hpm_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, gptmr_channel_get_default_config(base, &config); config.cmp[0] = 0; config.reload = cnt; +#ifdef BSP_USING_GPTMRV2 + config.prescaler = clock_get_frequency(hpm_gptmr->clock_name) / timer->freq; +#endif timer->mode = mode; @@ -334,17 +352,35 @@ static rt_err_t hpm_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd switch (cmd) { case CLOCK_TIMER_CTRL_FREQ_SET: +#ifdef BSP_USING_GPTMRV2 + if ((args == RT_NULL) || (*(rt_uint32_t *)args == 0U)) + { + return -RT_EINVAL; + } + hpm_gptmr->timer.freq = *(rt_uint32_t*)args; +#else err = -RT_ERROR; +#endif break; case CLOCK_TIMER_CTRL_INFO_GET: + if (args == RT_NULL) + { + return -RT_EINVAL; + } *(rt_clock_timer_t*)args = hpm_gptmr->timer; break; case CLOCK_TIMER_CTRL_MODE_SET: + if (args == RT_NULL) + { + return -RT_EINVAL; + } hpm_gptmr->timer.mode = *(rt_uint32_t*)args; break; case CLOCK_TIMER_CTRL_STOP: gptmr_stop_counter(base, hpm_gptmr->channel); break; + default: + return -RT_EINVAL; } return err; diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw.c b/bsp/hpmicro/libraries/drivers/drv_tsw.c index 79f3022250..d64ba419e7 100644 --- a/bsp/hpmicro/libraries/drivers/drv_tsw.c +++ b/bsp/hpmicro/libraries/drivers/drv_tsw.c @@ -13,9 +13,10 @@ #ifdef BSP_USING_TSW #include <rtdbg.h> #include "drv_tsw.h" -#include "board.h" #if defined(BSP_USING_TSW_PHY_RTL8211) +#include "hpm_tsw_rtl8211.h" +#include "board.h" #include "hpm_rtl8211.h" #endif @@ -250,7 +251,11 @@ static void eth_rx_callback(struct eth_device* dev) } } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK void isr_tsw(hpm_tsw_t *obj) +#else +void isr_tsw(int vector, hpm_tsw_t *obj) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { static int idx = 0; uint8_t *prx = (uint8_t *)obj->tsw_dev->rx_buff_cfg->buffer; @@ -262,11 +267,13 @@ void isr_tsw(hpm_tsw_t *obj) eth_rx_callback(obj->eth_dev); } +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK SDK_DECLARE_EXT_ISR_M(IRQn_TSW_0, isr_tsw_port_cpu) void isr_tsw_port_cpu(void) { isr_tsw(&tsw); } +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ int rt_hw_tsw_init(void) { @@ -313,6 +320,11 @@ int rt_hw_tsw_init(void) LOG_D("Ethernet device %d initialize unsuccessfully!\n"); return err; } + +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register TSW device to irq table */ + rt_hw_interrupt_install(s_geths[i]->irq_num, (rt_isr_handler_t)isr_tsw, s_geths[i], s_geths[i]->name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return err; diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c index 7eb8074089..00fd3eb7aa 100644 --- a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c +++ b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2025-3-31 Jiading Initial version + * 2026-9-18 Jiading Wait for tsw_phy_speed_valid before announcing link-up */ #include "rtthread.h" @@ -16,9 +17,9 @@ #include "hpm_tsw_drv.h" #include "drv_tsw_phy.h" #include "hpm_tsw_phy.h" -#include "hpm_soc.h" #include "netif/ethernetif.h" #include "board.h" +#include "hpm_soc.h" typedef struct { TSW_Type *instance; @@ -67,27 +68,51 @@ tsw_phy_monitor_handle_t phy_monitor_handle = { static struct rt_phy_ops phy_ops; -static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +static rt_phy_status phy_query_status(rt_phy_t *phy, tsw_phy_status_t *phy_status) { - tsw_phy_instance_t *phy_ins = (tsw_phy_instance_t *)object; + tsw_phy_instance_t *phy_ins = phy->bus->hw_obj; + hpm_stat_t stat = status_fail; - if (phy_ins->instance == HPM_TSW) { - rtl8211_config_t phy_config; + *phy_status = (tsw_phy_status_t){0}; - /* Set MDC clock frequency */ - tsw_ep_set_mdio_config(phy_ins->instance, phy_ins->port, src_clock_hz / (2 * PHY_MDIO_CLK_FREQ) - 1); +#if defined(__USE_RTL8211) && __USE_RTL8211 + stat = rtl8211_get_phy_status(phy_ins->instance, phy_ins->port, RTL8211_ADDR, phy_status); +#endif - /* PHY Reset */ - rtl8211_reset(phy_ins->instance, phy_ins->port); - rtl8211_basic_mode_default_config(phy_ins->instance, &phy_config); - if (rtl8211_basic_mode_init(phy_ins->instance, phy_ins->port, &phy_config) == true) { - return PHY_STATUS_OK; - } else { - return PHY_STATUS_FAIL; - } + if (stat != status_success) { + return PHY_STATUS_FAIL; } - return -RT_EINVAL; + return PHY_STATUS_OK; +} + +static void phy_apply_mac(tsw_phy_instance_t *phy_ins, const phy_info_t *phy_info) +{ + tsw_port_speed_t port_speed[] = {tsw_port_speed_10mbps, tsw_port_speed_100mbps, tsw_port_speed_1000mbps}; + + if (phy_info->phy_speed >= ARRAY_SIZE(port_speed)) { + return; + } + + tsw_set_port_speed(phy_ins->instance, phy_ins->port, port_speed[phy_info->phy_speed]); +} + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + tsw_phy_instance_t *phy_ins = (tsw_phy_instance_t *)object; + rtl8211_config_t phy_config; + + /* Set MDC clock frequency */ + tsw_ep_set_mdio_config(phy_ins->instance, phy_ins->port, src_clock_hz / (2 * PHY_MDIO_CLK_FREQ) - 1); + + /* PHY Reset */ + rtl8211_reset(phy_ins->instance, phy_ins->port, RTL8211_ADDR); + rtl8211_basic_mode_default_config(phy_ins->instance, &phy_config); + if (rtl8211_basic_mode_init(phy_ins->instance, phy_ins->port, RTL8211_ADDR, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } } static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) @@ -120,29 +145,28 @@ static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *d static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) { - tsw_phy_instance_t *phy_ins = phy->bus->hw_obj; tsw_phy_status_t phy_status; - if (phy_ins->instance == HPM_TSW) { - #if defined(__USE_RTL8211) && __USE_RTL8211 - rtl8211_get_phy_status(phy_ins->instance, phy_ins->port, &phy_status); - #endif + if (phy_query_status(phy, &phy_status) != PHY_STATUS_OK) { + *status = RT_FALSE; + return PHY_STATUS_FAIL; } - *status = phy_status.tsw_phy_link; + *status = (phy_status.tsw_phy_link == tsw_phy_link_up) ? RT_TRUE : RT_FALSE; return PHY_STATUS_OK; } static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) { - tsw_phy_instance_t *phy_ins = phy->bus->hw_obj; tsw_phy_status_t phy_status; - if (phy_ins->instance == HPM_TSW) { - #if defined(__USE_RTL8211) && __USE_RTL8211 - rtl8211_get_phy_status(phy_ins->instance, phy_ins->port, &phy_status); - #endif + if (phy_query_status(phy, &phy_status) != PHY_STATUS_OK) { + return PHY_STATUS_FAIL; + } + + if (!tsw_phy_link_up_with_valid_speed(&phy_status)) { + return PHY_STATUS_FAIL; } *speed = phy_status.tsw_phy_speed; @@ -155,43 +179,56 @@ static void phy_poll_status(void *parameter) { int ret; phy_info_t phy_info; - rt_bool_t status; - rt_device_t dev; - rt_phy_msg_t msg; - rt_uint32_t speed, duplex; + tsw_phy_status_t phy_status; phy_device_t *phy_dev; - struct eth_device* eth_dev; + struct eth_device *eth_dev; char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; - tsw_port_speed_t port_speed[] = {tsw_port_speed_10mbps, tsw_port_speed_100mbps, tsw_port_speed_1000mbps}; tsw_phy_monitor_handle_t *phy_monitor_handle = (tsw_phy_monitor_handle_t *)parameter; for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) { eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; - phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); - - if (status) { - phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + if (phy_query_status(&phy_dev->phy, &phy_status) != PHY_STATUS_OK) { + continue; + } - ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); - if (ret != 0) { - memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (phy_status.tsw_phy_link == tsw_phy_link_down) { + if (phy_dev->phy_link != PHY_LINK_DOWN) { + phy_dev->phy_link = PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, RT_FALSE); + LOG_I("PHY Status: %s", "Link down\n"); } + continue; + } + + if (!tsw_phy_link_up_with_valid_speed(&phy_status)) { + continue; } - if (phy_dev->phy_link != status) { - phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; - eth_device_linkchange(eth_dev, status); - LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); - if (status == PHY_LINK_UP) { + phy_info.phy_speed = phy_status.tsw_phy_speed; + phy_info.phy_duplex = phy_status.tsw_phy_duplex; + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (phy_dev->phy_link == PHY_LINK_UP) { + phy_apply_mac(phy_monitor_handle->phy_handle[i]->phy_ins, &phy_dev->phy_info); LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); - tsw_set_port_speed(phy_monitor_handle->phy_handle[i]->phy_ins->instance, phy_monitor_handle->phy_handle[i]->phy_ins->port, port_speed[phy_dev->phy_info.phy_speed]); - if (!(phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX)) { - LOG_E("Error: PHY is in half duplex now, but TSW MAC supports only full duplex mode!\n"); - return; - } + } + } + + if (phy_dev->phy_link != PHY_LINK_UP) { + phy_dev->phy_link = PHY_LINK_UP; + eth_device_linkchange(eth_dev, RT_TRUE); + LOG_I("PHY Status: %s", "Link up"); + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + phy_apply_mac(phy_monitor_handle->phy_handle[i]->phy_ins, &phy_dev->phy_info); + if (!(phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX)) { + LOG_E("Error: PHY is in half duplex now, but TSW MAC supports only full duplex mode!\n"); + return; } } } diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h index d7d3604105..ad6f9bb548 100644 --- a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h +++ b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h @@ -12,6 +12,7 @@ #include <rtdevice.h> #if defined(BSP_USING_TSW_PHY_RTL8211) +#include "hpm_tsw_rtl8211.h" #include "hpm_rtl8211.h" #endif diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.c b/bsp/hpmicro/libraries/drivers/drv_uart.c index 991fa6142e..72f2264dc5 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart.c @@ -38,160 +38,161 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void static int hpm_uart_putc(struct rt_serial_device *serial, char ch); static int hpm_uart_getc(struct rt_serial_device *serial); - +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK #if defined(BSP_USING_UART0) struct rt_serial_device serial0; -SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) void uart0_isr(void) { hpm_uart_isr(&serial0); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) #endif #if defined(BSP_USING_UART1) struct rt_serial_device serial1; -SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) void uart1_isr(void) { hpm_uart_isr(&serial1); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) #endif #if defined(BSP_USING_UART2) struct rt_serial_device serial2; -SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) void uart2_isr(void) { hpm_uart_isr(&serial2); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) #endif #if defined(BSP_USING_UART3) struct rt_serial_device serial3; -SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) void uart3_isr(void) { hpm_uart_isr(&serial3); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) #endif #if defined(BSP_USING_UART4) struct rt_serial_device serial4; -SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) void uart4_isr(void) { hpm_uart_isr(&serial4); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) #endif #if defined(BSP_USING_UART5) struct rt_serial_device serial5; -SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) void uart5_isr(void) { hpm_uart_isr(&serial5); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) #endif #if defined(BSP_USING_UART6) struct rt_serial_device serial6; -SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) void uart6_isr(void) { hpm_uart_isr(&serial6); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) #endif #if defined(BSP_USING_UART7) struct rt_serial_device serial7; -SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) void uart7_isr(void) { hpm_uart_isr(&serial7); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) #endif #if defined(BSP_USING_UART8) struct rt_serial_device serial8; -SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) void uart8_isr(void) { hpm_uart_isr(&serial8); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) #endif #if defined(BSP_USING_UART9) struct rt_serial_device serial9; -SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) void uart9_isr(void) { hpm_uart_isr(&serial9); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) #endif #if defined(BSP_USING_UART10) struct rt_serial_device serial10; -SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) void uart10_isr(void) { hpm_uart_isr(&serial10); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) #endif #if defined(BSP_USING_UART11) struct rt_serial_device serial11; -SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) void uart11_isr(void) { hpm_uart_isr(&serial11); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) #endif #if defined(BSP_USING_UART12) struct rt_serial_device serial12; -SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) void uart12_isr(void) { hpm_uart_isr(&serial12); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) #endif #if defined(BSP_USING_UART13) struct rt_serial_device serial13; -SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) void uart13_isr(void) { hpm_uart_isr(&serial13); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) #endif #if defined(BSP_USING_UART14) struct rt_serial_device serial14; -SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) void uart14_isr(void) { hpm_uart_isr(&serial14); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) #endif #if defined(BSP_USING_UART15) struct rt_serial_device serial15; -SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) void uart15_isr(void) { hpm_uart_isr(&serial15); } +SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) #endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ static const struct hpm_uart uarts[] = { #if defined(BSP_USING_UART0) @@ -441,7 +442,11 @@ static const struct hpm_uart uarts[] = { * * @param serial Serial device */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_uart_isr(struct rt_serial_device *serial) +#else +static void hpm_uart_isr(int vector, struct rt_serial_device *serial) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { struct hpm_uart *uart; @@ -461,6 +466,7 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria RT_ASSERT(cfg != RT_NULL); uart_config_t uart_config; + hpm_stat_t stat; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; init_uart_pins(uart->uart_base); @@ -472,10 +478,13 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria uart_config.parity = cfg->parity; uart_config.word_length = cfg->data_bits - DATA_BITS_5; + stat = uart_init(uart->uart_base, &uart_config); + if (stat != status_success) + { + return -RT_ERROR; + } - uart_init(uart->uart_base, &uart_config); - - hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, NULL); + return hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, NULL); } @@ -558,6 +567,10 @@ int rt_hw_uart_init(void) uarts[i].device_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, (void*)&uarts[i]); +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register UART device to irq table */ + rt_hw_interrupt_install(uarts[i].irq_num, (rt_isr_handler_t)hpm_uart_isr, uarts[i].serial, uarts[i].device_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return err; diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c index 279236978a..8a5c8bc730 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c @@ -3,40 +3,90 @@ * * SPDX-License-Identifier: BSD-3-Clause * + * @file drv_uart_v2.c + * @brief UART driver implementation for RT-Thread on HPMicro Microcontrollers + * + * This file implements the UART (Universal Asynchronous Receiver-Transmitter) driver + * for HPMicro microcontrollers, providing a complete interface + * between RT-Thread's serial framework and the HPM UART hardware. + * + * Features: + * - Support for up to 16 UART controllers (UART0-UART15) + * - Interrupt-driven and DMA-based data transfer + * - Configurable baud rates, data bits, stop bits, and parity + * - Hardware flow control support + * - Ring buffer management for efficient data handling + * - Cache coherency support for DMA operations + * - RX idle detection for improved DMA efficiency + * + * Architecture: + * - Each UART controller is represented by a hpm_uart structure + * - ISR functions handle interrupt-driven operations + * - DMA channels are dynamically allocated and managed + * - Configuration macros reduce code duplication + * * Change Logs: * Date Author Notes * 2022-03-08 HPMicro First version * 2022-07-28 HPMicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined - * 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment' + * 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment * 2023-03-07 HPMicro Fix the issue that the data_width was not initialized before setup dma handshake * 2024-06-10 HPMicro Fix memory leakage issue + * 2025-09-01 HPMicro Added comprehensive macros to reduce code duplication + * 2025-12-10 HPMicro Added DMA ping-pong buffer support for RX DMA mode * */ -#include <rtthread.h> -#include <rtdevice.h> -#include "board.h" -#include "drv_uart_v2.h" -#include "hpm_uart_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_l1c_drv.h" -#include "hpm_dma_mgr.h" -#include "hpm_soc.h" -#include "hpm_clock_drv.h" +/* RT-Thread configuration */ +#include "rtconfig.h" #ifdef RT_USING_SERIAL_V2 +/* RT-Thread core includes */ +#include <rtthread.h> /* RT-Thread kernel and threading support */ +#include <rtdevice.h> /* RT-Thread device framework */ + +/* Board and driver specific includes */ +#include "board.h" /* Board configuration and pin definitions */ +#include "drv_uart_v2.h" /* UART driver header file */ + +/* HPM SDK includes */ +#include "hpm_uart_drv.h" /* HPM UART driver API */ +#include "hpm_l1c_drv.h" /* L1 cache driver for DMA coherency */ +#include "hpm_dma_mgr.h" /* DMA manager for resource allocation */ +#include "hpm_soc.h" /* HPM SoC definitions and register maps */ +#include "hpm_clock_drv.h" /* Clock driver for UART clock configuration */ +#include "hpm_sysctl_drv.h" + + +/* ============================================================================ + * DMA Configuration and Definitions + * ============================================================================ + */ + #ifdef RT_SERIAL_USING_DMA -#define BOARD_UART_DMAMUX HPM_DMAMUX -#define UART_DMA_TRIGGER_LEVEL (1U) +/* DMA hardware configuration */ +#define BOARD_UART_DMAMUX HPM_DMAMUX /* DMA multiplexer base address */ +#define UART_DMA_TRIGGER_LEVEL (1U) /* DMA trigger level for UART operations */ + +/** + * @brief DMA channel handle structure for UART operations + * + * This structure manages DMA channel resources and callbacks for UART operations. + * It provides a complete interface for DMA-based UART data transfer with proper + * error handling and completion notification. + */ typedef struct dma_channel { - struct rt_serial_device *serial; - dma_resource_t resource; - void (*tranfer_done)(struct rt_serial_device *serial); - void (*tranfer_abort)(struct rt_serial_device *serial); - void (*tranfer_error)(struct rt_serial_device *serial); - void *ringbuf_ptr; + struct rt_serial_device *serial; /* Associated RT-Thread serial device */ + dma_resource_t resource; /* DMA resource (base, channel, IRQ) */ + void (*transfer_done)(struct rt_serial_device *serial); /* Transfer completion callback */ +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + void (*halftransfer_cb)(struct rt_serial_device *serial); /* Half transfer callback */ +#endif + void (*transfer_abort)(struct rt_serial_device *serial); /* Transfer abort callback */ + void (*transfer_error)(struct rt_serial_device *serial); /* Transfer error callback */ + void *ringbuf_ptr; /* Pointer to ring buffer for DMA operations */ } hpm_dma_channel_handle_t; //static struct dma_channel dma_channels[DMA_SOC_CHANNEL_NUM]; @@ -44,41 +94,73 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg); static void hpm_uart_receive_dma_next(struct rt_serial_device *serial); #endif -#define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ - +/** + * @brief UART device structure for HPM microcontrollers + * + * This structure contains all the necessary information to manage a UART controller, + * including hardware registers, DMA configuration, interrupt settings, and device + * identification. It serves as the primary data structure for UART operations. + */ struct hpm_uart { - UART_Type *uart_base; - rt_uint32_t irq_num; - rt_uint8_t irq_priority; - clock_name_t clk_name; - struct rt_serial_device *serial; - char *device_name; + /* Hardware configuration */ + UART_Type *uart_base; /* UART hardware register base address */ + rt_uint32_t txbuf_size; /* Transmit buffer size in bytes */ + rt_uint32_t rxbuf_size; /* Receive buffer size in bytes */ + rt_uint32_t irq_num; /* UART interrupt number */ + rt_uint8_t irq_priority; /* UART interrupt priority */ + + /* DMA configuration */ + bool enable_dma; /* Overall DMA enable flag */ + bool enable_tx_dma; /* Transmit DMA enable flag */ + bool enable_rx_dma; /* Receive DMA enable flag */ + + /* Clock and device configuration */ + clock_name_t clk_name; /* UART clock source name */ + struct rt_serial_device *serial; /* Associated RT-Thread serial device */ + char *device_name; /* Device name string (e.g., "uart0") */ + + /* DMA multiplexer configuration */ + uint32_t tx_dma_mux; /* TX DMA multiplexer source */ + uint32_t rx_dma_mux; /* RX DMA multiplexer source */ + uint32_t dma_flags; /* DMA operation flags */ + #ifdef RT_SERIAL_USING_DMA - uint32_t tx_dma_mux; - uint32_t rx_dma_mux; - uint32_t dma_flags; - hpm_dma_channel_handle_t tx_chn_ctx; - hpm_dma_channel_handle_t rx_chn_ctx; - bool tx_resource_allocated; - bool rx_resource_allocated; -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) - ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024]; -#endif + /* DMA channel contexts */ + hpm_dma_channel_handle_t tx_chn_ctx; /* TX DMA channel context */ + hpm_dma_channel_handle_t rx_chn_ctx; /* RX DMA channel context */ + bool tx_resource_allocated; /* TX DMA resource allocation status */ + bool rx_resource_allocated; /* RX DMA resource allocation status */ + rt_uint32_t dma_pingpong_size; /* DMA ping buffer size */ + rt_uint32_t dma_rx_remain_size; /* Remaining size for RX DMA operations */ #endif + rt_uint32_t rx_buffer_size; /* RX buffer size */ + rt_uint32_t rx_fifo_index; /* RX FIFO index */ }; +/* ============================================================================ + * Function Declarations + * ============================================================================ + */ + +/* External functions */ +extern void init_uart_pins(UART_Type *ptr); /* Initialize UART pins (defined in board.c) */ -extern void init_uart_pins(UART_Type *ptr); -static void hpm_uart_isr(struct rt_serial_device *serial); -static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); -static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg); -static int hpm_uart_putc(struct rt_serial_device *serial, char ch); -static int hpm_uart_getc(struct rt_serial_device *serial); +/* UART driver function prototypes */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +static void hpm_uart_isr(struct rt_serial_device *serial); /* UART interrupt service routine */ +#else +static void hpm_uart_isr(int vector, struct rt_serial_device *serial); /* UART interrupt service routine */ +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ +static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); /* Configure UART parameters */ +static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg); /* Control UART operations */ +static int hpm_uart_putc(struct rt_serial_device *serial, char ch); /* Send single character */ +static int hpm_uart_getc(struct rt_serial_device *serial); /* Receive single character */ #ifdef RT_SERIAL_USING_DMA int hpm_uart_dma_register_channel(struct rt_serial_device *serial, bool is_tx, void (*done)(struct rt_serial_device *serial), + void (*htc)(struct rt_serial_device *serial), void (*abort)(struct rt_serial_device *serial), void (*error)(struct rt_serial_device *serial)) { @@ -87,622 +169,523 @@ int hpm_uart_dma_register_channel(struct rt_serial_device *serial, if (is_tx) { uart->tx_chn_ctx.serial = serial; - uart->tx_chn_ctx.tranfer_done = done; - uart->tx_chn_ctx.tranfer_abort = abort; - uart->tx_chn_ctx.tranfer_error = error; + uart->tx_chn_ctx.transfer_done = done; +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + uart->tx_chn_ctx.halftransfer_cb = htc; +#else + (void)htc; +#endif + uart->tx_chn_ctx.transfer_abort = abort; + uart->tx_chn_ctx.transfer_error = error; } else { uart->rx_chn_ctx.serial = serial; - uart->rx_chn_ctx.tranfer_done = done; - uart->rx_chn_ctx.tranfer_abort = abort; - uart->rx_chn_ctx.tranfer_error = error; + uart->rx_chn_ctx.transfer_done = done; +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + uart->rx_chn_ctx.halftransfer_cb = htc; +#else + (void)htc; +#endif + uart->rx_chn_ctx.transfer_abort = abort; + uart->rx_chn_ctx.transfer_error = error; } return RT_EOK; } #endif /* RT_SERIAL_USING_DMA */ -#if defined(BSP_USING_UART0) -struct rt_serial_device serial0; -SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) -void uart0_isr(void) -{ - hpm_uart_isr(&serial0); -} -#endif - +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +/* ============================================================================ + * UART ISR Function Macros + * ============================================================================ + * + * These macros generate UART interrupt service routine functions and device + * declarations for each UART controller. They reduce code duplication by + * automatically generating the necessary ISR functions and device structures. + * + * Each macro generates: + * - A serial device structure (serial0, serial1, etc.) + * - An ISR function declaration with proper interrupt mapping + * - An ISR function implementation that calls the common ISR handler + * + * Usage: UART_ISR_DECLARE(n) where n is the UART number (0-15) + */ +#define UART_ISR_DECLARE(n) \ + struct rt_serial_device serial##n; \ + SDK_DECLARE_EXT_ISR_M(IRQn_UART##n,uart##n##_isr) \ + void uart##n##_isr(void) \ + { \ + hpm_uart_isr(&serial##n); \ + } \ -#if defined(BSP_USING_UART1) -struct rt_serial_device serial1; -SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) -void uart1_isr(void) -{ - hpm_uart_isr(&serial1); -} +#ifdef BSP_USING_UART0 +UART_ISR_DECLARE(0) #endif - -#if defined(BSP_USING_UART2) -struct rt_serial_device serial2; -SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) -void uart2_isr(void) -{ - hpm_uart_isr(&serial2); -} +#ifdef BSP_USING_UART1 +UART_ISR_DECLARE(1) #endif - -#if defined(BSP_USING_UART3) -struct rt_serial_device serial3; -SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) -void uart3_isr(void) -{ - hpm_uart_isr(&serial3); -} +#ifdef BSP_USING_UART2 +UART_ISR_DECLARE(2) #endif - -#if defined(BSP_USING_UART4) -struct rt_serial_device serial4; -SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) -void uart4_isr(void) -{ - hpm_uart_isr(&serial4); -} +#ifdef BSP_USING_UART3 +UART_ISR_DECLARE(3) #endif - -#if defined(BSP_USING_UART5) -struct rt_serial_device serial5; -SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) -void uart5_isr(void) -{ - hpm_uart_isr(&serial5); -} +#ifdef BSP_USING_UART4 +UART_ISR_DECLARE(4) #endif - -#if defined(BSP_USING_UART6) -struct rt_serial_device serial6; -SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) -void uart6_isr(void) -{ - hpm_uart_isr(&serial6); -} +#ifdef BSP_USING_UART5 +UART_ISR_DECLARE(5) #endif - -#if defined(BSP_USING_UART7) -struct rt_serial_device serial7; -SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) -void uart7_isr(void) -{ - hpm_uart_isr(&serial7); -} +#ifdef BSP_USING_UART6 +UART_ISR_DECLARE(6) #endif - -#if defined(BSP_USING_UART8) -struct rt_serial_device serial8; -SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) -void uart8_isr(void) -{ - hpm_uart_isr(&serial8); -} +#ifdef BSP_USING_UART7 +UART_ISR_DECLARE(7) #endif +#ifdef BSP_USING_UART8 +UART_ISR_DECLARE(8) +#endif -#if defined(BSP_USING_UART9) -struct rt_serial_device serial9; -SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) -void uart9_isr(void) -{ - hpm_uart_isr(&serial9); -} +#ifdef BSP_USING_UART9 +UART_ISR_DECLARE(9) #endif +#ifdef BSP_USING_UART10 +UART_ISR_DECLARE(10) +#endif -#if defined(BSP_USING_UART10) -struct rt_serial_device serial10; -SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) -void uart10_isr(void) -{ - hpm_uart_isr(&serial10); -} +#ifdef BSP_USING_UART11 +UART_ISR_DECLARE(11) #endif -#if defined(BSP_USING_UART11) -struct rt_serial_device serial11; -SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) -void uart11_isr(void) -{ - hpm_uart_isr(&serial11); -} +#ifdef BSP_USING_UART12 +UART_ISR_DECLARE(12) #endif -#if defined(BSP_USING_UART12) -struct rt_serial_device serial12; -SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) -void uart12_isr(void) -{ - hpm_uart_isr(&serial12); -} +#ifdef BSP_USING_UART13 +UART_ISR_DECLARE(13) #endif -#if defined(BSP_USING_UART13) -struct rt_serial_device serial13; -SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) -void uart13_isr(void) -{ - hpm_uart_isr(&serial13); -} +#ifdef BSP_USING_UART14 +UART_ISR_DECLARE(14) #endif -#if defined(BSP_USING_UART14) -struct rt_serial_device serial14; -SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) -void uart14_isr(void) -{ - hpm_uart_isr(&serial14); -} +#ifdef BSP_USING_UART15 +UART_ISR_DECLARE(15) #endif -#if defined(BSP_USING_UART15) -struct rt_serial_device serial15; -SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) -void uart15_isr(void) +#ifdef BSP_USING_PUART +struct rt_serial_device serial_puart; +SDK_DECLARE_EXT_ISR_M(IRQn_PUART, puart_isr) +void puart_isr(void) { - hpm_uart_isr(&serial15); + hpm_uart_isr(&serial_puart); } #endif -static struct hpm_uart uarts[] = -{ -#if defined(BSP_USING_UART0) -{ - HPM_UART0, - IRQn_UART0, -#if defined(BSP_UART0_IRQ_PRIORITY) - .irq_priority = BSP_UART0_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart0, - &serial0, - "uart0", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART0_TX, - HPM_DMA_SRC_UART0_RX, - 0, -#endif -}, -#endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ + +/* ============================================================================ + * UART Structure Initialization Macro + * ============================================================================ + * + * This macro initializes a UART device structure with all necessary configuration + * parameters. It automatically sets up hardware addresses, buffer sizes, interrupt + * priorities, DMA configuration, and device identification. + * + * The macro handles: + * - Hardware register base addresses + * - Buffer size configuration from board definitions + * - Interrupt number and priority assignment + * - DMA enable flags based on configuration + * - Clock source assignment + * - Device name generation + * - DMA multiplexer source configuration + * - DMA resource allocation status initialization + * + * Usage: UART_INIT_STRUCT(n) where n is the UART number (0-15) + */ -#if defined(BSP_USING_UART1) -{ - HPM_UART1, - IRQn_UART1, -#if defined(BSP_UART1_IRQ_PRIORITY) - .irq_priority = BSP_UART1_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart1, - &serial1, - "uart1", #ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART1_TX, - HPM_DMA_SRC_UART1_RX, - 0, -#endif -}, +#define UART_INIT_STRUCT(n) \ + { \ + .uart_base = HPM_UART##n, \ + .txbuf_size = BSP_UART##n##_TX_BUFSIZE, \ + .rxbuf_size = BSP_UART##n##_RX_BUFSIZE, \ + .irq_num = IRQn_UART##n, \ + .irq_priority = UART_IRQ_PRI_VAL(n), \ + .enable_dma = (UART_TX_USING_DMA_VAL(n) || UART_RX_USING_DMA_VAL(n)), \ + .enable_tx_dma = UART_TX_USING_DMA_VAL(n), \ + .enable_rx_dma = UART_RX_USING_DMA_VAL(n), \ + .clk_name = clock_uart##n, \ + .serial = &serial##n, \ + .device_name = "uart" #n, \ + .tx_dma_mux = HPM_DMA_SRC_UART##n##_TX, \ + .rx_dma_mux = HPM_DMA_SRC_UART##n##_RX, \ + .dma_flags = 0, \ + .dma_pingpong_size = BSP_UART##n##_DMA_PINGPONG_BUFSIZE, \ + .rx_buffer_size = BSP_UART##n##_RX_BUFSIZE, \ + .rx_fifo_index = 0, \ + } +#else +#define UART_INIT_STRUCT(n) \ + { \ + .uart_base = HPM_UART##n, \ + .txbuf_size = BSP_UART##n##_TX_BUFSIZE, \ + .rxbuf_size = BSP_UART##n##_RX_BUFSIZE, \ + .irq_num = IRQn_UART##n, \ + .irq_priority = UART_IRQ_PRI_VAL(n), \ + .clk_name = clock_uart##n, \ + .serial = &serial##n, \ + .device_name = "uart" #n, \ + .rx_buffer_size = BSP_UART##n##_RX_BUFSIZE, \ + .rx_fifo_index = 0, \ + } #endif -#if defined(BSP_USING_UART2) -{ - HPM_UART2, - IRQn_UART2, -#if defined(BSP_UART2_IRQ_PRIORITY) - .irq_priority = BSP_UART2_IRQ_PRIORITY, -#else - .irq_priority = 1, + +/* ============================================================================ + * UART Device Array + * ============================================================================ + * + * This array contains all configured UART device structures. Each entry is + * conditionally compiled based on the BSP_USING_UARTx configuration macros. + * The array is used by the driver to manage multiple UART controllers. + */ +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; #endif - clock_uart2, - &serial2, - "uart2", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART2_TX, - HPM_DMA_SRC_UART2_RX, - 0, +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; #endif -}, +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; #endif - #if defined(BSP_USING_UART3) -{ - HPM_UART3, - IRQn_UART3, -#if defined(BSP_UART3_IRQ_PRIORITY) - .irq_priority = BSP_UART3_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart3, - &serial3, - "uart3", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART3_TX, - HPM_DMA_SRC_UART3_RX, - 0, -#endif -}, +struct rt_serial_device serial3; #endif - #if defined(BSP_USING_UART4) -{ - HPM_UART4, - IRQn_UART4, -#if defined(BSP_UART4_IRQ_PRIORITY) - .irq_priority = BSP_UART4_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart4, - &serial4, - "uart4", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART4_TX, - HPM_DMA_SRC_UART4_RX, - 0, -#endif -}, +struct rt_serial_device serial4; #endif - #if defined(BSP_USING_UART5) -{ - HPM_UART5, - IRQn_UART5, -#if defined(BSP_UART5_IRQ_PRIORITY) - .irq_priority = BSP_UART5_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart5, - &serial5, - "uart5", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART5_TX, - HPM_DMA_SRC_UART5_RX, - 0, -#endif -}, +struct rt_serial_device serial5; #endif - #if defined(BSP_USING_UART6) -{ - HPM_UART6, - IRQn_UART6, -#if defined(BSP_UART6_IRQ_PRIORITY) - .irq_priority = BSP_UART6_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart6, - &serial6, - "uart6", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART6_TX, - HPM_DMA_SRC_UART6_RX, - 0, -#endif -}, +struct rt_serial_device serial6; #endif - #if defined(BSP_USING_UART7) -{ - HPM_UART7, - IRQn_UART7, -#if defined(BSP_UART7_IRQ_PRIORITY) - .irq_priority = BSP_UART7_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart7, - &serial7, - "uart7", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART7_TX, - HPM_DMA_SRC_UART7_RX, - 0, -#endif -}, +struct rt_serial_device serial7; #endif - #if defined(BSP_USING_UART8) -{ - HPM_UART8, - IRQn_UART8, -#if defined(BSP_UART8_IRQ_PRIORITY) - .irq_priority = BSP_UART8_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart8, - &serial8, - "uart8", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART8_TX, - HPM_DMA_SRC_UART8_RX, - 0, -#endif -}, +struct rt_serial_device serial8; #endif - #if defined(BSP_USING_UART9) -{ - HPM_UART9, - IRQn_UART9, -#if defined(BSP_UART9_IRQ_PRIORITY) - .irq_priority = BSP_UART9_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart9, - &serial9, - "uart9", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART9_TX, - HPM_DMA_SRC_UART9_RX, - 0, -#endif -}, +struct rt_serial_device serial9; #endif - #if defined(BSP_USING_UART10) -{ - HPM_UART10, - IRQn_UART10, -#if defined(BSP_UART10_IRQ_PRIORITY) - .irq_priority = BSP_UART10_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart10, - &serial10, - "uart10", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART10_TX, - HPM_DMA_SRC_UART10_RX, - 0, -#endif -}, +struct rt_serial_device serial10; #endif - #if defined(BSP_USING_UART11) -{ - HPM_UART11, - IRQn_UART11, -#if defined(BSP_UART11_IRQ_PRIORITY) - .irq_priority = BSP_UART11_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart11, - &serial11, - "uart11", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART11_TX, - HPM_DMA_SRC_UART11_RX, - 0, -#endif -}, +struct rt_serial_device serial11; #endif - #if defined(BSP_USING_UART12) -{ - HPM_UART12, - IRQn_UART12, -#if defined(BSP_UART12_IRQ_PRIORITY) - .irq_priority = BSP_UART12_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart12, - &serial12, - "uart12", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART12_TX, - HPM_DMA_SRC_UART12_RX, - 0, -#endif -}, +struct rt_serial_device serial12; #endif - #if defined(BSP_USING_UART13) -{ - HPM_UART13, - IRQn_UART13, -#if defined(BSP_UART13_IRQ_PRIORITY) - .irq_priority = BSP_UART13_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart13, - &serial13, - "uart13", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART13_TX, - HPM_DMA_SRC_UART13_RX, - 0, -#endif -}, +struct rt_serial_device serial13; #endif - #if defined(BSP_USING_UART14) -{ - HPM_UART14, - IRQn_UART14, -#if defined(BSP_UART14_IRQ_PRIORITY) - .irq_priority = BSP_UART14_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart14, - &serial14, - "uart14", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART14_TX, - HPM_DMA_SRC_UART14_RX, - 0, -#endif -}, +struct rt_serial_device serial14; #endif - #if defined(BSP_USING_UART15) -{ - HPM_UART15, - IRQn_UART15, -#if defined(BSP_UART15_IRQ_PRIORITY) - .irq_priority = BSP_UART15_IRQ_PRIORITY, -#else - .irq_priority = 1, -#endif - clock_uart15, - &serial15, - "uart15", -#ifdef RT_SERIAL_USING_DMA - HPM_DMA_SRC_UART15_TX, - HPM_DMA_SRC_UART15_RX, - 0, +struct rt_serial_device serial15; #endif -}, +#if defined(BSP_USING_PUART) +struct rt_serial_device serial_puart; #endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ -}; - -enum +static struct hpm_uart uarts[] = { #if defined(BSP_USING_UART0) - HPM_UART0_INDEX, + UART_INIT_STRUCT(0), #endif #if defined(BSP_USING_UART1) - HPM_UART1_INDEX, + UART_INIT_STRUCT(1), #endif #if defined(BSP_USING_UART2) - HPM_UART2_INDEX, + UART_INIT_STRUCT(2), #endif #if defined(BSP_USING_UART3) - HPM_UART3_INDEX, + UART_INIT_STRUCT(3), #endif #if defined(BSP_USING_UART4) - HPM_UART4_INDEX, + UART_INIT_STRUCT(4), #endif #if defined(BSP_USING_UART5) - HPM_UART5_INDEX, + UART_INIT_STRUCT(5), #endif #if defined(BSP_USING_UART6) - HPM_UART6_INDEX, + UART_INIT_STRUCT(6), #endif #if defined(BSP_USING_UART7) - HPM_UART7_INDEX, + UART_INIT_STRUCT(7), #endif #if defined(BSP_USING_UART8) - HPM_UART8_INDEX, + UART_INIT_STRUCT(8), #endif #if defined(BSP_USING_UART9) - HPM_UART9_INDEX, + UART_INIT_STRUCT(9), #endif #if defined(BSP_USING_UART10) - HPM_UART10_INDEX, + UART_INIT_STRUCT(10), #endif #if defined(BSP_USING_UART11) - HPM_UART11_INDEX, + UART_INIT_STRUCT(11), #endif #if defined(BSP_USING_UART12) - HPM_UART12_INDEX, + UART_INIT_STRUCT(12), #endif #if defined(BSP_USING_UART13) - HPM_UART13_INDEX, + UART_INIT_STRUCT(13), #endif #if defined(BSP_USING_UART14) - HPM_UART14_INDEX, + UART_INIT_STRUCT(14), #endif #if defined(BSP_USING_UART15) - HPM_UART15_INDEX, + UART_INIT_STRUCT(15), +#endif + +#if defined(BSP_USING_PUART) + { + .uart_base = HPM_PUART, + .txbuf_size = BSP_PUART_TX_BUFSIZE, + .rxbuf_size = BSP_PUART_RX_BUFSIZE, + .irq_num = IRQn_PUART, + .irq_priority = BSP_PUART_IRQ_PRIORITY, + .clk_name = clock_puart, + .serial = &serial_puart, + .device_name = "puart", + .rx_buffer_size = BSP_PUART_RX_BUFSIZE, + .rx_fifo_index = 0, + } #endif }; + + #if defined(RT_SERIAL_USING_DMA) +/** + * @brief DMA transfer completion callback + * + * This function is called when a DMA transfer completes successfully. + * It validates the DMA resource and calls the appropriate completion callback. + * + * @param base DMA controller base address + * @param channel DMA channel number + * @param user_data Pointer to DMA channel handle + */ static void uart_dma_tc_callback(DMA_Type *base, uint32_t channel, void *user_data) { hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + + /* Validate DMA resource to ensure this callback is for the correct channel */ if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { return; } - dma_handle->tranfer_done(dma_handle->serial); + + /* Call the transfer completion callback */ + if (dma_handle->transfer_done != RT_NULL) { + dma_handle->transfer_done(dma_handle->serial); + } } +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +/** + * @brief DMA half transfer completion callback + * + * This function is called when a DMA transfer reaches half completion. + * It validates the DMA resource and calls the appropriate half transfer callback. + * + * @param base DMA controller base address + * @param channel DMA channel number + * @param user_data Pointer to DMA channel handle + */ +static void uart_dma_htc_callback(DMA_Type *base, uint32_t channel, void *user_data) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + + /* Validate DMA resource to ensure this callback is for the correct channel */ + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) + { + return; + } + + /* Call the half transfer completion callback */ + if (dma_handle->halftransfer_cb != RT_NULL) { + dma_handle->halftransfer_cb(dma_handle->serial); + } +} + +#endif + +/** + * @brief DMA receive interrupt service routine + * + * This function handles DMA receive interrupts, processes received data, + * and notifies the RT-Thread serial framework about the received data. + * + * @param serial Pointer to the serial device structure + * @param isr_flag Interrupt flag indicating the type of interrupt + */ +static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + rt_size_t recv_len, counter; + rt_base_t level; + RT_ASSERT(serial != RT_NULL); + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + /* Skip processing if ping buffer is not configured */ + if (serial->config.dma_ping_bufsz == 0) { + return; + } + + if (isr_flag == UART_RX_DMA_IT_TC_FLAG) { + level = rt_hw_interrupt_disable(); + dma_mgr_disable_channel(&uart->rx_chn_ctx.resource); + } + counter = dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); + if (counter <= uart->dma_rx_remain_size) { + recv_len = uart->dma_rx_remain_size - counter; + } else { + recv_len = serial->config.dma_ping_bufsz + uart->dma_rx_remain_size - counter; + } + if (recv_len > 0) { + rt_uint8_t *ptr = NULL; + rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ptr); + if (l1c_dc_is_enabled()) { + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)ptr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)ptr + serial->config.dma_ping_bufsz); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); + } + uart->dma_rx_remain_size = counter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + if (isr_flag == UART_RX_DMA_IT_TC_FLAG) { + rt_hw_interrupt_enable(level); + dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); + } +} + +/** + * @brief DMA transfer abort callback + * + * This function is called when a DMA transfer is aborted. + * It validates the DMA resource and calls the appropriate abort callback. + * + * @param base DMA controller base address + * @param channel DMA channel number + * @param user_data Pointer to DMA channel handle + */ static void uart_dma_abort_callback(DMA_Type *base, uint32_t channel, void *user_data) { hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + + /* Validate DMA resource to ensure this callback is for the correct channel */ if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { return; } - dma_handle->tranfer_abort(dma_handle->serial); + + /* Call the transfer abort callback */ + if (dma_handle->transfer_abort != RT_NULL) { + dma_handle->transfer_abort(dma_handle->serial); + } } +/** + * @brief DMA transfer error callback + * + * This function is called when a DMA transfer encounters an error. + * It validates the DMA resource and calls the appropriate error callback. + * + * @param base DMA controller base address + * @param channel DMA channel number + * @param user_data Pointer to DMA channel handle + */ static void uart_dma_error_callback(DMA_Type *base, uint32_t channel, void *user_data) { hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + + /* Validate DMA resource to ensure this callback is for the correct channel */ if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { return; } - dma_handle->tranfer_error(dma_handle->serial); + + /* Call the transfer error callback */ + if (dma_handle->transfer_error != RT_NULL) { + dma_handle->transfer_error(dma_handle->serial); + } } +/** + * @brief UART TX DMA transfer completion handler + * + * This function is called when a TX DMA transfer completes. + * It notifies the RT-Thread serial framework about the completion. + * + * @param serial Pointer to the serial device structure + */ static void uart_tx_done(struct rt_serial_device *serial) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); } +/** + * @brief UART RX DMA transfer completion handler + * + * This function is called when an RX DMA transfer completes. + * It handles cache coherency, processes received data, and notifies + * the RT-Thread serial framework about the completion. + * + * @param serial Pointer to the serial device structure + */ static void uart_rx_done(struct rt_serial_device *serial) { struct rt_serial_rx_fifo *rx_fifo; rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; - #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) - uint32_t uart_recv_data_count = 0; - struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; - uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer); - uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); - if (l1c_dc_is_enabled()) { - uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)uart->rx_idle_tmp_buffer); - uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)uart->rx_idle_tmp_buffer + rx_idle_tmp_buffer_size); - uint32_t aligned_size = aligned_end - aligned_start; - l1c_dc_invalidate(aligned_start, aligned_size); - } - /* if open uart again after closing uart, an idle interrupt may be triggered, but uart initialization is not performed at this time, and the program exits if the rxfifo is empty. */ - if (rx_fifo == RT_NULL) { - return; - } - rt_ringbuffer_put(&(rx_fifo->rb), uart->rx_idle_tmp_buffer, uart_recv_data_count); - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE); +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) + dma_recv_isr(serial, UART_RX_DMA_IT_TC_FLAG); +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + /* DMAV2 supports circular mode, no need to reconfigure DMA, can return directly */ + return; +#endif #else if (l1c_dc_is_enabled()) { uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)rx_fifo->rb.buffer_ptr); @@ -711,18 +694,46 @@ static void uart_rx_done(struct rt_serial_device *serial) l1c_dc_invalidate(aligned_start, aligned_size); } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8)); -#endif /* prepare for next read */ +#endif hpm_uart_receive_dma_next(serial); } + +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 +/** + * @brief UART RX DMA half transfer completion handler + * + * This function is called when an RX DMA transfer reaches half completion. + * It handles cache coherency and processes received data. + * + * @param serial Pointer to the serial device structure + */ +static void uart_rx_half_done(struct rt_serial_device *serial) +{ + dma_recv_isr(serial, UART_RX_DMA_IT_HT_FLAG); +} +#endif #endif /* RT_SERIAL_USING_DMA */ /** - * @brief UART common interrupt process. This + * @brief UART common interrupt service routine + * + * This function handles all UART interrupt events including: + * - RX data available: Reads data from UART FIFO and stores in ring buffer + * - RX timeout: Handles timeout conditions and overrun errors + * - TX slot available: Transmits data from ring buffer to UART FIFO + * - RX idle detection: Handles DMA-based RX idle detection (if supported) * - * @param serial Serial device + * The function processes interrupts efficiently by reading multiple bytes + * when possible and managing ring buffer operations. + * + * @param serial Pointer to the serial device structure */ +#ifndef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK static void hpm_uart_isr(struct rt_serial_device *serial) +#else +static void hpm_uart_isr(int vector, struct rt_serial_device *serial) +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ { struct hpm_uart *uart; rt_uint32_t stat, enabled_irq; @@ -743,6 +754,7 @@ static void hpm_uart_isr(struct rt_serial_device *serial) if (irq_id == uart_intr_id_rx_data_avail) { while (uart_check_status(uart->uart_base, uart_stat_data_ready)) { count++; + uart->rx_fifo_index++; put_char = uart_read_byte(uart->uart_base); rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); /*in order to ensure rx fifo there are remaining bytes*/ @@ -751,26 +763,31 @@ static void hpm_uart_isr(struct rt_serial_device *serial) } } } - + /* check if RX FIFO index has reached minimum buffer size */ + if (uart->rx_fifo_index >= RT_SERIAL_RX_MINBUFSZ) { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + uart->rx_fifo_index = 0; + } if (irq_id == uart_intr_id_rx_timeout) { while ((uart_check_status(uart->uart_base, uart_stat_data_ready)) || (uart_check_status(uart->uart_base, uart_stat_overrun_error))) { put_char= uart_read_byte(uart->uart_base); rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + uart->rx_fifo_index = 0; } - if ((irq_id & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { + if ((irq_id == uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { /* UART in mode Transmitter */ struct rt_serial_tx_fifo *tx_fifo; tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; RT_ASSERT(tx_fifo != RT_NULL); rt_uint8_t put_char = 0; uint32_t fifo_size = 0, ringbuffer_data_len = 0, tx_size = 0; - uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); fifo_size = uart_get_fifo_size(uart->uart_base); ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); - if (ringbuffer_data_len <= 0) { + if (ringbuffer_data_len == 0) { + uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); } else { tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; @@ -778,25 +795,31 @@ static void hpm_uart_isr(struct rt_serial_device *serial) rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); uart_write_byte(uart->uart_base, put_char); } - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); } } - #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) if (uart_is_rxline_idle(uart->uart_base)) { - if ((uart->rx_chn_ctx.resource.base != RT_NULL) && (dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel) > 0)) { - /* if the rxline is idle, but the dma transfer is not finished, it means that the rxline idle interrupt is triggered before the dma transfer is finished */ - uart_rx_done(serial); - } uart_clear_rxline_idle_flag(uart->uart_base); - uart_flush(uart->uart_base); + dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); } #endif } +/** + * @brief Configure UART parameters + * + * This function configures the UART hardware with the specified parameters + * including baud rate, data bits, stop bits, parity, and DMA settings. + * It also initializes the UART pins and clock configuration. + * + * @param serial Pointer to the serial device structure + * @param cfg Pointer to the serial configuration structure + * @return RT_EOK on success, -RT_ERROR on failure + */ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - + /* Validate input parameters */ RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); @@ -849,6 +872,9 @@ hpm_stat_t hpm_uart_dma_rx_init(struct hpm_uart *uart_ctx) uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_RX; uart_ctx->rx_resource_allocated = true; dma_mgr_install_chn_tc_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_tc_callback, &uart_ctx->rx_chn_ctx); +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + dma_mgr_install_chn_half_tc_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_htc_callback, &uart_ctx->rx_chn_ctx); +#endif dma_mgr_install_chn_abort_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_abort_callback, &uart_ctx->rx_chn_ctx); dma_mgr_install_chn_error_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_error_callback, &uart_ctx->rx_chn_ctx); } @@ -890,12 +916,18 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) chg_config.dmamux_src = uart->rx_dma_mux; chg_config.src_addr = (uint32_t)&(uart->uart_base->RBR); chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; - chg_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; chg_config.src_width = DMA_TRANSFER_WIDTH_BYTE; #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - chg_config.dst_addr = (uint32_t)uart->rx_idle_tmp_buffer; - chg_config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + chg_config.en_infiniteloop = true; +#endif + uart->dma_rx_remain_size = serial->config.dma_ping_bufsz; + rt_uint8_t *ptr = NULL; + rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ptr); + chg_config.dst_addr = (uint32_t)ptr; + chg_config.size_in_byte = serial->config.dma_ping_bufsz; #else chg_config.dst_addr = (uint32_t)rx_fifo->rb.buffer_ptr; chg_config.size_in_byte = serial->config.rx_bufsz; @@ -904,9 +936,14 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) return -RT_ERROR; } dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); +#ifdef HPMSOC_HAS_HPMSDK_DMAV2 + dma_mgr_enable_chn_irq(&uart->rx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC | DMA_MGR_INTERRUPT_MASK_HALF_TC); + hpm_uart_dma_register_channel(serial, false, uart_rx_done, uart_rx_half_done, RT_NULL, RT_NULL); +#else dma_mgr_enable_chn_irq(&uart->rx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); - dma_mgr_enable_dma_irq_with_priority(&uart->rx_chn_ctx.resource, 1); - hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); + hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL, RT_NULL); +#endif + dma_mgr_enable_dma_irq_with_priority(&uart->rx_chn_ctx.resource, uart->irq_priority); #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); #endif @@ -936,8 +973,11 @@ static void hpm_uart_receive_dma_next(struct rt_serial_device *serial) struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - buf_addr = (uint32_t)uart->rx_idle_tmp_buffer; - buf_size = sizeof(uart->rx_idle_tmp_buffer); + rt_uint8_t *ptr = NULL; + uart->dma_rx_remain_size = serial->config.dma_ping_bufsz; + rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ptr); + buf_addr = (uint32_t)ptr; + buf_size = serial->config.dma_ping_bufsz; #else buf_addr = (uint32_t)rx_fifo->rb.buffer_ptr; buf_size = serial->config.rx_bufsz; @@ -957,8 +997,23 @@ static void hpm_uart_transmit_dma(struct rt_serial_device *serial, uint8_t *src, #endif /* RT_SERIAL_USING_DMA */ +/** + * @brief Control UART operations + * + * This function handles various UART control operations including: + * - Interrupt enable/disable (RX/TX) + * - DMA enable/disable and configuration + * - Buffer allocation and management + * - Operation mode checking + * + * @param serial Pointer to the serial device structure + * @param cmd Control command (RT_DEVICE_CTRL_*) + * @param arg Command argument + * @return RT_EOK on success, -RT_ERROR on failure + */ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { + /* Validate input parameters */ RT_ASSERT(serial != RT_NULL); rt_ubase_t ctrl_arg = (rt_ubase_t) arg; @@ -1032,35 +1087,65 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); } else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) { /* enable tx irq */ - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); } break; case RT_DEVICE_CTRL_CONFIG: #ifdef RT_SERIAL_USING_DMA - if ((ctrl_arg == RT_DEVICE_FLAG_DMA_RX) || (ctrl_arg == RT_DEVICE_FLAG_INT_RX)) { - if ((rx_fifo) && (((rt_uint32_t)rx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (rx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { - rt_free(rx_fifo); + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + if ((!rx_fifo) || (((rt_uint32_t)rx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (rx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { + if (rx_fifo) { + rt_free(rx_fifo); + } rx_fifo = RT_NULL; rx_fifo = (struct rt_serial_rx_fifo *) rt_malloc(sizeof(struct rt_serial_rx_fifo)); RT_ASSERT(rx_fifo != RT_NULL); - tmp_buffer = rt_malloc(serial->config.rx_bufsz + HPM_L1C_CACHELINE_SIZE); + + /* Calculate total buffer size needed for both ring buffers plus alignment padding */ + rt_uint32_t rx_tmp_size = serial->config.rx_bufsz + serial->config.dma_ping_bufsz; + /* Allocate extra cacheline size for alignment: + * - 1x for main buffer alignment + * - 1x for ping buffer alignment (if ping buffer is used) + */ + rt_uint32_t extra_align = (serial->config.dma_ping_bufsz > 0) ? + (2 * HPM_L1C_CACHELINE_SIZE) : HPM_L1C_CACHELINE_SIZE; + if (rx_tmp_size > (UINT32_MAX - extra_align)) { + return -RT_ERROR; + } + tmp_buffer = rt_malloc(rx_tmp_size + extra_align); RT_ASSERT(tmp_buffer != RT_NULL); + + /* Free old buffer if exists */ if (uart->rx_chn_ctx.ringbuf_ptr != RT_NULL) { rt_free(uart->rx_chn_ctx.ringbuf_ptr); } + /* Save original pointer for later deallocation */ uart->rx_chn_ctx.ringbuf_ptr = (void *)tmp_buffer; + + /* Align first buffer (main RX ring buffer) */ tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE)); rt_ringbuffer_init(&rx_fifo->rb, tmp_buffer, serial->config.rx_bufsz); rt_ringbuffer_reset(&rx_fifo->rb); + + /* Initialize DMA ping buffer only if size is non-zero */ + if (serial->config.dma_ping_bufsz > 0) { + /* Move to next buffer position and align DMA ping buffer */ + tmp_buffer += serial->config.rx_bufsz; /* Move past the main buffer */ + tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE)); + rt_ringbuffer_init(&rx_fifo->dma_ping_rb, tmp_buffer, serial->config.dma_ping_bufsz); + rt_ringbuffer_reset(&rx_fifo->dma_ping_rb); + } + serial->serial_rx = rx_fifo; } } - if ((ctrl_arg == RT_DEVICE_FLAG_DMA_TX) || (ctrl_arg == RT_DEVICE_FLAG_INT_TX)) { - if ((tx_fifo) && (((rt_uint32_t)tx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (tx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { - rt_free(tx_fifo); + if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { + if ((!tx_fifo) || (((rt_uint32_t)tx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (tx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { + if (tx_fifo) { + rt_free(tx_fifo); + } tx_fifo = RT_NULL; tx_fifo = (struct rt_serial_tx_fifo *) rt_malloc(sizeof(struct rt_serial_tx_fifo)); RT_ASSERT(tx_fifo != RT_NULL); @@ -1102,19 +1187,44 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void } +/** + * @brief Send a single character via UART + * + * This function sends a single character through the UART interface. + * It uses blocking operation and flushes the UART buffer after transmission. + * + * @param serial Pointer to the serial device structure + * @param ch Character to send + * @return RT_EOK on success, -RT_ERROR on failure + */ static int hpm_uart_putc(struct rt_serial_device *serial, char ch) { - struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; - uart_send_byte(uart->uart_base, ch); - uart_flush(uart->uart_base); - return ch; + hpm_stat_t stat; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + /* Send the character and flush the UART buffer */ + stat = uart_send_byte(uart->uart_base, ch); + if (stat == status_success) { + stat = uart_flush(uart->uart_base); + } + return (stat == status_success) ? RT_EOK : -RT_ERROR; } +/** + * @brief Receive a single character from UART + * + * This function receives a single character from the UART interface. + * It checks if data is available before attempting to read. + * + * @param serial Pointer to the serial device structure + * @return The received character, or -1 if no data is available + */ static int hpm_uart_getc(struct rt_serial_device *serial) { int result = -1; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + /* Check if data is available in the UART FIFO */ if (uart_check_status(uart->uart_base, uart_stat_data_ready)) { uart_receive_byte(uart->uart_base, (uint8_t*)&result); } @@ -1122,6 +1232,18 @@ static int hpm_uart_getc(struct rt_serial_device *serial) return result; } +/** + * @brief Transmit data via UART + * + * This function transmits data through the UART interface using either + * DMA or interrupt-driven methods based on the configuration. + * + * @param serial Pointer to the serial device structure + * @param buf Pointer to the data buffer to transmit + * @param size Number of bytes to transmit + * @param tx_flag Transmission flags + * @return Number of bytes transmitted + */ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, @@ -1139,7 +1261,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, RT_ASSERT(tx_fifo != RT_NULL); #ifdef RT_SERIAL_USING_DMA if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) { - hpm_uart_dma_register_channel(serial, true, uart_tx_done, RT_NULL, RT_NULL); + hpm_uart_dma_register_channel(serial, true, uart_tx_done, RT_NULL, RT_NULL, RT_NULL); intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num); if (l1c_dc_is_enabled()) { uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)buf); @@ -1171,398 +1293,92 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, return size; } +/** + * @brief UART operations structure + * + * This structure defines the function pointers for all UART operations. + * It provides the interface between RT-Thread's serial framework and + * the HPM UART driver implementation. + */ static const struct rt_uart_ops hpm_uart_ops = { - hpm_uart_configure, - hpm_uart_control, - hpm_uart_putc, - hpm_uart_getc, - hpm_uart_transmit, + .configure = hpm_uart_configure, /* Configure UART parameters */ + .control = hpm_uart_control, /* Control UART operations */ + .putc = hpm_uart_putc, /* Send single character */ + .getc = hpm_uart_getc, /* Receive single character */ + .transmit = hpm_uart_transmit, /* Transmit data buffer */ }; +/** + * @brief Configure all UART devices + * + * This function configures all enabled UART devices with default settings + * and initializes DMA resources if configured. It sets up buffer sizes, + * DMA channels, and other device-specific parameters. + * + * @return RT_EOK on success, -RT_ERROR on failure + */ static int hpm_uart_config(void) { - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - hpm_stat_t status = status_success; - -#ifdef BSP_USING_UART0 - uarts[HPM_UART0_INDEX].serial->config = config; - uarts[HPM_UART0_INDEX].serial->config.rx_bufsz = BSP_UART0_RX_BUFSIZE; - uarts[HPM_UART0_INDEX].serial->config.tx_bufsz = BSP_UART0_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART0_INDEX].dma_flags = 0; -#ifdef BSP_UART0_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART0_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART0_RX_USING_DMA -#ifdef BSP_UART0_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART0_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART0_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART0 + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; /* Default serial configuration */ + hpm_stat_t status = status_success; /* DMA initialization status */ -#ifdef BSP_USING_UART1 - uarts[HPM_UART1_INDEX].serial->config = config; - uarts[HPM_UART1_INDEX].serial->config.rx_bufsz = BSP_UART1_RX_BUFSIZE; - uarts[HPM_UART1_INDEX].serial->config.tx_bufsz = BSP_UART1_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART1_INDEX].dma_flags = 0; -#ifdef BSP_UART1_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART1_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART1_RX_USING_DMA -#ifdef BSP_UART1_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART1_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART1_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART1 - -#ifdef BSP_USING_UART2 - uarts[HPM_UART2_INDEX].serial->config = config; - uarts[HPM_UART2_INDEX].serial->config.rx_bufsz = BSP_UART2_RX_BUFSIZE; - uarts[HPM_UART2_INDEX].serial->config.tx_bufsz = BSP_UART2_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART2_INDEX].dma_flags = 0; -#ifdef BSP_UART2_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART2_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART2_RX_USING_DMA -#ifdef BSP_UART2_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART2_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART2_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART2 - -#ifdef BSP_USING_UART3 - uarts[HPM_UART3_INDEX].serial->config = config; - uarts[HPM_UART3_INDEX].serial->config.rx_bufsz = BSP_UART3_RX_BUFSIZE; - uarts[HPM_UART3_INDEX].serial->config.tx_bufsz = BSP_UART3_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART3_INDEX].dma_flags = 0; -#ifdef BSP_UART3_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART3_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART3_RX_USING_DMA -#ifdef BSP_UART3_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART3_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART3_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART3 - -#ifdef BSP_USING_UART4 - uarts[HPM_UART4_INDEX].serial->config = config; - uarts[HPM_UART4_INDEX].serial->config.rx_bufsz = BSP_UART4_RX_BUFSIZE; - uarts[HPM_UART4_INDEX].serial->config.tx_bufsz = BSP_UART4_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART4_INDEX].dma_flags = 0; -#ifdef BSP_UART4_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART4_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART4_RX_USING_DMA -#ifdef BSP_UART4_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART4_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART4_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART4 - -#ifdef BSP_USING_UART5 - uarts[HPM_UART5_INDEX].serial->config = config; - uarts[HPM_UART5_INDEX].serial->config.rx_bufsz = BSP_UART5_RX_BUFSIZE; - uarts[HPM_UART5_INDEX].serial->config.tx_bufsz = BSP_UART5_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART5_INDEX].dma_flags = 0; -#ifdef BSP_UART5_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART5_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART5_RX_USING_DMA -#ifdef BSP_UART5_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART5_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART5_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART5 - -#ifdef BSP_USING_UART6 - uarts[HPM_UART6_INDEX].serial->config = config; - uarts[HPM_UART6_INDEX].serial->config.rx_bufsz = BSP_UART6_RX_BUFSIZE; - uarts[HPM_UART6_INDEX].serial->config.tx_bufsz = BSP_UART6_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART6_INDEX].dma_flags = 0; -#ifdef BSP_UART6_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART6_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART6_RX_USING_DMA -#ifdef BSP_UART6_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART6_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART6_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART6 - -#ifdef BSP_USING_UART7 - uarts[HPM_UART7_INDEX].serial->config = config; - uarts[HPM_UART7_INDEX].serial->config.rx_bufsz = BSP_UART7_RX_BUFSIZE; - uarts[HPM_UART7_INDEX].serial->config.tx_bufsz = BSP_UART7_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART7_INDEX].dma_flags = 0; -#ifdef BSP_UART7_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART7_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART7_RX_USING_DMA -#ifdef BSP_UART7_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART7_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART7_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART7 - -#ifdef BSP_USING_UART8 - uarts[HPM_UART8_INDEX].serial->config = config; - uarts[HPM_UART8_INDEX].serial->config.rx_bufsz = BSP_UART8_RX_BUFSIZE; - uarts[HPM_UART8_INDEX].serial->config.tx_bufsz = BSP_UART8_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART8_INDEX].dma_flags = 0; -#ifdef BSP_UART8_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART8_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART8_RX_USING_DMA -#ifdef BSP_UART8_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART8_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART8_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART8 - -#ifdef BSP_USING_UART9 - uarts[HPM_UART9_INDEX].serial->config = config; - uarts[HPM_UART9_INDEX].serial->config.rx_bufsz = BSP_UART9_RX_BUFSIZE; - uarts[HPM_UART9_INDEX].serial->config.tx_bufsz = BSP_UART9_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART9_INDEX].dma_flags = 0; -#ifdef BSP_UART9_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART9_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART9_RX_USING_DMA -#ifdef BSP_UART9_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART9_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART9_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART9 - -#ifdef BSP_USING_UART10 - uarts[HPM_UART10_INDEX].serial->config = config; - uarts[HPM_UART10_INDEX].serial->config.rx_bufsz = BSP_UART10_RX_BUFSIZE; - uarts[HPM_UART10_INDEX].serial->config.tx_bufsz = BSP_UART10_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART10_INDEX].dma_flags = 0; -#ifdef BSP_UART10_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART10_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART10_RX_USING_DMA -#ifdef BSP_UART10_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART10_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART10_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART10 - -#ifdef BSP_USING_UART11 - uarts[HPM_UART11_INDEX].serial->config = config; - uarts[HPM_UART11_INDEX].serial->config.rx_bufsz = BSP_UART11_RX_BUFSIZE; - uarts[HPM_UART11_INDEX].serial->config.tx_bufsz = BSP_UART11_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART11_INDEX].dma_flags = 0; -#ifdef BSP_UART11_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART11_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART11_RX_USING_DMA -#ifdef BSP_UART11_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART11_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART11_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART11 - -#ifdef BSP_USING_UART12 - uarts[HPM_UART12_INDEX].serial->config = config; - uarts[HPM_UART12_INDEX].serial->config.rx_bufsz = BSP_UART12_RX_BUFSIZE; - uarts[HPM_UART12_INDEX].serial->config.tx_bufsz = BSP_UART12_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART12_INDEX].dma_flags = 0; -#ifdef BSP_UART12_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART12_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART12_RX_USING_DMA -#ifdef BSP_UART12_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART12_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART12_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART12 - -#ifdef BSP_USING_UART13 - uarts[HPM_UART13_INDEX].serial->config = config; - uarts[HPM_UART13_INDEX].serial->config.rx_bufsz = BSP_UART13_RX_BUFSIZE; - uarts[HPM_UART13_INDEX].serial->config.tx_bufsz = BSP_UART13_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART13_INDEX].dma_flags = 0; -#ifdef BSP_UART13_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART13_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART13_RX_USING_DMA -#ifdef BSP_UART13_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART13_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART13_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART13 - -#ifdef BSP_USING_UART14 - uarts[HPM_UART14_INDEX].serial->config = config; - uarts[HPM_UART14_INDEX].serial->config.rx_bufsz = BSP_UART14_RX_BUFSIZE; - uarts[HPM_UART14_INDEX].serial->config.tx_bufsz = BSP_UART14_TX_BUFSIZE; -#ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART14_INDEX].dma_flags = 0; -#ifdef BSP_UART14_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART14_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART14_RX_USING_DMA -#ifdef BSP_UART14_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART14_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART14_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART14 - -#ifdef BSP_USING_UART15 - uarts[HPM_UART15_INDEX].serial->config = config; - uarts[HPM_UART15_INDEX].serial->config.rx_bufsz = BSP_UART15_RX_BUFSIZE; - uarts[HPM_UART15_INDEX].serial->config.tx_bufsz = BSP_UART15_TX_BUFSIZE; + for (uint32_t i=0; i < ARRAY_SIZE(uarts); i++) { + struct hpm_uart *uart = &uarts[i]; + uart->serial->config = config; + uart->serial->config.rx_bufsz = uart->rxbuf_size; + uart->serial->config.tx_bufsz = uart->txbuf_size; + uart->dma_flags = 0; + if (uart->enable_rx_dma) { +#if defined (RT_SERIAL_USING_DMA) + status = hpm_uart_dma_rx_init(uart); + if (status != status_success) { + return -RT_ERROR; + } +#else + return -RT_ERROR; +#endif + } else { + uart->dma_flags = (uart->dma_flags & ~RT_DEVICE_FLAG_DMA_RX) | RT_DEVICE_FLAG_INT_RX; + } + if (uart->enable_tx_dma) { +#if defined (RT_SERIAL_USING_DMA) + status = hpm_uart_dma_tx_init(uart); + if (status != status_success) { + return -RT_ERROR; + } +#else + return -RT_ERROR; +#endif + } else { + uart->dma_flags = (uart->dma_flags & ~RT_DEVICE_FLAG_DMA_TX) | RT_DEVICE_FLAG_INT_TX; + } #ifdef RT_SERIAL_USING_DMA - uarts[HPM_UART15_INDEX].dma_flags = 0; -#ifdef BSP_UART15_RX_USING_DMA - status = hpm_uart_dma_rx_init(&uarts[HPM_UART15_INDEX]); - if (status != status_success) - { - return -RT_ERROR; - } -#endif //BSP_UART15_RX_USING_DMA -#ifdef BSP_UART15_TX_USING_DMA - status = hpm_uart_dma_tx_init(&uarts[HPM_UART15_INDEX]); - if (status != status_success) - { - return -RT_ERROR; + if (uart->enable_rx_dma) { + uart->serial->config.dma_ping_bufsz = uart->dma_pingpong_size; + } +#endif } -#endif //BSP_UART15_TX_USING_DMA -#endif // RT_SERIAL_USING_DMA -#endif //BSP_USING_UART15 - return RT_EOK; } +/** + * @brief Initialize UART hardware + * + * This function initializes all configured UART devices and registers them + * with the RT-Thread device framework. It includes protection against + * multiple initialization calls. + * + * @return RT_EOK on success, -RT_ERROR on failure + */ int rt_hw_uart_init(void) { - /* Added bypass logic here since the rt_hw_uart_init function will be initialized twice, the 2nd initialization should be bypassed */ + /* Protection against multiple initialization calls */ static bool initialized; rt_err_t err = RT_EOK; + if (initialized) { return err; @@ -1576,7 +1392,7 @@ int rt_hw_uart_init(void) return -RT_ERROR; } - for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { + for (uint32_t i = 0; i < ARRAY_SIZE(uarts); i++) { uarts[i].serial->ops = &hpm_uart_ops; /* register UART device */ @@ -1584,11 +1400,16 @@ int rt_hw_uart_init(void) uarts[i].device_name, RT_DEVICE_FLAG_RDWR, (void*)&uarts[i]); +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register UART device to irq table */ + rt_hw_interrupt_install(uarts[i].irq_num, (rt_isr_handler_t)hpm_uart_isr, uarts[i].serial, uarts[i].device_name); +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ } return err; } +/* Register UART initialization function to be called during board initialization */ INIT_BOARD_EXPORT(rt_hw_uart_init); -#endif /* RT_USING_SERIAL */ +#endif /* RT_USING_SERIAL_V2 */ diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.h b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h index 34ca294f74..eeb6005c91 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.h +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,393 @@ #ifndef DRV_UART_V2_H #define DRV_UART_V2_H +#include "rtconfig.h" + +/* ============================================================================ + * UART IRQ Priority Configuration Macros + * ============================================================================ + * + * These macros handle the configuration of interrupt priorities for each UART controller. + * If a specific priority is defined in the board configuration (BSP_UARTx_IRQ_PRIORITY), + * it will be used; otherwise, a default priority of 1 is applied. + * + * The macros follow a consistent pattern: + * - Check if BSP_UARTx_IRQ_PRIORITY is defined + * - Use the configured value if available + * - Fall back to default priority of 1 + * + * Usage: UART_IRQ_PRI_VAL(n) where n is the UART number (0-15) + */ + +#ifdef BSP_UART0_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_0 BSP_UART0_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_0 1 +#endif + +#ifdef BSP_UART1_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_1 BSP_UART1_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_1 1 +#endif + +#ifdef BSP_UART2_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_2 BSP_UART2_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_2 1 +#endif + +#ifdef BSP_UART3_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_3 BSP_UART3_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_3 1 +#endif + +#ifdef BSP_UART4_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_4 BSP_UART4_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_4 1 +#endif + +#ifdef BSP_UART5_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_5 BSP_UART5_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_5 1 +#endif + +#ifdef BSP_UART6_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_6 BSP_UART6_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_6 1 +#endif + +#ifdef BSP_UART7_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_7 BSP_UART7_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_7 1 +#endif + +#ifdef BSP_UART8_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_8 BSP_UART8_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_8 1 +#endif + +#ifdef BSP_UART9_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_9 BSP_UART9_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_9 1 +#endif + +#ifdef BSP_UART10_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_10 BSP_UART10_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_10 1 +#endif + +#ifdef BSP_UART11_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_11 BSP_UART11_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_11 1 +#endif + +#ifdef BSP_UART12_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_12 BSP_UART12_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_12 1 +#endif + +#ifdef BSP_UART13_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_13 BSP_UART13_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_13 1 +#endif + +#ifdef BSP_UART14_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_14 BSP_UART14_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_14 1 +#endif + +#ifdef BSP_UART15_IRQ_PRIORITY +#define UART_IRQ_PRI_VAL_15 BSP_UART15_IRQ_PRIORITY +#else +#define UART_IRQ_PRI_VAL_15 1 +#endif + +#define UART_IRQ_PRI_VAL(n) UART_IRQ_PRI_VAL_##n + +/* ============================================================================ +* UART DMA Configuration Macros +* ============================================================================ +* +* These macros handle the configuration of DMA usage for each UART controller. +* They check if DMA is enabled for TX and/or RX operations and set appropriate +* boolean values for the UART device structure. +* +* Configuration options: +* - BSP_UARTx_RX_USING_DMA: Enable DMA for receive operations +* - BSP_UARTx_TX_USING_DMA: Enable DMA for transmit operations +* +* The macros follow a consistent pattern: +* - Check if BSP_UARTx_RX_USING_DMA is defined +* - Set to true if defined, false otherwise +* - Similar pattern for TX DMA configuration +* +* Usage: +* - UART_RX_USING_DMA_VAL(n) for RX DMA configuration +* - UART_TX_USING_DMA_VAL(n) for TX DMA configuration +* where n is the UART number (0-15) +*/ +#ifdef BSP_UART0_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_0 true +#else +#define UART_RX_USING_DMA_VAL_0 false +#endif + +#ifdef BSP_UART1_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_1 true +#else +#define UART_RX_USING_DMA_VAL_1 false +#endif + +#ifdef BSP_UART2_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_2 true +#else +#define UART_RX_USING_DMA_VAL_2 false +#endif + +#ifdef BSP_UART3_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_3 true +#else +#define UART_RX_USING_DMA_VAL_3 false +#endif + +#ifdef BSP_UART4_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_4 true +#else +#define UART_RX_USING_DMA_VAL_4 false +#endif + +#ifdef BSP_UART5_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_5 true +#else +#define UART_RX_USING_DMA_VAL_5 false +#endif + +#ifdef BSP_UART6_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_6 true +#else +#define UART_RX_USING_DMA_VAL_6 false +#endif + +#ifdef BSP_UART7_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_7 true +#else +#define UART_RX_USING_DMA_VAL_7 false +#endif + +#ifdef BSP_UART8_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_8 true +#else +#define UART_RX_USING_DMA_VAL_8 false +#endif + +#ifdef BSP_UART9_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_9 true +#else +#define UART_RX_USING_DMA_VAL_9 false +#endif + +#ifdef BSP_UART10_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_10 true +#else +#define UART_RX_USING_DMA_VAL_10 false +#endif + +#ifdef BSP_UART11_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_11 true +#else +#define UART_RX_USING_DMA_VAL_11 false +#endif + +#ifdef BSP_UART12_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_12 true +#else +#define UART_RX_USING_DMA_VAL_12 false +#endif + +#ifdef BSP_UART13_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_13 true +#else +#define UART_RX_USING_DMA_VAL_13 false +#endif + +#ifdef BSP_UART14_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_14 true +#else +#define UART_RX_USING_DMA_VAL_14 false +#endif + +#ifdef BSP_UART15_RX_USING_DMA +#define UART_RX_USING_DMA_VAL_15 true +#else +#define UART_RX_USING_DMA_VAL_15 false +#endif + +#define UART_RX_USING_DMA_VAL(n) UART_RX_USING_DMA_VAL_##n + +#ifdef BSP_UART0_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_0 true +#else +#define UART_TX_USING_DMA_VAL_0 false +#endif + +#ifdef BSP_UART1_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_1 true +#else +#define UART_TX_USING_DMA_VAL_1 false +#endif + +#ifdef BSP_UART2_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_2 true +#else +#define UART_TX_USING_DMA_VAL_2 false +#endif + +#ifdef BSP_UART3_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_3 true +#else +#define UART_TX_USING_DMA_VAL_3 false +#endif + +#ifdef BSP_UART4_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_4 true +#else +#define UART_TX_USING_DMA_VAL_4 false +#endif + +#ifdef BSP_UART5_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_5 true +#else +#define UART_TX_USING_DMA_VAL_5 false +#endif + +#ifdef BSP_UART6_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_6 true +#else +#define UART_TX_USING_DMA_VAL_6 false +#endif + +#ifdef BSP_UART7_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_7 true +#else +#define UART_TX_USING_DMA_VAL_7 false +#endif + +#ifdef BSP_UART8_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_8 true +#else +#define UART_TX_USING_DMA_VAL_8 false +#endif + +#ifdef BSP_UART9_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_9 true +#else +#define UART_TX_USING_DMA_VAL_9 false +#endif + +#ifdef BSP_UART10_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_10 true +#else +#define UART_TX_USING_DMA_VAL_10 false +#endif + +#ifdef BSP_UART11_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_11 true +#else +#define UART_TX_USING_DMA_VAL_11 false +#endif + +#ifdef BSP_UART12_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_12 true +#else +#define UART_TX_USING_DMA_VAL_12 false +#endif + +#ifdef BSP_UART13_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_13 true +#else +#define UART_TX_USING_DMA_VAL_13 false +#endif + +#ifdef BSP_UART14_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_14 true +#else +#define UART_TX_USING_DMA_VAL_14 false +#endif + +#ifdef BSP_UART15_TX_USING_DMA +#define UART_TX_USING_DMA_VAL_15 true +#else +#define UART_TX_USING_DMA_VAL_15 false +#endif + +#define UART_TX_USING_DMA_VAL(n) UART_TX_USING_DMA_VAL_##n + +#ifndef BSP_UART0_DMA_PINGPONG_BUFSIZE +#define BSP_UART0_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART1_DMA_PINGPONG_BUFSIZE +#define BSP_UART1_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART2_DMA_PINGPONG_BUFSIZE +#define BSP_UART2_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART3_DMA_PINGPONG_BUFSIZE +#define BSP_UART3_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART4_DMA_PINGPONG_BUFSIZE +#define BSP_UART4_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART5_DMA_PINGPONG_BUFSIZE +#define BSP_UART5_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART6_DMA_PINGPONG_BUFSIZE +#define BSP_UART6_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART7_DMA_PINGPONG_BUFSIZE +#define BSP_UART7_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART8_DMA_PINGPONG_BUFSIZE +#define BSP_UART8_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART9_DMA_PINGPONG_BUFSIZE +#define BSP_UART9_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART10_DMA_PINGPONG_BUFSIZE +#define BSP_UART10_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART11_DMA_PINGPONG_BUFSIZE +#define BSP_UART11_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART12_DMA_PINGPONG_BUFSIZE +#define BSP_UART12_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART13_DMA_PINGPONG_BUFSIZE +#define BSP_UART13_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART14_DMA_PINGPONG_BUFSIZE +#define BSP_UART14_DMA_PINGPONG_BUFSIZE 0 +#endif +#ifndef BSP_UART15_DMA_PINGPONG_BUFSIZE +#define BSP_UART15_DMA_PINGPONG_BUFSIZE 0 +#endif + +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_HT_FLAG 0x01 +#define UART_RX_DMA_IT_TC_FLAG 0x02 + int rt_hw_uart_init(void); diff --git a/bsp/hpmicro/libraries/drivers/drv_usb.c b/bsp/hpmicro/libraries/drivers/drv_usb.c index 0d460417c4..a3c636a310 100644 --- a/bsp/hpmicro/libraries/drivers/drv_usb.c +++ b/bsp/hpmicro/libraries/drivers/drv_usb.c @@ -83,6 +83,10 @@ rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RT_DEVICE_CTRL_BLK_GETGEOME: + if (args == RT_NULL) + { + return -RT_EINVAL; + } struct rt_device_blk_geometry *geometry = (struct rt_device_blk_geometry *)args; geometry->sector_count = tuh_msc_get_block_count(usb_dev_addr, LUN_USB); geometry->bytes_per_sector = tuh_msc_get_block_size(usb_dev_addr, LUN_USB); @@ -93,11 +97,11 @@ rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args) break; default: - ret = RT_EINVAL; + ret = -RT_EINVAL; break; } - return RT_EOK; + return ret; } int rt_hw_usb_init(void) @@ -112,6 +116,16 @@ int rt_hw_usb_init(void) LOG_E("rt device %s failed, status=%d\n", "usb", err); return err; } + +#ifdef HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK + /* Register usb device to irq table */ + extern void hpm_isr_usb0(void); + rt_hw_interrupt_install(IRQn_USB0, (rt_isr_handler_t)hpm_isr_usb0, HPM_USB0, "usb0"); +#ifdef HPM_USB1_BASE + extern void hpm_isr_usb1(void); + rt_hw_interrupt_install(IRQn_USB1, (rt_isr_handler_t)hpm_isr_usb1, HPM_USB1, "usb1"); +#endif +#endif /* HPM_USING_RTTHREAD_INTERRUPT_FRAMEWORK */ return err; } diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c index ae1bae48e1..2c07294dbe 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -1,32 +1,58 @@ /* - * Copyright (c) 2021 - 2022 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * + * Change Logs: + * Date Author Notes + * 2022-05-08 HPMicro the first version + * 2025-09-01 HPMicro Revised the code, reduced repetitive codes, removed interrupt related codes */ -#include <rthw.h> -#include <rtdevice.h> -#include <rtdbg.h> +#include "rtconfig.h" + +#ifdef BSP_USING_WDG #include "board.h" #include "drv_wdt.h" #include "hpm_wdg_drv.h" +#include <rtdbg.h> +#include <rtdevice.h> +#include <rthw.h> #include "hpm_sysctl_drv.h" +/* Macros to reduce repetitive code */ +#define WDG_DECLARE(n) rt_watchdog_t wdog##n -#ifdef BSP_USING_WDG +#define WDG_DEVICE_INIT(n) \ + { \ + .wdog_base = HPM_WDG## n, \ + .device_name = "wdt" #n, \ + .clock_name = clock_watchdog## n, \ + .wdog = &wdog## n, \ + .wdog_ctrl = \ + { \ + .reset_interval = reset_interval_clock_period_mult_16k, \ + .interrupt_interval = interrupt_interval_clock_period_multi_8k, \ + .reset_enable = true, \ + .interrupt_enable = false, \ + .clksrc = wdg_clksrc_extclk, \ + .wdg_enable = false, \ + }, \ + }, +#define WDG_CTX(wdt) \ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)(wdt)->parent.user_data; \ + WDG_Type *base = hpm_wdog->wdog_base typedef struct hpm_wdog { WDG_Type *wdog_base; char *device_name; clock_name_t clock_name; - uint32_t irq_num; rt_watchdog_t *wdog; wdg_control_t wdog_ctrl; -}hpm_wdog_t; +} hpm_wdog_t; static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt); static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag); @@ -34,126 +60,50 @@ static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt); static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt); static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); -static void hpm_wdog_isr(rt_watchdog_t *wdt); - #if defined(BSP_USING_WDG0) -rt_watchdog_t wdog0; -SDK_DECLARE_EXT_ISR_M(IRQn_WDG0, wdog0_isr) -void wdog0_isr(void) -{ - hpm_wdog_isr(&wdog0); -} +WDG_DECLARE(0); #endif #if defined(BSP_USING_WDG1) -rt_watchdog_t wdog1; -SDK_DECLARE_EXT_ISR_M(IRQn_WDG1, wdog1_isr) -void wdog1_isr(void) -{ - hpm_wdog_isr(&wdog1); -} +WDG_DECLARE(1); #endif #if defined(BSP_USING_WDG2) -rt_watchdog_t wdog2; -SDK_DECLARE_EXT_ISR_M(IRQn_WDG2, wdog2_isr) -void wdog2_isr(void) -{ - hpm_wdog_isr(&wdog2); -} +WDG_DECLARE(2); #endif #if defined(BSP_USING_WDG3) -rt_watchdog_t wdog3; -SDK_DECLARE_EXT_ISR_M(IRQn_WDG3, wdog3_isr) -void wdog3_isr(void) -{ - hpm_wdog_isr(&wdog3); -} +WDG_DECLARE(3); #endif -static hpm_wdog_t wdogs[] = { +static hpm_wdog_t wdogs[] = +{ #ifdef BSP_USING_WDG0 - { - .wdog_base = HPM_WDG0, - .device_name = "wdt0", - .clock_name = clock_watchdog0, - .irq_num = IRQn_WDG0, - .wdog = &wdog0, - .wdog_ctrl = { - .reset_interval = reset_interval_clock_period_mult_16k, - .interrupt_interval = interrupt_interval_clock_period_multi_8k, - .reset_enable = true, - .interrupt_enable = false, - .clksrc = wdg_clksrc_extclk, - .wdg_enable = false, - }, - }, + WDG_DEVICE_INIT(0) #endif #ifdef BSP_USING_WDG1 - { - .wdog_base = HPM_WDG1, - .device_name = "wdt1", - .clock_name = clock_watchdog1, - .irq_num = IRQn_WDG1, - .wdog = &wdog1, - .wdog_ctrl = { - .reset_interval = reset_interval_clock_period_mult_16k, - .interrupt_interval = interrupt_interval_clock_period_multi_8k, - .reset_enable = true, - .interrupt_enable = false, - .clksrc = wdg_clksrc_extclk, - .wdg_enable = false, - }, - }, + WDG_DEVICE_INIT(1) #endif #ifdef BSP_USING_WDG2 - { - .wdog_base = HPM_WDG2, - .device_name = "wdt2", - .clock_name = clock_watchdog2, - .irq_num = IRQn_WDG2, - .wdog = &wdog2, - .wdog_ctrl = { - .reset_interval = reset_interval_clock_period_mult_16k, - .interrupt_interval = interrupt_interval_clock_period_multi_8k, - .reset_enable = true, - .interrupt_enable = false, - .clksrc = wdg_clksrc_extclk, - .wdg_enable = false, - }, - }, + WDG_DEVICE_INIT(2) #endif #ifdef BSP_USING_WDG3 - { - .wdog_base = HPM_WDG3, - .device_name = "wdt3", - .clock_name = clock_watchdog3, - .irq_num = IRQn_WDG3, - .wdog = &wdog3, - .wdog_ctrl = { - .reset_interval = reset_interval_clock_period_mult_16k, - .interrupt_interval = interrupt_interval_clock_period_multi_8k, - .reset_enable = true, - .interrupt_enable = false, - .clksrc = wdg_clksrc_extclk, - .wdg_enable = false, - }, - }, + WDG_DEVICE_INIT(3) #endif }; -static struct rt_watchdog_ops hpm_wdog_ops = { +static struct rt_watchdog_ops hpm_wdog_ops = +{ .init = hpm_wdog_init, .control = hpm_wdog_control, }; static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) { - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; clock_add_to_group(hpm_wdog->clock_name, BOARD_RUNNING_CORE & 0x1); @@ -165,7 +115,7 @@ static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) { - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; rt_enter_critical(); @@ -176,7 +126,7 @@ static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) { - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; rt_enter_critical(); @@ -188,7 +138,7 @@ static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt) { - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; rt_enter_critical(); @@ -202,7 +152,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) { rt_err_t ret = RT_EOK; - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; wdg_control_t *wdog_ctrl = &hpm_wdog->wdog_ctrl; @@ -210,12 +160,19 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) switch (cmd) { case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + if (args == RT_NULL) + { + return -RT_EINVAL; + } temp = wdg_get_total_reset_interval_in_us(base, WDG_EXT_CLK_FREQ); temp /= 1000000UL; /* Convert to seconds */ *(uint32_t *)args = temp; break; case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: - RT_ASSERT(*(uint32_t *)args != 0); + if ((args == RT_NULL) || (*(uint32_t *)args == 0U)) + { + return -RT_EINVAL; + } temp = *(uint32_t *)args; temp *= 1000000U; /* Convert to microseconds */ wdog_ctrl->interrupt_interval = wdg_convert_interrupt_interval_from_us(WDG_EXT_CLK_FREQ, temp); @@ -230,13 +187,17 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) hpm_wdog_refresh(wdt); break; case RT_DEVICE_CTRL_WDT_START: - hpm_wdog_open(wdt, *(uint16_t*)args); + if (args == RT_NULL) + { + return -RT_EINVAL; + } + hpm_wdog_open(wdt, *(uint16_t *)args); break; case RT_DEVICE_CTRL_WDT_STOP: hpm_wdog_close(wdt); break; default: - ret = RT_EINVAL; + ret = -RT_EINVAL; break; } @@ -245,12 +206,13 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) void hpm_wdog_isr(rt_watchdog_t *wdt) { - hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + hpm_wdog_t *hpm_wdog = (hpm_wdog_t *)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; uint32_t status = wdg_get_status(base); - if (IS_HPM_BITMASK_SET(status, WDG_ST_INTEXPIRED_MASK)) { + if (IS_HPM_BITMASK_SET(status, WDG_ST_INTEXPIRED_MASK)) + { wdg_clear_status(base, WDG_ST_INTEXPIRED_MASK); } } @@ -259,7 +221,6 @@ int rt_hw_wdt_init(void) { rt_err_t err = RT_EOK; -#if defined(BSP_USING_WDG) for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++) { wdogs[i].wdog->ops = &hpm_wdog_ops; @@ -270,9 +231,8 @@ int rt_hw_wdt_init(void) LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err); } } -#endif return err; } INIT_BOARD_EXPORT(rt_hw_wdt_init); -#endif /* RT_USING_WDT */
\ No newline at end of file +#endif /* RT_USING_WDT */ diff --git a/bsp/hpmicro/libraries/misc/SConscript b/bsp/hpmicro/libraries/misc/SConscript new file mode 100644 index 0000000000..bb673e4f18 --- /dev/null +++ b/bsp/hpmicro/libraries/misc/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs')
\ No newline at end of file diff --git a/bsp/hpmicro/libraries/misc/lwip_ptp/SConscript b/bsp/hpmicro/libraries/misc/lwip_ptp/SConscript new file mode 100644 index 0000000000..812c8f3728 --- /dev/null +++ b/bsp/hpmicro/libraries/misc/lwip_ptp/SConscript @@ -0,0 +1,7 @@ +from building import * + +cwd = GetCurrentDir() + +group = DefineGroup('lwip_ptp', [], depend=['BSP_USING_ETH'], CPPPATH=[cwd]) + +Return('group') diff --git a/bsp/hpmicro/libraries/misc/lwip_ptp/lwip_ptp_tx_ts.h b/bsp/hpmicro/libraries/misc/lwip_ptp/lwip_ptp_tx_ts.h new file mode 100644 index 0000000000..73bc530111 --- /dev/null +++ b/bsp/hpmicro/libraries/misc/lwip_ptp/lwip_ptp_tx_ts.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2026 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef LWIP_PTP_TX_TS_H +#define LWIP_PTP_TX_TS_H + +#include <stdbool.h> +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/prot/ethernet.h" +#include "lwip/prot/ip.h" +#include "lwip/prot/ip4.h" +#include "lwip/prot/udp.h" + +/** + * @brief True if this Ethernet frame should use ENET TX descriptor TTSE and HW timestamp + * PTPd sends messages that need precise egress time on UDP event port 319 only. + * General port 320 (Announce, Follow_Up, Delay_Resp, etc.) does not use TX HW stamp. + */ +static inline bool lwip_ptp_frame_needs_tx_hw_timestamp(const struct pbuf *p) +{ + u8_t hdr[SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR + IP_HLEN + sizeof(struct udp_hdr)]; + u16_t ethertype; + u16_t ip_off; + const struct ip_hdr *iph; + u16_t ip_len; + const struct udp_hdr *udph; + + if (p == NULL || p->tot_len < (s16_t)(SIZEOF_ETH_HDR + IP_HLEN + UDP_HLEN)) { + return false; + } + if (pbuf_copy_partial(p, hdr, (u16_t)sizeof(hdr), 0) != (u16_t)sizeof(hdr)) { + return false; + } + ethertype = lwip_ntohs(*(u16_t *)(hdr + 12U)); + ip_off = SIZEOF_ETH_HDR; + if (ethertype == ETHTYPE_VLAN) { + if (p->tot_len < (s16_t)(SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR + IP_HLEN + UDP_HLEN)) { + return false; + } + ethertype = lwip_ntohs(*(u16_t *)(hdr + (SIZEOF_ETH_HDR + 2U))); + ip_off = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR; + } + if (ethertype != ETHTYPE_IP) { + return false; + } + iph = (const struct ip_hdr *)(hdr + ip_off); + if (IPH_HL(iph) != 5) { + return false; + } + if (IPH_PROTO(iph) != IP_PROTO_UDP) { + return false; + } + ip_len = IP_HLEN; + if ((u32_t)ip_off + (u32_t)ip_len + UDP_HLEN > sizeof(hdr)) { + return false; + } + udph = (const struct udp_hdr *)(hdr + ip_off + ip_len); + return udph->dest == PP_HTONS(319); +} + +#endif /* LWIP_PTP_TX_TS_H */ diff --git a/bsp/hpmicro/tools/sdk_dist.py b/bsp/hpmicro/tools/sdk_dist.py index 3d7fd1aba4..7169ecc108 100644 --- a/bsp/hpmicro/tools/sdk_dist.py +++ b/bsp/hpmicro/tools/sdk_dist.py @@ -1,8 +1,4 @@ import os -import sys -import shutil -cwd_path = os.getcwd() -sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) def update_rtt_root_path(path): if not os.path.isfile(path): @@ -38,7 +34,6 @@ def update_dist_project_paths(dist_dir): # BSP dist function def dist_do_building(BSP_ROOT, dist_dir): from mkdist import bsp_copy_files - import rtconfig library_dir = os.path.join(dist_dir, 'libraries') |
