Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

8 files changed, 262 insertions, 262 deletions

diff --git a/bsp/asm9260t/applications/application.c b/bsp/asm9260t/applications/application.c
index 49c016521d..d60546ca76 100644
--- a/bsp/asm9260t/applications/application.c
+++ b/bsp/asm9260t/applications/application.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		 first version
+ * Date           Author        Notes
+ * 2011-01-13     weety      first version
  * 2015-04-27     ArdaFu     Port bsp from at91sam9260 to asm9260t
  */
 
diff --git a/bsp/asm9260t/drivers/usart.c b/bsp/asm9260t/drivers/usart.c
index ea5dd1a830..3a17f97b38 100644
--- a/bsp/asm9260t/drivers/usart.c
+++ b/bsp/asm9260t/drivers/usart.c
@@ -58,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
     uart = (asm_uart_t *)serial->parent.user_data;
-    
+
     Hw_UartDisable(uart->port);
 
     Hw_UartReset(uart->port);
-    
-    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, 
+
+    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits,
                   cfg->stop_bits, cfg->parity);
 
     Hw_UartEnable(uart->port);
diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c
index fa5e1bee9e..8361a59589 100644
--- a/bsp/asm9260t/platform/gpio.c
+++ b/bsp/asm9260t/platform/gpio.c
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 
diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h
index 6f42bd6b4b..fba92d1f2c 100644
--- a/bsp/asm9260t/platform/interrupt.h
+++ b/bsp/asm9260t/platform/interrupt.h
@@ -15,69 +15,69 @@
 
 
 // IRQ Source
-#define INT_ARM_COMMRX                    0 
-#define INT_ARM_COMMTX                    1 
-#define INT_RTC                           2 
-#define INT_GPIO0                         3 
-#define INT_GPIO1                         4 
-#define INT_GPIO2                         5 
-#define INT_GPIO3                         6 
-#define INT_GPIO4_IIS1                    7 
-#define INT_USB0                          8 
-#define INT_USB1                          9 
-#define INT_USB0_DMA                      10  
-#define INT_USB1_DMA                      11  
-#define INT_MAC                           12  
-#define INT_MAC_PMT                       13  
-#define INT_NAND                          14  
-#define INT_UART0                         15  
-#define INT_UART1                         16  
-#define INT_UART2                         17  
-#define INT_UART3                         18  
-#define INT_UART4                         19  
-#define INT_UART5                         20  
-#define INT_UART6                         21  
-#define INT_UART7                         22  
-#define INT_UART8                         23  
-#define INT_UART9                         24  
-#define INT_I2S0                          25  
-#define INT_I2C0                          26  
-#define INT_I2C1                          27  
-#define INT_CAMIF                         28  
-#define INT_TIMER0                        29  
-#define INT_TIMER1                        30  
-#define INT_TIMER2                        31  
-#define INT_TIMER3                        32  
-#define INT_ADC0                          33  
-#define INT_DAC0                          34  
-#define INT_USB0_RESUME_HOSTDISCONNECT    35    
-#define INT_USB0_VBUSVALID                36    
-#define INT_USB1_RESUME_HOSTDISCONNECT    37    
-#define INT_USB1_VBUSVALID                38    
-#define INT_DMA0_CH0                      39  
-#define INT_DMA0_CH1                      40  
-#define INT_DMA0_CH2                      41  
-#define INT_DMA0_CH3                      42  
-#define INT_DMA0_CH4                      43  
-#define INT_DMA0_CH5                      44  
-#define INT_DMA0_CH6                      45  
-#define INT_DMA0_CH7                      46  
-#define INT_DMA1_CH0                      47  
-#define INT_DMA1_CH1                      48  
-#define INT_DMA1_CH2                      49  
-#define INT_DMA1_CH3                      50  
-#define INT_DMA1_CH4                      51  
-#define INT_DMA1_CH5                      52  
-#define INT_DMA1_CH6                      53  
-#define INT_DMA1_CH7                      54  
-#define INT_WATCHDOG                      55  
-#define INT_CAN0                          56  
-#define INT_CAN1                          57  
-#define INT_QEI                           58  
-#define INT_MCPWM                         59  
-#define INT_SPI0                          60  
-#define INT_SPI1                          61  
-#define INT_QUADSPI0                      62  
+#define INT_ARM_COMMRX                    0
+#define INT_ARM_COMMTX                    1
+#define INT_RTC                           2
+#define INT_GPIO0                         3
+#define INT_GPIO1                         4
+#define INT_GPIO2                         5
+#define INT_GPIO3                         6
+#define INT_GPIO4_IIS1                    7
+#define INT_USB0                          8
+#define INT_USB1                          9
+#define INT_USB0_DMA                      10
+#define INT_USB1_DMA                      11
+#define INT_MAC                           12
+#define INT_MAC_PMT                       13
+#define INT_NAND                          14
+#define INT_UART0                         15
+#define INT_UART1                         16
+#define INT_UART2                         17
+#define INT_UART3                         18
+#define INT_UART4                         19
+#define INT_UART5                         20
+#define INT_UART6                         21
+#define INT_UART7                         22
+#define INT_UART8                         23
+#define INT_UART9                         24
+#define INT_I2S0                          25
+#define INT_I2C0                          26
+#define INT_I2C1                          27
+#define INT_CAMIF                         28
+#define INT_TIMER0                        29
+#define INT_TIMER1                        30
+#define INT_TIMER2                        31
+#define INT_TIMER3                        32
+#define INT_ADC0                          33
+#define INT_DAC0                          34
+#define INT_USB0_RESUME_HOSTDISCONNECT    35
+#define INT_USB0_VBUSVALID                36
+#define INT_USB1_RESUME_HOSTDISCONNECT    37
+#define INT_USB1_VBUSVALID                38
+#define INT_DMA0_CH0                      39
+#define INT_DMA0_CH1                      40
+#define INT_DMA0_CH2                      41
+#define INT_DMA0_CH3                      42
+#define INT_DMA0_CH4                      43
+#define INT_DMA0_CH5                      44
+#define INT_DMA0_CH6                      45
+#define INT_DMA0_CH7                      46
+#define INT_DMA1_CH0                      47
+#define INT_DMA1_CH1                      48
+#define INT_DMA1_CH2                      49
+#define INT_DMA1_CH3                      50
+#define INT_DMA1_CH4                      51
+#define INT_DMA1_CH5                      52
+#define INT_DMA1_CH6                      53
+#define INT_DMA1_CH7                      54
+#define INT_WATCHDOG                      55
+#define INT_CAN0                          56
+#define INT_CAN1                          57
+#define INT_QEI                           58
+#define INT_MCPWM                         59
+#define INT_SPI0                          60
+#define INT_SPI1                          61
+#define INT_QUADSPI0                      62
 #define INT_SSP0                          63
 
 #endif
diff --git a/bsp/asm9260t/platform/rt_low_level_init.h b/bsp/asm9260t/platform/rt_low_level_init.h
index 93a1fade4c..c79adf5284 100644
--- a/bsp/asm9260t/platform/rt_low_level_init.h
+++ b/bsp/asm9260t/platform/rt_low_level_init.h
@@ -9,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096
diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c
index 32dbf740d0..3a3340f48d 100644
--- a/bsp/asm9260t/platform/system_clock.c
+++ b/bsp/asm9260t/platform/system_clock.c
@@ -14,269 +14,269 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk uhpck = {
-	"uhpck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "uhpck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk pllb = {
-	"pllb",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "pllb",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk udpck = {
-	"udpck",
-	0,
-	&pllb,
-	{RT_NULL, RT_NULL},
+    "udpck",
+    0,
+    &pllb,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	// four primary clocks 
-	&clk32k,
-	&main_clk,
-	&plla,
+    // four primary clocks
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	// MCK 
-	&mck
+    // MCK
+    &mck
 };
 
 // clocks cannot be de-registered no refcounting necessary
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
+    struct clk *clk;
+    rt_list_t *list;
 
-	return RT_NULL;
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	rate;
+    rt_uint32_t rate;
 
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	unsigned mul, div;
+    unsigned mul, div;
 
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
+    div = reg & 0xff;
+    mul = (reg >> 16) & 0x7ff;
+    if (div && mul) {
+        freq /= div;
+        freq *= mul + 1;
+    } else
+        freq = 0;
 
-	return freq;
+    return freq;
 }
 
 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 {
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+    unsigned i, div = 0, mul = 0, diff = 1 << 30;
+    unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 
-	//PLL output max 240 MHz (or 180 MHz per errata)
-	if (out_freq > 240000000)
-		goto fail;
+    //PLL output max 240 MHz (or 180 MHz per errata)
+    if (out_freq > 240000000)
+        goto fail;
 
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
+    for (i = 1; i < 256; i++) {
+        int diff1;
+        unsigned input, mul1;
 
-		//
-		// PLL input between 1MHz and 32MHz per spec, but lower
-		// frequences seem necessary in some cases so allow 100K.
-		// Warning: some newer products need 2MHz min.
-		//
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
+        //
+        // PLL input between 1MHz and 32MHz per spec, but lower
+        // frequences seem necessary in some cases so allow 100K.
+        // Warning: some newer products need 2MHz min.
+        //
+        input = main_freq / i;
+        if (input < 100000)
+            continue;
+        if (input > 32000000)
+            continue;
 
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
+        mul1 = out_freq / input;
+        if (mul1 > 2048)
+            continue;
+        if (mul1 < 2)
+            goto fail;
 
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
+        diff1 = out_freq - input * mul1;
+        if (diff1 < 0)
+            diff1 = -diff1;
+        if (diff > diff1) {
+            diff = diff1;
+            div = i;
+            mul = mul1;
+            if (diff == 0)
+                break;
+        }
+    }
+    if (i == 256 && diff > (out_freq >> 5))
+        goto fail;
+    return ret | ((mul - 1) << 16) | div;
 fail:
-	return 0;
+    return 0;
 }
 
 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	if (pll == &pllb && (reg & AT91_PMC_USB96M))
-		return freq / 2;
-	else
-		return freq;
+    if (pll == &pllb && (reg & AT91_PMC_USB96M))
+        return freq / 2;
+    else
+        return freq;
 }
 
 
 // PLLB generated USB full speed clock init
 static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
 {
-	rt_uint32_t at91_pllb_usb_init;
-	//
-	// USB clock init:  choose 48 MHz PLLB value,
-	// disable 48MHz clock during usb peripheral suspend.
-	//
-	// REVISIT:  assumes MCK doesn't derive from PLLB!
-	//
-	uhpck.parent = &pllb;
+    rt_uint32_t at91_pllb_usb_init;
+    //
+    // USB clock init:  choose 48 MHz PLLB value,
+    // disable 48MHz clock during usb peripheral suspend.
+    //
+    // REVISIT:  assumes MCK doesn't derive from PLLB!
+    //
+    uhpck.parent = &pllb;
+
+    at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+    pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-	
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
+    at91_sys_write(AT91_CKGR_PLLBR, 0);
 
-	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91_PMC_CSS_SLOW:
-			return &clk32k;
-		case AT91_PMC_CSS_MAIN:
-			return &main_clk;
-		case AT91_PMC_CSS_PLLA:
-			return &plla;
-		case AT91_PMC_CSS_PLLB:
-			return &pllb;
-	}
+    switch (css) {
+        case AT91_PMC_CSS_SLOW:
+            return &clk32k;
+        case AT91_PMC_CSS_MAIN:
+            return &main_clk;
+        case AT91_PMC_CSS_PLLA:
+            return &plla;
+        case AT91_PMC_CSS_PLLB:
+            return &pllb;
+    }
 
-	return RT_NULL;
+    return RT_NULL;
 }
 
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr;
-	int i;
-	int pll_overclock = false;
+    unsigned tmp, freq, mckr;
+    int i;
+    int pll_overclock = false;
+
+    //
+    // When the bootloader initialized the main oscillator correctly,
+    // there's no problem using the cycle counter.  But if it didn't,
+    // or when using oscillator bypass mode, we must be told the speed
+     // of the main clock.
+    //
+    if (!main_clock) {
+        do {
+            tmp = at91_sys_read(AT91_CKGR_MCFR);
+        } while (!(tmp & AT91_PMC_MAINRDY));
+        main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
 
-	//
-	// When the bootloader initialized the main oscillator correctly,
-	// there's no problem using the cycle counter.  But if it didn't,
-	// or when using oscillator bypass mode, we must be told the speed
-	 // of the main clock.
-	//
-	if (!main_clock) {
-		do {
-			tmp = at91_sys_read(AT91_CKGR_MCFR);
-		} while (!(tmp & AT91_PMC_MAINRDY));
-		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
+    // report if PLLA is more than mildly overclocked
+    plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+    if (plla.rate_hz > 209000000)
+        pll_overclock = true;
+    if (pll_overclock)
+        ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
-	// report if PLLA is more than mildly overclocked 
-	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-	if (plla.rate_hz > 209000000)
-		pll_overclock = true;
-	if (pll_overclock)
-		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+    at91_pllb_usbfs_clock_init(main_clock);
 
-	at91_pllb_usbfs_clock_init(main_clock);
+    //
+     // MCK and CPU derive from one of those primary clocks.
+     // For now, assume this parentage won't change.
+     //
+    mckr = at91_sys_read(AT91_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));               // prescale
 
-	//
-	 // MCK and CPU derive from one of those primary clocks.
-	 // For now, assume this parentage won't change.
-	 //
-	mckr = at91_sys_read(AT91_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				// prescale 
-	
-	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv 
+    mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv
 
-	// Register the PMC's standard clocks 
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+    // Register the PMC's standard clocks
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
 
-	rt_list_insert_after(&clocks, &pllb.node);
-	rt_list_insert_after(&clocks, &uhpck.node);
-	rt_list_insert_after(&clocks, &udpck.node);
+    rt_list_insert_after(&clocks, &pllb.node);
+    rt_list_insert_after(&clocks, &uhpck.node);
+    rt_list_insert_after(&clocks, &udpck.node);
 
-	// MCK and CPU clock are "always on" 
-	//clk_enable(&mck);
+    // MCK and CPU clock are "always on"
+    //clk_enable(&mck);
 
-	//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-	//	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-	//	(unsigned) main_clock / 1000000,
-	//	((unsigned) main_clock % 1000000) / 1000); //cause blocked
+    //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+    //  freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+    //  (unsigned) main_clock / 1000000,
+    //  ((unsigned) main_clock % 1000000) / 1000); //cause blocked
 
-	return 0;
+    return 0;
 }
 */
 
@@ -284,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock)
 
 void rt_hw_clock_init(void)
 {
-	//at91_clock_init(18432000);
+    //at91_clock_init(18432000);
 }
 
diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c
index 9dc2cca560..08613200db 100644
--- a/bsp/asm9260t/platform/uart.c
+++ b/bsp/asm9260t/platform/uart.c
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 #include "uart.h"
diff --git a/bsp/asm9260t/platform/uart.h b/bsp/asm9260t/platform/uart.h
index f6e0f30fc6..b938483882 100644
--- a/bsp/asm9260t/platform/uart.h
+++ b/bsp/asm9260t/platform/uart.h
@@ -36,16 +36,16 @@ typedef struct
     volatile rt_uint32_t ISO7816STATUS[4];
 } HW_USART_TypeDef;
 
-#define USART0	((HW_USART_TypeDef *)UART0_BASE)
-#define USART1	((HW_USART_TypeDef *)UART1_BASE)
-#define USART2	((HW_USART_TypeDef *)UART2_BASE)
-#define USART3	((HW_USART_TypeDef *)UART3_BASE)
-#define USART4	((HW_USART_TypeDef *)UART4_BASE)
-#define USART5	((HW_USART_TypeDef *)UART5_BASE)
-#define USART6	((HW_USART_TypeDef *)UART6_BASE)
-#define USART7	((HW_USART_TypeDef *)UART7_BASE)
-#define USART8	((HW_USART_TypeDef *)UART8_BASE)
-#define USART9	((HW_USART_TypeDef *)UART9_BASE)
+#define USART0  ((HW_USART_TypeDef *)UART0_BASE)
+#define USART1  ((HW_USART_TypeDef *)UART1_BASE)
+#define USART2  ((HW_USART_TypeDef *)UART2_BASE)
+#define USART3  ((HW_USART_TypeDef *)UART3_BASE)
+#define USART4  ((HW_USART_TypeDef *)UART4_BASE)
+#define USART5  ((HW_USART_TypeDef *)UART5_BASE)
+#define USART6  ((HW_USART_TypeDef *)UART6_BASE)
+#define USART7  ((HW_USART_TypeDef *)UART7_BASE)
+#define USART8  ((HW_USART_TypeDef *)UART8_BASE)
+#define USART9  ((HW_USART_TypeDef *)UART9_BASE)
 
 
 #define ASM_UART_INTR_RXIS   (1UL << 4)
@@ -91,7 +91,7 @@ typedef struct
 extern void Hw_UartDisable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartEnable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartReset(HW_USART_TypeDef* uartBase);
-extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, 
+extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate,
                           int dataBits, int stopBits, int parity);
 extern void Hw_UartInit(int index);
 #endif