diff options
| author | Bernard Xiong <[email protected]> | 2021-05-28 16:20:08 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-05-28 16:20:08 +0800 |
| commit | 92beddf3bccf6346e26aa097f82464456fb8e6bd (patch) | |
| tree | 197e4a108118dda016ea02274172f0c40e7ee8ed /bsp/at91sam9260 | |
| parent | b18a99b44240ec3152011e159cc24a5af8dff0ce (diff) | |
| parent | 03f4d40e30f3c94e1db0b3a65b3610dee695694a (diff) | |
Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5
[lts 3.1.x] format codes
Diffstat (limited to 'bsp/at91sam9260')
29 files changed, 3056 insertions, 3056 deletions
diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c index be110b5bd2..f1a377e1e9 100644 --- a/bsp/at91sam9260/applications/application.c +++ b/bsp/at91sam9260/applications/application.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -34,106 +34,106 @@ static int rt_led_app_init(void); int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - + #ifdef RT_USING_LED - rt_led_app_init(); + rt_led_app_init(); #endif } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -141,14 +141,14 @@ static int rt_led_app_init(void) #include <dfs_nfs.h> void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9260/drivers/at91_i2c_gpio.c b/bsp/at91sam9260/drivers/at91_i2c_gpio.c index fb4c0ccfaf..d863ffed88 100644 --- a/bsp/at91sam9260/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9260/drivers/at91_i2c_gpio.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include <rtdevice.h> @@ -15,101 +15,101 @@ static void at91_i2c_gpio_init() { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); + } } static rt_int32_t at91_get_sda(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, - 5, - 100 + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; + + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - bus->priv = (void *)&bit_ops; + bus->priv = (void *)&bit_ops; - at91_i2c_gpio_init(); + at91_i2c_gpio_init(); - rt_i2c_bit_add_bus(bus, "i2c0"); + rt_i2c_bit_add_bus(bus, "i2c0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9260/drivers/at91_mci.c b/bsp/at91sam9260/drivers/at91_mci.c index dfa5d5172e..92f7abdfec 100644 --- a/bsp/at91sam9260/drivers/at91_mci.c +++ b/bsp/at91sam9260/drivers/at91_mci.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include <rtthread.h> @@ -23,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ - | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) +#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ + | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ + | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -56,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91_MCI_IMR); + imr = at91_mci_read(AT91_MCI_IMR); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91_MCI_SDCR); - dtor = at91_mci_read(AT91_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91_MCI_SDCR); + dtor = at91_mci_read(AT91_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_SDCR, sdcr); - at91_mci_write(AT91_MCI_DTOR, dtor); - at91_mci_write(AT91_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_SDCR, sdcr); + at91_mci_write(AT91_MCI_DTOR, dtor); + at91_mci_write(AT91_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -95,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); - at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); - mr = AT91_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); + mr = AT91_MCI_PDCMODE | 0x34a; - mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; + mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; - at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ } /* @@ -115,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; + struct at91_mci *mci; - mci = (struct at91_mci *)data; + mci = (struct at91_mci *)data; - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -155,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; - mci_dbg("pre dma read\n"); + mci_dbg("pre dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - if (i == 0) - { - at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } + if (i == 0) + { + at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } - mci_dbg("pre dma read done\n"); + mci_dbg("pre dma read done\n"); } /* @@ -218,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; - mci->cmd = cmd; + mci->cmd = cmd; - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); - } - } + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); + } + } - cmdr = cmd->cmd_code; + cmdr = cmd->cmd_code; - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91_MCI_RSPTYP_136; - else - cmdr |= AT91_MCI_RSPTYP_48; - } + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91_MCI_RSPTYP_136; + else + cmdr |= AT91_MCI_RSPTYP_48; + } - if (data) - { + if (data) + { - block_length = data->blksize; - blocks = data->blks; + block_length = data->blksize; + blocks = data->blks; - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91_MCI_TRCMD_START; + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91_MCI_TRCMD_START; - if (data->flags & DATA_STREAM) - cmdr |= AT91_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } + if (data->flags & DATA_STREAM) + cmdr |= AT91_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91_MCI_SPCMD_INIT; - }*/ + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91_MCI_SPCMD_INIT; + }*/ - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91_MCI_TRCMD_STOP; + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91_MCI_TRCMD_STOP; - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91_MCI_OPDCMD; + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91_MCI_OPDCMD; - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); - if (!data) - { - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); - at91_mci_write(AT91_PDC_RPR, 0); - at91_mci_write(AT91_PDC_RCR, 0); - at91_mci_write(AT91_PDC_RNPR, 0); - at91_mci_write(AT91_PDC_RNCR, 0); - at91_mci_write(AT91_PDC_TPR, 0); - at91_mci_write(AT91_PDC_TCR, 0); - at91_mci_write(AT91_PDC_TNPR, 0); - at91_mci_write(AT91_PDC_TNCR, 0); - ier = AT91_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91_MCI_PDCMODE; - at91_mci_write(AT91_MCI_MR, mr); + if (!data) + { + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); + at91_mci_write(AT91_PDC_RPR, 0); + at91_mci_write(AT91_PDC_RCR, 0); + at91_mci_write(AT91_PDC_RNPR, 0); + at91_mci_write(AT91_PDC_RNCR, 0); + at91_mci_write(AT91_PDC_TPR, 0); + at91_mci_write(AT91_PDC_TCR, 0); + at91_mci_write(AT91_PDC_TNPR, 0); + at91_mci_write(AT91_PDC_TNCR, 0); + ier = AT91_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91_MCI_PDCMODE; + at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_BLKR, - AT91_MCI_BLKR_BCNT(blocks) | - AT91_MCI_BLKR_BLKLEN(block_length)); + at91_mci_write(AT91_MCI_BLKR, + AT91_MCI_BLKR_BCNT(blocks) | + AT91_MCI_BLKR_BLKLEN(block_length)); - /* - * Disable the PDC controller - */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* + * Disable the PDC controller + */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - { - /* - * Handle a read - */ + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + { + /* + * Handle a read + */ - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91_MCI_CMDRDY; - } - } - } + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91_MCI_CMDRDY; + } + } + } - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ - at91_mci_write(AT91_MCI_ARGR, cmd->arg); - at91_mci_write(AT91_MCI_CMDR, cmdr); + at91_mci_write(AT91_MCI_ARGR, cmd->arg); + at91_mci_write(AT91_MCI_CMDR, cmdr); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); - } + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); + } - /* Enable selected interrupts */ - at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); + /* Enable selected interrupts */ + at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); } /* @@ -404,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -430,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -446,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); - } else - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); + } else + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); } @@ -477,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); + at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); - } + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); + } - /* command not completed, have to wait */ - return 0; + /* command not completed, have to wait */ + return 0; } /* @@ -532,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); + cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - if (status & AT91_MCI_ERRORS) - { - if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) - { - if (data) - { - if (status & AT91_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } + if (status & AT91_MCI_ERRORS) + { + if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) + { + if (data) + { + if (status & AT91_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -597,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; - int_status = at91_mci_read(AT91_MCI_SR); - int_mask = at91_mci_read(AT91_MCI_IMR); + int_status = at91_mci_read(AT91_MCI_SR); + int_mask = at91_mci_read(AT91_MCI_IMR); - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); - int_status = int_status & int_mask; + int_status = int_status & int_mask; - if (int_status & AT91_MCI_ERRORS) - { - completed = 1; + if (int_status & AT91_MCI_ERRORS) + { + completed = 1; - if (int_status & AT91_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ + if (int_status & AT91_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ - if (int_status & AT91_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } + if (int_status & AT91_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } - if (int_status & AT91_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } + if (int_status & AT91_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } - if (int_status & AT91_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); - completed = 1; - } + if (int_status & AT91_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); + completed = 1; + } - if (int_status & AT91_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); + if (int_status & AT91_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); - if (int_status & AT91_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } + if (int_status & AT91_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } - if (int_status & AT91_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); + if (int_status & AT91_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); - if (int_status & AT91_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - } + if (int_status & AT91_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + } - /*if (int_status & AT91_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ + /*if (int_status & AT91_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ - if (int_status & AT91_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); + if (int_status & AT91_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); - if (int_status & AT91_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); + if (int_status & AT91_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); - if (int_status & AT91_MCI_RXRDY) - mci_dbg("Ready to receive\n"); + if (int_status & AT91_MCI_RXRDY) + mci_dbg("Ready to receive\n"); - if (int_status & AT91_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } + if (int_status & AT91_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); } @@ -720,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); - } + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); + } - /* Set the clock divider */ - at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); + /* Set the clock divider */ + at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); #else - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; + struct rt_mmcsd_host *host; + struct at91_mci *mci; + + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } + rt_memset(mci, 0, sizeof(struct at91_mci)); - rt_memset(mci, 0, sizeof(struct at91_mci)); + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; + mci->host = host; - mci->host = host; + mci_gpio_init(); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - mci_gpio_init(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); + at91_mci_disable(); + at91_mci_enable(); - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - //rt_timer_start(&mci->timer); + //rt_timer_start(&mci->timer); - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - host->private_data = mci; + host->private_data = mci; - mmcsd_change(host); + mmcsd_change(host); - return 0; + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -896,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9260/drivers/at91_mci.h b/bsp/at91sam9260/drivers/at91_mci.h index f2e4a0a56c..80eb07385d 100644 --- a/bsp/at91sam9260/drivers/at91_mci.h +++ b/bsp/at91sam9260/drivers/at91_mci.h @@ -11,99 +11,99 @@ #ifndef __AT91_MCI_H__ #define __AT91_MCI_H__ -#define AT91_MCI_CR 0x00 /* Control Register */ -#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91_MCI_CR 0x00 /* Control Register */ +#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91_MCI_MR 0x04 /* Mode Register */ -#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91_MCI_MR 0x04 /* Mode Register */ +#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91_MCI_DTOMUL_1 (0 << 4) -#define AT91_MCI_DTOMUL_16 (1 << 4) -#define AT91_MCI_DTOMUL_128 (2 << 4) -#define AT91_MCI_DTOMUL_256 (3 << 4) -#define AT91_MCI_DTOMUL_1K (4 << 4) -#define AT91_MCI_DTOMUL_4K (5 << 4) -#define AT91_MCI_DTOMUL_64K (6 << 4) -#define AT91_MCI_DTOMUL_1M (7 << 4) +#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91_MCI_DTOMUL_1 (0 << 4) +#define AT91_MCI_DTOMUL_16 (1 << 4) +#define AT91_MCI_DTOMUL_128 (2 << 4) +#define AT91_MCI_DTOMUL_256 (3 << 4) +#define AT91_MCI_DTOMUL_1K (4 << 4) +#define AT91_MCI_DTOMUL_4K (5 << 4) +#define AT91_MCI_DTOMUL_64K (6 << 4) +#define AT91_MCI_DTOMUL_1M (7 << 4) -#define AT91_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91_MCI_ARGR 0x10 /* Argument Register */ +#define AT91_MCI_ARGR 0x10 /* Argument Register */ -#define AT91_MCI_CMDR 0x14 /* Command Register */ -#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91_MCI_RSPTYP_NONE (0 << 6) -#define AT91_MCI_RSPTYP_48 (1 << 6) -#define AT91_MCI_RSPTYP_136 (2 << 6) -#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91_MCI_SPCMD_NONE (0 << 8) -#define AT91_MCI_SPCMD_INIT (1 << 8) -#define AT91_MCI_SPCMD_SYNC (2 << 8) -#define AT91_MCI_SPCMD_ICMD (4 << 8) -#define AT91_MCI_SPCMD_IRESP (5 << 8) -#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91_MCI_TRCMD_NONE (0 << 16) -#define AT91_MCI_TRCMD_START (1 << 16) -#define AT91_MCI_TRCMD_STOP (2 << 16) -#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91_MCI_TRTYP_BLOCK (0 << 19) -#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91_MCI_TRTYP_STREAM (2 << 19) +#define AT91_MCI_CMDR 0x14 /* Command Register */ +#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91_MCI_RSPTYP_NONE (0 << 6) +#define AT91_MCI_RSPTYP_48 (1 << 6) +#define AT91_MCI_RSPTYP_136 (2 << 6) +#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91_MCI_SPCMD_NONE (0 << 8) +#define AT91_MCI_SPCMD_INIT (1 << 8) +#define AT91_MCI_SPCMD_SYNC (2 << 8) +#define AT91_MCI_SPCMD_ICMD (4 << 8) +#define AT91_MCI_SPCMD_IRESP (5 << 8) +#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91_MCI_TRCMD_NONE (0 << 16) +#define AT91_MCI_TRCMD_START (1 << 16) +#define AT91_MCI_TRCMD_STOP (2 << 16) +#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91_MCI_TRTYP_BLOCK (0 << 19) +#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91_MCI_TRTYP_STREAM (2 << 19) -#define AT91_MCI_BLKR 0x18 /* Block Register */ -#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91_MCI_BLKR 0x18 /* Block Register */ +#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91_MCI_SR 0x40 /* Status Register */ -#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91_MCI_SR 0x40 /* Status Register */ +#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c index 78404a4ee0..8a063cfc86 100644 --- a/bsp/at91sam9260/drivers/board.c +++ b/bsp/at91sam9260/drivers/board.c @@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); static struct mem_desc at91_mem_desc[] = { - { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ - { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ - { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ - { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ + { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ + { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ + { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ + { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ }; -#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer */ void rt_timer_handler(int vector, void *param) { - #ifdef RT_USING_DBGU - if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) - { - rt_dbgu_isr(); - } - #endif - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) - { - unsigned nr_ticks; + #ifdef RT_USING_DBGU + if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) + { + rt_dbgu_isr(); + } + #endif + if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) + { + unsigned nr_ticks; - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - rt_tick_increase(); - } + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + rt_tick_increase(); + } } static void at91sam926x_pit_reset(void) { - /* Disable timer and irqs */ - at91_sys_write(AT91_PIT_MR, 0); + /* Disable timer and irqs */ + at91_sys_write(AT91_PIT_MR, 0); - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) - ; + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) + ; - /* Start PIT but don't enable IRQ */ - //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); - pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN - | AT91_PIT_PITIEN); - rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); + /* Start PIT but don't enable IRQ */ + //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN + | AT91_PIT_PITIEN); + rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); } /* @@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void) */ static void at91sam926x_pit_init(void) { - rt_uint32_t pit_rate; - rt_uint32_t bits; + rt_uint32_t pit_rate; + rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam926x_pit_reset(); + /* Initialize and enable the timer */ + at91sam926x_pit_reset(); } @@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void) */ void rt_hw_timer_init() { - at91sam926x_pit_init(); + at91sam926x_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91_ID_SYS); } - + void at91_tc1_init() { - at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0); - writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR); - writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR); - writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR); - writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV); + at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0); + writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR); + writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR); + writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR); + writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV); } -#define RXRDY 0x01 -#define TXRDY (1 << 1) -#define BPS 115200 /* serial baudrate */ +#define RXRDY 0x01 +#define TXRDY (1 << 1) +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t CR; - volatile rt_uint32_t MR; - volatile rt_uint32_t IER; - volatile rt_uint32_t IDR; - volatile rt_uint32_t IMR; - volatile rt_uint32_t CSR; - volatile rt_uint32_t RHR; - volatile rt_uint32_t THR; - volatile rt_uint32_t BRGR; - volatile rt_uint32_t RTOR; - volatile rt_uint32_t TTGR; - volatile rt_uint32_t reserved0[5]; - volatile rt_uint32_t FIDI; - volatile rt_uint32_t NER; - volatile rt_uint32_t reserved1; - volatile rt_uint32_t IFR; - volatile rt_uint32_t reserved2[44]; - volatile rt_uint32_t RPR; - volatile rt_uint32_t RCR; - volatile rt_uint32_t TPR; - volatile rt_uint32_t TCR; - volatile rt_uint32_t RNPR; - volatile rt_uint32_t RNCR; - volatile rt_uint32_t TNPR; - volatile rt_uint32_t TNCR; - volatile rt_uint32_t PTCR; - volatile rt_uint32_t PTSR; + volatile rt_uint32_t CR; + volatile rt_uint32_t MR; + volatile rt_uint32_t IER; + volatile rt_uint32_t IDR; + volatile rt_uint32_t IMR; + volatile rt_uint32_t CSR; + volatile rt_uint32_t RHR; + volatile rt_uint32_t THR; + volatile rt_uint32_t BRGR; + volatile rt_uint32_t RTOR; + volatile rt_uint32_t TTGR; + volatile rt_uint32_t reserved0[5]; + volatile rt_uint32_t FIDI; + volatile rt_uint32_t NER; + volatile rt_uint32_t reserved1; + volatile rt_uint32_t IFR; + volatile rt_uint32_t reserved2[44]; + volatile rt_uint32_t RPR; + volatile rt_uint32_t RCR; + volatile rt_uint32_t TPR; + volatile rt_uint32_t TCR; + volatile rt_uint32_t RNPR; + volatile rt_uint32_t RNCR; + volatile rt_uint32_t TNPR; + volatile rt_uint32_t TNCR; + volatile rt_uint32_t PTCR; + volatile rt_uint32_t PTSR; }uartport; #define CIDR FIDI #define EXID NER #define FNR reserved1 -#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) +#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) static void at91_usart_putc(char c) { while (!(DBGU->CSR & TXRDY)); - DBGU->THR = c; + DBGU->THR = c; } /** @@ -191,33 +191,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } - at91_usart_putc(*str++); - } + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; + int div; + int mode = 0; - DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - mode |= AT91_US_CHRL_8; - mode |= AT91_US_NBSTOP_1; - mode |= AT91_US_PAR_NONE; - DBGU->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - DBGU->BRGR = div; - DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; + DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + mode |= AT91_US_CHRL_8; + mode |= AT91_US_NBSTOP_1; + mode |= AT91_US_PAR_NONE; + DBGU->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + DBGU->BRGR = div; + DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; } @@ -226,31 +226,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c index 8d56a99ffa..10277813d4 100644 --- a/bsp/at91sam9260/drivers/led.c +++ b/bsp/at91sam9260/drivers/led.c @@ -14,59 +14,59 @@ #if 1 // GB9260 board -#define PIO_LED AT91_PIOB -#define LED1 (1 << 25) // LED_SYS -#define LED2 (0) -#define LED3 (1 << 23) // LED_USR -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOB +#define LED1 (1 << 25) // LED_SYS +#define LED2 (0) +#define LED3 (1 << 23) // LED_USR +#define LED_ALL (LED1 | LED2 | LED3) #else -#define PIO_LED AT91_PIOC -#define LED1 (1 << 8) -#define LED2 (1 << 11) -#define LED3 (1 << 6) -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOC +#define LED1 (1 << 8) +#define LED2 (1 << 11) +#define LED3 (1 << 6) +#define LED_ALL (LED1 | LED2 | LED3) #endif void led_init(void) { - at91_sys_write(PIO_LED+0x00, LED_ALL); - at91_sys_write(PIO_LED+0x10, LED_ALL); - at91_sys_write(PIO_LED+0x64, LED_ALL); - at91_sys_write(PIO_LED+0x30, LED_ALL); + at91_sys_write(PIO_LED+0x00, LED_ALL); + at91_sys_write(PIO_LED+0x10, LED_ALL); + at91_sys_write(PIO_LED+0x64, LED_ALL); + at91_sys_write(PIO_LED+0x30, LED_ALL); } void led_on(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x34, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x34, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x34, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x34, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x34, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x34, LED3); + break; + default: + break; + } } void led_off(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x30, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x30, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x30, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x30, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x30, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x30, LED3); + break; + default: + break; + } } diff --git a/bsp/at91sam9260/drivers/macb.c b/bsp/at91sam9260/drivers/macb.c index 78fdfab902..702d7e04a4 100644 --- a/bsp/at91sam9260/drivers/macb.c +++ b/bsp/at91sam9260/drivers/macb.c @@ -14,7 +14,7 @@ #include <at91sam926x.h> #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -22,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -36,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -45,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - unsigned int regs; + unsigned int regs; - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; - unsigned int tx_stop; + unsigned int tx_stop; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -165,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; - status = macb_readl(macb, ISR); + status = macb_readl(macb, ISR); - while (status) { + while (status) { - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } + } - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ - status = macb_readl(macb, ISR); - } + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - frame = macb_readl(macb, MAN); + frame = macb_readl(macb, MAN); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); - return MACB_BFEXT(DATA, frame); + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; + + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } - } + } } @@ -420,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; + + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); - - /* choose RMII or MII mode. This depends on the board */ + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; + if (!macb_phy_init(dev)) + return -RT_ERROR; + + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); + + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - rt_timer_start(&macb->timer); - - return RT_EOK; + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -611,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } - macb->tx_stop = 0; + macb->tx_stop = 0; - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); - return RT_EOK; + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; + unsigned int i; - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } - macb->rx_tail = new_tail; + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; + + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } - rt_sem_release(&macb->rx_lock); + rt_sem_release(&macb->rx_lock); - return p; + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + /* Pins used for MII and RMII */ + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); #ifndef GONFIG_RMII - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + + macb->tx_pending = DEF_TX_RING_PENDING; - macb->tx_pending = DEF_TX_RING_PENDING; + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - macb_writel(macb, NCFGR, ncfgr); + macb_writel(macb, NCFGR, ncfgr); - macb->link = 0; + macb->link = 0; - return RT_EOK; + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + rt_err_t ret; + at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - eth_device_init(&(macb_device.parent), "e0"); + eth_device_init(&(macb_device.parent), "e0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9260/drivers/macb.h b/bsp/at91sam9260/drivers/macb.h index d6ecb2dd56..ed2ad390b7 100644 --- a/bsp/at91sam9260/drivers/macb.h +++ b/bsp/at91sam9260/drivers/macb.h @@ -12,319 +12,319 @@ #include <mii.h> /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9260/drivers/mii.h b/bsp/at91sam9260/drivers/mii.h index 84f7cfe91c..03d914b7c3 100644 --- a/bsp/at91sam9260/drivers/mii.h +++ b/bsp/at91sam9260/drivers/mii.h @@ -22,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -37,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -56,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -85,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -107,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -118,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -137,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c index dee5585f36..2d493a21bb 100644 --- a/bsp/at91sam9260/drivers/usart.c +++ b/bsp/at91sam9260/drivers/usart.c @@ -14,54 +14,54 @@ #include <at91sam926x.h> #include <rtdevice.h> -#define RXRDY 0x01 -#define TXRDY (1 << 1) +#define RXRDY 0x01 +#define TXRDY (1 << 1) typedef struct uartport { - volatile rt_uint32_t CR; - volatile rt_uint32_t MR; - volatile rt_uint32_t IER; - volatile rt_uint32_t IDR; - volatile rt_uint32_t IMR; - volatile rt_uint32_t CSR; - volatile rt_uint32_t RHR; - volatile rt_uint32_t THR; - volatile rt_uint32_t BRGR; - volatile rt_uint32_t RTOR; - volatile rt_uint32_t TTGR; - volatile rt_uint32_t reserved0[5]; - volatile rt_uint32_t FIDI; - volatile rt_uint32_t NER; - volatile rt_uint32_t reserved1; - volatile rt_uint32_t IFR; - volatile rt_uint32_t reserved2[44]; - volatile rt_uint32_t RPR; - volatile rt_uint32_t RCR; - volatile rt_uint32_t TPR; - volatile rt_uint32_t TCR; - volatile rt_uint32_t RNPR; - volatile rt_uint32_t RNCR; - volatile rt_uint32_t TNPR; - volatile rt_uint32_t TNCR; - volatile rt_uint32_t PTCR; - volatile rt_uint32_t PTSR; + volatile rt_uint32_t CR; + volatile rt_uint32_t MR; + volatile rt_uint32_t IER; + volatile rt_uint32_t IDR; + volatile rt_uint32_t IMR; + volatile rt_uint32_t CSR; + volatile rt_uint32_t RHR; + volatile rt_uint32_t THR; + volatile rt_uint32_t BRGR; + volatile rt_uint32_t RTOR; + volatile rt_uint32_t TTGR; + volatile rt_uint32_t reserved0[5]; + volatile rt_uint32_t FIDI; + volatile rt_uint32_t NER; + volatile rt_uint32_t reserved1; + volatile rt_uint32_t IFR; + volatile rt_uint32_t reserved2[44]; + volatile rt_uint32_t RPR; + volatile rt_uint32_t RCR; + volatile rt_uint32_t TPR; + volatile rt_uint32_t TCR; + volatile rt_uint32_t RNPR; + volatile rt_uint32_t RNCR; + volatile rt_uint32_t TNPR; + volatile rt_uint32_t TNCR; + volatile rt_uint32_t PTCR; + volatile rt_uint32_t PTSR; }uartport; #define CIDR FIDI #define EXID NER #define FNR reserved1 -#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) +#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) -#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) -#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) -#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) -#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) +#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) +#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) +#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) +#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) struct at91_uart { - uartport *port; - int irq; + uartport *port; + int irq; }; @@ -71,18 +71,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->CSR; - if (!(status & uart->port->IMR)) - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->CSR; + if (!(status & uart->port->IMR)) + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -91,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; + uart = (struct at91_uart *)serial->parent.user_data; - uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91_US_CHRL_8; - break; - case DATA_BITS_7: - mode |= AT91_US_CHRL_7; - break; - case DATA_BITS_6: - mode |= AT91_US_CHRL_6; - break; - case DATA_BITS_5: - mode |= AT91_US_CHRL_5; - break; - default: - mode |= AT91_US_CHRL_8; - break; - } + uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91_US_CHRL_8; + break; + case DATA_BITS_7: + mode |= AT91_US_CHRL_7; + break; + case DATA_BITS_6: + mode |= AT91_US_CHRL_6; + break; + case DATA_BITS_5: + mode |= AT91_US_CHRL_5; + break; + default: + mode |= AT91_US_CHRL_8; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91_US_NBSTOP_2; - break; - case STOP_BITS_1: - default: - mode |= AT91_US_NBSTOP_1; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91_US_NBSTOP_2; + break; + case STOP_BITS_1: + default: + mode |= AT91_US_NBSTOP_1; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91_US_PAR_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91_US_PAR_NONE; + break; + } - uart->port->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->BRGR = div; - uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; - uart->port->IER = 0x01; + uart->port->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->BRGR = div; + uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; + uart->port->IER = 0x01; return RT_EOK; } @@ -168,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -182,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->CSR & TXRDY)); - uart->port->THR = c; + uart->port->THR = c; return 1; } @@ -193,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->CSR & RXRDY) - { - result = uart->port->RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -218,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - DBGU, - AT91_ID_SYS + DBGU, + AT91_ID_SYS }; #endif @@ -227,82 +227,82 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - UART0, - AT91SAM9260_ID_US0 + UART0, + AT91SAM9260_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - UART1, - AT91SAM9260_ID_US1 + UART1, + AT91SAM9260_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - UART2, - AT91SAM9260_ID_US2 + UART2, + AT91SAM9260_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - UART3, - AT91SAM9260_ID_US3 + UART3, + AT91SAM9260_ID_US3 }; #endif void at91_usart_gpio_init(void) { - rt_uint32_t val; + rt_uint32_t val; #ifdef RT_USING_DBGU - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); - //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); + //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); #endif #ifdef RT_USING_UART0 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); #endif #ifdef RT_USING_UART1 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); #endif #ifdef RT_USING_UART2 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); #endif #ifdef RT_USING_UART3 - at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11)); + at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11)); #endif } @@ -314,17 +314,17 @@ void at91_usart_gpio_init(void) */ int rt_hw_uart_init(void) { - at91_usart_gpio_init(); + at91_usart_gpio_init(); #if defined(RT_USING_DBGU) - serial_dbgu.ops = &at91_usart_ops; - serial_dbgu.config.baud_rate = BAUD_RATE_115200; + serial_dbgu.ops = &at91_usart_ops; + serial_dbgu.config.baud_rate = BAUD_RATE_115200; serial_dbgu.config.bit_order = BIT_ORDER_LSB; serial_dbgu.config.data_bits = DATA_BITS_8; serial_dbgu.config.parity = PARITY_NONE; serial_dbgu.config.stop_bits = STOP_BITS_1; serial_dbgu.config.invert = NRZ_NORMAL; - serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ; + serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial_dbgu, "dbgu", @@ -333,83 +333,83 @@ int rt_hw_uart_init(void) #endif #if defined(RT_USING_UART0) - serial0.ops = &at91_usart_ops; - serial0.config.baud_rate = BAUD_RATE_115200; + serial0.ops = &at91_usart_ops; + serial0.config.baud_rate = BAUD_RATE_115200; serial0.config.bit_order = BIT_ORDER_LSB; serial0.config.data_bits = DATA_BITS_8; serial0.config.parity = PARITY_NONE; serial0.config.stop_bits = STOP_BITS_1; serial0.config.invert = NRZ_NORMAL; - serial0.config.bufsz = RT_SERIAL_RB_BUFSZ; + serial0.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart0); - rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler, - (void *)&(serial0.parent), "UART0"); - rt_hw_interrupt_umask(uart0.irq); + rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler, + (void *)&(serial0.parent), "UART0"); + rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART1) - serial1.ops = &at91_usart_ops; + serial1.ops = &at91_usart_ops; serial1.int_rx = &uart1_int_rx; - serial1.config.baud_rate = BAUD_RATE_115200; + serial1.config.baud_rate = BAUD_RATE_115200; serial1.config.bit_order = BIT_ORDER_LSB; serial1.config.data_bits = DATA_BITS_8; serial1.config.parity = PARITY_NONE; serial1.config.stop_bits = STOP_BITS_1; serial1.config.invert = NRZ_NORMAL; - serial1.config.bufsz = RT_SERIAL_RB_BUFSZ; + serial1.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart1); - rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, - (void *)&(serial1.parent), "UART1"); - rt_hw_interrupt_umask(uart1.irq); + rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, + (void *)&(serial1.parent), "UART1"); + rt_hw_interrupt_umask(uart1.irq); #endif #if defined(RT_USING_UART2) - serial2.ops = &at91_usart_ops; - serial2.config.baud_rate = BAUD_RATE_115200; + serial2.ops = &at91_usart_ops; + serial2.config.baud_rate = BAUD_RATE_115200; serial2.config.bit_order = BIT_ORDER_LSB; serial2.config.data_bits = DATA_BITS_8; serial2.config.parity = PARITY_NONE; serial2.config.stop_bits = STOP_BITS_1; serial2.config.invert = NRZ_NORMAL; - serial2.config.bufsz = RT_SERIAL_RB_BUFSZ; + serial2.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart2); - rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, - (void *)&(serial2.parent), "UART2"); - rt_hw_interrupt_umask(uart2.irq); + rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, + (void *)&(serial2.parent), "UART2"); + rt_hw_interrupt_umask(uart2.irq); #endif #if defined(RT_USING_UART3) - serial3.ops = &at91_usart_ops; - serial3.config.baud_rate = BAUD_RATE_115200; + serial3.ops = &at91_usart_ops; + serial3.config.baud_rate = BAUD_RATE_115200; serial3.config.bit_order = BIT_ORDER_LSB; serial3.config.data_bits = DATA_BITS_8; serial3.config.parity = PARITY_NONE; serial3.config.stop_bits = STOP_BITS_1; serial3.config.invert = NRZ_NORMAL; - serial3.config.bufsz = RT_SERIAL_RB_BUFSZ; + serial3.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart3); - rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, - (void *)&(serial3.parent), "UART3"); - rt_hw_interrupt_umask(uart3.irq); + rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, + (void *)&(serial3.parent), "UART3"); + rt_hw_interrupt_umask(uart3.irq); #endif - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); @@ -417,7 +417,7 @@ INIT_BOARD_EXPORT(rt_hw_uart_init); #ifdef RT_USING_DBGU void rt_dbgu_isr(void) { - rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent)); + rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent)); } #endif diff --git a/bsp/at91sam9260/platform/at91_aic.h b/bsp/at91sam9260/platform/at91_aic.h index f9db21dde1..3f9139d1fc 100644 --- a/bsp/at91sam9260/platform/at91_aic.h +++ b/bsp/at91sam9260/platform/at91_aic.h @@ -15,41 +15,41 @@ extern "C" { #endif -#define AIC_IRQS 32 +#define AIC_IRQS 32 -#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ -#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ -#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ -#define AT91_AIC_SRCTYPE_LOW (0 << 5) -#define AT91_AIC_SRCTYPE_FALLING (1 << 5) -#define AT91_AIC_SRCTYPE_HIGH (2 << 5) -#define AT91_AIC_SRCTYPE_RISING (3 << 5) +#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ +#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ +#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ +#define AT91_AIC_SRCTYPE_LOW (0 << 5) +#define AT91_AIC_SRCTYPE_FALLING (1 << 5) +#define AT91_AIC_SRCTYPE_HIGH (2 << 5) +#define AT91_AIC_SRCTYPE_RISING (3 << 5) -#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ -#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ -#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ -#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ -#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ +#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ +#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ +#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ +#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ +#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ -#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ -#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ -#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ -#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ -#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ +#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ +#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ +#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ +#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ +#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ -#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ -#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ -#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ -#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ -#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ -#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ -#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ -#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ -#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ +#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ +#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ +#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ +#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ +#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ +#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ +#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ +#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ +#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ -#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ -#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ -#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ +#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ +#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ +#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_pdc.h b/bsp/at91sam9260/platform/at91_pdc.h index 1b8cc39fec..905bedbadb 100644 --- a/bsp/at91sam9260/platform/at91_pdc.h +++ b/bsp/at91sam9260/platform/at91_pdc.h @@ -11,21 +11,21 @@ #ifndef __AT91_PDC_H__ #define __AT91_PDC_H__ -#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ -#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ -#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ -#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ -#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ -#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ -#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ -#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ +#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ +#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ +#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ +#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ +#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ -#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ -#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ -#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ -#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ -#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ +#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ +#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ +#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ +#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ +#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ -#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ +#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ #endif diff --git a/bsp/at91sam9260/platform/at91_pio.h b/bsp/at91sam9260/platform/at91_pio.h index 8d09bf96e3..444df2b9fb 100644 --- a/bsp/at91sam9260/platform/at91_pio.h +++ b/bsp/at91sam9260/platform/at91_pio.h @@ -16,35 +16,35 @@ extern "C" { #endif -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ +#define PIO_PER 0x00 /* Enable Register */ +#define PIO_PDR 0x04 /* Disable Register */ +#define PIO_PSR 0x08 /* Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Register */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ +#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ +#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pull-up Status Register */ +#define PIO_ASR 0x70 /* Peripheral A Select Register */ +#define PIO_BSR 0x74 /* Peripheral B Select Register */ +#define PIO_ABSR 0x78 /* AB Status Register */ +#define PIO_OWER 0xa0 /* Output Write Enable Register */ +#define PIO_OWDR 0xa4 /* Output Write Disable Register */ +#define PIO_OWSR 0xa8 /* Output Write Status Register */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_pit.h b/bsp/at91sam9260/platform/at91_pit.h index 2a7120c7ea..78c8ed643c 100644 --- a/bsp/at91sam9260/platform/at91_pit.h +++ b/bsp/at91sam9260/platform/at91_pit.h @@ -15,18 +15,18 @@ extern "C" { #endif -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ +#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ +#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ +#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ +#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ +#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ +#define AT91_PIT_PITS (1 << 0) /* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ +#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ +#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ +#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ +#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_pmc.h b/bsp/at91sam9260/platform/at91_pmc.h index 9f789dbde5..7d14f55c7c 100644 --- a/bsp/at91sam9260/platform/at91_pmc.h +++ b/bsp/at91sam9260/platform/at91_pmc.h @@ -15,119 +15,119 @@ extern "C" { #endif -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ +#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ -#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_rstc.h b/bsp/at91sam9260/platform/at91_rstc.h index 8546f8198b..e7ba900e36 100644 --- a/bsp/at91sam9260/platform/at91_rstc.h +++ b/bsp/at91sam9260/platform/at91_rstc.h @@ -15,27 +15,27 @@ extern "C" { #endif -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ +#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ +#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ +#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ +#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ +#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ +#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ +#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) +#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ +#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ +#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ +#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ +#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ +#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_serial.h b/bsp/at91sam9260/platform/at91_serial.h index 6357d590b4..e19a6c02dc 100644 --- a/bsp/at91sam9260/platform/at91_serial.h +++ b/bsp/at91sam9260/platform/at91_serial.h @@ -15,113 +15,113 @@ extern "C" { #endif -#define AT91_US_CR 0x00 /* Control Register */ -#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */ -#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */ -#define AT91_US_RXEN (1 << 4) /* Receiver Enable */ -#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */ -#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */ -#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */ -#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */ -#define AT91_US_STTBRK (1 << 9) /* Start Break */ -#define AT91_US_STPBRK (1 << 10) /* Stop Break */ -#define AT91_US_STTTO (1 << 11) /* Start Time-out */ -#define AT91_US_SENDA (1 << 12) /* Send Address */ -#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */ -#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ -#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */ -#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ -#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ -#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */ -#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */ +#define AT91_US_CR 0x00 /* Control Register */ +#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */ +#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */ +#define AT91_US_RXEN (1 << 4) /* Receiver Enable */ +#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */ +#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */ +#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */ +#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */ +#define AT91_US_STTBRK (1 << 9) /* Start Break */ +#define AT91_US_STPBRK (1 << 10) /* Stop Break */ +#define AT91_US_STTTO (1 << 11) /* Start Time-out */ +#define AT91_US_SENDA (1 << 12) /* Send Address */ +#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */ +#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ +#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */ +#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ +#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ +#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */ +#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */ -#define AT91_US_MR 0x04 /* Mode Register */ -#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */ -#define AT91_US_USMODE_NORMAL 0 -#define AT91_US_USMODE_RS485 1 -#define AT91_US_USMODE_HWHS 2 -#define AT91_US_USMODE_MODEM 3 -#define AT91_US_USMODE_ISO7816_T0 4 -#define AT91_US_USMODE_ISO7816_T1 6 -#define AT91_US_USMODE_IRDA 8 -#define AT91_US_USCLKS (3 << 4) /* Clock Selection */ -#define AT91_US_USCLKS_MCK (0 << 4) -#define AT91_US_USCLKS_MCK_DIV8 (1 << 4) -#define AT91_US_USCLKS_SCK (3 << 4) -#define AT91_US_CHRL (3 << 6) /* Character Length */ -#define AT91_US_CHRL_5 (0 << 6) -#define AT91_US_CHRL_6 (1 << 6) -#define AT91_US_CHRL_7 (2 << 6) -#define AT91_US_CHRL_8 (3 << 6) -#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */ -#define AT91_US_PAR (7 << 9) /* Parity Type */ -#define AT91_US_PAR_EVEN (0 << 9) -#define AT91_US_PAR_ODD (1 << 9) -#define AT91_US_PAR_SPACE (2 << 9) -#define AT91_US_PAR_MARK (3 << 9) -#define AT91_US_PAR_NONE (4 << 9) -#define AT91_US_PAR_MULTI_DROP (6 << 9) -#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */ -#define AT91_US_NBSTOP_1 (0 << 12) -#define AT91_US_NBSTOP_1_5 (1 << 12) -#define AT91_US_NBSTOP_2 (2 << 12) -#define AT91_US_CHMODE (3 << 14) /* Channel Mode */ -#define AT91_US_CHMODE_NORMAL (0 << 14) -#define AT91_US_CHMODE_ECHO (1 << 14) -#define AT91_US_CHMODE_LOC_LOOP (2 << 14) -#define AT91_US_CHMODE_REM_LOOP (3 << 14) -#define AT91_US_MSBF (1 << 16) /* Bit Order */ -#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */ -#define AT91_US_CLKO (1 << 18) /* Clock Output Select */ -#define AT91_US_OVER (1 << 19) /* Oversampling Mode */ -#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ -#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */ -#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */ -#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ +#define AT91_US_MR 0x04 /* Mode Register */ +#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */ +#define AT91_US_USMODE_NORMAL 0 +#define AT91_US_USMODE_RS485 1 +#define AT91_US_USMODE_HWHS 2 +#define AT91_US_USMODE_MODEM 3 +#define AT91_US_USMODE_ISO7816_T0 4 +#define AT91_US_USMODE_ISO7816_T1 6 +#define AT91_US_USMODE_IRDA 8 +#define AT91_US_USCLKS (3 << 4) /* Clock Selection */ +#define AT91_US_USCLKS_MCK (0 << 4) +#define AT91_US_USCLKS_MCK_DIV8 (1 << 4) +#define AT91_US_USCLKS_SCK (3 << 4) +#define AT91_US_CHRL (3 << 6) /* Character Length */ +#define AT91_US_CHRL_5 (0 << 6) +#define AT91_US_CHRL_6 (1 << 6) +#define AT91_US_CHRL_7 (2 << 6) +#define AT91_US_CHRL_8 (3 << 6) +#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */ +#define AT91_US_PAR (7 << 9) /* Parity Type */ +#define AT91_US_PAR_EVEN (0 << 9) +#define AT91_US_PAR_ODD (1 << 9) +#define AT91_US_PAR_SPACE (2 << 9) +#define AT91_US_PAR_MARK (3 << 9) +#define AT91_US_PAR_NONE (4 << 9) +#define AT91_US_PAR_MULTI_DROP (6 << 9) +#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */ +#define AT91_US_NBSTOP_1 (0 << 12) +#define AT91_US_NBSTOP_1_5 (1 << 12) +#define AT91_US_NBSTOP_2 (2 << 12) +#define AT91_US_CHMODE (3 << 14) /* Channel Mode */ +#define AT91_US_CHMODE_NORMAL (0 << 14) +#define AT91_US_CHMODE_ECHO (1 << 14) +#define AT91_US_CHMODE_LOC_LOOP (2 << 14) +#define AT91_US_CHMODE_REM_LOOP (3 << 14) +#define AT91_US_MSBF (1 << 16) /* Bit Order */ +#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */ +#define AT91_US_CLKO (1 << 18) /* Clock Output Select */ +#define AT91_US_OVER (1 << 19) /* Oversampling Mode */ +#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ +#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */ +#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */ +#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ -#define AT91_US_IER 0x08 /* Interrupt Enable Register */ -#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */ -#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */ -#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */ -#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ -#define AT91_US_OVRE (1 << 5) /* Overrun Error */ -#define AT91_US_FRAME (1 << 6) /* Framing Error */ -#define AT91_US_PARE (1 << 7) /* Parity Error */ -#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */ -#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ -#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ -#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */ -#define AT91_US_NACK (1 << 13) /* Non Acknowledge */ -#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ -#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ -#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ -#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */ -#define AT91_US_RI (1 << 20) /* RI */ -#define AT91_US_DSR (1 << 21) /* DSR */ -#define AT91_US_DCD (1 << 22) /* DCD */ -#define AT91_US_CTS (1 << 23) /* CTS */ +#define AT91_US_IER 0x08 /* Interrupt Enable Register */ +#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */ +#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */ +#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */ +#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ +#define AT91_US_OVRE (1 << 5) /* Overrun Error */ +#define AT91_US_FRAME (1 << 6) /* Framing Error */ +#define AT91_US_PARE (1 << 7) /* Parity Error */ +#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */ +#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ +#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ +#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */ +#define AT91_US_NACK (1 << 13) /* Non Acknowledge */ +#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ +#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ +#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ +#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */ +#define AT91_US_RI (1 << 20) /* RI */ +#define AT91_US_DSR (1 << 21) /* DSR */ +#define AT91_US_DCD (1 << 22) /* DCD */ +#define AT91_US_CTS (1 << 23) /* CTS */ -#define AT91_US_IDR 0x0c /* Interrupt Disable Register */ -#define AT91_US_IMR 0x10 /* Interrupt Mask Register */ -#define AT91_US_CSR 0x14 /* Channel Status Register */ -#define AT91_US_RHR 0x18 /* Receiver Holding Register */ -#define AT91_US_THR 0x1c /* Transmitter Holding Register */ -#define AT91_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ +#define AT91_US_IDR 0x0c /* Interrupt Disable Register */ +#define AT91_US_IMR 0x10 /* Interrupt Mask Register */ +#define AT91_US_CSR 0x14 /* Channel Status Register */ +#define AT91_US_RHR 0x18 /* Receiver Holding Register */ +#define AT91_US_THR 0x1c /* Transmitter Holding Register */ +#define AT91_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ -#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */ -#define AT91_US_CD (0xffff << 0) /* Clock Divider */ +#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */ +#define AT91_US_CD (0xffff << 0) /* Clock Divider */ -#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */ -#define AT91_US_TO (0xffff << 0) /* Time-out Value */ +#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */ +#define AT91_US_TO (0xffff << 0) /* Time-out Value */ -#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */ -#define AT91_US_TG (0xff << 0) /* Timeguard Value */ +#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */ +#define AT91_US_TG (0xff << 0) /* Timeguard Value */ -#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */ -#define AT91_US_NER 0x44 /* Number of Errors Register */ -#define AT91_US_IF 0x4c /* IrDA Filter Register */ +#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */ +#define AT91_US_NER 0x44 /* Number of Errors Register */ +#define AT91_US_IF 0x4c /* IrDA Filter Register */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_shdwc.h b/bsp/at91sam9260/platform/at91_shdwc.h index 3ff026ee9d..0ae994af96 100644 --- a/bsp/at91sam9260/platform/at91_shdwc.h +++ b/bsp/at91sam9260/platform/at91_shdwc.h @@ -15,24 +15,24 @@ extern "C" { #endif -#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ -#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ -#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ +#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ +#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ +#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ -#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ -#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ -#define AT91_SHDW_WKMODE0_NONE 0 -#define AT91_SHDW_WKMODE0_HIGH 1 -#define AT91_SHDW_WKMODE0_LOW 2 -#define AT91_SHDW_WKMODE0_ANYLEVEL 3 -#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ -#define AT91_SHDW_CPTWK0_(x) ((x) << 4) -#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ +#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ +#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ +#define AT91_SHDW_WKMODE0_NONE 0 +#define AT91_SHDW_WKMODE0_HIGH 1 +#define AT91_SHDW_WKMODE0_LOW 2 +#define AT91_SHDW_WKMODE0_ANYLEVEL 3 +#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ +#define AT91_SHDW_CPTWK0_(x) ((x) << 4) +#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ -#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ -#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ -#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ -#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ +#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ +#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ +#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ +#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91_tc.h b/bsp/at91sam9260/platform/at91_tc.h index bae215cfae..a868ef9b0e 100644 --- a/bsp/at91sam9260/platform/at91_tc.h +++ b/bsp/at91sam9260/platform/at91_tc.h @@ -15,133 +15,133 @@ extern "C" { #endif -#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ -#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ +#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ +#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ -#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ -#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ -#define AT91_TC_TC0XC0S_TCLK0 (0 << 0) -#define AT91_TC_TC0XC0S_NONE (1 << 0) -#define AT91_TC_TC0XC0S_TIOA1 (2 << 0) -#define AT91_TC_TC0XC0S_TIOA2 (3 << 0) -#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ -#define AT91_TC_TC1XC1S_TCLK1 (0 << 2) -#define AT91_TC_TC1XC1S_NONE (1 << 2) -#define AT91_TC_TC1XC1S_TIOA0 (2 << 2) -#define AT91_TC_TC1XC1S_TIOA2 (3 << 2) -#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ -#define AT91_TC_TC2XC2S_TCLK2 (0 << 4) -#define AT91_TC_TC2XC2S_NONE (1 << 4) -#define AT91_TC_TC2XC2S_TIOA0 (2 << 4) -#define AT91_TC_TC2XC2S_TIOA1 (3 << 4) +#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ +#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ +#define AT91_TC_TC0XC0S_TCLK0 (0 << 0) +#define AT91_TC_TC0XC0S_NONE (1 << 0) +#define AT91_TC_TC0XC0S_TIOA1 (2 << 0) +#define AT91_TC_TC0XC0S_TIOA2 (3 << 0) +#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ +#define AT91_TC_TC1XC1S_TCLK1 (0 << 2) +#define AT91_TC_TC1XC1S_NONE (1 << 2) +#define AT91_TC_TC1XC1S_TIOA0 (2 << 2) +#define AT91_TC_TC1XC1S_TIOA2 (3 << 2) +#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ +#define AT91_TC_TC2XC2S_TCLK2 (0 << 4) +#define AT91_TC_TC2XC2S_NONE (1 << 4) +#define AT91_TC_TC2XC2S_TIOA0 (2 << 4) +#define AT91_TC_TC2XC2S_TIOA1 (3 << 4) -#define AT91_TC_CCR 0x00 /* Channel Control Register */ -#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ -#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ -#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ +#define AT91_TC_CCR 0x00 /* Channel Control Register */ +#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ +#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ +#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ -#define AT91_TC_CMR 0x04 /* Channel Mode Register */ -#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ -#define AT91_TC_TIMER_CLOCK1 (0 << 0) -#define AT91_TC_TIMER_CLOCK2 (1 << 0) -#define AT91_TC_TIMER_CLOCK3 (2 << 0) -#define AT91_TC_TIMER_CLOCK4 (3 << 0) -#define AT91_TC_TIMER_CLOCK5 (4 << 0) -#define AT91_TC_XC0 (5 << 0) -#define AT91_TC_XC1 (6 << 0) -#define AT91_TC_XC2 (7 << 0) -#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ -#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ -#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ -#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ -#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ -#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ -#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ -#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ -#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ -#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ +#define AT91_TC_CMR 0x04 /* Channel Mode Register */ +#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ +#define AT91_TC_TIMER_CLOCK1 (0 << 0) +#define AT91_TC_TIMER_CLOCK2 (1 << 0) +#define AT91_TC_TIMER_CLOCK3 (2 << 0) +#define AT91_TC_TIMER_CLOCK4 (3 << 0) +#define AT91_TC_TIMER_CLOCK5 (4 << 0) +#define AT91_TC_XC0 (5 << 0) +#define AT91_TC_XC1 (6 << 0) +#define AT91_TC_XC2 (7 << 0) +#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ +#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ +#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ +#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ +#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ +#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ +#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ +#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ +#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ +#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ -#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ -#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ -#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ -#define AT91_TC_EEVTEDG_NONE (0 << 8) -#define AT91_TC_EEVTEDG_RISING (1 << 8) -#define AT91_TC_EEVTEDG_FALLING (2 << 8) -#define AT91_TC_EEVTEDG_BOTH (3 << 8) -#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ -#define AT91_TC_EEVT_TIOB (0 << 10) -#define AT91_TC_EEVT_XC0 (1 << 10) -#define AT91_TC_EEVT_XC1 (2 << 10) -#define AT91_TC_EEVT_XC2 (3 << 10) -#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ -#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ -#define AT91_TC_WAVESEL_UP (0 << 13) -#define AT91_TC_WAVESEL_UP_AUTO (2 << 13) -#define AT91_TC_WAVESEL_UPDOWN (1 << 13) -#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) -#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ -#define AT91_TC_ACPA_NONE (0 << 16) -#define AT91_TC_ACPA_SET (1 << 16) -#define AT91_TC_ACPA_CLEAR (2 << 16) -#define AT91_TC_ACPA_TOGGLE (3 << 16) -#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ -#define AT91_TC_ACPC_NONE (0 << 18) -#define AT91_TC_ACPC_SET (1 << 18) -#define AT91_TC_ACPC_CLEAR (2 << 18) -#define AT91_TC_ACPC_TOGGLE (3 << 18) -#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ -#define AT91_TC_AEEVT_NONE (0 << 20) -#define AT91_TC_AEEVT_SET (1 << 20) -#define AT91_TC_AEEVT_CLEAR (2 << 20) -#define AT91_TC_AEEVT_TOGGLE (3 << 20) -#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ -#define AT91_TC_ASWTRG_NONE (0 << 22) -#define AT91_TC_ASWTRG_SET (1 << 22) -#define AT91_TC_ASWTRG_CLEAR (2 << 22) -#define AT91_TC_ASWTRG_TOGGLE (3 << 22) -#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ -#define AT91_TC_BCPB_NONE (0 << 24) -#define AT91_TC_BCPB_SET (1 << 24) -#define AT91_TC_BCPB_CLEAR (2 << 24) -#define AT91_TC_BCPB_TOGGLE (3 << 24) -#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ -#define AT91_TC_BCPC_NONE (0 << 26) -#define AT91_TC_BCPC_SET (1 << 26) -#define AT91_TC_BCPC_CLEAR (2 << 26) -#define AT91_TC_BCPC_TOGGLE (3 << 26) -#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ -#define AT91_TC_BEEVT_NONE (0 << 28) -#define AT91_TC_BEEVT_SET (1 << 28) -#define AT91_TC_BEEVT_CLEAR (2 << 28) -#define AT91_TC_BEEVT_TOGGLE (3 << 28) -#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ -#define AT91_TC_BSWTRG_NONE (0 << 30) -#define AT91_TC_BSWTRG_SET (1 << 30) -#define AT91_TC_BSWTRG_CLEAR (2 << 30) -#define AT91_TC_BSWTRG_TOGGLE (3 << 30) +#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ +#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ +#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ +#define AT91_TC_EEVTEDG_NONE (0 << 8) +#define AT91_TC_EEVTEDG_RISING (1 << 8) +#define AT91_TC_EEVTEDG_FALLING (2 << 8) +#define AT91_TC_EEVTEDG_BOTH (3 << 8) +#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ +#define AT91_TC_EEVT_TIOB (0 << 10) +#define AT91_TC_EEVT_XC0 (1 << 10) +#define AT91_TC_EEVT_XC1 (2 << 10) +#define AT91_TC_EEVT_XC2 (3 << 10) +#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ +#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ +#define AT91_TC_WAVESEL_UP (0 << 13) +#define AT91_TC_WAVESEL_UP_AUTO (2 << 13) +#define AT91_TC_WAVESEL_UPDOWN (1 << 13) +#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) +#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ +#define AT91_TC_ACPA_NONE (0 << 16) +#define AT91_TC_ACPA_SET (1 << 16) +#define AT91_TC_ACPA_CLEAR (2 << 16) +#define AT91_TC_ACPA_TOGGLE (3 << 16) +#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ +#define AT91_TC_ACPC_NONE (0 << 18) +#define AT91_TC_ACPC_SET (1 << 18) +#define AT91_TC_ACPC_CLEAR (2 << 18) +#define AT91_TC_ACPC_TOGGLE (3 << 18) +#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ +#define AT91_TC_AEEVT_NONE (0 << 20) +#define AT91_TC_AEEVT_SET (1 << 20) +#define AT91_TC_AEEVT_CLEAR (2 << 20) +#define AT91_TC_AEEVT_TOGGLE (3 << 20) +#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ +#define AT91_TC_ASWTRG_NONE (0 << 22) +#define AT91_TC_ASWTRG_SET (1 << 22) +#define AT91_TC_ASWTRG_CLEAR (2 << 22) +#define AT91_TC_ASWTRG_TOGGLE (3 << 22) +#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ +#define AT91_TC_BCPB_NONE (0 << 24) +#define AT91_TC_BCPB_SET (1 << 24) +#define AT91_TC_BCPB_CLEAR (2 << 24) +#define AT91_TC_BCPB_TOGGLE (3 << 24) +#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ +#define AT91_TC_BCPC_NONE (0 << 26) +#define AT91_TC_BCPC_SET (1 << 26) +#define AT91_TC_BCPC_CLEAR (2 << 26) +#define AT91_TC_BCPC_TOGGLE (3 << 26) +#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ +#define AT91_TC_BEEVT_NONE (0 << 28) +#define AT91_TC_BEEVT_SET (1 << 28) +#define AT91_TC_BEEVT_CLEAR (2 << 28) +#define AT91_TC_BEEVT_TOGGLE (3 << 28) +#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ +#define AT91_TC_BSWTRG_NONE (0 << 30) +#define AT91_TC_BSWTRG_SET (1 << 30) +#define AT91_TC_BSWTRG_CLEAR (2 << 30) +#define AT91_TC_BSWTRG_TOGGLE (3 << 30) -#define AT91_TC_CV 0x10 /* Counter Value */ -#define AT91_TC_RA 0x14 /* Register A */ -#define AT91_TC_RB 0x18 /* Register B */ -#define AT91_TC_RC 0x1c /* Register C */ +#define AT91_TC_CV 0x10 /* Counter Value */ +#define AT91_TC_RA 0x14 /* Register A */ +#define AT91_TC_RB 0x18 /* Register B */ +#define AT91_TC_RC 0x1c /* Register C */ -#define AT91_TC_SR 0x20 /* Status Register */ -#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ -#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ -#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ -#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ -#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ -#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ -#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ -#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ -#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ -#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ -#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ +#define AT91_TC_SR 0x20 /* Status Register */ +#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ +#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ +#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ +#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ +#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ +#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ +#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ +#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ +#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ +#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ +#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ -#define AT91_TC_IER 0x24 /* Interrupt Enable Register */ -#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ -#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ +#define AT91_TC_IER 0x24 /* Interrupt Enable Register */ +#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ +#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91sam9260_matrix.h b/bsp/at91sam9260/platform/at91sam9260_matrix.h index be501c1f55..7a59a2054d 100644 --- a/bsp/at91sam9260/platform/at91sam9260_matrix.h +++ b/bsp/at91sam9260/platform/at91sam9260_matrix.h @@ -15,67 +15,67 @@ extern "C" { #endif -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/at91sam926x.h b/bsp/at91sam9260/platform/at91sam926x.h index 00f93ffd17..d8199956a5 100644 --- a/bsp/at91sam9260/platform/at91sam926x.h +++ b/bsp/at91sam9260/platform/at91sam926x.h @@ -33,169 +33,169 @@ extern "C" { /* * Peripheral identifiers/interrupts. */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ +#define AT91SAM9260_ID_US0 6 /* USART 0 */ +#define AT91SAM9260_ID_US1 7 /* USART 1 */ +#define AT91SAM9260_ID_US2 8 /* USART 2 */ +#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ +#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9260_ID_UHP 20 /* USB Host port */ +#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ +#define AT91SAM9260_ID_US3 23 /* USART 3 */ +#define AT91SAM9260_ID_US4 24 /* USART 4 */ +#define AT91SAM9260_ID_US5 25 /* USART 5 */ +#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ +#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ +#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ +#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ /* * User Peripheral physical base addresses. */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 -#define AT91SAM9260_BASE_DBGU 0xfffff200 +#define AT91SAM9260_BASE_TCB0 0xfffa0000 +#define AT91SAM9260_BASE_TC0 0xfffa0000 +#define AT91SAM9260_BASE_TC1 0xfffa0040 +#define AT91SAM9260_BASE_TC2 0xfffa0080 +#define AT91SAM9260_BASE_UDP 0xfffa4000 +#define AT91SAM9260_BASE_MCI 0xfffa8000 +#define AT91SAM9260_BASE_TWI 0xfffac000 +#define AT91SAM9260_BASE_US0 0xfffb0000 +#define AT91SAM9260_BASE_US1 0xfffb4000 +#define AT91SAM9260_BASE_US2 0xfffb8000 +#define AT91SAM9260_BASE_SSC 0xfffbc000 +#define AT91SAM9260_BASE_ISI 0xfffc0000 +#define AT91SAM9260_BASE_EMAC 0xfffc4000 +#define AT91SAM9260_BASE_SPI0 0xfffc8000 +#define AT91SAM9260_BASE_SPI1 0xfffcc000 +#define AT91SAM9260_BASE_US3 0xfffd0000 +#define AT91SAM9260_BASE_US4 0xfffd4000 +#define AT91SAM9260_BASE_US5 0xfffd8000 +#define AT91SAM9260_BASE_TCB1 0xfffdc000 +#define AT91SAM9260_BASE_TC3 0xfffdc000 +#define AT91SAM9260_BASE_TC4 0xfffdc040 +#define AT91SAM9260_BASE_TC5 0xfffdc080 +#define AT91SAM9260_BASE_ADC 0xfffe0000 +#define AT91_BASE_SYS 0xffffe800 +#define AT91SAM9260_BASE_DBGU 0xfffff200 /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) /* * Internal Memory. */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ +#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ +#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ +#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ +#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ -#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ -#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ +#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ +#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ /* Serial ports */ -#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ +#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ /* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 +#define AT91_CHIPSELECT_0 0x10000000 +#define AT91_CHIPSELECT_1 0x20000000 +#define AT91_CHIPSELECT_2 0x30000000 +#define AT91_CHIPSELECT_3 0x40000000 +#define AT91_CHIPSELECT_4 0x50000000 +#define AT91_CHIPSELECT_5 0x60000000 +#define AT91_CHIPSELECT_6 0x70000000 +#define AT91_CHIPSELECT_7 0x80000000 /* SDRAM */ -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 /* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) diff --git a/bsp/at91sam9260/platform/gpio.h b/bsp/at91sam9260/platform/gpio.h index 4634ed78ae..52f34453d7 100644 --- a/bsp/at91sam9260/platform/gpio.h +++ b/bsp/at91sam9260/platform/gpio.h @@ -14,117 +14,117 @@ #include <rtthread.h> #include <at91_aic.h> -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 3 +#define MAX_GPIO_BANKS 3 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 21aa17e7c6..7c40ffbdad 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -175,7 +175,7 @@ static void at91_gpio_irq_init() rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].counter = 0; #endif - idx++; + idx++; } rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); @@ -308,7 +308,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -322,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -400,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; + int irq; - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include <finsh.h> diff --git a/bsp/at91sam9260/platform/io.h b/bsp/at91sam9260/platform/io.h index 8252d185ba..3e41feee90 100644 --- a/bsp/at91sam9260/platform/io.h +++ b/bsp/at91sam9260/platform/io.h @@ -11,31 +11,31 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define AT91_BASE_SYS 0xffffe800 +#define AT91_BASE_SYS 0xffffe800 -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) rt_inline unsigned int at91_sys_read(unsigned int reg_offset) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - return readl(addr + reg_offset); + return readl(addr + reg_offset); } rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - writel(value, addr + reg_offset); + writel(value, addr + reg_offset); } diff --git a/bsp/at91sam9260/platform/irq.h b/bsp/at91sam9260/platform/irq.h index 339ec1f766..76d4200d3b 100644 --- a/bsp/at91sam9260/platform/irq.h +++ b/bsp/at91sam9260/platform/irq.h @@ -7,7 +7,7 @@ * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -18,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/reset.c b/bsp/at91sam9260/platform/reset.c index b793b9589d..4b5462a9e1 100644 --- a/bsp/at91sam9260/platform/reset.c +++ b/bsp/at91sam9260/platform/reset.c @@ -19,12 +19,12 @@ void machine_reset(void) { - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } void machine_shutdown(void) { - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); } #ifdef RT_USING_FINSH @@ -35,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9260/platform/rt_low_level_init.c b/bsp/at91sam9260/platform/rt_low_level_init.c index 4af18b0eee..31ddf27ae6 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.c +++ b/bsp/at91sam9260/platform/rt_low_level_init.c @@ -7,9 +7,9 @@ * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91_RSTC_PROCRST (1 << 0) #define AT91_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9260/platform/rt_low_level_init.h b/bsp/at91sam9260/platform/rt_low_level_init.h index 93a1fade4c..c79adf5284 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.h +++ b/bsp/at91sam9260/platform/rt_low_level_init.h @@ -9,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9260/platform/system_clock.c b/bsp/at91sam9260/platform/system_clock.c index f59aba016c..a8f866fdd6 100644 --- a/bsp/at91sam9260/platform/system_clock.c +++ b/bsp/at91sam9260/platform/system_clock.c @@ -14,270 +14,270 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t rate; + rt_uint32_t flags; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } /* PLLB generated USB full speed clock init */ static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_sys_write(AT91_CKGR_PLLBR, 0); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } - return RT_NULL; + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; + + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + at91_pllb_usbfs_clock_init(main_clock); - at91_pllb_usbfs_clock_init(main_clock); + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - return 0; + return 0; } /** @@ -285,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(18432000); + at91_clock_init(18432000); } |