Merge pull request #1515 from TanekLiang/ch802-fpga

[bsp] add ck802 bsp support

13 files changed, 1578 insertions, 0 deletions

diff --git a/bsp/ck802/drivers/SConscript b/bsp/ck802/drivers/SConscript
new file mode 100644
index 0000000000..11acddcea6
--- /dev/null
+++ b/bsp/ck802/drivers/SConscript
@@ -0,0 +1,14 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drivers.
+src = Glob("*.c") + Glob("*.cpp")
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/ck802/drivers/board.c b/bsp/ck802/drivers/board.c
new file mode 100644
index 0000000000..55f0e47331
--- /dev/null
+++ b/bsp/ck802/drivers/board.c
@@ -0,0 +1,60 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-08-10     Urey         first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "csi_core.h"
+#include "pinmux.h"
+
+extern int __bss_end__;
+#define SYS_HEAP_BEGIN    (&__bss_end__)
+
+#include "core_ck802.h"
+
+/**
+ * This function will initial CK802 board.
+ */
+void rt_hw_board_init(void)
+{
+    phobos_ioreuse_initial();
+
+    /* NVIC Configuration */
+    drv_nvic_init(2);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)CK802_IRAM_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/ck802/drivers/board.h b/bsp/ck802/drivers/board.h
new file mode 100644
index 0000000000..9c404a29c7
--- /dev/null
+++ b/bsp/ck802/drivers/board.h
@@ -0,0 +1,32 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-08-10     Urey         first implementation
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define APB_DEFAULT_FREQ        20000000   /* Hz */
+#define CK802_IRAM_SIZE         94
+#define CK802_IRAM_END          (0x20000000 + CK802_IRAM_SIZE * 1024)
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/ck802/drivers/board_coretimer.c b/bsp/ck802/drivers/board_coretimer.c
new file mode 100644
index 0000000000..d3275e68d8
--- /dev/null
+++ b/bsp/ck802/drivers/board_coretimer.c
@@ -0,0 +1,81 @@
+/*
+ * File      : board_coretimer.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-01-01     Urey      first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "board_coretimer.h"
+
+#include <stdint.h>
+
+static inline unsigned int readreg32(volatile unsigned int *addr)
+{
+    return *(volatile unsigned int *)addr;
+}
+
+static inline void writereg32(unsigned int b, volatile unsigned int *addr)
+{
+    *(volatile unsigned int *)addr = b;
+}
+
+void CKTimerInit(uint32_t timer_id, uint32_t freq)
+{
+    uint32_t reg;
+
+    writereg32(APB_DEFAULT_FREQ / freq, CORET_RVR);
+    writereg32(0, CORET_CVR);
+
+    reg = readreg32(CORET_CSR);
+    reg |= CORETIM_TXCONTROL_ENABLE;
+    reg |= CORETIM_TXCONTROL_INTMASK;
+    writereg32(reg, CORET_CSR);
+
+    return;
+}
+
+void CKTimerClear(uint32_t timer_id)
+{
+    uint32_t reg;
+
+    reg = readreg32(CORET_CSR);
+    reg |= ~CORETIM_TXCONTROL_MODE;
+    writereg32(reg, CORET_CSR);
+}
+
+uint32_t CKTimer_CurrentValue(void)
+{
+    return readreg32(CORET_CVR);
+}
+
+void __attribute__((isr)) SysTick_Handler(void)
+{
+    CKTimerClear(0x1);
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
diff --git a/bsp/ck802/drivers/board_coretimer.h b/bsp/ck802/drivers/board_coretimer.h
new file mode 100644
index 0000000000..e911c8e838
--- /dev/null
+++ b/bsp/ck802/drivers/board_coretimer.h
@@ -0,0 +1,52 @@
+/*
+ * File      : board_coretimer.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-01-01     Urey      first version
+ */
+#ifndef _BOARD_CORETIMER_H_
+#define _BOARD_CORETIMER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define CK_TIMER_BASE     (0xE000E000)
+
+#define CORET_CSR         (volatile unsigned int *)(CK_TIMER_BASE + 0x10)
+#define CORET_RVR         (volatile unsigned int *)(CK_TIMER_BASE + 0x14)
+#define CORET_CVR         (volatile unsigned int *)(CK_TIMER_BASE + 0x18)
+#define CORET_CALIB       (volatile unsigned int *)(CK_TIMER_BASE + 0x1c)
+
+/*
+ *  define the bits for TxControl
+ */
+#define CORETIM_TXCONTROL_ENABLE      (1UL << 0)
+#define CORETIM_TXCONTROL_INTMASK     (1UL << 1)
+#define CORETIM_TXCONTROL_MODE        (1UL << 16)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BOARD_CORETIMER_H_ */
diff --git a/bsp/ck802/drivers/board_uart.c b/bsp/ck802/drivers/board_uart.c
new file mode 100644
index 0000000000..5dd7018f56
--- /dev/null
+++ b/bsp/ck802/drivers/board_uart.c
@@ -0,0 +1,273 @@
+/*
+ * File      : board_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-23     Urey         first implementation
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_CONSOLE
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "board.h"
+#include "soc.h"
+#include "dw_usart.h"
+#include "drv_usart.h"
+#include "pin_name.h"
+#include "pinmux.h"
+
+#if CONFIG_USART
+struct
+{
+    uint32_t base;
+    uint32_t irq;
+} const sg_usart_config[CONFIG_USART_NUM] =
+{
+    { CSKY_UART0_BASE, UART0_IRQn },
+    { CSKY_UART1_BASE, UART1_IRQn },
+    { CSKY_UART2_BASE, UART2_IRQn },
+    { CSKY_UART3_BASE, UART3_IRQn }
+};
+
+typedef struct
+{
+    pin_t    tx;
+    pin_t    rx;
+    uint16_t cfg_idx;    //idx of sg_usart_config[]
+    uint16_t function;
+} usart_pin_map_t;
+const static usart_pin_map_t s_usart_pin_map[] =
+{
+    {
+        PA0_TXD0_PWM0_XX_SIROUT0,
+        PA1_RXD0_PWM1_XX_SIRIN0,
+        0,
+        0
+    },
+    {
+        PA10_TXD1_PWM1_XX_SIROUT1,
+        PA11_RXD1_PWM2_XX_SIRIN1,
+        1,
+        0
+    },
+    {
+        PA23_TXD2_PWM5_XX_SIROUT2,
+        PA22_RXD2_PWM4_XX_SIRIN2,
+        2,
+        0
+    },
+    {
+        PA26_TXD3_PWMFAULT_XX_SIROUT3,
+        PA27_RXD3_PWM0_XX_SIRIN3,
+        3,
+        0
+    }
+};
+
+int32_t target_usart_init(pin_t tx, pin_t rx, uint32_t *base, uint32_t *irq)
+{
+    uint32_t idx;
+
+    for (idx = 0; idx < sizeof(s_usart_pin_map) / sizeof(usart_pin_map_t); idx++)
+    {
+        if (s_usart_pin_map[idx].tx == tx && s_usart_pin_map[idx].rx == rx)
+        {
+            *base = sg_usart_config[s_usart_pin_map[idx].cfg_idx].base;
+            *irq = sg_usart_config[s_usart_pin_map[idx].cfg_idx].irq;
+
+            /*pinmux*/
+            pin_mux(s_usart_pin_map[idx].tx, s_usart_pin_map[idx].function);
+            pin_mux(s_usart_pin_map[idx].rx, s_usart_pin_map[idx].function);
+            return s_usart_pin_map[idx].cfg_idx;
+        }
+    }
+    return -1;
+}
+#endif
+
+#ifdef RT_USING_UART1
+#define UART_TXD1     PA10_TXD1_PWM1_XX_SIROUT1
+#define UART_RXD1     PA11_RXD1_PWM2_XX_SIRIN1
+
+static  usart_handle_t uart1_handle;
+static struct rt_serial_device  serial1;
+/*
+static void usart1_event_cb(uint32_t event, void *cb_arg)
+{
+    switch (event)
+    {
+    case USART_EVENT_SEND_COMPLETE:
+        rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_TX_DONE);
+        break;
+
+    case USART_EVENT_RECEIVED:
+        rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+        break;
+
+    default:
+        break;
+    }
+}
+*/
+
+__attribute__((isr)) void USART1_IRQHandler(void)
+{
+    rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+}
+#endif
+
+/*
+ * UART interface
+ */
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int ret;
+    usart_handle_t uart;
+
+    uint32_t bauds;
+    usart_mode_e mode;
+    usart_parity_e parity;
+    usart_stop_bits_e stopbits;
+    usart_data_bits_e databits;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    /* set baudrate parity...*/
+    bauds = cfg->baud_rate;
+    mode = USART_MODE_ASYNCHRONOUS;
+
+    if (cfg->parity == PARITY_EVEN)
+        parity = USART_PARITY_EVEN;
+    else if (cfg->parity == PARITY_ODD)
+        parity = USART_PARITY_ODD;
+    else
+        parity = USART_PARITY_NONE;
+
+    stopbits = USART_STOP_BITS_1 ;
+    databits = USART_DATA_BITS_8;
+
+    ret = csi_usart_config(uart, SYSTEM_CLOCK, bauds, USART_MODE_ASYNCHRONOUS, parity, stopbits, databits);
+
+    if (ret < 0)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        dw_usart_clr_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable the UART Interrupt */
+        dw_usart_set_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    dw_usart_putchar(uart,c);
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    uint8_t ch;
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    if (!dw_usart_getchar_no_poll(uart, &ch))
+    {
+        return (int)(ch);
+    }
+    else
+    {
+        return -1;
+    }
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+
+int rt_hw_usart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART1
+    serial1.ops                 = & _uart_ops;
+    serial1.config              = config;
+    serial1.config.bufsz        = 2048;
+    serial1.config.baud_rate    = 115200;
+
+    uart1_handle = csi_usart_initialize(UART_TXD1, UART_RXD1, NULL/*usart1_event_cb*/,
+                                        (void *) 0);
+
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart1_handle);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif
diff --git a/bsp/ck802/drivers/config.h b/bsp/ck802/drivers/config.h
new file mode 100644
index 0000000000..e02d3204f9
--- /dev/null
+++ b/bsp/ck802/drivers/config.h
@@ -0,0 +1,44 @@
+/* config.h -- Autogenerated! Do not edit. */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_KERNEL_NONE 1
+//#define CONFIG_AES 1
+//#define CONFIG_SPI 1
+//#define CONFIG_SPI_DMA 1
+//#define CONFIG_DMAC 1
+//#define CONFIG_GPIO 1
+//#define CONFIG_IIC 1
+//#define CONFIG_SHA 1
+//#define CONFIG_RSA 1
+//#define CONFIG_TIMER 1
+#define CONFIG_USART 1
+//#define CONFIG_TRNG 1
+//#define CONFIG_CRC 1
+//#define CONFIG_EFLASH 1
+//#define CONFIG_WDT 1
+//#define CONFIG_RTC 1
+//#define CONFIG_PWM 1
+//#define CONFIG_TEST 1
+//#define CONFIG_ETH 1
+//#define CONFIG_TEST_DRIVER 1
+//#define CONFIG_TEST_AES 1
+//#define CONFIG_TEST_ETH 1
+//#define CONFIG_TEST_DMAC 1
+//#define CONFIG_TEST_GPIO 1
+//#define CONFIG_TEST_IIC 1
+//#define CONFIG_TEST_SHA 1
+//#define CONFIG_TEST_RSA 1
+//#define CONFIG_TEST_TIMER 1
+//#define CONFIG_TEST_USART 1
+//#define CONFIG_TEST_TRNG 1
+//#define CONFIG_TEST_CRC 1
+//#define CONFIG_TEST_EFLASH 1
+//#define CONFIG_TEST_SPI 1
+//#define CONFIG_TEST_WDT 1
+//#define CONFIG_TEST_RTC 1
+//#define CONFIG_TEST_PWM 1
+
+#endif /* __CONFIG_H */
+
diff --git a/bsp/ck802/drivers/isr.c b/bsp/ck802/drivers/isr.c
new file mode 100644
index 0000000000..c8c3f909d0
--- /dev/null
+++ b/bsp/ck802/drivers/isr.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     isr.c
+ * @brief    source file for the interrupt server route
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <drv_common.h>
+#include "config.h"
+#include "soc.h"
+
+extern void dw_usart_irqhandler(int32_t idx);
+extern void dw_timer_irqhandler(int32_t idx);
+extern void dw_gpio_irqhandler(int32_t idx);
+extern void dw_iic_irqhandler(int32_t idx);
+extern void ck_rtc_irqhandler(int32_t idx);
+extern void dw_spi_irqhandler(int32_t idx);
+extern void dw_wdt_irqhandler(int32_t idx);
+extern void ck_dma_irqhandler(int32_t idx);
+extern void ck_aes_irqhandler(int32_t idx);
+extern void ck_sha_irqhandler(int32_t idx);
+#ifdef CONFIG_KERNEL_FREERTOS
+extern void CKTimer1Isr(void);
+extern void CKPendSVIsr(void);
+#endif
+
+#define readl(addr) \
+    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+__attribute__((isr)) void CORET_IRQHandler(void)
+{
+    readl(0xE000E010);
+}
+
+#if defined(CONFIG_USART)
+/*
+__attribute__((isr)) void USART0_IRQHandler(void)
+{
+    dw_usart_irqhandler(0);
+}
+
+
+__attribute__((isr)) void USART1_IRQHandler(void)
+{
+    dw_usart_irqhandler(1);
+}
+
+
+__attribute__((isr)) void USART2_IRQHandler(void)
+{
+    dw_usart_irqhandler(2);
+}
+
+__attribute__((isr)) void USART3_IRQHandler(void)
+{
+    dw_usart_irqhandler(3);
+}
+*/
+#endif
+
+#if defined(CONFIG_TIMER)
+__attribute__((isr)) void TIMA0_IRQHandler(void)
+{
+    dw_timer_irqhandler(0);
+}
+
+__attribute__((isr)) void TIMA1_IRQHandler(void)
+{
+    dw_timer_irqhandler(1);
+}
+__attribute__((isr)) void TIMB0_IRQHandler(void)
+{
+    dw_timer_irqhandler(2);
+}
+
+__attribute__((isr)) void TIMB1_IRQHandler(void)
+{
+    dw_timer_irqhandler(3);
+}
+
+#endif
+
+#if defined(CONFIG_GPIO)
+
+__attribute__((isr)) void GPIOA_IRQHandler(void)
+{
+    dw_gpio_irqhandler(0);
+}
+
+__attribute__((isr)) void GPIOB_IRQHandler(void)
+{
+    dw_gpio_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_IIC)
+__attribute__((isr)) void I2C0_IRQHandler(void)
+{
+    dw_iic_irqhandler(0);
+}
+
+__attribute__((isr)) void I2C1_IRQHandler(void)
+{
+    dw_iic_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_RTC)
+
+__attribute__((isr)) void RTC_IRQHandler(void)
+{
+    ck_rtc_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_AES)
+
+__attribute__((isr)) void AES_IRQHandler(void)
+{
+    ck_aes_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_SHA)
+
+__attribute__((isr)) void SHA_IRQHandler(void)
+{
+    ck_sha_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_SPI) && defined(CONFIG_GPIO)
+__attribute__((isr)) void SPI0_IRQHandler(void)
+{
+    dw_spi_irqhandler(0);
+}
+
+__attribute__((isr)) void SPI1_IRQHandler(void)
+{
+    dw_spi_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_WDT)
+__attribute__((isr)) void WDT_IRQHandler(void)
+{
+    dw_wdt_irqhandler(0);
+}
+#endif
+
+#if defined(CONFIG_DMAC)
+__attribute__((isr)) void DMAC_IRQHandler(void)
+{
+    ck_dma_irqhandler(0);
+}
+#endif
diff --git a/bsp/ck802/drivers/pin_name.h b/bsp/ck802/drivers/pin_name.h
new file mode 100644
index 0000000000..73141f0865
--- /dev/null
+++ b/bsp/ck802/drivers/pin_name.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pn_name.h
+ * @brief    header file for the pin_name
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _PINNAMES_H
+#define _PINNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    PA0_TXD0_PWM0_XX_SIROUT0 = 0,
+    PA1_RXD0_PWM1_XX_SIRIN0,
+    PA2_CTS0_PWM2_SPI0CLK_XX,
+    PA3_RTS0_PWM3_SPI0TX_XX,
+    PA4_SCL0_PWM4_SPI0RX_XX,
+    PA5_SDA0_PWM5_SPI0CS_XX,
+    PA6_SPI0CLK_PWMTRIG0_SCL0_XX,
+    PA7_SPI0TX_PWMTRIG1_SDA0_XX,
+    PA8_SPI0RX_TRIGFAULT_SCL1_XX,
+    PA9_SPI0CS_PWM0_SDA1_XX,
+    PA10_TXD1_PWM1_XX_SIROUT1,
+    PA11_RXD1_PWM2_XX_SIRIN1,
+    PA12_CTS1_PWM3_SPI1CLK_XX,
+    PA13_RTS1_PWM4_SPI1TX_XX,
+    PA14_SCL1_PWM5_SPI1RX_XX,
+    PA15_SDA1_PWMTRIG0_SPI1CS0_XX,
+    PA16_SPI1CLK_PWMTRIG1_XX_XX,
+    PA17_SPI1TX_PWMFAULT_XX_XX,
+    PA18_SPI1RX_PWM0_XX_XX,
+    PA19_SPI1CS0_PWM1_XX_XX,
+    PA20_SPI1CS1_PWM2_XX_XX,
+    PA21_SPI1CS2_PWM3_XX_XX,
+    PA22_RXD2_PWM4_XX_SIRIN2,
+    PA23_TXD2_PWM5_XX_SIROUT2,
+    PA24_CTS2_PWMTRIG0_SPI1CS1_XX,
+    PA25_XX_PWMTRIG1_SPI1CS2_XX,
+    PA26_TXD3_PWMFAULT_XX_SIROUT3,
+    PA27_RXD3_PWM0_XX_SIRIN3,
+    PA28_I2SMCLK_PWM1_XX_XX,
+    PA29_I2SSCLK_PWM2_XX_XX,
+    PA30_I2SWSCLK_PWM3_XX_XX,
+    PA31_I2SSDA__SCL0_PWM4_XX,
+    PB0_ADC0_SDA0_PWM5_XX,
+    PB1_ADC1_SCL1_USISCLK_XX,
+    PB2_ADC2_SDA1_USISD0_XX,
+    PB3_ADC3_SPI1CLK_USISD1_XX,
+    PB4_ADC4_SPI1TX_USINSS_XX,
+    PB5_ADC5_SPI1RX_USISCLK_XX,
+    PB6_ADC6_SPI1CS0_USISD0_XX,
+    PB7_ADC7_SPI1CS1_USISD1_XX,
+    PB8_PWMTRIG0_SPI1CS2_USINSS_XX,
+    PB9_PWMTRIG1_CTS3_XX_XX,
+    PB10_PWMFAULT_RTS3_XX_XX
+}
+pin_name_t;
+
+typedef enum
+{
+    PORTA = 0,
+    PORTB = 1
+} port_name_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/ck802/drivers/pinmux.c b/bsp/ck802/drivers/pinmux.c
new file mode 100644
index 0000000000..5990285ed0
--- /dev/null
+++ b/bsp/ck802/drivers/pinmux.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pinmux.c
+ * @brief    source file for the pinmux
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <stdint.h>
+#include "pinmux.h"
+#include "pin_name.h"
+
+#define readl(addr) \
+    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/*******************************************************************************
+ * function: phobos_ioreuse_inital
+ *
+ * description:
+ *   initial phobos_pinmux
+ *******************************************************************************/
+
+void phobos_ioreuse_initial(void)
+{
+    unsigned int value;
+
+    /* gpio data source select */
+    value = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    value |= GPIO0_REUSE_EN;
+    writel(value, PHOBOS_GIPO0_PORTCTL_REG);
+
+    value = readl(PHOBOS_GIPO1_PORTCTL_REG);
+    value |= GPIO1_REUSE_EN;
+    writel(value, PHOBOS_GIPO1_PORTCTL_REG);
+
+    /* reuse function select */
+    value = readl(PHOBOS_IOMUX0L_REG);
+    value |= IOMUX0L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0L_REG);
+
+    value = readl(PHOBOS_IOMUX0H_REG);
+    value |= IOMUX1L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0H_REG);
+
+    value = readl(PHOBOS_IOMUX1L_REG);
+    value |= IOMUX1L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX1L_REG);
+}
+
+void phobos_pwm_ioreuse(void)
+{
+    unsigned int value;
+
+    /* gpio data source select */
+    value = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    value |= PWM_GPIO0_REUSE_EN;
+    writel(value, PHOBOS_GIPO0_PORTCTL_REG);
+
+    /* reuse function select */
+    value = readl(PHOBOS_IOMUX0L_REG);
+    value |= PWM_IOMUX0L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0L_REG);
+}
+
+
+int32_t pin_mux(pin_name_t pin, uint16_t function)
+{
+    unsigned int val = 0;
+    unsigned int reg_val = 0;
+
+    uint8_t offset;
+
+    if (function > 3)
+    {
+        if (pin < PB0_ADC0_SDA0_PWM5_XX)
+        {
+            offset = pin;
+            /* gpio data source select */
+            val = readl(PHOBOS_GIPO0_PORTCTL_REG);
+            val &= ~(1 << offset);
+            writel(val, PHOBOS_GIPO0_PORTCTL_REG);
+            return 0;
+        }
+        else if (pin >= PB0_ADC0_SDA0_PWM5_XX)
+        {
+            offset = pin - 32;
+            /* gpio data source select */
+            val = readl(PHOBOS_GIPO1_PORTCTL_REG);
+            val &= ~(1 << offset);
+            writel(val, PHOBOS_GIPO1_PORTCTL_REG);
+            return 0;
+        }
+        else
+        {
+            return -1;
+        }
+    }
+
+    if (pin >= PB0_ADC0_SDA0_PWM5_XX)
+    {
+        offset = pin - 32;
+
+        /* gpio data source select */
+        val = readl(PHOBOS_GIPO1_PORTCTL_REG);
+        val |= (1 << offset);
+        writel(val, PHOBOS_GIPO1_PORTCTL_REG);
+
+        reg_val = (0x3 << (offset * 2));
+        /* reuse function select */
+        val = readl(PHOBOS_IOMUX1L_REG);
+        val &= ~(reg_val);
+        val |= (function << (2 * offset));
+        writel(val, PHOBOS_IOMUX1L_REG);
+        return 0;
+    }
+
+    offset = pin;
+    /* gpio data source select */
+    val = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    val |= (1 << offset);
+    writel(val, PHOBOS_GIPO0_PORTCTL_REG);
+
+    if (pin >= PA16_SPI1CLK_PWMTRIG1_XX_XX)
+    {
+        offset = pin - 16;
+        reg_val = (0x3 << (offset * 2));
+        /* reuse function select */
+        val = readl(PHOBOS_IOMUX0H_REG);
+        val &= ~(reg_val);
+        val |= (function << (2 * offset));
+        writel(val, PHOBOS_IOMUX0H_REG);
+        return 0;
+    }
+
+    reg_val = (0x3 << (offset * 2));
+    /* reuse function select */
+    val = readl(PHOBOS_IOMUX0L_REG);
+    val &= ~(reg_val);
+    val |= (function << (2 * offset));
+    writel(val, PHOBOS_IOMUX0L_REG);
+    return 0;
+}
diff --git a/bsp/ck802/drivers/pinmux.h b/bsp/ck802/drivers/pinmux.h
new file mode 100644
index 0000000000..e299c9a8fb
--- /dev/null
+++ b/bsp/ck802/drivers/pinmux.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pinmux.h
+ * @brief    Header file for the pinmux
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef PHOBOS_PINMUX_H
+#define PHOBOS_PINMUX_H
+
+#include <stdint.h>
+#include "pin_name.h"
+
+void phobos_ioreuse_initial(void);
+int32_t pin_mux(pin_name_t pin, uint16_t function);
+
+/* IOMUX0L function definition */
+#define PA0_UART0_TX      0x00000000
+#define PA0_PWM_CH0       0x00000001
+#define PA0_UART0_SIROUT  0x00000003
+#define PA1_UART0_RX      0x00000000
+#define PA1_PWM_CH1       0x00000004
+#define PA1_UART0_SIRIN   0x0000000C
+#define PA2_UART0_CTS     0x00000000
+#define PA2_PWM_CH2       0x00000010
+#define PA2_SPI0_CLK      0x00000020
+#define PA3_UART0_TRS     0x00000000
+#define PA3_PWM_CH3       0x00000040
+#define PA3_SPI0_TX       0x00000080
+#define PA4_I2C0_SCL      0x00000000
+#define PA4_PWM_CH4       0x00000100
+#define PA4_SPI0_RX       0x00000200
+#define PA5_I2C0_SDA      0x00000000
+#define PA5_PWM_CH5       0x00000400
+#define PA5_SPI0_CS       0x00000800
+#define PA6_SPI0_CLK      0x00000000
+#define PA6_ETB_TRIG0     0x00001000
+#define PA6_I2C0_SCL      0x00002000
+#define PA7_SPI_TX        0x00000000
+#define PA7_ETB_TRIG1     0x00004000
+#define PA7_I2C0_SDA      0x00008000
+#define PA8_SPI0_TX       0x00000000
+#define PA8_PWM_FAULT     0x00010000
+#define PA8_I2C1_SCL      0x00020000
+#define PA9_SPI0_CS       0x00000000
+#define PA9_PWM_CH0       0x00040000
+#define PA9_I2C1_SDA      0x00080000
+#define PA10_UART1_TX     0x00000000
+#define PA10_PWM_CH1      0x00100000
+#define PA10_UART1_SIROUT 0x00300000
+#define PA11_UART1_RX     0x00000000
+#define PA11_PWM_CH2      0x00400000
+#define PA11_UART1_SIRIN  0x00C00000
+#define PA12_UART1_CTS    0x00000000
+#define PA12_PWM_CH3      0x01000000
+#define PA12_SPI1_CLK     0x02000000
+#define PA13_UART1_RTS    0x00000000
+#define PA13_PWM_CH4      0x04000000
+#define PA13_SPI1_TX      0x08000000
+#define PA14_I2C1_SCL     0x00000000
+#define PA14_PWM_CH5      0x10000000
+#define PA14_SPI1_RX      0x20000000
+#define PA15_I2C1_SDA     0x00000000
+#define PA15_ETB_TRIG0    0x40000000
+#define PA15_SPI1_CS0     0x80000000
+
+/* IOMUX0H function definition */
+#define PA16_SPI1_CLK     0x00000000
+#define PA16_ETB_TRIG1    0x00000001
+#define PA17_SPI1_TX      0x00000000
+#define PA17_PWM_FAULT    0x00000004
+#define PA18_SPI1_RX      0x00000000
+#define PA18_PWM_CH0      0x00000010
+#define PA19_SPI1_CS0     0x00000000
+#define PA19_PWM_CH1      0x00000040
+#define PA20_UART2_RX     0x00000000
+#define PA20_PWM_CH2      0x00000100
+#define PA21_SPI1_CS2     0x00000000
+#define PA21_PWM_CH3      0x00000400
+#define PA22_UART2_RX     0x00000000
+#define PA22_PWM_CH4      0x00001000
+#define PA22_UART2_SIRI   0x00003000
+#define PA23_UART2_TX     0x00000000
+#define PA23_PWM_CH5      0x00004000
+#define PA23_UART2_SIROUT 0x0000C000
+#define PA24_UART2_CTS    0x00000000
+#define PA24_ETB_TRIG0    0x00010000
+#define PA24_SPI1_CS1     0x00020000
+#define PA25_UART2_RTS    0x00000000
+#define PA25_ETB_TRIG1    0x00040000
+#define PA25_SPI1_CS2     0x00080000
+#define PA26_UART3_TX     0x00000000
+#define PA26_PWM_FAULT    0x00100000
+#define PA26_UART3_SIROUT 0x00300000
+#define PA27_UART3_RX     0x00000000
+#define PA27_PWM_CH0      0x00400000
+#define PA27_UART3_SIRIN  0x00C00000
+#define PA28_I2S_MCLK     0x00000000
+#define PA28_PWM_CH1      0x01000000
+#define PA29_I2S_SCLK     0x00000000
+#define PA29_PWM_CH2      0x04000000
+#define PA30_I2S_WSCLK    0x00000000
+#define PA30_PWM_CH3      0x10000000
+#define PA31_I2S_SDA      0x00000000
+#define PA31_I2C0_SCL     0x40000000
+#define PA31_PWM_CH4      0x80000000
+
+/* IOMUX1L function definition */
+#define PB0_ADC0       0x00000000
+#define PB0_I2C0_SDA   0x00000001
+#define PB0_PWM_CH5    0x00000002
+#define PB1_ADC1       0x00000000
+#define PB1_I2C1_SCL   0x00000004
+#define PB1_USI_SCLK   0x00000008
+#define PB2_ADC2       0x00000000
+#define PB2_I2C1_SDA   0x00000010
+#define PB2_USI_SD0    0x00000020
+#define PB3_ADC3       0x00000000
+#define PB3_SPI1_CLK   0x00000040
+#define PB3_USI_SD1    0x00000080
+#define PB4_ADC4       0x00000000
+#define PB4_SPI1_TX    0x00000100
+#define PB4_USI_NSS    0x00000200
+#define PB5_ADC5       0x00000000
+#define PB5_SPI1_RX    0x00000400
+#define PB5_USI_SCLK   0x00000800
+#define PB6_ADC6       0x00000000
+#define PB6_SPI1_CS0   0x00001000
+#define PB6_USI_SD0    0x00002000
+#define PB7_ADC7       0x00000000
+#define PB7_SPI1_CS1   0x00004000
+#define PB7_USI_SD1    0x00008000
+#define PB8_ETB_TRIG0  0x00000000
+#define PB8_SPI1_CS2   0x00010000
+#define PB8_USI_NSS    0x00020000
+#define PB9_ETB_TRIG1  0x00000000
+#define PB9_UART3_CTS  0x00040000
+#define PB10_PWM_FAULT 0x00000000
+#define PB10_UART3_RTS 0x00100000
+
+
+/* flag as identification */
+#define GPIO_SET_BIT0  0x00000001
+#define GPIO_SET_BIT1  0x00000002
+#define GPIO_SET_BIT2  0x00000004
+#define GPIO_SET_BIT3  0x00000008
+#define GPIO_SET_BIT4  0x00000010
+#define GPIO_SET_BIT5  0x00000020
+#define GPIO_SET_BIT6  0x00000040
+#define GPIO_SET_BIT7  0x00000080
+#define GPIO_SET_BIT8  0x00000100
+#define GPIO_SET_BIT9  0x00000200
+#define GPIO_SET_BIT10 0x00000400
+#define GPIO_SET_BIT11 0x00000800
+#define GPIO_SET_BIT12 0x00001000
+#define GPIO_SET_BIT13 0x00002000
+#define GPIO_SET_BIT14 0x00004000
+#define GPIO_SET_BIT15 0x00008000
+#define GPIO_SET_BIT16 0x00010000
+#define GPIO_SET_BIT17 0x00020000
+#define GPIO_SET_BIT18 0x00040000
+#define GPIO_SET_BIT19 0x00080000
+#define GPIO_SET_BIT20 0x00100000
+#define GPIO_SET_BIT21 0x00200000
+#define GPIO_SET_BIT22 0x00400000
+#define GPIO_SET_BIT23 0x00800000
+#define GPIO_SET_BIT24 0x01000000
+#define GPIO_SET_BIT25 0x02000000
+#define GPIO_SET_BIT26 0x04000000
+#define GPIO_SET_BIT27 0x08000000
+#define GPIO_SET_BIT28 0x10000000
+#define GPIO_SET_BIT29 0x20000000
+#define GPIO_SET_BIT30 0x40000000
+#define GPIO_SET_BIT31 0x80000000
+
+/******************************************************************************
+ * phobos gpio control and gpio reuse function
+ * selecting regester adddress
+ ******************************************************************************/
+
+#define PHOBOS_GIPO0_PORTCTL_REG 0x50018008
+#define PHOBOS_GIPO1_PORTCTL_REG 0x60018008
+#define PHOBOS_IOMUX0L_REG       0x50018100
+#define PHOBOS_IOMUX0H_REG       0x50018104
+#define PHOBOS_IOMUX1L_REG       0x50018108
+
+/*************basic gpio reuse v1.0********************************************
+ * UART0(PA0,PA1)
+ * UART1(PA10,PA11)
+ * UART2(PA22,PA23)
+ * UART3(PA26,PA27)
+ * IIS(PA24,PA25,PA26,PA27)
+ * SPI1(PA16,PA17,PA18)
+ * IIC0(PA4,PA5)
+ ******************************************************************************/
+#define GPIO0_REUSE_EN                (GPIO_SET_BIT0|GPIO_SET_BIT1|GPIO_SET_BIT4|GPIO_SET_BIT5|GPIO_SET_BIT6|GPIO_SET_BIT9|GPIO_SET_BIT10|GPIO_SET_BIT11|GPIO_SET_BIT16|GPIO_SET_BIT17|GPIO_SET_BIT18|GPIO_SET_BIT22|GPIO_SET_BIT23|GPIO_SET_BIT26|GPIO_SET_BIT27)
+#define GPIO1_REUSE_EN                (GPIO_SET_BIT0)
+#define IOMUX0L_FUNCTION_SEL          (PA0_UART0_TX|PA1_UART0_RX|PA4_I2C0_SCL|PA5_I2C0_SDA|PA6_ETB_TRIG0|PA9_PWM_CH0|PA10_UART1_TX|PA11_UART1_RX)
+#define IOMUX0H_FUNCTION_SEL          (PA16_SPI1_CLK|PA17_SPI1_TX|PA18_SPI1_RX|PA22_UART2_RX|PA23_UART2_TX|PA26_UART3_TX|PA27_UART3_RX)
+#define IOMUX1L_FUNCTION_SEL          (PB0_ADC0)
+
+#define PWM_GPIO0_REUSE_EN          (GPIO0_REUSE_EN|GPIO_SET_BIT0|GPIO_SET_BIT1|GPIO_SET_BIT2|GPIO_SET_BIT12|GPIO_SET_BIT13|GPIO_SET_BIT14)
+#define PWM_IOMUX0L_FUNCTION_SEL    (IOMUX0L_FUNCTION_SEL|PA0_PWM_CH0|PA1_PWM_CH1|PA2_PWM_CH2|PA12_PWM_CH3|PA13_PWM_CH4|PA14_PWM_CH5)
+
+#endif /* PHOBOS_PINMUX_H */
diff --git a/bsp/ck802/drivers/soc.h b/bsp/ck802/drivers/soc.h
new file mode 100644
index 0000000000..7a3b80cf79
--- /dev/null
+++ b/bsp/ck802/drivers/soc.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**************************************************************************//**
+ * @file     soc.h
+ * @brief    CSI Core Peripheral Access Layer Header File for
+ *           CSKYSOC Device Series
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef SOC_H
+#define SOC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define  SYSTEM_CLOCK    (20000000)
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+    /* ----------------------  CSKYCK801 Specific Interrupt Numbers  --------------------- */
+    GPIOA_IRQn                      =   0,
+    CORET_IRQn                      =   1,      /* core Timer Interrupt */
+    TIMA0_IRQn                      =   2,      /* timerA0 Interrupt */
+    TIMA1_IRQn                      =   3,      /* timerA1 Interrupt */
+    WDT_IRQn                        =   5,      /* wdt Interrupt */
+    UART0_IRQn                      =   6,      /* uart0 Interrupt */
+    UART1_IRQn                      =   7,      /* uart1 Interrupt */
+    UART2_IRQn                      =   8,      /* uart2 Interrupt */
+    I2C0_IRQn                       =   9,      /* i2c0 Interrupt */
+    I2C1_IRQn                       =   10,     /* i2c1 Interrupt */
+    SPI1_IRQn                       =   11,     /* spi0 Interrupt */
+    SPI0_IRQn                       =   12,     /* spi1 Interrupt */
+    RTC_IRQn                        =   13,     /* rtc Interrupt */
+    EXTWAK_IRQn                     =   14,     /* extwakeup Interrupt */
+    DMAC_IRQn                       =   17,     /* dmac Interrupt */
+    PMU_IRQn                        =   18,     /* pmu Interrupt */
+    PWM_IRQn                        =   19,     /* pwm Interrupt */
+    UART3_IRQn                      =   21,     /* uart3 Interrupt */
+    TIMB0_IRQn                      =   23,     /* timerB0 Interrupt */
+    TIMB1_IRQn                      =   24,     /* timerB1 Interrupt */
+    GPIOB_IRQn                      =   27,     /* GPIOB Interrupt */
+    AES_IRQn                        =   26,     /* aes Interrupt */
+    RSA_IRQn                        =   28,     /* rsa Interrupt */
+    SHA_IRQn                        =   29,     /* sha Interrupt */
+
+}
+IRQn_Type;
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* --------  Configuration of the CK801 Processor and Core Peripherals  ------- */
+#define __CK802_REV               0x0000U   /* Core revision r0p0 */
+#define __MGU_PRESENT             0         /* MGU present or not */
+#define __NVIC_PRIO_BITS          2         /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used */
+
+#include "core_ck802.h"                     /* Processor and core peripherals */
+#include "stdint.h"
+
+typedef enum
+{
+    CKENUM_DMA_UART0_RX,
+    CKENUM_DMA_UART0_TX,
+    CKENUM_DMA_UART1_RX,
+    CKENUM_DMA_UART1_TX,
+    CKENUM_DMA_ADC_RX,
+    CKENUM_DMA_ADC_TX,
+    CKENUM_DMA_SPI1_RX,
+    CKENUM_DMA_SPI1_TX,
+    CKENUM_DMA_SPI0_RX,
+    CKENUM_DMA_SPI0_TX,
+    CKENUM_DMA_IIC_RX,
+    CKENUM_DMA_IIC_TX,
+    CKENUM_DMA_IIC1_RX,
+    CKENUM_DMA_IIC1_TX,
+    CKENUM_DMA_IIS_RX,
+    CKENUM_DMA_IIS_TX,
+    CKENUM_DMA_MEMORY
+} ckenum_dma_device_e;
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+#if 0
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t RBR;           /* Offset: 0x000 (R/ )  Receive buffer register */
+        __OM uint32_t THR;           /* Offset: 0x000 ( /W)  Transmission hold register */
+        __IOM uint32_t DLL;          /* Offset: 0x000 (R/W)  Clock frequency division low section register */
+    };
+    union
+    {
+        __IOM uint32_t DLH;          /* Offset: 0x004 (R/W)  Clock frequency division high section register */
+        __IOM uint32_t IER;          /* Offset: 0x004 (R/W)  Interrupt enable register */
+    };
+    __IM uint32_t IIR;             /* Offset: 0x008 (R/ )  Interrupt indicia register */
+    __IOM uint32_t LCR;            /* Offset: 0x00C (R/W)  Transmission control register */
+    __IOM uint32_t MCR;            /* Offset: 0x010 (R/W)  Modem control register */
+    __IM uint32_t LSR;             /* Offset: 0x014 (R/ )  Transmission state register */
+    __IM uint32_t MSR;             /* Offset: 0x018 (R/ )  Modem state register */
+    uint32_t RESERVED1[24];
+    __IM uint32_t USR;             /* Offset: 0x07c (R/ )  UART state register */
+} CSKY_UART_TypeDef;
+
+/* ================================================================================ */
+/* ==============            Inter-Integrated Circuit (IIC)           ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t IC_CON;                    /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IOM uint32_t IC_TAR;                    /* Offset: 0x004 (R/W)  Transmission hold register */
+    __IOM uint32_t IC_SAR;                    /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    __IOM uint32_t IC_HS_MADDR;               /* Offset: 0x00c (R/W)  Clock frequency division high section register */
+    __IOM uint32_t IC_DATA_CMD;               /* Offset: 0x010 (R/W)  Interrupt enable register */
+    __IOM uint32_t IC_SS_SCL_HCNT;            /* Offset: 0x014 (R/W)  Interrupt indicia register */
+    __IOM uint32_t IC_SS_SCL_LCNT;            /* Offset: 0x018 (R/W)  Transmission control register */
+    __IOM uint32_t IC_FS_SCL_HCNT;            /* Offset: 0x01c (R/W)  Modem control register */
+    __IOM uint32_t IC_FS_SCL_LCNT;            /* Offset: 0x020 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_HCNT;            /* Offset: 0x024 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_LCNT;            /* Offset: 0x028 (R/W)  Transmission state register */
+    __IOM uint32_t IC_INTR_STAT;              /* Offset: 0x02c (R)  Transmission state register */
+    __IOM uint32_t IC_INTR_MASK;              /* Offset: 0x030 (R/W)  Transmission state register */
+    __IOM uint32_t IC_RAW_INTR_STAT;          /* Offset: 0x034 (R)  Transmission state register */
+    __IOM uint32_t IC_RX_TL;                  /* Offset: 0x038 (R/W)  Transmission state register */
+    __IOM uint32_t IC_TX_TL;                  /* Offset: 0x03c (R/W)  Transmission state register */
+    __IOM uint32_t IC_CLR_INTR;               /* Offset: 0x040 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_UNDER;           /* Offset: 0x044 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_OVER;            /* Offset: 0x048 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_OVER;            /* Offset: 0x04c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RD_REQ;             /* Offset: 0x050 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_ABRT;            /* Offset: 0x054 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_DONE;            /* Offset: 0x058 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_ACTIVITY;           /* Offset: 0x05c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_STOP_DET;           /* Offset: 0x060 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_START_DET;          /* Offset: 0x064 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_GEN_CALL;           /* Offset: 0x068 (R)  Transmission state register */
+    __IOM uint32_t IC_ENABLE;                 /* Offset: 0x06c (R/W)  Transmission state register */
+    __IOM uint32_t IC_STATUS;                 /* Offset: 0x070 (R)  Transmission state register */
+    __IOM uint32_t IC_TXFLR;                  /* Offset: 0x074 (R)  Transmission state register */
+    __IOM uint32_t IC_RXFLR;                  /* Offset: 0x078 (R)  Transmission state register */
+    uint32_t RESERVED;                        /* Offset: 0x014 (R/ )  Transmission state register */
+    __IOM uint32_t IC_TX_ABRT_SOURCE;         /* Offset: 0x080 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR1;                   /* Offset: 0x084 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_CR;                 /* Offset: 0x088 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_TDLR;               /* Offset: 0x08c (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_RDLR;               /* Offset: 0x090 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR2;                   /* Offset: 0x094 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR3;                   /* Offset: 0x098 (R/W)  Transmission state register */
+    __IOM uint32_t IC_MULTI_SLAVE;            /* Offset: 0x09c (R/W)  Transmission state register */
+    __IOM uint32_t IC_GEN_CALL_EN;            /* Offset: 0x0a0 (R/W)  Transmission state register */
+
+} CSKY_IIC_TypeDef;
+
+/* ================================================================================ */
+/* ==============                          TIMER                      ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t TxLoadCount;               /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IOM uint32_t TxCurrentValue;            /* Offset: 0x004 (R)  Transmission hold register */
+    __IOM uint32_t TxControl;                 /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    __IOM uint32_t TxEOI;                     /* Offset: 0x00c (R)  Clock frequency division high section register */
+    __IOM uint32_t TxIntStatus;               /* Offset: 0x010 (R)  Interrupt enable register */
+
+} CSKY_TIMER_TypeDef;
+
+/* ================================================================================ */
+/* ==============                    TIMER  Control                   ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t TimersIntStatus;            /* Offset: 0x000 (R)  Interrupt indicia register */
+    __IOM uint32_t TimerEOI;                   /* Offset: 0x004 (R)  Transmission control register */
+    __IOM uint32_t TimerRawIntStatus;          /* Offset: 0x008 (R)  Modem control register */
+
+} CSKY_TIMER_Control_TypeDef;
+
+/* ================================================================================ */
+/* ==============                        GPIO                         ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t SWPORT_DR;                 /* Offset: 0x000 (R/W)  Interrupt indicia register */
+    __IOM uint32_t SWPORT_DDR;                /* Offset: 0x004 (R/W)  Interrupt indicia register */
+    __IOM uint32_t PORT_CTL;                  /* Offset: 0x008 (R/W)  Interrupt indicia register */
+} CKStruct_GPIO, *PCKStruct_GPIO;
+
+typedef struct
+{
+    __IOM uint32_t SHA_CON;                     /* Offset: 0x000 (R/W)  Control register */
+    __IOM uint32_t SHA_INTSTATE;                /* Offset: 0x004 (R/W)  Instatus register */
+    __IOM uint32_t SHA_H0L;                     /* Offset: 0x008 (R/W)  H0L register */
+    __IOM uint32_t SHA_H1L;                     /* Offset: 0x00c (R/W)  H1L register */
+    __IOM uint32_t SHA_H2L;                     /* Offset: 0x010 (R/W)  H2L register */
+    __IOM uint32_t SHA_H3L;                     /* Offset: 0x014 (R/W)  H3L register */
+    __IOM uint32_t SHA_H4L;                     /* Offset: 0x018 (R/W)  H4L register */
+    __IOM uint32_t SHA_H5L;                     /* Offset: 0x01c (R/W)  H5L register */
+    __IOM uint32_t SHA_H6L;                     /* Offset: 0x020 (R/W)  H6L register */
+    __IOM uint32_t SHA_H7L;                     /* Offset: 0x024 (R/W)  H7L register */
+    __IOM uint32_t SHA_H0H;                     /* Offset: 0x028 (R/W)  H0H register */
+    __IOM uint32_t SHA_H1H;                     /* Offset: 0x02c (R/W)  H1H register */
+    __IOM uint32_t SHA_H2H;                     /* Offset: 0x030 (R/W)  H2H register */
+    __IOM uint32_t SHA_H3H;                     /* Offset: 0x034 (R/W)  H3H register */
+    __IOM uint32_t SHA_H4H;                     /* Offset: 0x038 (R/W)  H4H register */
+    __IOM uint32_t SHA_H5H;                     /* Offset: 0x03c (R/W)  H5H register */
+    __IOM uint32_t SHA_H6H;                     /* Offset: 0x040 (R/W)  H6H register */
+    __IOM uint32_t SHA_H7H;                     /* Offset: 0x044 (R/W)  H7H register */
+    __IOM uint32_t SHA_DATA1;                   /* Offset: 0x048 (R/W)  DATA1 register */
+    uint32_t REV[15];
+    __IOM uint32_t SHA_DATA2;                   /* Offset: 0x088 (R/W)  DATA2 register */
+} CSKY_SHA_TypeDef;
+
+#endif
+
+#define CONFIG_CRC_NUM  1
+#define CONFIG_IIC_NUM  2
+#define CONFIG_TRNG_NUM 1
+#define CONFIG_EFLASH_NUM 1
+#define CONFIG_AES_NUM  1
+#define CONFIG_RSA_NUM  1
+#define CONFIG_SHA_NUM  1
+#define CONFIG_SPI_NUM  2
+#define CONFIG_PWM_NUM  1
+#define CONFIG_TIMER_NUM 4
+#define CONFIG_RTC_NUM 1
+#define CONFIG_WDT_NUM 1
+#define CONFIG_DMAC_NUM 1
+#define CONFIG_ETH_NUM 2
+
+#define CSKY_I2C0_BASE             (0x50014000UL)
+#define CSKY_I2C1_BASE             (0x60014000UL)
+
+#define CONFIG_USART_NUM 4
+#define CSKY_UART0_BASE            (0x50010000UL)
+#define CSKY_UART1_BASE            (0x50010400UL)
+#define CSKY_UART2_BASE            (0x60010000UL)
+#define CSKY_UART3_BASE            (0x60010400UL)
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+/* --------------------------  CPU FPGA memory map  ------------------------------- */
+#define CSKY_EFLASH_BASE           (0x10000000UL)
+#define CSKY_SRAM_BASE             (0x20000000UL)
+
+#define CSKY_PMU_BASE              (0x40000000UL)
+#define CSKY_DMA_BASE              (0x40001000UL)
+#define CSKY_EFLASH_CONTROL_BASE   (0x40005000UL)
+#define CSKY_OTP_BASE              (0x40006000UL)
+#define CSKY_SRAM_CONTROL_BASE     (0x40009000UL)
+#define CSKY_AES_BASE              (0x4000d000UL)
+#define CSKY_SHA_BASE              (0x4000e000UL)
+#define CSKY_RSA_BASE              (0x4000f000UL)
+#define CSKY_CRC_BASE              (0x40010000UL)
+#define CSKY_TRNG_BASE             (0x40015000UL)
+#define CSKY_TIMERA0_BASE          (0x50000000UL)
+#define CSKY_TIMERA1_BASE          (0x50000014UL)
+#define CSKY_TIMERA_CONTROL_BASE   (0x500000a0UL)
+#define CSKY_RTC_BASE              (0x50004000UL)
+#define CSKY_WDT_BASE              (0x50008000UL)
+#define CSKY_SPI0_BASE             (0x5000c000UL)
+
+#define CONFIG_GPIO_NUM            2
+#define CONFIG_GPIO_PIN_NUM        43
+#define CSKY_GPIOA_BASE            (0x50018000UL)
+#define CSKY_GPIOA_CONTROL_BASE    (0x50018030UL)
+#define CSKY_PWM_BASE              (0x5001c000UL)
+#define CSKY_ADC_BASE              (0x50020000UL)
+#define CSKY_I2S0_BASE             (0x50030000UL)
+#define CSKY_TIMERB0_BASE          (0x60000000UL)
+#define CSKY_TIMERB1_BASE          (0x60000014UL)
+#define CSKY_SPI1_BASE             (0x6000c000UL)
+
+#define CSKY_GPIOB_BASE            (0x60018000UL)
+#define CSKY_GPIOB_CONTROL_BASE    (0x60018030UL)
+#define CSKY_TIMERB_CONTROL_BASE   (0x600000a0UL)
+#define CSKY_SIPC_BASE             (0x6001c000UL)
+#define CSKY_I2S1_BASE             (0x60020000UL)
+#define CSKY_ETB_BASE              (0x60024000UL)
+#define CSKY_USI_BASE              (0x60028000UL)
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+#define CSKY_UART1                 ((   CSKY_UART_TypeDef *)    CSKY_UART1_BASE)
+#define CSKY_SHA                   ((   CSKY_SHA_TypeDef *)     CSKY_SHA_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SOC_H */
diff --git a/bsp/ck802/drivers/system.c b/bsp/ck802/drivers/system.c
new file mode 100644
index 0000000000..772a8dab5e
--- /dev/null
+++ b/bsp/ck802/drivers/system.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     system_PHOBOS.c
+ * @brief    CSI Device System Source File for PHOBOS
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#include "soc.h"
+#include "csi_core.h"
+#include "config.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+int SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency      */
+
+extern int __Vectors;
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/**
+  * @brief  initialize the system
+  *         Initialize the psr and vbr.
+  * @param  None
+  * @return None
+  */
+void SystemInit(void)
+{
+    /* Here we may setting exception vector, MGU, cache, and so on. */
+#ifdef CONFIG_SYSTEM_SECURE
+    __set_PSR(0xc0000140);
+#else
+    __set_PSR(0x80000140);
+#endif
+    __set_VBR((uint32_t) & (__Vectors));
+
+    drv_coret_config(200 * 1000, CORET_IRQn);    //10ms
+    drv_nvic_enable_irq(CORET_IRQn);
+
+    SystemCoreClock = SYSTEM_CLOCK;
+}